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Always make all PowerPC exception definitions visible.
[qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26 #include "dis-asm.h"
27 #include "host-utils.h"
28
29 //#define PPC_DUMP_CPU
30 //#define PPC_DEBUG_SPR
31 //#define PPC_DEBUG_IRQ
32
33 struct ppc_def_t {
34 const unsigned char *name;
35 uint32_t pvr;
36 uint64_t insns_flags;
37 uint64_t msr_mask;
38 uint8_t mmu_model;
39 uint8_t excp_model;
40 uint8_t bus_model;
41 uint8_t pad;
42 uint32_t flags;
43 int bfd_mach;
44 void (*init_proc)(CPUPPCState *env);
45 int (*check_pow)(CPUPPCState *env);
46 };
47
48 /* For user-mode emulation, we don't emulate any IRQ controller */
49 #if defined(CONFIG_USER_ONLY)
50 #define PPC_IRQ_INIT_FN(name) \
51 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
52 { \
53 }
54 #else
55 #define PPC_IRQ_INIT_FN(name) \
56 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
57 #endif
58
59 PPC_IRQ_INIT_FN(40x);
60 PPC_IRQ_INIT_FN(6xx);
61 PPC_IRQ_INIT_FN(970);
62
63 /* Generic callbacks:
64 * do nothing but store/retrieve spr value
65 */
66 #ifdef PPC_DUMP_SPR_ACCESSES
67 static void spr_read_generic (void *opaque, int sprn)
68 {
69 gen_op_load_dump_spr(sprn);
70 }
71
72 static void spr_write_generic (void *opaque, int sprn)
73 {
74 gen_op_store_dump_spr(sprn);
75 }
76 #else
77 static void spr_read_generic (void *opaque, int sprn)
78 {
79 gen_op_load_spr(sprn);
80 }
81
82 static void spr_write_generic (void *opaque, int sprn)
83 {
84 gen_op_store_spr(sprn);
85 }
86 #endif
87
88 #if !defined(CONFIG_USER_ONLY)
89 static void spr_write_clear (void *opaque, int sprn)
90 {
91 gen_op_mask_spr(sprn);
92 }
93 #endif
94
95 /* SPR common to all PowerPC */
96 /* XER */
97 static void spr_read_xer (void *opaque, int sprn)
98 {
99 gen_op_load_xer();
100 }
101
102 static void spr_write_xer (void *opaque, int sprn)
103 {
104 gen_op_store_xer();
105 }
106
107 /* LR */
108 static void spr_read_lr (void *opaque, int sprn)
109 {
110 gen_op_load_lr();
111 }
112
113 static void spr_write_lr (void *opaque, int sprn)
114 {
115 gen_op_store_lr();
116 }
117
118 /* CTR */
119 static void spr_read_ctr (void *opaque, int sprn)
120 {
121 gen_op_load_ctr();
122 }
123
124 static void spr_write_ctr (void *opaque, int sprn)
125 {
126 gen_op_store_ctr();
127 }
128
129 /* User read access to SPR */
130 /* USPRx */
131 /* UMMCRx */
132 /* UPMCx */
133 /* USIA */
134 /* UDECR */
135 static void spr_read_ureg (void *opaque, int sprn)
136 {
137 gen_op_load_spr(sprn + 0x10);
138 }
139
140 /* SPR common to all non-embedded PowerPC */
141 /* DECR */
142 #if !defined(CONFIG_USER_ONLY)
143 static void spr_read_decr (void *opaque, int sprn)
144 {
145 gen_op_load_decr();
146 }
147
148 static void spr_write_decr (void *opaque, int sprn)
149 {
150 gen_op_store_decr();
151 }
152 #endif
153
154 /* SPR common to all non-embedded PowerPC, except 601 */
155 /* Time base */
156 static void spr_read_tbl (void *opaque, int sprn)
157 {
158 gen_op_load_tbl();
159 }
160
161 static void spr_read_tbu (void *opaque, int sprn)
162 {
163 gen_op_load_tbu();
164 }
165
166 __attribute__ (( unused ))
167 static void spr_read_atbl (void *opaque, int sprn)
168 {
169 gen_op_load_atbl();
170 }
171
172 __attribute__ (( unused ))
173 static void spr_read_atbu (void *opaque, int sprn)
174 {
175 gen_op_load_atbu();
176 }
177
178 #if !defined(CONFIG_USER_ONLY)
179 static void spr_write_tbl (void *opaque, int sprn)
180 {
181 gen_op_store_tbl();
182 }
183
184 static void spr_write_tbu (void *opaque, int sprn)
185 {
186 gen_op_store_tbu();
187 }
188
189 __attribute__ (( unused ))
190 static void spr_write_atbl (void *opaque, int sprn)
191 {
192 gen_op_store_atbl();
193 }
194
195 __attribute__ (( unused ))
196 static void spr_write_atbu (void *opaque, int sprn)
197 {
198 gen_op_store_atbu();
199 }
200 #endif
201
202 #if !defined(CONFIG_USER_ONLY)
203 /* IBAT0U...IBAT0U */
204 /* IBAT0L...IBAT7L */
205 static void spr_read_ibat (void *opaque, int sprn)
206 {
207 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
208 }
209
210 static void spr_read_ibat_h (void *opaque, int sprn)
211 {
212 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
213 }
214
215 static void spr_write_ibatu (void *opaque, int sprn)
216 {
217 gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
218 }
219
220 static void spr_write_ibatu_h (void *opaque, int sprn)
221 {
222 gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
223 }
224
225 static void spr_write_ibatl (void *opaque, int sprn)
226 {
227 gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
228 }
229
230 static void spr_write_ibatl_h (void *opaque, int sprn)
231 {
232 gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
233 }
234
235 /* DBAT0U...DBAT7U */
236 /* DBAT0L...DBAT7L */
237 static void spr_read_dbat (void *opaque, int sprn)
238 {
239 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
240 }
241
242 static void spr_read_dbat_h (void *opaque, int sprn)
243 {
244 gen_op_load_dbat(sprn & 1, ((sprn - SPR_DBAT4U) / 2) + 4);
245 }
246
247 static void spr_write_dbatu (void *opaque, int sprn)
248 {
249 gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
250 }
251
252 static void spr_write_dbatu_h (void *opaque, int sprn)
253 {
254 gen_op_store_dbatu(((sprn - SPR_DBAT4U) / 2) + 4);
255 }
256
257 static void spr_write_dbatl (void *opaque, int sprn)
258 {
259 gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
260 }
261
262 static void spr_write_dbatl_h (void *opaque, int sprn)
263 {
264 gen_op_store_dbatl(((sprn - SPR_DBAT4L) / 2) + 4);
265 }
266
267 /* SDR1 */
268 static void spr_read_sdr1 (void *opaque, int sprn)
269 {
270 gen_op_load_sdr1();
271 }
272
273 static void spr_write_sdr1 (void *opaque, int sprn)
274 {
275 gen_op_store_sdr1();
276 }
277
278 /* 64 bits PowerPC specific SPRs */
279 /* ASR */
280 #if defined(TARGET_PPC64)
281 __attribute__ (( unused ))
282 static void spr_read_asr (void *opaque, int sprn)
283 {
284 gen_op_load_asr();
285 }
286
287 __attribute__ (( unused ))
288 static void spr_write_asr (void *opaque, int sprn)
289 {
290 gen_op_store_asr();
291 }
292 #endif
293 #endif
294
295 /* PowerPC 601 specific registers */
296 /* RTC */
297 static void spr_read_601_rtcl (void *opaque, int sprn)
298 {
299 gen_op_load_601_rtcl();
300 }
301
302 static void spr_read_601_rtcu (void *opaque, int sprn)
303 {
304 gen_op_load_601_rtcu();
305 }
306
307 #if !defined(CONFIG_USER_ONLY)
308 static void spr_write_601_rtcu (void *opaque, int sprn)
309 {
310 gen_op_store_601_rtcu();
311 }
312
313 static void spr_write_601_rtcl (void *opaque, int sprn)
314 {
315 gen_op_store_601_rtcl();
316 }
317
318 static void spr_write_hid0_601 (void *opaque, int sprn)
319 {
320 DisasContext *ctx = opaque;
321
322 gen_op_store_hid0_601();
323 /* Must stop the translation as endianness may have changed */
324 GEN_STOP(ctx);
325 }
326 #endif
327
328 /* Unified bats */
329 #if !defined(CONFIG_USER_ONLY)
330 static void spr_read_601_ubat (void *opaque, int sprn)
331 {
332 gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
333 }
334
335 static void spr_write_601_ubatu (void *opaque, int sprn)
336 {
337 gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
338 }
339
340 static void spr_write_601_ubatl (void *opaque, int sprn)
341 {
342 gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
343 }
344 #endif
345
346 /* PowerPC 40x specific registers */
347 #if !defined(CONFIG_USER_ONLY)
348 static void spr_read_40x_pit (void *opaque, int sprn)
349 {
350 gen_op_load_40x_pit();
351 }
352
353 static void spr_write_40x_pit (void *opaque, int sprn)
354 {
355 gen_op_store_40x_pit();
356 }
357
358 static void spr_write_40x_dbcr0 (void *opaque, int sprn)
359 {
360 DisasContext *ctx = opaque;
361
362 gen_op_store_40x_dbcr0();
363 /* We must stop translation as we may have rebooted */
364 GEN_STOP(ctx);
365 }
366
367 static void spr_write_40x_sler (void *opaque, int sprn)
368 {
369 gen_op_store_40x_sler();
370 }
371
372 static void spr_write_booke_tcr (void *opaque, int sprn)
373 {
374 gen_op_store_booke_tcr();
375 }
376
377 static void spr_write_booke_tsr (void *opaque, int sprn)
378 {
379 gen_op_store_booke_tsr();
380 }
381 #endif
382
383 /* PowerPC 403 specific registers */
384 /* PBL1 / PBU1 / PBL2 / PBU2 */
385 #if !defined(CONFIG_USER_ONLY)
386 static void spr_read_403_pbr (void *opaque, int sprn)
387 {
388 gen_op_load_403_pb(sprn - SPR_403_PBL1);
389 }
390
391 static void spr_write_403_pbr (void *opaque, int sprn)
392 {
393 gen_op_store_403_pb(sprn - SPR_403_PBL1);
394 }
395
396 static void spr_write_pir (void *opaque, int sprn)
397 {
398 gen_op_store_pir();
399 }
400 #endif
401
402 #if !defined(CONFIG_USER_ONLY)
403 /* Callback used to write the exception vector base */
404 static void spr_write_excp_prefix (void *opaque, int sprn)
405 {
406 gen_op_store_excp_prefix();
407 gen_op_store_spr(sprn);
408 }
409
410 static void spr_write_excp_vector (void *opaque, int sprn)
411 {
412 DisasContext *ctx = opaque;
413
414 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
415 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR0);
416 gen_op_store_spr(sprn);
417 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
418 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR32 + 32);
419 gen_op_store_spr(sprn);
420 } else {
421 printf("Trying to write an unknown exception vector %d %03x\n",
422 sprn, sprn);
423 GEN_EXCP_PRIVREG(ctx);
424 }
425 }
426 #endif
427
428 #if defined(CONFIG_USER_ONLY)
429 #define spr_register(env, num, name, uea_read, uea_write, \
430 oea_read, oea_write, initial_value) \
431 do { \
432 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
433 } while (0)
434 static inline void _spr_register (CPUPPCState *env, int num,
435 const unsigned char *name,
436 void (*uea_read)(void *opaque, int sprn),
437 void (*uea_write)(void *opaque, int sprn),
438 target_ulong initial_value)
439 #else
440 static inline void spr_register (CPUPPCState *env, int num,
441 const unsigned char *name,
442 void (*uea_read)(void *opaque, int sprn),
443 void (*uea_write)(void *opaque, int sprn),
444 void (*oea_read)(void *opaque, int sprn),
445 void (*oea_write)(void *opaque, int sprn),
446 target_ulong initial_value)
447 #endif
448 {
449 ppc_spr_t *spr;
450
451 spr = &env->spr_cb[num];
452 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
453 #if !defined(CONFIG_USER_ONLY)
454 spr->oea_read != NULL || spr->oea_write != NULL ||
455 #endif
456 spr->uea_read != NULL || spr->uea_write != NULL) {
457 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
458 exit(1);
459 }
460 #if defined(PPC_DEBUG_SPR)
461 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
462 initial_value);
463 #endif
464 spr->name = name;
465 spr->uea_read = uea_read;
466 spr->uea_write = uea_write;
467 #if !defined(CONFIG_USER_ONLY)
468 spr->oea_read = oea_read;
469 spr->oea_write = oea_write;
470 #endif
471 env->spr[num] = initial_value;
472 }
473
474 /* Generic PowerPC SPRs */
475 static void gen_spr_generic (CPUPPCState *env)
476 {
477 /* Integer processing */
478 spr_register(env, SPR_XER, "XER",
479 &spr_read_xer, &spr_write_xer,
480 &spr_read_xer, &spr_write_xer,
481 0x00000000);
482 /* Branch contol */
483 spr_register(env, SPR_LR, "LR",
484 &spr_read_lr, &spr_write_lr,
485 &spr_read_lr, &spr_write_lr,
486 0x00000000);
487 spr_register(env, SPR_CTR, "CTR",
488 &spr_read_ctr, &spr_write_ctr,
489 &spr_read_ctr, &spr_write_ctr,
490 0x00000000);
491 /* Interrupt processing */
492 spr_register(env, SPR_SRR0, "SRR0",
493 SPR_NOACCESS, SPR_NOACCESS,
494 &spr_read_generic, &spr_write_generic,
495 0x00000000);
496 spr_register(env, SPR_SRR1, "SRR1",
497 SPR_NOACCESS, SPR_NOACCESS,
498 &spr_read_generic, &spr_write_generic,
499 0x00000000);
500 /* Processor control */
501 spr_register(env, SPR_SPRG0, "SPRG0",
502 SPR_NOACCESS, SPR_NOACCESS,
503 &spr_read_generic, &spr_write_generic,
504 0x00000000);
505 spr_register(env, SPR_SPRG1, "SPRG1",
506 SPR_NOACCESS, SPR_NOACCESS,
507 &spr_read_generic, &spr_write_generic,
508 0x00000000);
509 spr_register(env, SPR_SPRG2, "SPRG2",
510 SPR_NOACCESS, SPR_NOACCESS,
511 &spr_read_generic, &spr_write_generic,
512 0x00000000);
513 spr_register(env, SPR_SPRG3, "SPRG3",
514 SPR_NOACCESS, SPR_NOACCESS,
515 &spr_read_generic, &spr_write_generic,
516 0x00000000);
517 }
518
519 /* SPR common to all non-embedded PowerPC, including 601 */
520 static void gen_spr_ne_601 (CPUPPCState *env)
521 {
522 /* Exception processing */
523 spr_register(env, SPR_DSISR, "DSISR",
524 SPR_NOACCESS, SPR_NOACCESS,
525 &spr_read_generic, &spr_write_generic,
526 0x00000000);
527 spr_register(env, SPR_DAR, "DAR",
528 SPR_NOACCESS, SPR_NOACCESS,
529 &spr_read_generic, &spr_write_generic,
530 0x00000000);
531 /* Timer */
532 spr_register(env, SPR_DECR, "DECR",
533 SPR_NOACCESS, SPR_NOACCESS,
534 &spr_read_decr, &spr_write_decr,
535 0x00000000);
536 /* Memory management */
537 spr_register(env, SPR_SDR1, "SDR1",
538 SPR_NOACCESS, SPR_NOACCESS,
539 &spr_read_sdr1, &spr_write_sdr1,
540 0x00000000);
541 }
542
543 /* BATs 0-3 */
544 static void gen_low_BATs (CPUPPCState *env)
545 {
546 #if !defined(CONFIG_USER_ONLY)
547 spr_register(env, SPR_IBAT0U, "IBAT0U",
548 SPR_NOACCESS, SPR_NOACCESS,
549 &spr_read_ibat, &spr_write_ibatu,
550 0x00000000);
551 spr_register(env, SPR_IBAT0L, "IBAT0L",
552 SPR_NOACCESS, SPR_NOACCESS,
553 &spr_read_ibat, &spr_write_ibatl,
554 0x00000000);
555 spr_register(env, SPR_IBAT1U, "IBAT1U",
556 SPR_NOACCESS, SPR_NOACCESS,
557 &spr_read_ibat, &spr_write_ibatu,
558 0x00000000);
559 spr_register(env, SPR_IBAT1L, "IBAT1L",
560 SPR_NOACCESS, SPR_NOACCESS,
561 &spr_read_ibat, &spr_write_ibatl,
562 0x00000000);
563 spr_register(env, SPR_IBAT2U, "IBAT2U",
564 SPR_NOACCESS, SPR_NOACCESS,
565 &spr_read_ibat, &spr_write_ibatu,
566 0x00000000);
567 spr_register(env, SPR_IBAT2L, "IBAT2L",
568 SPR_NOACCESS, SPR_NOACCESS,
569 &spr_read_ibat, &spr_write_ibatl,
570 0x00000000);
571 spr_register(env, SPR_IBAT3U, "IBAT3U",
572 SPR_NOACCESS, SPR_NOACCESS,
573 &spr_read_ibat, &spr_write_ibatu,
574 0x00000000);
575 spr_register(env, SPR_IBAT3L, "IBAT3L",
576 SPR_NOACCESS, SPR_NOACCESS,
577 &spr_read_ibat, &spr_write_ibatl,
578 0x00000000);
579 spr_register(env, SPR_DBAT0U, "DBAT0U",
580 SPR_NOACCESS, SPR_NOACCESS,
581 &spr_read_dbat, &spr_write_dbatu,
582 0x00000000);
583 spr_register(env, SPR_DBAT0L, "DBAT0L",
584 SPR_NOACCESS, SPR_NOACCESS,
585 &spr_read_dbat, &spr_write_dbatl,
586 0x00000000);
587 spr_register(env, SPR_DBAT1U, "DBAT1U",
588 SPR_NOACCESS, SPR_NOACCESS,
589 &spr_read_dbat, &spr_write_dbatu,
590 0x00000000);
591 spr_register(env, SPR_DBAT1L, "DBAT1L",
592 SPR_NOACCESS, SPR_NOACCESS,
593 &spr_read_dbat, &spr_write_dbatl,
594 0x00000000);
595 spr_register(env, SPR_DBAT2U, "DBAT2U",
596 SPR_NOACCESS, SPR_NOACCESS,
597 &spr_read_dbat, &spr_write_dbatu,
598 0x00000000);
599 spr_register(env, SPR_DBAT2L, "DBAT2L",
600 SPR_NOACCESS, SPR_NOACCESS,
601 &spr_read_dbat, &spr_write_dbatl,
602 0x00000000);
603 spr_register(env, SPR_DBAT3U, "DBAT3U",
604 SPR_NOACCESS, SPR_NOACCESS,
605 &spr_read_dbat, &spr_write_dbatu,
606 0x00000000);
607 spr_register(env, SPR_DBAT3L, "DBAT3L",
608 SPR_NOACCESS, SPR_NOACCESS,
609 &spr_read_dbat, &spr_write_dbatl,
610 0x00000000);
611 env->nb_BATs += 4;
612 #endif
613 }
614
615 /* BATs 4-7 */
616 static void gen_high_BATs (CPUPPCState *env)
617 {
618 #if !defined(CONFIG_USER_ONLY)
619 spr_register(env, SPR_IBAT4U, "IBAT4U",
620 SPR_NOACCESS, SPR_NOACCESS,
621 &spr_read_ibat_h, &spr_write_ibatu_h,
622 0x00000000);
623 spr_register(env, SPR_IBAT4L, "IBAT4L",
624 SPR_NOACCESS, SPR_NOACCESS,
625 &spr_read_ibat_h, &spr_write_ibatl_h,
626 0x00000000);
627 spr_register(env, SPR_IBAT5U, "IBAT5U",
628 SPR_NOACCESS, SPR_NOACCESS,
629 &spr_read_ibat_h, &spr_write_ibatu_h,
630 0x00000000);
631 spr_register(env, SPR_IBAT5L, "IBAT5L",
632 SPR_NOACCESS, SPR_NOACCESS,
633 &spr_read_ibat_h, &spr_write_ibatl_h,
634 0x00000000);
635 spr_register(env, SPR_IBAT6U, "IBAT6U",
636 SPR_NOACCESS, SPR_NOACCESS,
637 &spr_read_ibat_h, &spr_write_ibatu_h,
638 0x00000000);
639 spr_register(env, SPR_IBAT6L, "IBAT6L",
640 SPR_NOACCESS, SPR_NOACCESS,
641 &spr_read_ibat_h, &spr_write_ibatl_h,
642 0x00000000);
643 spr_register(env, SPR_IBAT7U, "IBAT7U",
644 SPR_NOACCESS, SPR_NOACCESS,
645 &spr_read_ibat_h, &spr_write_ibatu_h,
646 0x00000000);
647 spr_register(env, SPR_IBAT7L, "IBAT7L",
648 SPR_NOACCESS, SPR_NOACCESS,
649 &spr_read_ibat_h, &spr_write_ibatl_h,
650 0x00000000);
651 spr_register(env, SPR_DBAT4U, "DBAT4U",
652 SPR_NOACCESS, SPR_NOACCESS,
653 &spr_read_dbat_h, &spr_write_dbatu_h,
654 0x00000000);
655 spr_register(env, SPR_DBAT4L, "DBAT4L",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_dbat_h, &spr_write_dbatl_h,
658 0x00000000);
659 spr_register(env, SPR_DBAT5U, "DBAT5U",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_dbat_h, &spr_write_dbatu_h,
662 0x00000000);
663 spr_register(env, SPR_DBAT5L, "DBAT5L",
664 SPR_NOACCESS, SPR_NOACCESS,
665 &spr_read_dbat_h, &spr_write_dbatl_h,
666 0x00000000);
667 spr_register(env, SPR_DBAT6U, "DBAT6U",
668 SPR_NOACCESS, SPR_NOACCESS,
669 &spr_read_dbat_h, &spr_write_dbatu_h,
670 0x00000000);
671 spr_register(env, SPR_DBAT6L, "DBAT6L",
672 SPR_NOACCESS, SPR_NOACCESS,
673 &spr_read_dbat_h, &spr_write_dbatl_h,
674 0x00000000);
675 spr_register(env, SPR_DBAT7U, "DBAT7U",
676 SPR_NOACCESS, SPR_NOACCESS,
677 &spr_read_dbat_h, &spr_write_dbatu_h,
678 0x00000000);
679 spr_register(env, SPR_DBAT7L, "DBAT7L",
680 SPR_NOACCESS, SPR_NOACCESS,
681 &spr_read_dbat_h, &spr_write_dbatl_h,
682 0x00000000);
683 env->nb_BATs += 4;
684 #endif
685 }
686
687 /* Generic PowerPC time base */
688 static void gen_tbl (CPUPPCState *env)
689 {
690 spr_register(env, SPR_VTBL, "TBL",
691 &spr_read_tbl, SPR_NOACCESS,
692 &spr_read_tbl, SPR_NOACCESS,
693 0x00000000);
694 spr_register(env, SPR_TBL, "TBL",
695 SPR_NOACCESS, SPR_NOACCESS,
696 SPR_NOACCESS, &spr_write_tbl,
697 0x00000000);
698 spr_register(env, SPR_VTBU, "TBU",
699 &spr_read_tbu, SPR_NOACCESS,
700 &spr_read_tbu, SPR_NOACCESS,
701 0x00000000);
702 spr_register(env, SPR_TBU, "TBU",
703 SPR_NOACCESS, SPR_NOACCESS,
704 SPR_NOACCESS, &spr_write_tbu,
705 0x00000000);
706 }
707
708 /* Softare table search registers */
709 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
710 {
711 #if !defined(CONFIG_USER_ONLY)
712 env->nb_tlb = nb_tlbs;
713 env->nb_ways = nb_ways;
714 env->id_tlbs = 1;
715 spr_register(env, SPR_DMISS, "DMISS",
716 SPR_NOACCESS, SPR_NOACCESS,
717 &spr_read_generic, SPR_NOACCESS,
718 0x00000000);
719 spr_register(env, SPR_DCMP, "DCMP",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_generic, SPR_NOACCESS,
722 0x00000000);
723 spr_register(env, SPR_HASH1, "HASH1",
724 SPR_NOACCESS, SPR_NOACCESS,
725 &spr_read_generic, SPR_NOACCESS,
726 0x00000000);
727 spr_register(env, SPR_HASH2, "HASH2",
728 SPR_NOACCESS, SPR_NOACCESS,
729 &spr_read_generic, SPR_NOACCESS,
730 0x00000000);
731 spr_register(env, SPR_IMISS, "IMISS",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_generic, SPR_NOACCESS,
734 0x00000000);
735 spr_register(env, SPR_ICMP, "ICMP",
736 SPR_NOACCESS, SPR_NOACCESS,
737 &spr_read_generic, SPR_NOACCESS,
738 0x00000000);
739 spr_register(env, SPR_RPA, "RPA",
740 SPR_NOACCESS, SPR_NOACCESS,
741 &spr_read_generic, &spr_write_generic,
742 0x00000000);
743 #endif
744 }
745
746 /* SPR common to MPC755 and G2 */
747 static void gen_spr_G2_755 (CPUPPCState *env)
748 {
749 /* SGPRs */
750 spr_register(env, SPR_SPRG4, "SPRG4",
751 SPR_NOACCESS, SPR_NOACCESS,
752 &spr_read_generic, &spr_write_generic,
753 0x00000000);
754 spr_register(env, SPR_SPRG5, "SPRG5",
755 SPR_NOACCESS, SPR_NOACCESS,
756 &spr_read_generic, &spr_write_generic,
757 0x00000000);
758 spr_register(env, SPR_SPRG6, "SPRG6",
759 SPR_NOACCESS, SPR_NOACCESS,
760 &spr_read_generic, &spr_write_generic,
761 0x00000000);
762 spr_register(env, SPR_SPRG7, "SPRG7",
763 SPR_NOACCESS, SPR_NOACCESS,
764 &spr_read_generic, &spr_write_generic,
765 0x00000000);
766 /* External access control */
767 /* XXX : not implemented */
768 spr_register(env, SPR_EAR, "EAR",
769 SPR_NOACCESS, SPR_NOACCESS,
770 &spr_read_generic, &spr_write_generic,
771 0x00000000);
772 }
773
774 /* SPR common to all 7xx PowerPC implementations */
775 static void gen_spr_7xx (CPUPPCState *env)
776 {
777 /* Breakpoints */
778 /* XXX : not implemented */
779 spr_register(env, SPR_DABR, "DABR",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_generic, &spr_write_generic,
782 0x00000000);
783 /* XXX : not implemented */
784 spr_register(env, SPR_IABR, "IABR",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_generic, &spr_write_generic,
787 0x00000000);
788 /* Cache management */
789 /* XXX : not implemented */
790 spr_register(env, SPR_ICTC, "ICTC",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_generic, &spr_write_generic,
793 0x00000000);
794 /* XXX : not implemented */
795 spr_register(env, SPR_L2CR, "L2CR",
796 SPR_NOACCESS, SPR_NOACCESS,
797 &spr_read_generic, &spr_write_generic,
798 0x00000000);
799 /* Performance monitors */
800 /* XXX : not implemented */
801 spr_register(env, SPR_MMCR0, "MMCR0",
802 SPR_NOACCESS, SPR_NOACCESS,
803 &spr_read_generic, &spr_write_generic,
804 0x00000000);
805 /* XXX : not implemented */
806 spr_register(env, SPR_MMCR1, "MMCR1",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_generic, &spr_write_generic,
809 0x00000000);
810 /* XXX : not implemented */
811 spr_register(env, SPR_PMC1, "PMC1",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_generic, &spr_write_generic,
814 0x00000000);
815 /* XXX : not implemented */
816 spr_register(env, SPR_PMC2, "PMC2",
817 SPR_NOACCESS, SPR_NOACCESS,
818 &spr_read_generic, &spr_write_generic,
819 0x00000000);
820 /* XXX : not implemented */
821 spr_register(env, SPR_PMC3, "PMC3",
822 SPR_NOACCESS, SPR_NOACCESS,
823 &spr_read_generic, &spr_write_generic,
824 0x00000000);
825 /* XXX : not implemented */
826 spr_register(env, SPR_PMC4, "PMC4",
827 SPR_NOACCESS, SPR_NOACCESS,
828 &spr_read_generic, &spr_write_generic,
829 0x00000000);
830 /* XXX : not implemented */
831 spr_register(env, SPR_SIAR, "SIAR",
832 SPR_NOACCESS, SPR_NOACCESS,
833 &spr_read_generic, SPR_NOACCESS,
834 0x00000000);
835 /* XXX : not implemented */
836 spr_register(env, SPR_UMMCR0, "UMMCR0",
837 &spr_read_ureg, SPR_NOACCESS,
838 &spr_read_ureg, SPR_NOACCESS,
839 0x00000000);
840 /* XXX : not implemented */
841 spr_register(env, SPR_UMMCR1, "UMMCR1",
842 &spr_read_ureg, SPR_NOACCESS,
843 &spr_read_ureg, SPR_NOACCESS,
844 0x00000000);
845 /* XXX : not implemented */
846 spr_register(env, SPR_UPMC1, "UPMC1",
847 &spr_read_ureg, SPR_NOACCESS,
848 &spr_read_ureg, SPR_NOACCESS,
849 0x00000000);
850 /* XXX : not implemented */
851 spr_register(env, SPR_UPMC2, "UPMC2",
852 &spr_read_ureg, SPR_NOACCESS,
853 &spr_read_ureg, SPR_NOACCESS,
854 0x00000000);
855 /* XXX : not implemented */
856 spr_register(env, SPR_UPMC3, "UPMC3",
857 &spr_read_ureg, SPR_NOACCESS,
858 &spr_read_ureg, SPR_NOACCESS,
859 0x00000000);
860 /* XXX : not implemented */
861 spr_register(env, SPR_UPMC4, "UPMC4",
862 &spr_read_ureg, SPR_NOACCESS,
863 &spr_read_ureg, SPR_NOACCESS,
864 0x00000000);
865 /* XXX : not implemented */
866 spr_register(env, SPR_USIAR, "USIAR",
867 &spr_read_ureg, SPR_NOACCESS,
868 &spr_read_ureg, SPR_NOACCESS,
869 0x00000000);
870 /* External access control */
871 /* XXX : not implemented */
872 spr_register(env, SPR_EAR, "EAR",
873 SPR_NOACCESS, SPR_NOACCESS,
874 &spr_read_generic, &spr_write_generic,
875 0x00000000);
876 }
877
878 static void gen_spr_thrm (CPUPPCState *env)
879 {
880 /* Thermal management */
881 /* XXX : not implemented */
882 spr_register(env, SPR_THRM1, "THRM1",
883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_generic, &spr_write_generic,
885 0x00000000);
886 /* XXX : not implemented */
887 spr_register(env, SPR_THRM2, "THRM2",
888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_generic, &spr_write_generic,
890 0x00000000);
891 /* XXX : not implemented */
892 spr_register(env, SPR_THRM3, "THRM3",
893 SPR_NOACCESS, SPR_NOACCESS,
894 &spr_read_generic, &spr_write_generic,
895 0x00000000);
896 }
897
898 /* SPR specific to PowerPC 604 implementation */
899 static void gen_spr_604 (CPUPPCState *env)
900 {
901 /* Processor identification */
902 spr_register(env, SPR_PIR, "PIR",
903 SPR_NOACCESS, SPR_NOACCESS,
904 &spr_read_generic, &spr_write_pir,
905 0x00000000);
906 /* Breakpoints */
907 /* XXX : not implemented */
908 spr_register(env, SPR_IABR, "IABR",
909 SPR_NOACCESS, SPR_NOACCESS,
910 &spr_read_generic, &spr_write_generic,
911 0x00000000);
912 /* XXX : not implemented */
913 spr_register(env, SPR_DABR, "DABR",
914 SPR_NOACCESS, SPR_NOACCESS,
915 &spr_read_generic, &spr_write_generic,
916 0x00000000);
917 /* Performance counters */
918 /* XXX : not implemented */
919 spr_register(env, SPR_MMCR0, "MMCR0",
920 SPR_NOACCESS, SPR_NOACCESS,
921 &spr_read_generic, &spr_write_generic,
922 0x00000000);
923 /* XXX : not implemented */
924 spr_register(env, SPR_MMCR1, "MMCR1",
925 SPR_NOACCESS, SPR_NOACCESS,
926 &spr_read_generic, &spr_write_generic,
927 0x00000000);
928 /* XXX : not implemented */
929 spr_register(env, SPR_PMC1, "PMC1",
930 SPR_NOACCESS, SPR_NOACCESS,
931 &spr_read_generic, &spr_write_generic,
932 0x00000000);
933 /* XXX : not implemented */
934 spr_register(env, SPR_PMC2, "PMC2",
935 SPR_NOACCESS, SPR_NOACCESS,
936 &spr_read_generic, &spr_write_generic,
937 0x00000000);
938 /* XXX : not implemented */
939 spr_register(env, SPR_PMC3, "PMC3",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943 /* XXX : not implemented */
944 spr_register(env, SPR_PMC4, "PMC4",
945 SPR_NOACCESS, SPR_NOACCESS,
946 &spr_read_generic, &spr_write_generic,
947 0x00000000);
948 /* XXX : not implemented */
949 spr_register(env, SPR_SIAR, "SIAR",
950 SPR_NOACCESS, SPR_NOACCESS,
951 &spr_read_generic, SPR_NOACCESS,
952 0x00000000);
953 /* XXX : not implemented */
954 spr_register(env, SPR_SDA, "SDA",
955 SPR_NOACCESS, SPR_NOACCESS,
956 &spr_read_generic, SPR_NOACCESS,
957 0x00000000);
958 /* External access control */
959 /* XXX : not implemented */
960 spr_register(env, SPR_EAR, "EAR",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, &spr_write_generic,
963 0x00000000);
964 }
965
966 /* SPR specific to PowerPC 603 implementation */
967 static void gen_spr_603 (CPUPPCState *env)
968 {
969 /* External access control */
970 /* XXX : not implemented */
971 spr_register(env, SPR_EAR, "EAR",
972 SPR_NOACCESS, SPR_NOACCESS,
973 &spr_read_generic, &spr_write_generic,
974 0x00000000);
975 }
976
977 /* SPR specific to PowerPC G2 implementation */
978 static void gen_spr_G2 (CPUPPCState *env)
979 {
980 /* Memory base address */
981 /* MBAR */
982 /* XXX : not implemented */
983 spr_register(env, SPR_MBAR, "MBAR",
984 SPR_NOACCESS, SPR_NOACCESS,
985 &spr_read_generic, &spr_write_generic,
986 0x00000000);
987 /* System version register */
988 /* SVR */
989 /* XXX : TODO: initialize it to an appropriate value */
990 spr_register(env, SPR_SVR, "SVR",
991 SPR_NOACCESS, SPR_NOACCESS,
992 &spr_read_generic, SPR_NOACCESS,
993 0x00000000);
994 /* Exception processing */
995 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
996 SPR_NOACCESS, SPR_NOACCESS,
997 &spr_read_generic, &spr_write_generic,
998 0x00000000);
999 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1000 SPR_NOACCESS, SPR_NOACCESS,
1001 &spr_read_generic, &spr_write_generic,
1002 0x00000000);
1003 /* Breakpoints */
1004 /* XXX : not implemented */
1005 spr_register(env, SPR_DABR, "DABR",
1006 SPR_NOACCESS, SPR_NOACCESS,
1007 &spr_read_generic, &spr_write_generic,
1008 0x00000000);
1009 /* XXX : not implemented */
1010 spr_register(env, SPR_DABR2, "DABR2",
1011 SPR_NOACCESS, SPR_NOACCESS,
1012 &spr_read_generic, &spr_write_generic,
1013 0x00000000);
1014 /* XXX : not implemented */
1015 spr_register(env, SPR_IABR, "IABR",
1016 SPR_NOACCESS, SPR_NOACCESS,
1017 &spr_read_generic, &spr_write_generic,
1018 0x00000000);
1019 /* XXX : not implemented */
1020 spr_register(env, SPR_IABR2, "IABR2",
1021 SPR_NOACCESS, SPR_NOACCESS,
1022 &spr_read_generic, &spr_write_generic,
1023 0x00000000);
1024 /* XXX : not implemented */
1025 spr_register(env, SPR_IBCR, "IBCR",
1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_generic,
1028 0x00000000);
1029 /* XXX : not implemented */
1030 spr_register(env, SPR_DBCR, "DBCR",
1031 SPR_NOACCESS, SPR_NOACCESS,
1032 &spr_read_generic, &spr_write_generic,
1033 0x00000000);
1034 }
1035
1036 /* SPR specific to PowerPC 602 implementation */
1037 static void gen_spr_602 (CPUPPCState *env)
1038 {
1039 /* ESA registers */
1040 /* XXX : not implemented */
1041 spr_register(env, SPR_SER, "SER",
1042 SPR_NOACCESS, SPR_NOACCESS,
1043 &spr_read_generic, &spr_write_generic,
1044 0x00000000);
1045 /* XXX : not implemented */
1046 spr_register(env, SPR_SEBR, "SEBR",
1047 SPR_NOACCESS, SPR_NOACCESS,
1048 &spr_read_generic, &spr_write_generic,
1049 0x00000000);
1050 /* XXX : not implemented */
1051 spr_register(env, SPR_ESASRR, "ESASRR",
1052 SPR_NOACCESS, SPR_NOACCESS,
1053 &spr_read_generic, &spr_write_generic,
1054 0x00000000);
1055 /* Floating point status */
1056 /* XXX : not implemented */
1057 spr_register(env, SPR_SP, "SP",
1058 SPR_NOACCESS, SPR_NOACCESS,
1059 &spr_read_generic, &spr_write_generic,
1060 0x00000000);
1061 /* XXX : not implemented */
1062 spr_register(env, SPR_LT, "LT",
1063 SPR_NOACCESS, SPR_NOACCESS,
1064 &spr_read_generic, &spr_write_generic,
1065 0x00000000);
1066 /* Watchdog timer */
1067 /* XXX : not implemented */
1068 spr_register(env, SPR_TCR, "TCR",
1069 SPR_NOACCESS, SPR_NOACCESS,
1070 &spr_read_generic, &spr_write_generic,
1071 0x00000000);
1072 /* Interrupt base */
1073 spr_register(env, SPR_IBR, "IBR",
1074 SPR_NOACCESS, SPR_NOACCESS,
1075 &spr_read_generic, &spr_write_generic,
1076 0x00000000);
1077 /* XXX : not implemented */
1078 spr_register(env, SPR_IABR, "IABR",
1079 SPR_NOACCESS, SPR_NOACCESS,
1080 &spr_read_generic, &spr_write_generic,
1081 0x00000000);
1082 }
1083
1084 /* SPR specific to PowerPC 601 implementation */
1085 static void gen_spr_601 (CPUPPCState *env)
1086 {
1087 /* Multiplication/division register */
1088 /* MQ */
1089 spr_register(env, SPR_MQ, "MQ",
1090 &spr_read_generic, &spr_write_generic,
1091 &spr_read_generic, &spr_write_generic,
1092 0x00000000);
1093 /* RTC registers */
1094 spr_register(env, SPR_601_RTCU, "RTCU",
1095 SPR_NOACCESS, SPR_NOACCESS,
1096 SPR_NOACCESS, &spr_write_601_rtcu,
1097 0x00000000);
1098 spr_register(env, SPR_601_VRTCU, "RTCU",
1099 &spr_read_601_rtcu, SPR_NOACCESS,
1100 &spr_read_601_rtcu, SPR_NOACCESS,
1101 0x00000000);
1102 spr_register(env, SPR_601_RTCL, "RTCL",
1103 SPR_NOACCESS, SPR_NOACCESS,
1104 SPR_NOACCESS, &spr_write_601_rtcl,
1105 0x00000000);
1106 spr_register(env, SPR_601_VRTCL, "RTCL",
1107 &spr_read_601_rtcl, SPR_NOACCESS,
1108 &spr_read_601_rtcl, SPR_NOACCESS,
1109 0x00000000);
1110 /* Timer */
1111 #if 0 /* ? */
1112 spr_register(env, SPR_601_UDECR, "UDECR",
1113 &spr_read_decr, SPR_NOACCESS,
1114 &spr_read_decr, SPR_NOACCESS,
1115 0x00000000);
1116 #endif
1117 /* External access control */
1118 /* XXX : not implemented */
1119 spr_register(env, SPR_EAR, "EAR",
1120 SPR_NOACCESS, SPR_NOACCESS,
1121 &spr_read_generic, &spr_write_generic,
1122 0x00000000);
1123 /* Memory management */
1124 #if !defined(CONFIG_USER_ONLY)
1125 spr_register(env, SPR_IBAT0U, "IBAT0U",
1126 SPR_NOACCESS, SPR_NOACCESS,
1127 &spr_read_601_ubat, &spr_write_601_ubatu,
1128 0x00000000);
1129 spr_register(env, SPR_IBAT0L, "IBAT0L",
1130 SPR_NOACCESS, SPR_NOACCESS,
1131 &spr_read_601_ubat, &spr_write_601_ubatl,
1132 0x00000000);
1133 spr_register(env, SPR_IBAT1U, "IBAT1U",
1134 SPR_NOACCESS, SPR_NOACCESS,
1135 &spr_read_601_ubat, &spr_write_601_ubatu,
1136 0x00000000);
1137 spr_register(env, SPR_IBAT1L, "IBAT1L",
1138 SPR_NOACCESS, SPR_NOACCESS,
1139 &spr_read_601_ubat, &spr_write_601_ubatl,
1140 0x00000000);
1141 spr_register(env, SPR_IBAT2U, "IBAT2U",
1142 SPR_NOACCESS, SPR_NOACCESS,
1143 &spr_read_601_ubat, &spr_write_601_ubatu,
1144 0x00000000);
1145 spr_register(env, SPR_IBAT2L, "IBAT2L",
1146 SPR_NOACCESS, SPR_NOACCESS,
1147 &spr_read_601_ubat, &spr_write_601_ubatl,
1148 0x00000000);
1149 spr_register(env, SPR_IBAT3U, "IBAT3U",
1150 SPR_NOACCESS, SPR_NOACCESS,
1151 &spr_read_601_ubat, &spr_write_601_ubatu,
1152 0x00000000);
1153 spr_register(env, SPR_IBAT3L, "IBAT3L",
1154 SPR_NOACCESS, SPR_NOACCESS,
1155 &spr_read_601_ubat, &spr_write_601_ubatl,
1156 0x00000000);
1157 env->nb_BATs = 4;
1158 #endif
1159 }
1160
1161 static void gen_spr_74xx (CPUPPCState *env)
1162 {
1163 /* Processor identification */
1164 spr_register(env, SPR_PIR, "PIR",
1165 SPR_NOACCESS, SPR_NOACCESS,
1166 &spr_read_generic, &spr_write_pir,
1167 0x00000000);
1168 /* XXX : not implemented */
1169 spr_register(env, SPR_MMCR2, "MMCR2",
1170 SPR_NOACCESS, SPR_NOACCESS,
1171 &spr_read_generic, &spr_write_generic,
1172 0x00000000);
1173 /* XXX : not implemented */
1174 spr_register(env, SPR_UMMCR2, "UMMCR2",
1175 &spr_read_ureg, SPR_NOACCESS,
1176 &spr_read_ureg, SPR_NOACCESS,
1177 0x00000000);
1178 /* XXX: not implemented */
1179 spr_register(env, SPR_BAMR, "BAMR",
1180 SPR_NOACCESS, SPR_NOACCESS,
1181 &spr_read_generic, &spr_write_generic,
1182 0x00000000);
1183 /* XXX : not implemented */
1184 spr_register(env, SPR_UBAMR, "UBAMR",
1185 &spr_read_ureg, SPR_NOACCESS,
1186 &spr_read_ureg, SPR_NOACCESS,
1187 0x00000000);
1188 /* XXX : not implemented */
1189 spr_register(env, SPR_MSSCR0, "MSSCR0",
1190 SPR_NOACCESS, SPR_NOACCESS,
1191 &spr_read_generic, &spr_write_generic,
1192 0x00000000);
1193 /* Hardware implementation registers */
1194 /* XXX : not implemented */
1195 spr_register(env, SPR_HID0, "HID0",
1196 SPR_NOACCESS, SPR_NOACCESS,
1197 &spr_read_generic, &spr_write_generic,
1198 0x00000000);
1199 /* XXX : not implemented */
1200 spr_register(env, SPR_HID1, "HID1",
1201 SPR_NOACCESS, SPR_NOACCESS,
1202 &spr_read_generic, &spr_write_generic,
1203 0x00000000);
1204 /* Altivec */
1205 spr_register(env, SPR_VRSAVE, "VRSAVE",
1206 &spr_read_generic, &spr_write_generic,
1207 &spr_read_generic, &spr_write_generic,
1208 0x00000000);
1209 }
1210
1211 static void gen_l3_ctrl (CPUPPCState *env)
1212 {
1213 /* L3CR */
1214 /* XXX : not implemented */
1215 spr_register(env, SPR_L3CR, "L3CR",
1216 SPR_NOACCESS, SPR_NOACCESS,
1217 &spr_read_generic, &spr_write_generic,
1218 0x00000000);
1219 /* L3ITCR0 */
1220 /* XXX : not implemented */
1221 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1222 SPR_NOACCESS, SPR_NOACCESS,
1223 &spr_read_generic, &spr_write_generic,
1224 0x00000000);
1225 /* L3ITCR1 */
1226 /* XXX : not implemented */
1227 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1228 SPR_NOACCESS, SPR_NOACCESS,
1229 &spr_read_generic, &spr_write_generic,
1230 0x00000000);
1231 /* L3ITCR2 */
1232 /* XXX : not implemented */
1233 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1234 SPR_NOACCESS, SPR_NOACCESS,
1235 &spr_read_generic, &spr_write_generic,
1236 0x00000000);
1237 /* L3ITCR3 */
1238 /* XXX : not implemented */
1239 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1240 SPR_NOACCESS, SPR_NOACCESS,
1241 &spr_read_generic, &spr_write_generic,
1242 0x00000000);
1243 /* L3OHCR */
1244 /* XXX : not implemented */
1245 spr_register(env, SPR_L3OHCR, "L3OHCR",
1246 SPR_NOACCESS, SPR_NOACCESS,
1247 &spr_read_generic, &spr_write_generic,
1248 0x00000000);
1249 /* L3PM */
1250 /* XXX : not implemented */
1251 spr_register(env, SPR_L3PM, "L3PM",
1252 SPR_NOACCESS, SPR_NOACCESS,
1253 &spr_read_generic, &spr_write_generic,
1254 0x00000000);
1255 }
1256
1257 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1258 {
1259 #if !defined(CONFIG_USER_ONLY)
1260 env->nb_tlb = nb_tlbs;
1261 env->nb_ways = nb_ways;
1262 env->id_tlbs = 1;
1263 /* XXX : not implemented */
1264 spr_register(env, SPR_PTEHI, "PTEHI",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_generic,
1267 0x00000000);
1268 /* XXX : not implemented */
1269 spr_register(env, SPR_PTELO, "PTELO",
1270 SPR_NOACCESS, SPR_NOACCESS,
1271 &spr_read_generic, &spr_write_generic,
1272 0x00000000);
1273 /* XXX : not implemented */
1274 spr_register(env, SPR_TLBMISS, "TLBMISS",
1275 SPR_NOACCESS, SPR_NOACCESS,
1276 &spr_read_generic, &spr_write_generic,
1277 0x00000000);
1278 #endif
1279 }
1280
1281 /* PowerPC BookE SPR */
1282 static void gen_spr_BookE (CPUPPCState *env)
1283 {
1284 /* Processor identification */
1285 spr_register(env, SPR_BOOKE_PIR, "PIR",
1286 SPR_NOACCESS, SPR_NOACCESS,
1287 &spr_read_generic, &spr_write_pir,
1288 0x00000000);
1289 /* Interrupt processing */
1290 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1291 SPR_NOACCESS, SPR_NOACCESS,
1292 &spr_read_generic, &spr_write_generic,
1293 0x00000000);
1294 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1295 SPR_NOACCESS, SPR_NOACCESS,
1296 &spr_read_generic, &spr_write_generic,
1297 0x00000000);
1298 #if 0
1299 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1300 SPR_NOACCESS, SPR_NOACCESS,
1301 &spr_read_generic, &spr_write_generic,
1302 0x00000000);
1303 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1304 SPR_NOACCESS, SPR_NOACCESS,
1305 &spr_read_generic, &spr_write_generic,
1306 0x00000000);
1307 #endif
1308 /* Debug */
1309 /* XXX : not implemented */
1310 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1311 SPR_NOACCESS, SPR_NOACCESS,
1312 &spr_read_generic, &spr_write_generic,
1313 0x00000000);
1314 /* XXX : not implemented */
1315 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1316 SPR_NOACCESS, SPR_NOACCESS,
1317 &spr_read_generic, &spr_write_generic,
1318 0x00000000);
1319 /* XXX : not implemented */
1320 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1321 SPR_NOACCESS, SPR_NOACCESS,
1322 &spr_read_generic, &spr_write_generic,
1323 0x00000000);
1324 /* XXX : not implemented */
1325 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1326 SPR_NOACCESS, SPR_NOACCESS,
1327 &spr_read_generic, &spr_write_generic,
1328 0x00000000);
1329 /* XXX : not implemented */
1330 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1333 0x00000000);
1334 /* XXX : not implemented */
1335 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1336 SPR_NOACCESS, SPR_NOACCESS,
1337 &spr_read_generic, &spr_write_generic,
1338 0x00000000);
1339 /* XXX : not implemented */
1340 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1341 SPR_NOACCESS, SPR_NOACCESS,
1342 &spr_read_generic, &spr_write_generic,
1343 0x00000000);
1344 /* XXX : not implemented */
1345 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1346 SPR_NOACCESS, SPR_NOACCESS,
1347 &spr_read_generic, &spr_write_generic,
1348 0x00000000);
1349 /* XXX : not implemented */
1350 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_generic,
1353 0x00000000);
1354 /* XXX : not implemented */
1355 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1356 SPR_NOACCESS, SPR_NOACCESS,
1357 &spr_read_generic, &spr_write_generic,
1358 0x00000000);
1359 /* XXX : not implemented */
1360 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1361 SPR_NOACCESS, SPR_NOACCESS,
1362 &spr_read_generic, &spr_write_generic,
1363 0x00000000);
1364 /* XXX : not implemented */
1365 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1366 SPR_NOACCESS, SPR_NOACCESS,
1367 &spr_read_generic, &spr_write_clear,
1368 0x00000000);
1369 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1370 SPR_NOACCESS, SPR_NOACCESS,
1371 &spr_read_generic, &spr_write_generic,
1372 0x00000000);
1373 spr_register(env, SPR_BOOKE_ESR, "ESR",
1374 SPR_NOACCESS, SPR_NOACCESS,
1375 &spr_read_generic, &spr_write_generic,
1376 0x00000000);
1377 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1378 SPR_NOACCESS, SPR_NOACCESS,
1379 &spr_read_generic, &spr_write_excp_prefix,
1380 0x00000000);
1381 /* Exception vectors */
1382 spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1383 SPR_NOACCESS, SPR_NOACCESS,
1384 &spr_read_generic, &spr_write_excp_vector,
1385 0x00000000);
1386 spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1387 SPR_NOACCESS, SPR_NOACCESS,
1388 &spr_read_generic, &spr_write_excp_vector,
1389 0x00000000);
1390 spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1391 SPR_NOACCESS, SPR_NOACCESS,
1392 &spr_read_generic, &spr_write_excp_vector,
1393 0x00000000);
1394 spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1395 SPR_NOACCESS, SPR_NOACCESS,
1396 &spr_read_generic, &spr_write_excp_vector,
1397 0x00000000);
1398 spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1399 SPR_NOACCESS, SPR_NOACCESS,
1400 &spr_read_generic, &spr_write_excp_vector,
1401 0x00000000);
1402 spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1403 SPR_NOACCESS, SPR_NOACCESS,
1404 &spr_read_generic, &spr_write_excp_vector,
1405 0x00000000);
1406 spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1407 SPR_NOACCESS, SPR_NOACCESS,
1408 &spr_read_generic, &spr_write_excp_vector,
1409 0x00000000);
1410 spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1411 SPR_NOACCESS, SPR_NOACCESS,
1412 &spr_read_generic, &spr_write_excp_vector,
1413 0x00000000);
1414 spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1415 SPR_NOACCESS, SPR_NOACCESS,
1416 &spr_read_generic, &spr_write_excp_vector,
1417 0x00000000);
1418 spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1419 SPR_NOACCESS, SPR_NOACCESS,
1420 &spr_read_generic, &spr_write_excp_vector,
1421 0x00000000);
1422 spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1423 SPR_NOACCESS, SPR_NOACCESS,
1424 &spr_read_generic, &spr_write_excp_vector,
1425 0x00000000);
1426 spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1427 SPR_NOACCESS, SPR_NOACCESS,
1428 &spr_read_generic, &spr_write_excp_vector,
1429 0x00000000);
1430 spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1431 SPR_NOACCESS, SPR_NOACCESS,
1432 &spr_read_generic, &spr_write_excp_vector,
1433 0x00000000);
1434 spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1435 SPR_NOACCESS, SPR_NOACCESS,
1436 &spr_read_generic, &spr_write_excp_vector,
1437 0x00000000);
1438 spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1439 SPR_NOACCESS, SPR_NOACCESS,
1440 &spr_read_generic, &spr_write_excp_vector,
1441 0x00000000);
1442 spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1443 SPR_NOACCESS, SPR_NOACCESS,
1444 &spr_read_generic, &spr_write_excp_vector,
1445 0x00000000);
1446 #if 0
1447 spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1448 SPR_NOACCESS, SPR_NOACCESS,
1449 &spr_read_generic, &spr_write_excp_vector,
1450 0x00000000);
1451 spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1452 SPR_NOACCESS, SPR_NOACCESS,
1453 &spr_read_generic, &spr_write_excp_vector,
1454 0x00000000);
1455 spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1456 SPR_NOACCESS, SPR_NOACCESS,
1457 &spr_read_generic, &spr_write_excp_vector,
1458 0x00000000);
1459 spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1460 SPR_NOACCESS, SPR_NOACCESS,
1461 &spr_read_generic, &spr_write_excp_vector,
1462 0x00000000);
1463 spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1464 SPR_NOACCESS, SPR_NOACCESS,
1465 &spr_read_generic, &spr_write_excp_vector,
1466 0x00000000);
1467 spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1468 SPR_NOACCESS, SPR_NOACCESS,
1469 &spr_read_generic, &spr_write_excp_vector,
1470 0x00000000);
1471 #endif
1472 spr_register(env, SPR_BOOKE_PID, "PID",
1473 SPR_NOACCESS, SPR_NOACCESS,
1474 &spr_read_generic, &spr_write_generic,
1475 0x00000000);
1476 spr_register(env, SPR_BOOKE_TCR, "TCR",
1477 SPR_NOACCESS, SPR_NOACCESS,
1478 &spr_read_generic, &spr_write_booke_tcr,
1479 0x00000000);
1480 spr_register(env, SPR_BOOKE_TSR, "TSR",
1481 SPR_NOACCESS, SPR_NOACCESS,
1482 &spr_read_generic, &spr_write_booke_tsr,
1483 0x00000000);
1484 /* Timer */
1485 spr_register(env, SPR_DECR, "DECR",
1486 SPR_NOACCESS, SPR_NOACCESS,
1487 &spr_read_decr, &spr_write_decr,
1488 0x00000000);
1489 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1490 SPR_NOACCESS, SPR_NOACCESS,
1491 SPR_NOACCESS, &spr_write_generic,
1492 0x00000000);
1493 /* SPRGs */
1494 spr_register(env, SPR_USPRG0, "USPRG0",
1495 &spr_read_generic, &spr_write_generic,
1496 &spr_read_generic, &spr_write_generic,
1497 0x00000000);
1498 spr_register(env, SPR_SPRG4, "SPRG4",
1499 SPR_NOACCESS, SPR_NOACCESS,
1500 &spr_read_generic, &spr_write_generic,
1501 0x00000000);
1502 spr_register(env, SPR_USPRG4, "USPRG4",
1503 &spr_read_ureg, SPR_NOACCESS,
1504 &spr_read_ureg, SPR_NOACCESS,
1505 0x00000000);
1506 spr_register(env, SPR_SPRG5, "SPRG5",
1507 SPR_NOACCESS, SPR_NOACCESS,
1508 &spr_read_generic, &spr_write_generic,
1509 0x00000000);
1510 spr_register(env, SPR_USPRG5, "USPRG5",
1511 &spr_read_ureg, SPR_NOACCESS,
1512 &spr_read_ureg, SPR_NOACCESS,
1513 0x00000000);
1514 spr_register(env, SPR_SPRG6, "SPRG6",
1515 SPR_NOACCESS, SPR_NOACCESS,
1516 &spr_read_generic, &spr_write_generic,
1517 0x00000000);
1518 spr_register(env, SPR_USPRG6, "USPRG6",
1519 &spr_read_ureg, SPR_NOACCESS,
1520 &spr_read_ureg, SPR_NOACCESS,
1521 0x00000000);
1522 spr_register(env, SPR_SPRG7, "SPRG7",
1523 SPR_NOACCESS, SPR_NOACCESS,
1524 &spr_read_generic, &spr_write_generic,
1525 0x00000000);
1526 spr_register(env, SPR_USPRG7, "USPRG7",
1527 &spr_read_ureg, SPR_NOACCESS,
1528 &spr_read_ureg, SPR_NOACCESS,
1529 0x00000000);
1530 }
1531
1532 /* FSL storage control registers */
1533 static void gen_spr_BookE_FSL (CPUPPCState *env)
1534 {
1535 #if !defined(CONFIG_USER_ONLY)
1536 /* TLB assist registers */
1537 /* XXX : not implemented */
1538 spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1539 SPR_NOACCESS, SPR_NOACCESS,
1540 &spr_read_generic, &spr_write_generic,
1541 0x00000000);
1542 /* XXX : not implemented */
1543 spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1544 SPR_NOACCESS, SPR_NOACCESS,
1545 &spr_read_generic, &spr_write_generic,
1546 0x00000000);
1547 /* XXX : not implemented */
1548 spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_generic,
1551 0x00000000);
1552 /* XXX : not implemented */
1553 spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
1557 /* XXX : not implemented */
1558 spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_generic, &spr_write_generic,
1561 0x00000000);
1562 /* XXX : not implemented */
1563 spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1564 SPR_NOACCESS, SPR_NOACCESS,
1565 &spr_read_generic, &spr_write_generic,
1566 0x00000000);
1567 /* XXX : not implemented */
1568 spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1569 SPR_NOACCESS, SPR_NOACCESS,
1570 &spr_read_generic, &spr_write_generic,
1571 0x00000000);
1572 if (env->nb_pids > 1) {
1573 /* XXX : not implemented */
1574 spr_register(env, SPR_BOOKE_PID1, "PID1",
1575 SPR_NOACCESS, SPR_NOACCESS,
1576 &spr_read_generic, &spr_write_generic,
1577 0x00000000);
1578 }
1579 if (env->nb_pids > 2) {
1580 /* XXX : not implemented */
1581 spr_register(env, SPR_BOOKE_PID2, "PID2",
1582 SPR_NOACCESS, SPR_NOACCESS,
1583 &spr_read_generic, &spr_write_generic,
1584 0x00000000);
1585 }
1586 /* XXX : not implemented */
1587 spr_register(env, SPR_MMUCFG, "MMUCFG",
1588 SPR_NOACCESS, SPR_NOACCESS,
1589 &spr_read_generic, SPR_NOACCESS,
1590 0x00000000); /* TOFIX */
1591 /* XXX : not implemented */
1592 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
1593 SPR_NOACCESS, SPR_NOACCESS,
1594 &spr_read_generic, &spr_write_generic,
1595 0x00000000); /* TOFIX */
1596 switch (env->nb_ways) {
1597 case 4:
1598 /* XXX : not implemented */
1599 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1600 SPR_NOACCESS, SPR_NOACCESS,
1601 &spr_read_generic, SPR_NOACCESS,
1602 0x00000000); /* TOFIX */
1603 /* Fallthru */
1604 case 3:
1605 /* XXX : not implemented */
1606 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1607 SPR_NOACCESS, SPR_NOACCESS,
1608 &spr_read_generic, SPR_NOACCESS,
1609 0x00000000); /* TOFIX */
1610 /* Fallthru */
1611 case 2:
1612 /* XXX : not implemented */
1613 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1614 SPR_NOACCESS, SPR_NOACCESS,
1615 &spr_read_generic, SPR_NOACCESS,
1616 0x00000000); /* TOFIX */
1617 /* Fallthru */
1618 case 1:
1619 /* XXX : not implemented */
1620 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1621 SPR_NOACCESS, SPR_NOACCESS,
1622 &spr_read_generic, SPR_NOACCESS,
1623 0x00000000); /* TOFIX */
1624 /* Fallthru */
1625 case 0:
1626 default:
1627 break;
1628 }
1629 #endif
1630 }
1631
1632 /* SPR specific to PowerPC 440 implementation */
1633 static void gen_spr_440 (CPUPPCState *env)
1634 {
1635 /* Cache control */
1636 /* XXX : not implemented */
1637 spr_register(env, SPR_440_DNV0, "DNV0",
1638 SPR_NOACCESS, SPR_NOACCESS,
1639 &spr_read_generic, &spr_write_generic,
1640 0x00000000);
1641 /* XXX : not implemented */
1642 spr_register(env, SPR_440_DNV1, "DNV1",
1643 SPR_NOACCESS, SPR_NOACCESS,
1644 &spr_read_generic, &spr_write_generic,
1645 0x00000000);
1646 /* XXX : not implemented */
1647 spr_register(env, SPR_440_DNV2, "DNV2",
1648 SPR_NOACCESS, SPR_NOACCESS,
1649 &spr_read_generic, &spr_write_generic,
1650 0x00000000);
1651 /* XXX : not implemented */
1652 spr_register(env, SPR_440_DNV3, "DNV3",
1653 SPR_NOACCESS, SPR_NOACCESS,
1654 &spr_read_generic, &spr_write_generic,
1655 0x00000000);
1656 /* XXX : not implemented */
1657 spr_register(env, SPR_440_DTV0, "DTV0",
1658 SPR_NOACCESS, SPR_NOACCESS,
1659 &spr_read_generic, &spr_write_generic,
1660 0x00000000);
1661 /* XXX : not implemented */
1662 spr_register(env, SPR_440_DTV1, "DTV1",
1663 SPR_NOACCESS, SPR_NOACCESS,
1664 &spr_read_generic, &spr_write_generic,
1665 0x00000000);
1666 /* XXX : not implemented */
1667 spr_register(env, SPR_440_DTV2, "DTV2",
1668 SPR_NOACCESS, SPR_NOACCESS,
1669 &spr_read_generic, &spr_write_generic,
1670 0x00000000);
1671 /* XXX : not implemented */
1672 spr_register(env, SPR_440_DTV3, "DTV3",
1673 SPR_NOACCESS, SPR_NOACCESS,
1674 &spr_read_generic, &spr_write_generic,
1675 0x00000000);
1676 /* XXX : not implemented */
1677 spr_register(env, SPR_440_DVLIM, "DVLIM",
1678 SPR_NOACCESS, SPR_NOACCESS,
1679 &spr_read_generic, &spr_write_generic,
1680 0x00000000);
1681 /* XXX : not implemented */
1682 spr_register(env, SPR_440_INV0, "INV0",
1683 SPR_NOACCESS, SPR_NOACCESS,
1684 &spr_read_generic, &spr_write_generic,
1685 0x00000000);
1686 /* XXX : not implemented */
1687 spr_register(env, SPR_440_INV1, "INV1",
1688 SPR_NOACCESS, SPR_NOACCESS,
1689 &spr_read_generic, &spr_write_generic,
1690 0x00000000);
1691 /* XXX : not implemented */
1692 spr_register(env, SPR_440_INV2, "INV2",
1693 SPR_NOACCESS, SPR_NOACCESS,
1694 &spr_read_generic, &spr_write_generic,
1695 0x00000000);
1696 /* XXX : not implemented */
1697 spr_register(env, SPR_440_INV3, "INV3",
1698 SPR_NOACCESS, SPR_NOACCESS,
1699 &spr_read_generic, &spr_write_generic,
1700 0x00000000);
1701 /* XXX : not implemented */
1702 spr_register(env, SPR_440_ITV0, "ITV0",
1703 SPR_NOACCESS, SPR_NOACCESS,
1704 &spr_read_generic, &spr_write_generic,
1705 0x00000000);
1706 /* XXX : not implemented */
1707 spr_register(env, SPR_440_ITV1, "ITV1",
1708 SPR_NOACCESS, SPR_NOACCESS,
1709 &spr_read_generic, &spr_write_generic,
1710 0x00000000);
1711 /* XXX : not implemented */
1712 spr_register(env, SPR_440_ITV2, "ITV2",
1713 SPR_NOACCESS, SPR_NOACCESS,
1714 &spr_read_generic, &spr_write_generic,
1715 0x00000000);
1716 /* XXX : not implemented */
1717 spr_register(env, SPR_440_ITV3, "ITV3",
1718 SPR_NOACCESS, SPR_NOACCESS,
1719 &spr_read_generic, &spr_write_generic,
1720 0x00000000);
1721 /* XXX : not implemented */
1722 spr_register(env, SPR_440_IVLIM, "IVLIM",
1723 SPR_NOACCESS, SPR_NOACCESS,
1724 &spr_read_generic, &spr_write_generic,
1725 0x00000000);
1726 /* Cache debug */
1727 /* XXX : not implemented */
1728 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, SPR_NOACCESS,
1731 0x00000000);
1732 /* XXX : not implemented */
1733 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1734 SPR_NOACCESS, SPR_NOACCESS,
1735 &spr_read_generic, SPR_NOACCESS,
1736 0x00000000);
1737 /* XXX : not implemented */
1738 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, SPR_NOACCESS,
1741 0x00000000);
1742 /* XXX : not implemented */
1743 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, SPR_NOACCESS,
1746 0x00000000);
1747 /* XXX : not implemented */
1748 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, SPR_NOACCESS,
1751 0x00000000);
1752 /* XXX : not implemented */
1753 spr_register(env, SPR_440_DBDR, "DBDR",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, &spr_write_generic,
1756 0x00000000);
1757 /* Processor control */
1758 spr_register(env, SPR_4xx_CCR0, "CCR0",
1759 SPR_NOACCESS, SPR_NOACCESS,
1760 &spr_read_generic, &spr_write_generic,
1761 0x00000000);
1762 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1763 SPR_NOACCESS, SPR_NOACCESS,
1764 &spr_read_generic, SPR_NOACCESS,
1765 0x00000000);
1766 /* Storage control */
1767 spr_register(env, SPR_440_MMUCR, "MMUCR",
1768 SPR_NOACCESS, SPR_NOACCESS,
1769 &spr_read_generic, &spr_write_generic,
1770 0x00000000);
1771 }
1772
1773 /* SPR shared between PowerPC 40x implementations */
1774 static void gen_spr_40x (CPUPPCState *env)
1775 {
1776 /* Cache */
1777 /* not emulated, as Qemu do not emulate caches */
1778 spr_register(env, SPR_40x_DCCR, "DCCR",
1779 SPR_NOACCESS, SPR_NOACCESS,
1780 &spr_read_generic, &spr_write_generic,
1781 0x00000000);
1782 /* not emulated, as Qemu do not emulate caches */
1783 spr_register(env, SPR_40x_ICCR, "ICCR",
1784 SPR_NOACCESS, SPR_NOACCESS,
1785 &spr_read_generic, &spr_write_generic,
1786 0x00000000);
1787 /* not emulated, as Qemu do not emulate caches */
1788 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1789 SPR_NOACCESS, SPR_NOACCESS,
1790 &spr_read_generic, SPR_NOACCESS,
1791 0x00000000);
1792 /* Exception */
1793 spr_register(env, SPR_40x_DEAR, "DEAR",
1794 SPR_NOACCESS, SPR_NOACCESS,
1795 &spr_read_generic, &spr_write_generic,
1796 0x00000000);
1797 spr_register(env, SPR_40x_ESR, "ESR",
1798 SPR_NOACCESS, SPR_NOACCESS,
1799 &spr_read_generic, &spr_write_generic,
1800 0x00000000);
1801 spr_register(env, SPR_40x_EVPR, "EVPR",
1802 SPR_NOACCESS, SPR_NOACCESS,
1803 &spr_read_generic, &spr_write_excp_prefix,
1804 0x00000000);
1805 spr_register(env, SPR_40x_SRR2, "SRR2",
1806 &spr_read_generic, &spr_write_generic,
1807 &spr_read_generic, &spr_write_generic,
1808 0x00000000);
1809 spr_register(env, SPR_40x_SRR3, "SRR3",
1810 &spr_read_generic, &spr_write_generic,
1811 &spr_read_generic, &spr_write_generic,
1812 0x00000000);
1813 /* Timers */
1814 spr_register(env, SPR_40x_PIT, "PIT",
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_40x_pit, &spr_write_40x_pit,
1817 0x00000000);
1818 spr_register(env, SPR_40x_TCR, "TCR",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, &spr_write_booke_tcr,
1821 0x00000000);
1822 spr_register(env, SPR_40x_TSR, "TSR",
1823 SPR_NOACCESS, SPR_NOACCESS,
1824 &spr_read_generic, &spr_write_booke_tsr,
1825 0x00000000);
1826 }
1827
1828 /* SPR specific to PowerPC 405 implementation */
1829 static void gen_spr_405 (CPUPPCState *env)
1830 {
1831 /* MMU */
1832 spr_register(env, SPR_40x_PID, "PID",
1833 SPR_NOACCESS, SPR_NOACCESS,
1834 &spr_read_generic, &spr_write_generic,
1835 0x00000000);
1836 spr_register(env, SPR_4xx_CCR0, "CCR0",
1837 SPR_NOACCESS, SPR_NOACCESS,
1838 &spr_read_generic, &spr_write_generic,
1839 0x00700000);
1840 /* Debug interface */
1841 /* XXX : not implemented */
1842 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1843 SPR_NOACCESS, SPR_NOACCESS,
1844 &spr_read_generic, &spr_write_40x_dbcr0,
1845 0x00000000);
1846 /* XXX : not implemented */
1847 spr_register(env, SPR_405_DBCR1, "DBCR1",
1848 SPR_NOACCESS, SPR_NOACCESS,
1849 &spr_read_generic, &spr_write_generic,
1850 0x00000000);
1851 /* XXX : not implemented */
1852 spr_register(env, SPR_40x_DBSR, "DBSR",
1853 SPR_NOACCESS, SPR_NOACCESS,
1854 &spr_read_generic, &spr_write_clear,
1855 /* Last reset was system reset */
1856 0x00000300);
1857 /* XXX : not implemented */
1858 spr_register(env, SPR_40x_DAC1, "DAC1",
1859 SPR_NOACCESS, SPR_NOACCESS,
1860 &spr_read_generic, &spr_write_generic,
1861 0x00000000);
1862 spr_register(env, SPR_40x_DAC2, "DAC2",
1863 SPR_NOACCESS, SPR_NOACCESS,
1864 &spr_read_generic, &spr_write_generic,
1865 0x00000000);
1866 /* XXX : not implemented */
1867 spr_register(env, SPR_405_DVC1, "DVC1",
1868 SPR_NOACCESS, SPR_NOACCESS,
1869 &spr_read_generic, &spr_write_generic,
1870 0x00000000);
1871 /* XXX : not implemented */
1872 spr_register(env, SPR_405_DVC2, "DVC2",
1873 SPR_NOACCESS, SPR_NOACCESS,
1874 &spr_read_generic, &spr_write_generic,
1875 0x00000000);
1876 /* XXX : not implemented */
1877 spr_register(env, SPR_40x_IAC1, "IAC1",
1878 SPR_NOACCESS, SPR_NOACCESS,
1879 &spr_read_generic, &spr_write_generic,
1880 0x00000000);
1881 spr_register(env, SPR_40x_IAC2, "IAC2",
1882 SPR_NOACCESS, SPR_NOACCESS,
1883 &spr_read_generic, &spr_write_generic,
1884 0x00000000);
1885 /* XXX : not implemented */
1886 spr_register(env, SPR_405_IAC3, "IAC3",
1887 SPR_NOACCESS, SPR_NOACCESS,
1888 &spr_read_generic, &spr_write_generic,
1889 0x00000000);
1890 /* XXX : not implemented */
1891 spr_register(env, SPR_405_IAC4, "IAC4",
1892 SPR_NOACCESS, SPR_NOACCESS,
1893 &spr_read_generic, &spr_write_generic,
1894 0x00000000);
1895 /* Storage control */
1896 /* XXX: TODO: not implemented */
1897 spr_register(env, SPR_405_SLER, "SLER",
1898 SPR_NOACCESS, SPR_NOACCESS,
1899 &spr_read_generic, &spr_write_40x_sler,
1900 0x00000000);
1901 spr_register(env, SPR_40x_ZPR, "ZPR",
1902 SPR_NOACCESS, SPR_NOACCESS,
1903 &spr_read_generic, &spr_write_generic,
1904 0x00000000);
1905 /* XXX : not implemented */
1906 spr_register(env, SPR_405_SU0R, "SU0R",
1907 SPR_NOACCESS, SPR_NOACCESS,
1908 &spr_read_generic, &spr_write_generic,
1909 0x00000000);
1910 /* SPRG */
1911 spr_register(env, SPR_USPRG0, "USPRG0",
1912 &spr_read_ureg, SPR_NOACCESS,
1913 &spr_read_ureg, SPR_NOACCESS,
1914 0x00000000);
1915 spr_register(env, SPR_SPRG4, "SPRG4",
1916 SPR_NOACCESS, SPR_NOACCESS,
1917 &spr_read_generic, &spr_write_generic,
1918 0x00000000);
1919 spr_register(env, SPR_USPRG4, "USPRG4",
1920 &spr_read_ureg, SPR_NOACCESS,
1921 &spr_read_ureg, SPR_NOACCESS,
1922 0x00000000);
1923 spr_register(env, SPR_SPRG5, "SPRG5",
1924 SPR_NOACCESS, SPR_NOACCESS,
1925 spr_read_generic, &spr_write_generic,
1926 0x00000000);
1927 spr_register(env, SPR_USPRG5, "USPRG5",
1928 &spr_read_ureg, SPR_NOACCESS,
1929 &spr_read_ureg, SPR_NOACCESS,
1930 0x00000000);
1931 spr_register(env, SPR_SPRG6, "SPRG6",
1932 SPR_NOACCESS, SPR_NOACCESS,
1933 spr_read_generic, &spr_write_generic,
1934 0x00000000);
1935 spr_register(env, SPR_USPRG6, "USPRG6",
1936 &spr_read_ureg, SPR_NOACCESS,
1937 &spr_read_ureg, SPR_NOACCESS,
1938 0x00000000);
1939 spr_register(env, SPR_SPRG7, "SPRG7",
1940 SPR_NOACCESS, SPR_NOACCESS,
1941 spr_read_generic, &spr_write_generic,
1942 0x00000000);
1943 spr_register(env, SPR_USPRG7, "USPRG7",
1944 &spr_read_ureg, SPR_NOACCESS,
1945 &spr_read_ureg, SPR_NOACCESS,
1946 0x00000000);
1947 }
1948
1949 /* SPR shared between PowerPC 401 & 403 implementations */
1950 static void gen_spr_401_403 (CPUPPCState *env)
1951 {
1952 /* Time base */
1953 spr_register(env, SPR_403_VTBL, "TBL",
1954 &spr_read_tbl, SPR_NOACCESS,
1955 &spr_read_tbl, SPR_NOACCESS,
1956 0x00000000);
1957 spr_register(env, SPR_403_TBL, "TBL",
1958 SPR_NOACCESS, SPR_NOACCESS,
1959 SPR_NOACCESS, &spr_write_tbl,
1960 0x00000000);
1961 spr_register(env, SPR_403_VTBU, "TBU",
1962 &spr_read_tbu, SPR_NOACCESS,
1963 &spr_read_tbu, SPR_NOACCESS,
1964 0x00000000);
1965 spr_register(env, SPR_403_TBU, "TBU",
1966 SPR_NOACCESS, SPR_NOACCESS,
1967 SPR_NOACCESS, &spr_write_tbu,
1968 0x00000000);
1969 /* Debug */
1970 /* not emulated, as Qemu do not emulate caches */
1971 spr_register(env, SPR_403_CDBCR, "CDBCR",
1972 SPR_NOACCESS, SPR_NOACCESS,
1973 &spr_read_generic, &spr_write_generic,
1974 0x00000000);
1975 }
1976
1977 /* SPR specific to PowerPC 401 implementation */
1978 static void gen_spr_401 (CPUPPCState *env)
1979 {
1980 /* Debug interface */
1981 /* XXX : not implemented */
1982 spr_register(env, SPR_40x_DBCR0, "DBCR",
1983 SPR_NOACCESS, SPR_NOACCESS,
1984 &spr_read_generic, &spr_write_40x_dbcr0,
1985 0x00000000);
1986 /* XXX : not implemented */
1987 spr_register(env, SPR_40x_DBSR, "DBSR",
1988 SPR_NOACCESS, SPR_NOACCESS,
1989 &spr_read_generic, &spr_write_clear,
1990 /* Last reset was system reset */
1991 0x00000300);
1992 /* XXX : not implemented */
1993 spr_register(env, SPR_40x_DAC1, "DAC",
1994 SPR_NOACCESS, SPR_NOACCESS,
1995 &spr_read_generic, &spr_write_generic,
1996 0x00000000);
1997 /* XXX : not implemented */
1998 spr_register(env, SPR_40x_IAC1, "IAC",
1999 SPR_NOACCESS, SPR_NOACCESS,
2000 &spr_read_generic, &spr_write_generic,
2001 0x00000000);
2002 /* Storage control */
2003 /* XXX: TODO: not implemented */
2004 spr_register(env, SPR_405_SLER, "SLER",
2005 SPR_NOACCESS, SPR_NOACCESS,
2006 &spr_read_generic, &spr_write_40x_sler,
2007 0x00000000);
2008 /* not emulated, as Qemu never does speculative access */
2009 spr_register(env, SPR_40x_SGR, "SGR",
2010 SPR_NOACCESS, SPR_NOACCESS,
2011 &spr_read_generic, &spr_write_generic,
2012 0xFFFFFFFF);
2013 /* not emulated, as Qemu do not emulate caches */
2014 spr_register(env, SPR_40x_DCWR, "DCWR",
2015 SPR_NOACCESS, SPR_NOACCESS,
2016 &spr_read_generic, &spr_write_generic,
2017 0x00000000);
2018 }
2019
2020 static void gen_spr_401x2 (CPUPPCState *env)
2021 {
2022 gen_spr_401(env);
2023 spr_register(env, SPR_40x_PID, "PID",
2024 SPR_NOACCESS, SPR_NOACCESS,
2025 &spr_read_generic, &spr_write_generic,
2026 0x00000000);
2027 spr_register(env, SPR_40x_ZPR, "ZPR",
2028 SPR_NOACCESS, SPR_NOACCESS,
2029 &spr_read_generic, &spr_write_generic,
2030 0x00000000);
2031 }
2032
2033 /* SPR specific to PowerPC 403 implementation */
2034 static void gen_spr_403 (CPUPPCState *env)
2035 {
2036 /* Debug interface */
2037 /* XXX : not implemented */
2038 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2039 SPR_NOACCESS, SPR_NOACCESS,
2040 &spr_read_generic, &spr_write_40x_dbcr0,
2041 0x00000000);
2042 /* XXX : not implemented */
2043 spr_register(env, SPR_40x_DBSR, "DBSR",
2044 SPR_NOACCESS, SPR_NOACCESS,
2045 &spr_read_generic, &spr_write_clear,
2046 /* Last reset was system reset */
2047 0x00000300);
2048 /* XXX : not implemented */
2049 spr_register(env, SPR_40x_DAC1, "DAC1",
2050 SPR_NOACCESS, SPR_NOACCESS,
2051 &spr_read_generic, &spr_write_generic,
2052 0x00000000);
2053 /* XXX : not implemented */
2054 spr_register(env, SPR_40x_DAC2, "DAC2",
2055 SPR_NOACCESS, SPR_NOACCESS,
2056 &spr_read_generic, &spr_write_generic,
2057 0x00000000);
2058 /* XXX : not implemented */
2059 spr_register(env, SPR_40x_IAC1, "IAC1",
2060 SPR_NOACCESS, SPR_NOACCESS,
2061 &spr_read_generic, &spr_write_generic,
2062 0x00000000);
2063 /* XXX : not implemented */
2064 spr_register(env, SPR_40x_IAC2, "IAC2",
2065 SPR_NOACCESS, SPR_NOACCESS,
2066 &spr_read_generic, &spr_write_generic,
2067 0x00000000);
2068 }
2069
2070 static void gen_spr_403_real (CPUPPCState *env)
2071 {
2072 spr_register(env, SPR_403_PBL1, "PBL1",
2073 SPR_NOACCESS, SPR_NOACCESS,
2074 &spr_read_403_pbr, &spr_write_403_pbr,
2075 0x00000000);
2076 spr_register(env, SPR_403_PBU1, "PBU1",
2077 SPR_NOACCESS, SPR_NOACCESS,
2078 &spr_read_403_pbr, &spr_write_403_pbr,
2079 0x00000000);
2080 spr_register(env, SPR_403_PBL2, "PBL2",
2081 SPR_NOACCESS, SPR_NOACCESS,
2082 &spr_read_403_pbr, &spr_write_403_pbr,
2083 0x00000000);
2084 spr_register(env, SPR_403_PBU2, "PBU2",
2085 SPR_NOACCESS, SPR_NOACCESS,
2086 &spr_read_403_pbr, &spr_write_403_pbr,
2087 0x00000000);
2088 }
2089
2090 static void gen_spr_403_mmu (CPUPPCState *env)
2091 {
2092 /* MMU */
2093 spr_register(env, SPR_40x_PID, "PID",
2094 SPR_NOACCESS, SPR_NOACCESS,
2095 &spr_read_generic, &spr_write_generic,
2096 0x00000000);
2097 spr_register(env, SPR_40x_ZPR, "ZPR",
2098 SPR_NOACCESS, SPR_NOACCESS,
2099 &spr_read_generic, &spr_write_generic,
2100 0x00000000);
2101 }
2102
2103 /* SPR specific to PowerPC compression coprocessor extension */
2104 static void gen_spr_compress (CPUPPCState *env)
2105 {
2106 /* XXX : not implemented */
2107 spr_register(env, SPR_401_SKR, "SKR",
2108 SPR_NOACCESS, SPR_NOACCESS,
2109 &spr_read_generic, &spr_write_generic,
2110 0x00000000);
2111 }
2112
2113 #if defined (TARGET_PPC64)
2114 /* SPR specific to PowerPC 620 */
2115 static void gen_spr_620 (CPUPPCState *env)
2116 {
2117 /* XXX : not implemented */
2118 spr_register(env, SPR_620_PMR0, "PMR0",
2119 SPR_NOACCESS, SPR_NOACCESS,
2120 &spr_read_generic, &spr_write_generic,
2121 0x00000000);
2122 /* XXX : not implemented */
2123 spr_register(env, SPR_620_PMR1, "PMR1",
2124 SPR_NOACCESS, SPR_NOACCESS,
2125 &spr_read_generic, &spr_write_generic,
2126 0x00000000);
2127 /* XXX : not implemented */
2128 spr_register(env, SPR_620_PMR2, "PMR2",
2129 SPR_NOACCESS, SPR_NOACCESS,
2130 &spr_read_generic, &spr_write_generic,
2131 0x00000000);
2132 /* XXX : not implemented */
2133 spr_register(env, SPR_620_PMR3, "PMR3",
2134 SPR_NOACCESS, SPR_NOACCESS,
2135 &spr_read_generic, &spr_write_generic,
2136 0x00000000);
2137 /* XXX : not implemented */
2138 spr_register(env, SPR_620_PMR4, "PMR4",
2139 SPR_NOACCESS, SPR_NOACCESS,
2140 &spr_read_generic, &spr_write_generic,
2141 0x00000000);
2142 /* XXX : not implemented */
2143 spr_register(env, SPR_620_PMR5, "PMR5",
2144 SPR_NOACCESS, SPR_NOACCESS,
2145 &spr_read_generic, &spr_write_generic,
2146 0x00000000);
2147 /* XXX : not implemented */
2148 spr_register(env, SPR_620_PMR6, "PMR6",
2149 SPR_NOACCESS, SPR_NOACCESS,
2150 &spr_read_generic, &spr_write_generic,
2151 0x00000000);
2152 /* XXX : not implemented */
2153 spr_register(env, SPR_620_PMR7, "PMR7",
2154 SPR_NOACCESS, SPR_NOACCESS,
2155 &spr_read_generic, &spr_write_generic,
2156 0x00000000);
2157 /* XXX : not implemented */
2158 spr_register(env, SPR_620_PMR8, "PMR8",
2159 SPR_NOACCESS, SPR_NOACCESS,
2160 &spr_read_generic, &spr_write_generic,
2161 0x00000000);
2162 /* XXX : not implemented */
2163 spr_register(env, SPR_620_PMR9, "PMR9",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 &spr_read_generic, &spr_write_generic,
2166 0x00000000);
2167 /* XXX : not implemented */
2168 spr_register(env, SPR_620_PMRA, "PMR10",
2169 SPR_NOACCESS, SPR_NOACCESS,
2170 &spr_read_generic, &spr_write_generic,
2171 0x00000000);
2172 /* XXX : not implemented */
2173 spr_register(env, SPR_620_PMRB, "PMR11",
2174 SPR_NOACCESS, SPR_NOACCESS,
2175 &spr_read_generic, &spr_write_generic,
2176 0x00000000);
2177 /* XXX : not implemented */
2178 spr_register(env, SPR_620_PMRC, "PMR12",
2179 SPR_NOACCESS, SPR_NOACCESS,
2180 &spr_read_generic, &spr_write_generic,
2181 0x00000000);
2182 /* XXX : not implemented */
2183 spr_register(env, SPR_620_PMRD, "PMR13",
2184 SPR_NOACCESS, SPR_NOACCESS,
2185 &spr_read_generic, &spr_write_generic,
2186 0x00000000);
2187 /* XXX : not implemented */
2188 spr_register(env, SPR_620_PMRE, "PMR14",
2189 SPR_NOACCESS, SPR_NOACCESS,
2190 &spr_read_generic, &spr_write_generic,
2191 0x00000000);
2192 /* XXX : not implemented */
2193 spr_register(env, SPR_620_PMRF, "PMR15",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 &spr_read_generic, &spr_write_generic,
2196 0x00000000);
2197 /* XXX : not implemented */
2198 spr_register(env, SPR_620_HID8, "HID8",
2199 SPR_NOACCESS, SPR_NOACCESS,
2200 &spr_read_generic, &spr_write_generic,
2201 0x00000000);
2202 /* XXX : not implemented */
2203 spr_register(env, SPR_620_HID9, "HID9",
2204 SPR_NOACCESS, SPR_NOACCESS,
2205 &spr_read_generic, &spr_write_generic,
2206 0x00000000);
2207 }
2208 #endif /* defined (TARGET_PPC64) */
2209
2210 // XXX: TODO
2211 /*
2212 * AMR => SPR 29 (Power 2.04)
2213 * CTRL => SPR 136 (Power 2.04)
2214 * CTRL => SPR 152 (Power 2.04)
2215 * SCOMC => SPR 276 (64 bits ?)
2216 * SCOMD => SPR 277 (64 bits ?)
2217 * TBU40 => SPR 286 (Power 2.04 hypv)
2218 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2219 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2220 * HDSISR => SPR 306 (Power 2.04 hypv)
2221 * HDAR => SPR 307 (Power 2.04 hypv)
2222 * PURR => SPR 309 (Power 2.04 hypv)
2223 * HDEC => SPR 310 (Power 2.04 hypv)
2224 * HIOR => SPR 311 (hypv)
2225 * RMOR => SPR 312 (970)
2226 * HRMOR => SPR 313 (Power 2.04 hypv)
2227 * HSRR0 => SPR 314 (Power 2.04 hypv)
2228 * HSRR1 => SPR 315 (Power 2.04 hypv)
2229 * LPCR => SPR 316 (970)
2230 * LPIDR => SPR 317 (970)
2231 * SPEFSCR => SPR 512 (Power 2.04 emb)
2232 * EPR => SPR 702 (Power 2.04 emb)
2233 * perf => 768-783 (Power 2.04)
2234 * perf => 784-799 (Power 2.04)
2235 * PPR => SPR 896 (Power 2.04)
2236 * EPLC => SPR 947 (Power 2.04 emb)
2237 * EPSC => SPR 948 (Power 2.04 emb)
2238 * DABRX => 1015 (Power 2.04 hypv)
2239 * FPECR => SPR 1022 (?)
2240 * ... and more (thermal management, performance counters, ...)
2241 */
2242
2243 /*****************************************************************************/
2244 /* Exception vectors models */
2245 static void init_excp_4xx_real (CPUPPCState *env)
2246 {
2247 #if !defined(CONFIG_USER_ONLY)
2248 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2249 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2250 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2251 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2252 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2253 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2254 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2255 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2256 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2257 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2258 env->excp_prefix = 0x00000000UL;
2259 env->ivor_mask = 0x0000FFF0UL;
2260 env->ivpr_mask = 0xFFFF0000UL;
2261 /* Hardware reset vector */
2262 env->hreset_vector = 0xFFFFFFFCUL;
2263 #endif
2264 }
2265
2266 static void init_excp_4xx_softmmu (CPUPPCState *env)
2267 {
2268 #if !defined(CONFIG_USER_ONLY)
2269 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2270 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2271 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2272 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2273 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2274 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2275 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2276 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2277 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2278 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2279 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2280 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2281 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2282 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2283 env->excp_prefix = 0x00000000UL;
2284 env->ivor_mask = 0x0000FFF0UL;
2285 env->ivpr_mask = 0xFFFF0000UL;
2286 /* Hardware reset vector */
2287 env->hreset_vector = 0xFFFFFFFCUL;
2288 #endif
2289 }
2290
2291 static void init_excp_BookE (CPUPPCState *env)
2292 {
2293 #if !defined(CONFIG_USER_ONLY)
2294 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2295 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2296 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2297 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2298 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2299 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2300 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2301 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2302 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2303 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2304 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2305 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2306 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2307 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2308 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2309 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2310 env->excp_prefix = 0x00000000UL;
2311 env->ivor_mask = 0x0000FFE0UL;
2312 env->ivpr_mask = 0xFFFF0000UL;
2313 /* Hardware reset vector */
2314 env->hreset_vector = 0xFFFFFFFCUL;
2315 #endif
2316 }
2317
2318 static void init_excp_601 (CPUPPCState *env)
2319 {
2320 #if !defined(CONFIG_USER_ONLY)
2321 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2322 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2323 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2324 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2325 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2326 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2327 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2328 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2329 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2330 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2331 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2332 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2333 env->excp_prefix = 0xFFF00000UL;
2334 /* Hardware reset vector */
2335 env->hreset_vector = 0x00000100UL;
2336 #endif
2337 }
2338
2339 static void init_excp_602 (CPUPPCState *env)
2340 {
2341 #if !defined(CONFIG_USER_ONLY)
2342 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2343 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2344 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2345 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2346 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2347 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2348 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2349 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2350 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2351 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2352 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2353 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2354 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2355 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2356 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2357 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2358 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2359 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2360 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2361 env->excp_prefix = 0xFFF00000UL;
2362 /* Hardware reset vector */
2363 env->hreset_vector = 0xFFFFFFFCUL;
2364 #endif
2365 }
2366
2367 static void init_excp_603 (CPUPPCState *env)
2368 {
2369 #if !defined(CONFIG_USER_ONLY)
2370 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2371 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2372 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2373 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2374 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2375 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2376 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2377 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2378 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2379 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2380 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2381 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2382 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2383 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2384 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2385 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2386 env->excp_prefix = 0x00000000UL;
2387 /* Hardware reset vector */
2388 env->hreset_vector = 0xFFFFFFFCUL;
2389 #endif
2390 }
2391
2392 static void init_excp_G2 (CPUPPCState *env)
2393 {
2394 #if !defined(CONFIG_USER_ONLY)
2395 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2396 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2397 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2398 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2399 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2400 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2401 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2402 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2403 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2404 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2405 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2406 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2407 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2408 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2409 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2410 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2411 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2412 env->excp_prefix = 0x00000000UL;
2413 /* Hardware reset vector */
2414 env->hreset_vector = 0xFFFFFFFCUL;
2415 #endif
2416 }
2417
2418 static void init_excp_604 (CPUPPCState *env)
2419 {
2420 #if !defined(CONFIG_USER_ONLY)
2421 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2422 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2423 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2424 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2425 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2426 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2427 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2428 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2429 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2430 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2431 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2432 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2433 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2434 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2435 env->excp_prefix = 0x00000000UL;
2436 /* Hardware reset vector */
2437 env->hreset_vector = 0xFFFFFFFCUL;
2438 #endif
2439 }
2440
2441 #if defined(TARGET_PPC64)
2442 static void init_excp_620 (CPUPPCState *env)
2443 {
2444 #if !defined(CONFIG_USER_ONLY)
2445 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2446 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2447 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2448 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2449 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2450 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2451 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2452 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2453 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2454 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2455 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2456 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2457 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2458 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2459 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2460 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2461 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2462 env->excp_prefix = 0xFFF00000UL;
2463 /* Hardware reset vector */
2464 env->hreset_vector = 0x0000000000000100ULL;
2465 #endif
2466 }
2467 #endif /* defined(TARGET_PPC64) */
2468
2469 static void init_excp_7x0 (CPUPPCState *env)
2470 {
2471 #if !defined(CONFIG_USER_ONLY)
2472 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2473 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2474 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2475 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2476 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2477 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2478 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2479 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2480 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2481 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2482 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2483 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2484 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2485 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2486 env->excp_prefix = 0x00000000UL;
2487 /* Hardware reset vector */
2488 env->hreset_vector = 0xFFFFFFFCUL;
2489 #endif
2490 }
2491
2492 static void init_excp_750FX (CPUPPCState *env)
2493 {
2494 #if !defined(CONFIG_USER_ONLY)
2495 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2496 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2497 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2498 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2499 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2500 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2501 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2502 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2503 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2504 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2505 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2506 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2507 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2508 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2509 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2510 env->excp_prefix = 0x00000000UL;
2511 /* Hardware reset vector */
2512 env->hreset_vector = 0xFFFFFFFCUL;
2513 #endif
2514 }
2515
2516 /* XXX: Check if this is correct */
2517 static void init_excp_7x5 (CPUPPCState *env)
2518 {
2519 #if !defined(CONFIG_USER_ONLY)
2520 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2521 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2522 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2523 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2524 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2525 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2526 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2527 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2528 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2529 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2530 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2531 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2532 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2533 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2534 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2535 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2536 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2537 env->excp_prefix = 0x00000000UL;
2538 /* Hardware reset vector */
2539 env->hreset_vector = 0xFFFFFFFCUL;
2540 #endif
2541 }
2542
2543 static void init_excp_7400 (CPUPPCState *env)
2544 {
2545 #if !defined(CONFIG_USER_ONLY)
2546 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2547 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2548 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2549 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2550 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2551 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2552 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2553 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2554 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2555 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2556 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2557 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2558 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2559 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2560 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2561 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2562 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2563 env->excp_prefix = 0x00000000UL;
2564 /* Hardware reset vector */
2565 env->hreset_vector = 0xFFFFFFFCUL;
2566 #endif
2567 }
2568
2569 static void init_excp_7450 (CPUPPCState *env)
2570 {
2571 #if !defined(CONFIG_USER_ONLY)
2572 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2573 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2574 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2575 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2576 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2577 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2578 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2579 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2580 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2581 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2582 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2583 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2584 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2585 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2586 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2587 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2588 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2589 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2590 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2591 env->excp_prefix = 0x00000000UL;
2592 /* Hardware reset vector */
2593 env->hreset_vector = 0xFFFFFFFCUL;
2594 #endif
2595 }
2596
2597 #if defined (TARGET_PPC64)
2598 static void init_excp_970 (CPUPPCState *env)
2599 {
2600 #if !defined(CONFIG_USER_ONLY)
2601 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2602 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2603 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2604 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2605 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2606 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2607 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2608 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2609 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2610 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2611 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2612 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2613 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2614 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2615 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2616 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2617 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2618 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2619 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2620 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2621 env->excp_prefix = 0x00000000FFF00000ULL;
2622 /* Hardware reset vector */
2623 env->hreset_vector = 0x0000000000000100ULL;
2624 #endif
2625 }
2626 #endif
2627
2628 /*****************************************************************************/
2629 /* Power management enable checks */
2630 static int check_pow_none (CPUPPCState *env)
2631 {
2632 return 0;
2633 }
2634
2635 static int check_pow_nocheck (CPUPPCState *env)
2636 {
2637 return 1;
2638 }
2639
2640 static int check_pow_hid0 (CPUPPCState *env)
2641 {
2642 if (env->spr[SPR_HID0] & 0x00E00000)
2643 return 1;
2644
2645 return 0;
2646 }
2647
2648 /*****************************************************************************/
2649 /* PowerPC implementations definitions */
2650
2651 /* PowerPC 40x instruction set */
2652 #define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_EMB_COMMON | \
2653 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ)
2654
2655 /* PowerPC 401 */
2656 #define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \
2657 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2658 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2659 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
2660 #define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx)
2661 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
2662 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
2663 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
2664 #define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2665 #define check_pow_401 check_pow_nocheck
2666
2667 static void init_proc_401 (CPUPPCState *env)
2668 {
2669 gen_spr_40x(env);
2670 gen_spr_401_403(env);
2671 gen_spr_401(env);
2672 init_excp_4xx_real(env);
2673 env->dcache_line_size = 32;
2674 env->icache_line_size = 32;
2675 /* Allocate hardware IRQ controller */
2676 ppc40x_irq_init(env);
2677 }
2678
2679 /* PowerPC 401x2 */
2680 #define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | \
2681 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2682 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2683 PPC_CACHE_DCBA | PPC_MFTB | \
2684 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2685 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
2686 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
2687 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
2688 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
2689 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
2690 #define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2691 #define check_pow_401x2 check_pow_nocheck
2692
2693 static void init_proc_401x2 (CPUPPCState *env)
2694 {
2695 gen_spr_40x(env);
2696 gen_spr_401_403(env);
2697 gen_spr_401x2(env);
2698 gen_spr_compress(env);
2699 /* Memory management */
2700 #if !defined(CONFIG_USER_ONLY)
2701 env->nb_tlb = 64;
2702 env->nb_ways = 1;
2703 env->id_tlbs = 0;
2704 #endif
2705 init_excp_4xx_softmmu(env);
2706 env->dcache_line_size = 32;
2707 env->icache_line_size = 32;
2708 /* Allocate hardware IRQ controller */
2709 ppc40x_irq_init(env);
2710 }
2711
2712 /* PowerPC 401x3 */
2713 #define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \
2714 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2715 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2716 PPC_CACHE_DCBA | PPC_MFTB | \
2717 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2718 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
2719 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
2720 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
2721 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
2722 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
2723 #define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2724 #define check_pow_401x3 check_pow_nocheck
2725
2726 __attribute__ (( unused ))
2727 static void init_proc_401x3 (CPUPPCState *env)
2728 {
2729 gen_spr_40x(env);
2730 gen_spr_401_403(env);
2731 gen_spr_401(env);
2732 gen_spr_401x2(env);
2733 gen_spr_compress(env);
2734 init_excp_4xx_softmmu(env);
2735 env->dcache_line_size = 32;
2736 env->icache_line_size = 32;
2737 /* Allocate hardware IRQ controller */
2738 ppc40x_irq_init(env);
2739 }
2740
2741 /* IOP480 */
2742 #define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \
2743 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2744 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2745 PPC_CACHE_DCBA | \
2746 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2747 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
2748 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
2749 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
2750 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
2751 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
2752 #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2753 #define check_pow_IOP480 check_pow_nocheck
2754
2755 static void init_proc_IOP480 (CPUPPCState *env)
2756 {
2757 gen_spr_40x(env);
2758 gen_spr_401_403(env);
2759 gen_spr_401x2(env);
2760 gen_spr_compress(env);
2761 /* Memory management */
2762 #if !defined(CONFIG_USER_ONLY)
2763 env->nb_tlb = 64;
2764 env->nb_ways = 1;
2765 env->id_tlbs = 0;
2766 #endif
2767 init_excp_4xx_softmmu(env);
2768 env->dcache_line_size = 32;
2769 env->icache_line_size = 32;
2770 /* Allocate hardware IRQ controller */
2771 ppc40x_irq_init(env);
2772 }
2773
2774 /* PowerPC 403 */
2775 #define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | \
2776 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2777 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2778 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
2779 #define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx)
2780 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
2781 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
2782 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
2783 #define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2784 #define check_pow_403 check_pow_nocheck
2785
2786 static void init_proc_403 (CPUPPCState *env)
2787 {
2788 gen_spr_40x(env);
2789 gen_spr_401_403(env);
2790 gen_spr_403(env);
2791 gen_spr_403_real(env);
2792 init_excp_4xx_real(env);
2793 env->dcache_line_size = 32;
2794 env->icache_line_size = 32;
2795 /* Allocate hardware IRQ controller */
2796 ppc40x_irq_init(env);
2797 #if !defined(CONFIG_USER_ONLY)
2798 /* Hardware reset vector */
2799 env->hreset_vector = 0xFFFFFFFCUL;
2800 #endif
2801 }
2802
2803 /* PowerPC 403 GCX */
2804 #define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | \
2805 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2806 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2807 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2808 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
2809 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
2810 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
2811 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
2812 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
2813 #define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2814 #define check_pow_403GCX check_pow_nocheck
2815
2816 static void init_proc_403GCX (CPUPPCState *env)
2817 {
2818 gen_spr_40x(env);
2819 gen_spr_401_403(env);
2820 gen_spr_403(env);
2821 gen_spr_403_real(env);
2822 gen_spr_403_mmu(env);
2823 /* Bus access control */
2824 /* not emulated, as Qemu never does speculative access */
2825 spr_register(env, SPR_40x_SGR, "SGR",
2826 SPR_NOACCESS, SPR_NOACCESS,
2827 &spr_read_generic, &spr_write_generic,
2828 0xFFFFFFFF);
2829 /* not emulated, as Qemu do not emulate caches */
2830 spr_register(env, SPR_40x_DCWR, "DCWR",
2831 SPR_NOACCESS, SPR_NOACCESS,
2832 &spr_read_generic, &spr_write_generic,
2833 0x00000000);
2834 /* Memory management */
2835 #if !defined(CONFIG_USER_ONLY)
2836 env->nb_tlb = 64;
2837 env->nb_ways = 1;
2838 env->id_tlbs = 0;
2839 #endif
2840 init_excp_4xx_softmmu(env);
2841 env->dcache_line_size = 32;
2842 env->icache_line_size = 32;
2843 /* Allocate hardware IRQ controller */
2844 ppc40x_irq_init(env);
2845 }
2846
2847 /* PowerPC 405 */
2848 #define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_MFTB | \
2849 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2850 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2851 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
2852 PPC_405_MAC)
2853 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
2854 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
2855 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
2856 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
2857 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
2858 #define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2859 POWERPC_FLAG_DE)
2860 #define check_pow_405 check_pow_nocheck
2861
2862 static void init_proc_405 (CPUPPCState *env)
2863 {
2864 /* Time base */
2865 gen_tbl(env);
2866 gen_spr_40x(env);
2867 gen_spr_405(env);
2868 /* Bus access control */
2869 /* not emulated, as Qemu never does speculative access */
2870 spr_register(env, SPR_40x_SGR, "SGR",
2871 SPR_NOACCESS, SPR_NOACCESS,
2872 &spr_read_generic, &spr_write_generic,
2873 0xFFFFFFFF);
2874 /* not emulated, as Qemu do not emulate caches */
2875 spr_register(env, SPR_40x_DCWR, "DCWR",
2876 SPR_NOACCESS, SPR_NOACCESS,
2877 &spr_read_generic, &spr_write_generic,
2878 0x00000000);
2879 /* Memory management */
2880 #if !defined(CONFIG_USER_ONLY)
2881 env->nb_tlb = 64;
2882 env->nb_ways = 1;
2883 env->id_tlbs = 0;
2884 #endif
2885 init_excp_4xx_softmmu(env);
2886 env->dcache_line_size = 32;
2887 env->icache_line_size = 32;
2888 /* Allocate hardware IRQ controller */
2889 ppc40x_irq_init(env);
2890 }
2891
2892 /* PowerPC 440 EP */
2893 #define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | \
2894 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2895 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2896 PPC_440_SPEC | PPC_RFMCI)
2897 #define POWERPC_MSRM_440EP (0x000000000006D630ULL)
2898 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
2899 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
2900 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
2901 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
2902 #define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2903 POWERPC_FLAG_DE)
2904 #define check_pow_440EP check_pow_nocheck
2905
2906 static void init_proc_440EP (CPUPPCState *env)
2907 {
2908 /* Time base */
2909 gen_tbl(env);
2910 gen_spr_BookE(env);
2911 gen_spr_440(env);
2912 /* XXX : not implemented */
2913 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2914 SPR_NOACCESS, SPR_NOACCESS,
2915 &spr_read_generic, &spr_write_generic,
2916 0x00000000);
2917 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2918 SPR_NOACCESS, SPR_NOACCESS,
2919 &spr_read_generic, &spr_write_generic,
2920 0x00000000);
2921 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2922 SPR_NOACCESS, SPR_NOACCESS,
2923 &spr_read_generic, &spr_write_generic,
2924 0x00000000);
2925 /* XXX : not implemented */
2926 spr_register(env, SPR_440_CCR1, "CCR1",
2927 SPR_NOACCESS, SPR_NOACCESS,
2928 &spr_read_generic, &spr_write_generic,
2929 0x00000000);
2930 /* Memory management */
2931 #if !defined(CONFIG_USER_ONLY)
2932 env->nb_tlb = 64;
2933 env->nb_ways = 1;
2934 env->id_tlbs = 0;
2935 #endif
2936 init_excp_BookE(env);
2937 env->dcache_line_size = 32;
2938 env->icache_line_size = 32;
2939 /* XXX: TODO: allocate internal IRQ controller */
2940 }
2941
2942 /* PowerPC 440 GP */
2943 #define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | \
2944 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2945 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2946 PPC_405_MAC | PPC_440_SPEC)
2947 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
2948 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
2949 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
2950 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
2951 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
2952 #define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2953 POWERPC_FLAG_DE)
2954 #define check_pow_440GP check_pow_nocheck
2955
2956 static void init_proc_440GP (CPUPPCState *env)
2957 {
2958 /* Time base */
2959 gen_tbl(env);
2960 gen_spr_BookE(env);
2961 gen_spr_440(env);
2962 /* Memory management */
2963 #if !defined(CONFIG_USER_ONLY)
2964 env->nb_tlb = 64;
2965 env->nb_ways = 1;
2966 env->id_tlbs = 0;
2967 #endif
2968 init_excp_BookE(env);
2969 env->dcache_line_size = 32;
2970 env->icache_line_size = 32;
2971 /* XXX: TODO: allocate internal IRQ controller */
2972 }
2973
2974 /* PowerPC 440x4 */
2975 #define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \
2976 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2977 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2978 PPC_440_SPEC)
2979 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
2980 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
2981 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
2982 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
2983 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
2984 #define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2985 POWERPC_FLAG_DE)
2986 #define check_pow_440x4 check_pow_nocheck
2987
2988 __attribute__ (( unused ))
2989 static void init_proc_440x4 (CPUPPCState *env)
2990 {
2991 /* Time base */
2992 gen_tbl(env);
2993 gen_spr_BookE(env);
2994 gen_spr_440(env);
2995 /* Memory management */
2996 #if !defined(CONFIG_USER_ONLY)
2997 env->nb_tlb = 64;
2998 env->nb_ways = 1;
2999 env->id_tlbs = 0;
3000 #endif
3001 init_excp_BookE(env);
3002 env->dcache_line_size = 32;
3003 env->icache_line_size = 32;
3004 /* XXX: TODO: allocate internal IRQ controller */
3005 }
3006
3007 /* PowerPC 440x5 */
3008 #define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \
3009 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3010 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3011 PPC_440_SPEC | PPC_RFMCI)
3012 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3013 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3014 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3015 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3016 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3017 #define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3018 POWERPC_FLAG_DE)
3019 #define check_pow_440x5 check_pow_nocheck
3020
3021 static void init_proc_440x5 (CPUPPCState *env)
3022 {
3023 /* Time base */
3024 gen_tbl(env);
3025 gen_spr_BookE(env);
3026 gen_spr_440(env);
3027 /* XXX : not implemented */
3028 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3029 SPR_NOACCESS, SPR_NOACCESS,
3030 &spr_read_generic, &spr_write_generic,
3031 0x00000000);
3032 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3033 SPR_NOACCESS, SPR_NOACCESS,
3034 &spr_read_generic, &spr_write_generic,
3035 0x00000000);
3036 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3037 SPR_NOACCESS, SPR_NOACCESS,
3038 &spr_read_generic, &spr_write_generic,
3039 0x00000000);
3040 /* XXX : not implemented */
3041 spr_register(env, SPR_440_CCR1, "CCR1",
3042 SPR_NOACCESS, SPR_NOACCESS,
3043 &spr_read_generic, &spr_write_generic,
3044 0x00000000);
3045 /* Memory management */
3046 #if !defined(CONFIG_USER_ONLY)
3047 env->nb_tlb = 64;
3048 env->nb_ways = 1;
3049 env->id_tlbs = 0;
3050 #endif
3051 init_excp_BookE(env);
3052 env->dcache_line_size = 32;
3053 env->icache_line_size = 32;
3054 /* XXX: TODO: allocate internal IRQ controller */
3055 }
3056
3057 /* PowerPC 460 (guessed) */
3058 #define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | \
3059 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3060 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
3061 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3062 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3063 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3064 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3065 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3066 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3067 #define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3068 POWERPC_FLAG_DE)
3069 #define check_pow_460 check_pow_nocheck
3070
3071 __attribute__ (( unused ))
3072 static void init_proc_460 (CPUPPCState *env)
3073 {
3074 /* Time base */
3075 gen_tbl(env);
3076 gen_spr_BookE(env);
3077 gen_spr_440(env);
3078 /* XXX : not implemented */
3079 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3080 SPR_NOACCESS, SPR_NOACCESS,
3081 &spr_read_generic, &spr_write_generic,
3082 0x00000000);
3083 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3084 SPR_NOACCESS, SPR_NOACCESS,
3085 &spr_read_generic, &spr_write_generic,
3086 0x00000000);
3087 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3088 SPR_NOACCESS, SPR_NOACCESS,
3089 &spr_read_generic, &spr_write_generic,
3090 0x00000000);
3091 /* XXX : not implemented */
3092 spr_register(env, SPR_440_CCR1, "CCR1",
3093 SPR_NOACCESS, SPR_NOACCESS,
3094 &spr_read_generic, &spr_write_generic,
3095 0x00000000);
3096 /* XXX : not implemented */
3097 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3098 &spr_read_generic, &spr_write_generic,
3099 &spr_read_generic, &spr_write_generic,
3100 0x00000000);
3101 /* Memory management */
3102 #if !defined(CONFIG_USER_ONLY)
3103 env->nb_tlb = 64;
3104 env->nb_ways = 1;
3105 env->id_tlbs = 0;
3106 #endif
3107 init_excp_BookE(env);
3108 env->dcache_line_size = 32;
3109 env->icache_line_size = 32;
3110 /* XXX: TODO: allocate internal IRQ controller */
3111 }
3112
3113 /* PowerPC 460F (guessed) */
3114 #define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
3115 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3116 PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
3117 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
3118 PPC_FLOAT_STFIWX | \
3119 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
3120 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3121 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3122 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3123 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3124 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3125 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3126 #define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3127 POWERPC_FLAG_DE)
3128 #define check_pow_460F check_pow_nocheck
3129
3130 __attribute__ (( unused ))
3131 static void init_proc_460F (CPUPPCState *env)
3132 {
3133 /* Time base */
3134 gen_tbl(env);
3135 gen_spr_BookE(env);
3136 gen_spr_440(env);
3137 /* XXX : not implemented */
3138 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3139 SPR_NOACCESS, SPR_NOACCESS,
3140 &spr_read_generic, &spr_write_generic,
3141 0x00000000);
3142 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3143 SPR_NOACCESS, SPR_NOACCESS,
3144 &spr_read_generic, &spr_write_generic,
3145 0x00000000);
3146 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3147 SPR_NOACCESS, SPR_NOACCESS,
3148 &spr_read_generic, &spr_write_generic,
3149 0x00000000);
3150 /* XXX : not implemented */
3151 spr_register(env, SPR_440_CCR1, "CCR1",
3152 SPR_NOACCESS, SPR_NOACCESS,
3153 &spr_read_generic, &spr_write_generic,
3154 0x00000000);
3155 /* XXX : not implemented */
3156 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3157 &spr_read_generic, &spr_write_generic,
3158 &spr_read_generic, &spr_write_generic,
3159 0x00000000);
3160 /* Memory management */
3161 #if !defined(CONFIG_USER_ONLY)
3162 env->nb_tlb = 64;
3163 env->nb_ways = 1;
3164 env->id_tlbs = 0;
3165 #endif
3166 init_excp_BookE(env);
3167 env->dcache_line_size = 32;
3168 env->icache_line_size = 32;
3169 /* XXX: TODO: allocate internal IRQ controller */
3170 }
3171
3172 /* Generic BookE PowerPC */
3173 #define POWERPC_INSNS_BookE (POWERPC_INSNS_EMB | \
3174 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3175 PPC_CACHE_DCBA | \
3176 PPC_FLOAT | PPC_FLOAT_FSQRT | \
3177 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3178 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3179 PPC_BOOKE)
3180 #define POWERPC_MSRM_BookE (0x000000000006D630ULL)
3181 #define POWERPC_MMU_BookE (POWERPC_MMU_BOOKE)
3182 #define POWERPC_EXCP_BookE (POWERPC_EXCP_BOOKE)
3183 #define POWERPC_INPUT_BookE (PPC_FLAGS_INPUT_BookE)
3184 #define POWERPC_BFDM_BookE (bfd_mach_ppc_403)
3185 #define POWERPC_FLAG_BookE (POWERPC_FLAG_NONE)
3186 #define check_pow_BookE check_pow_nocheck
3187
3188 __attribute__ (( unused ))
3189 static void init_proc_BookE (CPUPPCState *env)
3190 {
3191 init_excp_BookE(env);
3192 env->dcache_line_size = 32;
3193 env->icache_line_size = 32;
3194 }
3195
3196 /* e200 core */
3197
3198 /* e300 core */
3199
3200 /* e500 core */
3201 #define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | \
3202 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3203 PPC_CACHE_DCBA | \
3204 PPC_BOOKE | PPC_E500_VECTOR)
3205 #define POWERPC_MMU_e500 (POWERPC_MMU_SOFT_4xx)
3206 #define POWERPC_EXCP_e500 (POWERPC_EXCP_40x)
3207 #define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
3208 #define POWERPC_BFDM_e500 (bfd_mach_ppc_403)
3209 #define POWERPC_FLAG_e500 (POWERPC_FLAG_SPE)
3210 #define check_pow_e500 check_pow_hid0
3211
3212 __attribute__ (( unused ))
3213 static void init_proc_e500 (CPUPPCState *env)
3214 {
3215 /* Time base */
3216 gen_tbl(env);
3217 gen_spr_BookE(env);
3218 /* Memory management */
3219 gen_spr_BookE_FSL(env);
3220 #if !defined(CONFIG_USER_ONLY)
3221 env->nb_tlb = 64;
3222 env->nb_ways = 1;
3223 env->id_tlbs = 0;
3224 #endif
3225 init_excp_BookE(env);
3226 env->dcache_line_size = 32;
3227 env->icache_line_size = 32;
3228 /* XXX: TODO: allocate internal IRQ controller */
3229 }
3230
3231 /* e600 core */
3232
3233 /* Non-embedded PowerPC */
3234 /* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
3235 #define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_FLOAT | \
3236 PPC_CACHE | PPC_CACHE_ICBI | \
3237 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE)
3238 /* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
3239 #define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
3240 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3241 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3242 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB | \
3243 PPC_SEGMENT)
3244
3245 /* POWER : same as 601, without mfmsr, mfsr */
3246 #if defined(TODO)
3247 #define POWERPC_INSNS_POWER (XXX_TODO)
3248 /* POWER RSC (from RAD6000) */
3249 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
3250 #endif /* TODO */
3251
3252 /* PowerPC 601 */
3253 #define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ | \
3254 PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
3255 #define POWERPC_MSRM_601 (0x000000000000FD70ULL)
3256 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
3257 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
3258 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
3259 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
3260 #define POWERPC_FLAG_601 (POWERPC_FLAG_SE)
3261 #define check_pow_601 check_pow_none
3262
3263 static void init_proc_601 (CPUPPCState *env)
3264 {
3265 gen_spr_ne_601(env);
3266 gen_spr_601(env);
3267 /* Hardware implementation registers */
3268 /* XXX : not implemented */
3269 spr_register(env, SPR_HID0, "HID0",
3270 SPR_NOACCESS, SPR_NOACCESS,
3271 &spr_read_generic, &spr_write_hid0_601,
3272 0x80010080);
3273 /* XXX : not implemented */
3274 spr_register(env, SPR_HID1, "HID1",
3275 SPR_NOACCESS, SPR_NOACCESS,
3276 &spr_read_generic, &spr_write_generic,
3277 0x00000000);
3278 /* XXX : not implemented */
3279 spr_register(env, SPR_601_HID2, "HID2",
3280 SPR_NOACCESS, SPR_NOACCESS,
3281 &spr_read_generic, &spr_write_generic,
3282 0x00000000);
3283 /* XXX : not implemented */
3284 spr_register(env, SPR_601_HID5, "HID5",
3285 SPR_NOACCESS, SPR_NOACCESS,
3286 &spr_read_generic, &spr_write_generic,
3287 0x00000000);
3288 /* XXX : not implemented */
3289 spr_register(env, SPR_601_HID15, "HID15",
3290 SPR_NOACCESS, SPR_NOACCESS,
3291 &spr_read_generic, &spr_write_generic,
3292 0x00000000);
3293 /* Memory management */
3294 #if !defined(CONFIG_USER_ONLY)
3295 env->nb_tlb = 64;
3296 env->nb_ways = 2;
3297 env->id_tlbs = 0;
3298 #endif
3299 init_excp_601(env);
3300 env->dcache_line_size = 64;
3301 env->icache_line_size = 64;
3302 /* Allocate hardware IRQ controller */
3303 ppc6xx_irq_init(env);
3304 }
3305
3306 /* PowerPC 602 */
3307 #define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
3308 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3309 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3310 PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\
3311 PPC_SEGMENT | PPC_602_SPEC)
3312 #define POWERPC_MSRM_602 (0x000000000033FF73ULL)
3313 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
3314 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
3315 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
3316 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
3317 #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3318 POWERPC_FLAG_BE)
3319 #define check_pow_602 check_pow_hid0
3320
3321 static void init_proc_602 (CPUPPCState *env)
3322 {
3323 gen_spr_ne_601(env);
3324 gen_spr_602(env);
3325 /* Time base */
3326 gen_tbl(env);
3327 /* hardware implementation registers */
3328 /* XXX : not implemented */
3329 spr_register(env, SPR_HID0, "HID0",
3330 SPR_NOACCESS, SPR_NOACCESS,
3331 &spr_read_generic, &spr_write_generic,
3332 0x00000000);
3333 /* XXX : not implemented */
3334 spr_register(env, SPR_HID1, "HID1",
3335 SPR_NOACCESS, SPR_NOACCESS,
3336 &spr_read_generic, &spr_write_generic,
3337 0x00000000);
3338 /* Memory management */
3339 gen_low_BATs(env);
3340 gen_6xx_7xx_soft_tlb(env, 64, 2);
3341 init_excp_602(env);
3342 env->dcache_line_size = 32;
3343 env->icache_line_size = 32;
3344 /* Allocate hardware IRQ controller */
3345 ppc6xx_irq_init(env);
3346 }
3347
3348 /* PowerPC 603 */
3349 #define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3350 #define POWERPC_MSRM_603 (0x000000000007FF73ULL)
3351 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
3352 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
3353 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
3354 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
3355 #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3356 POWERPC_FLAG_BE)
3357 #define check_pow_603 check_pow_hid0
3358
3359 static void init_proc_603 (CPUPPCState *env)
3360 {
3361 gen_spr_ne_601(env);
3362 gen_spr_603(env);
3363 /* Time base */
3364 gen_tbl(env);
3365 /* hardware implementation registers */
3366 /* XXX : not implemented */
3367 spr_register(env, SPR_HID0, "HID0",
3368 SPR_NOACCESS, SPR_NOACCESS,
3369 &spr_read_generic, &spr_write_generic,
3370 0x00000000);
3371 /* XXX : not implemented */
3372 spr_register(env, SPR_HID1, "HID1",
3373 SPR_NOACCESS, SPR_NOACCESS,
3374 &spr_read_generic, &spr_write_generic,
3375 0x00000000);
3376 /* Memory management */
3377 gen_low_BATs(env);
3378 gen_6xx_7xx_soft_tlb(env, 64, 2);
3379 init_excp_603(env);
3380 env->dcache_line_size = 32;
3381 env->icache_line_size = 32;
3382 /* Allocate hardware IRQ controller */
3383 ppc6xx_irq_init(env);
3384 }
3385
3386 /* PowerPC 603e */
3387 #define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3388 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
3389 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
3390 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
3391 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
3392 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
3393 #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3394 POWERPC_FLAG_BE)
3395 #define check_pow_603E check_pow_hid0
3396
3397 static void init_proc_603E (CPUPPCState *env)
3398 {
3399 gen_spr_ne_601(env);
3400 gen_spr_603(env);
3401 /* Time base */
3402 gen_tbl(env);
3403 /* hardware implementation registers */
3404 /* XXX : not implemented */
3405 spr_register(env, SPR_HID0, "HID0",
3406 SPR_NOACCESS, SPR_NOACCESS,
3407 &spr_read_generic, &spr_write_generic,
3408 0x00000000);
3409 /* XXX : not implemented */
3410 spr_register(env, SPR_HID1, "HID1",
3411 SPR_NOACCESS, SPR_NOACCESS,
3412 &spr_read_generic, &spr_write_generic,
3413 0x00000000);
3414 /* XXX : not implemented */
3415 spr_register(env, SPR_IABR, "IABR",
3416 SPR_NOACCESS, SPR_NOACCESS,
3417 &spr_read_generic, &spr_write_generic,
3418 0x00000000);
3419 /* Memory management */
3420 gen_low_BATs(env);
3421 gen_6xx_7xx_soft_tlb(env, 64, 2);
3422 init_excp_603(env);
3423 env->dcache_line_size = 32;
3424 env->icache_line_size = 32;
3425 /* Allocate hardware IRQ controller */
3426 ppc6xx_irq_init(env);
3427 }
3428
3429 /* PowerPC G2 */
3430 #define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3431 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3432 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3433 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3434 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3435 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3436 #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3437 POWERPC_FLAG_BE)
3438 #define check_pow_G2 check_pow_hid0
3439
3440 static void init_proc_G2 (CPUPPCState *env)
3441 {
3442 gen_spr_ne_601(env);
3443 gen_spr_G2_755(env);
3444 gen_spr_G2(env);
3445 /* Time base */
3446 gen_tbl(env);
3447 /* Hardware implementation register */
3448 /* XXX : not implemented */
3449 spr_register(env, SPR_HID0, "HID0",
3450 SPR_NOACCESS, SPR_NOACCESS,
3451 &spr_read_generic, &spr_write_generic,
3452 0x00000000);
3453 /* XXX : not implemented */
3454 spr_register(env, SPR_HID1, "HID1",
3455 SPR_NOACCESS, SPR_NOACCESS,
3456 &spr_read_generic, &spr_write_generic,
3457 0x00000000);
3458 /* XXX : not implemented */
3459 spr_register(env, SPR_HID2, "HID2",
3460 SPR_NOACCESS, SPR_NOACCESS,
3461 &spr_read_generic, &spr_write_generic,
3462 0x00000000);
3463 /* Memory management */
3464 gen_low_BATs(env);
3465 gen_high_BATs(env);
3466 gen_6xx_7xx_soft_tlb(env, 64, 2);
3467 init_excp_G2(env);
3468 env->dcache_line_size = 32;
3469 env->icache_line_size = 32;
3470 /* Allocate hardware IRQ controller */
3471 ppc6xx_irq_init(env);
3472 }
3473
3474 /* PowerPC G2LE */
3475 #define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3476 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3477 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3478 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3479 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
3480 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
3481 #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3482 POWERPC_FLAG_BE)
3483 #define check_pow_G2LE check_pow_hid0
3484
3485 static void init_proc_G2LE (CPUPPCState *env)
3486 {
3487 gen_spr_ne_601(env);
3488 gen_spr_G2_755(env);
3489 gen_spr_G2(env);
3490 /* Time base */
3491 gen_tbl(env);
3492 /* Hardware implementation register */
3493 /* XXX : not implemented */
3494 spr_register(env, SPR_HID0, "HID0",
3495 SPR_NOACCESS, SPR_NOACCESS,
3496 &spr_read_generic, &spr_write_generic,
3497 0x00000000);
3498 /* XXX : not implemented */
3499 spr_register(env, SPR_HID1, "HID1",
3500 SPR_NOACCESS, SPR_NOACCESS,
3501 &spr_read_generic, &spr_write_generic,
3502 0x00000000);
3503 /* XXX : not implemented */
3504 spr_register(env, SPR_HID2, "HID2",
3505 SPR_NOACCESS, SPR_NOACCESS,
3506 &spr_read_generic, &spr_write_generic,
3507 0x00000000);
3508 /* Memory management */
3509 gen_low_BATs(env);
3510 gen_high_BATs(env);
3511 gen_6xx_7xx_soft_tlb(env, 64, 2);
3512 init_excp_G2(env);
3513 env->dcache_line_size = 32;
3514 env->icache_line_size = 32;
3515 /* Allocate hardware IRQ controller */
3516 ppc6xx_irq_init(env);
3517 }
3518
3519 /* PowerPC 604 */
3520 #define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3521 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
3522 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
3523 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
3524 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
3525 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
3526 #define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3527 POWERPC_FLAG_PMM)
3528 #define check_pow_604 check_pow_nocheck
3529
3530 static void init_proc_604 (CPUPPCState *env)
3531 {
3532 gen_spr_ne_601(env);
3533 gen_spr_604(env);
3534 /* Time base */
3535 gen_tbl(env);
3536 /* Hardware implementation registers */
3537 /* XXX : not implemented */
3538 spr_register(env, SPR_HID0, "HID0",
3539 SPR_NOACCESS, SPR_NOACCESS,
3540 &spr_read_generic, &spr_write_generic,
3541 0x00000000);
3542 /* XXX : not implemented */
3543 spr_register(env, SPR_HID1, "HID1",
3544 SPR_NOACCESS, SPR_NOACCESS,
3545 &spr_read_generic, &spr_write_generic,
3546 0x00000000);
3547 /* Memory management */
3548 gen_low_BATs(env);
3549 init_excp_604(env);
3550 env->dcache_line_size = 32;
3551 env->icache_line_size = 32;
3552 /* Allocate hardware IRQ controller */
3553 ppc6xx_irq_init(env);
3554 }
3555
3556 /* PowerPC 740/750 (aka G3) */
3557 #define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3558 #define POWERPC_MSRM_7x0 (0x000000000005FF77ULL)
3559 #define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
3560 //#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
3561 #define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
3562 #define POWERPC_BFDM_7x0 (bfd_mach_ppc_750)
3563 #define POWERPC_FLAG_7x0 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3564 POWERPC_FLAG_PMM)
3565 #define check_pow_7x0 check_pow_hid0
3566
3567 static void init_proc_7x0 (CPUPPCState *env)
3568 {
3569 gen_spr_ne_601(env);
3570 gen_spr_7xx(env);
3571 /* Time base */
3572 gen_tbl(env);
3573 /* Thermal management */
3574 gen_spr_thrm(env);
3575 /* Hardware implementation registers */
3576 /* XXX : not implemented */
3577 spr_register(env, SPR_HID0, "HID0",
3578 SPR_NOACCESS, SPR_NOACCESS,
3579 &spr_read_generic, &spr_write_generic,
3580 0x00000000);
3581 /* XXX : not implemented */
3582 spr_register(env, SPR_HID1, "HID1",
3583 SPR_NOACCESS, SPR_NOACCESS,
3584 &spr_read_generic, &spr_write_generic,
3585 0x00000000);
3586 /* Memory management */
3587 gen_low_BATs(env);
3588 init_excp_7x0(env);
3589 env->dcache_line_size = 32;
3590 env->icache_line_size = 32;
3591 /* Allocate hardware IRQ controller */
3592 ppc6xx_irq_init(env);
3593 }
3594
3595 /* PowerPC 750FX/GX */
3596 #define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN)
3597 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
3598 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
3599 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
3600 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
3601 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
3602 #define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3603 POWERPC_FLAG_PMM)
3604 #define check_pow_750fx check_pow_hid0
3605
3606 static void init_proc_750fx (CPUPPCState *env)
3607 {
3608 gen_spr_ne_601(env);
3609 gen_spr_7xx(env);
3610 /* Time base */
3611 gen_tbl(env);
3612 /* Thermal management */
3613 gen_spr_thrm(env);
3614 /* Hardware implementation registers */
3615 /* XXX : not implemented */
3616 spr_register(env, SPR_HID0, "HID0",
3617 SPR_NOACCESS, SPR_NOACCESS,
3618 &spr_read_generic, &spr_write_generic,
3619 0x00000000);
3620 /* XXX : not implemented */
3621 spr_register(env, SPR_HID1, "HID1",
3622 SPR_NOACCESS, SPR_NOACCESS,
3623 &spr_read_generic, &spr_write_generic,
3624 0x00000000);
3625 /* XXX : not implemented */
3626 spr_register(env, SPR_750_HID2, "HID2",
3627 SPR_NOACCESS, SPR_NOACCESS,
3628 &spr_read_generic, &spr_write_generic,
3629 0x00000000);
3630 /* Memory management */
3631 gen_low_BATs(env);
3632 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3633 gen_high_BATs(env);
3634 init_excp_750FX(env);
3635 env->dcache_line_size = 32;
3636 env->icache_line_size = 32;
3637 /* Allocate hardware IRQ controller */
3638 ppc6xx_irq_init(env);
3639 }
3640
3641 /* PowerPC 745/755 */
3642 #define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
3643 #define POWERPC_MSRM_7x5 (0x000000000005FF77ULL)
3644 #define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
3645 //#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
3646 #define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
3647 #define POWERPC_BFDM_7x5 (bfd_mach_ppc_750)
3648 #define POWERPC_FLAG_7x5 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3649 POWERPC_FLAG_PMM)
3650 #define check_pow_7x5 check_pow_hid0
3651
3652 static void init_proc_7x5 (CPUPPCState *env)
3653 {
3654 gen_spr_ne_601(env);
3655 gen_spr_G2_755(env);
3656 /* Time base */
3657 gen_tbl(env);
3658 /* L2 cache control */
3659 /* XXX : not implemented */
3660 spr_register(env, SPR_ICTC, "ICTC",
3661 SPR_NOACCESS, SPR_NOACCESS,
3662 &spr_read_generic, &spr_write_generic,
3663 0x00000000);
3664 /* XXX : not implemented */
3665 spr_register(env, SPR_L2PMCR, "L2PMCR",
3666 SPR_NOACCESS, SPR_NOACCESS,
3667 &spr_read_generic, &spr_write_generic,
3668 0x00000000);
3669 /* Hardware implementation registers */
3670 /* XXX : not implemented */
3671 spr_register(env, SPR_HID0, "HID0",
3672 SPR_NOACCESS, SPR_NOACCESS,
3673 &spr_read_generic, &spr_write_generic,
3674 0x00000000);
3675 /* XXX : not implemented */
3676 spr_register(env, SPR_HID1, "HID1",
3677 SPR_NOACCESS, SPR_NOACCESS,
3678 &spr_read_generic, &spr_write_generic,
3679 0x00000000);
3680 /* XXX : not implemented */
3681 spr_register(env, SPR_HID2, "HID2",
3682 SPR_NOACCESS, SPR_NOACCESS,
3683 &spr_read_generic, &spr_write_generic,
3684 0x00000000);
3685 /* Memory management */
3686 gen_low_BATs(env);
3687 gen_high_BATs(env);
3688 gen_6xx_7xx_soft_tlb(env, 64, 2);
3689 init_excp_7x5(env);
3690 env->dcache_line_size = 32;
3691 env->icache_line_size = 32;
3692 /* Allocate hardware IRQ controller */
3693 ppc6xx_irq_init(env);
3694 #if !defined(CONFIG_USER_ONLY)
3695 /* Hardware reset vector */
3696 env->hreset_vector = 0xFFFFFFFCUL;
3697 #endif
3698 }
3699
3700 /* PowerPC 7400 (aka G4) */
3701 #define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3702 PPC_EXTERN | PPC_MEM_TLBIA | \
3703 PPC_ALTIVEC)
3704 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
3705 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
3706 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
3707 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
3708 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
3709 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3710 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3711 #define check_pow_7400 check_pow_hid0
3712
3713 static void init_proc_7400 (CPUPPCState *env)
3714 {
3715 gen_spr_ne_601(env);
3716 gen_spr_7xx(env);
3717 /* Time base */
3718 gen_tbl(env);
3719 /* 74xx specific SPR */
3720 gen_spr_74xx(env);
3721 /* Thermal management */
3722 gen_spr_thrm(env);
3723 /* Memory management */
3724 gen_low_BATs(env);
3725 init_excp_7400(env);
3726 env->dcache_line_size = 32;
3727 env->icache_line_size = 32;
3728 /* Allocate hardware IRQ controller */
3729 ppc6xx_irq_init(env);
3730 }
3731
3732 /* PowerPC 7410 (aka G4) */
3733 #define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3734 PPC_EXTERN | PPC_MEM_TLBIA | \
3735 PPC_ALTIVEC)
3736 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
3737 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
3738 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
3739 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
3740 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
3741 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3742 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3743 #define check_pow_7410 check_pow_hid0
3744
3745 static void init_proc_7410 (CPUPPCState *env)
3746 {
3747 gen_spr_ne_601(env);
3748 gen_spr_7xx(env);
3749 /* Time base */
3750 gen_tbl(env);
3751 /* 74xx specific SPR */
3752 gen_spr_74xx(env);
3753 /* Thermal management */
3754 gen_spr_thrm(env);
3755 /* L2PMCR */
3756 /* XXX : not implemented */
3757 spr_register(env, SPR_L2PMCR, "L2PMCR",
3758 SPR_NOACCESS, SPR_NOACCESS,
3759 &spr_read_generic, &spr_write_generic,
3760 0x00000000);
3761 /* LDSTDB */
3762 /* XXX : not implemented */
3763 spr_register(env, SPR_LDSTDB, "LDSTDB",
3764 SPR_NOACCESS, SPR_NOACCESS,
3765 &spr_read_generic, &spr_write_generic,
3766 0x00000000);
3767 /* Memory management */
3768 gen_low_BATs(env);
3769 init_excp_7400(env);
3770 env->dcache_line_size = 32;
3771 env->icache_line_size = 32;
3772 /* Allocate hardware IRQ controller */
3773 ppc6xx_irq_init(env);
3774 }
3775
3776 /* PowerPC 7440 (aka G4) */
3777 #define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3778 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3779 PPC_ALTIVEC)
3780 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
3781 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
3782 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
3783 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
3784 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
3785 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3786 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3787 #define check_pow_7440 check_pow_hid0
3788
3789 __attribute__ (( unused ))
3790 static void init_proc_7440 (CPUPPCState *env)
3791 {
3792 gen_spr_ne_601(env);
3793 gen_spr_7xx(env);
3794 /* Time base */
3795 gen_tbl(env);
3796 /* 74xx specific SPR */
3797 gen_spr_74xx(env);
3798 /* LDSTCR */
3799 /* XXX : not implemented */
3800 spr_register(env, SPR_LDSTCR, "LDSTCR",
3801 SPR_NOACCESS, SPR_NOACCESS,
3802 &spr_read_generic, &spr_write_generic,
3803 0x00000000);
3804 /* ICTRL */
3805 /* XXX : not implemented */
3806 spr_register(env, SPR_ICTRL, "ICTRL",
3807 SPR_NOACCESS, SPR_NOACCESS,
3808 &spr_read_generic, &spr_write_generic,
3809 0x00000000);
3810 /* MSSSR0 */
3811 /* XXX : not implemented */
3812 spr_register(env, SPR_MSSSR0, "MSSSR0",
3813 SPR_NOACCESS, SPR_NOACCESS,
3814 &spr_read_generic, &spr_write_generic,
3815 0x00000000);
3816 /* PMC */
3817 /* XXX : not implemented */
3818 spr_register(env, SPR_PMC5, "PMC5",
3819 SPR_NOACCESS, SPR_NOACCESS,
3820 &spr_read_generic, &spr_write_generic,
3821 0x00000000);
3822 /* XXX : not implemented */
3823 spr_register(env, SPR_UPMC5, "UPMC5",
3824 &spr_read_ureg, SPR_NOACCESS,
3825 &spr_read_ureg, SPR_NOACCESS,
3826 0x00000000);
3827 /* XXX : not implemented */
3828 spr_register(env, SPR_PMC6, "PMC6",
3829 SPR_NOACCESS, SPR_NOACCESS,
3830 &spr_read_generic, &spr_write_generic,
3831 0x00000000);
3832 /* XXX : not implemented */
3833 spr_register(env, SPR_UPMC6, "UPMC6",
3834 &spr_read_ureg, SPR_NOACCESS,
3835 &spr_read_ureg, SPR_NOACCESS,
3836 0x00000000);
3837 /* Memory management */
3838 gen_low_BATs(env);
3839 gen_74xx_soft_tlb(env, 128, 2);
3840 init_excp_7450(env);
3841 env->dcache_line_size = 32;
3842 env->icache_line_size = 32;
3843 /* Allocate hardware IRQ controller */
3844 ppc6xx_irq_init(env);
3845 }
3846
3847 /* PowerPC 7450 (aka G4) */
3848 #define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3849 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3850 PPC_ALTIVEC)
3851 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
3852 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
3853 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
3854 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
3855 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
3856 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3857 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3858 #define check_pow_7450 check_pow_hid0
3859
3860 __attribute__ (( unused ))
3861 static void init_proc_7450 (CPUPPCState *env)
3862 {
3863 gen_spr_ne_601(env);
3864 gen_spr_7xx(env);
3865 /* Time base */
3866 gen_tbl(env);
3867 /* 74xx specific SPR */
3868 gen_spr_74xx(env);
3869 /* Level 3 cache control */
3870 gen_l3_ctrl(env);
3871 /* LDSTCR */
3872 /* XXX : not implemented */
3873 spr_register(env, SPR_LDSTCR, "LDSTCR",
3874 SPR_NOACCESS, SPR_NOACCESS,
3875 &spr_read_generic, &spr_write_generic,
3876 0x00000000);
3877 /* ICTRL */
3878 /* XXX : not implemented */
3879 spr_register(env, SPR_ICTRL, "ICTRL",
3880 SPR_NOACCESS, SPR_NOACCESS,
3881 &spr_read_generic, &spr_write_generic,
3882 0x00000000);
3883 /* MSSSR0 */
3884 /* XXX : not implemented */
3885 spr_register(env, SPR_MSSSR0, "MSSSR0",
3886 SPR_NOACCESS, SPR_NOACCESS,
3887 &spr_read_generic, &spr_write_generic,
3888 0x00000000);
3889 /* PMC */
3890 /* XXX : not implemented */
3891 spr_register(env, SPR_PMC5, "PMC5",
3892 SPR_NOACCESS, SPR_NOACCESS,
3893 &spr_read_generic, &spr_write_generic,
3894 0x00000000);
3895 /* XXX : not implemented */
3896 spr_register(env, SPR_UPMC5, "UPMC5",
3897 &spr_read_ureg, SPR_NOACCESS,
3898 &spr_read_ureg, SPR_NOACCESS,
3899 0x00000000);
3900 /* XXX : not implemented */
3901 spr_register(env, SPR_PMC6, "PMC6",
3902 SPR_NOACCESS, SPR_NOACCESS,
3903 &spr_read_generic, &spr_write_generic,
3904 0x00000000);
3905 /* XXX : not implemented */
3906 spr_register(env, SPR_UPMC6, "UPMC6",
3907 &spr_read_ureg, SPR_NOACCESS,
3908 &spr_read_ureg, SPR_NOACCESS,
3909 0x00000000);
3910 /* Memory management */
3911 gen_low_BATs(env);
3912 gen_74xx_soft_tlb(env, 128, 2);
3913 init_excp_7450(env);
3914 env->dcache_line_size = 32;
3915 env->icache_line_size = 32;
3916 /* Allocate hardware IRQ controller */
3917 ppc6xx_irq_init(env);
3918 }
3919
3920 /* PowerPC 7445 (aka G4) */
3921 #define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3922 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3923 PPC_ALTIVEC)
3924 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
3925 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
3926 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
3927 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
3928 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
3929 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3930 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3931 #define check_pow_7445 check_pow_hid0
3932
3933 __attribute__ (( unused ))
3934 static void init_proc_7445 (CPUPPCState *env)
3935 {
3936 gen_spr_ne_601(env);
3937 gen_spr_7xx(env);
3938 /* Time base */
3939 gen_tbl(env);
3940 /* 74xx specific SPR */
3941 gen_spr_74xx(env);
3942 /* LDSTCR */
3943 /* XXX : not implemented */
3944 spr_register(env, SPR_LDSTCR, "LDSTCR",
3945 SPR_NOACCESS, SPR_NOACCESS,
3946 &spr_read_generic, &spr_write_generic,
3947 0x00000000);
3948 /* ICTRL */
3949 /* XXX : not implemented */
3950 spr_register(env, SPR_ICTRL, "ICTRL",
3951 SPR_NOACCESS, SPR_NOACCESS,
3952 &spr_read_generic, &spr_write_generic,
3953 0x00000000);
3954 /* MSSSR0 */
3955 /* XXX : not implemented */
3956 spr_register(env, SPR_MSSSR0, "MSSSR0",
3957 SPR_NOACCESS, SPR_NOACCESS,
3958 &spr_read_generic, &spr_write_generic,
3959 0x00000000);
3960 /* PMC */
3961 /* XXX : not implemented */
3962 spr_register(env, SPR_PMC5, "PMC5",
3963 SPR_NOACCESS, SPR_NOACCESS,
3964 &spr_read_generic, &spr_write_generic,
3965 0x00000000);
3966 /* XXX : not implemented */
3967 spr_register(env, SPR_UPMC5, "UPMC5",
3968 &spr_read_ureg, SPR_NOACCESS,
3969 &spr_read_ureg, SPR_NOACCESS,
3970 0x00000000);
3971 /* XXX : not implemented */
3972 spr_register(env, SPR_PMC6, "PMC6",
3973 SPR_NOACCESS, SPR_NOACCESS,
3974 &spr_read_generic, &spr_write_generic,
3975 0x00000000);
3976 /* XXX : not implemented */
3977 spr_register(env, SPR_UPMC6, "UPMC6",
3978 &spr_read_ureg, SPR_NOACCESS,
3979 &spr_read_ureg, SPR_NOACCESS,
3980 0x00000000);
3981 /* SPRGs */
3982 spr_register(env, SPR_SPRG4, "SPRG4",
3983 SPR_NOACCESS, SPR_NOACCESS,
3984 &spr_read_generic, &spr_write_generic,
3985 0x00000000);
3986 spr_register(env, SPR_USPRG4, "USPRG4",
3987 &spr_read_ureg, SPR_NOACCESS,
3988 &spr_read_ureg, SPR_NOACCESS,
3989 0x00000000);
3990 spr_register(env, SPR_SPRG5, "SPRG5",
3991 SPR_NOACCESS, SPR_NOACCESS,
3992 &spr_read_generic, &spr_write_generic,
3993 0x00000000);
3994 spr_register(env, SPR_USPRG5, "USPRG5",
3995 &spr_read_ureg, SPR_NOACCESS,
3996 &spr_read_ureg, SPR_NOACCESS,
3997 0x00000000);
3998 spr_register(env, SPR_SPRG6, "SPRG6",
3999 SPR_NOACCESS, SPR_NOACCESS,
4000 &spr_read_generic, &spr_write_generic,
4001 0x00000000);
4002 spr_register(env, SPR_USPRG6, "USPRG6",
4003 &spr_read_ureg, SPR_NOACCESS,
4004 &spr_read_ureg, SPR_NOACCESS,
4005 0x00000000);
4006 spr_register(env, SPR_SPRG7, "SPRG7",
4007 SPR_NOACCESS, SPR_NOACCESS,
4008 &spr_read_generic, &spr_write_generic,
4009 0x00000000);
4010 spr_register(env, SPR_USPRG7, "USPRG7",
4011 &spr_read_ureg, SPR_NOACCESS,
4012 &spr_read_ureg, SPR_NOACCESS,
4013 0x00000000);
4014 /* Memory management */
4015 gen_low_BATs(env);
4016 gen_high_BATs(env);
4017 gen_74xx_soft_tlb(env, 128, 2);
4018 init_excp_7450(env);
4019 env->dcache_line_size = 32;
4020 env->icache_line_size = 32;
4021 /* Allocate hardware IRQ controller */
4022 ppc6xx_irq_init(env);
4023 }
4024
4025 /* PowerPC 7455 (aka G4) */
4026 #define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
4027 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
4028 PPC_ALTIVEC)
4029 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
4030 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
4031 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
4032 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
4033 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
4034 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4035 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4036 #define check_pow_7455 check_pow_hid0
4037
4038 __attribute__ (( unused ))
4039 static void init_proc_7455 (CPUPPCState *env)
4040 {
4041 gen_spr_ne_601(env);
4042 gen_spr_7xx(env);
4043 /* Time base */
4044 gen_tbl(env);
4045 /* 74xx specific SPR */
4046 gen_spr_74xx(env);
4047 /* Level 3 cache control */
4048 gen_l3_ctrl(env);
4049 /* LDSTCR */
4050 /* XXX : not implemented */
4051 spr_register(env, SPR_LDSTCR, "LDSTCR",
4052 SPR_NOACCESS, SPR_NOACCESS,
4053 &spr_read_generic, &spr_write_generic,
4054 0x00000000);
4055 /* ICTRL */
4056 /* XXX : not implemented */
4057 spr_register(env, SPR_ICTRL, "ICTRL",
4058 SPR_NOACCESS, SPR_NOACCESS,
4059 &spr_read_generic, &spr_write_generic,
4060 0x00000000);
4061 /* MSSSR0 */
4062 /* XXX : not implemented */
4063 spr_register(env, SPR_MSSSR0, "MSSSR0",
4064 SPR_NOACCESS, SPR_NOACCESS,
4065 &spr_read_generic, &spr_write_generic,
4066 0x00000000);
4067 /* PMC */
4068 /* XXX : not implemented */
4069 spr_register(env, SPR_PMC5, "PMC5",
4070 SPR_NOACCESS, SPR_NOACCESS,
4071 &spr_read_generic, &spr_write_generic,
4072 0x00000000);
4073 /* XXX : not implemented */
4074 spr_register(env, SPR_UPMC5, "UPMC5",
4075 &spr_read_ureg, SPR_NOACCESS,
4076 &spr_read_ureg, SPR_NOACCESS,
4077 0x00000000);
4078 /* XXX : not implemented */
4079 spr_register(env, SPR_PMC6, "PMC6",
4080 SPR_NOACCESS, SPR_NOACCESS,
4081 &spr_read_generic, &spr_write_generic,
4082 0x00000000);
4083 /* XXX : not implemented */
4084 spr_register(env, SPR_UPMC6, "UPMC6",
4085 &spr_read_ureg, SPR_NOACCESS,
4086 &spr_read_ureg, SPR_NOACCESS,
4087 0x00000000);
4088 /* SPRGs */
4089 spr_register(env, SPR_SPRG4, "SPRG4",
4090 SPR_NOACCESS, SPR_NOACCESS,
4091 &spr_read_generic, &spr_write_generic,
4092 0x00000000);
4093 spr_register(env, SPR_USPRG4, "USPRG4",
4094 &spr_read_ureg, SPR_NOACCESS,
4095 &spr_read_ureg, SPR_NOACCESS,
4096 0x00000000);
4097 spr_register(env, SPR_SPRG5, "SPRG5",
4098 SPR_NOACCESS, SPR_NOACCESS,
4099 &spr_read_generic, &spr_write_generic,
4100 0x00000000);
4101 spr_register(env, SPR_USPRG5, "USPRG5",
4102 &spr_read_ureg, SPR_NOACCESS,
4103 &spr_read_ureg, SPR_NOACCESS,
4104 0x00000000);
4105 spr_register(env, SPR_SPRG6, "SPRG6",
4106 SPR_NOACCESS, SPR_NOACCESS,
4107 &spr_read_generic, &spr_write_generic,
4108 0x00000000);
4109 spr_register(env, SPR_USPRG6, "USPRG6",
4110 &spr_read_ureg, SPR_NOACCESS,
4111 &spr_read_ureg, SPR_NOACCESS,
4112 0x00000000);
4113 spr_register(env, SPR_SPRG7, "SPRG7",
4114 SPR_NOACCESS, SPR_NOACCESS,
4115 &spr_read_generic, &spr_write_generic,
4116 0x00000000);
4117 spr_register(env, SPR_USPRG7, "USPRG7",
4118 &spr_read_ureg, SPR_NOACCESS,
4119 &spr_read_ureg, SPR_NOACCESS,
4120 0x00000000);
4121 /* Memory management */
4122 gen_low_BATs(env);
4123 gen_high_BATs(env);
4124 gen_74xx_soft_tlb(env, 128, 2);
4125 init_excp_7450(env);
4126 env->dcache_line_size = 32;
4127 env->icache_line_size = 32;
4128 /* Allocate hardware IRQ controller */
4129 ppc6xx_irq_init(env);
4130 }
4131
4132 #if defined (TARGET_PPC64)
4133 #define POWERPC_INSNS_WORK64 (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
4134 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
4135 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
4136 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)
4137 /* PowerPC 970 */
4138 #define POWERPC_INSNS_970 (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4139 PPC_64B | PPC_ALTIVEC | \
4140 PPC_SEGMENT_64B | PPC_SLBI)
4141 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
4142 #define POWERPC_MMU_970 (POWERPC_MMU_64B)
4143 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
4144 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
4145 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
4146 #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4147 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4148
4149 #if defined(CONFIG_USER_ONLY)
4150 #define POWERPC970_HID5_INIT 0x00000080
4151 #else
4152 #define POWERPC970_HID5_INIT 0x00000000
4153 #endif
4154
4155 static int check_pow_970 (CPUPPCState *env)
4156 {
4157 if (env->spr[SPR_HID0] & 0x00600000)
4158 return 1;
4159
4160 return 0;
4161 }
4162
4163 static void init_proc_970 (CPUPPCState *env)
4164 {
4165 gen_spr_ne_601(env);
4166 gen_spr_7xx(env);
4167 /* Time base */
4168 gen_tbl(env);
4169 /* Hardware implementation registers */
4170 /* XXX : not implemented */
4171 spr_register(env, SPR_HID0, "HID0",
4172 SPR_NOACCESS, SPR_NOACCESS,
4173 &spr_read_generic, &spr_write_clear,
4174 0x60000000);
4175 /* XXX : not implemented */
4176 spr_register(env, SPR_HID1, "HID1",
4177 SPR_NOACCESS, SPR_NOACCESS,
4178 &spr_read_generic, &spr_write_generic,
4179 0x00000000);
4180 /* XXX : not implemented */
4181 spr_register(env, SPR_750_HID2, "HID2",
4182 SPR_NOACCESS, SPR_NOACCESS,
4183 &spr_read_generic, &spr_write_generic,
4184 0x00000000);
4185 /* XXX : not implemented */
4186 spr_register(env, SPR_970_HID5, "HID5",
4187 SPR_NOACCESS, SPR_NOACCESS,
4188 &spr_read_generic, &spr_write_generic,
4189 POWERPC970_HID5_INIT);
4190 /* Memory management */
4191 /* XXX: not correct */
4192 gen_low_BATs(env);
4193 /* XXX : not implemented */
4194 spr_register(env, SPR_MMUCFG, "MMUCFG",
4195 SPR_NOACCESS, SPR_NOACCESS,
4196 &spr_read_generic, SPR_NOACCESS,
4197 0x00000000); /* TOFIX */
4198 /* XXX : not implemented */
4199 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4200 SPR_NOACCESS, SPR_NOACCESS,
4201 &spr_read_generic, &spr_write_generic,
4202 0x00000000); /* TOFIX */
4203 spr_register(env, SPR_HIOR, "SPR_HIOR",
4204 SPR_NOACCESS, SPR_NOACCESS,
4205 &spr_read_generic, &spr_write_generic,
4206 0xFFF00000); /* XXX: This is a hack */
4207 #if !defined(CONFIG_USER_ONLY)
4208 env->slb_nr = 32;
4209 #endif
4210 init_excp_970(env);
4211 env->dcache_line_size = 128;
4212 env->icache_line_size = 128;
4213 /* Allocate hardware IRQ controller */
4214 ppc970_irq_init(env);
4215 }
4216
4217 /* PowerPC 970FX (aka G5) */
4218 #define POWERPC_INSNS_970FX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4219 PPC_64B | PPC_ALTIVEC | \
4220 PPC_SEGMENT_64B | PPC_SLBI)
4221 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
4222 #define POWERPC_MMU_970FX (POWERPC_MMU_64B)
4223 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
4224 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
4225 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
4226 #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4227 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4228
4229 static int check_pow_970FX (CPUPPCState *env)
4230 {
4231 if (env->spr[SPR_HID0] & 0x00600000)
4232 return 1;
4233
4234 return 0;
4235 }
4236
4237 static void init_proc_970FX (CPUPPCState *env)
4238 {
4239 gen_spr_ne_601(env);
4240 gen_spr_7xx(env);
4241 /* Time base */
4242 gen_tbl(env);
4243 /* Hardware implementation registers */
4244 /* XXX : not implemented */
4245 spr_register(env, SPR_HID0, "HID0",
4246 SPR_NOACCESS, SPR_NOACCESS,
4247 &spr_read_generic, &spr_write_clear,
4248 0x60000000);
4249 /* XXX : not implemented */
4250 spr_register(env, SPR_HID1, "HID1",
4251 SPR_NOACCESS, SPR_NOACCESS,
4252 &spr_read_generic, &spr_write_generic,
4253 0x00000000);
4254 /* XXX : not implemented */
4255 spr_register(env, SPR_750_HID2, "HID2",
4256 SPR_NOACCESS, SPR_NOACCESS,
4257 &spr_read_generic, &spr_write_generic,
4258 0x00000000);
4259 /* XXX : not implemented */
4260 spr_register(env, SPR_970_HID5, "HID5",
4261 SPR_NOACCESS, SPR_NOACCESS,
4262 &spr_read_generic, &spr_write_generic,
4263 POWERPC970_HID5_INIT);
4264 /* Memory management */
4265 /* XXX: not correct */
4266 gen_low_BATs(env);
4267 /* XXX : not implemented */
4268 spr_register(env, SPR_MMUCFG, "MMUCFG",
4269 SPR_NOACCESS, SPR_NOACCESS,
4270 &spr_read_generic, SPR_NOACCESS,
4271 0x00000000); /* TOFIX */
4272 /* XXX : not implemented */
4273 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4274 SPR_NOACCESS, SPR_NOACCESS,
4275 &spr_read_generic, &spr_write_generic,
4276 0x00000000); /* TOFIX */
4277 spr_register(env, SPR_HIOR, "SPR_HIOR",
4278 SPR_NOACCESS, SPR_NOACCESS,
4279 &spr_read_generic, &spr_write_generic,
4280 0xFFF00000); /* XXX: This is a hack */
4281 #if !defined(CONFIG_USER_ONLY)
4282 env->slb_nr = 32;
4283 #endif
4284 init_excp_970(env);
4285 env->dcache_line_size = 128;
4286 env->icache_line_size = 128;
4287 /* Allocate hardware IRQ controller */
4288 ppc970_irq_init(env);
4289 }
4290
4291 /* PowerPC 970 GX */
4292 #define POWERPC_INSNS_970GX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4293 PPC_64B | PPC_ALTIVEC | \
4294 PPC_SEGMENT_64B | PPC_SLBI)
4295 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
4296 #define POWERPC_MMU_970GX (POWERPC_MMU_64B)
4297 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
4298 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
4299 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
4300 #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4301 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4302
4303 static int check_pow_970GX (CPUPPCState *env)
4304 {
4305 if (env->spr[SPR_HID0] & 0x00600000)
4306 return 1;
4307
4308 return 0;
4309 }
4310
4311 static void init_proc_970GX (CPUPPCState *env)
4312 {
4313 gen_spr_ne_601(env);
4314 gen_spr_7xx(env);
4315 /* Time base */
4316 gen_tbl(env);
4317 /* Hardware implementation registers */
4318 /* XXX : not implemented */
4319 spr_register(env, SPR_HID0, "HID0",
4320 SPR_NOACCESS, SPR_NOACCESS,
4321 &spr_read_generic, &spr_write_clear,
4322 0x60000000);
4323 /* XXX : not implemented */
4324 spr_register(env, SPR_HID1, "HID1",
4325 SPR_NOACCESS, SPR_NOACCESS,
4326 &spr_read_generic, &spr_write_generic,
4327 0x00000000);
4328 /* XXX : not implemented */
4329 spr_register(env, SPR_750_HID2, "HID2",
4330 SPR_NOACCESS, SPR_NOACCESS,
4331 &spr_read_generic, &spr_write_generic,
4332 0x00000000);
4333 /* XXX : not implemented */
4334 spr_register(env, SPR_970_HID5, "HID5",
4335 SPR_NOACCESS, SPR_NOACCESS,
4336 &spr_read_generic, &spr_write_generic,
4337 POWERPC970_HID5_INIT);
4338 /* Memory management */
4339 /* XXX: not correct */
4340 gen_low_BATs(env);
4341 /* XXX : not implemented */
4342 spr_register(env, SPR_MMUCFG, "MMUCFG",
4343 SPR_NOACCESS, SPR_NOACCESS,
4344 &spr_read_generic, SPR_NOACCESS,
4345 0x00000000); /* TOFIX */
4346 /* XXX : not implemented */
4347 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4348 SPR_NOACCESS, SPR_NOACCESS,
4349 &spr_read_generic, &spr_write_generic,
4350 0x00000000); /* TOFIX */
4351 spr_register(env, SPR_HIOR, "SPR_HIOR",
4352 SPR_NOACCESS, SPR_NOACCESS,
4353 &spr_read_generic, &spr_write_generic,
4354 0xFFF00000); /* XXX: This is a hack */
4355 #if !defined(CONFIG_USER_ONLY)
4356 env->slb_nr = 32;
4357 #endif
4358 init_excp_970(env);
4359 env->dcache_line_size = 128;
4360 env->icache_line_size = 128;
4361 /* Allocate hardware IRQ controller */
4362 ppc970_irq_init(env);
4363 }
4364
4365 /* PowerPC 970 MP */
4366 #define POWERPC_INSNS_970MP (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4367 PPC_64B | PPC_ALTIVEC | \
4368 PPC_SEGMENT_64B | PPC_SLBI)
4369 #define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
4370 #define POWERPC_MMU_970MP (POWERPC_MMU_64B)
4371 #define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
4372 #define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
4373 #define POWERPC_BFDM_970MP (bfd_mach_ppc64)
4374 #define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4375 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4376
4377 static int check_pow_970MP (CPUPPCState *env)
4378 {
4379 if (env->spr[SPR_HID0] & 0x01C00000)
4380 return 1;
4381
4382 return 0;
4383 }
4384
4385 static void init_proc_970MP (CPUPPCState *env)
4386 {
4387 gen_spr_ne_601(env);
4388 gen_spr_7xx(env);
4389 /* Time base */
4390 gen_tbl(env);
4391 /* Hardware implementation registers */
4392 /* XXX : not implemented */
4393 spr_register(env, SPR_HID0, "HID0",
4394 SPR_NOACCESS, SPR_NOACCESS,
4395 &spr_read_generic, &spr_write_clear,
4396 0x60000000);
4397 /* XXX : not implemented */
4398 spr_register(env, SPR_HID1, "HID1",
4399 SPR_NOACCESS, SPR_NOACCESS,
4400 &spr_read_generic, &spr_write_generic,
4401 0x00000000);
4402 /* XXX : not implemented */
4403 spr_register(env, SPR_750_HID2, "HID2",
4404 SPR_NOACCESS, SPR_NOACCESS,
4405 &spr_read_generic, &spr_write_generic,
4406 0x00000000);
4407 /* XXX : not implemented */
4408 spr_register(env, SPR_970_HID5, "HID5",
4409 SPR_NOACCESS, SPR_NOACCESS,
4410 &spr_read_generic, &spr_write_generic,
4411 POWERPC970_HID5_INIT);
4412 /* Memory management */
4413 /* XXX: not correct */
4414 gen_low_BATs(env);
4415 /* XXX : not implemented */
4416 spr_register(env, SPR_MMUCFG, "MMUCFG",
4417 SPR_NOACCESS, SPR_NOACCESS,
4418 &spr_read_generic, SPR_NOACCESS,
4419 0x00000000); /* TOFIX */
4420 /* XXX : not implemented */
4421 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4422 SPR_NOACCESS, SPR_NOACCESS,
4423 &spr_read_generic, &spr_write_generic,
4424 0x00000000); /* TOFIX */
4425 spr_register(env, SPR_HIOR, "SPR_HIOR",
4426 SPR_NOACCESS, SPR_NOACCESS,
4427 &spr_read_generic, &spr_write_generic,
4428 0xFFF00000); /* XXX: This is a hack */
4429 #if !defined(CONFIG_USER_ONLY)
4430 env->slb_nr = 32;
4431 #endif
4432 init_excp_970(env);
4433 env->dcache_line_size = 128;
4434 env->icache_line_size = 128;
4435 /* Allocate hardware IRQ controller */
4436 ppc970_irq_init(env);
4437 }
4438
4439 /* PowerPC 620 */
4440 #define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
4441 PPC_64B | PPC_SLBI)
4442 #define POWERPC_MSRM_620 (0x800000000005FF73ULL)
4443 #define POWERPC_MMU_620 (POWERPC_MMU_64B)
4444 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
4445 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
4446 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
4447 #define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE)
4448 #define check_pow_620 check_pow_nocheck /* Check this */
4449
4450 __attribute__ (( unused ))
4451 static void init_proc_620 (CPUPPCState *env)
4452 {
4453 gen_spr_ne_601(env);
4454 gen_spr_620(env);
4455 /* Time base */
4456 gen_tbl(env);
4457 /* Hardware implementation registers */
4458 /* XXX : not implemented */
4459 spr_register(env, SPR_HID0, "HID0",
4460 SPR_NOACCESS, SPR_NOACCESS,
4461 &spr_read_generic, &spr_write_generic,
4462 0x00000000);
4463 /* Memory management */
4464 gen_low_BATs(env);
4465 gen_high_BATs(env);
4466 init_excp_620(env);
4467 env->dcache_line_size = 64;
4468 env->icache_line_size = 64;
4469 /* Allocate hardware IRQ controller */
4470 ppc6xx_irq_init(env);
4471 }
4472 #endif /* defined (TARGET_PPC64) */
4473
4474 /* Default 32 bits PowerPC target will be 604 */
4475 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
4476 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
4477 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
4478 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
4479 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
4480 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
4481 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
4482 #define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
4483 #define check_pow_PPC32 check_pow_604
4484 #define init_proc_PPC32 init_proc_604
4485
4486 /* Default 64 bits PowerPC target will be 970 FX */
4487 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
4488 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
4489 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
4490 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
4491 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
4492 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
4493 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
4494 #define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
4495 #define check_pow_PPC64 check_pow_970FX
4496 #define init_proc_PPC64 init_proc_970FX
4497
4498 /* Default PowerPC target will be PowerPC 32 */
4499 #if defined (TARGET_PPC64) && 0 // XXX: TODO
4500 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
4501 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
4502 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
4503 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
4504 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
4505 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
4506 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
4507 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
4508 #define check_pow_DEFAULT check_pow_PPC64
4509 #define init_proc_DEFAULT init_proc_PPC64
4510 #else
4511 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
4512 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
4513 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
4514 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
4515 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
4516 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
4517 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
4518 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
4519 #define check_pow_DEFAULT check_pow_PPC32
4520 #define init_proc_DEFAULT init_proc_PPC32
4521 #endif
4522
4523 /*****************************************************************************/
4524 /* PVR definitions for most known PowerPC */
4525 enum {
4526 /* PowerPC 401 family */
4527 /* Generic PowerPC 401 */
4528 #define CPU_POWERPC_401 CPU_POWERPC_401G2
4529 /* PowerPC 401 cores */
4530 CPU_POWERPC_401A1 = 0x00210000,
4531 CPU_POWERPC_401B2 = 0x00220000,
4532 #if 0
4533 CPU_POWERPC_401B3 = xxx,
4534 #endif
4535 CPU_POWERPC_401C2 = 0x00230000,
4536 CPU_POWERPC_401D2 = 0x00240000,
4537 CPU_POWERPC_401E2 = 0x00250000,
4538 CPU_POWERPC_401F2 = 0x00260000,
4539 CPU_POWERPC_401G2 = 0x00270000,
4540 /* PowerPC 401 microcontrolers */
4541 #if 0
4542 CPU_POWERPC_401GF = xxx,
4543 #endif
4544 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
4545 /* IBM Processor for Network Resources */
4546 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
4547 #if 0
4548 CPU_POWERPC_XIPCHIP = xxx,
4549 #endif
4550 /* PowerPC 403 family */
4551 /* Generic PowerPC 403 */
4552 #define CPU_POWERPC_403 CPU_POWERPC_403GC
4553 /* PowerPC 403 microcontrollers */
4554 CPU_POWERPC_403GA = 0x00200011,
4555 CPU_POWERPC_403GB = 0x00200100,
4556 CPU_POWERPC_403GC = 0x00200200,
4557 CPU_POWERPC_403GCX = 0x00201400,
4558 #if 0
4559 CPU_POWERPC_403GP = xxx,
4560 #endif
4561 /* PowerPC 405 family */
4562 /* Generic PowerPC 405 */
4563 #define CPU_POWERPC_405 CPU_POWERPC_405D4
4564 /* PowerPC 405 cores */
4565 #if 0
4566 CPU_POWERPC_405A3 = xxx,
4567 #endif
4568 #if 0
4569 CPU_POWERPC_405A4 = xxx,
4570 #endif
4571 #if 0
4572 CPU_POWERPC_405B3 = xxx,
4573 #endif
4574 #if 0
4575 CPU_POWERPC_405B4 = xxx,
4576 #endif
4577 #if 0
4578 CPU_POWERPC_405C3 = xxx,
4579 #endif
4580 #if 0
4581 CPU_POWERPC_405C4 = xxx,
4582 #endif
4583 CPU_POWERPC_405D2 = 0x20010000,
4584 #if 0
4585 CPU_POWERPC_405D3 = xxx,
4586 #endif
4587 CPU_POWERPC_405D4 = 0x41810000,
4588 #if 0
4589 CPU_POWERPC_405D5 = xxx,
4590 #endif
4591 #if 0
4592 CPU_POWERPC_405E4 = xxx,
4593 #endif
4594 #if 0
4595 CPU_POWERPC_405F4 = xxx,
4596 #endif
4597 #if 0
4598 CPU_POWERPC_405F5 = xxx,
4599 #endif
4600 #if 0
4601 CPU_POWERPC_405F6 = xxx,
4602 #endif
4603 /* PowerPC 405 microcontrolers */
4604 /* XXX: missing 0x200108a0 */
4605 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
4606 CPU_POWERPC_405CRa = 0x40110041,
4607 CPU_POWERPC_405CRb = 0x401100C5,
4608 CPU_POWERPC_405CRc = 0x40110145,
4609 CPU_POWERPC_405EP = 0x51210950,
4610 #if 0
4611 CPU_POWERPC_405EXr = xxx,
4612 #endif
4613 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
4614 #if 0
4615 CPU_POWERPC_405FX = xxx,
4616 #endif
4617 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
4618 CPU_POWERPC_405GPa = 0x40110000,
4619 CPU_POWERPC_405GPb = 0x40110040,
4620 CPU_POWERPC_405GPc = 0x40110082,
4621 CPU_POWERPC_405GPd = 0x401100C4,
4622 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
4623 CPU_POWERPC_405GPR = 0x50910951,
4624 #if 0
4625 CPU_POWERPC_405H = xxx,
4626 #endif
4627 #if 0
4628 CPU_POWERPC_405L = xxx,
4629 #endif
4630 CPU_POWERPC_405LP = 0x41F10000,
4631 #if 0
4632 CPU_POWERPC_405PM = xxx,
4633 #endif
4634 #if 0
4635 CPU_POWERPC_405PS = xxx,
4636 #endif
4637 #if 0
4638 CPU_POWERPC_405S = xxx,
4639 #endif
4640 /* IBM network processors */
4641 CPU_POWERPC_NPE405H = 0x414100C0,
4642 CPU_POWERPC_NPE405H2 = 0x41410140,
4643 CPU_POWERPC_NPE405L = 0x416100C0,
4644 CPU_POWERPC_NPE4GS3 = 0x40B10000,
4645 #if 0
4646 CPU_POWERPC_NPCxx1 = xxx,
4647 #endif
4648 #if 0
4649 CPU_POWERPC_NPR161 = xxx,
4650 #endif
4651 #if 0
4652 CPU_POWERPC_LC77700 = xxx,
4653 #endif
4654 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
4655 #if 0
4656 CPU_POWERPC_STB01000 = xxx,
4657 #endif
4658 #if 0
4659 CPU_POWERPC_STB01010 = xxx,
4660 #endif
4661 #if 0
4662 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
4663 #endif
4664 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
4665 #if 0
4666 CPU_POWERPC_STB043 = xxx,
4667 #endif
4668 #if 0
4669 CPU_POWERPC_STB045 = xxx,
4670 #endif
4671 CPU_POWERPC_STB04 = 0x41810000,
4672 CPU_POWERPC_STB25 = 0x51510950,
4673 #if 0
4674 CPU_POWERPC_STB130 = xxx,
4675 #endif
4676 /* Xilinx cores */
4677 CPU_POWERPC_X2VP4 = 0x20010820,
4678 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
4679 CPU_POWERPC_X2VP20 = 0x20010860,
4680 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
4681 #if 0
4682 CPU_POWERPC_ZL10310 = xxx,
4683 #endif
4684 #if 0
4685 CPU_POWERPC_ZL10311 = xxx,
4686 #endif
4687 #if 0
4688 CPU_POWERPC_ZL10320 = xxx,
4689 #endif
4690 #if 0
4691 CPU_POWERPC_ZL10321 = xxx,
4692 #endif
4693 /* PowerPC 440 family */
4694 /* Generic PowerPC 440 */
4695 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
4696 /* PowerPC 440 cores */
4697 #if 0
4698 CPU_POWERPC_440A4 = xxx,
4699 #endif
4700 #if 0
4701 CPU_POWERPC_440A5 = xxx,
4702 #endif
4703 #if 0
4704 CPU_POWERPC_440B4 = xxx,
4705 #endif
4706 #if 0
4707 CPU_POWERPC_440F5 = xxx,
4708 #endif
4709 #if 0
4710 CPU_POWERPC_440G5 = xxx,
4711 #endif
4712 #if 0
4713 CPU_POWERPC_440H4 = xxx,
4714 #endif
4715 #if 0
4716 CPU_POWERPC_440H6 = xxx,
4717 #endif
4718 /* PowerPC 440 microcontrolers */
4719 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
4720 CPU_POWERPC_440EPa = 0x42221850,
4721 CPU_POWERPC_440EPb = 0x422218D3,
4722 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
4723 CPU_POWERPC_440GPb = 0x40120440,
4724 CPU_POWERPC_440GPc = 0x40120481,
4725 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
4726 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
4727 CPU_POWERPC_440GRX = 0x200008D0,
4728 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
4729 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
4730 CPU_POWERPC_440GXa = 0x51B21850,
4731 CPU_POWERPC_440GXb = 0x51B21851,
4732 CPU_POWERPC_440GXc = 0x51B21892,
4733 CPU_POWERPC_440GXf = 0x51B21894,
4734 #if 0
4735 CPU_POWERPC_440S = xxx,
4736 #endif
4737 CPU_POWERPC_440SP = 0x53221850,
4738 CPU_POWERPC_440SP2 = 0x53221891,
4739 CPU_POWERPC_440SPE = 0x53421890,
4740 /* PowerPC 460 family */
4741 #if 0
4742 /* Generic PowerPC 464 */
4743 #define CPU_POWERPC_464 CPU_POWERPC_464H90
4744 #endif
4745 /* PowerPC 464 microcontrolers */
4746 #if 0
4747 CPU_POWERPC_464H90 = xxx,
4748 #endif
4749 #if 0
4750 CPU_POWERPC_464H90FP = xxx,
4751 #endif
4752 /* Freescale embedded PowerPC cores */
4753 /* PowerPC MPC 5xx cores (aka RCPU) */
4754 CPU_POWERPC_5xx = 0x00020020,
4755 #define CPU_POWERPC_509 CPU_POWERPC_5xx
4756 #define CPU_POWERPC_533 CPU_POWERPC_5xx
4757 #define CPU_POWERPC_534 CPU_POWERPC_5xx
4758 #define CPU_POWERPC_555 CPU_POWERPC_5xx
4759 #define CPU_POWERPC_556 CPU_POWERPC_5xx
4760 #define CPU_POWERPC_560 CPU_POWERPC_5xx
4761 #define CPU_POWERPC_561 CPU_POWERPC_5xx
4762 #define CPU_POWERPC_562 CPU_POWERPC_5xx
4763 #define CPU_POWERPC_563 CPU_POWERPC_5xx
4764 #define CPU_POWERPC_564 CPU_POWERPC_5xx
4765 #define CPU_POWERPC_565 CPU_POWERPC_5xx
4766 #define CPU_POWERPC_566 CPU_POWERPC_5xx
4767 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
4768 CPU_POWERPC_8xx = 0x00500000,
4769 #define CPU_POWERPC_821 CPU_POWERPC_8xx
4770 #define CPU_POWERPC_823 CPU_POWERPC_8xx
4771 #define CPU_POWERPC_850 CPU_POWERPC_8xx
4772 #define CPU_POWERPC_852T CPU_POWERPC_8xx
4773 #define CPU_POWERPC_855T CPU_POWERPC_8xx
4774 #define CPU_POWERPC_859 CPU_POWERPC_8xx
4775 #define CPU_POWERPC_860 CPU_POWERPC_8xx
4776 #define CPU_POWERPC_862 CPU_POWERPC_8xx
4777 #define CPU_POWERPC_866 CPU_POWERPC_8xx
4778 #define CPU_POWERPC_857 CPU_POWERPC_8xx
4779 #define CPU_POWERPC_870 CPU_POWERPC_8xx
4780 #define CPU_POWERPC_875 CPU_POWERPC_8xx
4781 #define CPU_POWERPC_880 CPU_POWERPC_8xx
4782 #define CPU_POWERPC_885 CPU_POWERPC_8xx
4783 /* G2 cores (aka PowerQUICC-II) */
4784 CPU_POWERPC_G2 = 0x00810011,
4785 CPU_POWERPC_G2H4 = 0x80811010,
4786 CPU_POWERPC_G2gp = 0x80821010,
4787 CPU_POWERPC_G2ls = 0x90810010,
4788 CPU_POWERPC_MPC603 = 0x00810100,
4789 #define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
4790 CPU_POWERPC_G2_HIP3 = 0x00810101,
4791 #define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
4792 #define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
4793 #define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
4794 #define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
4795 #define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
4796 #define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
4797 CPU_POWERPC_G2_HIP4 = 0x80811014,
4798 #define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
4799 #define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
4800 #define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
4801 #define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
4802 #define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
4803 #define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
4804 #define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
4805 #define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
4806 /* G2_LE core (aka PowerQUICC-II) */
4807 CPU_POWERPC_G2LE = 0x80820010,
4808 CPU_POWERPC_G2LEgp = 0x80822010,
4809 CPU_POWERPC_G2LEls = 0xA0822010,
4810 CPU_POWERPC_G2LEgp1 = 0x80822011,
4811 /* XXX: MPC 5121 ? */
4812 #define CPU_POWERPC_MPC5200 CPU_POWERPC_G2LEgp1
4813 CPU_POWERPC_G2LEgp3 = 0x80822013,
4814 #define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
4815 #define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
4816 #define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
4817 #define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
4818 #define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
4819 #define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
4820 #define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
4821 /* e200 family */
4822 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
4823 #if 0
4824 CPU_POWERPC_e200z0 = xxx,
4825 #define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
4826 #define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
4827 #define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
4828 #define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
4829 #endif
4830 #if 0
4831 CPU_POWERPC_e200z1 = xxx,
4832 #define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
4833 #define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
4834 #define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
4835 #define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
4836 #define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
4837 #define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
4838 #endif
4839 #if 0 /* ? */
4840 CPU_POWERPC_e200z3 = 0x81120000,
4841 #define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
4842 #define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
4843 #endif
4844 CPU_POWERPC_e200z5 = 0x81000000,
4845 CPU_POWERPC_e200z6 = 0x81120000,
4846 #define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
4847 #define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
4848 #define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
4849 #define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
4850 #define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
4851 #define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
4852 /* e300 family */
4853 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
4854 CPU_POWERPC_e300c1 = 0x00830000,
4855 #define CPU_POWERPC_MPC8343A CPU_POWERPC_e300c1
4856 #define CPU_POWERPC_MPC8343EA CPU_POWERPC_e300c1
4857 #define CPU_POWERPC_MPC8347A CPU_POWERPC_e300c1
4858 #define CPU_POWERPC_MPC8347EA CPU_POWERPC_e300c1
4859 #define CPU_POWERPC_MPC8349 CPU_POWERPC_e300c1
4860 #define CPU_POWERPC_MPC8349E CPU_POWERPC_e300c1
4861 #define CPU_POWERPC_MPC8358E CPU_POWERPC_e300c1
4862 #define CPU_POWERPC_MPC8360E CPU_POWERPC_e300c1
4863 CPU_POWERPC_e300c2 = 0x00840000,
4864 #define CPU_POWERPC_MPC8321 CPU_POWERPC_e300c2
4865 #define CPU_POWERPC_MPC8321E CPU_POWERPC_e300c2
4866 #define CPU_POWERPC_MPC8323 CPU_POWERPC_e300c2
4867 #define CPU_POWERPC_MPC8323E CPU_POWERPC_e300c2
4868 CPU_POWERPC_e300c3 = 0x00850000,
4869 #define CPU_POWERPC_MPC8313 CPU_POWERPC_e300c3
4870 #define CPU_POWERPC_MPC8313E CPU_POWERPC_e300c3
4871 #define CPU_POWERPC_MPC8314 CPU_POWERPC_e300c3
4872 #define CPU_POWERPC_MPC8314E CPU_POWERPC_e300c3
4873 #define CPU_POWERPC_MPC8315 CPU_POWERPC_e300c3
4874 #define CPU_POWERPC_MPC8315E CPU_POWERPC_e300c3
4875 CPU_POWERPC_e300c4 = 0x00860000,
4876 #define CPU_POWERPC_MPC8377 CPU_POWERPC_e300c4
4877 #define CPU_POWERPC_MPC8377E CPU_POWERPC_e300c4
4878 #define CPU_POWERPC_MPC8378 CPU_POWERPC_e300c4
4879 #define CPU_POWERPC_MPC8378E CPU_POWERPC_e300c4
4880 #define CPU_POWERPC_MPC8379 CPU_POWERPC_e300c4
4881 #define CPU_POWERPC_MPC8379E CPU_POWERPC_e300c4
4882 /* e500 family */
4883 #define CPU_POWERPC_e500 CPU_POWERPC_e500_v22
4884 CPU_POWERPC_e500_v10 = 0x80200010,
4885 #define CPU_POWERPC_MPC8540_v1 CPU_POWERPC_e500_v10
4886 CPU_POWERPC_e500_v20 = 0x80200020,
4887 #define CPU_POWERPC_MPC8540_v2 CPU_POWERPC_e500_v20
4888 #define CPU_POWERPC_MPC8541 CPU_POWERPC_e500_v20
4889 #define CPU_POWERPC_MPC8541E CPU_POWERPC_e500_v20
4890 #define CPU_POWERPC_MPC8555 CPU_POWERPC_e500_v20
4891 #define CPU_POWERPC_MPC8555E CPU_POWERPC_e500_v20
4892 #define CPU_POWERPC_MPC8560 CPU_POWERPC_e500_v20
4893 CPU_POWERPC_e500v2_v10 = 0x80210010,
4894 #define CPU_POWERPC_MPC8543 CPU_POWERPC_e500v2_v10
4895 #define CPU_POWERPC_MPC8543E CPU_POWERPC_e500v2_v10
4896 #define CPU_POWERPC_MPC8545 CPU_POWERPC_e500v2_v10
4897 #define CPU_POWERPC_MPC8545E CPU_POWERPC_e500v2_v10
4898 #define CPU_POWERPC_MPC8547E CPU_POWERPC_e500v2_v10
4899 #define CPU_POWERPC_MPC8548 CPU_POWERPC_e500v2_v10
4900 #define CPU_POWERPC_MPC8548E CPU_POWERPC_e500v2_v10
4901 CPU_POWERPC_e500v2_v20 = 0x80210020,
4902 CPU_POWERPC_e500v2_v21 = 0x80210021,
4903 #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
4904 #define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
4905 #define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
4906 #define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
4907 CPU_POWERPC_e500v2_v22 = 0x80210022,
4908 #define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
4909 #define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
4910 #define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
4911 #define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
4912 #define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
4913 #define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
4914 CPU_POWERPC_e500v2_v30 = 0x80210030,
4915 #define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
4916 /* e600 family */
4917 CPU_POWERPC_e600 = 0x80040010,
4918 #define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
4919 #define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
4920 #define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
4921 /* PowerPC 6xx cores */
4922 #define CPU_POWERPC_601 CPU_POWERPC_601_v2
4923 CPU_POWERPC_601_v0 = 0x00010001,
4924 CPU_POWERPC_601_v1 = 0x00010001,
4925 CPU_POWERPC_601_v2 = 0x00010002,
4926 CPU_POWERPC_602 = 0x00050100,
4927 CPU_POWERPC_603 = 0x00030100,
4928 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
4929 CPU_POWERPC_603E_v11 = 0x00060101,
4930 CPU_POWERPC_603E_v12 = 0x00060102,
4931 CPU_POWERPC_603E_v13 = 0x00060103,
4932 CPU_POWERPC_603E_v14 = 0x00060104,
4933 CPU_POWERPC_603E_v22 = 0x00060202,
4934 CPU_POWERPC_603E_v3 = 0x00060300,
4935 CPU_POWERPC_603E_v4 = 0x00060400,
4936 CPU_POWERPC_603E_v41 = 0x00060401,
4937 CPU_POWERPC_603E7t = 0x00071201,
4938 CPU_POWERPC_603E7v = 0x00070100,
4939 CPU_POWERPC_603E7v1 = 0x00070101,
4940 CPU_POWERPC_603E7v2 = 0x00070201,
4941 CPU_POWERPC_603E7 = 0x00070200,
4942 CPU_POWERPC_603P = 0x00070000,
4943 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
4944 /* XXX: missing 0x00040303 (604) */
4945 CPU_POWERPC_604 = 0x00040103,
4946 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
4947 /* XXX: missing 0x00091203 */
4948 /* XXX: missing 0x00092110 */
4949 /* XXX: missing 0x00092120 */
4950 CPU_POWERPC_604E_v10 = 0x00090100,
4951 CPU_POWERPC_604E_v22 = 0x00090202,
4952 CPU_POWERPC_604E_v24 = 0x00090204,
4953 /* XXX: missing 0x000a0100 */
4954 /* XXX: missing 0x00093102 */
4955 CPU_POWERPC_604R = 0x000a0101,
4956 #if 0
4957 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
4958 #endif
4959 /* PowerPC 740/750 cores (aka G3) */
4960 /* XXX: missing 0x00084202 */
4961 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
4962 CPU_POWERPC_7x0_v20 = 0x00080200,
4963 CPU_POWERPC_7x0_v21 = 0x00080201,
4964 CPU_POWERPC_7x0_v22 = 0x00080202,
4965 CPU_POWERPC_7x0_v30 = 0x00080300,
4966 CPU_POWERPC_7x0_v31 = 0x00080301,
4967 CPU_POWERPC_740E = 0x00080100,
4968 CPU_POWERPC_7x0P = 0x10080000,
4969 /* XXX: missing 0x00087010 (CL ?) */
4970 CPU_POWERPC_750CL = 0x00087200,
4971 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
4972 CPU_POWERPC_750CX_v21 = 0x00082201,
4973 CPU_POWERPC_750CX_v22 = 0x00082202,
4974 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
4975 CPU_POWERPC_750CXE_v21 = 0x00082211,
4976 CPU_POWERPC_750CXE_v22 = 0x00082212,
4977 CPU_POWERPC_750CXE_v23 = 0x00082213,
4978 CPU_POWERPC_750CXE_v24 = 0x00082214,
4979 CPU_POWERPC_750CXE_v24b = 0x00083214,
4980 CPU_POWERPC_750CXE_v31 = 0x00083211,
4981 CPU_POWERPC_750CXE_v31b = 0x00083311,
4982 CPU_POWERPC_750CXR = 0x00083410,
4983 CPU_POWERPC_750E = 0x00080200,
4984 CPU_POWERPC_750FL = 0x700A0203,
4985 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
4986 CPU_POWERPC_750FX_v10 = 0x70000100,
4987 CPU_POWERPC_750FX_v20 = 0x70000200,
4988 CPU_POWERPC_750FX_v21 = 0x70000201,
4989 CPU_POWERPC_750FX_v22 = 0x70000202,
4990 CPU_POWERPC_750FX_v23 = 0x70000203,
4991 CPU_POWERPC_750GL = 0x70020102,
4992 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
4993 CPU_POWERPC_750GX_v10 = 0x70020100,
4994 CPU_POWERPC_750GX_v11 = 0x70020101,
4995 CPU_POWERPC_750GX_v12 = 0x70020102,
4996 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
4997 CPU_POWERPC_750L_v22 = 0x00088202,
4998 CPU_POWERPC_750L_v30 = 0x00088300,
4999 CPU_POWERPC_750L_v32 = 0x00088302,
5000 /* PowerPC 745/755 cores */
5001 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
5002 CPU_POWERPC_7x5_v10 = 0x00083100,
5003 CPU_POWERPC_7x5_v11 = 0x00083101,
5004 CPU_POWERPC_7x5_v20 = 0x00083200,
5005 CPU_POWERPC_7x5_v21 = 0x00083201,
5006 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
5007 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
5008 CPU_POWERPC_7x5_v24 = 0x00083204,
5009 CPU_POWERPC_7x5_v25 = 0x00083205,
5010 CPU_POWERPC_7x5_v26 = 0x00083206,
5011 CPU_POWERPC_7x5_v27 = 0x00083207,
5012 CPU_POWERPC_7x5_v28 = 0x00083208,
5013 #if 0
5014 CPU_POWERPC_7x5P = xxx,
5015 #endif
5016 /* PowerPC 74xx cores (aka G4) */
5017 /* XXX: missing 0x000C1101 */
5018 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
5019 CPU_POWERPC_7400_v10 = 0x000C0100,
5020 CPU_POWERPC_7400_v11 = 0x000C0101,
5021 CPU_POWERPC_7400_v20 = 0x000C0200,
5022 CPU_POWERPC_7400_v22 = 0x000C0202,
5023 CPU_POWERPC_7400_v26 = 0x000C0206,
5024 CPU_POWERPC_7400_v27 = 0x000C0207,
5025 CPU_POWERPC_7400_v28 = 0x000C0208,
5026 CPU_POWERPC_7400_v29 = 0x000C0209,
5027 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
5028 CPU_POWERPC_7410_v10 = 0x800C1100,
5029 CPU_POWERPC_7410_v11 = 0x800C1101,
5030 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
5031 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
5032 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
5033 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
5034 CPU_POWERPC_7448_v10 = 0x80040100,
5035 CPU_POWERPC_7448_v11 = 0x80040101,
5036 CPU_POWERPC_7448_v20 = 0x80040200,
5037 CPU_POWERPC_7448_v21 = 0x80040201,
5038 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
5039 CPU_POWERPC_7450_v10 = 0x80000100,
5040 CPU_POWERPC_7450_v11 = 0x80000101,
5041 CPU_POWERPC_7450_v12 = 0x80000102,
5042 CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
5043 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
5044 CPU_POWERPC_74x1 = 0x80000203,
5045 CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
5046 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
5047 CPU_POWERPC_74x5_v10 = 0x80010100,
5048 /* XXX: missing 0x80010200 */
5049 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
5050 CPU_POWERPC_74x5_v32 = 0x80010302,
5051 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
5052 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
5053 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
5054 /* XXX: is 0x8002xxxx 7447 and 0x8003xxxx 7457 ? */
5055 /* XXX: missing 0x80030102 */
5056 /* XXX: missing 0x80020101 */
5057 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
5058 CPU_POWERPC_74x7_v11 = 0x80030101, /* aka B: 1.1 */
5059 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
5060 /* 64 bits PowerPC */
5061 #if defined(TARGET_PPC64)
5062 CPU_POWERPC_620 = 0x00140000,
5063 CPU_POWERPC_630 = 0x00400000,
5064 CPU_POWERPC_631 = 0x00410104,
5065 CPU_POWERPC_POWER4 = 0x00350000,
5066 CPU_POWERPC_POWER4P = 0x00380000,
5067 /* XXX: missing 0x003A0201 */
5068 CPU_POWERPC_POWER5 = 0x003A0203,
5069 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
5070 CPU_POWERPC_POWER5P = 0x003B0000,
5071 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
5072 CPU_POWERPC_POWER6 = 0x003E0000,
5073 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 running POWER5 mode */
5074 CPU_POWERPC_POWER6A = 0x0F000002,
5075 CPU_POWERPC_970 = 0x00390202,
5076 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
5077 CPU_POWERPC_970FX_v10 = 0x00391100,
5078 CPU_POWERPC_970FX_v20 = 0x003C0200,
5079 CPU_POWERPC_970FX_v21 = 0x003C0201,
5080 CPU_POWERPC_970FX_v30 = 0x003C0300,
5081 CPU_POWERPC_970FX_v31 = 0x003C0301,
5082 CPU_POWERPC_970GX = 0x00450000,
5083 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
5084 CPU_POWERPC_970MP_v10 = 0x00440100,
5085 CPU_POWERPC_970MP_v11 = 0x00440101,
5086 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
5087 CPU_POWERPC_CELL_v10 = 0x00700100,
5088 CPU_POWERPC_CELL_v20 = 0x00700400,
5089 CPU_POWERPC_CELL_v30 = 0x00700500,
5090 CPU_POWERPC_CELL_v31 = 0x00700501,
5091 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
5092 CPU_POWERPC_RS64 = 0x00330000,
5093 CPU_POWERPC_RS64II = 0x00340000,
5094 CPU_POWERPC_RS64III = 0x00360000,
5095 CPU_POWERPC_RS64IV = 0x00370000,
5096 #endif /* defined(TARGET_PPC64) */
5097 /* Original POWER */
5098 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
5099 * POWER2 (RIOS2) & RSC2 (P2SC) here
5100 */
5101 #if 0
5102 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
5103 #endif
5104 #if 0
5105 CPU_POWER2 = xxx, /* 0x40000 ? */
5106 #endif
5107 /* PA Semi core */
5108 CPU_POWERPC_PA6T = 0x00900000,
5109 };
5110
5111 /* System version register (used on MPC 8xxx) */
5112 enum {
5113 PPC_SVR_5200_v10 = 0x80110010,
5114 PPC_SVR_5200_v11 = 0x80110011,
5115 PPC_SVR_5200_v12 = 0x80110012,
5116 PPC_SVR_5200B_v20 = 0x80110020,
5117 PPC_SVR_5200B_v21 = 0x80110021,
5118 #if 0
5119 PPC_SVR_5533 = xxx,
5120 #endif
5121 #if 0
5122 PPC_SVR_5534 = xxx,
5123 #endif
5124 #if 0
5125 PPC_SVR_5553 = xxx,
5126 #endif
5127 #if 0
5128 PPC_SVR_5554 = xxx,
5129 #endif
5130 #if 0
5131 PPC_SVR_5561 = xxx,
5132 #endif
5133 #if 0
5134 PPC_SVR_5565 = xxx,
5135 #endif
5136 #if 0
5137 PPC_SVR_5566 = xxx,
5138 #endif
5139 #if 0
5140 PPC_SVR_5567 = xxx,
5141 #endif
5142 #if 0
5143 PPC_SVR_8313 = xxx,
5144 #endif
5145 #if 0
5146 PPC_SVR_8313E = xxx,
5147 #endif
5148 #if 0
5149 PPC_SVR_8314 = xxx,
5150 #endif
5151 #if 0
5152 PPC_SVR_8314E = xxx,
5153 #endif
5154 #if 0
5155 PPC_SVR_8315 = xxx,
5156 #endif
5157 #if 0
5158 PPC_SVR_8315E = xxx,
5159 #endif
5160 #if 0
5161 PPC_SVR_8321 = xxx,
5162 #endif
5163 #if 0
5164 PPC_SVR_8321E = xxx,
5165 #endif
5166 #if 0
5167 PPC_SVR_8323 = xxx,
5168 #endif
5169 #if 0
5170 PPC_SVR_8323E = xxx,
5171 #endif
5172 PPC_SVR_8343A = 0x80570030,
5173 PPC_SVR_8343EA = 0x80560030,
5174 PPC_SVR_8347AP = 0x80550030, /* PBGA package */
5175 PPC_SVR_8347AT = 0x80530030, /* TBGA package */
5176 PPC_SVR_8347EAP = 0x80540030, /* PBGA package */
5177 PPC_SVR_8347EAT = 0x80520030, /* TBGA package */
5178 PPC_SVR_8349 = 0x80510010,
5179 PPC_SVR_8349A = 0x80510030,
5180 PPC_SVR_8349E = 0x80500010,
5181 PPC_SVR_8349EA = 0x80500030,
5182 #if 0
5183 PPC_SVR_8358E = xxx,
5184 #endif
5185 #if 0
5186 PPC_SVR_8360E = xxx,
5187 #endif
5188 PPC_SVR_8377 = 0x80C70010,
5189 PPC_SVR_8377E = 0x80C60010,
5190 PPC_SVR_8378 = 0x80C50010,
5191 PPC_SVR_8378E = 0x80C40010,
5192 PPC_SVR_8379 = 0x80C30010,
5193 PPC_SVR_8379E = 0x80C00010,
5194 PPC_SVR_8533_v10 = 0x80340010,
5195 PPC_SVR_8533_v11 = 0x80340011,
5196 PPC_SVR_8533E_v10 = 0x803C0010,
5197 PPC_SVR_8533E_v11 = 0x803C0011,
5198 PPC_SVR_8540_v10 = 0x80300010,
5199 PPC_SVR_8540_v20 = 0x80300020,
5200 PPC_SVR_8540_v21 = 0x80300021,
5201 PPC_SVR_8541_v10 = 0x80720010,
5202 PPC_SVR_8541_v11 = 0x80720011,
5203 PPC_SVR_8541E_v10 = 0x807A0010,
5204 PPC_SVR_8541E_v11 = 0x807A0011,
5205 PPC_SVR_8543_v10 = 0x80320010,
5206 PPC_SVR_8543_v11 = 0x80320011,
5207 PPC_SVR_8543_v20 = 0x80320020,
5208 PPC_SVR_8543_v21 = 0x80320021,
5209 PPC_SVR_8543E_v10 = 0x803A0010,
5210 PPC_SVR_8543E_v11 = 0x803A0011,
5211 PPC_SVR_8543E_v20 = 0x803A0020,
5212 PPC_SVR_8543E_v21 = 0x803A0021,
5213 PPC_SVR_8544_v10 = 0x80340110,
5214 PPC_SVR_8544_v11 = 0x80340111,
5215 PPC_SVR_8544E_v10 = 0x803C0110,
5216 PPC_SVR_8544E_v11 = 0x803C0111,
5217 PPC_SVR_8545_v20 = 0x80310220,
5218 PPC_SVR_8545_v21 = 0x80310221,
5219 PPC_SVR_8545E_v20 = 0x80390220,
5220 PPC_SVR_8545E_v21 = 0x80390221,
5221 PPC_SVR_8547E_v20 = 0x80390120,
5222 PPC_SVR_8547E_v21 = 0x80390121,
5223 PPC_SCR_8548_v10 = 0x80310010,
5224 PPC_SCR_8548_v11 = 0x80310011,
5225 PPC_SCR_8548_v20 = 0x80310020,
5226 PPC_SCR_8548_v21 = 0x80310021,
5227 PPC_SVR_8548E_v10 = 0x80390010,
5228 PPC_SVR_8548E_v11 = 0x80390011,
5229 PPC_SVR_8548E_v20 = 0x80390020,
5230 PPC_SVR_8548E_v21 = 0x80390021,
5231 PPC_SVR_8555_v10 = 0x80710010,
5232 PPC_SVR_8555_v11 = 0x80710011,
5233 PPC_SVR_8555E_v10 = 0x80790010,
5234 PPC_SVR_8555E_v11 = 0x80790011,
5235 PPC_SVR_8560_v10 = 0x80700010,
5236 PPC_SVR_8560_v20 = 0x80700020,
5237 PPC_SVR_8560_v21 = 0x80700021,
5238 PPC_SVR_8567 = 0x80750111,
5239 PPC_SVR_8567E = 0x807D0111,
5240 PPC_SVR_8568 = 0x80750011,
5241 PPC_SVR_8568E = 0x807D0011,
5242 PPC_SVR_8572 = 0x80E00010,
5243 PPC_SVR_8572E = 0x80E80010,
5244 #if 0
5245 PPC_SVR_8610 = xxx,
5246 #endif
5247 PPC_SVR_8641 = 0x80900021,
5248 PPC_SVR_8641D = 0x80900121,
5249 };
5250
5251 /*****************************************************************************/
5252 /* PowerPC CPU definitions */
5253 #define POWERPC_DEF(_name, _pvr, _type) \
5254 { \
5255 .name = _name, \
5256 .pvr = _pvr, \
5257 .insns_flags = glue(POWERPC_INSNS_,_type), \
5258 .msr_mask = glue(POWERPC_MSRM_,_type), \
5259 .mmu_model = glue(POWERPC_MMU_,_type), \
5260 .excp_model = glue(POWERPC_EXCP_,_type), \
5261 .bus_model = glue(POWERPC_INPUT_,_type), \
5262 .bfd_mach = glue(POWERPC_BFDM_,_type), \
5263 .flags = glue(POWERPC_FLAG_,_type), \
5264 .init_proc = &glue(init_proc_,_type), \
5265 .check_pow = &glue(check_pow_,_type), \
5266 }
5267
5268 static const ppc_def_t ppc_defs[] = {
5269 /* Embedded PowerPC */
5270 /* PowerPC 401 family */
5271 /* Generic PowerPC 401 */
5272 POWERPC_DEF("401", CPU_POWERPC_401, 401),
5273 /* PowerPC 401 cores */
5274 /* PowerPC 401A1 */
5275 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
5276 /* PowerPC 401B2 */
5277 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
5278 #if defined (TODO)
5279 /* PowerPC 401B3 */
5280 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
5281 #endif
5282 /* PowerPC 401C2 */
5283 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
5284 /* PowerPC 401D2 */
5285 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
5286 /* PowerPC 401E2 */
5287 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
5288 /* PowerPC 401F2 */
5289 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
5290 /* PowerPC 401G2 */
5291 /* XXX: to be checked */
5292 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
5293 /* PowerPC 401 microcontrolers */
5294 #if defined (TODO)
5295 /* PowerPC 401GF */
5296 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
5297 #endif
5298 /* IOP480 (401 microcontroler) */
5299 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
5300 /* IBM Processor for Network Resources */
5301 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
5302 #if defined (TODO)
5303 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
5304 #endif
5305 /* PowerPC 403 family */
5306 /* Generic PowerPC 403 */
5307 POWERPC_DEF("403", CPU_POWERPC_403, 403),
5308 /* PowerPC 403 microcontrolers */
5309 /* PowerPC 403 GA */
5310 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
5311 /* PowerPC 403 GB */
5312 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
5313 /* PowerPC 403 GC */
5314 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
5315 /* PowerPC 403 GCX */
5316 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
5317 #if defined (TODO)
5318 /* PowerPC 403 GP */
5319 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
5320 #endif
5321 /* PowerPC 405 family */
5322 /* Generic PowerPC 405 */
5323 POWERPC_DEF("405", CPU_POWERPC_405, 405),
5324 /* PowerPC 405 cores */
5325 #if defined (TODO)
5326 /* PowerPC 405 A3 */
5327 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
5328 #endif
5329 #if defined (TODO)
5330 /* PowerPC 405 A4 */
5331 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
5332 #endif
5333 #if defined (TODO)
5334 /* PowerPC 405 B3 */
5335 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
5336 #endif
5337 #if defined (TODO)
5338 /* PowerPC 405 B4 */
5339 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
5340 #endif
5341 #if defined (TODO)
5342 /* PowerPC 405 C3 */
5343 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
5344 #endif
5345 #if defined (TODO)
5346 /* PowerPC 405 C4 */
5347 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
5348 #endif
5349 /* PowerPC 405 D2 */
5350 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
5351 #if defined (TODO)
5352 /* PowerPC 405 D3 */
5353 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
5354 #endif
5355 /* PowerPC 405 D4 */
5356 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
5357 #if defined (TODO)
5358 /* PowerPC 405 D5 */
5359 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
5360 #endif
5361 #if defined (TODO)
5362 /* PowerPC 405 E4 */
5363 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
5364 #endif
5365 #if defined (TODO)
5366 /* PowerPC 405 F4 */
5367 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
5368 #endif
5369 #if defined (TODO)
5370 /* PowerPC 405 F5 */
5371 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
5372 #endif
5373 #if defined (TODO)
5374 /* PowerPC 405 F6 */
5375 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
5376 #endif
5377 /* PowerPC 405 microcontrolers */
5378 /* PowerPC 405 CR */
5379 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
5380 /* PowerPC 405 CRa */
5381 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
5382 /* PowerPC 405 CRb */
5383 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
5384 /* PowerPC 405 CRc */
5385 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
5386 /* PowerPC 405 EP */
5387 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
5388 #if defined(TODO)
5389 /* PowerPC 405 EXr */
5390 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
5391 #endif
5392 /* PowerPC 405 EZ */
5393 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
5394 #if defined(TODO)
5395 /* PowerPC 405 FX */
5396 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
5397 #endif
5398 /* PowerPC 405 GP */
5399 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
5400 /* PowerPC 405 GPa */
5401 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
5402 /* PowerPC 405 GPb */
5403 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
5404 /* PowerPC 405 GPc */
5405 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
5406 /* PowerPC 405 GPd */
5407 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
5408 /* PowerPC 405 GPe */
5409 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
5410 /* PowerPC 405 GPR */
5411 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
5412 #if defined(TODO)
5413 /* PowerPC 405 H */
5414 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
5415 #endif
5416 #if defined(TODO)
5417 /* PowerPC 405 L */
5418 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
5419 #endif
5420 /* PowerPC 405 LP */
5421 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
5422 #if defined(TODO)
5423 /* PowerPC 405 PM */
5424 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
5425 #endif
5426 #if defined(TODO)
5427 /* PowerPC 405 PS */
5428 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
5429 #endif
5430 #if defined(TODO)
5431 /* PowerPC 405 S */
5432 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
5433 #endif
5434 /* Npe405 H */
5435 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
5436 /* Npe405 H2 */
5437 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
5438 /* Npe405 L */
5439 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
5440 /* Npe4GS3 */
5441 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
5442 #if defined (TODO)
5443 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
5444 #endif
5445 #if defined (TODO)
5446 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
5447 #endif
5448 #if defined (TODO)
5449 /* PowerPC LC77700 (Sanyo) */
5450 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
5451 #endif
5452 /* PowerPC 401/403/405 based set-top-box microcontrolers */
5453 #if defined (TODO)
5454 /* STB010000 */
5455 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
5456 #endif
5457 #if defined (TODO)
5458 /* STB01010 */
5459 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
5460 #endif
5461 #if defined (TODO)
5462 /* STB0210 */
5463 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
5464 #endif
5465 /* STB03xx */
5466 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
5467 #if defined (TODO)
5468 /* STB043x */
5469 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
5470 #endif
5471 #if defined (TODO)
5472 /* STB045x */
5473 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
5474 #endif
5475 /* STB04xx */
5476 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
5477 /* STB25xx */
5478 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
5479 #if defined (TODO)
5480 /* STB130 */
5481 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
5482 #endif
5483 /* Xilinx PowerPC 405 cores */
5484 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
5485 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
5486 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
5487 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
5488 #if defined (TODO)
5489 /* Zarlink ZL10310 */
5490 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
5491 #endif
5492 #if defined (TODO)
5493 /* Zarlink ZL10311 */
5494 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
5495 #endif
5496 #if defined (TODO)
5497 /* Zarlink ZL10320 */
5498 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
5499 #endif
5500 #if defined (TODO)
5501 /* Zarlink ZL10321 */
5502 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
5503 #endif
5504 /* PowerPC 440 family */
5505 /* Generic PowerPC 440 */
5506 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
5507 /* PowerPC 440 cores */
5508 #if defined (TODO)
5509 /* PowerPC 440 A4 */
5510 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
5511 #endif
5512 #if defined (TODO)
5513 /* PowerPC 440 A5 */
5514 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
5515 #endif
5516 #if defined (TODO)
5517 /* PowerPC 440 B4 */
5518 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
5519 #endif
5520 #if defined (TODO)
5521 /* PowerPC 440 G4 */
5522 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
5523 #endif
5524 #if defined (TODO)
5525 /* PowerPC 440 F5 */
5526 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
5527 #endif
5528 #if defined (TODO)
5529 /* PowerPC 440 G5 */
5530 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
5531 #endif
5532 #if defined (TODO)
5533 /* PowerPC 440H4 */
5534 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
5535 #endif
5536 #if defined (TODO)
5537 /* PowerPC 440H6 */
5538 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
5539 #endif
5540 /* PowerPC 440 microcontrolers */
5541 /* PowerPC 440 EP */
5542 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
5543 /* PowerPC 440 EPa */
5544 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
5545 /* PowerPC 440 EPb */
5546 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
5547 /* PowerPC 440 EPX */
5548 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
5549 /* PowerPC 440 GP */
5550 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
5551 /* PowerPC 440 GPb */
5552 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
5553 /* PowerPC 440 GPc */
5554 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
5555 /* PowerPC 440 GR */
5556 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
5557 /* PowerPC 440 GRa */
5558 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
5559 /* PowerPC 440 GRX */
5560 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
5561 /* PowerPC 440 GX */
5562 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
5563 /* PowerPC 440 GXa */
5564 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
5565 /* PowerPC 440 GXb */
5566 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
5567 /* PowerPC 440 GXc */
5568 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
5569 /* PowerPC 440 GXf */
5570 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
5571 #if defined(TODO)
5572 /* PowerPC 440 S */
5573 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
5574 #endif
5575 /* PowerPC 440 SP */
5576 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
5577 /* PowerPC 440 SP2 */
5578 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
5579 /* PowerPC 440 SPE */
5580 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
5581 /* PowerPC 460 family */
5582 #if defined (TODO)
5583 /* Generic PowerPC 464 */
5584 POWERPC_DEF("464", CPU_POWERPC_464, 460),
5585 #endif
5586 /* PowerPC 464 microcontrolers */
5587 #if defined (TODO)
5588 /* PowerPC 464H90 */
5589 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
5590 #endif
5591 #if defined (TODO)
5592 /* PowerPC 464H90F */
5593 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
5594 #endif
5595 /* Freescale embedded PowerPC cores */
5596 /* e200 family */
5597 #if defined (TODO)
5598 /* Generic PowerPC e200 core */
5599 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
5600 #endif
5601 #if defined (TODO)
5602 /* PowerPC e200z5 core */
5603 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
5604 #endif
5605 #if defined (TODO)
5606 /* PowerPC e200z6 core */
5607 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
5608 #endif
5609 /* e300 family */
5610 #if defined (TODO)
5611 /* Generic PowerPC e300 core */
5612 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
5613 #endif
5614 #if defined (TODO)
5615 /* PowerPC e300c1 core */
5616 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
5617 #endif
5618 #if defined (TODO)
5619 /* PowerPC e300c2 core */
5620 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
5621 #endif
5622 #if defined (TODO)
5623 /* PowerPC e300c3 core */
5624 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
5625 #endif
5626 /* e500 family */
5627 #if defined (TODO)
5628 /* PowerPC e500 core */
5629 POWERPC_DEF("e500", CPU_POWERPC_e500, e500),
5630 #endif
5631 #if defined (TODO)
5632 /* PowerPC e500 v1.1 core */
5633 POWERPC_DEF("e500v1.1", CPU_POWERPC_e500_v11, e500),
5634 #endif
5635 #if defined (TODO)
5636 /* PowerPC e500 v1.2 core */
5637 POWERPC_DEF("e500v1.2", CPU_POWERPC_e500_v12, e500),
5638 #endif
5639 #if defined (TODO)
5640 /* PowerPC e500 v2.1 core */
5641 POWERPC_DEF("e500v2.1", CPU_POWERPC_e500_v21, e500),
5642 #endif
5643 #if defined (TODO)
5644 /* PowerPC e500 v2.2 core */
5645 POWERPC_DEF("e500v2.2", CPU_POWERPC_e500_v22, e500),
5646 #endif
5647 /* e600 family */
5648 #if defined (TODO)
5649 /* PowerPC e600 core */
5650 POWERPC_DEF("e600", CPU_POWERPC_e600, e600),
5651 #endif
5652 /* PowerPC MPC 5xx cores */
5653 #if defined (TODO)
5654 /* PowerPC MPC 5xx */
5655 POWERPC_DEF("mpc5xx", CPU_POWERPC_5xx, 5xx),
5656 #endif
5657 /* PowerPC MPC 8xx cores */
5658 #if defined (TODO)
5659 /* PowerPC MPC 8xx */
5660 POWERPC_DEF("mpc8xx", CPU_POWERPC_8xx, 8xx),
5661 #endif
5662 /* PowerPC MPC 8xxx cores */
5663 #if defined (TODO)
5664 /* PowerPC MPC 82xx HIP3 */
5665 POWERPC_DEF("mpc82xxhip3", CPU_POWERPC_82xx_HIP3, 82xx),
5666 #endif
5667 #if defined (TODO)
5668 /* PowerPC MPC 82xx HIP4 */
5669 POWERPC_DEF("mpc82xxhip4", CPU_POWERPC_82xx_HIP4, 82xx),
5670 #endif
5671 #if defined (TODO)
5672 /* PowerPC MPC 827x */
5673 POWERPC_DEF("mpc827x", CPU_POWERPC_827x, 827x),
5674 #endif
5675
5676 /* 32 bits "classic" PowerPC */
5677 /* PowerPC 6xx family */
5678 /* PowerPC 601 */
5679 POWERPC_DEF("601", CPU_POWERPC_601, 601),
5680 /* PowerPC 601v0 */
5681 POWERPC_DEF("601v0", CPU_POWERPC_601_v0, 601),
5682 /* PowerPC 601v1 */
5683 POWERPC_DEF("601v1", CPU_POWERPC_601_v1, 601),
5684 /* PowerPC 601v2 */
5685 POWERPC_DEF("601v2", CPU_POWERPC_601_v2, 601),
5686 /* PowerPC 602 */
5687 POWERPC_DEF("602", CPU_POWERPC_602, 602),
5688 /* PowerPC 603 */
5689 POWERPC_DEF("603", CPU_POWERPC_603, 603),
5690 /* Code name for PowerPC 603 */
5691 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
5692 /* PowerPC 603e */
5693 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
5694 /* Code name for PowerPC 603e */
5695 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
5696 /* PowerPC 603e v1.1 */
5697 POWERPC_DEF("603e1.1", CPU_POWERPC_603E_v11, 603E),
5698 /* PowerPC 603e v1.2 */
5699 POWERPC_DEF("603e1.2", CPU_POWERPC_603E_v12, 603E),
5700 /* PowerPC 603e v1.3 */
5701 POWERPC_DEF("603e1.3", CPU_POWERPC_603E_v13, 603E),
5702 /* PowerPC 603e v1.4 */
5703 POWERPC_DEF("603e1.4", CPU_POWERPC_603E_v14, 603E),
5704 /* PowerPC 603e v2.2 */
5705 POWERPC_DEF("603e2.2", CPU_POWERPC_603E_v22, 603E),
5706 /* PowerPC 603e v3 */
5707 POWERPC_DEF("603e3", CPU_POWERPC_603E_v3, 603E),
5708 /* PowerPC 603e v4 */
5709 POWERPC_DEF("603e4", CPU_POWERPC_603E_v4, 603E),
5710 /* PowerPC 603e v4.1 */
5711 POWERPC_DEF("603e4.1", CPU_POWERPC_603E_v41, 603E),
5712 /* PowerPC 603e */
5713 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
5714 /* PowerPC 603e7t */
5715 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
5716 /* PowerPC 603e7v */
5717 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
5718 /* Code name for PowerPC 603ev */
5719 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
5720 /* PowerPC 603e7v1 */
5721 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
5722 /* PowerPC 603e7v2 */
5723 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
5724 /* PowerPC 603p */
5725 /* to be checked */
5726 POWERPC_DEF("603p", CPU_POWERPC_603P, 603),
5727 /* PowerPC 603r */
5728 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
5729 /* Code name for PowerPC 603r */
5730 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
5731 /* PowerPC G2 core */
5732 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
5733 /* PowerPC G2 H4 */
5734 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
5735 /* PowerPC G2 GP */
5736 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
5737 /* PowerPC G2 LS */
5738 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
5739 /* PowerPC G2LE */
5740 /* Same as G2, with little-endian mode support */
5741 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
5742 /* PowerPC G2LE GP */
5743 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
5744 /* PowerPC G2LE LS */
5745 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
5746 /* PowerPC 604 */
5747 POWERPC_DEF("604", CPU_POWERPC_604, 604),
5748 /* PowerPC 604e */
5749 /* XXX: code names "Sirocco" "Mach 5" */
5750 POWERPC_DEF("604e", CPU_POWERPC_604E, 604),
5751 /* PowerPC 604e v1.0 */
5752 POWERPC_DEF("604e1.0", CPU_POWERPC_604E_v10, 604),
5753 /* PowerPC 604e v2.2 */
5754 POWERPC_DEF("604e2.2", CPU_POWERPC_604E_v22, 604),
5755 /* PowerPC 604e v2.4 */
5756 POWERPC_DEF("604e2.4", CPU_POWERPC_604E_v24, 604),
5757 /* PowerPC 604r */
5758 POWERPC_DEF("604r", CPU_POWERPC_604R, 604),
5759 #if defined(TODO)
5760 /* PowerPC 604ev */
5761 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604),
5762 #endif
5763 /* PowerPC 7xx family */
5764 /* Generic PowerPC 740 (G3) */
5765 POWERPC_DEF("740", CPU_POWERPC_7x0, 7x0),
5766 /* Generic PowerPC 750 (G3) */
5767 POWERPC_DEF("750", CPU_POWERPC_7x0, 7x0),
5768 /* Code name for generic PowerPC 740/750 (G3) */
5769 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 7x0),
5770 /* XXX: 750 codename "Typhoon" */
5771 /* PowerPC 740/750 is also known as G3 */
5772 POWERPC_DEF("G3", CPU_POWERPC_7x0, 7x0),
5773 /* PowerPC 740 v2.0 (G3) */
5774 POWERPC_DEF("740v2.0", CPU_POWERPC_7x0_v20, 7x0),
5775 /* PowerPC 750 v2.0 (G3) */
5776 POWERPC_DEF("750v2.0", CPU_POWERPC_7x0_v20, 7x0),
5777 /* PowerPC 740 v2.1 (G3) */
5778 POWERPC_DEF("740v2.1", CPU_POWERPC_7x0_v21, 7x0),
5779 /* PowerPC 750 v2.1 (G3) */
5780 POWERPC_DEF("750v2.1", CPU_POWERPC_7x0_v21, 7x0),
5781 /* PowerPC 740 v2.2 (G3) */
5782 POWERPC_DEF("740v2.2", CPU_POWERPC_7x0_v22, 7x0),
5783 /* PowerPC 750 v2.2 (G3) */
5784 POWERPC_DEF("750v2.2", CPU_POWERPC_7x0_v22, 7x0),
5785 /* PowerPC 740 v3.0 (G3) */
5786 POWERPC_DEF("740v3.0", CPU_POWERPC_7x0_v30, 7x0),
5787 /* PowerPC 750 v3.0 (G3) */
5788 POWERPC_DEF("750v3.0", CPU_POWERPC_7x0_v30, 7x0),
5789 /* PowerPC 740 v3.1 (G3) */
5790 POWERPC_DEF("740v3.1", CPU_POWERPC_7x0_v31, 7x0),
5791 /* PowerPC 750 v3.1 (G3) */
5792 POWERPC_DEF("750v3.1", CPU_POWERPC_7x0_v31, 7x0),
5793 /* PowerPC 740E (G3) */
5794 POWERPC_DEF("740e", CPU_POWERPC_740E, 7x0),
5795 /* PowerPC 740P (G3) */
5796 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 7x0),
5797 /* PowerPC 750P (G3) */
5798 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 7x0),
5799 /* Code name for PowerPC 740P/750P (G3) */
5800 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 7x0),
5801 /* PowerPC 750CL (G3 embedded) */
5802 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 7x0),
5803 /* PowerPC 750CX (G3 embedded) */
5804 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 7x0),
5805 /* PowerPC 750CX v2.1 (G3 embedded) */
5806 POWERPC_DEF("750cx2.1", CPU_POWERPC_750CX_v21, 7x0),
5807 /* PowerPC 750CX v2.2 (G3 embedded) */
5808 POWERPC_DEF("750cx2.2", CPU_POWERPC_750CX_v22, 7x0),
5809 /* PowerPC 750CXe (G3 embedded) */
5810 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 7x0),
5811 /* PowerPC 750CXe v2.1 (G3 embedded) */
5812 POWERPC_DEF("750cxe21", CPU_POWERPC_750CXE_v21, 7x0),
5813 /* PowerPC 750CXe v2.2 (G3 embedded) */
5814 POWERPC_DEF("750cxe22", CPU_POWERPC_750CXE_v22, 7x0),
5815 /* PowerPC 750CXe v2.3 (G3 embedded) */
5816 POWERPC_DEF("750cxe23", CPU_POWERPC_750CXE_v23, 7x0),
5817 /* PowerPC 750CXe v2.4 (G3 embedded) */
5818 POWERPC_DEF("750cxe24", CPU_POWERPC_750CXE_v24, 7x0),
5819 /* PowerPC 750CXe v2.4b (G3 embedded) */
5820 POWERPC_DEF("750cxe24b", CPU_POWERPC_750CXE_v24b, 7x0),
5821 /* PowerPC 750CXe v3.1 (G3 embedded) */
5822 POWERPC_DEF("750cxe31", CPU_POWERPC_750CXE_v31, 7x0),
5823 /* PowerPC 750CXe v3.1b (G3 embedded) */
5824 POWERPC_DEF("750cxe3.1b", CPU_POWERPC_750CXE_v31b, 7x0),
5825 /* PowerPC 750CXr (G3 embedded) */
5826 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 7x0),
5827 /* PowerPC 750E (G3) */
5828 POWERPC_DEF("750e", CPU_POWERPC_750E, 7x0),
5829 /* PowerPC 750FL (G3 embedded) */
5830 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
5831 /* PowerPC 750FX (G3 embedded) */
5832 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
5833 /* PowerPC 750FX v1.0 (G3 embedded) */
5834 POWERPC_DEF("750fx1.0", CPU_POWERPC_750FX_v10, 750fx),
5835 /* PowerPC 750FX v2.0 (G3 embedded) */
5836 POWERPC_DEF("750fx2.0", CPU_POWERPC_750FX_v20, 750fx),
5837 /* PowerPC 750FX v2.1 (G3 embedded) */
5838 POWERPC_DEF("750fx2.1", CPU_POWERPC_750FX_v21, 750fx),
5839 /* PowerPC 750FX v2.2 (G3 embedded) */
5840 POWERPC_DEF("750fx2.2", CPU_POWERPC_750FX_v22, 750fx),
5841 /* PowerPC 750FX v2.3 (G3 embedded) */
5842 POWERPC_DEF("750fx2.3", CPU_POWERPC_750FX_v23, 750fx),
5843 /* PowerPC 750GL (G3 embedded) */
5844 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750fx),
5845 /* PowerPC 750GX (G3 embedded) */
5846 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750fx),
5847 /* PowerPC 750GX v1.0 (G3 embedded) */
5848 POWERPC_DEF("750gx1.0", CPU_POWERPC_750GX_v10, 750fx),
5849 /* PowerPC 750GX v1.1 (G3 embedded) */
5850 POWERPC_DEF("750gx1.1", CPU_POWERPC_750GX_v11, 750fx),
5851 /* PowerPC 750GX v1.2 (G3 embedded) */
5852 POWERPC_DEF("750gx1.2", CPU_POWERPC_750GX_v12, 750fx),
5853 /* PowerPC 750L (G3 embedded) */
5854 POWERPC_DEF("750l", CPU_POWERPC_750L, 7x0),
5855 /* Code name for PowerPC 750L (G3 embedded) */
5856 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 7x0),
5857 /* PowerPC 750L v2.2 (G3 embedded) */
5858 POWERPC_DEF("750l2.2", CPU_POWERPC_750L_v22, 7x0),
5859 /* PowerPC 750L v3.0 (G3 embedded) */
5860 POWERPC_DEF("750l3.0", CPU_POWERPC_750L_v30, 7x0),
5861 /* PowerPC 750L v3.2 (G3 embedded) */
5862 POWERPC_DEF("750l3.2", CPU_POWERPC_750L_v32, 7x0),
5863 /* Generic PowerPC 745 */
5864 POWERPC_DEF("745", CPU_POWERPC_7x5, 7x5),
5865 /* Generic PowerPC 755 */
5866 POWERPC_DEF("755", CPU_POWERPC_7x5, 7x5),
5867 /* Code name for PowerPC 745/755 */
5868 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 7x5),
5869 /* PowerPC 745 v1.0 */
5870 POWERPC_DEF("745v1.0", CPU_POWERPC_7x5_v10, 7x5),
5871 /* PowerPC 755 v1.0 */
5872 POWERPC_DEF("755v1.0", CPU_POWERPC_7x5_v10, 7x5),
5873 /* PowerPC 745 v1.1 */
5874 POWERPC_DEF("745v1.1", CPU_POWERPC_7x5_v11, 7x5),
5875 /* PowerPC 755 v1.1 */
5876 POWERPC_DEF("755v1.1", CPU_POWERPC_7x5_v11, 7x5),
5877 /* PowerPC 745 v2.0 */
5878 POWERPC_DEF("745v2.0", CPU_POWERPC_7x5_v20, 7x5),
5879 /* PowerPC 755 v2.0 */
5880 POWERPC_DEF("755v2.0", CPU_POWERPC_7x5_v20, 7x5),
5881 /* PowerPC 745 v2.1 */
5882 POWERPC_DEF("745v2.1", CPU_POWERPC_7x5_v21, 7x5),
5883 /* PowerPC 755 v2.1 */
5884 POWERPC_DEF("755v2.1", CPU_POWERPC_7x5_v21, 7x5),
5885 /* PowerPC 745 v2.2 */
5886 POWERPC_DEF("745v2.2", CPU_POWERPC_7x5_v22, 7x5),
5887 /* PowerPC 755 v2.2 */
5888 POWERPC_DEF("755v2.2", CPU_POWERPC_7x5_v22, 7x5),
5889 /* PowerPC 745 v2.3 */
5890 POWERPC_DEF("745v2.3", CPU_POWERPC_7x5_v23, 7x5),
5891 /* PowerPC 755 v2.3 */
5892 POWERPC_DEF("755v2.3", CPU_POWERPC_7x5_v23, 7x5),
5893 /* PowerPC 745 v2.4 */
5894 POWERPC_DEF("745v2.4", CPU_POWERPC_7x5_v24, 7x5),
5895 /* PowerPC 755 v2.4 */
5896 POWERPC_DEF("755v2.4", CPU_POWERPC_7x5_v24, 7x5),
5897 /* PowerPC 745 v2.5 */
5898 POWERPC_DEF("745v2.5", CPU_POWERPC_7x5_v25, 7x5),
5899 /* PowerPC 755 v2.5 */
5900 POWERPC_DEF("755v2.5", CPU_POWERPC_7x5_v25, 7x5),
5901 /* PowerPC 745 v2.6 */
5902 POWERPC_DEF("745v2.6", CPU_POWERPC_7x5_v26, 7x5),
5903 /* PowerPC 755 v2.6 */
5904 POWERPC_DEF("755v2.6", CPU_POWERPC_7x5_v26, 7x5),
5905 /* PowerPC 745 v2.7 */
5906 POWERPC_DEF("745v2.7", CPU_POWERPC_7x5_v27, 7x5),
5907 /* PowerPC 755 v2.7 */
5908 POWERPC_DEF("755v2.7", CPU_POWERPC_7x5_v27, 7x5),
5909 /* PowerPC 745 v2.8 */
5910 POWERPC_DEF("745v2.8", CPU_POWERPC_7x5_v28, 7x5),
5911 /* PowerPC 755 v2.8 */
5912 POWERPC_DEF("755v2.8", CPU_POWERPC_7x5_v28, 7x5),
5913 #if defined (TODO)
5914 /* PowerPC 745P (G3) */
5915 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 7x5),
5916 /* PowerPC 755P (G3) */
5917 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 7x5),
5918 #endif
5919 /* PowerPC 74xx family */
5920 /* PowerPC 7400 (G4) */
5921 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
5922 /* Code name for PowerPC 7400 */
5923 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
5924 /* PowerPC 74xx is also well known as G4 */
5925 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
5926 /* PowerPC 7400 v1.0 (G4) */
5927 POWERPC_DEF("7400v1.0", CPU_POWERPC_7400_v10, 7400),
5928 /* PowerPC 7400 v1.1 (G4) */
5929 POWERPC_DEF("7400v1.1", CPU_POWERPC_7400_v11, 7400),
5930 /* PowerPC 7400 v2.0 (G4) */
5931 POWERPC_DEF("7400v2.0", CPU_POWERPC_7400_v20, 7400),
5932 /* PowerPC 7400 v2.2 (G4) */
5933 POWERPC_DEF("7400v2.2", CPU_POWERPC_7400_v22, 7400),
5934 /* PowerPC 7400 v2.6 (G4) */
5935 POWERPC_DEF("7400v2.6", CPU_POWERPC_7400_v26, 7400),
5936 /* PowerPC 7400 v2.7 (G4) */
5937 POWERPC_DEF("7400v2.7", CPU_POWERPC_7400_v27, 7400),
5938 /* PowerPC 7400 v2.8 (G4) */
5939 POWERPC_DEF("7400v2.8", CPU_POWERPC_7400_v28, 7400),
5940 /* PowerPC 7400 v2.9 (G4) */
5941 POWERPC_DEF("7400v2.9", CPU_POWERPC_7400_v29, 7400),
5942 /* PowerPC 7410 (G4) */
5943 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
5944 /* Code name for PowerPC 7410 */
5945 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
5946 /* PowerPC 7410 v1.0 (G4) */
5947 POWERPC_DEF("7410v1.0", CPU_POWERPC_7410_v10, 7410),
5948 /* PowerPC 7410 v1.1 (G4) */
5949 POWERPC_DEF("7410v1.1", CPU_POWERPC_7410_v11, 7410),
5950 /* PowerPC 7410 v1.2 (G4) */
5951 POWERPC_DEF("7410v1.2", CPU_POWERPC_7410_v12, 7410),
5952 /* PowerPC 7410 v1.3 (G4) */
5953 POWERPC_DEF("7410v1.3", CPU_POWERPC_7410_v13, 7410),
5954 /* PowerPC 7410 v1.4 (G4) */
5955 POWERPC_DEF("7410v1.4", CPU_POWERPC_7410_v14, 7410),
5956 /* PowerPC 7448 (G4) */
5957 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
5958 /* PowerPC 7448 v1.0 (G4) */
5959 POWERPC_DEF("7448v1.0", CPU_POWERPC_7448_v10, 7400),
5960 /* PowerPC 7448 v1.1 (G4) */
5961 POWERPC_DEF("7448v1.1", CPU_POWERPC_7448_v11, 7400),
5962 /* PowerPC 7448 v2.0 (G4) */
5963 POWERPC_DEF("7448v2.0", CPU_POWERPC_7448_v20, 7400),
5964 /* PowerPC 7448 v2.1 (G4) */
5965 POWERPC_DEF("7448v2.1", CPU_POWERPC_7448_v21, 7400),
5966 /* PowerPC 7450 (G4) */
5967 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
5968 /* Code name for PowerPC 7450 */
5969 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
5970 /* PowerPC 7450 v1.0 (G4) */
5971 POWERPC_DEF("7450v1.0", CPU_POWERPC_7450_v10, 7450),
5972 /* PowerPC 7450 v1.1 (G4) */
5973 POWERPC_DEF("7450v1.1", CPU_POWERPC_7450_v11, 7450),
5974 /* PowerPC 7450 v1.2 (G4) */
5975 POWERPC_DEF("7450v1.2", CPU_POWERPC_7450_v12, 7450),
5976 /* PowerPC 7450 v2.0 (G4) */
5977 POWERPC_DEF("7450v2.0", CPU_POWERPC_7450_v20, 7450),
5978 /* PowerPC 7450 v2.1 (G4) */
5979 POWERPC_DEF("7450v2.1", CPU_POWERPC_7450_v21, 7450),
5980 /* PowerPC 7441 (G4) */
5981 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
5982 /* PowerPC 7451 (G4) */
5983 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
5984 /* PowerPC 7441g (G4) */
5985 POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 7440),
5986 /* PowerPC 7451g (G4) */
5987 POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 7450),
5988 /* PowerPC 7445 (G4) */
5989 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
5990 /* PowerPC 7455 (G4) */
5991 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
5992 /* Code name for PowerPC 7445/7455 */
5993 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
5994 /* PowerPC 7445 v1.0 (G4) */
5995 POWERPC_DEF("7445v1.0", CPU_POWERPC_74x5_v10, 7445),
5996 /* PowerPC 7455 v1.0 (G4) */
5997 POWERPC_DEF("7455v1.0", CPU_POWERPC_74x5_v10, 7455),
5998 /* PowerPC 7445 v2.1 (G4) */
5999 POWERPC_DEF("7445v2.1", CPU_POWERPC_74x5_v21, 7445),
6000 /* PowerPC 7455 v2.1 (G4) */
6001 POWERPC_DEF("7455v2.1", CPU_POWERPC_74x5_v21, 7455),
6002 /* PowerPC 7445 v3.2 (G4) */
6003 POWERPC_DEF("7445v3.2", CPU_POWERPC_74x5_v32, 7445),
6004 /* PowerPC 7455 v3.2 (G4) */
6005 POWERPC_DEF("7455v3.2", CPU_POWERPC_74x5_v32, 7455),
6006 /* PowerPC 7445 v3.3 (G4) */
6007 POWERPC_DEF("7445v3.3", CPU_POWERPC_74x5_v33, 7445),
6008 /* PowerPC 7455 v3.3 (G4) */
6009 POWERPC_DEF("7455v3.3", CPU_POWERPC_74x5_v33, 7455),
6010 /* PowerPC 7445 v3.4 (G4) */
6011 POWERPC_DEF("7445v3.4", CPU_POWERPC_74x5_v34, 7445),
6012 /* PowerPC 7455 v3.4 (G4) */
6013 POWERPC_DEF("7455v3.4", CPU_POWERPC_74x5_v34, 7455),
6014 /* PowerPC 7447 (G4) */
6015 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
6016 /* PowerPC 7457 (G4) */
6017 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
6018 /* Code name for PowerPC 7447/7457 */
6019 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
6020 /* PowerPC 7447 v1.0 (G4) */
6021 POWERPC_DEF("7447v1.0", CPU_POWERPC_74x7_v10, 7445),
6022 /* PowerPC 7457 v1.0 (G4) */
6023 POWERPC_DEF("7457v1.0", CPU_POWERPC_74x7_v10, 7455),
6024 /* Code name for PowerPC 7447A/7457A */
6025 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10, 7455),
6026 /* PowerPC 7447 v1.1 (G4) */
6027 POWERPC_DEF("7447v1.1", CPU_POWERPC_74x7_v11, 7445),
6028 /* PowerPC 7457 v1.1 (G4) */
6029 POWERPC_DEF("7457v1.1", CPU_POWERPC_74x7_v11, 7455),
6030 /* PowerPC 7447 v1.2 (G4) */
6031 POWERPC_DEF("7447v1.2", CPU_POWERPC_74x7_v12, 7445),
6032 /* PowerPC 7457 v1.2 (G4) */
6033 POWERPC_DEF("7457v1.2", CPU_POWERPC_74x7_v12, 7455),
6034 /* 64 bits PowerPC */
6035 #if defined (TARGET_PPC64)
6036 /* PowerPC 620 */
6037 /* XXX: code name "Trident" */
6038 POWERPC_DEF("620", CPU_POWERPC_620, 620),
6039 #if defined (TODO)
6040 /* PowerPC 630 (POWER3) */
6041 /* XXX: code names: "Boxer" "Dino" */
6042 POWERPC_DEF("630", CPU_POWERPC_630, 630),
6043 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
6044 #endif
6045 #if defined (TODO)
6046 /* PowerPC 631 (Power 3+) */
6047 POWERPC_DEF("631", CPU_POWERPC_631, 631),
6048 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
6049 #endif
6050 #if defined (TODO)
6051 /* POWER4 */
6052 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
6053 #endif
6054 #if defined (TODO)
6055 /* POWER4p */
6056 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
6057 #endif
6058 #if defined (TODO)
6059 /* POWER5 */
6060 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
6061 /* POWER5GR */
6062 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
6063 #endif
6064 #if defined (TODO)
6065 /* POWER5+ */
6066 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
6067 /* POWER5GS */
6068 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
6069 #endif
6070 #if defined (TODO)
6071 /* POWER6 */
6072 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
6073 /* POWER6 running in POWER5 mode */
6074 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
6075 /* POWER6A */
6076 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
6077 #endif
6078 /* PowerPC 970 */
6079 POWERPC_DEF("970", CPU_POWERPC_970, 970),
6080 /* PowerPC 970FX (G5) */
6081 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
6082 /* PowerPC 970FX v1.0 (G5) */
6083 POWERPC_DEF("970fx1.0", CPU_POWERPC_970FX_v10, 970FX),
6084 /* PowerPC 970FX v2.0 (G5) */
6085 POWERPC_DEF("970fx2.0", CPU_POWERPC_970FX_v20, 970FX),
6086 /* PowerPC 970FX v2.1 (G5) */
6087 POWERPC_DEF("970fx2.1", CPU_POWERPC_970FX_v21, 970FX),
6088 /* PowerPC 970FX v3.0 (G5) */
6089 POWERPC_DEF("970fx3.0", CPU_POWERPC_970FX_v30, 970FX),
6090 /* PowerPC 970FX v3.1 (G5) */
6091 POWERPC_DEF("970fx3.1", CPU_POWERPC_970FX_v31, 970FX),
6092 /* PowerPC 970GX (G5) */
6093 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
6094 /* PowerPC 970MP */
6095 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
6096 /* PowerPC 970MP v1.0 */
6097 POWERPC_DEF("970mp1.0", CPU_POWERPC_970MP_v10, 970MP),
6098 /* PowerPC 970MP v1.1 */
6099 POWERPC_DEF("970mp1.1", CPU_POWERPC_970MP_v11, 970MP),
6100 #if defined (TODO)
6101 /* PowerPC Cell */
6102 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
6103 #endif
6104 #if defined (TODO)
6105 /* PowerPC Cell v1.0 */
6106 POWERPC_DEF("Cell1.0", CPU_POWERPC_CELL_v10, 970),
6107 #endif
6108 #if defined (TODO)
6109 /* PowerPC Cell v2.0 */
6110 POWERPC_DEF("Cell2.0", CPU_POWERPC_CELL_v20, 970),
6111 #endif
6112 #if defined (TODO)
6113 /* PowerPC Cell v3.0 */
6114 POWERPC_DEF("Cell3.0", CPU_POWERPC_CELL_v30, 970),
6115 #endif
6116 #if defined (TODO)
6117 /* PowerPC Cell v3.1 */
6118 POWERPC_DEF("Cell3.1", CPU_POWERPC_CELL_v31, 970),
6119 #endif
6120 #if defined (TODO)
6121 /* PowerPC Cell v3.2 */
6122 POWERPC_DEF("Cell3.2", CPU_POWERPC_CELL_v32, 970),
6123 #endif
6124 #if defined (TODO)
6125 /* RS64 (Apache/A35) */
6126 /* This one seems to support the whole POWER2 instruction set
6127 * and the PowerPC 64 one.
6128 */
6129 /* What about A10 & A30 ? */
6130 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
6131 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
6132 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
6133 #endif
6134 #if defined (TODO)
6135 /* RS64-II (NorthStar/A50) */
6136 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
6137 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
6138 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
6139 #endif
6140 #if defined (TODO)
6141 /* RS64-III (Pulsar) */
6142 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
6143 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
6144 #endif
6145 #if defined (TODO)
6146 /* RS64-IV (IceStar/IStar/SStar) */
6147 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
6148 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
6149 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
6150 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
6151 #endif
6152 #endif /* defined (TARGET_PPC64) */
6153 /* POWER */
6154 #if defined (TODO)
6155 /* Original POWER */
6156 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
6157 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
6158 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
6159 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
6160 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
6161 #endif
6162 #if defined (TODO)
6163 /* POWER2 */
6164 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
6165 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
6166 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
6167 #endif
6168 /* PA semi cores */
6169 #if defined (TODO)
6170 /* PA PA6T */
6171 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
6172 #endif
6173 /* Generic PowerPCs */
6174 #if defined (TARGET_PPC64)
6175 #if defined (TODO)
6176 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
6177 #endif
6178 #endif
6179 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
6180 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
6181 /* Fallback */
6182 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
6183 };
6184
6185 /*****************************************************************************/
6186 /* Generic CPU instanciation routine */
6187 static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
6188 {
6189 #if !defined(CONFIG_USER_ONLY)
6190 int i;
6191
6192 env->irq_inputs = NULL;
6193 /* Set all exception vectors to an invalid address */
6194 for (i = 0; i < POWERPC_EXCP_NB; i++)
6195 env->excp_vectors[i] = (target_ulong)(-1ULL);
6196 env->excp_prefix = 0x00000000;
6197 env->ivor_mask = 0x00000000;
6198 env->ivpr_mask = 0x00000000;
6199 /* Default MMU definitions */
6200 env->nb_BATs = 0;
6201 env->nb_tlb = 0;
6202 env->nb_ways = 0;
6203 #endif
6204 /* Register SPR common to all PowerPC implementations */
6205 gen_spr_generic(env);
6206 spr_register(env, SPR_PVR, "PVR",
6207 SPR_NOACCESS, SPR_NOACCESS,
6208 &spr_read_generic, SPR_NOACCESS,
6209 def->pvr);
6210 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
6211 (*def->init_proc)(env);
6212 /* MSR bits & flags consistency checks */
6213 if (env->msr_mask & (1 << 25)) {
6214 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
6215 case POWERPC_FLAG_SPE:
6216 case POWERPC_FLAG_VRE:
6217 break;
6218 default:
6219 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6220 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
6221 exit(1);
6222 }
6223 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
6224 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6225 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
6226 exit(1);
6227 }
6228 if (env->msr_mask & (1 << 17)) {
6229 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
6230 case POWERPC_FLAG_TGPR:
6231 case POWERPC_FLAG_CE:
6232 break;
6233 default:
6234 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6235 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
6236 exit(1);
6237 }
6238 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
6239 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6240 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
6241 exit(1);
6242 }
6243 if (env->msr_mask & (1 << 10)) {
6244 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6245 POWERPC_FLAG_UBLE)) {
6246 case POWERPC_FLAG_SE:
6247 case POWERPC_FLAG_DWE:
6248 case POWERPC_FLAG_UBLE:
6249 break;
6250 default:
6251 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6252 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
6253 "POWERPC_FLAG_UBLE\n");
6254 exit(1);
6255 }
6256 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6257 POWERPC_FLAG_UBLE)) {
6258 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6259 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
6260 "POWERPC_FLAG_UBLE\n");
6261 exit(1);
6262 }
6263 if (env->msr_mask & (1 << 9)) {
6264 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6265 case POWERPC_FLAG_BE:
6266 case POWERPC_FLAG_DE:
6267 break;
6268 default:
6269 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6270 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
6271 exit(1);
6272 }
6273 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6274 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6275 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
6276 exit(1);
6277 }
6278 if (env->msr_mask & (1 << 2)) {
6279 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6280 case POWERPC_FLAG_PX:
6281 case POWERPC_FLAG_PMM:
6282 break;
6283 default:
6284 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6285 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
6286 exit(1);
6287 }
6288 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6289 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6290 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
6291 exit(1);
6292 }
6293 /* Allocate TLBs buffer when needed */
6294 #if !defined(CONFIG_USER_ONLY)
6295 if (env->nb_tlb != 0) {
6296 int nb_tlb = env->nb_tlb;
6297 if (env->id_tlbs != 0)
6298 nb_tlb *= 2;
6299 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
6300 /* Pre-compute some useful values */
6301 env->tlb_per_way = env->nb_tlb / env->nb_ways;
6302 }
6303 if (env->irq_inputs == NULL) {
6304 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
6305 " Attempt Qemu to crash very soon !\n");
6306 }
6307 #endif
6308 if (env->check_pow == NULL) {
6309 fprintf(stderr, "WARNING: no power management check handler "
6310 "registered.\n"
6311 " Attempt Qemu to crash very soon !\n");
6312 }
6313 }
6314
6315 #if defined(PPC_DUMP_CPU)
6316 static void dump_ppc_sprs (CPUPPCState *env)
6317 {
6318 ppc_spr_t *spr;
6319 #if !defined(CONFIG_USER_ONLY)
6320 uint32_t sr, sw;
6321 #endif
6322 uint32_t ur, uw;
6323 int i, j, n;
6324
6325 printf("Special purpose registers:\n");
6326 for (i = 0; i < 32; i++) {
6327 for (j = 0; j < 32; j++) {
6328 n = (i << 5) | j;
6329 spr = &env->spr_cb[n];
6330 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
6331 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
6332 #if !defined(CONFIG_USER_ONLY)
6333 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
6334 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
6335 if (sw || sr || uw || ur) {
6336 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
6337 (i << 5) | j, (i << 5) | j, spr->name,
6338 sw ? 'w' : '-', sr ? 'r' : '-',
6339 uw ? 'w' : '-', ur ? 'r' : '-');
6340 }
6341 #else
6342 if (uw || ur) {
6343 printf("SPR: %4d (%03x) %-8s u%c%c\n",
6344 (i << 5) | j, (i << 5) | j, spr->name,
6345 uw ? 'w' : '-', ur ? 'r' : '-');
6346 }
6347 #endif
6348 }
6349 }
6350 fflush(stdout);
6351 fflush(stderr);
6352 }
6353 #endif
6354
6355 /*****************************************************************************/
6356 #include <stdlib.h>
6357 #include <string.h>
6358
6359 int fflush (FILE *stream);
6360
6361 /* Opcode types */
6362 enum {
6363 PPC_DIRECT = 0, /* Opcode routine */
6364 PPC_INDIRECT = 1, /* Indirect opcode table */
6365 };
6366
6367 static inline int is_indirect_opcode (void *handler)
6368 {
6369 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
6370 }
6371
6372 static inline opc_handler_t **ind_table(void *handler)
6373 {
6374 return (opc_handler_t **)((unsigned long)handler & ~3);
6375 }
6376
6377 /* Instruction table creation */
6378 /* Opcodes tables creation */
6379 static void fill_new_table (opc_handler_t **table, int len)
6380 {
6381 int i;
6382
6383 for (i = 0; i < len; i++)
6384 table[i] = &invalid_handler;
6385 }
6386
6387 static int create_new_table (opc_handler_t **table, unsigned char idx)
6388 {
6389 opc_handler_t **tmp;
6390
6391 tmp = malloc(0x20 * sizeof(opc_handler_t));
6392 if (tmp == NULL)
6393 return -1;
6394 fill_new_table(tmp, 0x20);
6395 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
6396
6397 return 0;
6398 }
6399
6400 static int insert_in_table (opc_handler_t **table, unsigned char idx,
6401 opc_handler_t *handler)
6402 {
6403 if (table[idx] != &invalid_handler)
6404 return -1;
6405 table[idx] = handler;
6406
6407 return 0;
6408 }
6409
6410 static int register_direct_insn (opc_handler_t **ppc_opcodes,
6411 unsigned char idx, opc_handler_t *handler)
6412 {
6413 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
6414 printf("*** ERROR: opcode %02x already assigned in main "
6415 "opcode table\n", idx);
6416 return -1;
6417 }
6418
6419 return 0;
6420 }
6421
6422 static int register_ind_in_table (opc_handler_t **table,
6423 unsigned char idx1, unsigned char idx2,
6424 opc_handler_t *handler)
6425 {
6426 if (table[idx1] == &invalid_handler) {
6427 if (create_new_table(table, idx1) < 0) {
6428 printf("*** ERROR: unable to create indirect table "
6429 "idx=%02x\n", idx1);
6430 return -1;
6431 }
6432 } else {
6433 if (!is_indirect_opcode(table[idx1])) {
6434 printf("*** ERROR: idx %02x already assigned to a direct "
6435 "opcode\n", idx1);
6436 return -1;
6437 }
6438 }
6439 if (handler != NULL &&
6440 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
6441 printf("*** ERROR: opcode %02x already assigned in "
6442 "opcode table %02x\n", idx2, idx1);
6443 return -1;
6444 }
6445
6446 return 0;
6447 }
6448
6449 static int register_ind_insn (opc_handler_t **ppc_opcodes,
6450 unsigned char idx1, unsigned char idx2,
6451 opc_handler_t *handler)
6452 {
6453 int ret;
6454
6455 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
6456
6457 return ret;
6458 }
6459
6460 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
6461 unsigned char idx1, unsigned char idx2,
6462 unsigned char idx3, opc_handler_t *handler)
6463 {
6464 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
6465 printf("*** ERROR: unable to join indirect table idx "
6466 "[%02x-%02x]\n", idx1, idx2);
6467 return -1;
6468 }
6469 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
6470 handler) < 0) {
6471 printf("*** ERROR: unable to insert opcode "
6472 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
6473 return -1;
6474 }
6475
6476 return 0;
6477 }
6478
6479 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
6480 {
6481 if (insn->opc2 != 0xFF) {
6482 if (insn->opc3 != 0xFF) {
6483 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
6484 insn->opc3, &insn->handler) < 0)
6485 return -1;
6486 } else {
6487 if (register_ind_insn(ppc_opcodes, insn->opc1,
6488 insn->opc2, &insn->handler) < 0)
6489 return -1;
6490 }
6491 } else {
6492 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
6493 return -1;
6494 }
6495
6496 return 0;
6497 }
6498
6499 static int test_opcode_table (opc_handler_t **table, int len)
6500 {
6501 int i, count, tmp;
6502
6503 for (i = 0, count = 0; i < len; i++) {
6504 /* Consistency fixup */
6505 if (table[i] == NULL)
6506 table[i] = &invalid_handler;
6507 if (table[i] != &invalid_handler) {
6508 if (is_indirect_opcode(table[i])) {
6509 tmp = test_opcode_table(ind_table(table[i]), 0x20);
6510 if (tmp == 0) {
6511 free(table[i]);
6512 table[i] = &invalid_handler;
6513 } else {
6514 count++;
6515 }
6516 } else {
6517 count++;
6518 }
6519 }
6520 }
6521
6522 return count;
6523 }
6524
6525 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
6526 {
6527 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
6528 printf("*** WARNING: no opcode defined !\n");
6529 }
6530
6531 /*****************************************************************************/
6532 static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
6533 {
6534 opcode_t *opc, *start, *end;
6535
6536 fill_new_table(env->opcodes, 0x40);
6537 if (&opc_start < &opc_end) {
6538 start = &opc_start;
6539 end = &opc_end;
6540 } else {
6541 start = &opc_end;
6542 end = &opc_start;
6543 }
6544 for (opc = start + 1; opc != end; opc++) {
6545 if ((opc->handler.type & def->insns_flags) != 0) {
6546 if (register_insn(env->opcodes, opc) < 0) {
6547 printf("*** ERROR initializing PowerPC instruction "
6548 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
6549 opc->opc3);
6550 return -1;
6551 }
6552 }
6553 }
6554 fix_opcode_tables(env->opcodes);
6555 fflush(stdout);
6556 fflush(stderr);
6557
6558 return 0;
6559 }
6560
6561 #if defined(PPC_DUMP_CPU)
6562 static void dump_ppc_insns (CPUPPCState *env)
6563 {
6564 opc_handler_t **table, *handler;
6565 uint8_t opc1, opc2, opc3;
6566
6567 printf("Instructions set:\n");
6568 /* opc1 is 6 bits long */
6569 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
6570 table = env->opcodes;
6571 handler = table[opc1];
6572 if (is_indirect_opcode(handler)) {
6573 /* opc2 is 5 bits long */
6574 for (opc2 = 0; opc2 < 0x20; opc2++) {
6575 table = env->opcodes;
6576 handler = env->opcodes[opc1];
6577 table = ind_table(handler);
6578 handler = table[opc2];
6579 if (is_indirect_opcode(handler)) {
6580 table = ind_table(handler);
6581 /* opc3 is 5 bits long */
6582 for (opc3 = 0; opc3 < 0x20; opc3++) {
6583 handler = table[opc3];
6584 if (handler->handler != &gen_invalid) {
6585 printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
6586 opc1, opc2, opc3, opc1, (opc3 << 5) | opc2,
6587 handler->oname);
6588 }
6589 }
6590 } else {
6591 if (handler->handler != &gen_invalid) {
6592 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
6593 opc1, opc2, opc1, opc2, handler->oname);
6594 }
6595 }
6596 }
6597 } else {
6598 if (handler->handler != &gen_invalid) {
6599 printf("INSN: %02x -- -- (%02d ----) : %s\n",
6600 opc1, opc1, handler->oname);
6601 }
6602 }
6603 }
6604 }
6605 #endif
6606
6607 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
6608 {
6609 env->msr_mask = def->msr_mask;
6610 env->mmu_model = def->mmu_model;
6611 env->excp_model = def->excp_model;
6612 env->bus_model = def->bus_model;
6613 env->flags = def->flags;
6614 env->bfd_mach = def->bfd_mach;
6615 env->check_pow = def->check_pow;
6616 if (create_ppc_opcodes(env, def) < 0)
6617 return -1;
6618 init_ppc_proc(env, def);
6619 #if defined(PPC_DUMP_CPU)
6620 {
6621 const unsigned char *mmu_model, *excp_model, *bus_model;
6622 switch (env->mmu_model) {
6623 case POWERPC_MMU_32B:
6624 mmu_model = "PowerPC 32";
6625 break;
6626 case POWERPC_MMU_SOFT_6xx:
6627 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
6628 break;
6629 case POWERPC_MMU_SOFT_74xx:
6630 mmu_model = "PowerPC 74xx with software driven TLBs";
6631 break;
6632 case POWERPC_MMU_SOFT_4xx:
6633 mmu_model = "PowerPC 4xx with software driven TLBs";
6634 break;
6635 case POWERPC_MMU_SOFT_4xx_Z:
6636 mmu_model = "PowerPC 4xx with software driven TLBs "
6637 "and zones protections";
6638 break;
6639 case POWERPC_MMU_REAL_4xx:
6640 mmu_model = "PowerPC 4xx real mode only";
6641 break;
6642 case POWERPC_MMU_BOOKE:
6643 mmu_model = "PowerPC BookE";
6644 break;
6645 case POWERPC_MMU_BOOKE_FSL:
6646 mmu_model = "PowerPC BookE FSL";
6647 break;
6648 #if defined (TARGET_PPC64)
6649 case POWERPC_MMU_64B:
6650 mmu_model = "PowerPC 64";
6651 break;
6652 #endif
6653 default:
6654 mmu_model = "Unknown or invalid";
6655 break;
6656 }
6657 switch (env->excp_model) {
6658 case POWERPC_EXCP_STD:
6659 excp_model = "PowerPC";
6660 break;
6661 case POWERPC_EXCP_40x:
6662 excp_model = "PowerPC 40x";
6663 break;
6664 case POWERPC_EXCP_601:
6665 excp_model = "PowerPC 601";
6666 break;
6667 case POWERPC_EXCP_602:
6668 excp_model = "PowerPC 602";
6669 break;
6670 case POWERPC_EXCP_603:
6671 excp_model = "PowerPC 603";
6672 break;
6673 case POWERPC_EXCP_603E:
6674 excp_model = "PowerPC 603e";
6675 break;
6676 case POWERPC_EXCP_604:
6677 excp_model = "PowerPC 604";
6678 break;
6679 case POWERPC_EXCP_7x0:
6680 excp_model = "PowerPC 740/750";
6681 break;
6682 case POWERPC_EXCP_7x5:
6683 excp_model = "PowerPC 745/755";
6684 break;
6685 case POWERPC_EXCP_74xx:
6686 excp_model = "PowerPC 74xx";
6687 break;
6688 case POWERPC_EXCP_BOOKE:
6689 excp_model = "PowerPC BookE";
6690 break;
6691 #if defined (TARGET_PPC64)
6692 case POWERPC_EXCP_970:
6693 excp_model = "PowerPC 970";
6694 break;
6695 #endif
6696 default:
6697 excp_model = "Unknown or invalid";
6698 break;
6699 }
6700 switch (env->bus_model) {
6701 case PPC_FLAGS_INPUT_6xx:
6702 bus_model = "PowerPC 6xx";
6703 break;
6704 case PPC_FLAGS_INPUT_BookE:
6705 bus_model = "PowerPC BookE";
6706 break;
6707 case PPC_FLAGS_INPUT_405:
6708 bus_model = "PowerPC 405";
6709 break;
6710 case PPC_FLAGS_INPUT_401:
6711 bus_model = "PowerPC 401/403";
6712 break;
6713 #if defined (TARGET_PPC64)
6714 case PPC_FLAGS_INPUT_970:
6715 bus_model = "PowerPC 970";
6716 break;
6717 #endif
6718 default:
6719 bus_model = "Unknown or invalid";
6720 break;
6721 }
6722 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
6723 " MMU model : %s\n",
6724 def->name, def->pvr, def->msr_mask, mmu_model);
6725 #if !defined(CONFIG_USER_ONLY)
6726 if (env->tlb != NULL) {
6727 printf(" %d %s TLB in %d ways\n",
6728 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
6729 env->nb_ways);
6730 }
6731 #endif
6732 printf(" Exceptions model : %s\n"
6733 " Bus model : %s\n",
6734 excp_model, bus_model);
6735 printf(" MSR features :\n");
6736 if (env->flags & POWERPC_FLAG_SPE)
6737 printf(" signal processing engine enable"
6738 "\n");
6739 else if (env->flags & POWERPC_FLAG_VRE)
6740 printf(" vector processor enable\n");
6741 if (env->flags & POWERPC_FLAG_TGPR)
6742 printf(" temporary GPRs\n");
6743 else if (env->flags & POWERPC_FLAG_CE)
6744 printf(" critical input enable\n");
6745 if (env->flags & POWERPC_FLAG_SE)
6746 printf(" single-step trace mode\n");
6747 else if (env->flags & POWERPC_FLAG_DWE)
6748 printf(" debug wait enable\n");
6749 else if (env->flags & POWERPC_FLAG_UBLE)
6750 printf(" user BTB lock enable\n");
6751 if (env->flags & POWERPC_FLAG_BE)
6752 printf(" branch-step trace mode\n");
6753 else if (env->flags & POWERPC_FLAG_DE)
6754 printf(" debug interrupt enable\n");
6755 if (env->flags & POWERPC_FLAG_PX)
6756 printf(" inclusive protection\n");
6757 else if (env->flags & POWERPC_FLAG_PMM)
6758 printf(" performance monitor mark\n");
6759 if (env->flags == POWERPC_FLAG_NONE)
6760 printf(" none\n");
6761 }
6762 dump_ppc_insns(env);
6763 dump_ppc_sprs(env);
6764 fflush(stdout);
6765 #endif
6766
6767 return 0;
6768 }
6769
6770 static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
6771 {
6772 const ppc_def_t *ret;
6773 uint32_t pvr_rev;
6774 int i, best, match, best_match, max;
6775
6776 ret = NULL;
6777 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6778 best = -1;
6779 pvr_rev = pvr & 0xFFFF;
6780 /* We want all specified bits to match */
6781 best_match = 32 - ctz32(pvr_rev);
6782 for (i = 0; i < max; i++) {
6783 /* We check that the 16 higher bits are the same to ensure the CPU
6784 * model will be the choosen one.
6785 */
6786 if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
6787 /* We want as much as possible of the low-level 16 bits
6788 * to be the same but we allow inexact matches.
6789 */
6790 match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
6791 /* We check '>=' instead of '>' because the PPC_defs table
6792 * is ordered by increasing revision.
6793 * Then, we will match the higher revision compatible
6794 * with the requested PVR
6795 */
6796 if (match >= best_match) {
6797 best = i;
6798 best_match = match;
6799 }
6800 }
6801 }
6802 if (best != -1)
6803 ret = &ppc_defs[best];
6804
6805 return ret;
6806 }
6807
6808 #include <ctype.h>
6809
6810 const ppc_def_t *cpu_ppc_find_by_name (const unsigned char *name)
6811 {
6812 const ppc_def_t *ret;
6813 const unsigned char *p;
6814 int i, max, len;
6815
6816 /* Check if the given name is a PVR */
6817 len = strlen(name);
6818 if (len == 10 && name[0] == '0' && name[1] == 'x') {
6819 p = name + 2;
6820 goto check_pvr;
6821 } else if (len == 8) {
6822 p = name;
6823 check_pvr:
6824 for (i = 0; i < 8; i++) {
6825 if (!isxdigit(*p++))
6826 break;
6827 }
6828 if (i == 8)
6829 return ppc_find_by_pvr(strtoul(name, NULL, 16));
6830 }
6831 ret = NULL;
6832 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6833 for (i = 0; i < max; i++) {
6834 if (strcasecmp(name, ppc_defs[i].name) == 0) {
6835 ret = &ppc_defs[i];
6836 break;
6837 }
6838 }
6839
6840 return ret;
6841 }
6842
6843 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
6844 {
6845 int i, max;
6846
6847 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6848 for (i = 0; i < max; i++) {
6849 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
6850 ppc_defs[i].name, ppc_defs[i].pvr);
6851 }
6852 }
Qemu copy for testing