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[qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "disas/bfd.h"
22 #include "exec/gdbstub.h"
23 #include <sysemu/kvm.h>
24 #include "kvm_ppc.h"
25 #include "sysemu/arch_init.h"
26 #include "sysemu/cpus.h"
27 #include "cpu-models.h"
28
29 //#define PPC_DUMP_CPU
30 //#define PPC_DEBUG_SPR
31 //#define PPC_DUMP_SPR_ACCESSES
32
33 /* For user-mode emulation, we don't emulate any IRQ controller */
34 #if defined(CONFIG_USER_ONLY)
35 #define PPC_IRQ_INIT_FN(name) \
36 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
37 { \
38 }
39 #else
40 #define PPC_IRQ_INIT_FN(name) \
41 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
42 #endif
43
44 PPC_IRQ_INIT_FN(40x);
45 PPC_IRQ_INIT_FN(6xx);
46 PPC_IRQ_INIT_FN(970);
47 PPC_IRQ_INIT_FN(POWER7);
48 PPC_IRQ_INIT_FN(e500);
49
50 /* Generic callbacks:
51 * do nothing but store/retrieve spr value
52 */
53 static void spr_load_dump_spr(int sprn)
54 {
55 #ifdef PPC_DUMP_SPR_ACCESSES
56 TCGv_i32 t0 = tcg_const_i32(sprn);
57 gen_helper_load_dump_spr(cpu_env, t0);
58 tcg_temp_free_i32(t0);
59 #endif
60 }
61
62 static void spr_read_generic (void *opaque, int gprn, int sprn)
63 {
64 gen_load_spr(cpu_gpr[gprn], sprn);
65 spr_load_dump_spr(sprn);
66 }
67
68 static void spr_store_dump_spr(int sprn)
69 {
70 #ifdef PPC_DUMP_SPR_ACCESSES
71 TCGv_i32 t0 = tcg_const_i32(sprn);
72 gen_helper_store_dump_spr(cpu_env, t0);
73 tcg_temp_free_i32(t0);
74 #endif
75 }
76
77 static void spr_write_generic (void *opaque, int sprn, int gprn)
78 {
79 gen_store_spr(sprn, cpu_gpr[gprn]);
80 spr_store_dump_spr(sprn);
81 }
82
83 #if !defined(CONFIG_USER_ONLY)
84 static void spr_write_generic32(void *opaque, int sprn, int gprn)
85 {
86 #ifdef TARGET_PPC64
87 TCGv t0 = tcg_temp_new();
88 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
89 gen_store_spr(sprn, t0);
90 tcg_temp_free(t0);
91 spr_store_dump_spr(sprn);
92 #else
93 spr_write_generic(opaque, sprn, gprn);
94 #endif
95 }
96
97 static void spr_write_clear (void *opaque, int sprn, int gprn)
98 {
99 TCGv t0 = tcg_temp_new();
100 TCGv t1 = tcg_temp_new();
101 gen_load_spr(t0, sprn);
102 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
103 tcg_gen_and_tl(t0, t0, t1);
104 gen_store_spr(sprn, t0);
105 tcg_temp_free(t0);
106 tcg_temp_free(t1);
107 }
108 #endif
109
110 /* SPR common to all PowerPC */
111 /* XER */
112 static void spr_read_xer (void *opaque, int gprn, int sprn)
113 {
114 gen_read_xer(cpu_gpr[gprn]);
115 }
116
117 static void spr_write_xer (void *opaque, int sprn, int gprn)
118 {
119 gen_write_xer(cpu_gpr[gprn]);
120 }
121
122 /* LR */
123 static void spr_read_lr (void *opaque, int gprn, int sprn)
124 {
125 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
126 }
127
128 static void spr_write_lr (void *opaque, int sprn, int gprn)
129 {
130 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
131 }
132
133 /* CFAR */
134 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
135 static void spr_read_cfar (void *opaque, int gprn, int sprn)
136 {
137 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
138 }
139
140 static void spr_write_cfar (void *opaque, int sprn, int gprn)
141 {
142 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
143 }
144 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
145
146 /* CTR */
147 static void spr_read_ctr (void *opaque, int gprn, int sprn)
148 {
149 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
150 }
151
152 static void spr_write_ctr (void *opaque, int sprn, int gprn)
153 {
154 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
155 }
156
157 /* User read access to SPR */
158 /* USPRx */
159 /* UMMCRx */
160 /* UPMCx */
161 /* USIA */
162 /* UDECR */
163 static void spr_read_ureg (void *opaque, int gprn, int sprn)
164 {
165 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
166 }
167
168 /* SPR common to all non-embedded PowerPC */
169 /* DECR */
170 #if !defined(CONFIG_USER_ONLY)
171 static void spr_read_decr (void *opaque, int gprn, int sprn)
172 {
173 if (use_icount) {
174 gen_io_start();
175 }
176 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
177 if (use_icount) {
178 gen_io_end();
179 gen_stop_exception(opaque);
180 }
181 }
182
183 static void spr_write_decr (void *opaque, int sprn, int gprn)
184 {
185 if (use_icount) {
186 gen_io_start();
187 }
188 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
189 if (use_icount) {
190 gen_io_end();
191 gen_stop_exception(opaque);
192 }
193 }
194 #endif
195
196 /* SPR common to all non-embedded PowerPC, except 601 */
197 /* Time base */
198 static void spr_read_tbl (void *opaque, int gprn, int sprn)
199 {
200 if (use_icount) {
201 gen_io_start();
202 }
203 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
204 if (use_icount) {
205 gen_io_end();
206 gen_stop_exception(opaque);
207 }
208 }
209
210 static void spr_read_tbu (void *opaque, int gprn, int sprn)
211 {
212 if (use_icount) {
213 gen_io_start();
214 }
215 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
216 if (use_icount) {
217 gen_io_end();
218 gen_stop_exception(opaque);
219 }
220 }
221
222 __attribute__ (( unused ))
223 static void spr_read_atbl (void *opaque, int gprn, int sprn)
224 {
225 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
226 }
227
228 __attribute__ (( unused ))
229 static void spr_read_atbu (void *opaque, int gprn, int sprn)
230 {
231 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
232 }
233
234 #if !defined(CONFIG_USER_ONLY)
235 static void spr_write_tbl (void *opaque, int sprn, int gprn)
236 {
237 if (use_icount) {
238 gen_io_start();
239 }
240 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
241 if (use_icount) {
242 gen_io_end();
243 gen_stop_exception(opaque);
244 }
245 }
246
247 static void spr_write_tbu (void *opaque, int sprn, int gprn)
248 {
249 if (use_icount) {
250 gen_io_start();
251 }
252 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
253 if (use_icount) {
254 gen_io_end();
255 gen_stop_exception(opaque);
256 }
257 }
258
259 __attribute__ (( unused ))
260 static void spr_write_atbl (void *opaque, int sprn, int gprn)
261 {
262 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
263 }
264
265 __attribute__ (( unused ))
266 static void spr_write_atbu (void *opaque, int sprn, int gprn)
267 {
268 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
269 }
270
271 #if defined(TARGET_PPC64)
272 __attribute__ (( unused ))
273 static void spr_read_purr (void *opaque, int gprn, int sprn)
274 {
275 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
276 }
277 #endif
278 #endif
279
280 #if !defined(CONFIG_USER_ONLY)
281 /* IBAT0U...IBAT0U */
282 /* IBAT0L...IBAT7L */
283 static void spr_read_ibat (void *opaque, int gprn, int sprn)
284 {
285 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
286 }
287
288 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
289 {
290 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
291 }
292
293 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
294 {
295 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
296 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
297 tcg_temp_free_i32(t0);
298 }
299
300 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
301 {
302 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
303 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
304 tcg_temp_free_i32(t0);
305 }
306
307 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
308 {
309 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
310 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
311 tcg_temp_free_i32(t0);
312 }
313
314 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
315 {
316 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
317 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
318 tcg_temp_free_i32(t0);
319 }
320
321 /* DBAT0U...DBAT7U */
322 /* DBAT0L...DBAT7L */
323 static void spr_read_dbat (void *opaque, int gprn, int sprn)
324 {
325 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
326 }
327
328 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
329 {
330 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
331 }
332
333 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
334 {
335 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
336 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
337 tcg_temp_free_i32(t0);
338 }
339
340 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
341 {
342 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
343 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
344 tcg_temp_free_i32(t0);
345 }
346
347 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
348 {
349 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
350 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
351 tcg_temp_free_i32(t0);
352 }
353
354 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
355 {
356 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
357 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
358 tcg_temp_free_i32(t0);
359 }
360
361 /* SDR1 */
362 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
363 {
364 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
365 }
366
367 /* 64 bits PowerPC specific SPRs */
368 #if defined(TARGET_PPC64)
369 static void spr_read_hior (void *opaque, int gprn, int sprn)
370 {
371 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
372 }
373
374 static void spr_write_hior (void *opaque, int sprn, int gprn)
375 {
376 TCGv t0 = tcg_temp_new();
377 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
378 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
379 tcg_temp_free(t0);
380 }
381 #endif
382 #endif
383
384 /* PowerPC 601 specific registers */
385 /* RTC */
386 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
387 {
388 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
389 }
390
391 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
392 {
393 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
394 }
395
396 #if !defined(CONFIG_USER_ONLY)
397 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
398 {
399 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
400 }
401
402 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
403 {
404 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
405 }
406
407 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
408 {
409 DisasContext *ctx = opaque;
410
411 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
412 /* Must stop the translation as endianness may have changed */
413 gen_stop_exception(ctx);
414 }
415 #endif
416
417 /* Unified bats */
418 #if !defined(CONFIG_USER_ONLY)
419 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
420 {
421 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
422 }
423
424 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
425 {
426 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
427 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
428 tcg_temp_free_i32(t0);
429 }
430
431 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
432 {
433 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
434 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
435 tcg_temp_free_i32(t0);
436 }
437 #endif
438
439 /* PowerPC 40x specific registers */
440 #if !defined(CONFIG_USER_ONLY)
441 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
442 {
443 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
444 }
445
446 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
447 {
448 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
449 }
450
451 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
452 {
453 DisasContext *ctx = opaque;
454
455 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
456 /* We must stop translation as we may have rebooted */
457 gen_stop_exception(ctx);
458 }
459
460 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
461 {
462 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
463 }
464
465 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
466 {
467 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
468 }
469
470 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
471 {
472 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
473 }
474 #endif
475
476 /* PowerPC 403 specific registers */
477 /* PBL1 / PBU1 / PBL2 / PBU2 */
478 #if !defined(CONFIG_USER_ONLY)
479 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
480 {
481 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
482 }
483
484 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
485 {
486 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
487 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
488 tcg_temp_free_i32(t0);
489 }
490
491 static void spr_write_pir (void *opaque, int sprn, int gprn)
492 {
493 TCGv t0 = tcg_temp_new();
494 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
495 gen_store_spr(SPR_PIR, t0);
496 tcg_temp_free(t0);
497 }
498 #endif
499
500 /* SPE specific registers */
501 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
502 {
503 TCGv_i32 t0 = tcg_temp_new_i32();
504 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
505 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
506 tcg_temp_free_i32(t0);
507 }
508
509 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
510 {
511 TCGv_i32 t0 = tcg_temp_new_i32();
512 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
513 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
514 tcg_temp_free_i32(t0);
515 }
516
517 #if !defined(CONFIG_USER_ONLY)
518 /* Callback used to write the exception vector base */
519 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
520 {
521 TCGv t0 = tcg_temp_new();
522 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
523 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
524 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
525 gen_store_spr(sprn, t0);
526 tcg_temp_free(t0);
527 }
528
529 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
530 {
531 DisasContext *ctx = opaque;
532 int sprn_offs;
533
534 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
535 sprn_offs = sprn - SPR_BOOKE_IVOR0;
536 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
537 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
538 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
539 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
540 } else {
541 printf("Trying to write an unknown exception vector %d %03x\n",
542 sprn, sprn);
543 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
544 return;
545 }
546
547 TCGv t0 = tcg_temp_new();
548 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
549 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
550 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
551 gen_store_spr(sprn, t0);
552 tcg_temp_free(t0);
553 }
554 #endif
555
556 static inline void vscr_init (CPUPPCState *env, uint32_t val)
557 {
558 env->vscr = val;
559 /* Altivec always uses round-to-nearest */
560 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
561 set_flush_to_zero(vscr_nj, &env->vec_status);
562 }
563
564 #ifdef CONFIG_USER_ONLY
565 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
566 oea_read, oea_write, one_reg_id, initial_value) \
567 _spr_register(env, num, name, uea_read, uea_write, initial_value)
568 #else
569 #if !defined(CONFIG_KVM)
570 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
571 oea_read, oea_write, one_reg_id, initial_value) \
572 _spr_register(env, num, name, uea_read, uea_write, \
573 oea_read, oea_write, initial_value)
574 #else
575 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
576 oea_read, oea_write, one_reg_id, initial_value) \
577 _spr_register(env, num, name, uea_read, uea_write, \
578 oea_read, oea_write, one_reg_id, initial_value)
579 #endif
580 #endif
581
582 #define spr_register(env, num, name, uea_read, uea_write, \
583 oea_read, oea_write, initial_value) \
584 spr_register_kvm(env, num, name, uea_read, uea_write, \
585 oea_read, oea_write, 0, initial_value)
586
587 static inline void _spr_register(CPUPPCState *env, int num,
588 const char *name,
589 void (*uea_read)(void *opaque, int gprn, int sprn),
590 void (*uea_write)(void *opaque, int sprn, int gprn),
591 #if !defined(CONFIG_USER_ONLY)
592
593 void (*oea_read)(void *opaque, int gprn, int sprn),
594 void (*oea_write)(void *opaque, int sprn, int gprn),
595 #endif
596 #if defined(CONFIG_KVM)
597 uint64_t one_reg_id,
598 #endif
599 target_ulong initial_value)
600 {
601 ppc_spr_t *spr;
602
603 spr = &env->spr_cb[num];
604 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
605 #if !defined(CONFIG_USER_ONLY)
606 spr->oea_read != NULL || spr->oea_write != NULL ||
607 #endif
608 spr->uea_read != NULL || spr->uea_write != NULL) {
609 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
610 exit(1);
611 }
612 #if defined(PPC_DEBUG_SPR)
613 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
614 name, initial_value);
615 #endif
616 spr->name = name;
617 spr->uea_read = uea_read;
618 spr->uea_write = uea_write;
619 #if !defined(CONFIG_USER_ONLY)
620 spr->oea_read = oea_read;
621 spr->oea_write = oea_write;
622 #endif
623 env->spr[num] = initial_value;
624 }
625
626 /* Generic PowerPC SPRs */
627 static void gen_spr_generic (CPUPPCState *env)
628 {
629 /* Integer processing */
630 spr_register(env, SPR_XER, "XER",
631 &spr_read_xer, &spr_write_xer,
632 &spr_read_xer, &spr_write_xer,
633 0x00000000);
634 /* Branch contol */
635 spr_register(env, SPR_LR, "LR",
636 &spr_read_lr, &spr_write_lr,
637 &spr_read_lr, &spr_write_lr,
638 0x00000000);
639 spr_register(env, SPR_CTR, "CTR",
640 &spr_read_ctr, &spr_write_ctr,
641 &spr_read_ctr, &spr_write_ctr,
642 0x00000000);
643 /* Interrupt processing */
644 spr_register(env, SPR_SRR0, "SRR0",
645 SPR_NOACCESS, SPR_NOACCESS,
646 &spr_read_generic, &spr_write_generic,
647 0x00000000);
648 spr_register(env, SPR_SRR1, "SRR1",
649 SPR_NOACCESS, SPR_NOACCESS,
650 &spr_read_generic, &spr_write_generic,
651 0x00000000);
652 /* Processor control */
653 spr_register(env, SPR_SPRG0, "SPRG0",
654 SPR_NOACCESS, SPR_NOACCESS,
655 &spr_read_generic, &spr_write_generic,
656 0x00000000);
657 spr_register(env, SPR_SPRG1, "SPRG1",
658 SPR_NOACCESS, SPR_NOACCESS,
659 &spr_read_generic, &spr_write_generic,
660 0x00000000);
661 spr_register(env, SPR_SPRG2, "SPRG2",
662 SPR_NOACCESS, SPR_NOACCESS,
663 &spr_read_generic, &spr_write_generic,
664 0x00000000);
665 spr_register(env, SPR_SPRG3, "SPRG3",
666 SPR_NOACCESS, SPR_NOACCESS,
667 &spr_read_generic, &spr_write_generic,
668 0x00000000);
669 }
670
671 /* SPR common to all non-embedded PowerPC, including 601 */
672 static void gen_spr_ne_601 (CPUPPCState *env)
673 {
674 /* Exception processing */
675 spr_register_kvm(env, SPR_DSISR, "DSISR",
676 SPR_NOACCESS, SPR_NOACCESS,
677 &spr_read_generic, &spr_write_generic,
678 KVM_REG_PPC_DSISR, 0x00000000);
679 spr_register_kvm(env, SPR_DAR, "DAR",
680 SPR_NOACCESS, SPR_NOACCESS,
681 &spr_read_generic, &spr_write_generic,
682 KVM_REG_PPC_DAR, 0x00000000);
683 /* Timer */
684 spr_register(env, SPR_DECR, "DECR",
685 SPR_NOACCESS, SPR_NOACCESS,
686 &spr_read_decr, &spr_write_decr,
687 0x00000000);
688 /* Memory management */
689 spr_register(env, SPR_SDR1, "SDR1",
690 SPR_NOACCESS, SPR_NOACCESS,
691 &spr_read_generic, &spr_write_sdr1,
692 0x00000000);
693 }
694
695 /* BATs 0-3 */
696 static void gen_low_BATs (CPUPPCState *env)
697 {
698 #if !defined(CONFIG_USER_ONLY)
699 spr_register(env, SPR_IBAT0U, "IBAT0U",
700 SPR_NOACCESS, SPR_NOACCESS,
701 &spr_read_ibat, &spr_write_ibatu,
702 0x00000000);
703 spr_register(env, SPR_IBAT0L, "IBAT0L",
704 SPR_NOACCESS, SPR_NOACCESS,
705 &spr_read_ibat, &spr_write_ibatl,
706 0x00000000);
707 spr_register(env, SPR_IBAT1U, "IBAT1U",
708 SPR_NOACCESS, SPR_NOACCESS,
709 &spr_read_ibat, &spr_write_ibatu,
710 0x00000000);
711 spr_register(env, SPR_IBAT1L, "IBAT1L",
712 SPR_NOACCESS, SPR_NOACCESS,
713 &spr_read_ibat, &spr_write_ibatl,
714 0x00000000);
715 spr_register(env, SPR_IBAT2U, "IBAT2U",
716 SPR_NOACCESS, SPR_NOACCESS,
717 &spr_read_ibat, &spr_write_ibatu,
718 0x00000000);
719 spr_register(env, SPR_IBAT2L, "IBAT2L",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_ibat, &spr_write_ibatl,
722 0x00000000);
723 spr_register(env, SPR_IBAT3U, "IBAT3U",
724 SPR_NOACCESS, SPR_NOACCESS,
725 &spr_read_ibat, &spr_write_ibatu,
726 0x00000000);
727 spr_register(env, SPR_IBAT3L, "IBAT3L",
728 SPR_NOACCESS, SPR_NOACCESS,
729 &spr_read_ibat, &spr_write_ibatl,
730 0x00000000);
731 spr_register(env, SPR_DBAT0U, "DBAT0U",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_dbat, &spr_write_dbatu,
734 0x00000000);
735 spr_register(env, SPR_DBAT0L, "DBAT0L",
736 SPR_NOACCESS, SPR_NOACCESS,
737 &spr_read_dbat, &spr_write_dbatl,
738 0x00000000);
739 spr_register(env, SPR_DBAT1U, "DBAT1U",
740 SPR_NOACCESS, SPR_NOACCESS,
741 &spr_read_dbat, &spr_write_dbatu,
742 0x00000000);
743 spr_register(env, SPR_DBAT1L, "DBAT1L",
744 SPR_NOACCESS, SPR_NOACCESS,
745 &spr_read_dbat, &spr_write_dbatl,
746 0x00000000);
747 spr_register(env, SPR_DBAT2U, "DBAT2U",
748 SPR_NOACCESS, SPR_NOACCESS,
749 &spr_read_dbat, &spr_write_dbatu,
750 0x00000000);
751 spr_register(env, SPR_DBAT2L, "DBAT2L",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_dbat, &spr_write_dbatl,
754 0x00000000);
755 spr_register(env, SPR_DBAT3U, "DBAT3U",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_dbat, &spr_write_dbatu,
758 0x00000000);
759 spr_register(env, SPR_DBAT3L, "DBAT3L",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_dbat, &spr_write_dbatl,
762 0x00000000);
763 env->nb_BATs += 4;
764 #endif
765 }
766
767 /* BATs 4-7 */
768 static void gen_high_BATs (CPUPPCState *env)
769 {
770 #if !defined(CONFIG_USER_ONLY)
771 spr_register(env, SPR_IBAT4U, "IBAT4U",
772 SPR_NOACCESS, SPR_NOACCESS,
773 &spr_read_ibat_h, &spr_write_ibatu_h,
774 0x00000000);
775 spr_register(env, SPR_IBAT4L, "IBAT4L",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_ibat_h, &spr_write_ibatl_h,
778 0x00000000);
779 spr_register(env, SPR_IBAT5U, "IBAT5U",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_ibat_h, &spr_write_ibatu_h,
782 0x00000000);
783 spr_register(env, SPR_IBAT5L, "IBAT5L",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_ibat_h, &spr_write_ibatl_h,
786 0x00000000);
787 spr_register(env, SPR_IBAT6U, "IBAT6U",
788 SPR_NOACCESS, SPR_NOACCESS,
789 &spr_read_ibat_h, &spr_write_ibatu_h,
790 0x00000000);
791 spr_register(env, SPR_IBAT6L, "IBAT6L",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_ibat_h, &spr_write_ibatl_h,
794 0x00000000);
795 spr_register(env, SPR_IBAT7U, "IBAT7U",
796 SPR_NOACCESS, SPR_NOACCESS,
797 &spr_read_ibat_h, &spr_write_ibatu_h,
798 0x00000000);
799 spr_register(env, SPR_IBAT7L, "IBAT7L",
800 SPR_NOACCESS, SPR_NOACCESS,
801 &spr_read_ibat_h, &spr_write_ibatl_h,
802 0x00000000);
803 spr_register(env, SPR_DBAT4U, "DBAT4U",
804 SPR_NOACCESS, SPR_NOACCESS,
805 &spr_read_dbat_h, &spr_write_dbatu_h,
806 0x00000000);
807 spr_register(env, SPR_DBAT4L, "DBAT4L",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_dbat_h, &spr_write_dbatl_h,
810 0x00000000);
811 spr_register(env, SPR_DBAT5U, "DBAT5U",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_dbat_h, &spr_write_dbatu_h,
814 0x00000000);
815 spr_register(env, SPR_DBAT5L, "DBAT5L",
816 SPR_NOACCESS, SPR_NOACCESS,
817 &spr_read_dbat_h, &spr_write_dbatl_h,
818 0x00000000);
819 spr_register(env, SPR_DBAT6U, "DBAT6U",
820 SPR_NOACCESS, SPR_NOACCESS,
821 &spr_read_dbat_h, &spr_write_dbatu_h,
822 0x00000000);
823 spr_register(env, SPR_DBAT6L, "DBAT6L",
824 SPR_NOACCESS, SPR_NOACCESS,
825 &spr_read_dbat_h, &spr_write_dbatl_h,
826 0x00000000);
827 spr_register(env, SPR_DBAT7U, "DBAT7U",
828 SPR_NOACCESS, SPR_NOACCESS,
829 &spr_read_dbat_h, &spr_write_dbatu_h,
830 0x00000000);
831 spr_register(env, SPR_DBAT7L, "DBAT7L",
832 SPR_NOACCESS, SPR_NOACCESS,
833 &spr_read_dbat_h, &spr_write_dbatl_h,
834 0x00000000);
835 env->nb_BATs += 4;
836 #endif
837 }
838
839 /* Generic PowerPC time base */
840 static void gen_tbl (CPUPPCState *env)
841 {
842 spr_register(env, SPR_VTBL, "TBL",
843 &spr_read_tbl, SPR_NOACCESS,
844 &spr_read_tbl, SPR_NOACCESS,
845 0x00000000);
846 spr_register(env, SPR_TBL, "TBL",
847 &spr_read_tbl, SPR_NOACCESS,
848 &spr_read_tbl, &spr_write_tbl,
849 0x00000000);
850 spr_register(env, SPR_VTBU, "TBU",
851 &spr_read_tbu, SPR_NOACCESS,
852 &spr_read_tbu, SPR_NOACCESS,
853 0x00000000);
854 spr_register(env, SPR_TBU, "TBU",
855 &spr_read_tbu, SPR_NOACCESS,
856 &spr_read_tbu, &spr_write_tbu,
857 0x00000000);
858 }
859
860 /* Softare table search registers */
861 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
862 {
863 #if !defined(CONFIG_USER_ONLY)
864 env->nb_tlb = nb_tlbs;
865 env->nb_ways = nb_ways;
866 env->id_tlbs = 1;
867 env->tlb_type = TLB_6XX;
868 spr_register(env, SPR_DMISS, "DMISS",
869 SPR_NOACCESS, SPR_NOACCESS,
870 &spr_read_generic, SPR_NOACCESS,
871 0x00000000);
872 spr_register(env, SPR_DCMP, "DCMP",
873 SPR_NOACCESS, SPR_NOACCESS,
874 &spr_read_generic, SPR_NOACCESS,
875 0x00000000);
876 spr_register(env, SPR_HASH1, "HASH1",
877 SPR_NOACCESS, SPR_NOACCESS,
878 &spr_read_generic, SPR_NOACCESS,
879 0x00000000);
880 spr_register(env, SPR_HASH2, "HASH2",
881 SPR_NOACCESS, SPR_NOACCESS,
882 &spr_read_generic, SPR_NOACCESS,
883 0x00000000);
884 spr_register(env, SPR_IMISS, "IMISS",
885 SPR_NOACCESS, SPR_NOACCESS,
886 &spr_read_generic, SPR_NOACCESS,
887 0x00000000);
888 spr_register(env, SPR_ICMP, "ICMP",
889 SPR_NOACCESS, SPR_NOACCESS,
890 &spr_read_generic, SPR_NOACCESS,
891 0x00000000);
892 spr_register(env, SPR_RPA, "RPA",
893 SPR_NOACCESS, SPR_NOACCESS,
894 &spr_read_generic, &spr_write_generic,
895 0x00000000);
896 #endif
897 }
898
899 /* SPR common to MPC755 and G2 */
900 static void gen_spr_G2_755 (CPUPPCState *env)
901 {
902 /* SGPRs */
903 spr_register(env, SPR_SPRG4, "SPRG4",
904 SPR_NOACCESS, SPR_NOACCESS,
905 &spr_read_generic, &spr_write_generic,
906 0x00000000);
907 spr_register(env, SPR_SPRG5, "SPRG5",
908 SPR_NOACCESS, SPR_NOACCESS,
909 &spr_read_generic, &spr_write_generic,
910 0x00000000);
911 spr_register(env, SPR_SPRG6, "SPRG6",
912 SPR_NOACCESS, SPR_NOACCESS,
913 &spr_read_generic, &spr_write_generic,
914 0x00000000);
915 spr_register(env, SPR_SPRG7, "SPRG7",
916 SPR_NOACCESS, SPR_NOACCESS,
917 &spr_read_generic, &spr_write_generic,
918 0x00000000);
919 }
920
921 /* SPR common to all 7xx PowerPC implementations */
922 static void gen_spr_7xx (CPUPPCState *env)
923 {
924 /* Breakpoints */
925 /* XXX : not implemented */
926 spr_register_kvm(env, SPR_DABR, "DABR",
927 SPR_NOACCESS, SPR_NOACCESS,
928 &spr_read_generic, &spr_write_generic,
929 KVM_REG_PPC_DABR, 0x00000000);
930 /* XXX : not implemented */
931 spr_register(env, SPR_IABR, "IABR",
932 SPR_NOACCESS, SPR_NOACCESS,
933 &spr_read_generic, &spr_write_generic,
934 0x00000000);
935 /* Cache management */
936 /* XXX : not implemented */
937 spr_register(env, SPR_ICTC, "ICTC",
938 SPR_NOACCESS, SPR_NOACCESS,
939 &spr_read_generic, &spr_write_generic,
940 0x00000000);
941 /* Performance monitors */
942 /* XXX : not implemented */
943 spr_register(env, SPR_MMCR0, "MMCR0",
944 SPR_NOACCESS, SPR_NOACCESS,
945 &spr_read_generic, &spr_write_generic,
946 0x00000000);
947 /* XXX : not implemented */
948 spr_register(env, SPR_MMCR1, "MMCR1",
949 SPR_NOACCESS, SPR_NOACCESS,
950 &spr_read_generic, &spr_write_generic,
951 0x00000000);
952 /* XXX : not implemented */
953 spr_register(env, SPR_PMC1, "PMC1",
954 SPR_NOACCESS, SPR_NOACCESS,
955 &spr_read_generic, &spr_write_generic,
956 0x00000000);
957 /* XXX : not implemented */
958 spr_register(env, SPR_PMC2, "PMC2",
959 SPR_NOACCESS, SPR_NOACCESS,
960 &spr_read_generic, &spr_write_generic,
961 0x00000000);
962 /* XXX : not implemented */
963 spr_register(env, SPR_PMC3, "PMC3",
964 SPR_NOACCESS, SPR_NOACCESS,
965 &spr_read_generic, &spr_write_generic,
966 0x00000000);
967 /* XXX : not implemented */
968 spr_register(env, SPR_PMC4, "PMC4",
969 SPR_NOACCESS, SPR_NOACCESS,
970 &spr_read_generic, &spr_write_generic,
971 0x00000000);
972 /* XXX : not implemented */
973 spr_register(env, SPR_SIAR, "SIAR",
974 SPR_NOACCESS, SPR_NOACCESS,
975 &spr_read_generic, SPR_NOACCESS,
976 0x00000000);
977 /* XXX : not implemented */
978 spr_register(env, SPR_UMMCR0, "UMMCR0",
979 &spr_read_ureg, SPR_NOACCESS,
980 &spr_read_ureg, SPR_NOACCESS,
981 0x00000000);
982 /* XXX : not implemented */
983 spr_register(env, SPR_UMMCR1, "UMMCR1",
984 &spr_read_ureg, SPR_NOACCESS,
985 &spr_read_ureg, SPR_NOACCESS,
986 0x00000000);
987 /* XXX : not implemented */
988 spr_register(env, SPR_UPMC1, "UPMC1",
989 &spr_read_ureg, SPR_NOACCESS,
990 &spr_read_ureg, SPR_NOACCESS,
991 0x00000000);
992 /* XXX : not implemented */
993 spr_register(env, SPR_UPMC2, "UPMC2",
994 &spr_read_ureg, SPR_NOACCESS,
995 &spr_read_ureg, SPR_NOACCESS,
996 0x00000000);
997 /* XXX : not implemented */
998 spr_register(env, SPR_UPMC3, "UPMC3",
999 &spr_read_ureg, SPR_NOACCESS,
1000 &spr_read_ureg, SPR_NOACCESS,
1001 0x00000000);
1002 /* XXX : not implemented */
1003 spr_register(env, SPR_UPMC4, "UPMC4",
1004 &spr_read_ureg, SPR_NOACCESS,
1005 &spr_read_ureg, SPR_NOACCESS,
1006 0x00000000);
1007 /* XXX : not implemented */
1008 spr_register(env, SPR_USIAR, "USIAR",
1009 &spr_read_ureg, SPR_NOACCESS,
1010 &spr_read_ureg, SPR_NOACCESS,
1011 0x00000000);
1012 /* External access control */
1013 /* XXX : not implemented */
1014 spr_register(env, SPR_EAR, "EAR",
1015 SPR_NOACCESS, SPR_NOACCESS,
1016 &spr_read_generic, &spr_write_generic,
1017 0x00000000);
1018 }
1019
1020 #ifdef TARGET_PPC64
1021 #ifndef CONFIG_USER_ONLY
1022 static void spr_read_uamr (void *opaque, int gprn, int sprn)
1023 {
1024 gen_load_spr(cpu_gpr[gprn], SPR_AMR);
1025 spr_load_dump_spr(SPR_AMR);
1026 }
1027
1028 static void spr_write_uamr (void *opaque, int sprn, int gprn)
1029 {
1030 gen_store_spr(SPR_AMR, cpu_gpr[gprn]);
1031 spr_store_dump_spr(SPR_AMR);
1032 }
1033
1034 static void spr_write_uamr_pr (void *opaque, int sprn, int gprn)
1035 {
1036 TCGv t0 = tcg_temp_new();
1037
1038 gen_load_spr(t0, SPR_UAMOR);
1039 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1040 gen_store_spr(SPR_AMR, t0);
1041 spr_store_dump_spr(SPR_AMR);
1042 }
1043 #endif /* CONFIG_USER_ONLY */
1044
1045 static void gen_spr_amr (CPUPPCState *env)
1046 {
1047 #ifndef CONFIG_USER_ONLY
1048 /* Virtual Page Class Key protection */
1049 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1050 * userspace accessible, 29 is privileged. So we only need to set
1051 * the kvm ONE_REG id on one of them, we use 29 */
1052 spr_register(env, SPR_UAMR, "UAMR",
1053 &spr_read_uamr, &spr_write_uamr_pr,
1054 &spr_read_uamr, &spr_write_uamr,
1055 0);
1056 spr_register_kvm(env, SPR_AMR, "AMR",
1057 SPR_NOACCESS, SPR_NOACCESS,
1058 &spr_read_generic, &spr_write_generic,
1059 KVM_REG_PPC_AMR, 0xffffffffffffffffULL);
1060 spr_register_kvm(env, SPR_UAMOR, "UAMOR",
1061 SPR_NOACCESS, SPR_NOACCESS,
1062 &spr_read_generic, &spr_write_generic,
1063 KVM_REG_PPC_UAMOR, 0);
1064 #endif /* !CONFIG_USER_ONLY */
1065 }
1066 #endif /* TARGET_PPC64 */
1067
1068 static void gen_spr_thrm (CPUPPCState *env)
1069 {
1070 /* Thermal management */
1071 /* XXX : not implemented */
1072 spr_register(env, SPR_THRM1, "THRM1",
1073 SPR_NOACCESS, SPR_NOACCESS,
1074 &spr_read_generic, &spr_write_generic,
1075 0x00000000);
1076 /* XXX : not implemented */
1077 spr_register(env, SPR_THRM2, "THRM2",
1078 SPR_NOACCESS, SPR_NOACCESS,
1079 &spr_read_generic, &spr_write_generic,
1080 0x00000000);
1081 /* XXX : not implemented */
1082 spr_register(env, SPR_THRM3, "THRM3",
1083 SPR_NOACCESS, SPR_NOACCESS,
1084 &spr_read_generic, &spr_write_generic,
1085 0x00000000);
1086 }
1087
1088 /* SPR specific to PowerPC 604 implementation */
1089 static void gen_spr_604 (CPUPPCState *env)
1090 {
1091 /* Processor identification */
1092 spr_register(env, SPR_PIR, "PIR",
1093 SPR_NOACCESS, SPR_NOACCESS,
1094 &spr_read_generic, &spr_write_pir,
1095 0x00000000);
1096 /* Breakpoints */
1097 /* XXX : not implemented */
1098 spr_register(env, SPR_IABR, "IABR",
1099 SPR_NOACCESS, SPR_NOACCESS,
1100 &spr_read_generic, &spr_write_generic,
1101 0x00000000);
1102 /* XXX : not implemented */
1103 spr_register_kvm(env, SPR_DABR, "DABR",
1104 SPR_NOACCESS, SPR_NOACCESS,
1105 &spr_read_generic, &spr_write_generic,
1106 KVM_REG_PPC_DABR, 0x00000000);
1107 /* Performance counters */
1108 /* XXX : not implemented */
1109 spr_register(env, SPR_MMCR0, "MMCR0",
1110 SPR_NOACCESS, SPR_NOACCESS,
1111 &spr_read_generic, &spr_write_generic,
1112 0x00000000);
1113 /* XXX : not implemented */
1114 spr_register(env, SPR_PMC1, "PMC1",
1115 SPR_NOACCESS, SPR_NOACCESS,
1116 &spr_read_generic, &spr_write_generic,
1117 0x00000000);
1118 /* XXX : not implemented */
1119 spr_register(env, SPR_PMC2, "PMC2",
1120 SPR_NOACCESS, SPR_NOACCESS,
1121 &spr_read_generic, &spr_write_generic,
1122 0x00000000);
1123 /* XXX : not implemented */
1124 spr_register(env, SPR_SIAR, "SIAR",
1125 SPR_NOACCESS, SPR_NOACCESS,
1126 &spr_read_generic, SPR_NOACCESS,
1127 0x00000000);
1128 /* XXX : not implemented */
1129 spr_register(env, SPR_SDA, "SDA",
1130 SPR_NOACCESS, SPR_NOACCESS,
1131 &spr_read_generic, SPR_NOACCESS,
1132 0x00000000);
1133 /* External access control */
1134 /* XXX : not implemented */
1135 spr_register(env, SPR_EAR, "EAR",
1136 SPR_NOACCESS, SPR_NOACCESS,
1137 &spr_read_generic, &spr_write_generic,
1138 0x00000000);
1139 }
1140
1141 /* SPR specific to PowerPC 603 implementation */
1142 static void gen_spr_603 (CPUPPCState *env)
1143 {
1144 /* External access control */
1145 /* XXX : not implemented */
1146 spr_register(env, SPR_EAR, "EAR",
1147 SPR_NOACCESS, SPR_NOACCESS,
1148 &spr_read_generic, &spr_write_generic,
1149 0x00000000);
1150 }
1151
1152 /* SPR specific to PowerPC G2 implementation */
1153 static void gen_spr_G2 (CPUPPCState *env)
1154 {
1155 /* Memory base address */
1156 /* MBAR */
1157 /* XXX : not implemented */
1158 spr_register(env, SPR_MBAR, "MBAR",
1159 SPR_NOACCESS, SPR_NOACCESS,
1160 &spr_read_generic, &spr_write_generic,
1161 0x00000000);
1162 /* Exception processing */
1163 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_generic, &spr_write_generic,
1166 0x00000000);
1167 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1168 SPR_NOACCESS, SPR_NOACCESS,
1169 &spr_read_generic, &spr_write_generic,
1170 0x00000000);
1171 /* Breakpoints */
1172 /* XXX : not implemented */
1173 spr_register(env, SPR_DABR, "DABR",
1174 SPR_NOACCESS, SPR_NOACCESS,
1175 &spr_read_generic, &spr_write_generic,
1176 0x00000000);
1177 /* XXX : not implemented */
1178 spr_register(env, SPR_DABR2, "DABR2",
1179 SPR_NOACCESS, SPR_NOACCESS,
1180 &spr_read_generic, &spr_write_generic,
1181 0x00000000);
1182 /* XXX : not implemented */
1183 spr_register(env, SPR_IABR, "IABR",
1184 SPR_NOACCESS, SPR_NOACCESS,
1185 &spr_read_generic, &spr_write_generic,
1186 0x00000000);
1187 /* XXX : not implemented */
1188 spr_register(env, SPR_IABR2, "IABR2",
1189 SPR_NOACCESS, SPR_NOACCESS,
1190 &spr_read_generic, &spr_write_generic,
1191 0x00000000);
1192 /* XXX : not implemented */
1193 spr_register(env, SPR_IBCR, "IBCR",
1194 SPR_NOACCESS, SPR_NOACCESS,
1195 &spr_read_generic, &spr_write_generic,
1196 0x00000000);
1197 /* XXX : not implemented */
1198 spr_register(env, SPR_DBCR, "DBCR",
1199 SPR_NOACCESS, SPR_NOACCESS,
1200 &spr_read_generic, &spr_write_generic,
1201 0x00000000);
1202 }
1203
1204 /* SPR specific to PowerPC 602 implementation */
1205 static void gen_spr_602 (CPUPPCState *env)
1206 {
1207 /* ESA registers */
1208 /* XXX : not implemented */
1209 spr_register(env, SPR_SER, "SER",
1210 SPR_NOACCESS, SPR_NOACCESS,
1211 &spr_read_generic, &spr_write_generic,
1212 0x00000000);
1213 /* XXX : not implemented */
1214 spr_register(env, SPR_SEBR, "SEBR",
1215 SPR_NOACCESS, SPR_NOACCESS,
1216 &spr_read_generic, &spr_write_generic,
1217 0x00000000);
1218 /* XXX : not implemented */
1219 spr_register(env, SPR_ESASRR, "ESASRR",
1220 SPR_NOACCESS, SPR_NOACCESS,
1221 &spr_read_generic, &spr_write_generic,
1222 0x00000000);
1223 /* Floating point status */
1224 /* XXX : not implemented */
1225 spr_register(env, SPR_SP, "SP",
1226 SPR_NOACCESS, SPR_NOACCESS,
1227 &spr_read_generic, &spr_write_generic,
1228 0x00000000);
1229 /* XXX : not implemented */
1230 spr_register(env, SPR_LT, "LT",
1231 SPR_NOACCESS, SPR_NOACCESS,
1232 &spr_read_generic, &spr_write_generic,
1233 0x00000000);
1234 /* Watchdog timer */
1235 /* XXX : not implemented */
1236 spr_register(env, SPR_TCR, "TCR",
1237 SPR_NOACCESS, SPR_NOACCESS,
1238 &spr_read_generic, &spr_write_generic,
1239 0x00000000);
1240 /* Interrupt base */
1241 spr_register(env, SPR_IBR, "IBR",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_generic, &spr_write_generic,
1244 0x00000000);
1245 /* XXX : not implemented */
1246 spr_register(env, SPR_IABR, "IABR",
1247 SPR_NOACCESS, SPR_NOACCESS,
1248 &spr_read_generic, &spr_write_generic,
1249 0x00000000);
1250 }
1251
1252 /* SPR specific to PowerPC 601 implementation */
1253 static void gen_spr_601 (CPUPPCState *env)
1254 {
1255 /* Multiplication/division register */
1256 /* MQ */
1257 spr_register(env, SPR_MQ, "MQ",
1258 &spr_read_generic, &spr_write_generic,
1259 &spr_read_generic, &spr_write_generic,
1260 0x00000000);
1261 /* RTC registers */
1262 spr_register(env, SPR_601_RTCU, "RTCU",
1263 SPR_NOACCESS, SPR_NOACCESS,
1264 SPR_NOACCESS, &spr_write_601_rtcu,
1265 0x00000000);
1266 spr_register(env, SPR_601_VRTCU, "RTCU",
1267 &spr_read_601_rtcu, SPR_NOACCESS,
1268 &spr_read_601_rtcu, SPR_NOACCESS,
1269 0x00000000);
1270 spr_register(env, SPR_601_RTCL, "RTCL",
1271 SPR_NOACCESS, SPR_NOACCESS,
1272 SPR_NOACCESS, &spr_write_601_rtcl,
1273 0x00000000);
1274 spr_register(env, SPR_601_VRTCL, "RTCL",
1275 &spr_read_601_rtcl, SPR_NOACCESS,
1276 &spr_read_601_rtcl, SPR_NOACCESS,
1277 0x00000000);
1278 /* Timer */
1279 #if 0 /* ? */
1280 spr_register(env, SPR_601_UDECR, "UDECR",
1281 &spr_read_decr, SPR_NOACCESS,
1282 &spr_read_decr, SPR_NOACCESS,
1283 0x00000000);
1284 #endif
1285 /* External access control */
1286 /* XXX : not implemented */
1287 spr_register(env, SPR_EAR, "EAR",
1288 SPR_NOACCESS, SPR_NOACCESS,
1289 &spr_read_generic, &spr_write_generic,
1290 0x00000000);
1291 /* Memory management */
1292 #if !defined(CONFIG_USER_ONLY)
1293 spr_register(env, SPR_IBAT0U, "IBAT0U",
1294 SPR_NOACCESS, SPR_NOACCESS,
1295 &spr_read_601_ubat, &spr_write_601_ubatu,
1296 0x00000000);
1297 spr_register(env, SPR_IBAT0L, "IBAT0L",
1298 SPR_NOACCESS, SPR_NOACCESS,
1299 &spr_read_601_ubat, &spr_write_601_ubatl,
1300 0x00000000);
1301 spr_register(env, SPR_IBAT1U, "IBAT1U",
1302 SPR_NOACCESS, SPR_NOACCESS,
1303 &spr_read_601_ubat, &spr_write_601_ubatu,
1304 0x00000000);
1305 spr_register(env, SPR_IBAT1L, "IBAT1L",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_601_ubat, &spr_write_601_ubatl,
1308 0x00000000);
1309 spr_register(env, SPR_IBAT2U, "IBAT2U",
1310 SPR_NOACCESS, SPR_NOACCESS,
1311 &spr_read_601_ubat, &spr_write_601_ubatu,
1312 0x00000000);
1313 spr_register(env, SPR_IBAT2L, "IBAT2L",
1314 SPR_NOACCESS, SPR_NOACCESS,
1315 &spr_read_601_ubat, &spr_write_601_ubatl,
1316 0x00000000);
1317 spr_register(env, SPR_IBAT3U, "IBAT3U",
1318 SPR_NOACCESS, SPR_NOACCESS,
1319 &spr_read_601_ubat, &spr_write_601_ubatu,
1320 0x00000000);
1321 spr_register(env, SPR_IBAT3L, "IBAT3L",
1322 SPR_NOACCESS, SPR_NOACCESS,
1323 &spr_read_601_ubat, &spr_write_601_ubatl,
1324 0x00000000);
1325 env->nb_BATs = 4;
1326 #endif
1327 }
1328
1329 static void gen_spr_74xx (CPUPPCState *env)
1330 {
1331 /* Processor identification */
1332 spr_register(env, SPR_PIR, "PIR",
1333 SPR_NOACCESS, SPR_NOACCESS,
1334 &spr_read_generic, &spr_write_pir,
1335 0x00000000);
1336 /* XXX : not implemented */
1337 spr_register(env, SPR_MMCR2, "MMCR2",
1338 SPR_NOACCESS, SPR_NOACCESS,
1339 &spr_read_generic, &spr_write_generic,
1340 0x00000000);
1341 /* XXX : not implemented */
1342 spr_register(env, SPR_UMMCR2, "UMMCR2",
1343 &spr_read_ureg, SPR_NOACCESS,
1344 &spr_read_ureg, SPR_NOACCESS,
1345 0x00000000);
1346 /* XXX: not implemented */
1347 spr_register(env, SPR_BAMR, "BAMR",
1348 SPR_NOACCESS, SPR_NOACCESS,
1349 &spr_read_generic, &spr_write_generic,
1350 0x00000000);
1351 /* XXX : not implemented */
1352 spr_register(env, SPR_MSSCR0, "MSSCR0",
1353 SPR_NOACCESS, SPR_NOACCESS,
1354 &spr_read_generic, &spr_write_generic,
1355 0x00000000);
1356 /* Hardware implementation registers */
1357 /* XXX : not implemented */
1358 spr_register(env, SPR_HID0, "HID0",
1359 SPR_NOACCESS, SPR_NOACCESS,
1360 &spr_read_generic, &spr_write_generic,
1361 0x00000000);
1362 /* XXX : not implemented */
1363 spr_register(env, SPR_HID1, "HID1",
1364 SPR_NOACCESS, SPR_NOACCESS,
1365 &spr_read_generic, &spr_write_generic,
1366 0x00000000);
1367 /* Altivec */
1368 spr_register(env, SPR_VRSAVE, "VRSAVE",
1369 &spr_read_generic, &spr_write_generic,
1370 &spr_read_generic, &spr_write_generic,
1371 0x00000000);
1372 /* XXX : not implemented */
1373 spr_register(env, SPR_L2CR, "L2CR",
1374 SPR_NOACCESS, SPR_NOACCESS,
1375 &spr_read_generic, &spr_write_generic,
1376 0x00000000);
1377 /* Not strictly an SPR */
1378 vscr_init(env, 0x00010000);
1379 }
1380
1381 static void gen_l3_ctrl (CPUPPCState *env)
1382 {
1383 /* L3CR */
1384 /* XXX : not implemented */
1385 spr_register(env, SPR_L3CR, "L3CR",
1386 SPR_NOACCESS, SPR_NOACCESS,
1387 &spr_read_generic, &spr_write_generic,
1388 0x00000000);
1389 /* L3ITCR0 */
1390 /* XXX : not implemented */
1391 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1392 SPR_NOACCESS, SPR_NOACCESS,
1393 &spr_read_generic, &spr_write_generic,
1394 0x00000000);
1395 /* L3PM */
1396 /* XXX : not implemented */
1397 spr_register(env, SPR_L3PM, "L3PM",
1398 SPR_NOACCESS, SPR_NOACCESS,
1399 &spr_read_generic, &spr_write_generic,
1400 0x00000000);
1401 }
1402
1403 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1404 {
1405 #if !defined(CONFIG_USER_ONLY)
1406 env->nb_tlb = nb_tlbs;
1407 env->nb_ways = nb_ways;
1408 env->id_tlbs = 1;
1409 env->tlb_type = TLB_6XX;
1410 /* XXX : not implemented */
1411 spr_register(env, SPR_PTEHI, "PTEHI",
1412 SPR_NOACCESS, SPR_NOACCESS,
1413 &spr_read_generic, &spr_write_generic,
1414 0x00000000);
1415 /* XXX : not implemented */
1416 spr_register(env, SPR_PTELO, "PTELO",
1417 SPR_NOACCESS, SPR_NOACCESS,
1418 &spr_read_generic, &spr_write_generic,
1419 0x00000000);
1420 /* XXX : not implemented */
1421 spr_register(env, SPR_TLBMISS, "TLBMISS",
1422 SPR_NOACCESS, SPR_NOACCESS,
1423 &spr_read_generic, &spr_write_generic,
1424 0x00000000);
1425 #endif
1426 }
1427
1428 #if !defined(CONFIG_USER_ONLY)
1429 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1430 {
1431 TCGv t0 = tcg_temp_new();
1432
1433 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1434 gen_store_spr(sprn, t0);
1435 tcg_temp_free(t0);
1436 }
1437
1438 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1439 {
1440 TCGv_i32 t0 = tcg_const_i32(sprn);
1441 gen_helper_booke206_tlbflush(cpu_env, t0);
1442 tcg_temp_free_i32(t0);
1443 }
1444
1445 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1446 {
1447 TCGv_i32 t0 = tcg_const_i32(sprn);
1448 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1449 tcg_temp_free_i32(t0);
1450 }
1451 #endif
1452
1453 static void gen_spr_usprgh (CPUPPCState *env)
1454 {
1455 spr_register(env, SPR_USPRG4, "USPRG4",
1456 &spr_read_ureg, SPR_NOACCESS,
1457 &spr_read_ureg, SPR_NOACCESS,
1458 0x00000000);
1459 spr_register(env, SPR_USPRG5, "USPRG5",
1460 &spr_read_ureg, SPR_NOACCESS,
1461 &spr_read_ureg, SPR_NOACCESS,
1462 0x00000000);
1463 spr_register(env, SPR_USPRG6, "USPRG6",
1464 &spr_read_ureg, SPR_NOACCESS,
1465 &spr_read_ureg, SPR_NOACCESS,
1466 0x00000000);
1467 spr_register(env, SPR_USPRG7, "USPRG7",
1468 &spr_read_ureg, SPR_NOACCESS,
1469 &spr_read_ureg, SPR_NOACCESS,
1470 0x00000000);
1471 }
1472
1473 /* PowerPC BookE SPR */
1474 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1475 {
1476 const char *ivor_names[64] = {
1477 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1478 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1479 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1480 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1481 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1482 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1483 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1484 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1485 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1486 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1487 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1488 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1489 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1490 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1491 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1492 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1493 };
1494 #define SPR_BOOKE_IVORxx (-1)
1495 int ivor_sprn[64] = {
1496 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1497 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1498 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1499 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1500 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1501 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1502 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1503 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1504 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1505 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1506 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1507 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1508 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1509 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1510 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1511 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1512 };
1513 int i;
1514
1515 /* Interrupt processing */
1516 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1517 SPR_NOACCESS, SPR_NOACCESS,
1518 &spr_read_generic, &spr_write_generic,
1519 0x00000000);
1520 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1521 SPR_NOACCESS, SPR_NOACCESS,
1522 &spr_read_generic, &spr_write_generic,
1523 0x00000000);
1524 /* Debug */
1525 /* XXX : not implemented */
1526 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1527 SPR_NOACCESS, SPR_NOACCESS,
1528 &spr_read_generic, &spr_write_generic,
1529 0x00000000);
1530 /* XXX : not implemented */
1531 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1532 SPR_NOACCESS, SPR_NOACCESS,
1533 &spr_read_generic, &spr_write_generic,
1534 0x00000000);
1535 /* XXX : not implemented */
1536 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1537 SPR_NOACCESS, SPR_NOACCESS,
1538 &spr_read_generic, &spr_write_generic,
1539 0x00000000);
1540 /* XXX : not implemented */
1541 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1542 SPR_NOACCESS, SPR_NOACCESS,
1543 &spr_read_generic, &spr_write_generic,
1544 0x00000000);
1545 /* XXX : not implemented */
1546 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1547 SPR_NOACCESS, SPR_NOACCESS,
1548 &spr_read_generic, &spr_write_40x_dbcr0,
1549 0x00000000);
1550 /* XXX : not implemented */
1551 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1552 SPR_NOACCESS, SPR_NOACCESS,
1553 &spr_read_generic, &spr_write_generic,
1554 0x00000000);
1555 /* XXX : not implemented */
1556 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1557 SPR_NOACCESS, SPR_NOACCESS,
1558 &spr_read_generic, &spr_write_generic,
1559 0x00000000);
1560 /* XXX : not implemented */
1561 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1562 SPR_NOACCESS, SPR_NOACCESS,
1563 &spr_read_generic, &spr_write_clear,
1564 0x00000000);
1565 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1566 SPR_NOACCESS, SPR_NOACCESS,
1567 &spr_read_generic, &spr_write_generic,
1568 0x00000000);
1569 spr_register(env, SPR_BOOKE_ESR, "ESR",
1570 SPR_NOACCESS, SPR_NOACCESS,
1571 &spr_read_generic, &spr_write_generic,
1572 0x00000000);
1573 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1574 SPR_NOACCESS, SPR_NOACCESS,
1575 &spr_read_generic, &spr_write_excp_prefix,
1576 0x00000000);
1577 /* Exception vectors */
1578 for (i = 0; i < 64; i++) {
1579 if (ivor_mask & (1ULL << i)) {
1580 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1581 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1582 exit(1);
1583 }
1584 spr_register(env, ivor_sprn[i], ivor_names[i],
1585 SPR_NOACCESS, SPR_NOACCESS,
1586 &spr_read_generic, &spr_write_excp_vector,
1587 0x00000000);
1588 }
1589 }
1590 spr_register(env, SPR_BOOKE_PID, "PID",
1591 SPR_NOACCESS, SPR_NOACCESS,
1592 &spr_read_generic, &spr_write_booke_pid,
1593 0x00000000);
1594 spr_register(env, SPR_BOOKE_TCR, "TCR",
1595 SPR_NOACCESS, SPR_NOACCESS,
1596 &spr_read_generic, &spr_write_booke_tcr,
1597 0x00000000);
1598 spr_register(env, SPR_BOOKE_TSR, "TSR",
1599 SPR_NOACCESS, SPR_NOACCESS,
1600 &spr_read_generic, &spr_write_booke_tsr,
1601 0x00000000);
1602 /* Timer */
1603 spr_register(env, SPR_DECR, "DECR",
1604 SPR_NOACCESS, SPR_NOACCESS,
1605 &spr_read_decr, &spr_write_decr,
1606 0x00000000);
1607 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1608 SPR_NOACCESS, SPR_NOACCESS,
1609 SPR_NOACCESS, &spr_write_generic,
1610 0x00000000);
1611 /* SPRGs */
1612 spr_register(env, SPR_USPRG0, "USPRG0",
1613 &spr_read_generic, &spr_write_generic,
1614 &spr_read_generic, &spr_write_generic,
1615 0x00000000);
1616 spr_register(env, SPR_SPRG4, "SPRG4",
1617 SPR_NOACCESS, SPR_NOACCESS,
1618 &spr_read_generic, &spr_write_generic,
1619 0x00000000);
1620 spr_register(env, SPR_SPRG5, "SPRG5",
1621 SPR_NOACCESS, SPR_NOACCESS,
1622 &spr_read_generic, &spr_write_generic,
1623 0x00000000);
1624 spr_register(env, SPR_SPRG6, "SPRG6",
1625 SPR_NOACCESS, SPR_NOACCESS,
1626 &spr_read_generic, &spr_write_generic,
1627 0x00000000);
1628 spr_register(env, SPR_SPRG7, "SPRG7",
1629 SPR_NOACCESS, SPR_NOACCESS,
1630 &spr_read_generic, &spr_write_generic,
1631 0x00000000);
1632 }
1633
1634 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1635 uint32_t maxsize, uint32_t flags,
1636 uint32_t nentries)
1637 {
1638 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1639 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1640 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1641 flags | nentries;
1642 }
1643
1644 /* BookE 2.06 storage control registers */
1645 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1646 uint32_t *tlbncfg)
1647 {
1648 #if !defined(CONFIG_USER_ONLY)
1649 const char *mas_names[8] = {
1650 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1651 };
1652 int mas_sprn[8] = {
1653 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1654 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1655 };
1656 int i;
1657
1658 /* TLB assist registers */
1659 /* XXX : not implemented */
1660 for (i = 0; i < 8; i++) {
1661 void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1662 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1663 uea_write = &spr_write_generic;
1664 }
1665 if (mas_mask & (1 << i)) {
1666 spr_register(env, mas_sprn[i], mas_names[i],
1667 SPR_NOACCESS, SPR_NOACCESS,
1668 &spr_read_generic, uea_write,
1669 0x00000000);
1670 }
1671 }
1672 if (env->nb_pids > 1) {
1673 /* XXX : not implemented */
1674 spr_register(env, SPR_BOOKE_PID1, "PID1",
1675 SPR_NOACCESS, SPR_NOACCESS,
1676 &spr_read_generic, &spr_write_booke_pid,
1677 0x00000000);
1678 }
1679 if (env->nb_pids > 2) {
1680 /* XXX : not implemented */
1681 spr_register(env, SPR_BOOKE_PID2, "PID2",
1682 SPR_NOACCESS, SPR_NOACCESS,
1683 &spr_read_generic, &spr_write_booke_pid,
1684 0x00000000);
1685 }
1686 /* XXX : not implemented */
1687 spr_register(env, SPR_MMUCFG, "MMUCFG",
1688 SPR_NOACCESS, SPR_NOACCESS,
1689 &spr_read_generic, SPR_NOACCESS,
1690 0x00000000); /* TOFIX */
1691 switch (env->nb_ways) {
1692 case 4:
1693 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, SPR_NOACCESS,
1696 tlbncfg[3]);
1697 /* Fallthru */
1698 case 3:
1699 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1700 SPR_NOACCESS, SPR_NOACCESS,
1701 &spr_read_generic, SPR_NOACCESS,
1702 tlbncfg[2]);
1703 /* Fallthru */
1704 case 2:
1705 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1706 SPR_NOACCESS, SPR_NOACCESS,
1707 &spr_read_generic, SPR_NOACCESS,
1708 tlbncfg[1]);
1709 /* Fallthru */
1710 case 1:
1711 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1712 SPR_NOACCESS, SPR_NOACCESS,
1713 &spr_read_generic, SPR_NOACCESS,
1714 tlbncfg[0]);
1715 /* Fallthru */
1716 case 0:
1717 default:
1718 break;
1719 }
1720 #endif
1721
1722 gen_spr_usprgh(env);
1723 }
1724
1725 /* SPR specific to PowerPC 440 implementation */
1726 static void gen_spr_440 (CPUPPCState *env)
1727 {
1728 /* Cache control */
1729 /* XXX : not implemented */
1730 spr_register(env, SPR_440_DNV0, "DNV0",
1731 SPR_NOACCESS, SPR_NOACCESS,
1732 &spr_read_generic, &spr_write_generic,
1733 0x00000000);
1734 /* XXX : not implemented */
1735 spr_register(env, SPR_440_DNV1, "DNV1",
1736 SPR_NOACCESS, SPR_NOACCESS,
1737 &spr_read_generic, &spr_write_generic,
1738 0x00000000);
1739 /* XXX : not implemented */
1740 spr_register(env, SPR_440_DNV2, "DNV2",
1741 SPR_NOACCESS, SPR_NOACCESS,
1742 &spr_read_generic, &spr_write_generic,
1743 0x00000000);
1744 /* XXX : not implemented */
1745 spr_register(env, SPR_440_DNV3, "DNV3",
1746 SPR_NOACCESS, SPR_NOACCESS,
1747 &spr_read_generic, &spr_write_generic,
1748 0x00000000);
1749 /* XXX : not implemented */
1750 spr_register(env, SPR_440_DTV0, "DTV0",
1751 SPR_NOACCESS, SPR_NOACCESS,
1752 &spr_read_generic, &spr_write_generic,
1753 0x00000000);
1754 /* XXX : not implemented */
1755 spr_register(env, SPR_440_DTV1, "DTV1",
1756 SPR_NOACCESS, SPR_NOACCESS,
1757 &spr_read_generic, &spr_write_generic,
1758 0x00000000);
1759 /* XXX : not implemented */
1760 spr_register(env, SPR_440_DTV2, "DTV2",
1761 SPR_NOACCESS, SPR_NOACCESS,
1762 &spr_read_generic, &spr_write_generic,
1763 0x00000000);
1764 /* XXX : not implemented */
1765 spr_register(env, SPR_440_DTV3, "DTV3",
1766 SPR_NOACCESS, SPR_NOACCESS,
1767 &spr_read_generic, &spr_write_generic,
1768 0x00000000);
1769 /* XXX : not implemented */
1770 spr_register(env, SPR_440_DVLIM, "DVLIM",
1771 SPR_NOACCESS, SPR_NOACCESS,
1772 &spr_read_generic, &spr_write_generic,
1773 0x00000000);
1774 /* XXX : not implemented */
1775 spr_register(env, SPR_440_INV0, "INV0",
1776 SPR_NOACCESS, SPR_NOACCESS,
1777 &spr_read_generic, &spr_write_generic,
1778 0x00000000);
1779 /* XXX : not implemented */
1780 spr_register(env, SPR_440_INV1, "INV1",
1781 SPR_NOACCESS, SPR_NOACCESS,
1782 &spr_read_generic, &spr_write_generic,
1783 0x00000000);
1784 /* XXX : not implemented */
1785 spr_register(env, SPR_440_INV2, "INV2",
1786 SPR_NOACCESS, SPR_NOACCESS,
1787 &spr_read_generic, &spr_write_generic,
1788 0x00000000);
1789 /* XXX : not implemented */
1790 spr_register(env, SPR_440_INV3, "INV3",
1791 SPR_NOACCESS, SPR_NOACCESS,
1792 &spr_read_generic, &spr_write_generic,
1793 0x00000000);
1794 /* XXX : not implemented */
1795 spr_register(env, SPR_440_ITV0, "ITV0",
1796 SPR_NOACCESS, SPR_NOACCESS,
1797 &spr_read_generic, &spr_write_generic,
1798 0x00000000);
1799 /* XXX : not implemented */
1800 spr_register(env, SPR_440_ITV1, "ITV1",
1801 SPR_NOACCESS, SPR_NOACCESS,
1802 &spr_read_generic, &spr_write_generic,
1803 0x00000000);
1804 /* XXX : not implemented */
1805 spr_register(env, SPR_440_ITV2, "ITV2",
1806 SPR_NOACCESS, SPR_NOACCESS,
1807 &spr_read_generic, &spr_write_generic,
1808 0x00000000);
1809 /* XXX : not implemented */
1810 spr_register(env, SPR_440_ITV3, "ITV3",
1811 SPR_NOACCESS, SPR_NOACCESS,
1812 &spr_read_generic, &spr_write_generic,
1813 0x00000000);
1814 /* XXX : not implemented */
1815 spr_register(env, SPR_440_IVLIM, "IVLIM",
1816 SPR_NOACCESS, SPR_NOACCESS,
1817 &spr_read_generic, &spr_write_generic,
1818 0x00000000);
1819 /* Cache debug */
1820 /* XXX : not implemented */
1821 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1822 SPR_NOACCESS, SPR_NOACCESS,
1823 &spr_read_generic, SPR_NOACCESS,
1824 0x00000000);
1825 /* XXX : not implemented */
1826 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1827 SPR_NOACCESS, SPR_NOACCESS,
1828 &spr_read_generic, SPR_NOACCESS,
1829 0x00000000);
1830 /* XXX : not implemented */
1831 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1832 SPR_NOACCESS, SPR_NOACCESS,
1833 &spr_read_generic, SPR_NOACCESS,
1834 0x00000000);
1835 /* XXX : not implemented */
1836 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1837 SPR_NOACCESS, SPR_NOACCESS,
1838 &spr_read_generic, SPR_NOACCESS,
1839 0x00000000);
1840 /* XXX : not implemented */
1841 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1842 SPR_NOACCESS, SPR_NOACCESS,
1843 &spr_read_generic, SPR_NOACCESS,
1844 0x00000000);
1845 /* XXX : not implemented */
1846 spr_register(env, SPR_440_DBDR, "DBDR",
1847 SPR_NOACCESS, SPR_NOACCESS,
1848 &spr_read_generic, &spr_write_generic,
1849 0x00000000);
1850 /* Processor control */
1851 spr_register(env, SPR_4xx_CCR0, "CCR0",
1852 SPR_NOACCESS, SPR_NOACCESS,
1853 &spr_read_generic, &spr_write_generic,
1854 0x00000000);
1855 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1856 SPR_NOACCESS, SPR_NOACCESS,
1857 &spr_read_generic, SPR_NOACCESS,
1858 0x00000000);
1859 /* Storage control */
1860 spr_register(env, SPR_440_MMUCR, "MMUCR",
1861 SPR_NOACCESS, SPR_NOACCESS,
1862 &spr_read_generic, &spr_write_generic,
1863 0x00000000);
1864 }
1865
1866 /* SPR shared between PowerPC 40x implementations */
1867 static void gen_spr_40x (CPUPPCState *env)
1868 {
1869 /* Cache */
1870 /* not emulated, as QEMU do not emulate caches */
1871 spr_register(env, SPR_40x_DCCR, "DCCR",
1872 SPR_NOACCESS, SPR_NOACCESS,
1873 &spr_read_generic, &spr_write_generic,
1874 0x00000000);
1875 /* not emulated, as QEMU do not emulate caches */
1876 spr_register(env, SPR_40x_ICCR, "ICCR",
1877 SPR_NOACCESS, SPR_NOACCESS,
1878 &spr_read_generic, &spr_write_generic,
1879 0x00000000);
1880 /* not emulated, as QEMU do not emulate caches */
1881 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1882 SPR_NOACCESS, SPR_NOACCESS,
1883 &spr_read_generic, SPR_NOACCESS,
1884 0x00000000);
1885 /* Exception */
1886 spr_register(env, SPR_40x_DEAR, "DEAR",
1887 SPR_NOACCESS, SPR_NOACCESS,
1888 &spr_read_generic, &spr_write_generic,
1889 0x00000000);
1890 spr_register(env, SPR_40x_ESR, "ESR",
1891 SPR_NOACCESS, SPR_NOACCESS,
1892 &spr_read_generic, &spr_write_generic,
1893 0x00000000);
1894 spr_register(env, SPR_40x_EVPR, "EVPR",
1895 SPR_NOACCESS, SPR_NOACCESS,
1896 &spr_read_generic, &spr_write_excp_prefix,
1897 0x00000000);
1898 spr_register(env, SPR_40x_SRR2, "SRR2",
1899 &spr_read_generic, &spr_write_generic,
1900 &spr_read_generic, &spr_write_generic,
1901 0x00000000);
1902 spr_register(env, SPR_40x_SRR3, "SRR3",
1903 &spr_read_generic, &spr_write_generic,
1904 &spr_read_generic, &spr_write_generic,
1905 0x00000000);
1906 /* Timers */
1907 spr_register(env, SPR_40x_PIT, "PIT",
1908 SPR_NOACCESS, SPR_NOACCESS,
1909 &spr_read_40x_pit, &spr_write_40x_pit,
1910 0x00000000);
1911 spr_register(env, SPR_40x_TCR, "TCR",
1912 SPR_NOACCESS, SPR_NOACCESS,
1913 &spr_read_generic, &spr_write_booke_tcr,
1914 0x00000000);
1915 spr_register(env, SPR_40x_TSR, "TSR",
1916 SPR_NOACCESS, SPR_NOACCESS,
1917 &spr_read_generic, &spr_write_booke_tsr,
1918 0x00000000);
1919 }
1920
1921 /* SPR specific to PowerPC 405 implementation */
1922 static void gen_spr_405 (CPUPPCState *env)
1923 {
1924 /* MMU */
1925 spr_register(env, SPR_40x_PID, "PID",
1926 SPR_NOACCESS, SPR_NOACCESS,
1927 &spr_read_generic, &spr_write_generic,
1928 0x00000000);
1929 spr_register(env, SPR_4xx_CCR0, "CCR0",
1930 SPR_NOACCESS, SPR_NOACCESS,
1931 &spr_read_generic, &spr_write_generic,
1932 0x00700000);
1933 /* Debug interface */
1934 /* XXX : not implemented */
1935 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1936 SPR_NOACCESS, SPR_NOACCESS,
1937 &spr_read_generic, &spr_write_40x_dbcr0,
1938 0x00000000);
1939 /* XXX : not implemented */
1940 spr_register(env, SPR_405_DBCR1, "DBCR1",
1941 SPR_NOACCESS, SPR_NOACCESS,
1942 &spr_read_generic, &spr_write_generic,
1943 0x00000000);
1944 /* XXX : not implemented */
1945 spr_register(env, SPR_40x_DBSR, "DBSR",
1946 SPR_NOACCESS, SPR_NOACCESS,
1947 &spr_read_generic, &spr_write_clear,
1948 /* Last reset was system reset */
1949 0x00000300);
1950 /* XXX : not implemented */
1951 spr_register(env, SPR_40x_DAC1, "DAC1",
1952 SPR_NOACCESS, SPR_NOACCESS,
1953 &spr_read_generic, &spr_write_generic,
1954 0x00000000);
1955 spr_register(env, SPR_40x_DAC2, "DAC2",
1956 SPR_NOACCESS, SPR_NOACCESS,
1957 &spr_read_generic, &spr_write_generic,
1958 0x00000000);
1959 /* XXX : not implemented */
1960 spr_register(env, SPR_405_DVC1, "DVC1",
1961 SPR_NOACCESS, SPR_NOACCESS,
1962 &spr_read_generic, &spr_write_generic,
1963 0x00000000);
1964 /* XXX : not implemented */
1965 spr_register(env, SPR_405_DVC2, "DVC2",
1966 SPR_NOACCESS, SPR_NOACCESS,
1967 &spr_read_generic, &spr_write_generic,
1968 0x00000000);
1969 /* XXX : not implemented */
1970 spr_register(env, SPR_40x_IAC1, "IAC1",
1971 SPR_NOACCESS, SPR_NOACCESS,
1972 &spr_read_generic, &spr_write_generic,
1973 0x00000000);
1974 spr_register(env, SPR_40x_IAC2, "IAC2",
1975 SPR_NOACCESS, SPR_NOACCESS,
1976 &spr_read_generic, &spr_write_generic,
1977 0x00000000);
1978 /* XXX : not implemented */
1979 spr_register(env, SPR_405_IAC3, "IAC3",
1980 SPR_NOACCESS, SPR_NOACCESS,
1981 &spr_read_generic, &spr_write_generic,
1982 0x00000000);
1983 /* XXX : not implemented */
1984 spr_register(env, SPR_405_IAC4, "IAC4",
1985 SPR_NOACCESS, SPR_NOACCESS,
1986 &spr_read_generic, &spr_write_generic,
1987 0x00000000);
1988 /* Storage control */
1989 /* XXX: TODO: not implemented */
1990 spr_register(env, SPR_405_SLER, "SLER",
1991 SPR_NOACCESS, SPR_NOACCESS,
1992 &spr_read_generic, &spr_write_40x_sler,
1993 0x00000000);
1994 spr_register(env, SPR_40x_ZPR, "ZPR",
1995 SPR_NOACCESS, SPR_NOACCESS,
1996 &spr_read_generic, &spr_write_generic,
1997 0x00000000);
1998 /* XXX : not implemented */
1999 spr_register(env, SPR_405_SU0R, "SU0R",
2000 SPR_NOACCESS, SPR_NOACCESS,
2001 &spr_read_generic, &spr_write_generic,
2002 0x00000000);
2003 /* SPRG */
2004 spr_register(env, SPR_USPRG0, "USPRG0",
2005 &spr_read_ureg, SPR_NOACCESS,
2006 &spr_read_ureg, SPR_NOACCESS,
2007 0x00000000);
2008 spr_register(env, SPR_SPRG4, "SPRG4",
2009 SPR_NOACCESS, SPR_NOACCESS,
2010 &spr_read_generic, &spr_write_generic,
2011 0x00000000);
2012 spr_register(env, SPR_SPRG5, "SPRG5",
2013 SPR_NOACCESS, SPR_NOACCESS,
2014 spr_read_generic, &spr_write_generic,
2015 0x00000000);
2016 spr_register(env, SPR_SPRG6, "SPRG6",
2017 SPR_NOACCESS, SPR_NOACCESS,
2018 spr_read_generic, &spr_write_generic,
2019 0x00000000);
2020 spr_register(env, SPR_SPRG7, "SPRG7",
2021 SPR_NOACCESS, SPR_NOACCESS,
2022 spr_read_generic, &spr_write_generic,
2023 0x00000000);
2024 gen_spr_usprgh(env);
2025 }
2026
2027 /* SPR shared between PowerPC 401 & 403 implementations */
2028 static void gen_spr_401_403 (CPUPPCState *env)
2029 {
2030 /* Time base */
2031 spr_register(env, SPR_403_VTBL, "TBL",
2032 &spr_read_tbl, SPR_NOACCESS,
2033 &spr_read_tbl, SPR_NOACCESS,
2034 0x00000000);
2035 spr_register(env, SPR_403_TBL, "TBL",
2036 SPR_NOACCESS, SPR_NOACCESS,
2037 SPR_NOACCESS, &spr_write_tbl,
2038 0x00000000);
2039 spr_register(env, SPR_403_VTBU, "TBU",
2040 &spr_read_tbu, SPR_NOACCESS,
2041 &spr_read_tbu, SPR_NOACCESS,
2042 0x00000000);
2043 spr_register(env, SPR_403_TBU, "TBU",
2044 SPR_NOACCESS, SPR_NOACCESS,
2045 SPR_NOACCESS, &spr_write_tbu,
2046 0x00000000);
2047 /* Debug */
2048 /* not emulated, as QEMU do not emulate caches */
2049 spr_register(env, SPR_403_CDBCR, "CDBCR",
2050 SPR_NOACCESS, SPR_NOACCESS,
2051 &spr_read_generic, &spr_write_generic,
2052 0x00000000);
2053 }
2054
2055 /* SPR specific to PowerPC 401 implementation */
2056 static void gen_spr_401 (CPUPPCState *env)
2057 {
2058 /* Debug interface */
2059 /* XXX : not implemented */
2060 spr_register(env, SPR_40x_DBCR0, "DBCR",
2061 SPR_NOACCESS, SPR_NOACCESS,
2062 &spr_read_generic, &spr_write_40x_dbcr0,
2063 0x00000000);
2064 /* XXX : not implemented */
2065 spr_register(env, SPR_40x_DBSR, "DBSR",
2066 SPR_NOACCESS, SPR_NOACCESS,
2067 &spr_read_generic, &spr_write_clear,
2068 /* Last reset was system reset */
2069 0x00000300);
2070 /* XXX : not implemented */
2071 spr_register(env, SPR_40x_DAC1, "DAC",
2072 SPR_NOACCESS, SPR_NOACCESS,
2073 &spr_read_generic, &spr_write_generic,
2074 0x00000000);
2075 /* XXX : not implemented */
2076 spr_register(env, SPR_40x_IAC1, "IAC",
2077 SPR_NOACCESS, SPR_NOACCESS,
2078 &spr_read_generic, &spr_write_generic,
2079 0x00000000);
2080 /* Storage control */
2081 /* XXX: TODO: not implemented */
2082 spr_register(env, SPR_405_SLER, "SLER",
2083 SPR_NOACCESS, SPR_NOACCESS,
2084 &spr_read_generic, &spr_write_40x_sler,
2085 0x00000000);
2086 /* not emulated, as QEMU never does speculative access */
2087 spr_register(env, SPR_40x_SGR, "SGR",
2088 SPR_NOACCESS, SPR_NOACCESS,
2089 &spr_read_generic, &spr_write_generic,
2090 0xFFFFFFFF);
2091 /* not emulated, as QEMU do not emulate caches */
2092 spr_register(env, SPR_40x_DCWR, "DCWR",
2093 SPR_NOACCESS, SPR_NOACCESS,
2094 &spr_read_generic, &spr_write_generic,
2095 0x00000000);
2096 }
2097
2098 static void gen_spr_401x2 (CPUPPCState *env)
2099 {
2100 gen_spr_401(env);
2101 spr_register(env, SPR_40x_PID, "PID",
2102 SPR_NOACCESS, SPR_NOACCESS,
2103 &spr_read_generic, &spr_write_generic,
2104 0x00000000);
2105 spr_register(env, SPR_40x_ZPR, "ZPR",
2106 SPR_NOACCESS, SPR_NOACCESS,
2107 &spr_read_generic, &spr_write_generic,
2108 0x00000000);
2109 }
2110
2111 /* SPR specific to PowerPC 403 implementation */
2112 static void gen_spr_403 (CPUPPCState *env)
2113 {
2114 /* Debug interface */
2115 /* XXX : not implemented */
2116 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2117 SPR_NOACCESS, SPR_NOACCESS,
2118 &spr_read_generic, &spr_write_40x_dbcr0,
2119 0x00000000);
2120 /* XXX : not implemented */
2121 spr_register(env, SPR_40x_DBSR, "DBSR",
2122 SPR_NOACCESS, SPR_NOACCESS,
2123 &spr_read_generic, &spr_write_clear,
2124 /* Last reset was system reset */
2125 0x00000300);
2126 /* XXX : not implemented */
2127 spr_register(env, SPR_40x_DAC1, "DAC1",
2128 SPR_NOACCESS, SPR_NOACCESS,
2129 &spr_read_generic, &spr_write_generic,
2130 0x00000000);
2131 /* XXX : not implemented */
2132 spr_register(env, SPR_40x_DAC2, "DAC2",
2133 SPR_NOACCESS, SPR_NOACCESS,
2134 &spr_read_generic, &spr_write_generic,
2135 0x00000000);
2136 /* XXX : not implemented */
2137 spr_register(env, SPR_40x_IAC1, "IAC1",
2138 SPR_NOACCESS, SPR_NOACCESS,
2139 &spr_read_generic, &spr_write_generic,
2140 0x00000000);
2141 /* XXX : not implemented */
2142 spr_register(env, SPR_40x_IAC2, "IAC2",
2143 SPR_NOACCESS, SPR_NOACCESS,
2144 &spr_read_generic, &spr_write_generic,
2145 0x00000000);
2146 }
2147
2148 static void gen_spr_403_real (CPUPPCState *env)
2149 {
2150 spr_register(env, SPR_403_PBL1, "PBL1",
2151 SPR_NOACCESS, SPR_NOACCESS,
2152 &spr_read_403_pbr, &spr_write_403_pbr,
2153 0x00000000);
2154 spr_register(env, SPR_403_PBU1, "PBU1",
2155 SPR_NOACCESS, SPR_NOACCESS,
2156 &spr_read_403_pbr, &spr_write_403_pbr,
2157 0x00000000);
2158 spr_register(env, SPR_403_PBL2, "PBL2",
2159 SPR_NOACCESS, SPR_NOACCESS,
2160 &spr_read_403_pbr, &spr_write_403_pbr,
2161 0x00000000);
2162 spr_register(env, SPR_403_PBU2, "PBU2",
2163 SPR_NOACCESS, SPR_NOACCESS,
2164 &spr_read_403_pbr, &spr_write_403_pbr,
2165 0x00000000);
2166 }
2167
2168 static void gen_spr_403_mmu (CPUPPCState *env)
2169 {
2170 /* MMU */
2171 spr_register(env, SPR_40x_PID, "PID",
2172 SPR_NOACCESS, SPR_NOACCESS,
2173 &spr_read_generic, &spr_write_generic,
2174 0x00000000);
2175 spr_register(env, SPR_40x_ZPR, "ZPR",
2176 SPR_NOACCESS, SPR_NOACCESS,
2177 &spr_read_generic, &spr_write_generic,
2178 0x00000000);
2179 }
2180
2181 /* SPR specific to PowerPC compression coprocessor extension */
2182 static void gen_spr_compress (CPUPPCState *env)
2183 {
2184 /* XXX : not implemented */
2185 spr_register(env, SPR_401_SKR, "SKR",
2186 SPR_NOACCESS, SPR_NOACCESS,
2187 &spr_read_generic, &spr_write_generic,
2188 0x00000000);
2189 }
2190
2191 static void gen_spr_5xx_8xx (CPUPPCState *env)
2192 {
2193 /* Exception processing */
2194 spr_register_kvm(env, SPR_DSISR, "DSISR",
2195 SPR_NOACCESS, SPR_NOACCESS,
2196 &spr_read_generic, &spr_write_generic,
2197 KVM_REG_PPC_DSISR, 0x00000000);
2198 spr_register_kvm(env, SPR_DAR, "DAR",
2199 SPR_NOACCESS, SPR_NOACCESS,
2200 &spr_read_generic, &spr_write_generic,
2201 KVM_REG_PPC_DAR, 0x00000000);
2202 /* Timer */
2203 spr_register(env, SPR_DECR, "DECR",
2204 SPR_NOACCESS, SPR_NOACCESS,
2205 &spr_read_decr, &spr_write_decr,
2206 0x00000000);
2207 /* XXX : not implemented */
2208 spr_register(env, SPR_MPC_EIE, "EIE",
2209 SPR_NOACCESS, SPR_NOACCESS,
2210 &spr_read_generic, &spr_write_generic,
2211 0x00000000);
2212 /* XXX : not implemented */
2213 spr_register(env, SPR_MPC_EID, "EID",
2214 SPR_NOACCESS, SPR_NOACCESS,
2215 &spr_read_generic, &spr_write_generic,
2216 0x00000000);
2217 /* XXX : not implemented */
2218 spr_register(env, SPR_MPC_NRI, "NRI",
2219 SPR_NOACCESS, SPR_NOACCESS,
2220 &spr_read_generic, &spr_write_generic,
2221 0x00000000);
2222 /* XXX : not implemented */
2223 spr_register(env, SPR_MPC_CMPA, "CMPA",
2224 SPR_NOACCESS, SPR_NOACCESS,
2225 &spr_read_generic, &spr_write_generic,
2226 0x00000000);
2227 /* XXX : not implemented */
2228 spr_register(env, SPR_MPC_CMPB, "CMPB",
2229 SPR_NOACCESS, SPR_NOACCESS,
2230 &spr_read_generic, &spr_write_generic,
2231 0x00000000);
2232 /* XXX : not implemented */
2233 spr_register(env, SPR_MPC_CMPC, "CMPC",
2234 SPR_NOACCESS, SPR_NOACCESS,
2235 &spr_read_generic, &spr_write_generic,
2236 0x00000000);
2237 /* XXX : not implemented */
2238 spr_register(env, SPR_MPC_CMPD, "CMPD",
2239 SPR_NOACCESS, SPR_NOACCESS,
2240 &spr_read_generic, &spr_write_generic,
2241 0x00000000);
2242 /* XXX : not implemented */
2243 spr_register(env, SPR_MPC_ECR, "ECR",
2244 SPR_NOACCESS, SPR_NOACCESS,
2245 &spr_read_generic, &spr_write_generic,
2246 0x00000000);
2247 /* XXX : not implemented */
2248 spr_register(env, SPR_MPC_DER, "DER",
2249 SPR_NOACCESS, SPR_NOACCESS,
2250 &spr_read_generic, &spr_write_generic,
2251 0x00000000);
2252 /* XXX : not implemented */
2253 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2254 SPR_NOACCESS, SPR_NOACCESS,
2255 &spr_read_generic, &spr_write_generic,
2256 0x00000000);
2257 /* XXX : not implemented */
2258 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2259 SPR_NOACCESS, SPR_NOACCESS,
2260 &spr_read_generic, &spr_write_generic,
2261 0x00000000);
2262 /* XXX : not implemented */
2263 spr_register(env, SPR_MPC_CMPE, "CMPE",
2264 SPR_NOACCESS, SPR_NOACCESS,
2265 &spr_read_generic, &spr_write_generic,
2266 0x00000000);
2267 /* XXX : not implemented */
2268 spr_register(env, SPR_MPC_CMPF, "CMPF",
2269 SPR_NOACCESS, SPR_NOACCESS,
2270 &spr_read_generic, &spr_write_generic,
2271 0x00000000);
2272 /* XXX : not implemented */
2273 spr_register(env, SPR_MPC_CMPG, "CMPG",
2274 SPR_NOACCESS, SPR_NOACCESS,
2275 &spr_read_generic, &spr_write_generic,
2276 0x00000000);
2277 /* XXX : not implemented */
2278 spr_register(env, SPR_MPC_CMPH, "CMPH",
2279 SPR_NOACCESS, SPR_NOACCESS,
2280 &spr_read_generic, &spr_write_generic,
2281 0x00000000);
2282 /* XXX : not implemented */
2283 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2284 SPR_NOACCESS, SPR_NOACCESS,
2285 &spr_read_generic, &spr_write_generic,
2286 0x00000000);
2287 /* XXX : not implemented */
2288 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2289 SPR_NOACCESS, SPR_NOACCESS,
2290 &spr_read_generic, &spr_write_generic,
2291 0x00000000);
2292 /* XXX : not implemented */
2293 spr_register(env, SPR_MPC_BAR, "BAR",
2294 SPR_NOACCESS, SPR_NOACCESS,
2295 &spr_read_generic, &spr_write_generic,
2296 0x00000000);
2297 /* XXX : not implemented */
2298 spr_register(env, SPR_MPC_DPDR, "DPDR",
2299 SPR_NOACCESS, SPR_NOACCESS,
2300 &spr_read_generic, &spr_write_generic,
2301 0x00000000);
2302 /* XXX : not implemented */
2303 spr_register(env, SPR_MPC_IMMR, "IMMR",
2304 SPR_NOACCESS, SPR_NOACCESS,
2305 &spr_read_generic, &spr_write_generic,
2306 0x00000000);
2307 }
2308
2309 static void gen_spr_5xx (CPUPPCState *env)
2310 {
2311 /* XXX : not implemented */
2312 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2313 SPR_NOACCESS, SPR_NOACCESS,
2314 &spr_read_generic, &spr_write_generic,
2315 0x00000000);
2316 /* XXX : not implemented */
2317 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2318 SPR_NOACCESS, SPR_NOACCESS,
2319 &spr_read_generic, &spr_write_generic,
2320 0x00000000);
2321 /* XXX : not implemented */
2322 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2323 SPR_NOACCESS, SPR_NOACCESS,
2324 &spr_read_generic, &spr_write_generic,
2325 0x00000000);
2326 /* XXX : not implemented */
2327 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2328 SPR_NOACCESS, SPR_NOACCESS,
2329 &spr_read_generic, &spr_write_generic,
2330 0x00000000);
2331 /* XXX : not implemented */
2332 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2333 SPR_NOACCESS, SPR_NOACCESS,
2334 &spr_read_generic, &spr_write_generic,
2335 0x00000000);
2336 /* XXX : not implemented */
2337 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2338 SPR_NOACCESS, SPR_NOACCESS,
2339 &spr_read_generic, &spr_write_generic,
2340 0x00000000);
2341 /* XXX : not implemented */
2342 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2343 SPR_NOACCESS, SPR_NOACCESS,
2344 &spr_read_generic, &spr_write_generic,
2345 0x00000000);
2346 /* XXX : not implemented */
2347 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2348 SPR_NOACCESS, SPR_NOACCESS,
2349 &spr_read_generic, &spr_write_generic,
2350 0x00000000);
2351 /* XXX : not implemented */
2352 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2353 SPR_NOACCESS, SPR_NOACCESS,
2354 &spr_read_generic, &spr_write_generic,
2355 0x00000000);
2356 /* XXX : not implemented */
2357 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2358 SPR_NOACCESS, SPR_NOACCESS,
2359 &spr_read_generic, &spr_write_generic,
2360 0x00000000);
2361 /* XXX : not implemented */
2362 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2363 SPR_NOACCESS, SPR_NOACCESS,
2364 &spr_read_generic, &spr_write_generic,
2365 0x00000000);
2366 /* XXX : not implemented */
2367 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2368 SPR_NOACCESS, SPR_NOACCESS,
2369 &spr_read_generic, &spr_write_generic,
2370 0x00000000);
2371 /* XXX : not implemented */
2372 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2373 SPR_NOACCESS, SPR_NOACCESS,
2374 &spr_read_generic, &spr_write_generic,
2375 0x00000000);
2376 /* XXX : not implemented */
2377 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2378 SPR_NOACCESS, SPR_NOACCESS,
2379 &spr_read_generic, &spr_write_generic,
2380 0x00000000);
2381 /* XXX : not implemented */
2382 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2383 SPR_NOACCESS, SPR_NOACCESS,
2384 &spr_read_generic, &spr_write_generic,
2385 0x00000000);
2386 /* XXX : not implemented */
2387 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2388 SPR_NOACCESS, SPR_NOACCESS,
2389 &spr_read_generic, &spr_write_generic,
2390 0x00000000);
2391 /* XXX : not implemented */
2392 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2393 SPR_NOACCESS, SPR_NOACCESS,
2394 &spr_read_generic, &spr_write_generic,
2395 0x00000000);
2396 /* XXX : not implemented */
2397 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2398 SPR_NOACCESS, SPR_NOACCESS,
2399 &spr_read_generic, &spr_write_generic,
2400 0x00000000);
2401 /* XXX : not implemented */
2402 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2403 SPR_NOACCESS, SPR_NOACCESS,
2404 &spr_read_generic, &spr_write_generic,
2405 0x00000000);
2406 /* XXX : not implemented */
2407 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2408 SPR_NOACCESS, SPR_NOACCESS,
2409 &spr_read_generic, &spr_write_generic,
2410 0x00000000);
2411 /* XXX : not implemented */
2412 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2413 SPR_NOACCESS, SPR_NOACCESS,
2414 &spr_read_generic, &spr_write_generic,
2415 0x00000000);
2416 }
2417
2418 static void gen_spr_8xx (CPUPPCState *env)
2419 {
2420 /* XXX : not implemented */
2421 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2422 SPR_NOACCESS, SPR_NOACCESS,
2423 &spr_read_generic, &spr_write_generic,
2424 0x00000000);
2425 /* XXX : not implemented */
2426 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2427 SPR_NOACCESS, SPR_NOACCESS,
2428 &spr_read_generic, &spr_write_generic,
2429 0x00000000);
2430 /* XXX : not implemented */
2431 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2432 SPR_NOACCESS, SPR_NOACCESS,
2433 &spr_read_generic, &spr_write_generic,
2434 0x00000000);
2435 /* XXX : not implemented */
2436 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2437 SPR_NOACCESS, SPR_NOACCESS,
2438 &spr_read_generic, &spr_write_generic,
2439 0x00000000);
2440 /* XXX : not implemented */
2441 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2442 SPR_NOACCESS, SPR_NOACCESS,
2443 &spr_read_generic, &spr_write_generic,
2444 0x00000000);
2445 /* XXX : not implemented */
2446 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2447 SPR_NOACCESS, SPR_NOACCESS,
2448 &spr_read_generic, &spr_write_generic,
2449 0x00000000);
2450 /* XXX : not implemented */
2451 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2452 SPR_NOACCESS, SPR_NOACCESS,
2453 &spr_read_generic, &spr_write_generic,
2454 0x00000000);
2455 /* XXX : not implemented */
2456 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2457 SPR_NOACCESS, SPR_NOACCESS,
2458 &spr_read_generic, &spr_write_generic,
2459 0x00000000);
2460 /* XXX : not implemented */
2461 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2462 SPR_NOACCESS, SPR_NOACCESS,
2463 &spr_read_generic, &spr_write_generic,
2464 0x00000000);
2465 /* XXX : not implemented */
2466 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2467 SPR_NOACCESS, SPR_NOACCESS,
2468 &spr_read_generic, &spr_write_generic,
2469 0x00000000);
2470 /* XXX : not implemented */
2471 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2472 SPR_NOACCESS, SPR_NOACCESS,
2473 &spr_read_generic, &spr_write_generic,
2474 0x00000000);
2475 /* XXX : not implemented */
2476 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2477 SPR_NOACCESS, SPR_NOACCESS,
2478 &spr_read_generic, &spr_write_generic,
2479 0x00000000);
2480 /* XXX : not implemented */
2481 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2482 SPR_NOACCESS, SPR_NOACCESS,
2483 &spr_read_generic, &spr_write_generic,
2484 0x00000000);
2485 /* XXX : not implemented */
2486 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2487 SPR_NOACCESS, SPR_NOACCESS,
2488 &spr_read_generic, &spr_write_generic,
2489 0x00000000);
2490 /* XXX : not implemented */
2491 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2492 SPR_NOACCESS, SPR_NOACCESS,
2493 &spr_read_generic, &spr_write_generic,
2494 0x00000000);
2495 /* XXX : not implemented */
2496 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2497 SPR_NOACCESS, SPR_NOACCESS,
2498 &spr_read_generic, &spr_write_generic,
2499 0x00000000);
2500 /* XXX : not implemented */
2501 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2502 SPR_NOACCESS, SPR_NOACCESS,
2503 &spr_read_generic, &spr_write_generic,
2504 0x00000000);
2505 /* XXX : not implemented */
2506 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2507 SPR_NOACCESS, SPR_NOACCESS,
2508 &spr_read_generic, &spr_write_generic,
2509 0x00000000);
2510 /* XXX : not implemented */
2511 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2512 SPR_NOACCESS, SPR_NOACCESS,
2513 &spr_read_generic, &spr_write_generic,
2514 0x00000000);
2515 /* XXX : not implemented */
2516 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2517 SPR_NOACCESS, SPR_NOACCESS,
2518 &spr_read_generic, &spr_write_generic,
2519 0x00000000);
2520 /* XXX : not implemented */
2521 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2522 SPR_NOACCESS, SPR_NOACCESS,
2523 &spr_read_generic, &spr_write_generic,
2524 0x00000000);
2525 /* XXX : not implemented */
2526 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2527 SPR_NOACCESS, SPR_NOACCESS,
2528 &spr_read_generic, &spr_write_generic,
2529 0x00000000);
2530 /* XXX : not implemented */
2531 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2532 SPR_NOACCESS, SPR_NOACCESS,
2533 &spr_read_generic, &spr_write_generic,
2534 0x00000000);
2535 /* XXX : not implemented */
2536 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2537 SPR_NOACCESS, SPR_NOACCESS,
2538 &spr_read_generic, &spr_write_generic,
2539 0x00000000);
2540 /* XXX : not implemented */
2541 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2542 SPR_NOACCESS, SPR_NOACCESS,
2543 &spr_read_generic, &spr_write_generic,
2544 0x00000000);
2545 }
2546
2547 // XXX: TODO
2548 /*
2549 * AMR => SPR 29 (Power 2.04)
2550 * CTRL => SPR 136 (Power 2.04)
2551 * CTRL => SPR 152 (Power 2.04)
2552 * SCOMC => SPR 276 (64 bits ?)
2553 * SCOMD => SPR 277 (64 bits ?)
2554 * TBU40 => SPR 286 (Power 2.04 hypv)
2555 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2556 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2557 * HDSISR => SPR 306 (Power 2.04 hypv)
2558 * HDAR => SPR 307 (Power 2.04 hypv)
2559 * PURR => SPR 309 (Power 2.04 hypv)
2560 * HDEC => SPR 310 (Power 2.04 hypv)
2561 * HIOR => SPR 311 (hypv)
2562 * RMOR => SPR 312 (970)
2563 * HRMOR => SPR 313 (Power 2.04 hypv)
2564 * HSRR0 => SPR 314 (Power 2.04 hypv)
2565 * HSRR1 => SPR 315 (Power 2.04 hypv)
2566 * LPCR => SPR 316 (970)
2567 * LPIDR => SPR 317 (970)
2568 * EPR => SPR 702 (Power 2.04 emb)
2569 * perf => 768-783 (Power 2.04)
2570 * perf => 784-799 (Power 2.04)
2571 * PPR => SPR 896 (Power 2.04)
2572 * EPLC => SPR 947 (Power 2.04 emb)
2573 * EPSC => SPR 948 (Power 2.04 emb)
2574 * DABRX => 1015 (Power 2.04 hypv)
2575 * FPECR => SPR 1022 (?)
2576 * ... and more (thermal management, performance counters, ...)
2577 */
2578
2579 /*****************************************************************************/
2580 /* Exception vectors models */
2581 static void init_excp_4xx_real (CPUPPCState *env)
2582 {
2583 #if !defined(CONFIG_USER_ONLY)
2584 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2585 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2586 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2587 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2588 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2589 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2590 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2591 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2592 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2593 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2594 env->hreset_excp_prefix = 0x00000000UL;
2595 env->ivor_mask = 0x0000FFF0UL;
2596 env->ivpr_mask = 0xFFFF0000UL;
2597 /* Hardware reset vector */
2598 env->hreset_vector = 0xFFFFFFFCUL;
2599 #endif
2600 }
2601
2602 static void init_excp_4xx_softmmu (CPUPPCState *env)
2603 {
2604 #if !defined(CONFIG_USER_ONLY)
2605 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2606 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2607 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2608 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2609 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2610 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2611 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2612 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2613 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2614 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2615 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2616 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2617 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2618 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2619 env->hreset_excp_prefix = 0x00000000UL;
2620 env->ivor_mask = 0x0000FFF0UL;
2621 env->ivpr_mask = 0xFFFF0000UL;
2622 /* Hardware reset vector */
2623 env->hreset_vector = 0xFFFFFFFCUL;
2624 #endif
2625 }
2626
2627 static void init_excp_MPC5xx (CPUPPCState *env)
2628 {
2629 #if !defined(CONFIG_USER_ONLY)
2630 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2631 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2632 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2633 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2634 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2635 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2636 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2637 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2638 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2639 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2640 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2641 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2642 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2643 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2644 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2645 env->hreset_excp_prefix = 0x00000000UL;
2646 env->ivor_mask = 0x0000FFF0UL;
2647 env->ivpr_mask = 0xFFFF0000UL;
2648 /* Hardware reset vector */
2649 env->hreset_vector = 0xFFFFFFFCUL;
2650 #endif
2651 }
2652
2653 static void init_excp_MPC8xx (CPUPPCState *env)
2654 {
2655 #if !defined(CONFIG_USER_ONLY)
2656 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2657 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2658 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2659 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2660 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2661 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2662 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2663 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2664 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2665 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2666 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2667 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2668 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2669 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2670 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2671 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2672 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2673 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2674 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2675 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2676 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2677 env->hreset_excp_prefix = 0x00000000UL;
2678 env->ivor_mask = 0x0000FFF0UL;
2679 env->ivpr_mask = 0xFFFF0000UL;
2680 /* Hardware reset vector */
2681 env->hreset_vector = 0xFFFFFFFCUL;
2682 #endif
2683 }
2684
2685 static void init_excp_G2 (CPUPPCState *env)
2686 {
2687 #if !defined(CONFIG_USER_ONLY)
2688 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2689 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2690 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2691 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2692 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2693 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2694 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2695 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2696 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2697 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2698 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2699 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2700 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2701 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2702 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2703 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2704 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2705 env->hreset_excp_prefix = 0x00000000UL;
2706 /* Hardware reset vector */
2707 env->hreset_vector = 0xFFFFFFFCUL;
2708 #endif
2709 }
2710
2711 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2712 {
2713 #if !defined(CONFIG_USER_ONLY)
2714 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2715 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2716 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2717 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2718 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2719 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2720 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2721 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2722 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2723 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2724 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2725 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2726 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2727 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2728 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2729 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2730 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2731 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2732 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2733 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2734 env->hreset_excp_prefix = 0x00000000UL;
2735 env->ivor_mask = 0x0000FFF7UL;
2736 env->ivpr_mask = ivpr_mask;
2737 /* Hardware reset vector */
2738 env->hreset_vector = 0xFFFFFFFCUL;
2739 #endif
2740 }
2741
2742 static void init_excp_BookE (CPUPPCState *env)
2743 {
2744 #if !defined(CONFIG_USER_ONLY)
2745 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2746 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2747 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2748 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2749 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2750 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2751 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2752 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2753 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2754 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2755 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2756 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2757 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2758 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2759 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2760 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2761 env->hreset_excp_prefix = 0x00000000UL;
2762 env->ivor_mask = 0x0000FFE0UL;
2763 env->ivpr_mask = 0xFFFF0000UL;
2764 /* Hardware reset vector */
2765 env->hreset_vector = 0xFFFFFFFCUL;
2766 #endif
2767 }
2768
2769 static void init_excp_601 (CPUPPCState *env)
2770 {
2771 #if !defined(CONFIG_USER_ONLY)
2772 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2773 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2774 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2775 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2776 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2777 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2778 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2779 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2780 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2781 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2782 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2783 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2784 env->hreset_excp_prefix = 0xFFF00000UL;
2785 /* Hardware reset vector */
2786 env->hreset_vector = 0x00000100UL;
2787 #endif
2788 }
2789
2790 static void init_excp_602 (CPUPPCState *env)
2791 {
2792 #if !defined(CONFIG_USER_ONLY)
2793 /* XXX: exception prefix has a special behavior on 602 */
2794 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2795 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2796 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2797 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2798 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2799 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2800 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2801 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2802 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2803 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2804 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2805 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2806 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2807 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2808 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2809 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2810 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2811 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2812 env->hreset_excp_prefix = 0xFFF00000UL;
2813 /* Hardware reset vector */
2814 env->hreset_vector = 0xFFFFFFFCUL;
2815 #endif
2816 }
2817
2818 static void init_excp_603 (CPUPPCState *env)
2819 {
2820 #if !defined(CONFIG_USER_ONLY)
2821 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2822 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2823 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2824 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2825 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2826 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2827 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2828 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2829 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2830 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2831 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2832 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2833 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2834 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2835 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2836 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2837 env->hreset_excp_prefix = 0x00000000UL;
2838 /* Hardware reset vector */
2839 env->hreset_vector = 0xFFFFFFFCUL;
2840 #endif
2841 }
2842
2843 static void init_excp_604 (CPUPPCState *env)
2844 {
2845 #if !defined(CONFIG_USER_ONLY)
2846 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2847 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2848 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2849 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2850 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2851 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2852 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2853 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2854 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2855 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2856 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2857 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2858 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2859 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2860 env->hreset_excp_prefix = 0xFFF00000UL;
2861 /* Hardware reset vector */
2862 env->hreset_vector = 0x00000100UL;
2863 #endif
2864 }
2865
2866 static void init_excp_7x0 (CPUPPCState *env)
2867 {
2868 #if !defined(CONFIG_USER_ONLY)
2869 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2870 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2871 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2872 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2873 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2874 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2875 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2876 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2877 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2878 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2879 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2880 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2881 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2882 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2883 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2884 env->hreset_excp_prefix = 0x00000000UL;
2885 /* Hardware reset vector */
2886 env->hreset_vector = 0xFFFFFFFCUL;
2887 #endif
2888 }
2889
2890 static void init_excp_750cl (CPUPPCState *env)
2891 {
2892 #if !defined(CONFIG_USER_ONLY)
2893 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2894 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2895 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2896 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2897 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2898 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2899 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2900 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2901 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2902 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2903 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2904 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2905 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2906 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2907 env->hreset_excp_prefix = 0x00000000UL;
2908 /* Hardware reset vector */
2909 env->hreset_vector = 0xFFFFFFFCUL;
2910 #endif
2911 }
2912
2913 static void init_excp_750cx (CPUPPCState *env)
2914 {
2915 #if !defined(CONFIG_USER_ONLY)
2916 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2917 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2918 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2919 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2920 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2921 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2922 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2923 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2924 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2925 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2926 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2927 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2928 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2929 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2930 env->hreset_excp_prefix = 0x00000000UL;
2931 /* Hardware reset vector */
2932 env->hreset_vector = 0xFFFFFFFCUL;
2933 #endif
2934 }
2935
2936 /* XXX: Check if this is correct */
2937 static void init_excp_7x5 (CPUPPCState *env)
2938 {
2939 #if !defined(CONFIG_USER_ONLY)
2940 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2941 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2942 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2943 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2944 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2945 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2946 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2947 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2948 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2949 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2950 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2951 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2952 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2953 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2954 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2955 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2956 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2957 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2958 env->hreset_excp_prefix = 0x00000000UL;
2959 /* Hardware reset vector */
2960 env->hreset_vector = 0xFFFFFFFCUL;
2961 #endif
2962 }
2963
2964 static void init_excp_7400 (CPUPPCState *env)
2965 {
2966 #if !defined(CONFIG_USER_ONLY)
2967 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2968 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2969 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2970 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2971 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2972 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2973 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2974 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2975 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2976 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2977 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2978 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2979 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2980 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2981 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2982 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2983 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2984 env->hreset_excp_prefix = 0x00000000UL;
2985 /* Hardware reset vector */
2986 env->hreset_vector = 0xFFFFFFFCUL;
2987 #endif
2988 }
2989
2990 static void init_excp_7450 (CPUPPCState *env)
2991 {
2992 #if !defined(CONFIG_USER_ONLY)
2993 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2994 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2995 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2996 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2997 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2998 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2999 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3000 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3001 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3002 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3003 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3004 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3005 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3006 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3007 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3008 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3009 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3010 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3011 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3012 env->hreset_excp_prefix = 0x00000000UL;
3013 /* Hardware reset vector */
3014 env->hreset_vector = 0xFFFFFFFCUL;
3015 #endif
3016 }
3017
3018 #if defined (TARGET_PPC64)
3019 static void init_excp_970 (CPUPPCState *env)
3020 {
3021 #if !defined(CONFIG_USER_ONLY)
3022 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3023 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3024 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3025 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3026 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3027 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3028 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3029 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3030 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3031 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3032 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3033 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3034 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3035 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3036 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3037 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3038 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3039 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3040 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3041 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3042 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
3043 /* Hardware reset vector */
3044 env->hreset_vector = 0x0000000000000100ULL;
3045 #endif
3046 }
3047
3048 static void init_excp_POWER7 (CPUPPCState *env)
3049 {
3050 #if !defined(CONFIG_USER_ONLY)
3051 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3052 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3053 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3054 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3055 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3056 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3057 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3058 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3059 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3060 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3061 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3062 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3063 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3064 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3065 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3066 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3067 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3068 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3069 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3070 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3071 env->hreset_excp_prefix = 0;
3072 /* Hardware reset vector */
3073 env->hreset_vector = 0x0000000000000100ULL;
3074 #endif
3075 }
3076 #endif
3077
3078 /*****************************************************************************/
3079 /* Power management enable checks */
3080 static int check_pow_none (CPUPPCState *env)
3081 {
3082 return 0;
3083 }
3084
3085 static int check_pow_nocheck (CPUPPCState *env)
3086 {
3087 return 1;
3088 }
3089
3090 static int check_pow_hid0 (CPUPPCState *env)
3091 {
3092 if (env->spr[SPR_HID0] & 0x00E00000)
3093 return 1;
3094
3095 return 0;
3096 }
3097
3098 static int check_pow_hid0_74xx (CPUPPCState *env)
3099 {
3100 if (env->spr[SPR_HID0] & 0x00600000)
3101 return 1;
3102
3103 return 0;
3104 }
3105
3106 /*****************************************************************************/
3107 /* PowerPC implementations definitions */
3108
3109 #define POWERPC_FAMILY(_name) \
3110 static void \
3111 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3112 \
3113 static const TypeInfo \
3114 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3115 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3116 .parent = TYPE_POWERPC_CPU, \
3117 .abstract = true, \
3118 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3119 }; \
3120 \
3121 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3122 { \
3123 type_register_static( \
3124 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3125 } \
3126 \
3127 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3128 \
3129 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3130
3131 static void init_proc_401 (CPUPPCState *env)
3132 {
3133 gen_spr_40x(env);
3134 gen_spr_401_403(env);
3135 gen_spr_401(env);
3136 init_excp_4xx_real(env);
3137 env->dcache_line_size = 32;
3138 env->icache_line_size = 32;
3139 /* Allocate hardware IRQ controller */
3140 ppc40x_irq_init(env);
3141
3142 SET_FIT_PERIOD(12, 16, 20, 24);
3143 SET_WDT_PERIOD(16, 20, 24, 28);
3144 }
3145
3146 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3147 {
3148 DeviceClass *dc = DEVICE_CLASS(oc);
3149 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3150
3151 dc->desc = "PowerPC 401";
3152 pcc->init_proc = init_proc_401;
3153 pcc->check_pow = check_pow_nocheck;
3154 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3155 PPC_WRTEE | PPC_DCR |
3156 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3157 PPC_CACHE_DCBZ |
3158 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3159 PPC_4xx_COMMON | PPC_40x_EXCP;
3160 pcc->insns_flags2 = PPC_NONE;
3161 pcc->msr_mask = 0x00000000000FD201ULL;
3162 pcc->mmu_model = POWERPC_MMU_REAL;
3163 pcc->excp_model = POWERPC_EXCP_40x;
3164 pcc->bus_model = PPC_FLAGS_INPUT_401;
3165 pcc->bfd_mach = bfd_mach_ppc_403;
3166 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3167 POWERPC_FLAG_BUS_CLK;
3168 }
3169
3170 static void init_proc_401x2 (CPUPPCState *env)
3171 {
3172 gen_spr_40x(env);
3173 gen_spr_401_403(env);
3174 gen_spr_401x2(env);
3175 gen_spr_compress(env);
3176 /* Memory management */
3177 #if !defined(CONFIG_USER_ONLY)
3178 env->nb_tlb = 64;
3179 env->nb_ways = 1;
3180 env->id_tlbs = 0;
3181 env->tlb_type = TLB_EMB;
3182 #endif
3183 init_excp_4xx_softmmu(env);
3184 env->dcache_line_size = 32;
3185 env->icache_line_size = 32;
3186 /* Allocate hardware IRQ controller */
3187 ppc40x_irq_init(env);
3188
3189 SET_FIT_PERIOD(12, 16, 20, 24);
3190 SET_WDT_PERIOD(16, 20, 24, 28);
3191 }
3192
3193 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3194 {
3195 DeviceClass *dc = DEVICE_CLASS(oc);
3196 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3197
3198 dc->desc = "PowerPC 401x2";
3199 pcc->init_proc = init_proc_401x2;
3200 pcc->check_pow = check_pow_nocheck;
3201 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3202 PPC_DCR | PPC_WRTEE |
3203 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3204 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3205 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3206 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3207 PPC_4xx_COMMON | PPC_40x_EXCP;
3208 pcc->insns_flags2 = PPC_NONE;
3209 pcc->msr_mask = 0x00000000001FD231ULL;
3210 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3211 pcc->excp_model = POWERPC_EXCP_40x;
3212 pcc->bus_model = PPC_FLAGS_INPUT_401;
3213 pcc->bfd_mach = bfd_mach_ppc_403;
3214 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3215 POWERPC_FLAG_BUS_CLK;
3216 }
3217
3218 static void init_proc_401x3 (CPUPPCState *env)
3219 {
3220 gen_spr_40x(env);
3221 gen_spr_401_403(env);
3222 gen_spr_401(env);
3223 gen_spr_401x2(env);
3224 gen_spr_compress(env);
3225 init_excp_4xx_softmmu(env);
3226 env->dcache_line_size = 32;
3227 env->icache_line_size = 32;
3228 /* Allocate hardware IRQ controller */
3229 ppc40x_irq_init(env);
3230
3231 SET_FIT_PERIOD(12, 16, 20, 24);
3232 SET_WDT_PERIOD(16, 20, 24, 28);
3233 }
3234
3235 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3236 {
3237 DeviceClass *dc = DEVICE_CLASS(oc);
3238 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3239
3240 dc->desc = "PowerPC 401x3";
3241 pcc->init_proc = init_proc_401x3;
3242 pcc->check_pow = check_pow_nocheck;
3243 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3244 PPC_DCR | PPC_WRTEE |
3245 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3246 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3247 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3248 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3249 PPC_4xx_COMMON | PPC_40x_EXCP;
3250 pcc->insns_flags2 = PPC_NONE;
3251 pcc->msr_mask = 0x00000000001FD631ULL;
3252 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3253 pcc->excp_model = POWERPC_EXCP_40x;
3254 pcc->bus_model = PPC_FLAGS_INPUT_401;
3255 pcc->bfd_mach = bfd_mach_ppc_403;
3256 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3257 POWERPC_FLAG_BUS_CLK;
3258 }
3259
3260 static void init_proc_IOP480 (CPUPPCState *env)
3261 {
3262 gen_spr_40x(env);
3263 gen_spr_401_403(env);
3264 gen_spr_401x2(env);
3265 gen_spr_compress(env);
3266 /* Memory management */
3267 #if !defined(CONFIG_USER_ONLY)
3268 env->nb_tlb = 64;
3269 env->nb_ways = 1;
3270 env->id_tlbs = 0;
3271 env->tlb_type = TLB_EMB;
3272 #endif
3273 init_excp_4xx_softmmu(env);
3274 env->dcache_line_size = 32;
3275 env->icache_line_size = 32;
3276 /* Allocate hardware IRQ controller */
3277 ppc40x_irq_init(env);
3278
3279 SET_FIT_PERIOD(8, 12, 16, 20);
3280 SET_WDT_PERIOD(16, 20, 24, 28);
3281 }
3282
3283 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3284 {
3285 DeviceClass *dc = DEVICE_CLASS(oc);
3286 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3287
3288 dc->desc = "IOP480";
3289 pcc->init_proc = init_proc_IOP480;
3290 pcc->check_pow = check_pow_nocheck;
3291 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3292 PPC_DCR | PPC_WRTEE |
3293 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3294 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3295 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3296 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3297 PPC_4xx_COMMON | PPC_40x_EXCP;
3298 pcc->insns_flags2 = PPC_NONE;
3299 pcc->msr_mask = 0x00000000001FD231ULL;
3300 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3301 pcc->excp_model = POWERPC_EXCP_40x;
3302 pcc->bus_model = PPC_FLAGS_INPUT_401;
3303 pcc->bfd_mach = bfd_mach_ppc_403;
3304 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3305 POWERPC_FLAG_BUS_CLK;
3306 }
3307
3308 static void init_proc_403 (CPUPPCState *env)
3309 {
3310 gen_spr_40x(env);
3311 gen_spr_401_403(env);
3312 gen_spr_403(env);
3313 gen_spr_403_real(env);
3314 init_excp_4xx_real(env);
3315 env->dcache_line_size = 32;
3316 env->icache_line_size = 32;
3317 /* Allocate hardware IRQ controller */
3318 ppc40x_irq_init(env);
3319
3320 SET_FIT_PERIOD(8, 12, 16, 20);
3321 SET_WDT_PERIOD(16, 20, 24, 28);
3322 }
3323
3324 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3325 {
3326 DeviceClass *dc = DEVICE_CLASS(oc);
3327 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3328
3329 dc->desc = "PowerPC 403";
3330 pcc->init_proc = init_proc_403;
3331 pcc->check_pow = check_pow_nocheck;
3332 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3333 PPC_DCR | PPC_WRTEE |
3334 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3335 PPC_CACHE_DCBZ |
3336 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3337 PPC_4xx_COMMON | PPC_40x_EXCP;
3338 pcc->insns_flags2 = PPC_NONE;
3339 pcc->msr_mask = 0x000000000007D00DULL;
3340 pcc->mmu_model = POWERPC_MMU_REAL;
3341 pcc->excp_model = POWERPC_EXCP_40x;
3342 pcc->bus_model = PPC_FLAGS_INPUT_401;
3343 pcc->bfd_mach = bfd_mach_ppc_403;
3344 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3345 POWERPC_FLAG_BUS_CLK;
3346 }
3347
3348 static void init_proc_403GCX (CPUPPCState *env)
3349 {
3350 gen_spr_40x(env);
3351 gen_spr_401_403(env);
3352 gen_spr_403(env);
3353 gen_spr_403_real(env);
3354 gen_spr_403_mmu(env);
3355 /* Bus access control */
3356 /* not emulated, as QEMU never does speculative access */
3357 spr_register(env, SPR_40x_SGR, "SGR",
3358 SPR_NOACCESS, SPR_NOACCESS,
3359 &spr_read_generic, &spr_write_generic,
3360 0xFFFFFFFF);
3361 /* not emulated, as QEMU do not emulate caches */
3362 spr_register(env, SPR_40x_DCWR, "DCWR",
3363 SPR_NOACCESS, SPR_NOACCESS,
3364 &spr_read_generic, &spr_write_generic,
3365 0x00000000);
3366 /* Memory management */
3367 #if !defined(CONFIG_USER_ONLY)
3368 env->nb_tlb = 64;
3369 env->nb_ways = 1;
3370 env->id_tlbs = 0;
3371 env->tlb_type = TLB_EMB;
3372 #endif
3373 init_excp_4xx_softmmu(env);
3374 env->dcache_line_size = 32;
3375 env->icache_line_size = 32;
3376 /* Allocate hardware IRQ controller */
3377 ppc40x_irq_init(env);
3378
3379 SET_FIT_PERIOD(8, 12, 16, 20);
3380 SET_WDT_PERIOD(16, 20, 24, 28);
3381 }
3382
3383 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3384 {
3385 DeviceClass *dc = DEVICE_CLASS(oc);
3386 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3387
3388 dc->desc = "PowerPC 403 GCX";
3389 pcc->init_proc = init_proc_403GCX;
3390 pcc->check_pow = check_pow_nocheck;
3391 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3392 PPC_DCR | PPC_WRTEE |
3393 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3394 PPC_CACHE_DCBZ |
3395 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3396 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3397 PPC_4xx_COMMON | PPC_40x_EXCP;
3398 pcc->insns_flags2 = PPC_NONE;
3399 pcc->msr_mask = 0x000000000007D00DULL;
3400 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3401 pcc->excp_model = POWERPC_EXCP_40x;
3402 pcc->bus_model = PPC_FLAGS_INPUT_401;
3403 pcc->bfd_mach = bfd_mach_ppc_403;
3404 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3405 POWERPC_FLAG_BUS_CLK;
3406 }
3407
3408 static void init_proc_405 (CPUPPCState *env)
3409 {
3410 /* Time base */
3411 gen_tbl(env);
3412 gen_spr_40x(env);
3413 gen_spr_405(env);
3414 /* Bus access control */
3415 /* not emulated, as QEMU never does speculative access */
3416 spr_register(env, SPR_40x_SGR, "SGR",
3417 SPR_NOACCESS, SPR_NOACCESS,
3418 &spr_read_generic, &spr_write_generic,
3419 0xFFFFFFFF);
3420 /* not emulated, as QEMU do not emulate caches */
3421 spr_register(env, SPR_40x_DCWR, "DCWR",
3422 SPR_NOACCESS, SPR_NOACCESS,
3423 &spr_read_generic, &spr_write_generic,
3424 0x00000000);
3425 /* Memory management */
3426 #if !defined(CONFIG_USER_ONLY)
3427 env->nb_tlb = 64;
3428 env->nb_ways = 1;
3429 env->id_tlbs = 0;
3430 env->tlb_type = TLB_EMB;
3431 #endif
3432 init_excp_4xx_softmmu(env);
3433 env->dcache_line_size = 32;
3434 env->icache_line_size = 32;
3435 /* Allocate hardware IRQ controller */
3436 ppc40x_irq_init(env);
3437
3438 SET_FIT_PERIOD(8, 12, 16, 20);
3439 SET_WDT_PERIOD(16, 20, 24, 28);
3440 }
3441
3442 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3443 {
3444 DeviceClass *dc = DEVICE_CLASS(oc);
3445 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3446
3447 dc->desc = "PowerPC 405";
3448 pcc->init_proc = init_proc_405;
3449 pcc->check_pow = check_pow_nocheck;
3450 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3451 PPC_DCR | PPC_WRTEE |
3452 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3453 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3454 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3455 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3456 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3457 pcc->insns_flags2 = PPC_NONE;
3458 pcc->msr_mask = 0x000000000006E630ULL;
3459 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3460 pcc->excp_model = POWERPC_EXCP_40x;
3461 pcc->bus_model = PPC_FLAGS_INPUT_405;
3462 pcc->bfd_mach = bfd_mach_ppc_403;
3463 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3464 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3465 }
3466
3467 static void init_proc_440EP (CPUPPCState *env)
3468 {
3469 /* Time base */
3470 gen_tbl(env);
3471 gen_spr_BookE(env, 0x000000000000FFFFULL);
3472 gen_spr_440(env);
3473 gen_spr_usprgh(env);
3474 /* Processor identification */
3475 spr_register(env, SPR_BOOKE_PIR, "PIR",
3476 SPR_NOACCESS, SPR_NOACCESS,
3477 &spr_read_generic, &spr_write_pir,
3478 0x00000000);
3479 /* XXX : not implemented */
3480 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3481 SPR_NOACCESS, SPR_NOACCESS,
3482 &spr_read_generic, &spr_write_generic,
3483 0x00000000);
3484 /* XXX : not implemented */
3485 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3486 SPR_NOACCESS, SPR_NOACCESS,
3487 &spr_read_generic, &spr_write_generic,
3488 0x00000000);
3489 /* XXX : not implemented */
3490 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3491 SPR_NOACCESS, SPR_NOACCESS,
3492 &spr_read_generic, &spr_write_generic,
3493 0x00000000);
3494 /* XXX : not implemented */
3495 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3496 SPR_NOACCESS, SPR_NOACCESS,
3497 &spr_read_generic, &spr_write_generic,
3498 0x00000000);
3499 /* XXX : not implemented */
3500 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3501 SPR_NOACCESS, SPR_NOACCESS,
3502 &spr_read_generic, &spr_write_generic,
3503 0x00000000);
3504 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3505 SPR_NOACCESS, SPR_NOACCESS,
3506 &spr_read_generic, &spr_write_generic,
3507 0x00000000);
3508 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3509 SPR_NOACCESS, SPR_NOACCESS,
3510 &spr_read_generic, &spr_write_generic,
3511 0x00000000);
3512 /* XXX : not implemented */
3513 spr_register(env, SPR_440_CCR1, "CCR1",
3514 SPR_NOACCESS, SPR_NOACCESS,
3515 &spr_read_generic, &spr_write_generic,
3516 0x00000000);
3517 /* Memory management */
3518 #if !defined(CONFIG_USER_ONLY)
3519 env->nb_tlb = 64;
3520 env->nb_ways = 1;
3521 env->id_tlbs = 0;
3522 env->tlb_type = TLB_EMB;
3523 #endif
3524 init_excp_BookE(env);
3525 env->dcache_line_size = 32;
3526 env->icache_line_size = 32;
3527 ppc40x_irq_init(env);
3528
3529 SET_FIT_PERIOD(12, 16, 20, 24);
3530 SET_WDT_PERIOD(20, 24, 28, 32);
3531 }
3532
3533 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3534 {
3535 DeviceClass *dc = DEVICE_CLASS(oc);
3536 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3537
3538 dc->desc = "PowerPC 440 EP";
3539 pcc->init_proc = init_proc_440EP;
3540 pcc->check_pow = check_pow_nocheck;
3541 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3542 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3543 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3544 PPC_FLOAT_STFIWX |
3545 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3546 PPC_CACHE | PPC_CACHE_ICBI |
3547 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3548 PPC_MEM_TLBSYNC | PPC_MFTB |
3549 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3550 PPC_440_SPEC;
3551 pcc->insns_flags2 = PPC_NONE;
3552 pcc->msr_mask = 0x000000000006FF30ULL;
3553 pcc->mmu_model = POWERPC_MMU_BOOKE;
3554 pcc->excp_model = POWERPC_EXCP_BOOKE;
3555 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3556 pcc->bfd_mach = bfd_mach_ppc_403;
3557 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3558 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3559 }
3560
3561 static void init_proc_440GP (CPUPPCState *env)
3562 {
3563 /* Time base */
3564 gen_tbl(env);
3565 gen_spr_BookE(env, 0x000000000000FFFFULL);
3566 gen_spr_440(env);
3567 gen_spr_usprgh(env);
3568 /* Processor identification */
3569 spr_register(env, SPR_BOOKE_PIR, "PIR",
3570 SPR_NOACCESS, SPR_NOACCESS,
3571 &spr_read_generic, &spr_write_pir,
3572 0x00000000);
3573 /* XXX : not implemented */
3574 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3575 SPR_NOACCESS, SPR_NOACCESS,
3576 &spr_read_generic, &spr_write_generic,
3577 0x00000000);
3578 /* XXX : not implemented */
3579 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3580 SPR_NOACCESS, SPR_NOACCESS,
3581 &spr_read_generic, &spr_write_generic,
3582 0x00000000);
3583 /* XXX : not implemented */
3584 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3585 SPR_NOACCESS, SPR_NOACCESS,
3586 &spr_read_generic, &spr_write_generic,
3587 0x00000000);
3588 /* XXX : not implemented */
3589 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3590 SPR_NOACCESS, SPR_NOACCESS,
3591 &spr_read_generic, &spr_write_generic,
3592 0x00000000);
3593 /* Memory management */
3594 #if !defined(CONFIG_USER_ONLY)
3595 env->nb_tlb = 64;
3596 env->nb_ways = 1;
3597 env->id_tlbs = 0;
3598 env->tlb_type = TLB_EMB;
3599 #endif
3600 init_excp_BookE(env);
3601 env->dcache_line_size = 32;
3602 env->icache_line_size = 32;
3603 /* XXX: TODO: allocate internal IRQ controller */
3604
3605 SET_FIT_PERIOD(12, 16, 20, 24);
3606 SET_WDT_PERIOD(20, 24, 28, 32);
3607 }
3608
3609 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3610 {
3611 DeviceClass *dc = DEVICE_CLASS(oc);
3612 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3613
3614 dc->desc = "PowerPC 440 GP";
3615 pcc->init_proc = init_proc_440GP;
3616 pcc->check_pow = check_pow_nocheck;
3617 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3618 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3619 PPC_CACHE | PPC_CACHE_ICBI |
3620 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3621 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3622 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3623 PPC_440_SPEC;
3624 pcc->insns_flags2 = PPC_NONE;
3625 pcc->msr_mask = 0x000000000006FF30ULL;
3626 pcc->mmu_model = POWERPC_MMU_BOOKE;
3627 pcc->excp_model = POWERPC_EXCP_BOOKE;
3628 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3629 pcc->bfd_mach = bfd_mach_ppc_403;
3630 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3631 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3632 }
3633
3634 static void init_proc_440x4 (CPUPPCState *env)
3635 {
3636 /* Time base */
3637 gen_tbl(env);
3638 gen_spr_BookE(env, 0x000000000000FFFFULL);
3639 gen_spr_440(env);
3640 gen_spr_usprgh(env);
3641 /* Processor identification */
3642 spr_register(env, SPR_BOOKE_PIR, "PIR",
3643 SPR_NOACCESS, SPR_NOACCESS,
3644 &spr_read_generic, &spr_write_pir,
3645 0x00000000);
3646 /* XXX : not implemented */
3647 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3648 SPR_NOACCESS, SPR_NOACCESS,
3649 &spr_read_generic, &spr_write_generic,
3650 0x00000000);
3651 /* XXX : not implemented */
3652 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3653 SPR_NOACCESS, SPR_NOACCESS,
3654 &spr_read_generic, &spr_write_generic,
3655 0x00000000);
3656 /* XXX : not implemented */
3657 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3658 SPR_NOACCESS, SPR_NOACCESS,
3659 &spr_read_generic, &spr_write_generic,
3660 0x00000000);
3661 /* XXX : not implemented */
3662 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3663 SPR_NOACCESS, SPR_NOACCESS,
3664 &spr_read_generic, &spr_write_generic,
3665 0x00000000);
3666 /* Memory management */
3667 #if !defined(CONFIG_USER_ONLY)
3668 env->nb_tlb = 64;
3669 env->nb_ways = 1;
3670 env->id_tlbs = 0;
3671 env->tlb_type = TLB_EMB;
3672 #endif
3673 init_excp_BookE(env);
3674 env->dcache_line_size = 32;
3675 env->icache_line_size = 32;
3676 /* XXX: TODO: allocate internal IRQ controller */
3677
3678 SET_FIT_PERIOD(12, 16, 20, 24);
3679 SET_WDT_PERIOD(20, 24, 28, 32);
3680 }
3681
3682 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3683 {
3684 DeviceClass *dc = DEVICE_CLASS(oc);
3685 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3686
3687 dc->desc = "PowerPC 440x4";
3688 pcc->init_proc = init_proc_440x4;
3689 pcc->check_pow = check_pow_nocheck;
3690 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3691 PPC_DCR | PPC_WRTEE |
3692 PPC_CACHE | PPC_CACHE_ICBI |
3693 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3694 PPC_MEM_TLBSYNC | PPC_MFTB |
3695 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3696 PPC_440_SPEC;
3697 pcc->insns_flags2 = PPC_NONE;
3698 pcc->msr_mask = 0x000000000006FF30ULL;
3699 pcc->mmu_model = POWERPC_MMU_BOOKE;
3700 pcc->excp_model = POWERPC_EXCP_BOOKE;
3701 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3702 pcc->bfd_mach = bfd_mach_ppc_403;
3703 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3704 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3705 }
3706
3707 static void init_proc_440x5 (CPUPPCState *env)
3708 {
3709 /* Time base */
3710 gen_tbl(env);
3711 gen_spr_BookE(env, 0x000000000000FFFFULL);
3712 gen_spr_440(env);
3713 gen_spr_usprgh(env);
3714 /* Processor identification */
3715 spr_register(env, SPR_BOOKE_PIR, "PIR",
3716 SPR_NOACCESS, SPR_NOACCESS,
3717 &spr_read_generic, &spr_write_pir,
3718 0x00000000);
3719 /* XXX : not implemented */
3720 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3721 SPR_NOACCESS, SPR_NOACCESS,
3722 &spr_read_generic, &spr_write_generic,
3723 0x00000000);
3724 /* XXX : not implemented */
3725 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3726 SPR_NOACCESS, SPR_NOACCESS,
3727 &spr_read_generic, &spr_write_generic,
3728 0x00000000);
3729 /* XXX : not implemented */
3730 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3731 SPR_NOACCESS, SPR_NOACCESS,
3732 &spr_read_generic, &spr_write_generic,
3733 0x00000000);
3734 /* XXX : not implemented */
3735 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3736 SPR_NOACCESS, SPR_NOACCESS,
3737 &spr_read_generic, &spr_write_generic,
3738 0x00000000);
3739 /* XXX : not implemented */
3740 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3741 SPR_NOACCESS, SPR_NOACCESS,
3742 &spr_read_generic, &spr_write_generic,
3743 0x00000000);
3744 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3745 SPR_NOACCESS, SPR_NOACCESS,
3746 &spr_read_generic, &spr_write_generic,
3747 0x00000000);
3748 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3749 SPR_NOACCESS, SPR_NOACCESS,
3750 &spr_read_generic, &spr_write_generic,
3751 0x00000000);
3752 /* XXX : not implemented */
3753 spr_register(env, SPR_440_CCR1, "CCR1",
3754 SPR_NOACCESS, SPR_NOACCESS,
3755 &spr_read_generic, &spr_write_generic,
3756 0x00000000);
3757 /* Memory management */
3758 #if !defined(CONFIG_USER_ONLY)
3759 env->nb_tlb = 64;
3760 env->nb_ways = 1;
3761 env->id_tlbs = 0;
3762 env->tlb_type = TLB_EMB;
3763 #endif
3764 init_excp_BookE(env);
3765 env->dcache_line_size = 32;
3766 env->icache_line_size = 32;
3767 ppc40x_irq_init(env);
3768
3769 SET_FIT_PERIOD(12, 16, 20, 24);
3770 SET_WDT_PERIOD(20, 24, 28, 32);
3771 }
3772
3773 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3774 {
3775 DeviceClass *dc = DEVICE_CLASS(oc);
3776 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3777
3778 dc->desc = "PowerPC 440x5";
3779 pcc->init_proc = init_proc_440x5;
3780 pcc->check_pow = check_pow_nocheck;
3781 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3782 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3783 PPC_CACHE | PPC_CACHE_ICBI |
3784 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3785 PPC_MEM_TLBSYNC | PPC_MFTB |
3786 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3787 PPC_440_SPEC;
3788 pcc->insns_flags2 = PPC_NONE;
3789 pcc->msr_mask = 0x000000000006FF30ULL;
3790 pcc->mmu_model = POWERPC_MMU_BOOKE;
3791 pcc->excp_model = POWERPC_EXCP_BOOKE;
3792 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3793 pcc->bfd_mach = bfd_mach_ppc_403;
3794 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3795 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3796 }
3797
3798 static void init_proc_460 (CPUPPCState *env)
3799 {
3800 /* Time base */
3801 gen_tbl(env);
3802 gen_spr_BookE(env, 0x000000000000FFFFULL);
3803 gen_spr_440(env);
3804 gen_spr_usprgh(env);
3805 /* Processor identification */
3806 spr_register(env, SPR_BOOKE_PIR, "PIR",
3807 SPR_NOACCESS, SPR_NOACCESS,
3808 &spr_read_generic, &spr_write_pir,
3809 0x00000000);
3810 /* XXX : not implemented */
3811 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3812 SPR_NOACCESS, SPR_NOACCESS,
3813 &spr_read_generic, &spr_write_generic,
3814 0x00000000);
3815 /* XXX : not implemented */
3816 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3817 SPR_NOACCESS, SPR_NOACCESS,
3818 &spr_read_generic, &spr_write_generic,
3819 0x00000000);
3820 /* XXX : not implemented */
3821 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3822 SPR_NOACCESS, SPR_NOACCESS,
3823 &spr_read_generic, &spr_write_generic,
3824 0x00000000);
3825 /* XXX : not implemented */
3826 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3827 SPR_NOACCESS, SPR_NOACCESS,
3828 &spr_read_generic, &spr_write_generic,
3829 0x00000000);
3830 /* XXX : not implemented */
3831 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3832 SPR_NOACCESS, SPR_NOACCESS,
3833 &spr_read_generic, &spr_write_generic,
3834 0x00000000);
3835 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3836 SPR_NOACCESS, SPR_NOACCESS,
3837 &spr_read_generic, &spr_write_generic,
3838 0x00000000);
3839 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3840 SPR_NOACCESS, SPR_NOACCESS,
3841 &spr_read_generic, &spr_write_generic,
3842 0x00000000);
3843 /* XXX : not implemented */
3844 spr_register(env, SPR_440_CCR1, "CCR1",
3845 SPR_NOACCESS, SPR_NOACCESS,
3846 &spr_read_generic, &spr_write_generic,
3847 0x00000000);
3848 /* XXX : not implemented */
3849 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3850 &spr_read_generic, &spr_write_generic,
3851 &spr_read_generic, &spr_write_generic,
3852 0x00000000);
3853 /* Memory management */
3854 #if !defined(CONFIG_USER_ONLY)
3855 env->nb_tlb = 64;
3856 env->nb_ways = 1;
3857 env->id_tlbs = 0;
3858 env->tlb_type = TLB_EMB;
3859 #endif
3860 init_excp_BookE(env);
3861 env->dcache_line_size = 32;
3862 env->icache_line_size = 32;
3863 /* XXX: TODO: allocate internal IRQ controller */
3864
3865 SET_FIT_PERIOD(12, 16, 20, 24);
3866 SET_WDT_PERIOD(20, 24, 28, 32);
3867 }
3868
3869 POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
3870 {
3871 DeviceClass *dc = DEVICE_CLASS(oc);
3872 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3873
3874 dc->desc = "PowerPC 460 (guessed)";
3875 pcc->init_proc = init_proc_460;
3876 pcc->check_pow = check_pow_nocheck;
3877 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3878 PPC_DCR | PPC_DCRX | PPC_DCRUX |
3879 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
3880 PPC_CACHE | PPC_CACHE_ICBI |
3881 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3882 PPC_MEM_TLBSYNC | PPC_TLBIVA |
3883 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3884 PPC_440_SPEC;
3885 pcc->insns_flags2 = PPC_NONE;
3886 pcc->msr_mask = 0x000000000006FF30ULL;
3887 pcc->mmu_model = POWERPC_MMU_BOOKE;
3888 pcc->excp_model = POWERPC_EXCP_BOOKE;
3889 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3890 pcc->bfd_mach = bfd_mach_ppc_403;
3891 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3892 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3893 }
3894
3895 static void init_proc_460F (CPUPPCState *env)
3896 {
3897 /* Time base */
3898 gen_tbl(env);
3899 gen_spr_BookE(env, 0x000000000000FFFFULL);
3900 gen_spr_440(env);
3901 gen_spr_usprgh(env);
3902 /* Processor identification */
3903 spr_register(env, SPR_BOOKE_PIR, "PIR",
3904 SPR_NOACCESS, SPR_NOACCESS,
3905 &spr_read_generic, &spr_write_pir,
3906 0x00000000);
3907 /* XXX : not implemented */
3908 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3909 SPR_NOACCESS, SPR_NOACCESS,
3910 &spr_read_generic, &spr_write_generic,
3911 0x00000000);
3912 /* XXX : not implemented */
3913 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3914 SPR_NOACCESS, SPR_NOACCESS,
3915 &spr_read_generic, &spr_write_generic,
3916 0x00000000);
3917 /* XXX : not implemented */
3918 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3919 SPR_NOACCESS, SPR_NOACCESS,
3920 &spr_read_generic, &spr_write_generic,
3921 0x00000000);
3922 /* XXX : not implemented */
3923 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3924 SPR_NOACCESS, SPR_NOACCESS,
3925 &spr_read_generic, &spr_write_generic,
3926 0x00000000);
3927 /* XXX : not implemented */
3928 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3929 SPR_NOACCESS, SPR_NOACCESS,
3930 &spr_read_generic, &spr_write_generic,
3931 0x00000000);
3932 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3933 SPR_NOACCESS, SPR_NOACCESS,
3934 &spr_read_generic, &spr_write_generic,
3935 0x00000000);
3936 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3937 SPR_NOACCESS, SPR_NOACCESS,
3938 &spr_read_generic, &spr_write_generic,
3939 0x00000000);
3940 /* XXX : not implemented */
3941 spr_register(env, SPR_440_CCR1, "CCR1",
3942 SPR_NOACCESS, SPR_NOACCESS,
3943 &spr_read_generic, &spr_write_generic,
3944 0x00000000);
3945 /* XXX : not implemented */
3946 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3947 &spr_read_generic, &spr_write_generic,
3948 &spr_read_generic, &spr_write_generic,
3949 0x00000000);
3950 /* Memory management */
3951 #if !defined(CONFIG_USER_ONLY)
3952 env->nb_tlb = 64;
3953 env->nb_ways = 1;
3954 env->id_tlbs = 0;
3955 env->tlb_type = TLB_EMB;
3956 #endif
3957 init_excp_BookE(env);
3958 env->dcache_line_size = 32;
3959 env->icache_line_size = 32;
3960 /* XXX: TODO: allocate internal IRQ controller */
3961
3962 SET_FIT_PERIOD(12, 16, 20, 24);
3963 SET_WDT_PERIOD(20, 24, 28, 32);
3964 }
3965
3966 POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
3967 {
3968 DeviceClass *dc = DEVICE_CLASS(oc);
3969 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3970
3971 dc->desc = "PowerPC 460F (guessed)";
3972 pcc->init_proc = init_proc_460F;
3973 pcc->check_pow = check_pow_nocheck;
3974 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3975 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3976 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3977 PPC_FLOAT_STFIWX | PPC_MFTB |
3978 PPC_DCR | PPC_DCRX | PPC_DCRUX |
3979 PPC_WRTEE | PPC_MFAPIDI |
3980 PPC_CACHE | PPC_CACHE_ICBI |
3981 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3982 PPC_MEM_TLBSYNC | PPC_TLBIVA |
3983 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3984 PPC_440_SPEC;
3985 pcc->insns_flags2 = PPC_NONE;
3986 pcc->msr_mask = 0x000000000006FF30ULL;
3987 pcc->mmu_model = POWERPC_MMU_BOOKE;
3988 pcc->excp_model = POWERPC_EXCP_BOOKE;
3989 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3990 pcc->bfd_mach = bfd_mach_ppc_403;
3991 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3992 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3993 }
3994
3995 static void init_proc_MPC5xx (CPUPPCState *env)
3996 {
3997 /* Time base */
3998 gen_tbl(env);
3999 gen_spr_5xx_8xx(env);
4000 gen_spr_5xx(env);
4001 init_excp_MPC5xx(env);
4002 env->dcache_line_size = 32;
4003 env->icache_line_size = 32;
4004 /* XXX: TODO: allocate internal IRQ controller */
4005 }
4006
4007 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4008 {
4009 DeviceClass *dc = DEVICE_CLASS(oc);
4010 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4011
4012 dc->desc = "Freescale 5xx cores (aka RCPU)";
4013 pcc->init_proc = init_proc_MPC5xx;
4014 pcc->check_pow = check_pow_none;
4015 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4016 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4017 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4018 PPC_MFTB;
4019 pcc->insns_flags2 = PPC_NONE;
4020 pcc->msr_mask = 0x000000000001FF43ULL;
4021 pcc->mmu_model = POWERPC_MMU_REAL;
4022 pcc->excp_model = POWERPC_EXCP_603;
4023 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4024 pcc->bfd_mach = bfd_mach_ppc_505;
4025 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4026 POWERPC_FLAG_BUS_CLK;
4027 }
4028
4029 static void init_proc_MPC8xx (CPUPPCState *env)
4030 {
4031 /* Time base */
4032 gen_tbl(env);
4033 gen_spr_5xx_8xx(env);
4034 gen_spr_8xx(env);
4035 init_excp_MPC8xx(env);
4036 env->dcache_line_size = 32;
4037 env->icache_line_size = 32;
4038 /* XXX: TODO: allocate internal IRQ controller */
4039 }
4040
4041 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4042 {
4043 DeviceClass *dc = DEVICE_CLASS(oc);
4044 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4045
4046 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4047 pcc->init_proc = init_proc_MPC8xx;
4048 pcc->check_pow = check_pow_none;
4049 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4050 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4051 PPC_CACHE_ICBI | PPC_MFTB;
4052 pcc->insns_flags2 = PPC_NONE;
4053 pcc->msr_mask = 0x000000000001F673ULL;
4054 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4055 pcc->excp_model = POWERPC_EXCP_603;
4056 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4057 pcc->bfd_mach = bfd_mach_ppc_860;
4058 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4059 POWERPC_FLAG_BUS_CLK;
4060 }
4061
4062 /* Freescale 82xx cores (aka PowerQUICC-II) */
4063
4064 static void init_proc_G2 (CPUPPCState *env)
4065 {
4066 gen_spr_ne_601(env);
4067 gen_spr_G2_755(env);
4068 gen_spr_G2(env);
4069 /* Time base */
4070 gen_tbl(env);
4071 /* External access control */
4072 /* XXX : not implemented */
4073 spr_register(env, SPR_EAR, "EAR",
4074 SPR_NOACCESS, SPR_NOACCESS,
4075 &spr_read_generic, &spr_write_generic,
4076 0x00000000);
4077 /* Hardware implementation register */
4078 /* XXX : not implemented */
4079 spr_register(env, SPR_HID0, "HID0",
4080 SPR_NOACCESS, SPR_NOACCESS,
4081 &spr_read_generic, &spr_write_generic,
4082 0x00000000);
4083 /* XXX : not implemented */
4084 spr_register(env, SPR_HID1, "HID1",
4085 SPR_NOACCESS, SPR_NOACCESS,
4086 &spr_read_generic, &spr_write_generic,
4087 0x00000000);
4088 /* XXX : not implemented */
4089 spr_register(env, SPR_HID2, "HID2",
4090 SPR_NOACCESS, SPR_NOACCESS,
4091 &spr_read_generic, &spr_write_generic,
4092 0x00000000);
4093 /* Memory management */
4094 gen_low_BATs(env);
4095 gen_high_BATs(env);
4096 gen_6xx_7xx_soft_tlb(env, 64, 2);
4097 init_excp_G2(env);
4098 env->dcache_line_size = 32;
4099 env->icache_line_size = 32;
4100 /* Allocate hardware IRQ controller */
4101 ppc6xx_irq_init(env);
4102 }
4103
4104 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4105 {
4106 DeviceClass *dc = DEVICE_CLASS(oc);
4107 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4108
4109 dc->desc = "PowerPC G2";
4110 pcc->init_proc = init_proc_G2;
4111 pcc->check_pow = check_pow_hid0;
4112 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4113 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4114 PPC_FLOAT_STFIWX |
4115 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4116 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4117 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4118 PPC_SEGMENT | PPC_EXTERN;
4119 pcc->insns_flags2 = PPC_NONE;
4120 pcc->msr_mask = 0x000000000006FFF2ULL;
4121 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4122 pcc->excp_model = POWERPC_EXCP_G2;
4123 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4124 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4125 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4126 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4127 }
4128
4129 static void init_proc_G2LE (CPUPPCState *env)
4130 {
4131 gen_spr_ne_601(env);
4132 gen_spr_G2_755(env);
4133 gen_spr_G2(env);
4134 /* Time base */
4135 gen_tbl(env);
4136 /* External access control */
4137 /* XXX : not implemented */
4138 spr_register(env, SPR_EAR, "EAR",
4139 SPR_NOACCESS, SPR_NOACCESS,
4140 &spr_read_generic, &spr_write_generic,
4141 0x00000000);
4142 /* Hardware implementation register */
4143 /* XXX : not implemented */
4144 spr_register(env, SPR_HID0, "HID0",
4145 SPR_NOACCESS, SPR_NOACCESS,
4146 &spr_read_generic, &spr_write_generic,
4147 0x00000000);
4148 /* XXX : not implemented */
4149 spr_register(env, SPR_HID1, "HID1",
4150 SPR_NOACCESS, SPR_NOACCESS,
4151 &spr_read_generic, &spr_write_generic,
4152 0x00000000);
4153 /* XXX : not implemented */
4154 spr_register(env, SPR_HID2, "HID2",
4155 SPR_NOACCESS, SPR_NOACCESS,
4156 &spr_read_generic, &spr_write_generic,
4157 0x00000000);
4158 /* Memory management */
4159 gen_low_BATs(env);
4160 gen_high_BATs(env);
4161 gen_6xx_7xx_soft_tlb(env, 64, 2);
4162 init_excp_G2(env);
4163 env->dcache_line_size = 32;
4164 env->icache_line_size = 32;
4165 /* Allocate hardware IRQ controller */
4166 ppc6xx_irq_init(env);
4167 }
4168
4169 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4170 {
4171 DeviceClass *dc = DEVICE_CLASS(oc);
4172 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4173
4174 dc->desc = "PowerPC G2LE";
4175 pcc->init_proc = init_proc_G2LE;
4176 pcc->check_pow = check_pow_hid0;
4177 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4178 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4179 PPC_FLOAT_STFIWX |
4180 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4181 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4182 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4183 PPC_SEGMENT | PPC_EXTERN;
4184 pcc->insns_flags2 = PPC_NONE;
4185 pcc->msr_mask = 0x000000000007FFF3ULL;
4186 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4187 pcc->excp_model = POWERPC_EXCP_G2;
4188 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4189 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4190 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4191 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4192 }
4193
4194 static void init_proc_e200 (CPUPPCState *env)
4195 {
4196 /* Time base */
4197 gen_tbl(env);
4198 gen_spr_BookE(env, 0x000000070000FFFFULL);
4199 /* XXX : not implemented */
4200 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4201 &spr_read_spefscr, &spr_write_spefscr,
4202 &spr_read_spefscr, &spr_write_spefscr,
4203 0x00000000);
4204 /* Memory management */
4205 gen_spr_BookE206(env, 0x0000005D, NULL);
4206 /* XXX : not implemented */
4207 spr_register(env, SPR_HID0, "HID0",
4208 SPR_NOACCESS, SPR_NOACCESS,
4209 &spr_read_generic, &spr_write_generic,
4210 0x00000000);
4211 /* XXX : not implemented */
4212 spr_register(env, SPR_HID1, "HID1",
4213 SPR_NOACCESS, SPR_NOACCESS,
4214 &spr_read_generic, &spr_write_generic,
4215 0x00000000);
4216 /* XXX : not implemented */
4217 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4218 SPR_NOACCESS, SPR_NOACCESS,
4219 &spr_read_generic, &spr_write_generic,
4220 0x00000000);
4221 /* XXX : not implemented */
4222 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4223 SPR_NOACCESS, SPR_NOACCESS,
4224 &spr_read_generic, &spr_write_generic,
4225 0x00000000);
4226 /* XXX : not implemented */
4227 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4228 SPR_NOACCESS, SPR_NOACCESS,
4229 &spr_read_generic, &spr_write_generic,
4230 0x00000000);
4231 /* XXX : not implemented */
4232 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4233 SPR_NOACCESS, SPR_NOACCESS,
4234 &spr_read_generic, &spr_write_generic,
4235 0x00000000);
4236 /* XXX : not implemented */
4237 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4238 SPR_NOACCESS, SPR_NOACCESS,
4239 &spr_read_generic, &spr_write_generic,
4240 0x00000000);
4241 /* XXX : not implemented */
4242 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4243 SPR_NOACCESS, SPR_NOACCESS,
4244 &spr_read_generic, &spr_write_generic,
4245 0x00000000);
4246 /* XXX : not implemented */
4247 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4248 SPR_NOACCESS, SPR_NOACCESS,
4249 &spr_read_generic, &spr_write_generic,
4250 0x00000000);
4251 /* XXX : not implemented */
4252 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4253 SPR_NOACCESS, SPR_NOACCESS,
4254 &spr_read_generic, &spr_write_generic,
4255 0x00000000);
4256 /* XXX : not implemented */
4257 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4258 SPR_NOACCESS, SPR_NOACCESS,
4259 &spr_read_generic, &spr_write_generic,
4260 0x00000000);
4261 /* XXX : not implemented */
4262 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4263 SPR_NOACCESS, SPR_NOACCESS,
4264 &spr_read_generic, &spr_write_generic,
4265 0x00000000);
4266 /* XXX : not implemented */
4267 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4268 SPR_NOACCESS, SPR_NOACCESS,
4269 &spr_read_generic, &spr_write_generic,
4270 0x00000000);
4271 /* XXX : not implemented */
4272 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4273 SPR_NOACCESS, SPR_NOACCESS,
4274 &spr_read_generic, &spr_write_generic,
4275 0x00000000);
4276 /* XXX : not implemented */
4277 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4278 SPR_NOACCESS, SPR_NOACCESS,
4279 &spr_read_generic, &spr_write_generic,
4280 0x00000000); /* TOFIX */
4281 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4282 SPR_NOACCESS, SPR_NOACCESS,
4283 &spr_read_generic, &spr_write_generic,
4284 0x00000000);
4285 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4286 SPR_NOACCESS, SPR_NOACCESS,
4287 &spr_read_generic, &spr_write_generic,
4288 0x00000000);
4289 #if !defined(CONFIG_USER_ONLY)
4290 env->nb_tlb = 64;
4291 env->nb_ways = 1;
4292 env->id_tlbs = 0;
4293 env->tlb_type = TLB_EMB;
4294 #endif
4295 init_excp_e200(env, 0xFFFF0000UL);
4296 env->dcache_line_size = 32;
4297 env->icache_line_size = 32;
4298 /* XXX: TODO: allocate internal IRQ controller */
4299 }
4300
4301 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4302 {
4303 DeviceClass *dc = DEVICE_CLASS(oc);
4304 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4305
4306 dc->desc = "e200 core";
4307 pcc->init_proc = init_proc_e200;
4308 pcc->check_pow = check_pow_hid0;
4309 /* XXX: unimplemented instructions:
4310 * dcblc
4311 * dcbtlst
4312 * dcbtstls
4313 * icblc
4314 * icbtls
4315 * tlbivax
4316 * all SPE multiply-accumulate instructions
4317 */
4318 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4319 PPC_SPE | PPC_SPE_SINGLE |
4320 PPC_WRTEE | PPC_RFDI |
4321 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4322 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4323 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4324 PPC_BOOKE;
4325 pcc->insns_flags2 = PPC_NONE;
4326 pcc->msr_mask = 0x000000000606FF30ULL;
4327 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4328 pcc->excp_model = POWERPC_EXCP_BOOKE;
4329 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4330 pcc->bfd_mach = bfd_mach_ppc_860;
4331 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4332 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4333 POWERPC_FLAG_BUS_CLK;
4334 }
4335
4336 static void init_proc_e300 (CPUPPCState *env)
4337 {
4338 gen_spr_ne_601(env);
4339 gen_spr_603(env);
4340 /* Time base */
4341 gen_tbl(env);
4342 /* hardware implementation registers */
4343 /* XXX : not implemented */
4344 spr_register(env, SPR_HID0, "HID0",
4345 SPR_NOACCESS, SPR_NOACCESS,
4346 &spr_read_generic, &spr_write_generic,
4347 0x00000000);
4348 /* XXX : not implemented */
4349 spr_register(env, SPR_HID1, "HID1",
4350 SPR_NOACCESS, SPR_NOACCESS,
4351 &spr_read_generic, &spr_write_generic,
4352 0x00000000);
4353 /* XXX : not implemented */
4354 spr_register(env, SPR_HID2, "HID2",
4355 SPR_NOACCESS, SPR_NOACCESS,
4356 &spr_read_generic, &spr_write_generic,
4357 0x00000000);
4358 /* Memory management */
4359 gen_low_BATs(env);
4360 gen_high_BATs(env);
4361 gen_6xx_7xx_soft_tlb(env, 64, 2);
4362 init_excp_603(env);
4363 env->dcache_line_size = 32;
4364 env->icache_line_size = 32;
4365 /* Allocate hardware IRQ controller */
4366 ppc6xx_irq_init(env);
4367 }
4368
4369 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4370 {
4371 DeviceClass *dc = DEVICE_CLASS(oc);
4372 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4373
4374 dc->desc = "e300 core";
4375 pcc->init_proc = init_proc_e300;
4376 pcc->check_pow = check_pow_hid0;
4377 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4378 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4379 PPC_FLOAT_STFIWX |
4380 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4381 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4382 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4383 PPC_SEGMENT | PPC_EXTERN;
4384 pcc->insns_flags2 = PPC_NONE;
4385 pcc->msr_mask = 0x000000000007FFF3ULL;
4386 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4387 pcc->excp_model = POWERPC_EXCP_603;
4388 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4389 pcc->bfd_mach = bfd_mach_ppc_603;
4390 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4391 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4392 }
4393
4394 #if !defined(CONFIG_USER_ONLY)
4395 static void spr_write_mas73(void *opaque, int sprn, int gprn)
4396 {
4397 TCGv val = tcg_temp_new();
4398 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4399 gen_store_spr(SPR_BOOKE_MAS3, val);
4400 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4401 gen_store_spr(SPR_BOOKE_MAS7, val);
4402 tcg_temp_free(val);
4403 }
4404
4405 static void spr_read_mas73(void *opaque, int gprn, int sprn)
4406 {
4407 TCGv mas7 = tcg_temp_new();
4408 TCGv mas3 = tcg_temp_new();
4409 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4410 tcg_gen_shli_tl(mas7, mas7, 32);
4411 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4412 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4413 tcg_temp_free(mas3);
4414 tcg_temp_free(mas7);
4415 }
4416
4417 #endif
4418
4419 enum fsl_e500_version {
4420 fsl_e500v1,
4421 fsl_e500v2,
4422 fsl_e500mc,
4423 fsl_e5500,
4424 };
4425
4426 static void init_proc_e500 (CPUPPCState *env, int version)
4427 {
4428 uint32_t tlbncfg[2];
4429 uint64_t ivor_mask;
4430 uint64_t ivpr_mask = 0xFFFF0000ULL;
4431 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4432 | 0x0020; /* 32 kb */
4433 #if !defined(CONFIG_USER_ONLY)
4434 int i;
4435 #endif
4436
4437 /* Time base */
4438 gen_tbl(env);
4439 /*
4440 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4441 * complain when accessing them.
4442 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4443 */
4444 switch (version) {
4445 case fsl_e500v1:
4446 case fsl_e500v2:
4447 default:
4448 ivor_mask = 0x0000000F0000FFFFULL;
4449 break;
4450 case fsl_e500mc:
4451 case fsl_e5500:
4452 ivor_mask = 0x000003FE0000FFFFULL;
4453 break;
4454 }
4455 gen_spr_BookE(env, ivor_mask);
4456 /* Processor identification */
4457 spr_register(env, SPR_BOOKE_PIR, "PIR",
4458 SPR_NOACCESS, SPR_NOACCESS,
4459 &spr_read_generic, &spr_write_pir,
4460 0x00000000);
4461 /* XXX : not implemented */
4462 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4463 &spr_read_spefscr, &spr_write_spefscr,
4464 &spr_read_spefscr, &spr_write_spefscr,
4465 0x00000000);
4466 #if !defined(CONFIG_USER_ONLY)
4467 /* Memory management */
4468 env->nb_pids = 3;
4469 env->nb_ways = 2;
4470 env->id_tlbs = 0;
4471 switch (version) {
4472 case fsl_e500v1:
4473 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4474 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4475 break;
4476 case fsl_e500v2:
4477 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4478 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4479 break;
4480 case fsl_e500mc:
4481 case fsl_e5500:
4482 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4483 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4484 break;
4485 default:
4486 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4487 }
4488 #endif
4489 /* Cache sizes */
4490 switch (version) {
4491 case fsl_e500v1:
4492 case fsl_e500v2:
4493 env->dcache_line_size = 32;
4494 env->icache_line_size = 32;
4495 break;
4496 case fsl_e500mc:
4497 case fsl_e5500:
4498 env->dcache_line_size = 64;
4499 env->icache_line_size = 64;
4500 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4501 break;
4502 default:
4503 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4504 }
4505 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4506 /* XXX : not implemented */
4507 spr_register(env, SPR_HID0, "HID0",
4508 SPR_NOACCESS, SPR_NOACCESS,
4509 &spr_read_generic, &spr_write_generic,
4510 0x00000000);
4511 /* XXX : not implemented */
4512 spr_register(env, SPR_HID1, "HID1",
4513 SPR_NOACCESS, SPR_NOACCESS,
4514 &spr_read_generic, &spr_write_generic,
4515 0x00000000);
4516 /* XXX : not implemented */
4517 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4518 SPR_NOACCESS, SPR_NOACCESS,
4519 &spr_read_generic, &spr_write_generic,
4520 0x00000000);
4521 /* XXX : not implemented */
4522 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4523 SPR_NOACCESS, SPR_NOACCESS,
4524 &spr_read_generic, &spr_write_generic,
4525 0x00000000);
4526 /* XXX : not implemented */
4527 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4528 SPR_NOACCESS, SPR_NOACCESS,
4529 &spr_read_generic, &spr_write_generic,
4530 0x00000000);
4531 /* XXX : not implemented */
4532 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4533 SPR_NOACCESS, SPR_NOACCESS,
4534 &spr_read_generic, &spr_write_generic,
4535 0x00000000);
4536 /* XXX : not implemented */
4537 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4538 SPR_NOACCESS, SPR_NOACCESS,
4539 &spr_read_generic, &spr_write_generic,
4540 0x00000000);
4541 /* XXX : not implemented */
4542 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4543 SPR_NOACCESS, SPR_NOACCESS,
4544 &spr_read_generic, &spr_write_generic,
4545 0x00000000);
4546 /* XXX : not implemented */
4547 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4548 SPR_NOACCESS, SPR_NOACCESS,
4549 &spr_read_generic, &spr_write_generic,
4550 l1cfg0);
4551 /* XXX : not implemented */
4552 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4553 SPR_NOACCESS, SPR_NOACCESS,
4554 &spr_read_generic, &spr_write_e500_l1csr0,
4555 0x00000000);
4556 /* XXX : not implemented */
4557 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4558 SPR_NOACCESS, SPR_NOACCESS,
4559 &spr_read_generic, &spr_write_generic,
4560 0x00000000);
4561 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4562 SPR_NOACCESS, SPR_NOACCESS,
4563 &spr_read_generic, &spr_write_generic,
4564 0x00000000);
4565 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4566 SPR_NOACCESS, SPR_NOACCESS,
4567 &spr_read_generic, &spr_write_generic,
4568 0x00000000);
4569 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4570 SPR_NOACCESS, SPR_NOACCESS,
4571 &spr_read_generic, &spr_write_booke206_mmucsr0,
4572 0x00000000);
4573 spr_register(env, SPR_BOOKE_EPR, "EPR",
4574 SPR_NOACCESS, SPR_NOACCESS,
4575 &spr_read_generic, SPR_NOACCESS,
4576 0x00000000);
4577 /* XXX better abstract into Emb.xxx features */
4578 if (version == fsl_e5500) {
4579 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4580 SPR_NOACCESS, SPR_NOACCESS,
4581 &spr_read_generic, &spr_write_generic,
4582 0x00000000);
4583 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4584 SPR_NOACCESS, SPR_NOACCESS,
4585 &spr_read_mas73, &spr_write_mas73,
4586 0x00000000);
4587 ivpr_mask = (target_ulong)~0xFFFFULL;
4588 }
4589
4590 #if !defined(CONFIG_USER_ONLY)
4591 env->nb_tlb = 0;
4592 env->tlb_type = TLB_MAS;
4593 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4594 env->nb_tlb += booke206_tlb_size(env, i);
4595 }
4596 #endif
4597
4598 init_excp_e200(env, ivpr_mask);
4599 /* Allocate hardware IRQ controller */
4600 ppce500_irq_init(env);
4601 }
4602
4603 static void init_proc_e500v1(CPUPPCState *env)
4604 {
4605 init_proc_e500(env, fsl_e500v1);
4606 }
4607
4608 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4609 {
4610 DeviceClass *dc = DEVICE_CLASS(oc);
4611 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4612
4613 dc->desc = "e500v1 core";
4614 pcc->init_proc = init_proc_e500v1;
4615 pcc->check_pow = check_pow_hid0;
4616 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4617 PPC_SPE | PPC_SPE_SINGLE |
4618 PPC_WRTEE | PPC_RFDI |
4619 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4620 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4621 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4622 pcc->insns_flags2 = PPC2_BOOKE206;
4623 pcc->msr_mask = 0x000000000606FF30ULL;
4624 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4625 pcc->excp_model = POWERPC_EXCP_BOOKE;
4626 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4627 pcc->bfd_mach = bfd_mach_ppc_860;
4628 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4629 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4630 POWERPC_FLAG_BUS_CLK;
4631 }
4632
4633 static void init_proc_e500v2(CPUPPCState *env)
4634 {
4635 init_proc_e500(env, fsl_e500v2);
4636 }
4637
4638 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4639 {
4640 DeviceClass *dc = DEVICE_CLASS(oc);
4641 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4642
4643 dc->desc = "e500v2 core";
4644 pcc->init_proc = init_proc_e500v2;
4645 pcc->check_pow = check_pow_hid0;
4646 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4647 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4648 PPC_WRTEE | PPC_RFDI |
4649 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4650 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4651 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4652 pcc->insns_flags2 = PPC2_BOOKE206;
4653 pcc->msr_mask = 0x000000000606FF30ULL;
4654 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4655 pcc->excp_model = POWERPC_EXCP_BOOKE;
4656 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4657 pcc->bfd_mach = bfd_mach_ppc_860;
4658 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4659 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4660 POWERPC_FLAG_BUS_CLK;
4661 }
4662
4663 static void init_proc_e500mc(CPUPPCState *env)
4664 {
4665 init_proc_e500(env, fsl_e500mc);
4666 }
4667
4668 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4669 {
4670 DeviceClass *dc = DEVICE_CLASS(oc);
4671 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4672
4673 dc->desc = "e500mc core";
4674 pcc->init_proc = init_proc_e500mc;
4675 pcc->check_pow = check_pow_none;
4676 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4677 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4678 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4679 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4680 PPC_FLOAT | PPC_FLOAT_FRES |
4681 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4682 PPC_FLOAT_STFIWX | PPC_WAIT |
4683 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4684 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4685 pcc->msr_mask = 0x000000001402FB36ULL;
4686 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4687 pcc->excp_model = POWERPC_EXCP_BOOKE;
4688 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4689 /* FIXME: figure out the correct flag for e500mc */
4690 pcc->bfd_mach = bfd_mach_ppc_e500;
4691 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4692 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4693 }
4694
4695 #ifdef TARGET_PPC64
4696 static void init_proc_e5500(CPUPPCState *env)
4697 {
4698 init_proc_e500(env, fsl_e5500);
4699 }
4700
4701 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
4702 {
4703 DeviceClass *dc = DEVICE_CLASS(oc);
4704 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4705
4706 dc->desc = "e5500 core";
4707 pcc->init_proc = init_proc_e5500;
4708 pcc->check_pow = check_pow_none;
4709 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4710 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4711 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4712 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4713 PPC_FLOAT | PPC_FLOAT_FRES |
4714 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4715 PPC_FLOAT_STFIWX | PPC_WAIT |
4716 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4717 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
4718 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4719 pcc->msr_mask = 0x000000009402FB36ULL;
4720 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4721 pcc->excp_model = POWERPC_EXCP_BOOKE;
4722 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4723 /* FIXME: figure out the correct flag for e5500 */
4724 pcc->bfd_mach = bfd_mach_ppc_e500;
4725 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4726 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4727 }
4728 #endif
4729
4730 /* Non-embedded PowerPC */
4731
4732 /* POWER : same as 601, without mfmsr, mfsr */
4733 POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
4734 {
4735 DeviceClass *dc = DEVICE_CLASS(oc);
4736 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4737
4738 dc->desc = "POWER";
4739 /* pcc->insns_flags = XXX_TODO; */
4740 /* POWER RSC (from RAD6000) */
4741 pcc->msr_mask = 0x00000000FEF0ULL;
4742 }
4743
4744 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4745
4746 static void init_proc_601 (CPUPPCState *env)
4747 {
4748 gen_spr_ne_601(env);
4749 gen_spr_601(env);
4750 /* Hardware implementation registers */
4751 /* XXX : not implemented */
4752 spr_register(env, SPR_HID0, "HID0",
4753 SPR_NOACCESS, SPR_NOACCESS,
4754 &spr_read_generic, &spr_write_hid0_601,
4755 0x80010080);
4756 /* XXX : not implemented */
4757 spr_register(env, SPR_HID1, "HID1",
4758 SPR_NOACCESS, SPR_NOACCESS,
4759 &spr_read_generic, &spr_write_generic,
4760 0x00000000);
4761 /* XXX : not implemented */
4762 spr_register(env, SPR_601_HID2, "HID2",
4763 SPR_NOACCESS, SPR_NOACCESS,
4764 &spr_read_generic, &spr_write_generic,
4765 0x00000000);
4766 /* XXX : not implemented */
4767 spr_register(env, SPR_601_HID5, "HID5",
4768 SPR_NOACCESS, SPR_NOACCESS,
4769 &spr_read_generic, &spr_write_generic,
4770 0x00000000);
4771 /* Memory management */
4772 init_excp_601(env);
4773 /* XXX: beware that dcache line size is 64
4774 * but dcbz uses 32 bytes "sectors"
4775 * XXX: this breaks clcs instruction !
4776 */
4777 env->dcache_line_size = 32;
4778 env->icache_line_size = 64;
4779 /* Allocate hardware IRQ controller */
4780 ppc6xx_irq_init(env);
4781 }
4782
4783 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
4784 {
4785 DeviceClass *dc = DEVICE_CLASS(oc);
4786 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4787
4788 dc->desc = "PowerPC 601";
4789 pcc->init_proc = init_proc_601;
4790 pcc->check_pow = check_pow_none;
4791 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4792 PPC_FLOAT |
4793 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4794 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4795 PPC_SEGMENT | PPC_EXTERN;
4796 pcc->insns_flags2 = PPC_NONE;
4797 pcc->msr_mask = 0x000000000000FD70ULL;
4798 pcc->mmu_model = POWERPC_MMU_601;
4799 pcc->excp_model = POWERPC_EXCP_601;
4800 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4801 pcc->bfd_mach = bfd_mach_ppc_601;
4802 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
4803 }
4804
4805 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4806
4807 static void init_proc_601v (CPUPPCState *env)
4808 {
4809 init_proc_601(env);
4810 /* XXX : not implemented */
4811 spr_register(env, SPR_601_HID15, "HID15",
4812 SPR_NOACCESS, SPR_NOACCESS,
4813 &spr_read_generic, &spr_write_generic,
4814 0x00000000);
4815 }
4816
4817 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
4818 {
4819 DeviceClass *dc = DEVICE_CLASS(oc);
4820 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4821
4822 dc->desc = "PowerPC 601v";
4823 pcc->init_proc = init_proc_601v;
4824 pcc->check_pow = check_pow_none;
4825 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4826 PPC_FLOAT |
4827 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4828 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4829 PPC_SEGMENT | PPC_EXTERN;
4830 pcc->insns_flags2 = PPC_NONE;
4831 pcc->msr_mask = 0x000000000000FD70ULL;
4832 pcc->mmu_model = POWERPC_MMU_601;
4833 pcc->excp_model = POWERPC_EXCP_601;
4834 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4835 pcc->bfd_mach = bfd_mach_ppc_601;
4836 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
4837 }
4838
4839 static void init_proc_602 (CPUPPCState *env)
4840 {
4841 gen_spr_ne_601(env);
4842 gen_spr_602(env);
4843 /* Time base */
4844 gen_tbl(env);
4845 /* hardware implementation registers */
4846 /* XXX : not implemented */
4847 spr_register(env, SPR_HID0, "HID0",
4848 SPR_NOACCESS, SPR_NOACCESS,
4849 &spr_read_generic, &spr_write_generic,
4850 0x00000000);
4851 /* XXX : not implemented */
4852 spr_register(env, SPR_HID1, "HID1",
4853 SPR_NOACCESS, SPR_NOACCESS,
4854 &spr_read_generic, &spr_write_generic,
4855 0x00000000);
4856 /* Memory management */
4857 gen_low_BATs(env);
4858 gen_6xx_7xx_soft_tlb(env, 64, 2);
4859 init_excp_602(env);
4860 env->dcache_line_size = 32;
4861 env->icache_line_size = 32;
4862 /* Allocate hardware IRQ controller */
4863 ppc6xx_irq_init(env);
4864 }
4865
4866 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
4867 {
4868 DeviceClass *dc = DEVICE_CLASS(oc);
4869 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4870
4871 dc->desc = "PowerPC 602";
4872 pcc->init_proc = init_proc_602;
4873 pcc->check_pow = check_pow_hid0;
4874 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4875 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4876 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4877 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4878 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4879 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
4880 PPC_SEGMENT | PPC_602_SPEC;
4881 pcc->insns_flags2 = PPC_NONE;
4882 pcc->msr_mask = 0x0000000000C7FF73ULL;
4883 /* XXX: 602 MMU is quite specific. Should add a special case */
4884 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4885 pcc->excp_model = POWERPC_EXCP_602;
4886 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4887 pcc->bfd_mach = bfd_mach_ppc_602;
4888 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4889 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4890 }
4891
4892 static void init_proc_603 (CPUPPCState *env)
4893 {
4894 gen_spr_ne_601(env);
4895 gen_spr_603(env);
4896 /* Time base */
4897 gen_tbl(env);
4898 /* hardware implementation registers */
4899 /* XXX : not implemented */
4900 spr_register(env, SPR_HID0, "HID0",
4901 SPR_NOACCESS, SPR_NOACCESS,
4902 &spr_read_generic, &spr_write_generic,
4903 0x00000000);
4904 /* XXX : not implemented */
4905 spr_register(env, SPR_HID1, "HID1",
4906 SPR_NOACCESS, SPR_NOACCESS,
4907 &spr_read_generic, &spr_write_generic,
4908 0x00000000);
4909 /* Memory management */
4910 gen_low_BATs(env);
4911 gen_6xx_7xx_soft_tlb(env, 64, 2);
4912 init_excp_603(env);
4913 env->dcache_line_size = 32;
4914 env->icache_line_size = 32;
4915 /* Allocate hardware IRQ controller */
4916 ppc6xx_irq_init(env);
4917 }
4918
4919 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
4920 {
4921 DeviceClass *dc = DEVICE_CLASS(oc);
4922 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4923
4924 dc->desc = "PowerPC 603";
4925 pcc->init_proc = init_proc_603;
4926 pcc->check_pow = check_pow_hid0;
4927 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4928 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4929 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4930 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4931 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4932 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4933 PPC_SEGMENT | PPC_EXTERN;
4934 pcc->insns_flags2 = PPC_NONE;
4935 pcc->msr_mask = 0x000000000007FF73ULL;
4936 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4937 pcc->excp_model = POWERPC_EXCP_603;
4938 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4939 pcc->bfd_mach = bfd_mach_ppc_603;
4940 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4941 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4942 }
4943
4944 static void init_proc_603E (CPUPPCState *env)
4945 {
4946 gen_spr_ne_601(env);
4947 gen_spr_603(env);
4948 /* Time base */
4949 gen_tbl(env);
4950 /* hardware implementation registers */
4951 /* XXX : not implemented */
4952 spr_register(env, SPR_HID0, "HID0",
4953 SPR_NOACCESS, SPR_NOACCESS,
4954 &spr_read_generic, &spr_write_generic,
4955 0x00000000);
4956 /* XXX : not implemented */
4957 spr_register(env, SPR_HID1, "HID1",
4958 SPR_NOACCESS, SPR_NOACCESS,
4959 &spr_read_generic, &spr_write_generic,
4960 0x00000000);
4961 /* XXX : not implemented */
4962 spr_register(env, SPR_IABR, "IABR",
4963 SPR_NOACCESS, SPR_NOACCESS,
4964 &spr_read_generic, &spr_write_generic,
4965 0x00000000);
4966 /* Memory management */
4967 gen_low_BATs(env);
4968 gen_6xx_7xx_soft_tlb(env, 64, 2);
4969 init_excp_603(env);
4970 env->dcache_line_size = 32;
4971 env->icache_line_size = 32;
4972 /* Allocate hardware IRQ controller */
4973 ppc6xx_irq_init(env);
4974 }
4975
4976 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
4977 {
4978 DeviceClass *dc = DEVICE_CLASS(oc);
4979 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4980
4981 dc->desc = "PowerPC 603e";
4982 pcc->init_proc = init_proc_603E;
4983 pcc->check_pow = check_pow_hid0;
4984 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4985 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4986 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4987 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4988 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4989 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4990 PPC_SEGMENT | PPC_EXTERN;
4991 pcc->insns_flags2 = PPC_NONE;
4992 pcc->msr_mask = 0x000000000007FF73ULL;
4993 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4994 pcc->excp_model = POWERPC_EXCP_603E;
4995 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4996 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4997 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4998 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4999 }
5000
5001 static void init_proc_604 (CPUPPCState *env)
5002 {
5003 gen_spr_ne_601(env);
5004 gen_spr_604(env);
5005 /* Time base */
5006 gen_tbl(env);
5007 /* Hardware implementation registers */
5008 /* XXX : not implemented */
5009 spr_register(env, SPR_HID0, "HID0",
5010 SPR_NOACCESS, SPR_NOACCESS,
5011 &spr_read_generic, &spr_write_generic,
5012 0x00000000);
5013 /* Memory management */
5014 gen_low_BATs(env);
5015 init_excp_604(env);
5016 env->dcache_line_size = 32;
5017 env->icache_line_size = 32;
5018 /* Allocate hardware IRQ controller */
5019 ppc6xx_irq_init(env);
5020 }
5021
5022 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5023 {
5024 DeviceClass *dc = DEVICE_CLASS(oc);
5025 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5026
5027 dc->desc = "PowerPC 604";
5028 pcc->init_proc = init_proc_604;
5029 pcc->check_pow = check_pow_nocheck;
5030 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5031 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5032 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5033 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5034 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5035 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5036 PPC_SEGMENT | PPC_EXTERN;
5037 pcc->insns_flags2 = PPC_NONE;
5038 pcc->msr_mask = 0x000000000005FF77ULL;
5039 pcc->mmu_model = POWERPC_MMU_32B;
5040 pcc->excp_model = POWERPC_EXCP_604;
5041 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5042 pcc->bfd_mach = bfd_mach_ppc_604;
5043 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5044 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5045 }
5046
5047 static void init_proc_604E (CPUPPCState *env)
5048 {
5049 gen_spr_ne_601(env);
5050 gen_spr_604(env);
5051 /* XXX : not implemented */
5052 spr_register(env, SPR_MMCR1, "MMCR1",
5053 SPR_NOACCESS, SPR_NOACCESS,
5054 &spr_read_generic, &spr_write_generic,
5055 0x00000000);
5056 /* XXX : not implemented */
5057 spr_register(env, SPR_PMC3, "PMC3",
5058 SPR_NOACCESS, SPR_NOACCESS,
5059 &spr_read_generic, &spr_write_generic,
5060 0x00000000);
5061 /* XXX : not implemented */
5062 spr_register(env, SPR_PMC4, "PMC4",
5063 SPR_NOACCESS, SPR_NOACCESS,
5064 &spr_read_generic, &spr_write_generic,
5065 0x00000000);
5066 /* Time base */
5067 gen_tbl(env);
5068 /* Hardware implementation registers */
5069 /* XXX : not implemented */
5070 spr_register(env, SPR_HID0, "HID0",
5071 SPR_NOACCESS, SPR_NOACCESS,
5072 &spr_read_generic, &spr_write_generic,
5073 0x00000000);
5074 /* XXX : not implemented */
5075 spr_register(env, SPR_HID1, "HID1",
5076 SPR_NOACCESS, SPR_NOACCESS,
5077 &spr_read_generic, &spr_write_generic,
5078 0x00000000);
5079 /* Memory management */
5080 gen_low_BATs(env);
5081 init_excp_604(env);
5082 env->dcache_line_size = 32;
5083 env->icache_line_size = 32;
5084 /* Allocate hardware IRQ controller */
5085 ppc6xx_irq_init(env);
5086 }
5087
5088 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5089 {
5090 DeviceClass *dc = DEVICE_CLASS(oc);
5091 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5092
5093 dc->desc = "PowerPC 604E";
5094 pcc->init_proc = init_proc_604E;
5095 pcc->check_pow = check_pow_nocheck;
5096 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5097 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5098 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5099 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5100 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5101 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5102 PPC_SEGMENT | PPC_EXTERN;
5103 pcc->insns_flags2 = PPC_NONE;
5104 pcc->msr_mask = 0x000000000005FF77ULL;
5105 pcc->mmu_model = POWERPC_MMU_32B;
5106 pcc->excp_model = POWERPC_EXCP_604;
5107 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5108 pcc->bfd_mach = bfd_mach_ppc_604;
5109 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5110 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5111 }
5112
5113 static void init_proc_740 (CPUPPCState *env)
5114 {
5115 gen_spr_ne_601(env);
5116 gen_spr_7xx(env);
5117 /* Time base */
5118 gen_tbl(env);
5119 /* Thermal management */
5120 gen_spr_thrm(env);
5121 /* Hardware implementation registers */
5122 /* XXX : not implemented */
5123 spr_register(env, SPR_HID0, "HID0",
5124 SPR_NOACCESS, SPR_NOACCESS,
5125 &spr_read_generic, &spr_write_generic,
5126 0x00000000);
5127 /* XXX : not implemented */
5128 spr_register(env, SPR_HID1, "HID1",
5129 SPR_NOACCESS, SPR_NOACCESS,
5130 &spr_read_generic, &spr_write_generic,
5131 0x00000000);
5132 /* Memory management */
5133 gen_low_BATs(env);
5134 init_excp_7x0(env);
5135 env->dcache_line_size = 32;
5136 env->icache_line_size = 32;
5137 /* Allocate hardware IRQ controller */
5138 ppc6xx_irq_init(env);
5139 }
5140
5141 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5142 {
5143 DeviceClass *dc = DEVICE_CLASS(oc);
5144 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5145
5146 dc->desc = "PowerPC 740";
5147 pcc->init_proc = init_proc_740;
5148 pcc->check_pow = check_pow_hid0;
5149 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5150 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5151 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5152 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5153 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5154 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5155 PPC_SEGMENT | PPC_EXTERN;
5156 pcc->insns_flags2 = PPC_NONE;
5157 pcc->msr_mask = 0x000000000005FF77ULL;
5158 pcc->mmu_model = POWERPC_MMU_32B;
5159 pcc->excp_model = POWERPC_EXCP_7x0;
5160 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5161 pcc->bfd_mach = bfd_mach_ppc_750;
5162 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5163 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5164 }
5165
5166 static void init_proc_750 (CPUPPCState *env)
5167 {
5168 gen_spr_ne_601(env);
5169 gen_spr_7xx(env);
5170 /* XXX : not implemented */
5171 spr_register(env, SPR_L2CR, "L2CR",
5172 SPR_NOACCESS, SPR_NOACCESS,
5173 &spr_read_generic, &spr_write_generic,
5174 0x00000000);
5175 /* Time base */
5176 gen_tbl(env);
5177 /* Thermal management */
5178 gen_spr_thrm(env);
5179 /* Hardware implementation registers */
5180 /* XXX : not implemented */
5181 spr_register(env, SPR_HID0, "HID0",
5182 SPR_NOACCESS, SPR_NOACCESS,
5183 &spr_read_generic, &spr_write_generic,
5184 0x00000000);
5185 /* XXX : not implemented */
5186 spr_register(env, SPR_HID1, "HID1",
5187 SPR_NOACCESS, SPR_NOACCESS,
5188 &spr_read_generic, &spr_write_generic,
5189 0x00000000);
5190 /* Memory management */
5191 gen_low_BATs(env);
5192 /* XXX: high BATs are also present but are known to be bugged on
5193 * die version 1.x
5194 */
5195 init_excp_7x0(env);
5196 env->dcache_line_size = 32;
5197 env->icache_line_size = 32;
5198 /* Allocate hardware IRQ controller */
5199 ppc6xx_irq_init(env);
5200 }
5201
5202 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5203 {
5204 DeviceClass *dc = DEVICE_CLASS(oc);
5205 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5206
5207 dc->desc = "PowerPC 750";
5208 pcc->init_proc = init_proc_750;
5209 pcc->check_pow = check_pow_hid0;
5210 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5211 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5212 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5213 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5214 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5215 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5216 PPC_SEGMENT | PPC_EXTERN;
5217 pcc->insns_flags2 = PPC_NONE;
5218 pcc->msr_mask = 0x000000000005FF77ULL;
5219 pcc->mmu_model = POWERPC_MMU_32B;
5220 pcc->excp_model = POWERPC_EXCP_7x0;
5221 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5222 pcc->bfd_mach = bfd_mach_ppc_750;
5223 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5224 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5225 }
5226
5227 static void init_proc_750cl (CPUPPCState *env)
5228 {
5229 gen_spr_ne_601(env);
5230 gen_spr_7xx(env);
5231 /* XXX : not implemented */
5232 spr_register(env, SPR_L2CR, "L2CR",
5233 SPR_NOACCESS, SPR_NOACCESS,
5234 &spr_read_generic, &spr_write_generic,
5235 0x00000000);
5236 /* Time base */
5237 gen_tbl(env);
5238 /* Thermal management */
5239 /* Those registers are fake on 750CL */
5240 spr_register(env, SPR_THRM1, "THRM1",
5241 SPR_NOACCESS, SPR_NOACCESS,
5242 &spr_read_generic, &spr_write_generic,
5243 0x00000000);
5244 spr_register(env, SPR_THRM2, "THRM2",
5245 SPR_NOACCESS, SPR_NOACCESS,
5246 &spr_read_generic, &spr_write_generic,
5247 0x00000000);
5248 spr_register(env, SPR_THRM3, "THRM3",
5249 SPR_NOACCESS, SPR_NOACCESS,
5250 &spr_read_generic, &spr_write_generic,
5251 0x00000000);
5252 /* XXX: not implemented */
5253 spr_register(env, SPR_750_TDCL, "TDCL",
5254 SPR_NOACCESS, SPR_NOACCESS,
5255 &spr_read_generic, &spr_write_generic,
5256 0x00000000);
5257 spr_register(env, SPR_750_TDCH, "TDCH",
5258 SPR_NOACCESS, SPR_NOACCESS,
5259 &spr_read_generic, &spr_write_generic,
5260 0x00000000);
5261 /* DMA */
5262 /* XXX : not implemented */
5263 spr_register(env, SPR_750_WPAR, "WPAR",
5264 SPR_NOACCESS, SPR_NOACCESS,
5265 &spr_read_generic, &spr_write_generic,
5266 0x00000000);
5267 spr_register(env, SPR_750_DMAL, "DMAL",
5268 SPR_NOACCESS, SPR_NOACCESS,
5269 &spr_read_generic, &spr_write_generic,
5270 0x00000000);
5271 spr_register(env, SPR_750_DMAU, "DMAU",
5272 SPR_NOACCESS, SPR_NOACCESS,
5273 &spr_read_generic, &spr_write_generic,
5274 0x00000000);
5275 /* Hardware implementation registers */
5276 /* XXX : not implemented */
5277 spr_register(env, SPR_HID0, "HID0",
5278 SPR_NOACCESS, SPR_NOACCESS,
5279 &spr_read_generic, &spr_write_generic,
5280 0x00000000);
5281 /* XXX : not implemented */
5282 spr_register(env, SPR_HID1, "HID1",
5283 SPR_NOACCESS, SPR_NOACCESS,
5284 &spr_read_generic, &spr_write_generic,
5285 0x00000000);
5286 /* XXX : not implemented */
5287 spr_register(env, SPR_750CL_HID2, "HID2",
5288 SPR_NOACCESS, SPR_NOACCESS,
5289 &spr_read_generic, &spr_write_generic,
5290 0x00000000);
5291 /* XXX : not implemented */
5292 spr_register(env, SPR_750CL_HID4, "HID4",
5293 SPR_NOACCESS, SPR_NOACCESS,
5294 &spr_read_generic, &spr_write_generic,
5295 0x00000000);
5296 /* Quantization registers */
5297 /* XXX : not implemented */
5298 spr_register(env, SPR_750_GQR0, "GQR0",
5299 SPR_NOACCESS, SPR_NOACCESS,
5300 &spr_read_generic, &spr_write_generic,
5301 0x00000000);
5302 /* XXX : not implemented */
5303 spr_register(env, SPR_750_GQR1, "GQR1",
5304 SPR_NOACCESS, SPR_NOACCESS,
5305 &spr_read_generic, &spr_write_generic,
5306 0x00000000);
5307 /* XXX : not implemented */
5308 spr_register(env, SPR_750_GQR2, "GQR2",
5309 SPR_NOACCESS, SPR_NOACCESS,
5310 &spr_read_generic, &spr_write_generic,
5311 0x00000000);
5312 /* XXX : not implemented */
5313 spr_register(env, SPR_750_GQR3, "GQR3",
5314 SPR_NOACCESS, SPR_NOACCESS,
5315 &spr_read_generic, &spr_write_generic,
5316 0x00000000);
5317 /* XXX : not implemented */
5318 spr_register(env, SPR_750_GQR4, "GQR4",
5319 SPR_NOACCESS, SPR_NOACCESS,
5320 &spr_read_generic, &spr_write_generic,
5321 0x00000000);
5322 /* XXX : not implemented */
5323 spr_register(env, SPR_750_GQR5, "GQR5",
5324 SPR_NOACCESS, SPR_NOACCESS,
5325 &spr_read_generic, &spr_write_generic,
5326 0x00000000);
5327 /* XXX : not implemented */
5328 spr_register(env, SPR_750_GQR6, "GQR6",
5329 SPR_NOACCESS, SPR_NOACCESS,
5330 &spr_read_generic, &spr_write_generic,
5331 0x00000000);
5332 /* XXX : not implemented */
5333 spr_register(env, SPR_750_GQR7, "GQR7",
5334 SPR_NOACCESS, SPR_NOACCESS,
5335 &spr_read_generic, &spr_write_generic,
5336 0x00000000);
5337 /* Memory management */
5338 gen_low_BATs(env);
5339 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5340 gen_high_BATs(env);
5341 init_excp_750cl(env);
5342 env->dcache_line_size = 32;
5343 env->icache_line_size = 32;
5344 /* Allocate hardware IRQ controller */
5345 ppc6xx_irq_init(env);
5346 }
5347
5348 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5349 {
5350 DeviceClass *dc = DEVICE_CLASS(oc);
5351 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5352
5353 dc->desc = "PowerPC 750 CL";
5354 pcc->init_proc = init_proc_750cl;
5355 pcc->check_pow = check_pow_hid0;
5356 /* XXX: not implemented:
5357 * cache lock instructions:
5358 * dcbz_l
5359 * floating point paired instructions
5360 * psq_lux
5361 * psq_lx
5362 * psq_stux
5363 * psq_stx
5364 * ps_abs
5365 * ps_add
5366 * ps_cmpo0
5367 * ps_cmpo1
5368 * ps_cmpu0
5369 * ps_cmpu1
5370 * ps_div
5371 * ps_madd
5372 * ps_madds0
5373 * ps_madds1
5374 * ps_merge00
5375 * ps_merge01
5376 * ps_merge10
5377 * ps_merge11
5378 * ps_mr
5379 * ps_msub
5380 * ps_mul
5381 * ps_muls0
5382 * ps_muls1
5383 * ps_nabs
5384 * ps_neg
5385 * ps_nmadd
5386 * ps_nmsub
5387 * ps_res
5388 * ps_rsqrte
5389 * ps_sel
5390 * ps_sub
5391 * ps_sum0
5392 * ps_sum1
5393 */
5394 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5395 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5396 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5397 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5398 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5399 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5400 PPC_SEGMENT | PPC_EXTERN;
5401 pcc->insns_flags2 = PPC_NONE;
5402 pcc->msr_mask = 0x000000000005FF77ULL;
5403 pcc->mmu_model = POWERPC_MMU_32B;
5404 pcc->excp_model = POWERPC_EXCP_7x0;
5405 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5406 pcc->bfd_mach = bfd_mach_ppc_750;
5407 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5408 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5409 }
5410
5411 static void init_proc_750cx (CPUPPCState *env)
5412 {
5413 gen_spr_ne_601(env);
5414 gen_spr_7xx(env);
5415 /* XXX : not implemented */
5416 spr_register(env, SPR_L2CR, "L2CR",
5417 SPR_NOACCESS, SPR_NOACCESS,
5418 &spr_read_generic, &spr_write_generic,
5419 0x00000000);
5420 /* Time base */
5421 gen_tbl(env);
5422 /* Thermal management */
5423 gen_spr_thrm(env);
5424 /* This register is not implemented but is present for compatibility */
5425 spr_register(env, SPR_SDA, "SDA",
5426 SPR_NOACCESS, SPR_NOACCESS,
5427 &spr_read_generic, &spr_write_generic,
5428 0x00000000);
5429 /* Hardware implementation registers */
5430 /* XXX : not implemented */
5431 spr_register(env, SPR_HID0, "HID0",
5432 SPR_NOACCESS, SPR_NOACCESS,
5433 &spr_read_generic, &spr_write_generic,
5434 0x00000000);
5435 /* XXX : not implemented */
5436 spr_register(env, SPR_HID1, "HID1",
5437 SPR_NOACCESS, SPR_NOACCESS,
5438 &spr_read_generic, &spr_write_generic,
5439 0x00000000);
5440 /* Memory management */
5441 gen_low_BATs(env);
5442 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5443 gen_high_BATs(env);
5444 init_excp_750cx(env);
5445 env->dcache_line_size = 32;
5446 env->icache_line_size = 32;
5447 /* Allocate hardware IRQ controller */
5448 ppc6xx_irq_init(env);
5449 }
5450
5451 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
5452 {
5453 DeviceClass *dc = DEVICE_CLASS(oc);
5454 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5455
5456 dc->desc = "PowerPC 750CX";
5457 pcc->init_proc = init_proc_750cx;
5458 pcc->check_pow = check_pow_hid0;
5459 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5460 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5461 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5462 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5463 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5464 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5465 PPC_SEGMENT | PPC_EXTERN;
5466 pcc->insns_flags2 = PPC_NONE;
5467 pcc->msr_mask = 0x000000000005FF77ULL;
5468 pcc->mmu_model = POWERPC_MMU_32B;
5469 pcc->excp_model = POWERPC_EXCP_7x0;
5470 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5471 pcc->bfd_mach = bfd_mach_ppc_750;
5472 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5473 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5474 }
5475
5476 static void init_proc_750fx (CPUPPCState *env)
5477 {
5478 gen_spr_ne_601(env);
5479 gen_spr_7xx(env);
5480 /* XXX : not implemented */
5481 spr_register(env, SPR_L2CR, "L2CR",
5482 SPR_NOACCESS, SPR_NOACCESS,
5483 &spr_read_generic, &spr_write_generic,
5484 0x00000000);
5485 /* Time base */
5486 gen_tbl(env);
5487 /* Thermal management */
5488 gen_spr_thrm(env);
5489 /* XXX : not implemented */
5490 spr_register(env, SPR_750_THRM4, "THRM4",
5491 SPR_NOACCESS, SPR_NOACCESS,
5492 &spr_read_generic, &spr_write_generic,
5493 0x00000000);
5494 /* Hardware implementation registers */
5495 /* XXX : not implemented */
5496 spr_register(env, SPR_HID0, "HID0",
5497 SPR_NOACCESS, SPR_NOACCESS,
5498 &spr_read_generic, &spr_write_generic,
5499 0x00000000);
5500 /* XXX : not implemented */
5501 spr_register(env, SPR_HID1, "HID1",
5502 SPR_NOACCESS, SPR_NOACCESS,
5503 &spr_read_generic, &spr_write_generic,
5504 0x00000000);
5505 /* XXX : not implemented */
5506 spr_register(env, SPR_750FX_HID2, "HID2",
5507 SPR_NOACCESS, SPR_NOACCESS,
5508 &spr_read_generic, &spr_write_generic,
5509 0x00000000);
5510 /* Memory management */
5511 gen_low_BATs(env);
5512 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5513 gen_high_BATs(env);
5514 init_excp_7x0(env);
5515 env->dcache_line_size = 32;
5516 env->icache_line_size = 32;
5517 /* Allocate hardware IRQ controller */
5518 ppc6xx_irq_init(env);
5519 }
5520
5521 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
5522 {
5523 DeviceClass *dc = DEVICE_CLASS(oc);
5524 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5525
5526 dc->desc = "PowerPC 750FX";
5527 pcc->init_proc = init_proc_750fx;
5528 pcc->check_pow = check_pow_hid0;
5529 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5530 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5531 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5532 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5533 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5534 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5535 PPC_SEGMENT | PPC_EXTERN;
5536 pcc->insns_flags2 = PPC_NONE;
5537 pcc->msr_mask = 0x000000000005FF77ULL;
5538 pcc->mmu_model = POWERPC_MMU_32B;
5539 pcc->excp_model = POWERPC_EXCP_7x0;
5540 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5541 pcc->bfd_mach = bfd_mach_ppc_750;
5542 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5543 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5544 }
5545
5546 static void init_proc_750gx (CPUPPCState *env)
5547 {
5548 gen_spr_ne_601(env);
5549 gen_spr_7xx(env);
5550 /* XXX : not implemented (XXX: different from 750fx) */
5551 spr_register(env, SPR_L2CR, "L2CR",
5552 SPR_NOACCESS, SPR_NOACCESS,
5553 &spr_read_generic, &spr_write_generic,
5554 0x00000000);
5555 /* Time base */
5556 gen_tbl(env);
5557 /* Thermal management */
5558 gen_spr_thrm(env);
5559 /* XXX : not implemented */
5560 spr_register(env, SPR_750_THRM4, "THRM4",
5561 SPR_NOACCESS, SPR_NOACCESS,
5562 &spr_read_generic, &spr_write_generic,
5563 0x00000000);
5564 /* Hardware implementation registers */
5565 /* XXX : not implemented (XXX: different from 750fx) */
5566 spr_register(env, SPR_HID0, "HID0",
5567 SPR_NOACCESS, SPR_NOACCESS,
5568 &spr_read_generic, &spr_write_generic,
5569 0x00000000);
5570 /* XXX : not implemented */
5571 spr_register(env, SPR_HID1, "HID1",
5572 SPR_NOACCESS, SPR_NOACCESS,
5573 &spr_read_generic, &spr_write_generic,
5574 0x00000000);
5575 /* XXX : not implemented (XXX: different from 750fx) */
5576 spr_register(env, SPR_750FX_HID2, "HID2",
5577 SPR_NOACCESS, SPR_NOACCESS,
5578 &spr_read_generic, &spr_write_generic,
5579 0x00000000);
5580 /* Memory management */
5581 gen_low_BATs(env);
5582 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5583 gen_high_BATs(env);
5584 init_excp_7x0(env);
5585 env->dcache_line_size = 32;
5586 env->icache_line_size = 32;
5587 /* Allocate hardware IRQ controller */
5588 ppc6xx_irq_init(env);
5589 }
5590
5591 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
5592 {
5593 DeviceClass *dc = DEVICE_CLASS(oc);
5594 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5595
5596 dc->desc = "PowerPC 750GX";
5597 pcc->init_proc = init_proc_750gx;
5598 pcc->check_pow = check_pow_hid0;
5599 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5600 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5601 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5602 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5603 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5604 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5605 PPC_SEGMENT | PPC_EXTERN;
5606 pcc->insns_flags2 = PPC_NONE;
5607 pcc->msr_mask = 0x000000000005FF77ULL;
5608 pcc->mmu_model = POWERPC_MMU_32B;
5609 pcc->excp_model = POWERPC_EXCP_7x0;
5610 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5611 pcc->bfd_mach = bfd_mach_ppc_750;
5612 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5613 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5614 }
5615
5616 static void init_proc_745 (CPUPPCState *env)
5617 {
5618 gen_spr_ne_601(env);
5619 gen_spr_7xx(env);
5620 gen_spr_G2_755(env);
5621 /* Time base */
5622 gen_tbl(env);
5623 /* Thermal management */
5624 gen_spr_thrm(env);
5625 /* Hardware implementation registers */
5626 /* XXX : not implemented */
5627 spr_register(env, SPR_HID0, "HID0",
5628 SPR_NOACCESS, SPR_NOACCESS,
5629 &spr_read_generic, &spr_write_generic,
5630 0x00000000);
5631 /* XXX : not implemented */
5632 spr_register(env, SPR_HID1, "HID1",
5633 SPR_NOACCESS, SPR_NOACCESS,
5634 &spr_read_generic, &spr_write_generic,
5635 0x00000000);
5636 /* XXX : not implemented */
5637 spr_register(env, SPR_HID2, "HID2",
5638 SPR_NOACCESS, SPR_NOACCESS,
5639 &spr_read_generic, &spr_write_generic,
5640 0x00000000);
5641 /* Memory management */
5642 gen_low_BATs(env);
5643 gen_high_BATs(env);
5644 gen_6xx_7xx_soft_tlb(env, 64, 2);
5645 init_excp_7x5(env);
5646 env->dcache_line_size = 32;
5647 env->icache_line_size = 32;
5648 /* Allocate hardware IRQ controller */
5649 ppc6xx_irq_init(env);
5650 }
5651
5652 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
5653 {
5654 DeviceClass *dc = DEVICE_CLASS(oc);
5655 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5656
5657 dc->desc = "PowerPC 745";
5658 pcc->init_proc = init_proc_745;
5659 pcc->check_pow = check_pow_hid0;
5660 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5661 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5662 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5663 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5664 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5665 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5666 PPC_SEGMENT | PPC_EXTERN;
5667 pcc->insns_flags2 = PPC_NONE;
5668 pcc->msr_mask = 0x000000000005FF77ULL;
5669 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5670 pcc->excp_model = POWERPC_EXCP_7x5;
5671 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5672 pcc->bfd_mach = bfd_mach_ppc_750;
5673 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5674 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5675 }
5676
5677 static void init_proc_755 (CPUPPCState *env)
5678 {
5679 gen_spr_ne_601(env);
5680 gen_spr_7xx(env);
5681 gen_spr_G2_755(env);
5682 /* Time base */
5683 gen_tbl(env);
5684 /* L2 cache control */
5685 /* XXX : not implemented */
5686 spr_register(env, SPR_L2CR, "L2CR",
5687 SPR_NOACCESS, SPR_NOACCESS,
5688 &spr_read_generic, &spr_write_generic,
5689 0x00000000);
5690 /* XXX : not implemented */
5691 spr_register(env, SPR_L2PMCR, "L2PMCR",
5692 SPR_NOACCESS, SPR_NOACCESS,
5693 &spr_read_generic, &spr_write_generic,
5694 0x00000000);
5695 /* Thermal management */
5696 gen_spr_thrm(env);
5697 /* Hardware implementation registers */
5698 /* XXX : not implemented */
5699 spr_register(env, SPR_HID0, "HID0",
5700 SPR_NOACCESS, SPR_NOACCESS,
5701 &spr_read_generic, &spr_write_generic,
5702 0x00000000);
5703 /* XXX : not implemented */
5704 spr_register(env, SPR_HID1, "HID1",
5705 SPR_NOACCESS, SPR_NOACCESS,
5706 &spr_read_generic, &spr_write_generic,
5707 0x00000000);
5708 /* XXX : not implemented */
5709 spr_register(env, SPR_HID2, "HID2",
5710 SPR_NOACCESS, SPR_NOACCESS,
5711 &spr_read_generic, &spr_write_generic,
5712 0x00000000);
5713 /* Memory management */
5714 gen_low_BATs(env);
5715 gen_high_BATs(env);
5716 gen_6xx_7xx_soft_tlb(env, 64, 2);
5717 init_excp_7x5(env);
5718 env->dcache_line_size = 32;
5719 env->icache_line_size = 32;
5720 /* Allocate hardware IRQ controller */
5721 ppc6xx_irq_init(env);
5722 }
5723
5724 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
5725 {
5726 DeviceClass *dc = DEVICE_CLASS(oc);
5727 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5728
5729 dc->desc = "PowerPC 755";
5730 pcc->init_proc = init_proc_755;
5731 pcc->check_pow = check_pow_hid0;
5732 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5733 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5734 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5735 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5736 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5737 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5738 PPC_SEGMENT | PPC_EXTERN;
5739 pcc->insns_flags2 = PPC_NONE;
5740 pcc->msr_mask = 0x000000000005FF77ULL;
5741 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5742 pcc->excp_model = POWERPC_EXCP_7x5;
5743 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5744 pcc->bfd_mach = bfd_mach_ppc_750;
5745 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5746 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5747 }
5748
5749 static void init_proc_7400 (CPUPPCState *env)
5750 {
5751 gen_spr_ne_601(env);
5752 gen_spr_7xx(env);
5753 /* Time base */
5754 gen_tbl(env);
5755 /* 74xx specific SPR */
5756 gen_spr_74xx(env);
5757 /* XXX : not implemented */
5758 spr_register(env, SPR_UBAMR, "UBAMR",
5759 &spr_read_ureg, SPR_NOACCESS,
5760 &spr_read_ureg, SPR_NOACCESS,
5761 0x00000000);
5762 /* XXX: this seems not implemented on all revisions. */
5763 /* XXX : not implemented */
5764 spr_register(env, SPR_MSSCR1, "MSSCR1",
5765 SPR_NOACCESS, SPR_NOACCESS,
5766 &spr_read_generic, &spr_write_generic,
5767 0x00000000);
5768 /* Thermal management */
5769 gen_spr_thrm(env);
5770 /* Memory management */
5771 gen_low_BATs(env);
5772 init_excp_7400(env);
5773 env->dcache_line_size = 32;
5774 env->icache_line_size = 32;
5775 /* Allocate hardware IRQ controller */
5776 ppc6xx_irq_init(env);
5777 }
5778
5779 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
5780 {
5781 DeviceClass *dc = DEVICE_CLASS(oc);
5782 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5783
5784 dc->desc = "PowerPC 7400 (aka G4)";
5785 pcc->init_proc = init_proc_7400;
5786 pcc->check_pow = check_pow_hid0;
5787 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5788 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5789 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5790 PPC_FLOAT_STFIWX |
5791 PPC_CACHE | PPC_CACHE_ICBI |
5792 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5793 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5794 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5795 PPC_MEM_TLBIA |
5796 PPC_SEGMENT | PPC_EXTERN |
5797 PPC_ALTIVEC;
5798 pcc->insns_flags2 = PPC_NONE;
5799 pcc->msr_mask = 0x000000000205FF77ULL;
5800 pcc->mmu_model = POWERPC_MMU_32B;
5801 pcc->excp_model = POWERPC_EXCP_74xx;
5802 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5803 pcc->bfd_mach = bfd_mach_ppc_7400;
5804 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5805 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5806 POWERPC_FLAG_BUS_CLK;
5807 }
5808
5809 static void init_proc_7410 (CPUPPCState *env)
5810 {
5811 gen_spr_ne_601(env);
5812 gen_spr_7xx(env);
5813 /* Time base */
5814 gen_tbl(env);
5815 /* 74xx specific SPR */
5816 gen_spr_74xx(env);
5817 /* XXX : not implemented */
5818 spr_register(env, SPR_UBAMR, "UBAMR",
5819 &spr_read_ureg, SPR_NOACCESS,
5820 &spr_read_ureg, SPR_NOACCESS,
5821 0x00000000);
5822 /* Thermal management */
5823 gen_spr_thrm(env);
5824 /* L2PMCR */
5825 /* XXX : not implemented */
5826 spr_register(env, SPR_L2PMCR, "L2PMCR",
5827 SPR_NOACCESS, SPR_NOACCESS,
5828 &spr_read_generic, &spr_write_generic,
5829 0x00000000);
5830 /* LDSTDB */
5831 /* XXX : not implemented */
5832 spr_register(env, SPR_LDSTDB, "LDSTDB",
5833 SPR_NOACCESS, SPR_NOACCESS,
5834 &spr_read_generic, &spr_write_generic,
5835 0x00000000);
5836 /* Memory management */
5837 gen_low_BATs(env);
5838 init_excp_7400(env);
5839 env->dcache_line_size = 32;
5840 env->icache_line_size = 32;
5841 /* Allocate hardware IRQ controller */
5842 ppc6xx_irq_init(env);
5843 }
5844
5845 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
5846 {
5847 DeviceClass *dc = DEVICE_CLASS(oc);
5848 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5849
5850 dc->desc = "PowerPC 7410 (aka G4)";
5851 pcc->init_proc = init_proc_7410;
5852 pcc->check_pow = check_pow_hid0;
5853 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5854 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5855 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5856 PPC_FLOAT_STFIWX |
5857 PPC_CACHE | PPC_CACHE_ICBI |
5858 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5859 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5860 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5861 PPC_MEM_TLBIA |
5862 PPC_SEGMENT | PPC_EXTERN |
5863 PPC_ALTIVEC;
5864 pcc->insns_flags2 = PPC_NONE;
5865 pcc->msr_mask = 0x000000000205FF77ULL;
5866 pcc->mmu_model = POWERPC_MMU_32B;
5867 pcc->excp_model = POWERPC_EXCP_74xx;
5868 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5869 pcc->bfd_mach = bfd_mach_ppc_7400;
5870 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5871 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5872 POWERPC_FLAG_BUS_CLK;
5873 }
5874
5875 static void init_proc_7440 (CPUPPCState *env)
5876 {
5877 gen_spr_ne_601(env);
5878 gen_spr_7xx(env);
5879 /* Time base */
5880 gen_tbl(env);
5881 /* 74xx specific SPR */
5882 gen_spr_74xx(env);
5883 /* XXX : not implemented */
5884 spr_register(env, SPR_UBAMR, "UBAMR",
5885 &spr_read_ureg, SPR_NOACCESS,
5886 &spr_read_ureg, SPR_NOACCESS,
5887 0x00000000);
5888 /* LDSTCR */
5889 /* XXX : not implemented */
5890 spr_register(env, SPR_LDSTCR, "LDSTCR",
5891 SPR_NOACCESS, SPR_NOACCESS,
5892 &spr_read_generic, &spr_write_generic,
5893 0x00000000);
5894 /* ICTRL */
5895 /* XXX : not implemented */
5896 spr_register(env, SPR_ICTRL, "ICTRL",
5897 SPR_NOACCESS, SPR_NOACCESS,
5898 &spr_read_generic, &spr_write_generic,
5899 0x00000000);
5900 /* MSSSR0 */
5901 /* XXX : not implemented */
5902 spr_register(env, SPR_MSSSR0, "MSSSR0",
5903 SPR_NOACCESS, SPR_NOACCESS,
5904 &spr_read_generic, &spr_write_generic,
5905 0x00000000);
5906 /* PMC */
5907 /* XXX : not implemented */
5908 spr_register(env, SPR_PMC5, "PMC5",
5909 SPR_NOACCESS, SPR_NOACCESS,
5910 &spr_read_generic, &spr_write_generic,
5911 0x00000000);
5912 /* XXX : not implemented */
5913 spr_register(env, SPR_UPMC5, "UPMC5",
5914 &spr_read_ureg, SPR_NOACCESS,
5915 &spr_read_ureg, SPR_NOACCESS,
5916 0x00000000);
5917 /* XXX : not implemented */
5918 spr_register(env, SPR_PMC6, "PMC6",
5919 SPR_NOACCESS, SPR_NOACCESS,
5920 &spr_read_generic, &spr_write_generic,
5921 0x00000000);
5922 /* XXX : not implemented */
5923 spr_register(env, SPR_UPMC6, "UPMC6",
5924 &spr_read_ureg, SPR_NOACCESS,
5925 &spr_read_ureg, SPR_NOACCESS,
5926 0x00000000);
5927 /* Memory management */
5928 gen_low_BATs(env);
5929 gen_74xx_soft_tlb(env, 128, 2);
5930 init_excp_7450(env);
5931 env->dcache_line_size = 32;
5932 env->icache_line_size = 32;
5933 /* Allocate hardware IRQ controller */
5934 ppc6xx_irq_init(env);
5935 }
5936
5937 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
5938 {
5939 DeviceClass *dc = DEVICE_CLASS(oc);
5940 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5941
5942 dc->desc = "PowerPC 7440 (aka G4)";
5943 pcc->init_proc = init_proc_7440;
5944 pcc->check_pow = check_pow_hid0_74xx;
5945 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5946 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5947 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5948 PPC_FLOAT_STFIWX |
5949 PPC_CACHE | PPC_CACHE_ICBI |
5950 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5951 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5952 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5953 PPC_MEM_TLBIA | PPC_74xx_TLB |
5954 PPC_SEGMENT | PPC_EXTERN |
5955 PPC_ALTIVEC;
5956 pcc->insns_flags2 = PPC_NONE;
5957 pcc->msr_mask = 0x000000000205FF77ULL;
5958 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
5959 pcc->excp_model = POWERPC_EXCP_74xx;
5960 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5961 pcc->bfd_mach = bfd_mach_ppc_7400;
5962 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5963 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5964 POWERPC_FLAG_BUS_CLK;
5965 }
5966
5967 static void init_proc_7450 (CPUPPCState *env)
5968 {
5969 gen_spr_ne_601(env);
5970 gen_spr_7xx(env);
5971 /* Time base */
5972 gen_tbl(env);
5973 /* 74xx specific SPR */
5974 gen_spr_74xx(env);
5975 /* Level 3 cache control */
5976 gen_l3_ctrl(env);
5977 /* L3ITCR1 */
5978 /* XXX : not implemented */
5979 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5980 SPR_NOACCESS, SPR_NOACCESS,
5981 &spr_read_generic, &spr_write_generic,
5982 0x00000000);
5983 /* L3ITCR2 */
5984 /* XXX : not implemented */
5985 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5986 SPR_NOACCESS, SPR_NOACCESS,
5987 &spr_read_generic, &spr_write_generic,
5988 0x00000000);
5989 /* L3ITCR3 */
5990 /* XXX : not implemented */
5991 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5992 SPR_NOACCESS, SPR_NOACCESS,
5993 &spr_read_generic, &spr_write_generic,
5994 0x00000000);
5995 /* L3OHCR */
5996 /* XXX : not implemented */
5997 spr_register(env, SPR_L3OHCR, "L3OHCR",
5998 SPR_NOACCESS, SPR_NOACCESS,
5999 &spr_read_generic, &spr_write_generic,
6000 0x00000000);
6001 /* XXX : not implemented */
6002 spr_register(env, SPR_UBAMR, "UBAMR",
6003 &spr_read_ureg, SPR_NOACCESS,
6004 &spr_read_ureg, SPR_NOACCESS,
6005 0x00000000);
6006 /* LDSTCR */
6007 /* XXX : not implemented */
6008 spr_register(env, SPR_LDSTCR, "LDSTCR",
6009 SPR_NOACCESS, SPR_NOACCESS,
6010 &spr_read_generic, &spr_write_generic,
6011 0x00000000);
6012 /* ICTRL */
6013 /* XXX : not implemented */
6014 spr_register(env, SPR_ICTRL, "ICTRL",
6015 SPR_NOACCESS, SPR_NOACCESS,
6016 &spr_read_generic, &spr_write_generic,
6017 0x00000000);
6018 /* MSSSR0 */
6019 /* XXX : not implemented */
6020 spr_register(env, SPR_MSSSR0, "MSSSR0",
6021 SPR_NOACCESS, SPR_NOACCESS,
6022 &spr_read_generic, &spr_write_generic,
6023 0x00000000);
6024 /* PMC */
6025 /* XXX : not implemented */
6026 spr_register(env, SPR_PMC5, "PMC5",
6027 SPR_NOACCESS, SPR_NOACCESS,
6028 &spr_read_generic, &spr_write_generic,
6029 0x00000000);
6030 /* XXX : not implemented */
6031 spr_register(env, SPR_UPMC5, "UPMC5",
6032 &spr_read_ureg, SPR_NOACCESS,
6033 &spr_read_ureg, SPR_NOACCESS,
6034 0x00000000);
6035 /* XXX : not implemented */
6036 spr_register(env, SPR_PMC6, "PMC6",
6037 SPR_NOACCESS, SPR_NOACCESS,
6038 &spr_read_generic, &spr_write_generic,
6039 0x00000000);
6040 /* XXX : not implemented */
6041 spr_register(env, SPR_UPMC6, "UPMC6",
6042 &spr_read_ureg, SPR_NOACCESS,
6043 &spr_read_ureg, SPR_NOACCESS,
6044 0x00000000);
6045 /* Memory management */
6046 gen_low_BATs(env);
6047 gen_74xx_soft_tlb(env, 128, 2);
6048 init_excp_7450(env);
6049 env->dcache_line_size = 32;
6050 env->icache_line_size = 32;
6051 /* Allocate hardware IRQ controller */
6052 ppc6xx_irq_init(env);
6053 }
6054
6055 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6056 {
6057 DeviceClass *dc = DEVICE_CLASS(oc);
6058 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6059
6060 dc->desc = "PowerPC 7450 (aka G4)";
6061 pcc->init_proc = init_proc_7450;
6062 pcc->check_pow = check_pow_hid0_74xx;
6063 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6064 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6065 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6066 PPC_FLOAT_STFIWX |
6067 PPC_CACHE | PPC_CACHE_ICBI |
6068 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6069 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6070 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6071 PPC_MEM_TLBIA | PPC_74xx_TLB |
6072 PPC_SEGMENT | PPC_EXTERN |
6073 PPC_ALTIVEC;
6074 pcc->insns_flags2 = PPC_NONE;
6075 pcc->msr_mask = 0x000000000205FF77ULL;
6076 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6077 pcc->excp_model = POWERPC_EXCP_74xx;
6078 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6079 pcc->bfd_mach = bfd_mach_ppc_7400;
6080 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6081 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6082 POWERPC_FLAG_BUS_CLK;
6083 }
6084
6085 static void init_proc_7445 (CPUPPCState *env)
6086 {
6087 gen_spr_ne_601(env);
6088 gen_spr_7xx(env);
6089 /* Time base */
6090 gen_tbl(env);
6091 /* 74xx specific SPR */
6092 gen_spr_74xx(env);
6093 /* LDSTCR */
6094 /* XXX : not implemented */
6095 spr_register(env, SPR_LDSTCR, "LDSTCR",
6096 SPR_NOACCESS, SPR_NOACCESS,
6097 &spr_read_generic, &spr_write_generic,
6098 0x00000000);
6099 /* ICTRL */
6100 /* XXX : not implemented */
6101 spr_register(env, SPR_ICTRL, "ICTRL",
6102 SPR_NOACCESS, SPR_NOACCESS,
6103 &spr_read_generic, &spr_write_generic,
6104 0x00000000);
6105 /* MSSSR0 */
6106 /* XXX : not implemented */
6107 spr_register(env, SPR_MSSSR0, "MSSSR0",
6108 SPR_NOACCESS, SPR_NOACCESS,
6109 &spr_read_generic, &spr_write_generic,
6110 0x00000000);
6111 /* PMC */
6112 /* XXX : not implemented */
6113 spr_register(env, SPR_PMC5, "PMC5",
6114 SPR_NOACCESS, SPR_NOACCESS,
6115 &spr_read_generic, &spr_write_generic,
6116 0x00000000);
6117 /* XXX : not implemented */
6118 spr_register(env, SPR_UPMC5, "UPMC5",
6119 &spr_read_ureg, SPR_NOACCESS,
6120 &spr_read_ureg, SPR_NOACCESS,
6121 0x00000000);
6122 /* XXX : not implemented */
6123 spr_register(env, SPR_PMC6, "PMC6",
6124 SPR_NOACCESS, SPR_NOACCESS,
6125 &spr_read_generic, &spr_write_generic,
6126 0x00000000);
6127 /* XXX : not implemented */
6128 spr_register(env, SPR_UPMC6, "UPMC6",
6129 &spr_read_ureg, SPR_NOACCESS,
6130 &spr_read_ureg, SPR_NOACCESS,
6131 0x00000000);
6132 /* SPRGs */
6133 spr_register(env, SPR_SPRG4, "SPRG4",
6134 SPR_NOACCESS, SPR_NOACCESS,
6135 &spr_read_generic, &spr_write_generic,
6136 0x00000000);
6137 spr_register(env, SPR_USPRG4, "USPRG4",
6138 &spr_read_ureg, SPR_NOACCESS,
6139 &spr_read_ureg, SPR_NOACCESS,
6140 0x00000000);
6141 spr_register(env, SPR_SPRG5, "SPRG5",
6142 SPR_NOACCESS, SPR_NOACCESS,
6143 &spr_read_generic, &spr_write_generic,
6144 0x00000000);
6145 spr_register(env, SPR_USPRG5, "USPRG5",
6146 &spr_read_ureg, SPR_NOACCESS,
6147 &spr_read_ureg, SPR_NOACCESS,
6148 0x00000000);
6149 spr_register(env, SPR_SPRG6, "SPRG6",
6150 SPR_NOACCESS, SPR_NOACCESS,
6151 &spr_read_generic, &spr_write_generic,
6152 0x00000000);
6153 spr_register(env, SPR_USPRG6, "USPRG6",
6154 &spr_read_ureg, SPR_NOACCESS,
6155 &spr_read_ureg, SPR_NOACCESS,
6156 0x00000000);
6157 spr_register(env, SPR_SPRG7, "SPRG7",
6158 SPR_NOACCESS, SPR_NOACCESS,
6159 &spr_read_generic, &spr_write_generic,
6160 0x00000000);
6161 spr_register(env, SPR_USPRG7, "USPRG7",
6162 &spr_read_ureg, SPR_NOACCESS,
6163 &spr_read_ureg, SPR_NOACCESS,
6164 0x00000000);
6165 /* Memory management */
6166 gen_low_BATs(env);
6167 gen_high_BATs(env);
6168 gen_74xx_soft_tlb(env, 128, 2);
6169 init_excp_7450(env);
6170 env->dcache_line_size = 32;
6171 env->icache_line_size = 32;
6172 /* Allocate hardware IRQ controller */
6173 ppc6xx_irq_init(env);
6174 }
6175
6176 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6177 {
6178 DeviceClass *dc = DEVICE_CLASS(oc);
6179 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6180
6181 dc->desc = "PowerPC 7445 (aka G4)";
6182 pcc->init_proc = init_proc_7445;
6183 pcc->check_pow = check_pow_hid0_74xx;
6184 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6185 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6186 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6187 PPC_FLOAT_STFIWX |
6188 PPC_CACHE | PPC_CACHE_ICBI |
6189 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6190 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6191 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6192 PPC_MEM_TLBIA | PPC_74xx_TLB |
6193 PPC_SEGMENT | PPC_EXTERN |
6194 PPC_ALTIVEC;
6195 pcc->insns_flags2 = PPC_NONE;
6196 pcc->msr_mask = 0x000000000205FF77ULL;
6197 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6198 pcc->excp_model = POWERPC_EXCP_74xx;
6199 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6200 pcc->bfd_mach = bfd_mach_ppc_7400;
6201 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6202 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6203 POWERPC_FLAG_BUS_CLK;
6204 }
6205
6206 static void init_proc_7455 (CPUPPCState *env)
6207 {
6208 gen_spr_ne_601(env);
6209 gen_spr_7xx(env);
6210 /* Time base */
6211 gen_tbl(env);
6212 /* 74xx specific SPR */
6213 gen_spr_74xx(env);
6214 /* Level 3 cache control */
6215 gen_l3_ctrl(env);
6216 /* LDSTCR */
6217 /* XXX : not implemented */
6218 spr_register(env, SPR_LDSTCR, "LDSTCR",
6219 SPR_NOACCESS, SPR_NOACCESS,
6220 &spr_read_generic, &spr_write_generic,
6221 0x00000000);
6222 /* ICTRL */
6223 /* XXX : not implemented */
6224 spr_register(env, SPR_ICTRL, "ICTRL",
6225 SPR_NOACCESS, SPR_NOACCESS,
6226 &spr_read_generic, &spr_write_generic,
6227 0x00000000);
6228 /* MSSSR0 */
6229 /* XXX : not implemented */
6230 spr_register(env, SPR_MSSSR0, "MSSSR0",
6231 SPR_NOACCESS, SPR_NOACCESS,
6232 &spr_read_generic, &spr_write_generic,
6233 0x00000000);
6234 /* PMC */
6235 /* XXX : not implemented */
6236 spr_register(env, SPR_PMC5, "PMC5",
6237 SPR_NOACCESS, SPR_NOACCESS,
6238 &spr_read_generic, &spr_write_generic,
6239 0x00000000);
6240 /* XXX : not implemented */
6241 spr_register(env, SPR_UPMC5, "UPMC5",
6242 &spr_read_ureg, SPR_NOACCESS,
6243 &spr_read_ureg, SPR_NOACCESS,
6244 0x00000000);
6245 /* XXX : not implemented */
6246 spr_register(env, SPR_PMC6, "PMC6",
6247 SPR_NOACCESS, SPR_NOACCESS,
6248 &spr_read_generic, &spr_write_generic,
6249 0x00000000);
6250 /* XXX : not implemented */
6251 spr_register(env, SPR_UPMC6, "UPMC6",
6252 &spr_read_ureg, SPR_NOACCESS,
6253 &spr_read_ureg, SPR_NOACCESS,
6254 0x00000000);
6255 /* SPRGs */
6256 spr_register(env, SPR_SPRG4, "SPRG4",
6257 SPR_NOACCESS, SPR_NOACCESS,
6258 &spr_read_generic, &spr_write_generic,
6259 0x00000000);
6260 spr_register(env, SPR_USPRG4, "USPRG4",
6261 &spr_read_ureg, SPR_NOACCESS,
6262 &spr_read_ureg, SPR_NOACCESS,
6263 0x00000000);
6264 spr_register(env, SPR_SPRG5, "SPRG5",
6265 SPR_NOACCESS, SPR_NOACCESS,
6266 &spr_read_generic, &spr_write_generic,
6267 0x00000000);
6268 spr_register(env, SPR_USPRG5, "USPRG5",
6269 &spr_read_ureg, SPR_NOACCESS,
6270 &spr_read_ureg, SPR_NOACCESS,
6271 0x00000000);
6272 spr_register(env, SPR_SPRG6, "SPRG6",
6273 SPR_NOACCESS, SPR_NOACCESS,
6274 &spr_read_generic, &spr_write_generic,
6275 0x00000000);
6276 spr_register(env, SPR_USPRG6, "USPRG6",
6277 &spr_read_ureg, SPR_NOACCESS,
6278 &spr_read_ureg, SPR_NOACCESS,
6279 0x00000000);
6280 spr_register(env, SPR_SPRG7, "SPRG7",
6281 SPR_NOACCESS, SPR_NOACCESS,
6282 &spr_read_generic, &spr_write_generic,
6283 0x00000000);
6284 spr_register(env, SPR_USPRG7, "USPRG7",
6285 &spr_read_ureg, SPR_NOACCESS,
6286 &spr_read_ureg, SPR_NOACCESS,
6287 0x00000000);
6288 /* Memory management */
6289 gen_low_BATs(env);
6290 gen_high_BATs(env);
6291 gen_74xx_soft_tlb(env, 128, 2);
6292 init_excp_7450(env);
6293 env->dcache_line_size = 32;
6294 env->icache_line_size = 32;
6295 /* Allocate hardware IRQ controller */
6296 ppc6xx_irq_init(env);
6297 }
6298
6299 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
6300 {
6301 DeviceClass *dc = DEVICE_CLASS(oc);
6302 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6303
6304 dc->desc = "PowerPC 7455 (aka G4)";
6305 pcc->init_proc = init_proc_7455;
6306 pcc->check_pow = check_pow_hid0_74xx;
6307 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6308 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6309 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6310 PPC_FLOAT_STFIWX |
6311 PPC_CACHE | PPC_CACHE_ICBI |
6312 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6313 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6314 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6315 PPC_MEM_TLBIA | PPC_74xx_TLB |
6316 PPC_SEGMENT | PPC_EXTERN |
6317 PPC_ALTIVEC;
6318 pcc->insns_flags2 = PPC_NONE;
6319 pcc->msr_mask = 0x000000000205FF77ULL;
6320 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6321 pcc->excp_model = POWERPC_EXCP_74xx;
6322 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6323 pcc->bfd_mach = bfd_mach_ppc_7400;
6324 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6325 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6326 POWERPC_FLAG_BUS_CLK;
6327 }
6328
6329 static void init_proc_7457 (CPUPPCState *env)
6330 {
6331 gen_spr_ne_601(env);
6332 gen_spr_7xx(env);
6333 /* Time base */
6334 gen_tbl(env);
6335 /* 74xx specific SPR */
6336 gen_spr_74xx(env);
6337 /* Level 3 cache control */
6338 gen_l3_ctrl(env);
6339 /* L3ITCR1 */
6340 /* XXX : not implemented */
6341 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6342 SPR_NOACCESS, SPR_NOACCESS,
6343 &spr_read_generic, &spr_write_generic,
6344 0x00000000);
6345 /* L3ITCR2 */
6346 /* XXX : not implemented */
6347 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6348 SPR_NOACCESS, SPR_NOACCESS,
6349 &spr_read_generic, &spr_write_generic,
6350 0x00000000);
6351 /* L3ITCR3 */
6352 /* XXX : not implemented */
6353 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6354 SPR_NOACCESS, SPR_NOACCESS,
6355 &spr_read_generic, &spr_write_generic,
6356 0x00000000);
6357 /* L3OHCR */
6358 /* XXX : not implemented */
6359 spr_register(env, SPR_L3OHCR, "L3OHCR",
6360 SPR_NOACCESS, SPR_NOACCESS,
6361 &spr_read_generic, &spr_write_generic,
6362 0x00000000);
6363 /* LDSTCR */
6364 /* XXX : not implemented */
6365 spr_register(env, SPR_LDSTCR, "LDSTCR",
6366 SPR_NOACCESS, SPR_NOACCESS,
6367 &spr_read_generic, &spr_write_generic,
6368 0x00000000);
6369 /* ICTRL */
6370 /* XXX : not implemented */
6371 spr_register(env, SPR_ICTRL, "ICTRL",
6372 SPR_NOACCESS, SPR_NOACCESS,
6373 &spr_read_generic, &spr_write_generic,
6374 0x00000000);
6375 /* MSSSR0 */
6376 /* XXX : not implemented */
6377 spr_register(env, SPR_MSSSR0, "MSSSR0",
6378 SPR_NOACCESS, SPR_NOACCESS,
6379 &spr_read_generic, &spr_write_generic,
6380 0x00000000);
6381 /* PMC */
6382 /* XXX : not implemented */
6383 spr_register(env, SPR_PMC5, "PMC5",
6384 SPR_NOACCESS, SPR_NOACCESS,
6385 &spr_read_generic, &spr_write_generic,
6386 0x00000000);
6387 /* XXX : not implemented */
6388 spr_register(env, SPR_UPMC5, "UPMC5",
6389 &spr_read_ureg, SPR_NOACCESS,
6390 &spr_read_ureg, SPR_NOACCESS,
6391 0x00000000);
6392 /* XXX : not implemented */
6393 spr_register(env, SPR_PMC6, "PMC6",
6394 SPR_NOACCESS, SPR_NOACCESS,
6395 &spr_read_generic, &spr_write_generic,
6396 0x00000000);
6397 /* XXX : not implemented */
6398 spr_register(env, SPR_UPMC6, "UPMC6",
6399 &spr_read_ureg, SPR_NOACCESS,
6400 &spr_read_ureg, SPR_NOACCESS,
6401 0x00000000);
6402 /* SPRGs */
6403 spr_register(env, SPR_SPRG4, "SPRG4",
6404 SPR_NOACCESS, SPR_NOACCESS,
6405 &spr_read_generic, &spr_write_generic,
6406 0x00000000);
6407 spr_register(env, SPR_USPRG4, "USPRG4",
6408 &spr_read_ureg, SPR_NOACCESS,
6409 &spr_read_ureg, SPR_NOACCESS,
6410 0x00000000);
6411 spr_register(env, SPR_SPRG5, "SPRG5",
6412 SPR_NOACCESS, SPR_NOACCESS,
6413 &spr_read_generic, &spr_write_generic,
6414 0x00000000);
6415 spr_register(env, SPR_USPRG5, "USPRG5",
6416 &spr_read_ureg, SPR_NOACCESS,
6417 &spr_read_ureg, SPR_NOACCESS,
6418 0x00000000);
6419 spr_register(env, SPR_SPRG6, "SPRG6",
6420 SPR_NOACCESS, SPR_NOACCESS,
6421 &spr_read_generic, &spr_write_generic,
6422 0x00000000);
6423 spr_register(env, SPR_USPRG6, "USPRG6",
6424 &spr_read_ureg, SPR_NOACCESS,
6425 &spr_read_ureg, SPR_NOACCESS,
6426 0x00000000);
6427 spr_register(env, SPR_SPRG7, "SPRG7",
6428 SPR_NOACCESS, SPR_NOACCESS,
6429 &spr_read_generic, &spr_write_generic,
6430 0x00000000);
6431 spr_register(env, SPR_USPRG7, "USPRG7",
6432 &spr_read_ureg, SPR_NOACCESS,
6433 &spr_read_ureg, SPR_NOACCESS,
6434 0x00000000);
6435 /* Memory management */
6436 gen_low_BATs(env);
6437 gen_high_BATs(env);
6438 gen_74xx_soft_tlb(env, 128, 2);
6439 init_excp_7450(env);
6440 env->dcache_line_size = 32;
6441 env->icache_line_size = 32;
6442 /* Allocate hardware IRQ controller */
6443 ppc6xx_irq_init(env);
6444 }
6445
6446 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
6447 {
6448 DeviceClass *dc = DEVICE_CLASS(oc);
6449 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6450
6451 dc->desc = "PowerPC 7457 (aka G4)";
6452 pcc->init_proc = init_proc_7457;
6453 pcc->check_pow = check_pow_hid0_74xx;
6454 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6455 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6456 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6457 PPC_FLOAT_STFIWX |
6458 PPC_CACHE | PPC_CACHE_ICBI |
6459 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6460 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6461 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6462 PPC_MEM_TLBIA | PPC_74xx_TLB |
6463 PPC_SEGMENT | PPC_EXTERN |
6464 PPC_ALTIVEC;
6465 pcc->insns_flags2 = PPC_NONE;
6466 pcc->msr_mask = 0x000000000205FF77ULL;
6467 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6468 pcc->excp_model = POWERPC_EXCP_74xx;
6469 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6470 pcc->bfd_mach = bfd_mach_ppc_7400;
6471 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6472 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6473 POWERPC_FLAG_BUS_CLK;
6474 }
6475
6476 #if defined (TARGET_PPC64)
6477 #if defined(CONFIG_USER_ONLY)
6478 #define POWERPC970_HID5_INIT 0x00000080
6479 #else
6480 #define POWERPC970_HID5_INIT 0x00000000
6481 #endif
6482
6483 static int check_pow_970 (CPUPPCState *env)
6484 {
6485 if (env->spr[SPR_HID0] & 0x00600000)
6486 return 1;
6487
6488 return 0;
6489 }
6490
6491 static void init_proc_970 (CPUPPCState *env)
6492 {
6493 gen_spr_ne_601(env);
6494 gen_spr_7xx(env);
6495 /* Time base */
6496 gen_tbl(env);
6497 /* Hardware implementation registers */
6498 /* XXX : not implemented */
6499 spr_register(env, SPR_HID0, "HID0",
6500 SPR_NOACCESS, SPR_NOACCESS,
6501 &spr_read_generic, &spr_write_clear,
6502 0x60000000);
6503 /* XXX : not implemented */
6504 spr_register(env, SPR_HID1, "HID1",
6505 SPR_NOACCESS, SPR_NOACCESS,
6506 &spr_read_generic, &spr_write_generic,
6507 0x00000000);
6508 /* XXX : not implemented */
6509 spr_register(env, SPR_750FX_HID2, "HID2",
6510 SPR_NOACCESS, SPR_NOACCESS,
6511 &spr_read_generic, &spr_write_generic,
6512 0x00000000);
6513 /* XXX : not implemented */
6514 spr_register(env, SPR_970_HID5, "HID5",
6515 SPR_NOACCESS, SPR_NOACCESS,
6516 &spr_read_generic, &spr_write_generic,
6517 POWERPC970_HID5_INIT);
6518 /* XXX : not implemented */
6519 spr_register(env, SPR_L2CR, "L2CR",
6520 SPR_NOACCESS, SPR_NOACCESS,
6521 &spr_read_generic, &spr_write_generic,
6522 0x00000000);
6523 /* Memory management */
6524 /* XXX: not correct */
6525 gen_low_BATs(env);
6526 /* XXX : not implemented */
6527 spr_register(env, SPR_MMUCFG, "MMUCFG",
6528 SPR_NOACCESS, SPR_NOACCESS,
6529 &spr_read_generic, SPR_NOACCESS,
6530 0x00000000); /* TOFIX */
6531 /* XXX : not implemented */
6532 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6533 SPR_NOACCESS, SPR_NOACCESS,
6534 &spr_read_generic, &spr_write_generic,
6535 0x00000000); /* TOFIX */
6536 spr_register(env, SPR_HIOR, "SPR_HIOR",
6537 SPR_NOACCESS, SPR_NOACCESS,
6538 &spr_read_hior, &spr_write_hior,
6539 0x00000000);
6540 #if !defined(CONFIG_USER_ONLY)
6541 env->slb_nr = 32;
6542 #endif
6543 init_excp_970(env);
6544 env->dcache_line_size = 128;
6545 env->icache_line_size = 128;
6546 /* Allocate hardware IRQ controller */
6547 ppc970_irq_init(env);
6548 /* Can't find information on what this should be on reset. This
6549 * value is the one used by 74xx processors. */
6550 vscr_init(env, 0x00010000);
6551 }
6552
6553 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
6554 {
6555 DeviceClass *dc = DEVICE_CLASS(oc);
6556 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6557
6558 dc->desc = "PowerPC 970";
6559 pcc->init_proc = init_proc_970;
6560 pcc->check_pow = check_pow_970;
6561 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6562 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6563 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6564 PPC_FLOAT_STFIWX |
6565 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6566 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6567 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6568 PPC_64B | PPC_ALTIVEC |
6569 PPC_SEGMENT_64B | PPC_SLBI;
6570 pcc->insns_flags2 = PPC_NONE;
6571 pcc->msr_mask = 0x900000000204FF36ULL;
6572 pcc->mmu_model = POWERPC_MMU_64B;
6573 pcc->excp_model = POWERPC_EXCP_970;
6574 pcc->bus_model = PPC_FLAGS_INPUT_970;
6575 pcc->bfd_mach = bfd_mach_ppc64;
6576 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6577 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6578 POWERPC_FLAG_BUS_CLK;
6579 }
6580
6581 static int check_pow_970FX (CPUPPCState *env)
6582 {
6583 if (env->spr[SPR_HID0] & 0x00600000)
6584 return 1;
6585
6586 return 0;
6587 }
6588
6589 static void init_proc_970FX (CPUPPCState *env)
6590 {
6591 gen_spr_ne_601(env);
6592 gen_spr_7xx(env);
6593 /* Time base */
6594 gen_tbl(env);
6595 /* Hardware implementation registers */
6596 /* XXX : not implemented */
6597 spr_register(env, SPR_HID0, "HID0",
6598 SPR_NOACCESS, SPR_NOACCESS,
6599 &spr_read_generic, &spr_write_clear,
6600 0x60000000);
6601 /* XXX : not implemented */
6602 spr_register(env, SPR_HID1, "HID1",
6603 SPR_NOACCESS, SPR_NOACCESS,
6604 &spr_read_generic, &spr_write_generic,
6605 0x00000000);
6606 /* XXX : not implemented */
6607 spr_register(env, SPR_750FX_HID2, "HID2",
6608 SPR_NOACCESS, SPR_NOACCESS,
6609 &spr_read_generic, &spr_write_generic,
6610 0x00000000);
6611 /* XXX : not implemented */
6612 spr_register(env, SPR_970_HID5, "HID5",
6613 SPR_NOACCESS, SPR_NOACCESS,
6614 &spr_read_generic, &spr_write_generic,
6615 POWERPC970_HID5_INIT);
6616 /* XXX : not implemented */
6617 spr_register(env, SPR_L2CR, "L2CR",
6618 SPR_NOACCESS, SPR_NOACCESS,
6619 &spr_read_generic, &spr_write_generic,
6620 0x00000000);
6621 /* Memory management */
6622 /* XXX: not correct */
6623 gen_low_BATs(env);
6624 /* XXX : not implemented */
6625 spr_register(env, SPR_MMUCFG, "MMUCFG",
6626 SPR_NOACCESS, SPR_NOACCESS,
6627 &spr_read_generic, SPR_NOACCESS,
6628 0x00000000); /* TOFIX */
6629 /* XXX : not implemented */
6630 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6631 SPR_NOACCESS, SPR_NOACCESS,
6632 &spr_read_generic, &spr_write_generic,
6633 0x00000000); /* TOFIX */
6634 spr_register(env, SPR_HIOR, "SPR_HIOR",
6635 SPR_NOACCESS, SPR_NOACCESS,
6636 &spr_read_hior, &spr_write_hior,
6637 0x00000000);
6638 spr_register(env, SPR_CTRL, "SPR_CTRL",
6639 SPR_NOACCESS, SPR_NOACCESS,
6640 &spr_read_generic, &spr_write_generic,
6641 0x00000000);
6642 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6643 SPR_NOACCESS, SPR_NOACCESS,
6644 &spr_read_generic, &spr_write_generic,
6645 0x00000000);
6646 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6647 &spr_read_generic, &spr_write_generic,
6648 &spr_read_generic, &spr_write_generic,
6649 0x00000000);
6650 #if !defined(CONFIG_USER_ONLY)
6651 env->slb_nr = 64;
6652 #endif
6653 init_excp_970(env);
6654 env->dcache_line_size = 128;
6655 env->icache_line_size = 128;
6656 /* Allocate hardware IRQ controller */
6657 ppc970_irq_init(env);
6658 /* Can't find information on what this should be on reset. This
6659 * value is the one used by 74xx processors. */
6660 vscr_init(env, 0x00010000);
6661 }
6662
6663 POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
6664 {
6665 DeviceClass *dc = DEVICE_CLASS(oc);
6666 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6667
6668 dc->desc = "PowerPC 970FX (aka G5)";
6669 pcc->init_proc = init_proc_970FX;
6670 pcc->check_pow = check_pow_970FX;
6671 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6672 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6673 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6674 PPC_FLOAT_STFIWX |
6675 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6676 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6677 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6678 PPC_64B | PPC_ALTIVEC |
6679 PPC_SEGMENT_64B | PPC_SLBI;
6680 pcc->insns_flags2 = PPC_NONE;
6681 pcc->msr_mask = 0x800000000204FF36ULL;
6682 pcc->mmu_model = POWERPC_MMU_64B;
6683 pcc->excp_model = POWERPC_EXCP_970;
6684 pcc->bus_model = PPC_FLAGS_INPUT_970;
6685 pcc->bfd_mach = bfd_mach_ppc64;
6686 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6687 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6688 POWERPC_FLAG_BUS_CLK;
6689 }
6690
6691 static int check_pow_970GX (CPUPPCState *env)
6692 {
6693 if (env->spr[SPR_HID0] & 0x00600000)
6694 return 1;
6695
6696 return 0;
6697 }
6698
6699 static void init_proc_970GX (CPUPPCState *env)
6700 {
6701 gen_spr_ne_601(env);
6702 gen_spr_7xx(env);
6703 /* Time base */
6704 gen_tbl(env);
6705 /* Hardware implementation registers */
6706 /* XXX : not implemented */
6707 spr_register(env, SPR_HID0, "HID0",
6708 SPR_NOACCESS, SPR_NOACCESS,
6709 &spr_read_generic, &spr_write_clear,
6710 0x60000000);
6711 /* XXX : not implemented */
6712 spr_register(env, SPR_HID1, "HID1",
6713 SPR_NOACCESS, SPR_NOACCESS,
6714 &spr_read_generic, &spr_write_generic,
6715 0x00000000);
6716 /* XXX : not implemented */
6717 spr_register(env, SPR_750FX_HID2, "HID2",
6718 SPR_NOACCESS, SPR_NOACCESS,
6719 &spr_read_generic, &spr_write_generic,
6720 0x00000000);
6721 /* XXX : not implemented */
6722 spr_register(env, SPR_970_HID5, "HID5",
6723 SPR_NOACCESS, SPR_NOACCESS,
6724 &spr_read_generic, &spr_write_generic,
6725 POWERPC970_HID5_INIT);
6726 /* XXX : not implemented */
6727 spr_register(env, SPR_L2CR, "L2CR",
6728 SPR_NOACCESS, SPR_NOACCESS,
6729 &spr_read_generic, &spr_write_generic,
6730 0x00000000);
6731 /* Memory management */
6732 /* XXX: not correct */
6733 gen_low_BATs(env);
6734 /* XXX : not implemented */
6735 spr_register(env, SPR_MMUCFG, "MMUCFG",
6736 SPR_NOACCESS, SPR_NOACCESS,
6737 &spr_read_generic, SPR_NOACCESS,
6738 0x00000000); /* TOFIX */
6739 /* XXX : not implemented */
6740 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6741 SPR_NOACCESS, SPR_NOACCESS,
6742 &spr_read_generic, &spr_write_generic,
6743 0x00000000); /* TOFIX */
6744 spr_register(env, SPR_HIOR, "SPR_HIOR",
6745 SPR_NOACCESS, SPR_NOACCESS,
6746 &spr_read_hior, &spr_write_hior,
6747 0x00000000);
6748 #if !defined(CONFIG_USER_ONLY)
6749 env->slb_nr = 32;
6750 #endif
6751 init_excp_970(env);
6752 env->dcache_line_size = 128;
6753 env->icache_line_size = 128;
6754 /* Allocate hardware IRQ controller */
6755 ppc970_irq_init(env);
6756 /* Can't find information on what this should be on reset. This
6757 * value is the one used by 74xx processors. */
6758 vscr_init(env, 0x00010000);
6759 }
6760
6761 POWERPC_FAMILY(970GX)(ObjectClass *oc, void *data)
6762 {
6763 DeviceClass *dc = DEVICE_CLASS(oc);
6764 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6765
6766 dc->desc = "PowerPC 970 GX";
6767 pcc->init_proc = init_proc_970GX;
6768 pcc->check_pow = check_pow_970GX;
6769 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6770 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6771 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6772 PPC_FLOAT_STFIWX |
6773 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6774 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6775 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6776 PPC_64B | PPC_ALTIVEC |
6777 PPC_SEGMENT_64B | PPC_SLBI;
6778 pcc->insns_flags2 = PPC_NONE;
6779 pcc->msr_mask = 0x800000000204FF36ULL;
6780 pcc->mmu_model = POWERPC_MMU_64B;
6781 pcc->excp_model = POWERPC_EXCP_970;
6782 pcc->bus_model = PPC_FLAGS_INPUT_970;
6783 pcc->bfd_mach = bfd_mach_ppc64;
6784 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6785 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6786 POWERPC_FLAG_BUS_CLK;
6787 }
6788
6789 static int check_pow_970MP (CPUPPCState *env)
6790 {
6791 if (env->spr[SPR_HID0] & 0x01C00000)
6792 return 1;
6793
6794 return 0;
6795 }
6796
6797 static void init_proc_970MP (CPUPPCState *env)
6798 {
6799 gen_spr_ne_601(env);
6800 gen_spr_7xx(env);
6801 /* Time base */
6802 gen_tbl(env);
6803 /* Hardware implementation registers */
6804 /* XXX : not implemented */
6805 spr_register(env, SPR_HID0, "HID0",
6806 SPR_NOACCESS, SPR_NOACCESS,
6807 &spr_read_generic, &spr_write_clear,
6808 0x60000000);
6809 /* XXX : not implemented */
6810 spr_register(env, SPR_HID1, "HID1",
6811 SPR_NOACCESS, SPR_NOACCESS,
6812 &spr_read_generic, &spr_write_generic,
6813 0x00000000);
6814 /* XXX : not implemented */
6815 spr_register(env, SPR_750FX_HID2, "HID2",
6816 SPR_NOACCESS, SPR_NOACCESS,
6817 &spr_read_generic, &spr_write_generic,
6818 0x00000000);
6819 /* XXX : not implemented */
6820 spr_register(env, SPR_970_HID5, "HID5",
6821 SPR_NOACCESS, SPR_NOACCESS,
6822 &spr_read_generic, &spr_write_generic,
6823 POWERPC970_HID5_INIT);
6824 /* XXX : not implemented */
6825 spr_register(env, SPR_L2CR, "L2CR",
6826 SPR_NOACCESS, SPR_NOACCESS,
6827 &spr_read_generic, &spr_write_generic,
6828 0x00000000);
6829 /* Memory management */
6830 /* XXX: not correct */
6831 gen_low_BATs(env);
6832 /* XXX : not implemented */
6833 spr_register(env, SPR_MMUCFG, "MMUCFG",
6834 SPR_NOACCESS, SPR_NOACCESS,
6835 &spr_read_generic, SPR_NOACCESS,
6836 0x00000000); /* TOFIX */
6837 /* XXX : not implemented */
6838 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6839 SPR_NOACCESS, SPR_NOACCESS,
6840 &spr_read_generic, &spr_write_generic,
6841 0x00000000); /* TOFIX */
6842 spr_register(env, SPR_HIOR, "SPR_HIOR",
6843 SPR_NOACCESS, SPR_NOACCESS,
6844 &spr_read_hior, &spr_write_hior,
6845 0x00000000);
6846 #if !defined(CONFIG_USER_ONLY)
6847 env->slb_nr = 32;
6848 #endif
6849 init_excp_970(env);
6850 env->dcache_line_size = 128;
6851 env->icache_line_size = 128;
6852 /* Allocate hardware IRQ controller */
6853 ppc970_irq_init(env);
6854 /* Can't find information on what this should be on reset. This
6855 * value is the one used by 74xx processors. */
6856 vscr_init(env, 0x00010000);
6857 }
6858
6859 POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
6860 {
6861 DeviceClass *dc = DEVICE_CLASS(oc);
6862 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6863
6864 dc->desc = "PowerPC 970 MP";
6865 pcc->init_proc = init_proc_970MP;
6866 pcc->check_pow = check_pow_970MP;
6867 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6868 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6869 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6870 PPC_FLOAT_STFIWX |
6871 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6872 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6873 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6874 PPC_64B | PPC_ALTIVEC |
6875 PPC_SEGMENT_64B | PPC_SLBI;
6876 pcc->insns_flags2 = PPC_NONE;
6877 pcc->msr_mask = 0x900000000204FF36ULL;
6878 pcc->mmu_model = POWERPC_MMU_64B;
6879 pcc->excp_model = POWERPC_EXCP_970;
6880 pcc->bus_model = PPC_FLAGS_INPUT_970;
6881 pcc->bfd_mach = bfd_mach_ppc64;
6882 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6883 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6884 POWERPC_FLAG_BUS_CLK;
6885 }
6886
6887 static void init_proc_POWER7 (CPUPPCState *env)
6888 {
6889 gen_spr_ne_601(env);
6890 gen_spr_7xx(env);
6891 /* Time base */
6892 gen_tbl(env);
6893 /* Processor identification */
6894 spr_register(env, SPR_PIR, "PIR",
6895 SPR_NOACCESS, SPR_NOACCESS,
6896 &spr_read_generic, &spr_write_pir,
6897 0x00000000);
6898 #if !defined(CONFIG_USER_ONLY)
6899 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6900 spr_register_kvm(env, SPR_PURR, "PURR",
6901 &spr_read_purr, SPR_NOACCESS,
6902 &spr_read_purr, SPR_NOACCESS,
6903 KVM_REG_PPC_PURR, 0x00000000);
6904 spr_register_kvm(env, SPR_SPURR, "SPURR",
6905 &spr_read_purr, SPR_NOACCESS,
6906 &spr_read_purr, SPR_NOACCESS,
6907 KVM_REG_PPC_SPURR, 0x00000000);
6908 spr_register(env, SPR_CFAR, "SPR_CFAR",
6909 SPR_NOACCESS, SPR_NOACCESS,
6910 &spr_read_cfar, &spr_write_cfar,
6911 0x00000000);
6912 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
6913 SPR_NOACCESS, SPR_NOACCESS,
6914 &spr_read_generic, &spr_write_generic,
6915 KVM_REG_PPC_DSCR, 0x00000000);
6916 #endif /* !CONFIG_USER_ONLY */
6917 /* Memory management */
6918 /* XXX : not implemented */
6919 spr_register(env, SPR_MMUCFG, "MMUCFG",
6920 SPR_NOACCESS, SPR_NOACCESS,
6921 &spr_read_generic, SPR_NOACCESS,
6922 0x00000000); /* TOFIX */
6923 gen_spr_amr(env);
6924 /* XXX : not implemented */
6925 spr_register(env, SPR_CTRL, "SPR_CTRLT",
6926 SPR_NOACCESS, SPR_NOACCESS,
6927 &spr_read_generic, &spr_write_generic,
6928 0x80800000);
6929 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
6930 SPR_NOACCESS, SPR_NOACCESS,
6931 &spr_read_generic, &spr_write_generic,
6932 0x80800000);
6933 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6934 &spr_read_generic, &spr_write_generic,
6935 &spr_read_generic, &spr_write_generic,
6936 0x00000000);
6937 #if !defined(CONFIG_USER_ONLY)
6938 env->slb_nr = 32;
6939 #endif
6940 init_excp_POWER7(env);
6941 env->dcache_line_size = 128;
6942 env->icache_line_size = 128;
6943 /* Allocate hardware IRQ controller */
6944 ppcPOWER7_irq_init(env);
6945 /* Can't find information on what this should be on reset. This
6946 * value is the one used by 74xx processors. */
6947 vscr_init(env, 0x00010000);
6948 }
6949
6950 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
6951 {
6952 DeviceClass *dc = DEVICE_CLASS(oc);
6953 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6954
6955 dc->desc = "POWER7";
6956 pcc->init_proc = init_proc_POWER7;
6957 pcc->check_pow = check_pow_nocheck;
6958 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6959 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6960 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6961 PPC_FLOAT_STFIWX |
6962 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6963 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6964 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6965 PPC_64B | PPC_ALTIVEC |
6966 PPC_SEGMENT_64B | PPC_SLBI |
6967 PPC_POPCNTB | PPC_POPCNTWD;
6968 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX;
6969 pcc->msr_mask = 0x800000000204FF36ULL;
6970 pcc->mmu_model = POWERPC_MMU_2_06;
6971 pcc->excp_model = POWERPC_EXCP_POWER7;
6972 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6973 pcc->bfd_mach = bfd_mach_ppc64;
6974 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6975 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6976 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR;
6977 }
6978 #endif /* defined (TARGET_PPC64) */
6979
6980
6981 /*****************************************************************************/
6982 /* Generic CPU instantiation routine */
6983 static void init_ppc_proc(PowerPCCPU *cpu)
6984 {
6985 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6986 CPUPPCState *env = &cpu->env;
6987 #if !defined(CONFIG_USER_ONLY)
6988 int i;
6989
6990 env->irq_inputs = NULL;
6991 /* Set all exception vectors to an invalid address */
6992 for (i = 0; i < POWERPC_EXCP_NB; i++)
6993 env->excp_vectors[i] = (target_ulong)(-1ULL);
6994 env->hreset_excp_prefix = 0x00000000;
6995 env->ivor_mask = 0x00000000;
6996 env->ivpr_mask = 0x00000000;
6997 /* Default MMU definitions */
6998 env->nb_BATs = 0;
6999 env->nb_tlb = 0;
7000 env->nb_ways = 0;
7001 env->tlb_type = TLB_NONE;
7002 #endif
7003 /* Register SPR common to all PowerPC implementations */
7004 gen_spr_generic(env);
7005 spr_register(env, SPR_PVR, "PVR",
7006 /* Linux permits userspace to read PVR */
7007 #if defined(CONFIG_LINUX_USER)
7008 &spr_read_generic,
7009 #else
7010 SPR_NOACCESS,
7011 #endif
7012 SPR_NOACCESS,
7013 &spr_read_generic, SPR_NOACCESS,
7014 pcc->pvr);
7015 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
7016 if (pcc->svr != POWERPC_SVR_NONE) {
7017 if (pcc->svr & POWERPC_SVR_E500) {
7018 spr_register(env, SPR_E500_SVR, "SVR",
7019 SPR_NOACCESS, SPR_NOACCESS,
7020 &spr_read_generic, SPR_NOACCESS,
7021 pcc->svr & ~POWERPC_SVR_E500);
7022 } else {
7023 spr_register(env, SPR_SVR, "SVR",
7024 SPR_NOACCESS, SPR_NOACCESS,
7025 &spr_read_generic, SPR_NOACCESS,
7026 pcc->svr);
7027 }
7028 }
7029 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
7030 (*pcc->init_proc)(env);
7031 #if !defined(CONFIG_USER_ONLY)
7032 env->excp_prefix = env->hreset_excp_prefix;
7033 #endif
7034 /* MSR bits & flags consistency checks */
7035 if (env->msr_mask & (1 << 25)) {
7036 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7037 case POWERPC_FLAG_SPE:
7038 case POWERPC_FLAG_VRE:
7039 break;
7040 default:
7041 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7042 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
7043 exit(1);
7044 }
7045 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7046 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7047 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
7048 exit(1);
7049 }
7050 if (env->msr_mask & (1 << 17)) {
7051 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7052 case POWERPC_FLAG_TGPR:
7053 case POWERPC_FLAG_CE:
7054 break;
7055 default:
7056 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7057 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
7058 exit(1);
7059 }
7060 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7061 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7062 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
7063 exit(1);
7064 }
7065 if (env->msr_mask & (1 << 10)) {
7066 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7067 POWERPC_FLAG_UBLE)) {
7068 case POWERPC_FLAG_SE:
7069 case POWERPC_FLAG_DWE:
7070 case POWERPC_FLAG_UBLE:
7071 break;
7072 default:
7073 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7074 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
7075 "POWERPC_FLAG_UBLE\n");
7076 exit(1);
7077 }
7078 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7079 POWERPC_FLAG_UBLE)) {
7080 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7081 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
7082 "POWERPC_FLAG_UBLE\n");
7083 exit(1);
7084 }
7085 if (env->msr_mask & (1 << 9)) {
7086 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7087 case POWERPC_FLAG_BE:
7088 case POWERPC_FLAG_DE:
7089 break;
7090 default:
7091 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7092 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
7093 exit(1);
7094 }
7095 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7096 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7097 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
7098 exit(1);
7099 }
7100 if (env->msr_mask & (1 << 2)) {
7101 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7102 case POWERPC_FLAG_PX:
7103 case POWERPC_FLAG_PMM:
7104 break;
7105 default:
7106 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7107 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
7108 exit(1);
7109 }
7110 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7111 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7112 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
7113 exit(1);
7114 }
7115 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
7116 fprintf(stderr, "PowerPC flags inconsistency\n"
7117 "Should define the time-base and decrementer clock source\n");
7118 exit(1);
7119 }
7120 /* Allocate TLBs buffer when needed */
7121 #if !defined(CONFIG_USER_ONLY)
7122 if (env->nb_tlb != 0) {
7123 int nb_tlb = env->nb_tlb;
7124 if (env->id_tlbs != 0)
7125 nb_tlb *= 2;
7126 switch (env->tlb_type) {
7127 case TLB_6XX:
7128 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
7129 break;
7130 case TLB_EMB:
7131 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
7132 break;
7133 case TLB_MAS:
7134 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
7135 break;
7136 }
7137 /* Pre-compute some useful values */
7138 env->tlb_per_way = env->nb_tlb / env->nb_ways;
7139 }
7140 if (env->irq_inputs == NULL) {
7141 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
7142 " Attempt QEMU to crash very soon !\n");
7143 }
7144 #endif
7145 if (env->check_pow == NULL) {
7146 fprintf(stderr, "WARNING: no power management check handler "
7147 "registered.\n"
7148 " Attempt QEMU to crash very soon !\n");
7149 }
7150 }
7151
7152 #if defined(PPC_DUMP_CPU)
7153 static void dump_ppc_sprs (CPUPPCState *env)
7154 {
7155 ppc_spr_t *spr;
7156 #if !defined(CONFIG_USER_ONLY)
7157 uint32_t sr, sw;
7158 #endif
7159 uint32_t ur, uw;
7160 int i, j, n;
7161
7162 printf("Special purpose registers:\n");
7163 for (i = 0; i < 32; i++) {
7164 for (j = 0; j < 32; j++) {
7165 n = (i << 5) | j;
7166 spr = &env->spr_cb[n];
7167 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
7168 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
7169 #if !defined(CONFIG_USER_ONLY)
7170 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
7171 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
7172 if (sw || sr || uw || ur) {
7173 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
7174 (i << 5) | j, (i << 5) | j, spr->name,
7175 sw ? 'w' : '-', sr ? 'r' : '-',
7176 uw ? 'w' : '-', ur ? 'r' : '-');
7177 }
7178 #else
7179 if (uw || ur) {
7180 printf("SPR: %4d (%03x) %-8s u%c%c\n",
7181 (i << 5) | j, (i << 5) | j, spr->name,
7182 uw ? 'w' : '-', ur ? 'r' : '-');
7183 }
7184 #endif
7185 }
7186 }
7187 fflush(stdout);
7188 fflush(stderr);
7189 }
7190 #endif
7191
7192 /*****************************************************************************/
7193 #include <stdlib.h>
7194 #include <string.h>
7195
7196 /* Opcode types */
7197 enum {
7198 PPC_DIRECT = 0, /* Opcode routine */
7199 PPC_INDIRECT = 1, /* Indirect opcode table */
7200 };
7201
7202 static inline int is_indirect_opcode (void *handler)
7203 {
7204 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
7205 }
7206
7207 static inline opc_handler_t **ind_table(void *handler)
7208 {
7209 return (opc_handler_t **)((uintptr_t)handler & ~3);
7210 }
7211
7212 /* Instruction table creation */
7213 /* Opcodes tables creation */
7214 static void fill_new_table (opc_handler_t **table, int len)
7215 {
7216 int i;
7217
7218 for (i = 0; i < len; i++)
7219 table[i] = &invalid_handler;
7220 }
7221
7222 static int create_new_table (opc_handler_t **table, unsigned char idx)
7223 {
7224 opc_handler_t **tmp;
7225
7226 tmp = malloc(0x20 * sizeof(opc_handler_t));
7227 fill_new_table(tmp, 0x20);
7228 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
7229
7230 return 0;
7231 }
7232
7233 static int insert_in_table (opc_handler_t **table, unsigned char idx,
7234 opc_handler_t *handler)
7235 {
7236 if (table[idx] != &invalid_handler)
7237 return -1;
7238 table[idx] = handler;
7239
7240 return 0;
7241 }
7242
7243 static int register_direct_insn (opc_handler_t **ppc_opcodes,
7244 unsigned char idx, opc_handler_t *handler)
7245 {
7246 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
7247 printf("*** ERROR: opcode %02x already assigned in main "
7248 "opcode table\n", idx);
7249 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7250 printf(" Registered handler '%s' - new handler '%s'\n",
7251 ppc_opcodes[idx]->oname, handler->oname);
7252 #endif
7253 return -1;
7254 }
7255
7256 return 0;
7257 }
7258
7259 static int register_ind_in_table (opc_handler_t **table,
7260 unsigned char idx1, unsigned char idx2,
7261 opc_handler_t *handler)
7262 {
7263 if (table[idx1] == &invalid_handler) {
7264 if (create_new_table(table, idx1) < 0) {
7265 printf("*** ERROR: unable to create indirect table "
7266 "idx=%02x\n", idx1);
7267 return -1;
7268 }
7269 } else {
7270 if (!is_indirect_opcode(table[idx1])) {
7271 printf("*** ERROR: idx %02x already assigned to a direct "
7272 "opcode\n", idx1);
7273 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7274 printf(" Registered handler '%s' - new handler '%s'\n",
7275 ind_table(table[idx1])[idx2]->oname, handler->oname);
7276 #endif
7277 return -1;
7278 }
7279 }
7280 if (handler != NULL &&
7281 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
7282 printf("*** ERROR: opcode %02x already assigned in "
7283 "opcode table %02x\n", idx2, idx1);
7284 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7285 printf(" Registered handler '%s' - new handler '%s'\n",
7286 ind_table(table[idx1])[idx2]->oname, handler->oname);
7287 #endif
7288 return -1;
7289 }
7290
7291 return 0;
7292 }
7293
7294 static int register_ind_insn (opc_handler_t **ppc_opcodes,
7295 unsigned char idx1, unsigned char idx2,
7296 opc_handler_t *handler)
7297 {
7298 int ret;
7299
7300 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
7301
7302 return ret;
7303 }
7304
7305 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
7306 unsigned char idx1, unsigned char idx2,
7307 unsigned char idx3, opc_handler_t *handler)
7308 {
7309 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
7310 printf("*** ERROR: unable to join indirect table idx "
7311 "[%02x-%02x]\n", idx1, idx2);
7312 return -1;
7313 }
7314 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
7315 handler) < 0) {
7316 printf("*** ERROR: unable to insert opcode "
7317 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
7318 return -1;
7319 }
7320
7321 return 0;
7322 }
7323
7324 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
7325 {
7326 if (insn->opc2 != 0xFF) {
7327 if (insn->opc3 != 0xFF) {
7328 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
7329 insn->opc3, &insn->handler) < 0)
7330 return -1;
7331 } else {
7332 if (register_ind_insn(ppc_opcodes, insn->opc1,
7333 insn->opc2, &insn->handler) < 0)
7334 return -1;
7335 }
7336 } else {
7337 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
7338 return -1;
7339 }
7340
7341 return 0;
7342 }
7343
7344 static int test_opcode_table (opc_handler_t **table, int len)
7345 {
7346 int i, count, tmp;
7347
7348 for (i = 0, count = 0; i < len; i++) {
7349 /* Consistency fixup */
7350 if (table[i] == NULL)
7351 table[i] = &invalid_handler;
7352 if (table[i] != &invalid_handler) {
7353 if (is_indirect_opcode(table[i])) {
7354 tmp = test_opcode_table(ind_table(table[i]), 0x20);
7355 if (tmp == 0) {
7356 free(table[i]);
7357 table[i] = &invalid_handler;
7358 } else {
7359 count++;
7360 }
7361 } else {
7362 count++;
7363 }
7364 }
7365 }
7366
7367 return count;
7368 }
7369
7370 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
7371 {
7372 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
7373 printf("*** WARNING: no opcode defined !\n");
7374 }
7375
7376 /*****************************************************************************/
7377 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
7378 {
7379 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7380 CPUPPCState *env = &cpu->env;
7381 opcode_t *opc;
7382
7383 fill_new_table(env->opcodes, 0x40);
7384 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
7385 if (((opc->handler.type & pcc->insns_flags) != 0) ||
7386 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
7387 if (register_insn(env->opcodes, opc) < 0) {
7388 error_setg(errp, "ERROR initializing PowerPC instruction "
7389 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
7390 opc->opc3);
7391 return;
7392 }
7393 }
7394 }
7395 fix_opcode_tables(env->opcodes);
7396 fflush(stdout);
7397 fflush(stderr);
7398 }
7399
7400 #if defined(PPC_DUMP_CPU)
7401 static void dump_ppc_insns (CPUPPCState *env)
7402 {
7403 opc_handler_t **table, *handler;
7404 const char *p, *q;
7405 uint8_t opc1, opc2, opc3;
7406
7407 printf("Instructions set:\n");
7408 /* opc1 is 6 bits long */
7409 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
7410 table = env->opcodes;
7411 handler = table[opc1];
7412 if (is_indirect_opcode(handler)) {
7413 /* opc2 is 5 bits long */
7414 for (opc2 = 0; opc2 < 0x20; opc2++) {
7415 table = env->opcodes;
7416 handler = env->opcodes[opc1];
7417 table = ind_table(handler);
7418 handler = table[opc2];
7419 if (is_indirect_opcode(handler)) {
7420 table = ind_table(handler);
7421 /* opc3 is 5 bits long */
7422 for (opc3 = 0; opc3 < 0x20; opc3++) {
7423 handler = table[opc3];
7424 if (handler->handler != &gen_invalid) {
7425 /* Special hack to properly dump SPE insns */
7426 p = strchr(handler->oname, '_');
7427 if (p == NULL) {
7428 printf("INSN: %02x %02x %02x (%02d %04d) : "
7429 "%s\n",
7430 opc1, opc2, opc3, opc1,
7431 (opc3 << 5) | opc2,
7432 handler->oname);
7433 } else {
7434 q = "speundef";
7435 if ((p - handler->oname) != strlen(q) ||
7436 memcmp(handler->oname, q, strlen(q)) != 0) {
7437 /* First instruction */
7438 printf("INSN: %02x %02x %02x (%02d %04d) : "
7439 "%.*s\n",
7440 opc1, opc2 << 1, opc3, opc1,
7441 (opc3 << 6) | (opc2 << 1),
7442 (int)(p - handler->oname),
7443 handler->oname);
7444 }
7445 if (strcmp(p + 1, q) != 0) {
7446 /* Second instruction */
7447 printf("INSN: %02x %02x %02x (%02d %04d) : "
7448 "%s\n",
7449 opc1, (opc2 << 1) | 1, opc3, opc1,
7450 (opc3 << 6) | (opc2 << 1) | 1,
7451 p + 1);
7452 }
7453 }
7454 }
7455 }
7456 } else {
7457 if (handler->handler != &gen_invalid) {
7458 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
7459 opc1, opc2, opc1, opc2, handler->oname);
7460 }
7461 }
7462 }
7463 } else {
7464 if (handler->handler != &gen_invalid) {
7465 printf("INSN: %02x -- -- (%02d ----) : %s\n",
7466 opc1, opc1, handler->oname);
7467 }
7468 }
7469 }
7470 }
7471 #endif
7472
7473 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7474 {
7475 if (n < 32) {
7476 stfq_p(mem_buf, env->fpr[n]);
7477 return 8;
7478 }
7479 if (n == 32) {
7480 stl_p(mem_buf, env->fpscr);
7481 return 4;
7482 }
7483 return 0;
7484 }
7485
7486 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7487 {
7488 if (n < 32) {
7489 env->fpr[n] = ldfq_p(mem_buf);
7490 return 8;
7491 }
7492 if (n == 32) {
7493 helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
7494 return 4;
7495 }
7496 return 0;
7497 }
7498
7499 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7500 {
7501 if (n < 32) {
7502 #ifdef HOST_WORDS_BIGENDIAN
7503 stq_p(mem_buf, env->avr[n].u64[0]);
7504 stq_p(mem_buf+8, env->avr[n].u64[1]);
7505 #else
7506 stq_p(mem_buf, env->avr[n].u64[1]);
7507 stq_p(mem_buf+8, env->avr[n].u64[0]);
7508 #endif
7509 return 16;
7510 }
7511 if (n == 32) {
7512 stl_p(mem_buf, env->vscr);
7513 return 4;
7514 }
7515 if (n == 33) {
7516 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
7517 return 4;
7518 }
7519 return 0;
7520 }
7521
7522 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7523 {
7524 if (n < 32) {
7525 #ifdef HOST_WORDS_BIGENDIAN
7526 env->avr[n].u64[0] = ldq_p(mem_buf);
7527 env->avr[n].u64[1] = ldq_p(mem_buf+8);
7528 #else
7529 env->avr[n].u64[1] = ldq_p(mem_buf);
7530 env->avr[n].u64[0] = ldq_p(mem_buf+8);
7531 #endif
7532 return 16;
7533 }
7534 if (n == 32) {
7535 env->vscr = ldl_p(mem_buf);
7536 return 4;
7537 }
7538 if (n == 33) {
7539 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
7540 return 4;
7541 }
7542 return 0;
7543 }
7544
7545 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7546 {
7547 if (n < 32) {
7548 #if defined(TARGET_PPC64)
7549 stl_p(mem_buf, env->gpr[n] >> 32);
7550 #else
7551 stl_p(mem_buf, env->gprh[n]);
7552 #endif
7553 return 4;
7554 }
7555 if (n == 32) {
7556 stq_p(mem_buf, env->spe_acc);
7557 return 8;
7558 }
7559 if (n == 33) {
7560 stl_p(mem_buf, env->spe_fscr);
7561 return 4;
7562 }
7563 return 0;
7564 }
7565
7566 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7567 {
7568 if (n < 32) {
7569 #if defined(TARGET_PPC64)
7570 target_ulong lo = (uint32_t)env->gpr[n];
7571 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
7572 env->gpr[n] = lo | hi;
7573 #else
7574 env->gprh[n] = ldl_p(mem_buf);
7575 #endif
7576 return 4;
7577 }
7578 if (n == 32) {
7579 env->spe_acc = ldq_p(mem_buf);
7580 return 8;
7581 }
7582 if (n == 33) {
7583 env->spe_fscr = ldl_p(mem_buf);
7584 return 4;
7585 }
7586 return 0;
7587 }
7588
7589 static int ppc_fixup_cpu(PowerPCCPU *cpu)
7590 {
7591 CPUPPCState *env = &cpu->env;
7592
7593 /* TCG doesn't (yet) emulate some groups of instructions that
7594 * are implemented on some otherwise supported CPUs (e.g. VSX
7595 * and decimal floating point instructions on POWER7). We
7596 * remove unsupported instruction groups from the cpu state's
7597 * instruction masks and hope the guest can cope. For at
7598 * least the pseries machine, the unavailability of these
7599 * instructions can be advertised to the guest via the device
7600 * tree. */
7601 if ((env->insns_flags & ~PPC_TCG_INSNS)
7602 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
7603 fprintf(stderr, "Warning: Disabling some instructions which are not "
7604 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
7605 env->insns_flags & ~PPC_TCG_INSNS,
7606 env->insns_flags2 & ~PPC_TCG_INSNS2);
7607 }
7608 env->insns_flags &= PPC_TCG_INSNS;
7609 env->insns_flags2 &= PPC_TCG_INSNS2;
7610 return 0;
7611 }
7612
7613 static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
7614 {
7615 PowerPCCPU *cpu = POWERPC_CPU(dev);
7616 CPUPPCState *env = &cpu->env;
7617 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7618 Error *local_err = NULL;
7619 #if !defined(CONFIG_USER_ONLY)
7620 int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
7621 #endif
7622
7623 #if !defined(CONFIG_USER_ONLY)
7624 if (smp_threads > max_smt) {
7625 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
7626 max_smt, kvm_enabled() ? "KVM" : "TCG");
7627 return;
7628 }
7629 #endif
7630
7631 if (kvm_enabled()) {
7632 if (kvmppc_fixup_cpu(cpu) != 0) {
7633 error_setg(errp, "Unable to virtualize selected CPU with KVM");
7634 return;
7635 }
7636 } else {
7637 if (ppc_fixup_cpu(cpu) != 0) {
7638 error_setg(errp, "Unable to emulate selected CPU with TCG");
7639 return;
7640 }
7641 }
7642
7643 #if defined(TARGET_PPCEMB)
7644 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
7645 error_setg(errp, "CPU does not possess a BookE MMU. "
7646 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
7647 "or choose another CPU model.");
7648 return;
7649 }
7650 #endif
7651
7652 create_ppc_opcodes(cpu, &local_err);
7653 if (local_err != NULL) {
7654 error_propagate(errp, local_err);
7655 return;
7656 }
7657 init_ppc_proc(cpu);
7658
7659 if (pcc->insns_flags & PPC_FLOAT) {
7660 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
7661 33, "power-fpu.xml", 0);
7662 }
7663 if (pcc->insns_flags & PPC_ALTIVEC) {
7664 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
7665 34, "power-altivec.xml", 0);
7666 }
7667 if (pcc->insns_flags & PPC_SPE) {
7668 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
7669 34, "power-spe.xml", 0);
7670 }
7671
7672 qemu_init_vcpu(env);
7673
7674 pcc->parent_realize(dev, errp);
7675
7676 #if defined(PPC_DUMP_CPU)
7677 {
7678 const char *mmu_model, *excp_model, *bus_model;
7679 switch (env->mmu_model) {
7680 case POWERPC_MMU_32B:
7681 mmu_model = "PowerPC 32";
7682 break;
7683 case POWERPC_MMU_SOFT_6xx:
7684 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
7685 break;
7686 case POWERPC_MMU_SOFT_74xx:
7687 mmu_model = "PowerPC 74xx with software driven TLBs";
7688 break;
7689 case POWERPC_MMU_SOFT_4xx:
7690 mmu_model = "PowerPC 4xx with software driven TLBs";
7691 break;
7692 case POWERPC_MMU_SOFT_4xx_Z:
7693 mmu_model = "PowerPC 4xx with software driven TLBs "
7694 "and zones protections";
7695 break;
7696 case POWERPC_MMU_REAL:
7697 mmu_model = "PowerPC real mode only";
7698 break;
7699 case POWERPC_MMU_MPC8xx:
7700 mmu_model = "PowerPC MPC8xx";
7701 break;
7702 case POWERPC_MMU_BOOKE:
7703 mmu_model = "PowerPC BookE";
7704 break;
7705 case POWERPC_MMU_BOOKE206:
7706 mmu_model = "PowerPC BookE 2.06";
7707 break;
7708 case POWERPC_MMU_601:
7709 mmu_model = "PowerPC 601";
7710 break;
7711 #if defined (TARGET_PPC64)
7712 case POWERPC_MMU_64B:
7713 mmu_model = "PowerPC 64";
7714 break;
7715 #endif
7716 default:
7717 mmu_model = "Unknown or invalid";
7718 break;
7719 }
7720 switch (env->excp_model) {
7721 case POWERPC_EXCP_STD:
7722 excp_model = "PowerPC";
7723 break;
7724 case POWERPC_EXCP_40x:
7725 excp_model = "PowerPC 40x";
7726 break;
7727 case POWERPC_EXCP_601:
7728 excp_model = "PowerPC 601";
7729 break;
7730 case POWERPC_EXCP_602:
7731 excp_model = "PowerPC 602";
7732 break;
7733 case POWERPC_EXCP_603:
7734 excp_model = "PowerPC 603";
7735 break;
7736 case POWERPC_EXCP_603E:
7737 excp_model = "PowerPC 603e";
7738 break;
7739 case POWERPC_EXCP_604:
7740 excp_model = "PowerPC 604";
7741 break;
7742 case POWERPC_EXCP_7x0:
7743 excp_model = "PowerPC 740/750";
7744 break;
7745 case POWERPC_EXCP_7x5:
7746 excp_model = "PowerPC 745/755";
7747 break;
7748 case POWERPC_EXCP_74xx:
7749 excp_model = "PowerPC 74xx";
7750 break;
7751 case POWERPC_EXCP_BOOKE:
7752 excp_model = "PowerPC BookE";
7753 break;
7754 #if defined (TARGET_PPC64)
7755 case POWERPC_EXCP_970:
7756 excp_model = "PowerPC 970";
7757 break;
7758 #endif
7759 default:
7760 excp_model = "Unknown or invalid";
7761 break;
7762 }
7763 switch (env->bus_model) {
7764 case PPC_FLAGS_INPUT_6xx:
7765 bus_model = "PowerPC 6xx";
7766 break;
7767 case PPC_FLAGS_INPUT_BookE:
7768 bus_model = "PowerPC BookE";
7769 break;
7770 case PPC_FLAGS_INPUT_405:
7771 bus_model = "PowerPC 405";
7772 break;
7773 case PPC_FLAGS_INPUT_401:
7774 bus_model = "PowerPC 401/403";
7775 break;
7776 case PPC_FLAGS_INPUT_RCPU:
7777 bus_model = "RCPU / MPC8xx";
7778 break;
7779 #if defined (TARGET_PPC64)
7780 case PPC_FLAGS_INPUT_970:
7781 bus_model = "PowerPC 970";
7782 break;
7783 #endif
7784 default:
7785 bus_model = "Unknown or invalid";
7786 break;
7787 }
7788 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
7789 " MMU model : %s\n",
7790 pcc->name, pcc->pvr, pcc->msr_mask, mmu_model);
7791 #if !defined(CONFIG_USER_ONLY)
7792 if (env->tlb != NULL) {
7793 printf(" %d %s TLB in %d ways\n",
7794 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
7795 env->nb_ways);
7796 }
7797 #endif
7798 printf(" Exceptions model : %s\n"
7799 " Bus model : %s\n",
7800 excp_model, bus_model);
7801 printf(" MSR features :\n");
7802 if (env->flags & POWERPC_FLAG_SPE)
7803 printf(" signal processing engine enable"
7804 "\n");
7805 else if (env->flags & POWERPC_FLAG_VRE)
7806 printf(" vector processor enable\n");
7807 if (env->flags & POWERPC_FLAG_TGPR)
7808 printf(" temporary GPRs\n");
7809 else if (env->flags & POWERPC_FLAG_CE)
7810 printf(" critical input enable\n");
7811 if (env->flags & POWERPC_FLAG_SE)
7812 printf(" single-step trace mode\n");
7813 else if (env->flags & POWERPC_FLAG_DWE)
7814 printf(" debug wait enable\n");
7815 else if (env->flags & POWERPC_FLAG_UBLE)
7816 printf(" user BTB lock enable\n");
7817 if (env->flags & POWERPC_FLAG_BE)
7818 printf(" branch-step trace mode\n");
7819 else if (env->flags & POWERPC_FLAG_DE)
7820 printf(" debug interrupt enable\n");
7821 if (env->flags & POWERPC_FLAG_PX)
7822 printf(" inclusive protection\n");
7823 else if (env->flags & POWERPC_FLAG_PMM)
7824 printf(" performance monitor mark\n");
7825 if (env->flags == POWERPC_FLAG_NONE)
7826 printf(" none\n");
7827 printf(" Time-base/decrementer clock source: %s\n",
7828 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
7829 }
7830 dump_ppc_insns(env);
7831 dump_ppc_sprs(env);
7832 fflush(stdout);
7833 #endif
7834 }
7835
7836 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
7837 {
7838 ObjectClass *oc = (ObjectClass *)a;
7839 uint32_t pvr = *(uint32_t *)b;
7840 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
7841
7842 /* -cpu host does a PVR lookup during construction */
7843 if (unlikely(strcmp(object_class_get_name(oc),
7844 TYPE_HOST_POWERPC_CPU) == 0)) {
7845 return -1;
7846 }
7847
7848 #if defined(TARGET_PPCEMB)
7849 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
7850 return -1;
7851 }
7852 #endif
7853
7854 return pcc->pvr == pvr ? 0 : -1;
7855 }
7856
7857 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
7858 {
7859 GSList *list, *item;
7860 PowerPCCPUClass *pcc = NULL;
7861
7862 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7863 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
7864 if (item != NULL) {
7865 pcc = POWERPC_CPU_CLASS(item->data);
7866 }
7867 g_slist_free(list);
7868
7869 return pcc;
7870 }
7871
7872 static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
7873 {
7874 ObjectClass *oc = (ObjectClass *)a;
7875 const char *name = b;
7876 #if defined(TARGET_PPCEMB)
7877 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7878 #endif
7879
7880 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
7881 #if defined(TARGET_PPCEMB)
7882 pcc->mmu_model == POWERPC_MMU_BOOKE &&
7883 #endif
7884 strcmp(object_class_get_name(oc) + strlen(name),
7885 "-" TYPE_POWERPC_CPU) == 0) {
7886 return 0;
7887 }
7888 return -1;
7889 }
7890
7891 #include <ctype.h>
7892
7893 static ObjectClass *ppc_cpu_class_by_name(const char *name)
7894 {
7895 GSList *list, *item;
7896 ObjectClass *ret = NULL;
7897 const char *p;
7898 int i, len;
7899
7900 /* Check if the given name is a PVR */
7901 len = strlen(name);
7902 if (len == 10 && name[0] == '0' && name[1] == 'x') {
7903 p = name + 2;
7904 goto check_pvr;
7905 } else if (len == 8) {
7906 p = name;
7907 check_pvr:
7908 for (i = 0; i < 8; i++) {
7909 if (!qemu_isxdigit(*p++))
7910 break;
7911 }
7912 if (i == 8) {
7913 ret = OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
7914 return ret;
7915 }
7916 }
7917
7918 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7919 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
7920 return ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
7921 }
7922 }
7923
7924 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7925 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
7926 if (item != NULL) {
7927 ret = OBJECT_CLASS(item->data);
7928 }
7929 g_slist_free(list);
7930
7931 return ret;
7932 }
7933
7934 PowerPCCPU *cpu_ppc_init(const char *cpu_model)
7935 {
7936 PowerPCCPU *cpu;
7937 CPUPPCState *env;
7938 ObjectClass *oc;
7939 Error *err = NULL;
7940
7941 oc = ppc_cpu_class_by_name(cpu_model);
7942 if (oc == NULL) {
7943 return NULL;
7944 }
7945
7946 cpu = POWERPC_CPU(object_new(object_class_get_name(oc)));
7947 env = &cpu->env;
7948 env->cpu_model_str = cpu_model;
7949
7950 object_property_set_bool(OBJECT(cpu), true, "realized", &err);
7951 if (err != NULL) {
7952 fprintf(stderr, "%s\n", error_get_pretty(err));
7953 error_free(err);
7954 object_unref(OBJECT(cpu));
7955 return NULL;
7956 }
7957
7958 return cpu;
7959 }
7960
7961 /* Sort by PVR, ordering special case "host" last. */
7962 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
7963 {
7964 ObjectClass *oc_a = (ObjectClass *)a;
7965 ObjectClass *oc_b = (ObjectClass *)b;
7966 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
7967 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
7968 const char *name_a = object_class_get_name(oc_a);
7969 const char *name_b = object_class_get_name(oc_b);
7970
7971 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
7972 return 1;
7973 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
7974 return -1;
7975 } else {
7976 /* Avoid an integer overflow during subtraction */
7977 if (pcc_a->pvr < pcc_b->pvr) {
7978 return -1;
7979 } else if (pcc_a->pvr > pcc_b->pvr) {
7980 return 1;
7981 } else {
7982 return 0;
7983 }
7984 }
7985 }
7986
7987 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
7988 {
7989 ObjectClass *oc = data;
7990 CPUListState *s = user_data;
7991 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7992 const char *typename = object_class_get_name(oc);
7993 char *name;
7994 int i;
7995
7996 #if defined(TARGET_PPCEMB)
7997 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
7998 return;
7999 }
8000 #endif
8001 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
8002 return;
8003 }
8004
8005 name = g_strndup(typename,
8006 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
8007 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
8008 name, pcc->pvr);
8009 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8010 const PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8011 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
8012
8013 if (alias_oc != oc) {
8014 continue;
8015 }
8016 (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
8017 alias->alias, name);
8018 }
8019 g_free(name);
8020 }
8021
8022 void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
8023 {
8024 CPUListState s = {
8025 .file = f,
8026 .cpu_fprintf = cpu_fprintf,
8027 };
8028 GSList *list;
8029
8030 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8031 list = g_slist_sort(list, ppc_cpu_list_compare);
8032 g_slist_foreach(list, ppc_cpu_list_entry, &s);
8033 g_slist_free(list);
8034
8035 #ifdef CONFIG_KVM
8036 cpu_fprintf(f, "\n");
8037 cpu_fprintf(f, "PowerPC %-16s\n", "host");
8038 #endif
8039 }
8040
8041 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
8042 {
8043 ObjectClass *oc = data;
8044 CpuDefinitionInfoList **first = user_data;
8045 const char *typename;
8046 CpuDefinitionInfoList *entry;
8047 CpuDefinitionInfo *info;
8048 #if defined(TARGET_PPCEMB)
8049 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8050
8051 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
8052 return;
8053 }
8054 #endif
8055
8056 typename = object_class_get_name(oc);
8057 info = g_malloc0(sizeof(*info));
8058 info->name = g_strndup(typename,
8059 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
8060
8061 entry = g_malloc0(sizeof(*entry));
8062 entry->value = info;
8063 entry->next = *first;
8064 *first = entry;
8065 }
8066
8067 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
8068 {
8069 CpuDefinitionInfoList *cpu_list = NULL;
8070 GSList *list;
8071 int i;
8072
8073 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8074 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
8075 g_slist_free(list);
8076
8077 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8078 const PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8079 ObjectClass *oc;
8080 CpuDefinitionInfoList *entry;
8081 CpuDefinitionInfo *info;
8082
8083 oc = ppc_cpu_class_by_name(alias->model);
8084 if (oc == NULL) {
8085 continue;
8086 }
8087
8088 info = g_malloc0(sizeof(*info));
8089 info->name = g_strdup(alias->alias);
8090
8091 entry = g_malloc0(sizeof(*entry));
8092 entry->value = info;
8093 entry->next = cpu_list;
8094 cpu_list = entry;
8095 }
8096
8097 return cpu_list;
8098 }
8099
8100 /* CPUClass::reset() */
8101 static void ppc_cpu_reset(CPUState *s)
8102 {
8103 PowerPCCPU *cpu = POWERPC_CPU(s);
8104 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8105 CPUPPCState *env = &cpu->env;
8106 target_ulong msr;
8107
8108 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
8109 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
8110 log_cpu_state(env, 0);
8111 }
8112
8113 pcc->parent_reset(s);
8114
8115 msr = (target_ulong)0;
8116 if (0) {
8117 /* XXX: find a suitable condition to enable the hypervisor mode */
8118 msr |= (target_ulong)MSR_HVB;
8119 }
8120 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
8121 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
8122 msr |= (target_ulong)1 << MSR_EP;
8123 #if defined(DO_SINGLE_STEP) && 0
8124 /* Single step trace mode */
8125 msr |= (target_ulong)1 << MSR_SE;
8126 msr |= (target_ulong)1 << MSR_BE;
8127 #endif
8128 #if defined(CONFIG_USER_ONLY)
8129 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
8130 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
8131 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
8132 msr |= (target_ulong)1 << MSR_PR;
8133 #else
8134 env->excp_prefix = env->hreset_excp_prefix;
8135 env->nip = env->hreset_vector | env->excp_prefix;
8136 if (env->mmu_model != POWERPC_MMU_REAL) {
8137 ppc_tlb_invalidate_all(env);
8138 }
8139 #endif
8140 env->msr = msr & env->msr_mask;
8141 #if defined(TARGET_PPC64)
8142 if (env->mmu_model & POWERPC_MMU_64) {
8143 env->msr |= (1ULL << MSR_SF);
8144 }
8145 #endif
8146 hreg_compute_hflags(env);
8147 env->reserve_addr = (target_ulong)-1ULL;
8148 /* Be sure no exception or interrupt is pending */
8149 env->pending_interrupts = 0;
8150 env->exception_index = POWERPC_EXCP_NONE;
8151 env->error_code = 0;
8152
8153 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
8154 env->vpa_addr = 0;
8155 env->slb_shadow_addr = 0;
8156 env->slb_shadow_size = 0;
8157 env->dtl_addr = 0;
8158 env->dtl_size = 0;
8159 #endif /* TARGET_PPC64 */
8160
8161 /* Flush all TLBs */
8162 tlb_flush(env, 1);
8163 }
8164
8165 static void ppc_cpu_initfn(Object *obj)
8166 {
8167 CPUState *cs = CPU(obj);
8168 PowerPCCPU *cpu = POWERPC_CPU(obj);
8169 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8170 CPUPPCState *env = &cpu->env;
8171
8172 cs->env_ptr = env;
8173 cpu_exec_init(env);
8174
8175 env->msr_mask = pcc->msr_mask;
8176 env->mmu_model = pcc->mmu_model;
8177 env->excp_model = pcc->excp_model;
8178 env->bus_model = pcc->bus_model;
8179 env->insns_flags = pcc->insns_flags;
8180 env->insns_flags2 = pcc->insns_flags2;
8181 env->flags = pcc->flags;
8182 env->bfd_mach = pcc->bfd_mach;
8183 env->check_pow = pcc->check_pow;
8184
8185 #if defined(TARGET_PPC64)
8186 if (pcc->sps) {
8187 env->sps = *pcc->sps;
8188 } else if (env->mmu_model & POWERPC_MMU_64) {
8189 /* Use default sets of page sizes */
8190 static const struct ppc_segment_page_sizes defsps = {
8191 .sps = {
8192 { .page_shift = 12, /* 4K */
8193 .slb_enc = 0,
8194 .enc = { { .page_shift = 12, .pte_enc = 0 } }
8195 },
8196 { .page_shift = 24, /* 16M */
8197 .slb_enc = 0x100,
8198 .enc = { { .page_shift = 24, .pte_enc = 0 } }
8199 },
8200 },
8201 };
8202 env->sps = defsps;
8203 }
8204 #endif /* defined(TARGET_PPC64) */
8205
8206 if (tcg_enabled()) {
8207 ppc_translate_init();
8208 }
8209 }
8210
8211 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
8212 {
8213 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8214 CPUClass *cc = CPU_CLASS(oc);
8215 DeviceClass *dc = DEVICE_CLASS(oc);
8216
8217 pcc->parent_realize = dc->realize;
8218 dc->realize = ppc_cpu_realizefn;
8219
8220 pcc->parent_reset = cc->reset;
8221 cc->reset = ppc_cpu_reset;
8222
8223 cc->class_by_name = ppc_cpu_class_by_name;
8224 cc->do_interrupt = ppc_cpu_do_interrupt;
8225 }
8226
8227 static const TypeInfo ppc_cpu_type_info = {
8228 .name = TYPE_POWERPC_CPU,
8229 .parent = TYPE_CPU,
8230 .instance_size = sizeof(PowerPCCPU),
8231 .instance_init = ppc_cpu_initfn,
8232 .abstract = true,
8233 .class_size = sizeof(PowerPCCPUClass),
8234 .class_init = ppc_cpu_class_init,
8235 };
8236
8237 static void ppc_cpu_register_types(void)
8238 {
8239 type_register_static(&ppc_cpu_type_info);
8240 }
8241
8242 type_init(ppc_cpu_register_types)
Qemu copy for testing