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[qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
19 */
20
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26 #include "dis-asm.h"
27 #include "host-utils.h"
28 #include "gdbstub.h"
29
30 //#define PPC_DUMP_CPU
31 //#define PPC_DEBUG_SPR
32 //#define PPC_DUMP_SPR_ACCESSES
33 #if defined(CONFIG_USER_ONLY)
34 #define TODO_USER_ONLY 1
35 #endif
36
37 struct ppc_def_t {
38 const char *name;
39 uint32_t pvr;
40 uint32_t svr;
41 uint64_t insns_flags;
42 uint64_t msr_mask;
43 powerpc_mmu_t mmu_model;
44 powerpc_excp_t excp_model;
45 powerpc_input_t bus_model;
46 uint32_t flags;
47 int bfd_mach;
48 void (*init_proc)(CPUPPCState *env);
49 int (*check_pow)(CPUPPCState *env);
50 };
51
52 /* For user-mode emulation, we don't emulate any IRQ controller */
53 #if defined(CONFIG_USER_ONLY)
54 #define PPC_IRQ_INIT_FN(name) \
55 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
56 { \
57 }
58 #else
59 #define PPC_IRQ_INIT_FN(name) \
60 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
61 #endif
62
63 PPC_IRQ_INIT_FN(40x);
64 PPC_IRQ_INIT_FN(6xx);
65 PPC_IRQ_INIT_FN(970);
66 PPC_IRQ_INIT_FN(e500);
67
68 /* Generic callbacks:
69 * do nothing but store/retrieve spr value
70 */
71 static void spr_read_generic (void *opaque, int gprn, int sprn)
72 {
73 gen_load_spr(cpu_gpr[gprn], sprn);
74 #ifdef PPC_DUMP_SPR_ACCESSES
75 {
76 TCGv t0 = tcg_const_i32(sprn);
77 gen_helper_load_dump_spr(t0);
78 tcg_temp_free_i32(t0);
79 }
80 #endif
81 }
82
83 static void spr_write_generic (void *opaque, int sprn, int gprn)
84 {
85 gen_store_spr(sprn, cpu_gpr[gprn]);
86 #ifdef PPC_DUMP_SPR_ACCESSES
87 {
88 TCGv t0 = tcg_const_i32(sprn);
89 gen_helper_store_dump_spr(t0);
90 tcg_temp_free_i32(t0);
91 }
92 #endif
93 }
94
95 #if !defined(CONFIG_USER_ONLY)
96 static void spr_write_clear (void *opaque, int sprn, int gprn)
97 {
98 TCGv t0 = tcg_temp_new();
99 TCGv t1 = tcg_temp_new();
100 gen_load_spr(t0, sprn);
101 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
102 tcg_gen_and_tl(t0, t0, t1);
103 gen_store_spr(sprn, t0);
104 tcg_temp_free(t0);
105 tcg_temp_free(t1);
106 }
107 #endif
108
109 /* SPR common to all PowerPC */
110 /* XER */
111 static void spr_read_xer (void *opaque, int gprn, int sprn)
112 {
113 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
114 }
115
116 static void spr_write_xer (void *opaque, int sprn, int gprn)
117 {
118 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
119 }
120
121 /* LR */
122 static void spr_read_lr (void *opaque, int gprn, int sprn)
123 {
124 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
125 }
126
127 static void spr_write_lr (void *opaque, int sprn, int gprn)
128 {
129 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
130 }
131
132 /* CTR */
133 static void spr_read_ctr (void *opaque, int gprn, int sprn)
134 {
135 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
136 }
137
138 static void spr_write_ctr (void *opaque, int sprn, int gprn)
139 {
140 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
141 }
142
143 /* User read access to SPR */
144 /* USPRx */
145 /* UMMCRx */
146 /* UPMCx */
147 /* USIA */
148 /* UDECR */
149 static void spr_read_ureg (void *opaque, int gprn, int sprn)
150 {
151 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
152 }
153
154 /* SPR common to all non-embedded PowerPC */
155 /* DECR */
156 #if !defined(CONFIG_USER_ONLY)
157 static void spr_read_decr (void *opaque, int gprn, int sprn)
158 {
159 gen_helper_load_decr(cpu_gpr[gprn]);
160 }
161
162 static void spr_write_decr (void *opaque, int sprn, int gprn)
163 {
164 gen_helper_store_decr(cpu_gpr[gprn]);
165 }
166 #endif
167
168 /* SPR common to all non-embedded PowerPC, except 601 */
169 /* Time base */
170 static void spr_read_tbl (void *opaque, int gprn, int sprn)
171 {
172 gen_helper_load_tbl(cpu_gpr[gprn]);
173 }
174
175 static void spr_read_tbu (void *opaque, int gprn, int sprn)
176 {
177 gen_helper_load_tbu(cpu_gpr[gprn]);
178 }
179
180 __attribute__ (( unused ))
181 static void spr_read_atbl (void *opaque, int gprn, int sprn)
182 {
183 gen_helper_load_atbl(cpu_gpr[gprn]);
184 }
185
186 __attribute__ (( unused ))
187 static void spr_read_atbu (void *opaque, int gprn, int sprn)
188 {
189 gen_helper_load_atbu(cpu_gpr[gprn]);
190 }
191
192 #if !defined(CONFIG_USER_ONLY)
193 static void spr_write_tbl (void *opaque, int sprn, int gprn)
194 {
195 gen_helper_store_tbl(cpu_gpr[gprn]);
196 }
197
198 static void spr_write_tbu (void *opaque, int sprn, int gprn)
199 {
200 gen_helper_store_tbu(cpu_gpr[gprn]);
201 }
202
203 __attribute__ (( unused ))
204 static void spr_write_atbl (void *opaque, int sprn, int gprn)
205 {
206 gen_helper_store_atbl(cpu_gpr[gprn]);
207 }
208
209 __attribute__ (( unused ))
210 static void spr_write_atbu (void *opaque, int sprn, int gprn)
211 {
212 gen_helper_store_atbu(cpu_gpr[gprn]);
213 }
214 #endif
215
216 #if !defined(CONFIG_USER_ONLY)
217 /* IBAT0U...IBAT0U */
218 /* IBAT0L...IBAT7L */
219 static void spr_read_ibat (void *opaque, int gprn, int sprn)
220 {
221 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
222 }
223
224 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
225 {
226 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
227 }
228
229 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
230 {
231 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
232 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
233 tcg_temp_free_i32(t0);
234 }
235
236 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
237 {
238 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4U) / 2);
239 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
240 tcg_temp_free_i32(t0);
241 }
242
243 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
244 {
245 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
246 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
247 tcg_temp_free_i32(t0);
248 }
249
250 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
251 {
252 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4L) / 2);
253 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
254 tcg_temp_free_i32(t0);
255 }
256
257 /* DBAT0U...DBAT7U */
258 /* DBAT0L...DBAT7L */
259 static void spr_read_dbat (void *opaque, int gprn, int sprn)
260 {
261 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
262 }
263
264 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
265 {
266 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
267 }
268
269 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
270 {
271 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
272 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
273 tcg_temp_free_i32(t0);
274 }
275
276 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
277 {
278 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
279 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
280 tcg_temp_free_i32(t0);
281 }
282
283 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
284 {
285 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
286 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
287 tcg_temp_free_i32(t0);
288 }
289
290 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
291 {
292 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
293 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
294 tcg_temp_free_i32(t0);
295 }
296
297 /* SDR1 */
298 static void spr_read_sdr1 (void *opaque, int gprn, int sprn)
299 {
300 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, sdr1));
301 }
302
303 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
304 {
305 gen_helper_store_sdr1(cpu_gpr[gprn]);
306 }
307
308 /* 64 bits PowerPC specific SPRs */
309 /* ASR */
310 #if defined(TARGET_PPC64)
311 static void spr_read_hior (void *opaque, int gprn, int sprn)
312 {
313 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
314 }
315
316 static void spr_write_hior (void *opaque, int sprn, int gprn)
317 {
318 TCGv t0 = tcg_temp_new();
319 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
320 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
321 tcg_temp_free(t0);
322 }
323
324 static void spr_read_asr (void *opaque, int gprn, int sprn)
325 {
326 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
327 }
328
329 static void spr_write_asr (void *opaque, int sprn, int gprn)
330 {
331 gen_helper_store_asr(cpu_gpr[gprn]);
332 }
333 #endif
334 #endif
335
336 /* PowerPC 601 specific registers */
337 /* RTC */
338 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
339 {
340 gen_helper_load_601_rtcl(cpu_gpr[gprn]);
341 }
342
343 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
344 {
345 gen_helper_load_601_rtcu(cpu_gpr[gprn]);
346 }
347
348 #if !defined(CONFIG_USER_ONLY)
349 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
350 {
351 gen_helper_store_601_rtcu(cpu_gpr[gprn]);
352 }
353
354 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
355 {
356 gen_helper_store_601_rtcl(cpu_gpr[gprn]);
357 }
358
359 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
360 {
361 DisasContext *ctx = opaque;
362
363 gen_helper_store_hid0_601(cpu_gpr[gprn]);
364 /* Must stop the translation as endianness may have changed */
365 gen_stop_exception(ctx);
366 }
367 #endif
368
369 /* Unified bats */
370 #if !defined(CONFIG_USER_ONLY)
371 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
372 {
373 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
374 }
375
376 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
377 {
378 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
379 gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
380 tcg_temp_free_i32(t0);
381 }
382
383 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
384 {
385 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
386 gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
387 tcg_temp_free_i32(t0);
388 }
389 #endif
390
391 /* PowerPC 40x specific registers */
392 #if !defined(CONFIG_USER_ONLY)
393 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
394 {
395 gen_helper_load_40x_pit(cpu_gpr[gprn]);
396 }
397
398 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
399 {
400 gen_helper_store_40x_pit(cpu_gpr[gprn]);
401 }
402
403 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
404 {
405 DisasContext *ctx = opaque;
406
407 gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
408 /* We must stop translation as we may have rebooted */
409 gen_stop_exception(ctx);
410 }
411
412 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
413 {
414 gen_helper_store_40x_sler(cpu_gpr[gprn]);
415 }
416
417 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
418 {
419 gen_helper_store_booke_tcr(cpu_gpr[gprn]);
420 }
421
422 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
423 {
424 gen_helper_store_booke_tsr(cpu_gpr[gprn]);
425 }
426 #endif
427
428 /* PowerPC 403 specific registers */
429 /* PBL1 / PBU1 / PBL2 / PBU2 */
430 #if !defined(CONFIG_USER_ONLY)
431 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
432 {
433 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
434 }
435
436 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
437 {
438 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
439 gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
440 tcg_temp_free_i32(t0);
441 }
442
443 static void spr_write_pir (void *opaque, int sprn, int gprn)
444 {
445 TCGv t0 = tcg_temp_new();
446 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
447 gen_store_spr(SPR_PIR, t0);
448 tcg_temp_free(t0);
449 }
450 #endif
451
452 #if !defined(CONFIG_USER_ONLY)
453 /* Callback used to write the exception vector base */
454 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
455 {
456 TCGv t0 = tcg_temp_new();
457 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
458 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
459 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
460 gen_store_spr(sprn, t0);
461 }
462
463 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
464 {
465 DisasContext *ctx = opaque;
466
467 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
468 TCGv t0 = tcg_temp_new();
469 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
470 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
471 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
472 gen_store_spr(sprn, t0);
473 tcg_temp_free(t0);
474 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
475 TCGv t0 = tcg_temp_new();
476 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
477 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
478 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
479 gen_store_spr(sprn, t0);
480 tcg_temp_free(t0);
481 } else {
482 printf("Trying to write an unknown exception vector %d %03x\n",
483 sprn, sprn);
484 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
485 }
486 }
487 #endif
488
489 static inline void vscr_init (CPUPPCState *env, uint32_t val)
490 {
491 env->vscr = val;
492 /* Altivec always uses round-to-nearest */
493 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
494 set_flush_to_zero(vscr_nj, &env->vec_status);
495 }
496
497 #if defined(CONFIG_USER_ONLY)
498 #define spr_register(env, num, name, uea_read, uea_write, \
499 oea_read, oea_write, initial_value) \
500 do { \
501 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
502 } while (0)
503 static inline void _spr_register (CPUPPCState *env, int num,
504 const char *name,
505 void (*uea_read)(void *opaque, int gprn, int sprn),
506 void (*uea_write)(void *opaque, int sprn, int gprn),
507 target_ulong initial_value)
508 #else
509 static inline void spr_register (CPUPPCState *env, int num,
510 const char *name,
511 void (*uea_read)(void *opaque, int gprn, int sprn),
512 void (*uea_write)(void *opaque, int sprn, int gprn),
513 void (*oea_read)(void *opaque, int gprn, int sprn),
514 void (*oea_write)(void *opaque, int sprn, int gprn),
515 target_ulong initial_value)
516 #endif
517 {
518 ppc_spr_t *spr;
519
520 spr = &env->spr_cb[num];
521 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
522 #if !defined(CONFIG_USER_ONLY)
523 spr->oea_read != NULL || spr->oea_write != NULL ||
524 #endif
525 spr->uea_read != NULL || spr->uea_write != NULL) {
526 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
527 exit(1);
528 }
529 #if defined(PPC_DEBUG_SPR)
530 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
531 initial_value);
532 #endif
533 spr->name = name;
534 spr->uea_read = uea_read;
535 spr->uea_write = uea_write;
536 #if !defined(CONFIG_USER_ONLY)
537 spr->oea_read = oea_read;
538 spr->oea_write = oea_write;
539 #endif
540 env->spr[num] = initial_value;
541 }
542
543 /* Generic PowerPC SPRs */
544 static void gen_spr_generic (CPUPPCState *env)
545 {
546 /* Integer processing */
547 spr_register(env, SPR_XER, "XER",
548 &spr_read_xer, &spr_write_xer,
549 &spr_read_xer, &spr_write_xer,
550 0x00000000);
551 /* Branch contol */
552 spr_register(env, SPR_LR, "LR",
553 &spr_read_lr, &spr_write_lr,
554 &spr_read_lr, &spr_write_lr,
555 0x00000000);
556 spr_register(env, SPR_CTR, "CTR",
557 &spr_read_ctr, &spr_write_ctr,
558 &spr_read_ctr, &spr_write_ctr,
559 0x00000000);
560 /* Interrupt processing */
561 spr_register(env, SPR_SRR0, "SRR0",
562 SPR_NOACCESS, SPR_NOACCESS,
563 &spr_read_generic, &spr_write_generic,
564 0x00000000);
565 spr_register(env, SPR_SRR1, "SRR1",
566 SPR_NOACCESS, SPR_NOACCESS,
567 &spr_read_generic, &spr_write_generic,
568 0x00000000);
569 /* Processor control */
570 spr_register(env, SPR_SPRG0, "SPRG0",
571 SPR_NOACCESS, SPR_NOACCESS,
572 &spr_read_generic, &spr_write_generic,
573 0x00000000);
574 spr_register(env, SPR_SPRG1, "SPRG1",
575 SPR_NOACCESS, SPR_NOACCESS,
576 &spr_read_generic, &spr_write_generic,
577 0x00000000);
578 spr_register(env, SPR_SPRG2, "SPRG2",
579 SPR_NOACCESS, SPR_NOACCESS,
580 &spr_read_generic, &spr_write_generic,
581 0x00000000);
582 spr_register(env, SPR_SPRG3, "SPRG3",
583 SPR_NOACCESS, SPR_NOACCESS,
584 &spr_read_generic, &spr_write_generic,
585 0x00000000);
586 }
587
588 /* SPR common to all non-embedded PowerPC, including 601 */
589 static void gen_spr_ne_601 (CPUPPCState *env)
590 {
591 /* Exception processing */
592 spr_register(env, SPR_DSISR, "DSISR",
593 SPR_NOACCESS, SPR_NOACCESS,
594 &spr_read_generic, &spr_write_generic,
595 0x00000000);
596 spr_register(env, SPR_DAR, "DAR",
597 SPR_NOACCESS, SPR_NOACCESS,
598 &spr_read_generic, &spr_write_generic,
599 0x00000000);
600 /* Timer */
601 spr_register(env, SPR_DECR, "DECR",
602 SPR_NOACCESS, SPR_NOACCESS,
603 &spr_read_decr, &spr_write_decr,
604 0x00000000);
605 /* Memory management */
606 spr_register(env, SPR_SDR1, "SDR1",
607 SPR_NOACCESS, SPR_NOACCESS,
608 &spr_read_sdr1, &spr_write_sdr1,
609 0x00000000);
610 }
611
612 /* BATs 0-3 */
613 static void gen_low_BATs (CPUPPCState *env)
614 {
615 #if !defined(CONFIG_USER_ONLY)
616 spr_register(env, SPR_IBAT0U, "IBAT0U",
617 SPR_NOACCESS, SPR_NOACCESS,
618 &spr_read_ibat, &spr_write_ibatu,
619 0x00000000);
620 spr_register(env, SPR_IBAT0L, "IBAT0L",
621 SPR_NOACCESS, SPR_NOACCESS,
622 &spr_read_ibat, &spr_write_ibatl,
623 0x00000000);
624 spr_register(env, SPR_IBAT1U, "IBAT1U",
625 SPR_NOACCESS, SPR_NOACCESS,
626 &spr_read_ibat, &spr_write_ibatu,
627 0x00000000);
628 spr_register(env, SPR_IBAT1L, "IBAT1L",
629 SPR_NOACCESS, SPR_NOACCESS,
630 &spr_read_ibat, &spr_write_ibatl,
631 0x00000000);
632 spr_register(env, SPR_IBAT2U, "IBAT2U",
633 SPR_NOACCESS, SPR_NOACCESS,
634 &spr_read_ibat, &spr_write_ibatu,
635 0x00000000);
636 spr_register(env, SPR_IBAT2L, "IBAT2L",
637 SPR_NOACCESS, SPR_NOACCESS,
638 &spr_read_ibat, &spr_write_ibatl,
639 0x00000000);
640 spr_register(env, SPR_IBAT3U, "IBAT3U",
641 SPR_NOACCESS, SPR_NOACCESS,
642 &spr_read_ibat, &spr_write_ibatu,
643 0x00000000);
644 spr_register(env, SPR_IBAT3L, "IBAT3L",
645 SPR_NOACCESS, SPR_NOACCESS,
646 &spr_read_ibat, &spr_write_ibatl,
647 0x00000000);
648 spr_register(env, SPR_DBAT0U, "DBAT0U",
649 SPR_NOACCESS, SPR_NOACCESS,
650 &spr_read_dbat, &spr_write_dbatu,
651 0x00000000);
652 spr_register(env, SPR_DBAT0L, "DBAT0L",
653 SPR_NOACCESS, SPR_NOACCESS,
654 &spr_read_dbat, &spr_write_dbatl,
655 0x00000000);
656 spr_register(env, SPR_DBAT1U, "DBAT1U",
657 SPR_NOACCESS, SPR_NOACCESS,
658 &spr_read_dbat, &spr_write_dbatu,
659 0x00000000);
660 spr_register(env, SPR_DBAT1L, "DBAT1L",
661 SPR_NOACCESS, SPR_NOACCESS,
662 &spr_read_dbat, &spr_write_dbatl,
663 0x00000000);
664 spr_register(env, SPR_DBAT2U, "DBAT2U",
665 SPR_NOACCESS, SPR_NOACCESS,
666 &spr_read_dbat, &spr_write_dbatu,
667 0x00000000);
668 spr_register(env, SPR_DBAT2L, "DBAT2L",
669 SPR_NOACCESS, SPR_NOACCESS,
670 &spr_read_dbat, &spr_write_dbatl,
671 0x00000000);
672 spr_register(env, SPR_DBAT3U, "DBAT3U",
673 SPR_NOACCESS, SPR_NOACCESS,
674 &spr_read_dbat, &spr_write_dbatu,
675 0x00000000);
676 spr_register(env, SPR_DBAT3L, "DBAT3L",
677 SPR_NOACCESS, SPR_NOACCESS,
678 &spr_read_dbat, &spr_write_dbatl,
679 0x00000000);
680 env->nb_BATs += 4;
681 #endif
682 }
683
684 /* BATs 4-7 */
685 static void gen_high_BATs (CPUPPCState *env)
686 {
687 #if !defined(CONFIG_USER_ONLY)
688 spr_register(env, SPR_IBAT4U, "IBAT4U",
689 SPR_NOACCESS, SPR_NOACCESS,
690 &spr_read_ibat_h, &spr_write_ibatu_h,
691 0x00000000);
692 spr_register(env, SPR_IBAT4L, "IBAT4L",
693 SPR_NOACCESS, SPR_NOACCESS,
694 &spr_read_ibat_h, &spr_write_ibatl_h,
695 0x00000000);
696 spr_register(env, SPR_IBAT5U, "IBAT5U",
697 SPR_NOACCESS, SPR_NOACCESS,
698 &spr_read_ibat_h, &spr_write_ibatu_h,
699 0x00000000);
700 spr_register(env, SPR_IBAT5L, "IBAT5L",
701 SPR_NOACCESS, SPR_NOACCESS,
702 &spr_read_ibat_h, &spr_write_ibatl_h,
703 0x00000000);
704 spr_register(env, SPR_IBAT6U, "IBAT6U",
705 SPR_NOACCESS, SPR_NOACCESS,
706 &spr_read_ibat_h, &spr_write_ibatu_h,
707 0x00000000);
708 spr_register(env, SPR_IBAT6L, "IBAT6L",
709 SPR_NOACCESS, SPR_NOACCESS,
710 &spr_read_ibat_h, &spr_write_ibatl_h,
711 0x00000000);
712 spr_register(env, SPR_IBAT7U, "IBAT7U",
713 SPR_NOACCESS, SPR_NOACCESS,
714 &spr_read_ibat_h, &spr_write_ibatu_h,
715 0x00000000);
716 spr_register(env, SPR_IBAT7L, "IBAT7L",
717 SPR_NOACCESS, SPR_NOACCESS,
718 &spr_read_ibat_h, &spr_write_ibatl_h,
719 0x00000000);
720 spr_register(env, SPR_DBAT4U, "DBAT4U",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_dbat_h, &spr_write_dbatu_h,
723 0x00000000);
724 spr_register(env, SPR_DBAT4L, "DBAT4L",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_dbat_h, &spr_write_dbatl_h,
727 0x00000000);
728 spr_register(env, SPR_DBAT5U, "DBAT5U",
729 SPR_NOACCESS, SPR_NOACCESS,
730 &spr_read_dbat_h, &spr_write_dbatu_h,
731 0x00000000);
732 spr_register(env, SPR_DBAT5L, "DBAT5L",
733 SPR_NOACCESS, SPR_NOACCESS,
734 &spr_read_dbat_h, &spr_write_dbatl_h,
735 0x00000000);
736 spr_register(env, SPR_DBAT6U, "DBAT6U",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_dbat_h, &spr_write_dbatu_h,
739 0x00000000);
740 spr_register(env, SPR_DBAT6L, "DBAT6L",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_dbat_h, &spr_write_dbatl_h,
743 0x00000000);
744 spr_register(env, SPR_DBAT7U, "DBAT7U",
745 SPR_NOACCESS, SPR_NOACCESS,
746 &spr_read_dbat_h, &spr_write_dbatu_h,
747 0x00000000);
748 spr_register(env, SPR_DBAT7L, "DBAT7L",
749 SPR_NOACCESS, SPR_NOACCESS,
750 &spr_read_dbat_h, &spr_write_dbatl_h,
751 0x00000000);
752 env->nb_BATs += 4;
753 #endif
754 }
755
756 /* Generic PowerPC time base */
757 static void gen_tbl (CPUPPCState *env)
758 {
759 spr_register(env, SPR_VTBL, "TBL",
760 &spr_read_tbl, SPR_NOACCESS,
761 &spr_read_tbl, SPR_NOACCESS,
762 0x00000000);
763 spr_register(env, SPR_TBL, "TBL",
764 SPR_NOACCESS, SPR_NOACCESS,
765 SPR_NOACCESS, &spr_write_tbl,
766 0x00000000);
767 spr_register(env, SPR_VTBU, "TBU",
768 &spr_read_tbu, SPR_NOACCESS,
769 &spr_read_tbu, SPR_NOACCESS,
770 0x00000000);
771 spr_register(env, SPR_TBU, "TBU",
772 SPR_NOACCESS, SPR_NOACCESS,
773 SPR_NOACCESS, &spr_write_tbu,
774 0x00000000);
775 }
776
777 /* Softare table search registers */
778 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
779 {
780 #if !defined(CONFIG_USER_ONLY)
781 env->nb_tlb = nb_tlbs;
782 env->nb_ways = nb_ways;
783 env->id_tlbs = 1;
784 spr_register(env, SPR_DMISS, "DMISS",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_generic, SPR_NOACCESS,
787 0x00000000);
788 spr_register(env, SPR_DCMP, "DCMP",
789 SPR_NOACCESS, SPR_NOACCESS,
790 &spr_read_generic, SPR_NOACCESS,
791 0x00000000);
792 spr_register(env, SPR_HASH1, "HASH1",
793 SPR_NOACCESS, SPR_NOACCESS,
794 &spr_read_generic, SPR_NOACCESS,
795 0x00000000);
796 spr_register(env, SPR_HASH2, "HASH2",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_generic, SPR_NOACCESS,
799 0x00000000);
800 spr_register(env, SPR_IMISS, "IMISS",
801 SPR_NOACCESS, SPR_NOACCESS,
802 &spr_read_generic, SPR_NOACCESS,
803 0x00000000);
804 spr_register(env, SPR_ICMP, "ICMP",
805 SPR_NOACCESS, SPR_NOACCESS,
806 &spr_read_generic, SPR_NOACCESS,
807 0x00000000);
808 spr_register(env, SPR_RPA, "RPA",
809 SPR_NOACCESS, SPR_NOACCESS,
810 &spr_read_generic, &spr_write_generic,
811 0x00000000);
812 #endif
813 }
814
815 /* SPR common to MPC755 and G2 */
816 static void gen_spr_G2_755 (CPUPPCState *env)
817 {
818 /* SGPRs */
819 spr_register(env, SPR_SPRG4, "SPRG4",
820 SPR_NOACCESS, SPR_NOACCESS,
821 &spr_read_generic, &spr_write_generic,
822 0x00000000);
823 spr_register(env, SPR_SPRG5, "SPRG5",
824 SPR_NOACCESS, SPR_NOACCESS,
825 &spr_read_generic, &spr_write_generic,
826 0x00000000);
827 spr_register(env, SPR_SPRG6, "SPRG6",
828 SPR_NOACCESS, SPR_NOACCESS,
829 &spr_read_generic, &spr_write_generic,
830 0x00000000);
831 spr_register(env, SPR_SPRG7, "SPRG7",
832 SPR_NOACCESS, SPR_NOACCESS,
833 &spr_read_generic, &spr_write_generic,
834 0x00000000);
835 }
836
837 /* SPR common to all 7xx PowerPC implementations */
838 static void gen_spr_7xx (CPUPPCState *env)
839 {
840 /* Breakpoints */
841 /* XXX : not implemented */
842 spr_register(env, SPR_DABR, "DABR",
843 SPR_NOACCESS, SPR_NOACCESS,
844 &spr_read_generic, &spr_write_generic,
845 0x00000000);
846 /* XXX : not implemented */
847 spr_register(env, SPR_IABR, "IABR",
848 SPR_NOACCESS, SPR_NOACCESS,
849 &spr_read_generic, &spr_write_generic,
850 0x00000000);
851 /* Cache management */
852 /* XXX : not implemented */
853 spr_register(env, SPR_ICTC, "ICTC",
854 SPR_NOACCESS, SPR_NOACCESS,
855 &spr_read_generic, &spr_write_generic,
856 0x00000000);
857 /* Performance monitors */
858 /* XXX : not implemented */
859 spr_register(env, SPR_MMCR0, "MMCR0",
860 SPR_NOACCESS, SPR_NOACCESS,
861 &spr_read_generic, &spr_write_generic,
862 0x00000000);
863 /* XXX : not implemented */
864 spr_register(env, SPR_MMCR1, "MMCR1",
865 SPR_NOACCESS, SPR_NOACCESS,
866 &spr_read_generic, &spr_write_generic,
867 0x00000000);
868 /* XXX : not implemented */
869 spr_register(env, SPR_PMC1, "PMC1",
870 SPR_NOACCESS, SPR_NOACCESS,
871 &spr_read_generic, &spr_write_generic,
872 0x00000000);
873 /* XXX : not implemented */
874 spr_register(env, SPR_PMC2, "PMC2",
875 SPR_NOACCESS, SPR_NOACCESS,
876 &spr_read_generic, &spr_write_generic,
877 0x00000000);
878 /* XXX : not implemented */
879 spr_register(env, SPR_PMC3, "PMC3",
880 SPR_NOACCESS, SPR_NOACCESS,
881 &spr_read_generic, &spr_write_generic,
882 0x00000000);
883 /* XXX : not implemented */
884 spr_register(env, SPR_PMC4, "PMC4",
885 SPR_NOACCESS, SPR_NOACCESS,
886 &spr_read_generic, &spr_write_generic,
887 0x00000000);
888 /* XXX : not implemented */
889 spr_register(env, SPR_SIAR, "SIAR",
890 SPR_NOACCESS, SPR_NOACCESS,
891 &spr_read_generic, SPR_NOACCESS,
892 0x00000000);
893 /* XXX : not implemented */
894 spr_register(env, SPR_UMMCR0, "UMMCR0",
895 &spr_read_ureg, SPR_NOACCESS,
896 &spr_read_ureg, SPR_NOACCESS,
897 0x00000000);
898 /* XXX : not implemented */
899 spr_register(env, SPR_UMMCR1, "UMMCR1",
900 &spr_read_ureg, SPR_NOACCESS,
901 &spr_read_ureg, SPR_NOACCESS,
902 0x00000000);
903 /* XXX : not implemented */
904 spr_register(env, SPR_UPMC1, "UPMC1",
905 &spr_read_ureg, SPR_NOACCESS,
906 &spr_read_ureg, SPR_NOACCESS,
907 0x00000000);
908 /* XXX : not implemented */
909 spr_register(env, SPR_UPMC2, "UPMC2",
910 &spr_read_ureg, SPR_NOACCESS,
911 &spr_read_ureg, SPR_NOACCESS,
912 0x00000000);
913 /* XXX : not implemented */
914 spr_register(env, SPR_UPMC3, "UPMC3",
915 &spr_read_ureg, SPR_NOACCESS,
916 &spr_read_ureg, SPR_NOACCESS,
917 0x00000000);
918 /* XXX : not implemented */
919 spr_register(env, SPR_UPMC4, "UPMC4",
920 &spr_read_ureg, SPR_NOACCESS,
921 &spr_read_ureg, SPR_NOACCESS,
922 0x00000000);
923 /* XXX : not implemented */
924 spr_register(env, SPR_USIAR, "USIAR",
925 &spr_read_ureg, SPR_NOACCESS,
926 &spr_read_ureg, SPR_NOACCESS,
927 0x00000000);
928 /* External access control */
929 /* XXX : not implemented */
930 spr_register(env, SPR_EAR, "EAR",
931 SPR_NOACCESS, SPR_NOACCESS,
932 &spr_read_generic, &spr_write_generic,
933 0x00000000);
934 }
935
936 static void gen_spr_thrm (CPUPPCState *env)
937 {
938 /* Thermal management */
939 /* XXX : not implemented */
940 spr_register(env, SPR_THRM1, "THRM1",
941 SPR_NOACCESS, SPR_NOACCESS,
942 &spr_read_generic, &spr_write_generic,
943 0x00000000);
944 /* XXX : not implemented */
945 spr_register(env, SPR_THRM2, "THRM2",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_generic, &spr_write_generic,
948 0x00000000);
949 /* XXX : not implemented */
950 spr_register(env, SPR_THRM3, "THRM3",
951 SPR_NOACCESS, SPR_NOACCESS,
952 &spr_read_generic, &spr_write_generic,
953 0x00000000);
954 }
955
956 /* SPR specific to PowerPC 604 implementation */
957 static void gen_spr_604 (CPUPPCState *env)
958 {
959 /* Processor identification */
960 spr_register(env, SPR_PIR, "PIR",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, &spr_write_pir,
963 0x00000000);
964 /* Breakpoints */
965 /* XXX : not implemented */
966 spr_register(env, SPR_IABR, "IABR",
967 SPR_NOACCESS, SPR_NOACCESS,
968 &spr_read_generic, &spr_write_generic,
969 0x00000000);
970 /* XXX : not implemented */
971 spr_register(env, SPR_DABR, "DABR",
972 SPR_NOACCESS, SPR_NOACCESS,
973 &spr_read_generic, &spr_write_generic,
974 0x00000000);
975 /* Performance counters */
976 /* XXX : not implemented */
977 spr_register(env, SPR_MMCR0, "MMCR0",
978 SPR_NOACCESS, SPR_NOACCESS,
979 &spr_read_generic, &spr_write_generic,
980 0x00000000);
981 /* XXX : not implemented */
982 spr_register(env, SPR_PMC1, "PMC1",
983 SPR_NOACCESS, SPR_NOACCESS,
984 &spr_read_generic, &spr_write_generic,
985 0x00000000);
986 /* XXX : not implemented */
987 spr_register(env, SPR_PMC2, "PMC2",
988 SPR_NOACCESS, SPR_NOACCESS,
989 &spr_read_generic, &spr_write_generic,
990 0x00000000);
991 /* XXX : not implemented */
992 spr_register(env, SPR_SIAR, "SIAR",
993 SPR_NOACCESS, SPR_NOACCESS,
994 &spr_read_generic, SPR_NOACCESS,
995 0x00000000);
996 /* XXX : not implemented */
997 spr_register(env, SPR_SDA, "SDA",
998 SPR_NOACCESS, SPR_NOACCESS,
999 &spr_read_generic, SPR_NOACCESS,
1000 0x00000000);
1001 /* External access control */
1002 /* XXX : not implemented */
1003 spr_register(env, SPR_EAR, "EAR",
1004 SPR_NOACCESS, SPR_NOACCESS,
1005 &spr_read_generic, &spr_write_generic,
1006 0x00000000);
1007 }
1008
1009 /* SPR specific to PowerPC 603 implementation */
1010 static void gen_spr_603 (CPUPPCState *env)
1011 {
1012 /* External access control */
1013 /* XXX : not implemented */
1014 spr_register(env, SPR_EAR, "EAR",
1015 SPR_NOACCESS, SPR_NOACCESS,
1016 &spr_read_generic, &spr_write_generic,
1017 0x00000000);
1018 }
1019
1020 /* SPR specific to PowerPC G2 implementation */
1021 static void gen_spr_G2 (CPUPPCState *env)
1022 {
1023 /* Memory base address */
1024 /* MBAR */
1025 /* XXX : not implemented */
1026 spr_register(env, SPR_MBAR, "MBAR",
1027 SPR_NOACCESS, SPR_NOACCESS,
1028 &spr_read_generic, &spr_write_generic,
1029 0x00000000);
1030 /* Exception processing */
1031 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1032 SPR_NOACCESS, SPR_NOACCESS,
1033 &spr_read_generic, &spr_write_generic,
1034 0x00000000);
1035 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1036 SPR_NOACCESS, SPR_NOACCESS,
1037 &spr_read_generic, &spr_write_generic,
1038 0x00000000);
1039 /* Breakpoints */
1040 /* XXX : not implemented */
1041 spr_register(env, SPR_DABR, "DABR",
1042 SPR_NOACCESS, SPR_NOACCESS,
1043 &spr_read_generic, &spr_write_generic,
1044 0x00000000);
1045 /* XXX : not implemented */
1046 spr_register(env, SPR_DABR2, "DABR2",
1047 SPR_NOACCESS, SPR_NOACCESS,
1048 &spr_read_generic, &spr_write_generic,
1049 0x00000000);
1050 /* XXX : not implemented */
1051 spr_register(env, SPR_IABR, "IABR",
1052 SPR_NOACCESS, SPR_NOACCESS,
1053 &spr_read_generic, &spr_write_generic,
1054 0x00000000);
1055 /* XXX : not implemented */
1056 spr_register(env, SPR_IABR2, "IABR2",
1057 SPR_NOACCESS, SPR_NOACCESS,
1058 &spr_read_generic, &spr_write_generic,
1059 0x00000000);
1060 /* XXX : not implemented */
1061 spr_register(env, SPR_IBCR, "IBCR",
1062 SPR_NOACCESS, SPR_NOACCESS,
1063 &spr_read_generic, &spr_write_generic,
1064 0x00000000);
1065 /* XXX : not implemented */
1066 spr_register(env, SPR_DBCR, "DBCR",
1067 SPR_NOACCESS, SPR_NOACCESS,
1068 &spr_read_generic, &spr_write_generic,
1069 0x00000000);
1070 }
1071
1072 /* SPR specific to PowerPC 602 implementation */
1073 static void gen_spr_602 (CPUPPCState *env)
1074 {
1075 /* ESA registers */
1076 /* XXX : not implemented */
1077 spr_register(env, SPR_SER, "SER",
1078 SPR_NOACCESS, SPR_NOACCESS,
1079 &spr_read_generic, &spr_write_generic,
1080 0x00000000);
1081 /* XXX : not implemented */
1082 spr_register(env, SPR_SEBR, "SEBR",
1083 SPR_NOACCESS, SPR_NOACCESS,
1084 &spr_read_generic, &spr_write_generic,
1085 0x00000000);
1086 /* XXX : not implemented */
1087 spr_register(env, SPR_ESASRR, "ESASRR",
1088 SPR_NOACCESS, SPR_NOACCESS,
1089 &spr_read_generic, &spr_write_generic,
1090 0x00000000);
1091 /* Floating point status */
1092 /* XXX : not implemented */
1093 spr_register(env, SPR_SP, "SP",
1094 SPR_NOACCESS, SPR_NOACCESS,
1095 &spr_read_generic, &spr_write_generic,
1096 0x00000000);
1097 /* XXX : not implemented */
1098 spr_register(env, SPR_LT, "LT",
1099 SPR_NOACCESS, SPR_NOACCESS,
1100 &spr_read_generic, &spr_write_generic,
1101 0x00000000);
1102 /* Watchdog timer */
1103 /* XXX : not implemented */
1104 spr_register(env, SPR_TCR, "TCR",
1105 SPR_NOACCESS, SPR_NOACCESS,
1106 &spr_read_generic, &spr_write_generic,
1107 0x00000000);
1108 /* Interrupt base */
1109 spr_register(env, SPR_IBR, "IBR",
1110 SPR_NOACCESS, SPR_NOACCESS,
1111 &spr_read_generic, &spr_write_generic,
1112 0x00000000);
1113 /* XXX : not implemented */
1114 spr_register(env, SPR_IABR, "IABR",
1115 SPR_NOACCESS, SPR_NOACCESS,
1116 &spr_read_generic, &spr_write_generic,
1117 0x00000000);
1118 }
1119
1120 /* SPR specific to PowerPC 601 implementation */
1121 static void gen_spr_601 (CPUPPCState *env)
1122 {
1123 /* Multiplication/division register */
1124 /* MQ */
1125 spr_register(env, SPR_MQ, "MQ",
1126 &spr_read_generic, &spr_write_generic,
1127 &spr_read_generic, &spr_write_generic,
1128 0x00000000);
1129 /* RTC registers */
1130 spr_register(env, SPR_601_RTCU, "RTCU",
1131 SPR_NOACCESS, SPR_NOACCESS,
1132 SPR_NOACCESS, &spr_write_601_rtcu,
1133 0x00000000);
1134 spr_register(env, SPR_601_VRTCU, "RTCU",
1135 &spr_read_601_rtcu, SPR_NOACCESS,
1136 &spr_read_601_rtcu, SPR_NOACCESS,
1137 0x00000000);
1138 spr_register(env, SPR_601_RTCL, "RTCL",
1139 SPR_NOACCESS, SPR_NOACCESS,
1140 SPR_NOACCESS, &spr_write_601_rtcl,
1141 0x00000000);
1142 spr_register(env, SPR_601_VRTCL, "RTCL",
1143 &spr_read_601_rtcl, SPR_NOACCESS,
1144 &spr_read_601_rtcl, SPR_NOACCESS,
1145 0x00000000);
1146 /* Timer */
1147 #if 0 /* ? */
1148 spr_register(env, SPR_601_UDECR, "UDECR",
1149 &spr_read_decr, SPR_NOACCESS,
1150 &spr_read_decr, SPR_NOACCESS,
1151 0x00000000);
1152 #endif
1153 /* External access control */
1154 /* XXX : not implemented */
1155 spr_register(env, SPR_EAR, "EAR",
1156 SPR_NOACCESS, SPR_NOACCESS,
1157 &spr_read_generic, &spr_write_generic,
1158 0x00000000);
1159 /* Memory management */
1160 #if !defined(CONFIG_USER_ONLY)
1161 spr_register(env, SPR_IBAT0U, "IBAT0U",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_601_ubat, &spr_write_601_ubatu,
1164 0x00000000);
1165 spr_register(env, SPR_IBAT0L, "IBAT0L",
1166 SPR_NOACCESS, SPR_NOACCESS,
1167 &spr_read_601_ubat, &spr_write_601_ubatl,
1168 0x00000000);
1169 spr_register(env, SPR_IBAT1U, "IBAT1U",
1170 SPR_NOACCESS, SPR_NOACCESS,
1171 &spr_read_601_ubat, &spr_write_601_ubatu,
1172 0x00000000);
1173 spr_register(env, SPR_IBAT1L, "IBAT1L",
1174 SPR_NOACCESS, SPR_NOACCESS,
1175 &spr_read_601_ubat, &spr_write_601_ubatl,
1176 0x00000000);
1177 spr_register(env, SPR_IBAT2U, "IBAT2U",
1178 SPR_NOACCESS, SPR_NOACCESS,
1179 &spr_read_601_ubat, &spr_write_601_ubatu,
1180 0x00000000);
1181 spr_register(env, SPR_IBAT2L, "IBAT2L",
1182 SPR_NOACCESS, SPR_NOACCESS,
1183 &spr_read_601_ubat, &spr_write_601_ubatl,
1184 0x00000000);
1185 spr_register(env, SPR_IBAT3U, "IBAT3U",
1186 SPR_NOACCESS, SPR_NOACCESS,
1187 &spr_read_601_ubat, &spr_write_601_ubatu,
1188 0x00000000);
1189 spr_register(env, SPR_IBAT3L, "IBAT3L",
1190 SPR_NOACCESS, SPR_NOACCESS,
1191 &spr_read_601_ubat, &spr_write_601_ubatl,
1192 0x00000000);
1193 env->nb_BATs = 4;
1194 #endif
1195 }
1196
1197 static void gen_spr_74xx (CPUPPCState *env)
1198 {
1199 /* Processor identification */
1200 spr_register(env, SPR_PIR, "PIR",
1201 SPR_NOACCESS, SPR_NOACCESS,
1202 &spr_read_generic, &spr_write_pir,
1203 0x00000000);
1204 /* XXX : not implemented */
1205 spr_register(env, SPR_MMCR2, "MMCR2",
1206 SPR_NOACCESS, SPR_NOACCESS,
1207 &spr_read_generic, &spr_write_generic,
1208 0x00000000);
1209 /* XXX : not implemented */
1210 spr_register(env, SPR_UMMCR2, "UMMCR2",
1211 &spr_read_ureg, SPR_NOACCESS,
1212 &spr_read_ureg, SPR_NOACCESS,
1213 0x00000000);
1214 /* XXX: not implemented */
1215 spr_register(env, SPR_BAMR, "BAMR",
1216 SPR_NOACCESS, SPR_NOACCESS,
1217 &spr_read_generic, &spr_write_generic,
1218 0x00000000);
1219 /* XXX : not implemented */
1220 spr_register(env, SPR_MSSCR0, "MSSCR0",
1221 SPR_NOACCESS, SPR_NOACCESS,
1222 &spr_read_generic, &spr_write_generic,
1223 0x00000000);
1224 /* Hardware implementation registers */
1225 /* XXX : not implemented */
1226 spr_register(env, SPR_HID0, "HID0",
1227 SPR_NOACCESS, SPR_NOACCESS,
1228 &spr_read_generic, &spr_write_generic,
1229 0x00000000);
1230 /* XXX : not implemented */
1231 spr_register(env, SPR_HID1, "HID1",
1232 SPR_NOACCESS, SPR_NOACCESS,
1233 &spr_read_generic, &spr_write_generic,
1234 0x00000000);
1235 /* Altivec */
1236 spr_register(env, SPR_VRSAVE, "VRSAVE",
1237 &spr_read_generic, &spr_write_generic,
1238 &spr_read_generic, &spr_write_generic,
1239 0x00000000);
1240 /* XXX : not implemented */
1241 spr_register(env, SPR_L2CR, "L2CR",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_generic, &spr_write_generic,
1244 0x00000000);
1245 /* Not strictly an SPR */
1246 vscr_init(env, 0x00010000);
1247 }
1248
1249 static void gen_l3_ctrl (CPUPPCState *env)
1250 {
1251 /* L3CR */
1252 /* XXX : not implemented */
1253 spr_register(env, SPR_L3CR, "L3CR",
1254 SPR_NOACCESS, SPR_NOACCESS,
1255 &spr_read_generic, &spr_write_generic,
1256 0x00000000);
1257 /* L3ITCR0 */
1258 /* XXX : not implemented */
1259 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1260 SPR_NOACCESS, SPR_NOACCESS,
1261 &spr_read_generic, &spr_write_generic,
1262 0x00000000);
1263 /* L3PM */
1264 /* XXX : not implemented */
1265 spr_register(env, SPR_L3PM, "L3PM",
1266 SPR_NOACCESS, SPR_NOACCESS,
1267 &spr_read_generic, &spr_write_generic,
1268 0x00000000);
1269 }
1270
1271 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1272 {
1273 #if !defined(CONFIG_USER_ONLY)
1274 env->nb_tlb = nb_tlbs;
1275 env->nb_ways = nb_ways;
1276 env->id_tlbs = 1;
1277 /* XXX : not implemented */
1278 spr_register(env, SPR_PTEHI, "PTEHI",
1279 SPR_NOACCESS, SPR_NOACCESS,
1280 &spr_read_generic, &spr_write_generic,
1281 0x00000000);
1282 /* XXX : not implemented */
1283 spr_register(env, SPR_PTELO, "PTELO",
1284 SPR_NOACCESS, SPR_NOACCESS,
1285 &spr_read_generic, &spr_write_generic,
1286 0x00000000);
1287 /* XXX : not implemented */
1288 spr_register(env, SPR_TLBMISS, "TLBMISS",
1289 SPR_NOACCESS, SPR_NOACCESS,
1290 &spr_read_generic, &spr_write_generic,
1291 0x00000000);
1292 #endif
1293 }
1294
1295 static void gen_spr_usprgh (CPUPPCState *env)
1296 {
1297 spr_register(env, SPR_USPRG4, "USPRG4",
1298 &spr_read_ureg, SPR_NOACCESS,
1299 &spr_read_ureg, SPR_NOACCESS,
1300 0x00000000);
1301 spr_register(env, SPR_USPRG5, "USPRG5",
1302 &spr_read_ureg, SPR_NOACCESS,
1303 &spr_read_ureg, SPR_NOACCESS,
1304 0x00000000);
1305 spr_register(env, SPR_USPRG6, "USPRG6",
1306 &spr_read_ureg, SPR_NOACCESS,
1307 &spr_read_ureg, SPR_NOACCESS,
1308 0x00000000);
1309 spr_register(env, SPR_USPRG7, "USPRG7",
1310 &spr_read_ureg, SPR_NOACCESS,
1311 &spr_read_ureg, SPR_NOACCESS,
1312 0x00000000);
1313 }
1314
1315 /* PowerPC BookE SPR */
1316 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1317 {
1318 const char *ivor_names[64] = {
1319 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1320 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1321 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1322 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1323 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1324 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1325 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1326 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1327 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1328 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1329 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1330 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1331 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1332 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1333 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1334 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1335 };
1336 #define SPR_BOOKE_IVORxx (-1)
1337 int ivor_sprn[64] = {
1338 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1339 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1340 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1341 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1342 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1343 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1344 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1345 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1346 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1347 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1348 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1349 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1350 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1351 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1352 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1353 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1354 };
1355 int i;
1356
1357 /* Interrupt processing */
1358 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1359 SPR_NOACCESS, SPR_NOACCESS,
1360 &spr_read_generic, &spr_write_generic,
1361 0x00000000);
1362 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1363 SPR_NOACCESS, SPR_NOACCESS,
1364 &spr_read_generic, &spr_write_generic,
1365 0x00000000);
1366 /* Debug */
1367 /* XXX : not implemented */
1368 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1369 SPR_NOACCESS, SPR_NOACCESS,
1370 &spr_read_generic, &spr_write_generic,
1371 0x00000000);
1372 /* XXX : not implemented */
1373 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1374 SPR_NOACCESS, SPR_NOACCESS,
1375 &spr_read_generic, &spr_write_generic,
1376 0x00000000);
1377 /* XXX : not implemented */
1378 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1379 SPR_NOACCESS, SPR_NOACCESS,
1380 &spr_read_generic, &spr_write_generic,
1381 0x00000000);
1382 /* XXX : not implemented */
1383 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1384 SPR_NOACCESS, SPR_NOACCESS,
1385 &spr_read_generic, &spr_write_generic,
1386 0x00000000);
1387 /* XXX : not implemented */
1388 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1389 SPR_NOACCESS, SPR_NOACCESS,
1390 &spr_read_generic, &spr_write_generic,
1391 0x00000000);
1392 /* XXX : not implemented */
1393 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1394 SPR_NOACCESS, SPR_NOACCESS,
1395 &spr_read_generic, &spr_write_generic,
1396 0x00000000);
1397 /* XXX : not implemented */
1398 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1399 SPR_NOACCESS, SPR_NOACCESS,
1400 &spr_read_generic, &spr_write_generic,
1401 0x00000000);
1402 /* XXX : not implemented */
1403 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1404 SPR_NOACCESS, SPR_NOACCESS,
1405 &spr_read_generic, &spr_write_clear,
1406 0x00000000);
1407 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1408 SPR_NOACCESS, SPR_NOACCESS,
1409 &spr_read_generic, &spr_write_generic,
1410 0x00000000);
1411 spr_register(env, SPR_BOOKE_ESR, "ESR",
1412 SPR_NOACCESS, SPR_NOACCESS,
1413 &spr_read_generic, &spr_write_generic,
1414 0x00000000);
1415 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1416 SPR_NOACCESS, SPR_NOACCESS,
1417 &spr_read_generic, &spr_write_excp_prefix,
1418 0x00000000);
1419 /* Exception vectors */
1420 for (i = 0; i < 64; i++) {
1421 if (ivor_mask & (1ULL << i)) {
1422 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1423 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1424 exit(1);
1425 }
1426 spr_register(env, ivor_sprn[i], ivor_names[i],
1427 SPR_NOACCESS, SPR_NOACCESS,
1428 &spr_read_generic, &spr_write_excp_vector,
1429 0x00000000);
1430 }
1431 }
1432 spr_register(env, SPR_BOOKE_PID, "PID",
1433 SPR_NOACCESS, SPR_NOACCESS,
1434 &spr_read_generic, &spr_write_generic,
1435 0x00000000);
1436 spr_register(env, SPR_BOOKE_TCR, "TCR",
1437 SPR_NOACCESS, SPR_NOACCESS,
1438 &spr_read_generic, &spr_write_booke_tcr,
1439 0x00000000);
1440 spr_register(env, SPR_BOOKE_TSR, "TSR",
1441 SPR_NOACCESS, SPR_NOACCESS,
1442 &spr_read_generic, &spr_write_booke_tsr,
1443 0x00000000);
1444 /* Timer */
1445 spr_register(env, SPR_DECR, "DECR",
1446 SPR_NOACCESS, SPR_NOACCESS,
1447 &spr_read_decr, &spr_write_decr,
1448 0x00000000);
1449 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1450 SPR_NOACCESS, SPR_NOACCESS,
1451 SPR_NOACCESS, &spr_write_generic,
1452 0x00000000);
1453 /* SPRGs */
1454 spr_register(env, SPR_USPRG0, "USPRG0",
1455 &spr_read_generic, &spr_write_generic,
1456 &spr_read_generic, &spr_write_generic,
1457 0x00000000);
1458 spr_register(env, SPR_SPRG4, "SPRG4",
1459 SPR_NOACCESS, SPR_NOACCESS,
1460 &spr_read_generic, &spr_write_generic,
1461 0x00000000);
1462 spr_register(env, SPR_SPRG5, "SPRG5",
1463 SPR_NOACCESS, SPR_NOACCESS,
1464 &spr_read_generic, &spr_write_generic,
1465 0x00000000);
1466 spr_register(env, SPR_SPRG6, "SPRG6",
1467 SPR_NOACCESS, SPR_NOACCESS,
1468 &spr_read_generic, &spr_write_generic,
1469 0x00000000);
1470 spr_register(env, SPR_SPRG7, "SPRG7",
1471 SPR_NOACCESS, SPR_NOACCESS,
1472 &spr_read_generic, &spr_write_generic,
1473 0x00000000);
1474 }
1475
1476 /* FSL storage control registers */
1477 static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
1478 {
1479 #if !defined(CONFIG_USER_ONLY)
1480 const char *mas_names[8] = {
1481 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1482 };
1483 int mas_sprn[8] = {
1484 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1485 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1486 };
1487 int i;
1488
1489 /* TLB assist registers */
1490 /* XXX : not implemented */
1491 for (i = 0; i < 8; i++) {
1492 if (mas_mask & (1 << i)) {
1493 spr_register(env, mas_sprn[i], mas_names[i],
1494 SPR_NOACCESS, SPR_NOACCESS,
1495 &spr_read_generic, &spr_write_generic,
1496 0x00000000);
1497 }
1498 }
1499 if (env->nb_pids > 1) {
1500 /* XXX : not implemented */
1501 spr_register(env, SPR_BOOKE_PID1, "PID1",
1502 SPR_NOACCESS, SPR_NOACCESS,
1503 &spr_read_generic, &spr_write_generic,
1504 0x00000000);
1505 }
1506 if (env->nb_pids > 2) {
1507 /* XXX : not implemented */
1508 spr_register(env, SPR_BOOKE_PID2, "PID2",
1509 SPR_NOACCESS, SPR_NOACCESS,
1510 &spr_read_generic, &spr_write_generic,
1511 0x00000000);
1512 }
1513 /* XXX : not implemented */
1514 spr_register(env, SPR_MMUCFG, "MMUCFG",
1515 SPR_NOACCESS, SPR_NOACCESS,
1516 &spr_read_generic, SPR_NOACCESS,
1517 0x00000000); /* TOFIX */
1518 /* XXX : not implemented */
1519 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
1520 SPR_NOACCESS, SPR_NOACCESS,
1521 &spr_read_generic, &spr_write_generic,
1522 0x00000000); /* TOFIX */
1523 switch (env->nb_ways) {
1524 case 4:
1525 /* XXX : not implemented */
1526 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1527 SPR_NOACCESS, SPR_NOACCESS,
1528 &spr_read_generic, SPR_NOACCESS,
1529 0x00000000); /* TOFIX */
1530 /* Fallthru */
1531 case 3:
1532 /* XXX : not implemented */
1533 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1534 SPR_NOACCESS, SPR_NOACCESS,
1535 &spr_read_generic, SPR_NOACCESS,
1536 0x00000000); /* TOFIX */
1537 /* Fallthru */
1538 case 2:
1539 /* XXX : not implemented */
1540 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1541 SPR_NOACCESS, SPR_NOACCESS,
1542 &spr_read_generic, SPR_NOACCESS,
1543 0x00000000); /* TOFIX */
1544 /* Fallthru */
1545 case 1:
1546 /* XXX : not implemented */
1547 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1548 SPR_NOACCESS, SPR_NOACCESS,
1549 &spr_read_generic, SPR_NOACCESS,
1550 0x00000000); /* TOFIX */
1551 /* Fallthru */
1552 case 0:
1553 default:
1554 break;
1555 }
1556 #endif
1557 }
1558
1559 /* SPR specific to PowerPC 440 implementation */
1560 static void gen_spr_440 (CPUPPCState *env)
1561 {
1562 /* Cache control */
1563 /* XXX : not implemented */
1564 spr_register(env, SPR_440_DNV0, "DNV0",
1565 SPR_NOACCESS, SPR_NOACCESS,
1566 &spr_read_generic, &spr_write_generic,
1567 0x00000000);
1568 /* XXX : not implemented */
1569 spr_register(env, SPR_440_DNV1, "DNV1",
1570 SPR_NOACCESS, SPR_NOACCESS,
1571 &spr_read_generic, &spr_write_generic,
1572 0x00000000);
1573 /* XXX : not implemented */
1574 spr_register(env, SPR_440_DNV2, "DNV2",
1575 SPR_NOACCESS, SPR_NOACCESS,
1576 &spr_read_generic, &spr_write_generic,
1577 0x00000000);
1578 /* XXX : not implemented */
1579 spr_register(env, SPR_440_DNV3, "DNV3",
1580 SPR_NOACCESS, SPR_NOACCESS,
1581 &spr_read_generic, &spr_write_generic,
1582 0x00000000);
1583 /* XXX : not implemented */
1584 spr_register(env, SPR_440_DTV0, "DTV0",
1585 SPR_NOACCESS, SPR_NOACCESS,
1586 &spr_read_generic, &spr_write_generic,
1587 0x00000000);
1588 /* XXX : not implemented */
1589 spr_register(env, SPR_440_DTV1, "DTV1",
1590 SPR_NOACCESS, SPR_NOACCESS,
1591 &spr_read_generic, &spr_write_generic,
1592 0x00000000);
1593 /* XXX : not implemented */
1594 spr_register(env, SPR_440_DTV2, "DTV2",
1595 SPR_NOACCESS, SPR_NOACCESS,
1596 &spr_read_generic, &spr_write_generic,
1597 0x00000000);
1598 /* XXX : not implemented */
1599 spr_register(env, SPR_440_DTV3, "DTV3",
1600 SPR_NOACCESS, SPR_NOACCESS,
1601 &spr_read_generic, &spr_write_generic,
1602 0x00000000);
1603 /* XXX : not implemented */
1604 spr_register(env, SPR_440_DVLIM, "DVLIM",
1605 SPR_NOACCESS, SPR_NOACCESS,
1606 &spr_read_generic, &spr_write_generic,
1607 0x00000000);
1608 /* XXX : not implemented */
1609 spr_register(env, SPR_440_INV0, "INV0",
1610 SPR_NOACCESS, SPR_NOACCESS,
1611 &spr_read_generic, &spr_write_generic,
1612 0x00000000);
1613 /* XXX : not implemented */
1614 spr_register(env, SPR_440_INV1, "INV1",
1615 SPR_NOACCESS, SPR_NOACCESS,
1616 &spr_read_generic, &spr_write_generic,
1617 0x00000000);
1618 /* XXX : not implemented */
1619 spr_register(env, SPR_440_INV2, "INV2",
1620 SPR_NOACCESS, SPR_NOACCESS,
1621 &spr_read_generic, &spr_write_generic,
1622 0x00000000);
1623 /* XXX : not implemented */
1624 spr_register(env, SPR_440_INV3, "INV3",
1625 SPR_NOACCESS, SPR_NOACCESS,
1626 &spr_read_generic, &spr_write_generic,
1627 0x00000000);
1628 /* XXX : not implemented */
1629 spr_register(env, SPR_440_ITV0, "ITV0",
1630 SPR_NOACCESS, SPR_NOACCESS,
1631 &spr_read_generic, &spr_write_generic,
1632 0x00000000);
1633 /* XXX : not implemented */
1634 spr_register(env, SPR_440_ITV1, "ITV1",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_generic, &spr_write_generic,
1637 0x00000000);
1638 /* XXX : not implemented */
1639 spr_register(env, SPR_440_ITV2, "ITV2",
1640 SPR_NOACCESS, SPR_NOACCESS,
1641 &spr_read_generic, &spr_write_generic,
1642 0x00000000);
1643 /* XXX : not implemented */
1644 spr_register(env, SPR_440_ITV3, "ITV3",
1645 SPR_NOACCESS, SPR_NOACCESS,
1646 &spr_read_generic, &spr_write_generic,
1647 0x00000000);
1648 /* XXX : not implemented */
1649 spr_register(env, SPR_440_IVLIM, "IVLIM",
1650 SPR_NOACCESS, SPR_NOACCESS,
1651 &spr_read_generic, &spr_write_generic,
1652 0x00000000);
1653 /* Cache debug */
1654 /* XXX : not implemented */
1655 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1656 SPR_NOACCESS, SPR_NOACCESS,
1657 &spr_read_generic, SPR_NOACCESS,
1658 0x00000000);
1659 /* XXX : not implemented */
1660 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1661 SPR_NOACCESS, SPR_NOACCESS,
1662 &spr_read_generic, SPR_NOACCESS,
1663 0x00000000);
1664 /* XXX : not implemented */
1665 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1666 SPR_NOACCESS, SPR_NOACCESS,
1667 &spr_read_generic, SPR_NOACCESS,
1668 0x00000000);
1669 /* XXX : not implemented */
1670 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1671 SPR_NOACCESS, SPR_NOACCESS,
1672 &spr_read_generic, SPR_NOACCESS,
1673 0x00000000);
1674 /* XXX : not implemented */
1675 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1676 SPR_NOACCESS, SPR_NOACCESS,
1677 &spr_read_generic, SPR_NOACCESS,
1678 0x00000000);
1679 /* XXX : not implemented */
1680 spr_register(env, SPR_440_DBDR, "DBDR",
1681 SPR_NOACCESS, SPR_NOACCESS,
1682 &spr_read_generic, &spr_write_generic,
1683 0x00000000);
1684 /* Processor control */
1685 spr_register(env, SPR_4xx_CCR0, "CCR0",
1686 SPR_NOACCESS, SPR_NOACCESS,
1687 &spr_read_generic, &spr_write_generic,
1688 0x00000000);
1689 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1690 SPR_NOACCESS, SPR_NOACCESS,
1691 &spr_read_generic, SPR_NOACCESS,
1692 0x00000000);
1693 /* Storage control */
1694 spr_register(env, SPR_440_MMUCR, "MMUCR",
1695 SPR_NOACCESS, SPR_NOACCESS,
1696 &spr_read_generic, &spr_write_generic,
1697 0x00000000);
1698 }
1699
1700 /* SPR shared between PowerPC 40x implementations */
1701 static void gen_spr_40x (CPUPPCState *env)
1702 {
1703 /* Cache */
1704 /* not emulated, as Qemu do not emulate caches */
1705 spr_register(env, SPR_40x_DCCR, "DCCR",
1706 SPR_NOACCESS, SPR_NOACCESS,
1707 &spr_read_generic, &spr_write_generic,
1708 0x00000000);
1709 /* not emulated, as Qemu do not emulate caches */
1710 spr_register(env, SPR_40x_ICCR, "ICCR",
1711 SPR_NOACCESS, SPR_NOACCESS,
1712 &spr_read_generic, &spr_write_generic,
1713 0x00000000);
1714 /* not emulated, as Qemu do not emulate caches */
1715 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1716 SPR_NOACCESS, SPR_NOACCESS,
1717 &spr_read_generic, SPR_NOACCESS,
1718 0x00000000);
1719 /* Exception */
1720 spr_register(env, SPR_40x_DEAR, "DEAR",
1721 SPR_NOACCESS, SPR_NOACCESS,
1722 &spr_read_generic, &spr_write_generic,
1723 0x00000000);
1724 spr_register(env, SPR_40x_ESR, "ESR",
1725 SPR_NOACCESS, SPR_NOACCESS,
1726 &spr_read_generic, &spr_write_generic,
1727 0x00000000);
1728 spr_register(env, SPR_40x_EVPR, "EVPR",
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, &spr_write_excp_prefix,
1731 0x00000000);
1732 spr_register(env, SPR_40x_SRR2, "SRR2",
1733 &spr_read_generic, &spr_write_generic,
1734 &spr_read_generic, &spr_write_generic,
1735 0x00000000);
1736 spr_register(env, SPR_40x_SRR3, "SRR3",
1737 &spr_read_generic, &spr_write_generic,
1738 &spr_read_generic, &spr_write_generic,
1739 0x00000000);
1740 /* Timers */
1741 spr_register(env, SPR_40x_PIT, "PIT",
1742 SPR_NOACCESS, SPR_NOACCESS,
1743 &spr_read_40x_pit, &spr_write_40x_pit,
1744 0x00000000);
1745 spr_register(env, SPR_40x_TCR, "TCR",
1746 SPR_NOACCESS, SPR_NOACCESS,
1747 &spr_read_generic, &spr_write_booke_tcr,
1748 0x00000000);
1749 spr_register(env, SPR_40x_TSR, "TSR",
1750 SPR_NOACCESS, SPR_NOACCESS,
1751 &spr_read_generic, &spr_write_booke_tsr,
1752 0x00000000);
1753 }
1754
1755 /* SPR specific to PowerPC 405 implementation */
1756 static void gen_spr_405 (CPUPPCState *env)
1757 {
1758 /* MMU */
1759 spr_register(env, SPR_40x_PID, "PID",
1760 SPR_NOACCESS, SPR_NOACCESS,
1761 &spr_read_generic, &spr_write_generic,
1762 0x00000000);
1763 spr_register(env, SPR_4xx_CCR0, "CCR0",
1764 SPR_NOACCESS, SPR_NOACCESS,
1765 &spr_read_generic, &spr_write_generic,
1766 0x00700000);
1767 /* Debug interface */
1768 /* XXX : not implemented */
1769 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1770 SPR_NOACCESS, SPR_NOACCESS,
1771 &spr_read_generic, &spr_write_40x_dbcr0,
1772 0x00000000);
1773 /* XXX : not implemented */
1774 spr_register(env, SPR_405_DBCR1, "DBCR1",
1775 SPR_NOACCESS, SPR_NOACCESS,
1776 &spr_read_generic, &spr_write_generic,
1777 0x00000000);
1778 /* XXX : not implemented */
1779 spr_register(env, SPR_40x_DBSR, "DBSR",
1780 SPR_NOACCESS, SPR_NOACCESS,
1781 &spr_read_generic, &spr_write_clear,
1782 /* Last reset was system reset */
1783 0x00000300);
1784 /* XXX : not implemented */
1785 spr_register(env, SPR_40x_DAC1, "DAC1",
1786 SPR_NOACCESS, SPR_NOACCESS,
1787 &spr_read_generic, &spr_write_generic,
1788 0x00000000);
1789 spr_register(env, SPR_40x_DAC2, "DAC2",
1790 SPR_NOACCESS, SPR_NOACCESS,
1791 &spr_read_generic, &spr_write_generic,
1792 0x00000000);
1793 /* XXX : not implemented */
1794 spr_register(env, SPR_405_DVC1, "DVC1",
1795 SPR_NOACCESS, SPR_NOACCESS,
1796 &spr_read_generic, &spr_write_generic,
1797 0x00000000);
1798 /* XXX : not implemented */
1799 spr_register(env, SPR_405_DVC2, "DVC2",
1800 SPR_NOACCESS, SPR_NOACCESS,
1801 &spr_read_generic, &spr_write_generic,
1802 0x00000000);
1803 /* XXX : not implemented */
1804 spr_register(env, SPR_40x_IAC1, "IAC1",
1805 SPR_NOACCESS, SPR_NOACCESS,
1806 &spr_read_generic, &spr_write_generic,
1807 0x00000000);
1808 spr_register(env, SPR_40x_IAC2, "IAC2",
1809 SPR_NOACCESS, SPR_NOACCESS,
1810 &spr_read_generic, &spr_write_generic,
1811 0x00000000);
1812 /* XXX : not implemented */
1813 spr_register(env, SPR_405_IAC3, "IAC3",
1814 SPR_NOACCESS, SPR_NOACCESS,
1815 &spr_read_generic, &spr_write_generic,
1816 0x00000000);
1817 /* XXX : not implemented */
1818 spr_register(env, SPR_405_IAC4, "IAC4",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, &spr_write_generic,
1821 0x00000000);
1822 /* Storage control */
1823 /* XXX: TODO: not implemented */
1824 spr_register(env, SPR_405_SLER, "SLER",
1825 SPR_NOACCESS, SPR_NOACCESS,
1826 &spr_read_generic, &spr_write_40x_sler,
1827 0x00000000);
1828 spr_register(env, SPR_40x_ZPR, "ZPR",
1829 SPR_NOACCESS, SPR_NOACCESS,
1830 &spr_read_generic, &spr_write_generic,
1831 0x00000000);
1832 /* XXX : not implemented */
1833 spr_register(env, SPR_405_SU0R, "SU0R",
1834 SPR_NOACCESS, SPR_NOACCESS,
1835 &spr_read_generic, &spr_write_generic,
1836 0x00000000);
1837 /* SPRG */
1838 spr_register(env, SPR_USPRG0, "USPRG0",
1839 &spr_read_ureg, SPR_NOACCESS,
1840 &spr_read_ureg, SPR_NOACCESS,
1841 0x00000000);
1842 spr_register(env, SPR_SPRG4, "SPRG4",
1843 SPR_NOACCESS, SPR_NOACCESS,
1844 &spr_read_generic, &spr_write_generic,
1845 0x00000000);
1846 spr_register(env, SPR_SPRG5, "SPRG5",
1847 SPR_NOACCESS, SPR_NOACCESS,
1848 spr_read_generic, &spr_write_generic,
1849 0x00000000);
1850 spr_register(env, SPR_SPRG6, "SPRG6",
1851 SPR_NOACCESS, SPR_NOACCESS,
1852 spr_read_generic, &spr_write_generic,
1853 0x00000000);
1854 spr_register(env, SPR_SPRG7, "SPRG7",
1855 SPR_NOACCESS, SPR_NOACCESS,
1856 spr_read_generic, &spr_write_generic,
1857 0x00000000);
1858 gen_spr_usprgh(env);
1859 }
1860
1861 /* SPR shared between PowerPC 401 & 403 implementations */
1862 static void gen_spr_401_403 (CPUPPCState *env)
1863 {
1864 /* Time base */
1865 spr_register(env, SPR_403_VTBL, "TBL",
1866 &spr_read_tbl, SPR_NOACCESS,
1867 &spr_read_tbl, SPR_NOACCESS,
1868 0x00000000);
1869 spr_register(env, SPR_403_TBL, "TBL",
1870 SPR_NOACCESS, SPR_NOACCESS,
1871 SPR_NOACCESS, &spr_write_tbl,
1872 0x00000000);
1873 spr_register(env, SPR_403_VTBU, "TBU",
1874 &spr_read_tbu, SPR_NOACCESS,
1875 &spr_read_tbu, SPR_NOACCESS,
1876 0x00000000);
1877 spr_register(env, SPR_403_TBU, "TBU",
1878 SPR_NOACCESS, SPR_NOACCESS,
1879 SPR_NOACCESS, &spr_write_tbu,
1880 0x00000000);
1881 /* Debug */
1882 /* not emulated, as Qemu do not emulate caches */
1883 spr_register(env, SPR_403_CDBCR, "CDBCR",
1884 SPR_NOACCESS, SPR_NOACCESS,
1885 &spr_read_generic, &spr_write_generic,
1886 0x00000000);
1887 }
1888
1889 /* SPR specific to PowerPC 401 implementation */
1890 static void gen_spr_401 (CPUPPCState *env)
1891 {
1892 /* Debug interface */
1893 /* XXX : not implemented */
1894 spr_register(env, SPR_40x_DBCR0, "DBCR",
1895 SPR_NOACCESS, SPR_NOACCESS,
1896 &spr_read_generic, &spr_write_40x_dbcr0,
1897 0x00000000);
1898 /* XXX : not implemented */
1899 spr_register(env, SPR_40x_DBSR, "DBSR",
1900 SPR_NOACCESS, SPR_NOACCESS,
1901 &spr_read_generic, &spr_write_clear,
1902 /* Last reset was system reset */
1903 0x00000300);
1904 /* XXX : not implemented */
1905 spr_register(env, SPR_40x_DAC1, "DAC",
1906 SPR_NOACCESS, SPR_NOACCESS,
1907 &spr_read_generic, &spr_write_generic,
1908 0x00000000);
1909 /* XXX : not implemented */
1910 spr_register(env, SPR_40x_IAC1, "IAC",
1911 SPR_NOACCESS, SPR_NOACCESS,
1912 &spr_read_generic, &spr_write_generic,
1913 0x00000000);
1914 /* Storage control */
1915 /* XXX: TODO: not implemented */
1916 spr_register(env, SPR_405_SLER, "SLER",
1917 SPR_NOACCESS, SPR_NOACCESS,
1918 &spr_read_generic, &spr_write_40x_sler,
1919 0x00000000);
1920 /* not emulated, as Qemu never does speculative access */
1921 spr_register(env, SPR_40x_SGR, "SGR",
1922 SPR_NOACCESS, SPR_NOACCESS,
1923 &spr_read_generic, &spr_write_generic,
1924 0xFFFFFFFF);
1925 /* not emulated, as Qemu do not emulate caches */
1926 spr_register(env, SPR_40x_DCWR, "DCWR",
1927 SPR_NOACCESS, SPR_NOACCESS,
1928 &spr_read_generic, &spr_write_generic,
1929 0x00000000);
1930 }
1931
1932 static void gen_spr_401x2 (CPUPPCState *env)
1933 {
1934 gen_spr_401(env);
1935 spr_register(env, SPR_40x_PID, "PID",
1936 SPR_NOACCESS, SPR_NOACCESS,
1937 &spr_read_generic, &spr_write_generic,
1938 0x00000000);
1939 spr_register(env, SPR_40x_ZPR, "ZPR",
1940 SPR_NOACCESS, SPR_NOACCESS,
1941 &spr_read_generic, &spr_write_generic,
1942 0x00000000);
1943 }
1944
1945 /* SPR specific to PowerPC 403 implementation */
1946 static void gen_spr_403 (CPUPPCState *env)
1947 {
1948 /* Debug interface */
1949 /* XXX : not implemented */
1950 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1951 SPR_NOACCESS, SPR_NOACCESS,
1952 &spr_read_generic, &spr_write_40x_dbcr0,
1953 0x00000000);
1954 /* XXX : not implemented */
1955 spr_register(env, SPR_40x_DBSR, "DBSR",
1956 SPR_NOACCESS, SPR_NOACCESS,
1957 &spr_read_generic, &spr_write_clear,
1958 /* Last reset was system reset */
1959 0x00000300);
1960 /* XXX : not implemented */
1961 spr_register(env, SPR_40x_DAC1, "DAC1",
1962 SPR_NOACCESS, SPR_NOACCESS,
1963 &spr_read_generic, &spr_write_generic,
1964 0x00000000);
1965 /* XXX : not implemented */
1966 spr_register(env, SPR_40x_DAC2, "DAC2",
1967 SPR_NOACCESS, SPR_NOACCESS,
1968 &spr_read_generic, &spr_write_generic,
1969 0x00000000);
1970 /* XXX : not implemented */
1971 spr_register(env, SPR_40x_IAC1, "IAC1",
1972 SPR_NOACCESS, SPR_NOACCESS,
1973 &spr_read_generic, &spr_write_generic,
1974 0x00000000);
1975 /* XXX : not implemented */
1976 spr_register(env, SPR_40x_IAC2, "IAC2",
1977 SPR_NOACCESS, SPR_NOACCESS,
1978 &spr_read_generic, &spr_write_generic,
1979 0x00000000);
1980 }
1981
1982 static void gen_spr_403_real (CPUPPCState *env)
1983 {
1984 spr_register(env, SPR_403_PBL1, "PBL1",
1985 SPR_NOACCESS, SPR_NOACCESS,
1986 &spr_read_403_pbr, &spr_write_403_pbr,
1987 0x00000000);
1988 spr_register(env, SPR_403_PBU1, "PBU1",
1989 SPR_NOACCESS, SPR_NOACCESS,
1990 &spr_read_403_pbr, &spr_write_403_pbr,
1991 0x00000000);
1992 spr_register(env, SPR_403_PBL2, "PBL2",
1993 SPR_NOACCESS, SPR_NOACCESS,
1994 &spr_read_403_pbr, &spr_write_403_pbr,
1995 0x00000000);
1996 spr_register(env, SPR_403_PBU2, "PBU2",
1997 SPR_NOACCESS, SPR_NOACCESS,
1998 &spr_read_403_pbr, &spr_write_403_pbr,
1999 0x00000000);
2000 }
2001
2002 static void gen_spr_403_mmu (CPUPPCState *env)
2003 {
2004 /* MMU */
2005 spr_register(env, SPR_40x_PID, "PID",
2006 SPR_NOACCESS, SPR_NOACCESS,
2007 &spr_read_generic, &spr_write_generic,
2008 0x00000000);
2009 spr_register(env, SPR_40x_ZPR, "ZPR",
2010 SPR_NOACCESS, SPR_NOACCESS,
2011 &spr_read_generic, &spr_write_generic,
2012 0x00000000);
2013 }
2014
2015 /* SPR specific to PowerPC compression coprocessor extension */
2016 static void gen_spr_compress (CPUPPCState *env)
2017 {
2018 /* XXX : not implemented */
2019 spr_register(env, SPR_401_SKR, "SKR",
2020 SPR_NOACCESS, SPR_NOACCESS,
2021 &spr_read_generic, &spr_write_generic,
2022 0x00000000);
2023 }
2024
2025 #if defined (TARGET_PPC64)
2026 /* SPR specific to PowerPC 620 */
2027 static void gen_spr_620 (CPUPPCState *env)
2028 {
2029 /* Processor identification */
2030 spr_register(env, SPR_PIR, "PIR",
2031 SPR_NOACCESS, SPR_NOACCESS,
2032 &spr_read_generic, &spr_write_pir,
2033 0x00000000);
2034 spr_register(env, SPR_ASR, "ASR",
2035 SPR_NOACCESS, SPR_NOACCESS,
2036 &spr_read_asr, &spr_write_asr,
2037 0x00000000);
2038 /* Breakpoints */
2039 /* XXX : not implemented */
2040 spr_register(env, SPR_IABR, "IABR",
2041 SPR_NOACCESS, SPR_NOACCESS,
2042 &spr_read_generic, &spr_write_generic,
2043 0x00000000);
2044 /* XXX : not implemented */
2045 spr_register(env, SPR_DABR, "DABR",
2046 SPR_NOACCESS, SPR_NOACCESS,
2047 &spr_read_generic, &spr_write_generic,
2048 0x00000000);
2049 /* XXX : not implemented */
2050 spr_register(env, SPR_SIAR, "SIAR",
2051 SPR_NOACCESS, SPR_NOACCESS,
2052 &spr_read_generic, SPR_NOACCESS,
2053 0x00000000);
2054 /* XXX : not implemented */
2055 spr_register(env, SPR_SDA, "SDA",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_generic, SPR_NOACCESS,
2058 0x00000000);
2059 /* XXX : not implemented */
2060 spr_register(env, SPR_620_PMC1R, "PMC1",
2061 SPR_NOACCESS, SPR_NOACCESS,
2062 &spr_read_generic, SPR_NOACCESS,
2063 0x00000000);
2064 spr_register(env, SPR_620_PMC1W, "PMC1",
2065 SPR_NOACCESS, SPR_NOACCESS,
2066 SPR_NOACCESS, &spr_write_generic,
2067 0x00000000);
2068 /* XXX : not implemented */
2069 spr_register(env, SPR_620_PMC2R, "PMC2",
2070 SPR_NOACCESS, SPR_NOACCESS,
2071 &spr_read_generic, SPR_NOACCESS,
2072 0x00000000);
2073 spr_register(env, SPR_620_PMC2W, "PMC2",
2074 SPR_NOACCESS, SPR_NOACCESS,
2075 SPR_NOACCESS, &spr_write_generic,
2076 0x00000000);
2077 /* XXX : not implemented */
2078 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2079 SPR_NOACCESS, SPR_NOACCESS,
2080 &spr_read_generic, SPR_NOACCESS,
2081 0x00000000);
2082 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2083 SPR_NOACCESS, SPR_NOACCESS,
2084 SPR_NOACCESS, &spr_write_generic,
2085 0x00000000);
2086 /* External access control */
2087 /* XXX : not implemented */
2088 spr_register(env, SPR_EAR, "EAR",
2089 SPR_NOACCESS, SPR_NOACCESS,
2090 &spr_read_generic, &spr_write_generic,
2091 0x00000000);
2092 #if 0 // XXX: check this
2093 /* XXX : not implemented */
2094 spr_register(env, SPR_620_PMR0, "PMR0",
2095 SPR_NOACCESS, SPR_NOACCESS,
2096 &spr_read_generic, &spr_write_generic,
2097 0x00000000);
2098 /* XXX : not implemented */
2099 spr_register(env, SPR_620_PMR1, "PMR1",
2100 SPR_NOACCESS, SPR_NOACCESS,
2101 &spr_read_generic, &spr_write_generic,
2102 0x00000000);
2103 /* XXX : not implemented */
2104 spr_register(env, SPR_620_PMR2, "PMR2",
2105 SPR_NOACCESS, SPR_NOACCESS,
2106 &spr_read_generic, &spr_write_generic,
2107 0x00000000);
2108 /* XXX : not implemented */
2109 spr_register(env, SPR_620_PMR3, "PMR3",
2110 SPR_NOACCESS, SPR_NOACCESS,
2111 &spr_read_generic, &spr_write_generic,
2112 0x00000000);
2113 /* XXX : not implemented */
2114 spr_register(env, SPR_620_PMR4, "PMR4",
2115 SPR_NOACCESS, SPR_NOACCESS,
2116 &spr_read_generic, &spr_write_generic,
2117 0x00000000);
2118 /* XXX : not implemented */
2119 spr_register(env, SPR_620_PMR5, "PMR5",
2120 SPR_NOACCESS, SPR_NOACCESS,
2121 &spr_read_generic, &spr_write_generic,
2122 0x00000000);
2123 /* XXX : not implemented */
2124 spr_register(env, SPR_620_PMR6, "PMR6",
2125 SPR_NOACCESS, SPR_NOACCESS,
2126 &spr_read_generic, &spr_write_generic,
2127 0x00000000);
2128 /* XXX : not implemented */
2129 spr_register(env, SPR_620_PMR7, "PMR7",
2130 SPR_NOACCESS, SPR_NOACCESS,
2131 &spr_read_generic, &spr_write_generic,
2132 0x00000000);
2133 /* XXX : not implemented */
2134 spr_register(env, SPR_620_PMR8, "PMR8",
2135 SPR_NOACCESS, SPR_NOACCESS,
2136 &spr_read_generic, &spr_write_generic,
2137 0x00000000);
2138 /* XXX : not implemented */
2139 spr_register(env, SPR_620_PMR9, "PMR9",
2140 SPR_NOACCESS, SPR_NOACCESS,
2141 &spr_read_generic, &spr_write_generic,
2142 0x00000000);
2143 /* XXX : not implemented */
2144 spr_register(env, SPR_620_PMRA, "PMR10",
2145 SPR_NOACCESS, SPR_NOACCESS,
2146 &spr_read_generic, &spr_write_generic,
2147 0x00000000);
2148 /* XXX : not implemented */
2149 spr_register(env, SPR_620_PMRB, "PMR11",
2150 SPR_NOACCESS, SPR_NOACCESS,
2151 &spr_read_generic, &spr_write_generic,
2152 0x00000000);
2153 /* XXX : not implemented */
2154 spr_register(env, SPR_620_PMRC, "PMR12",
2155 SPR_NOACCESS, SPR_NOACCESS,
2156 &spr_read_generic, &spr_write_generic,
2157 0x00000000);
2158 /* XXX : not implemented */
2159 spr_register(env, SPR_620_PMRD, "PMR13",
2160 SPR_NOACCESS, SPR_NOACCESS,
2161 &spr_read_generic, &spr_write_generic,
2162 0x00000000);
2163 /* XXX : not implemented */
2164 spr_register(env, SPR_620_PMRE, "PMR14",
2165 SPR_NOACCESS, SPR_NOACCESS,
2166 &spr_read_generic, &spr_write_generic,
2167 0x00000000);
2168 /* XXX : not implemented */
2169 spr_register(env, SPR_620_PMRF, "PMR15",
2170 SPR_NOACCESS, SPR_NOACCESS,
2171 &spr_read_generic, &spr_write_generic,
2172 0x00000000);
2173 #endif
2174 /* XXX : not implemented */
2175 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2176 SPR_NOACCESS, SPR_NOACCESS,
2177 &spr_read_generic, &spr_write_generic,
2178 0x00000000);
2179 /* XXX : not implemented */
2180 spr_register(env, SPR_620_L2CR, "L2CR",
2181 SPR_NOACCESS, SPR_NOACCESS,
2182 &spr_read_generic, &spr_write_generic,
2183 0x00000000);
2184 /* XXX : not implemented */
2185 spr_register(env, SPR_620_L2SR, "L2SR",
2186 SPR_NOACCESS, SPR_NOACCESS,
2187 &spr_read_generic, &spr_write_generic,
2188 0x00000000);
2189 }
2190 #endif /* defined (TARGET_PPC64) */
2191
2192 static void gen_spr_5xx_8xx (CPUPPCState *env)
2193 {
2194 /* Exception processing */
2195 spr_register(env, SPR_DSISR, "DSISR",
2196 SPR_NOACCESS, SPR_NOACCESS,
2197 &spr_read_generic, &spr_write_generic,
2198 0x00000000);
2199 spr_register(env, SPR_DAR, "DAR",
2200 SPR_NOACCESS, SPR_NOACCESS,
2201 &spr_read_generic, &spr_write_generic,
2202 0x00000000);
2203 /* Timer */
2204 spr_register(env, SPR_DECR, "DECR",
2205 SPR_NOACCESS, SPR_NOACCESS,
2206 &spr_read_decr, &spr_write_decr,
2207 0x00000000);
2208 /* XXX : not implemented */
2209 spr_register(env, SPR_MPC_EIE, "EIE",
2210 SPR_NOACCESS, SPR_NOACCESS,
2211 &spr_read_generic, &spr_write_generic,
2212 0x00000000);
2213 /* XXX : not implemented */
2214 spr_register(env, SPR_MPC_EID, "EID",
2215 SPR_NOACCESS, SPR_NOACCESS,
2216 &spr_read_generic, &spr_write_generic,
2217 0x00000000);
2218 /* XXX : not implemented */
2219 spr_register(env, SPR_MPC_NRI, "NRI",
2220 SPR_NOACCESS, SPR_NOACCESS,
2221 &spr_read_generic, &spr_write_generic,
2222 0x00000000);
2223 /* XXX : not implemented */
2224 spr_register(env, SPR_MPC_CMPA, "CMPA",
2225 SPR_NOACCESS, SPR_NOACCESS,
2226 &spr_read_generic, &spr_write_generic,
2227 0x00000000);
2228 /* XXX : not implemented */
2229 spr_register(env, SPR_MPC_CMPB, "CMPB",
2230 SPR_NOACCESS, SPR_NOACCESS,
2231 &spr_read_generic, &spr_write_generic,
2232 0x00000000);
2233 /* XXX : not implemented */
2234 spr_register(env, SPR_MPC_CMPC, "CMPC",
2235 SPR_NOACCESS, SPR_NOACCESS,
2236 &spr_read_generic, &spr_write_generic,
2237 0x00000000);
2238 /* XXX : not implemented */
2239 spr_register(env, SPR_MPC_CMPD, "CMPD",
2240 SPR_NOACCESS, SPR_NOACCESS,
2241 &spr_read_generic, &spr_write_generic,
2242 0x00000000);
2243 /* XXX : not implemented */
2244 spr_register(env, SPR_MPC_ECR, "ECR",
2245 SPR_NOACCESS, SPR_NOACCESS,
2246 &spr_read_generic, &spr_write_generic,
2247 0x00000000);
2248 /* XXX : not implemented */
2249 spr_register(env, SPR_MPC_DER, "DER",
2250 SPR_NOACCESS, SPR_NOACCESS,
2251 &spr_read_generic, &spr_write_generic,
2252 0x00000000);
2253 /* XXX : not implemented */
2254 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2255 SPR_NOACCESS, SPR_NOACCESS,
2256 &spr_read_generic, &spr_write_generic,
2257 0x00000000);
2258 /* XXX : not implemented */
2259 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2260 SPR_NOACCESS, SPR_NOACCESS,
2261 &spr_read_generic, &spr_write_generic,
2262 0x00000000);
2263 /* XXX : not implemented */
2264 spr_register(env, SPR_MPC_CMPE, "CMPE",
2265 SPR_NOACCESS, SPR_NOACCESS,
2266 &spr_read_generic, &spr_write_generic,
2267 0x00000000);
2268 /* XXX : not implemented */
2269 spr_register(env, SPR_MPC_CMPF, "CMPF",
2270 SPR_NOACCESS, SPR_NOACCESS,
2271 &spr_read_generic, &spr_write_generic,
2272 0x00000000);
2273 /* XXX : not implemented */
2274 spr_register(env, SPR_MPC_CMPG, "CMPG",
2275 SPR_NOACCESS, SPR_NOACCESS,
2276 &spr_read_generic, &spr_write_generic,
2277 0x00000000);
2278 /* XXX : not implemented */
2279 spr_register(env, SPR_MPC_CMPH, "CMPH",
2280 SPR_NOACCESS, SPR_NOACCESS,
2281 &spr_read_generic, &spr_write_generic,
2282 0x00000000);
2283 /* XXX : not implemented */
2284 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2285 SPR_NOACCESS, SPR_NOACCESS,
2286 &spr_read_generic, &spr_write_generic,
2287 0x00000000);
2288 /* XXX : not implemented */
2289 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2290 SPR_NOACCESS, SPR_NOACCESS,
2291 &spr_read_generic, &spr_write_generic,
2292 0x00000000);
2293 /* XXX : not implemented */
2294 spr_register(env, SPR_MPC_BAR, "BAR",
2295 SPR_NOACCESS, SPR_NOACCESS,
2296 &spr_read_generic, &spr_write_generic,
2297 0x00000000);
2298 /* XXX : not implemented */
2299 spr_register(env, SPR_MPC_DPDR, "DPDR",
2300 SPR_NOACCESS, SPR_NOACCESS,
2301 &spr_read_generic, &spr_write_generic,
2302 0x00000000);
2303 /* XXX : not implemented */
2304 spr_register(env, SPR_MPC_IMMR, "IMMR",
2305 SPR_NOACCESS, SPR_NOACCESS,
2306 &spr_read_generic, &spr_write_generic,
2307 0x00000000);
2308 }
2309
2310 static void gen_spr_5xx (CPUPPCState *env)
2311 {
2312 /* XXX : not implemented */
2313 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2314 SPR_NOACCESS, SPR_NOACCESS,
2315 &spr_read_generic, &spr_write_generic,
2316 0x00000000);
2317 /* XXX : not implemented */
2318 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2319 SPR_NOACCESS, SPR_NOACCESS,
2320 &spr_read_generic, &spr_write_generic,
2321 0x00000000);
2322 /* XXX : not implemented */
2323 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2324 SPR_NOACCESS, SPR_NOACCESS,
2325 &spr_read_generic, &spr_write_generic,
2326 0x00000000);
2327 /* XXX : not implemented */
2328 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2329 SPR_NOACCESS, SPR_NOACCESS,
2330 &spr_read_generic, &spr_write_generic,
2331 0x00000000);
2332 /* XXX : not implemented */
2333 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2334 SPR_NOACCESS, SPR_NOACCESS,
2335 &spr_read_generic, &spr_write_generic,
2336 0x00000000);
2337 /* XXX : not implemented */
2338 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2339 SPR_NOACCESS, SPR_NOACCESS,
2340 &spr_read_generic, &spr_write_generic,
2341 0x00000000);
2342 /* XXX : not implemented */
2343 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2344 SPR_NOACCESS, SPR_NOACCESS,
2345 &spr_read_generic, &spr_write_generic,
2346 0x00000000);
2347 /* XXX : not implemented */
2348 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2349 SPR_NOACCESS, SPR_NOACCESS,
2350 &spr_read_generic, &spr_write_generic,
2351 0x00000000);
2352 /* XXX : not implemented */
2353 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2354 SPR_NOACCESS, SPR_NOACCESS,
2355 &spr_read_generic, &spr_write_generic,
2356 0x00000000);
2357 /* XXX : not implemented */
2358 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2359 SPR_NOACCESS, SPR_NOACCESS,
2360 &spr_read_generic, &spr_write_generic,
2361 0x00000000);
2362 /* XXX : not implemented */
2363 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2364 SPR_NOACCESS, SPR_NOACCESS,
2365 &spr_read_generic, &spr_write_generic,
2366 0x00000000);
2367 /* XXX : not implemented */
2368 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2369 SPR_NOACCESS, SPR_NOACCESS,
2370 &spr_read_generic, &spr_write_generic,
2371 0x00000000);
2372 /* XXX : not implemented */
2373 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2374 SPR_NOACCESS, SPR_NOACCESS,
2375 &spr_read_generic, &spr_write_generic,
2376 0x00000000);
2377 /* XXX : not implemented */
2378 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2379 SPR_NOACCESS, SPR_NOACCESS,
2380 &spr_read_generic, &spr_write_generic,
2381 0x00000000);
2382 /* XXX : not implemented */
2383 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2384 SPR_NOACCESS, SPR_NOACCESS,
2385 &spr_read_generic, &spr_write_generic,
2386 0x00000000);
2387 /* XXX : not implemented */
2388 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2389 SPR_NOACCESS, SPR_NOACCESS,
2390 &spr_read_generic, &spr_write_generic,
2391 0x00000000);
2392 /* XXX : not implemented */
2393 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2394 SPR_NOACCESS, SPR_NOACCESS,
2395 &spr_read_generic, &spr_write_generic,
2396 0x00000000);
2397 /* XXX : not implemented */
2398 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2399 SPR_NOACCESS, SPR_NOACCESS,
2400 &spr_read_generic, &spr_write_generic,
2401 0x00000000);
2402 /* XXX : not implemented */
2403 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2404 SPR_NOACCESS, SPR_NOACCESS,
2405 &spr_read_generic, &spr_write_generic,
2406 0x00000000);
2407 /* XXX : not implemented */
2408 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2409 SPR_NOACCESS, SPR_NOACCESS,
2410 &spr_read_generic, &spr_write_generic,
2411 0x00000000);
2412 /* XXX : not implemented */
2413 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2414 SPR_NOACCESS, SPR_NOACCESS,
2415 &spr_read_generic, &spr_write_generic,
2416 0x00000000);
2417 }
2418
2419 static void gen_spr_8xx (CPUPPCState *env)
2420 {
2421 /* XXX : not implemented */
2422 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2423 SPR_NOACCESS, SPR_NOACCESS,
2424 &spr_read_generic, &spr_write_generic,
2425 0x00000000);
2426 /* XXX : not implemented */
2427 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2428 SPR_NOACCESS, SPR_NOACCESS,
2429 &spr_read_generic, &spr_write_generic,
2430 0x00000000);
2431 /* XXX : not implemented */
2432 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2433 SPR_NOACCESS, SPR_NOACCESS,
2434 &spr_read_generic, &spr_write_generic,
2435 0x00000000);
2436 /* XXX : not implemented */
2437 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2438 SPR_NOACCESS, SPR_NOACCESS,
2439 &spr_read_generic, &spr_write_generic,
2440 0x00000000);
2441 /* XXX : not implemented */
2442 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2443 SPR_NOACCESS, SPR_NOACCESS,
2444 &spr_read_generic, &spr_write_generic,
2445 0x00000000);
2446 /* XXX : not implemented */
2447 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2448 SPR_NOACCESS, SPR_NOACCESS,
2449 &spr_read_generic, &spr_write_generic,
2450 0x00000000);
2451 /* XXX : not implemented */
2452 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2453 SPR_NOACCESS, SPR_NOACCESS,
2454 &spr_read_generic, &spr_write_generic,
2455 0x00000000);
2456 /* XXX : not implemented */
2457 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2458 SPR_NOACCESS, SPR_NOACCESS,
2459 &spr_read_generic, &spr_write_generic,
2460 0x00000000);
2461 /* XXX : not implemented */
2462 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2463 SPR_NOACCESS, SPR_NOACCESS,
2464 &spr_read_generic, &spr_write_generic,
2465 0x00000000);
2466 /* XXX : not implemented */
2467 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2468 SPR_NOACCESS, SPR_NOACCESS,
2469 &spr_read_generic, &spr_write_generic,
2470 0x00000000);
2471 /* XXX : not implemented */
2472 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2473 SPR_NOACCESS, SPR_NOACCESS,
2474 &spr_read_generic, &spr_write_generic,
2475 0x00000000);
2476 /* XXX : not implemented */
2477 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2478 SPR_NOACCESS, SPR_NOACCESS,
2479 &spr_read_generic, &spr_write_generic,
2480 0x00000000);
2481 /* XXX : not implemented */
2482 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2483 SPR_NOACCESS, SPR_NOACCESS,
2484 &spr_read_generic, &spr_write_generic,
2485 0x00000000);
2486 /* XXX : not implemented */
2487 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2488 SPR_NOACCESS, SPR_NOACCESS,
2489 &spr_read_generic, &spr_write_generic,
2490 0x00000000);
2491 /* XXX : not implemented */
2492 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2493 SPR_NOACCESS, SPR_NOACCESS,
2494 &spr_read_generic, &spr_write_generic,
2495 0x00000000);
2496 /* XXX : not implemented */
2497 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2498 SPR_NOACCESS, SPR_NOACCESS,
2499 &spr_read_generic, &spr_write_generic,
2500 0x00000000);
2501 /* XXX : not implemented */
2502 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2503 SPR_NOACCESS, SPR_NOACCESS,
2504 &spr_read_generic, &spr_write_generic,
2505 0x00000000);
2506 /* XXX : not implemented */
2507 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2508 SPR_NOACCESS, SPR_NOACCESS,
2509 &spr_read_generic, &spr_write_generic,
2510 0x00000000);
2511 /* XXX : not implemented */
2512 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2513 SPR_NOACCESS, SPR_NOACCESS,
2514 &spr_read_generic, &spr_write_generic,
2515 0x00000000);
2516 /* XXX : not implemented */
2517 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2518 SPR_NOACCESS, SPR_NOACCESS,
2519 &spr_read_generic, &spr_write_generic,
2520 0x00000000);
2521 /* XXX : not implemented */
2522 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2523 SPR_NOACCESS, SPR_NOACCESS,
2524 &spr_read_generic, &spr_write_generic,
2525 0x00000000);
2526 /* XXX : not implemented */
2527 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2528 SPR_NOACCESS, SPR_NOACCESS,
2529 &spr_read_generic, &spr_write_generic,
2530 0x00000000);
2531 /* XXX : not implemented */
2532 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2533 SPR_NOACCESS, SPR_NOACCESS,
2534 &spr_read_generic, &spr_write_generic,
2535 0x00000000);
2536 /* XXX : not implemented */
2537 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2538 SPR_NOACCESS, SPR_NOACCESS,
2539 &spr_read_generic, &spr_write_generic,
2540 0x00000000);
2541 /* XXX : not implemented */
2542 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2543 SPR_NOACCESS, SPR_NOACCESS,
2544 &spr_read_generic, &spr_write_generic,
2545 0x00000000);
2546 }
2547
2548 // XXX: TODO
2549 /*
2550 * AMR => SPR 29 (Power 2.04)
2551 * CTRL => SPR 136 (Power 2.04)
2552 * CTRL => SPR 152 (Power 2.04)
2553 * SCOMC => SPR 276 (64 bits ?)
2554 * SCOMD => SPR 277 (64 bits ?)
2555 * TBU40 => SPR 286 (Power 2.04 hypv)
2556 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2557 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2558 * HDSISR => SPR 306 (Power 2.04 hypv)
2559 * HDAR => SPR 307 (Power 2.04 hypv)
2560 * PURR => SPR 309 (Power 2.04 hypv)
2561 * HDEC => SPR 310 (Power 2.04 hypv)
2562 * HIOR => SPR 311 (hypv)
2563 * RMOR => SPR 312 (970)
2564 * HRMOR => SPR 313 (Power 2.04 hypv)
2565 * HSRR0 => SPR 314 (Power 2.04 hypv)
2566 * HSRR1 => SPR 315 (Power 2.04 hypv)
2567 * LPCR => SPR 316 (970)
2568 * LPIDR => SPR 317 (970)
2569 * SPEFSCR => SPR 512 (Power 2.04 emb)
2570 * EPR => SPR 702 (Power 2.04 emb)
2571 * perf => 768-783 (Power 2.04)
2572 * perf => 784-799 (Power 2.04)
2573 * PPR => SPR 896 (Power 2.04)
2574 * EPLC => SPR 947 (Power 2.04 emb)
2575 * EPSC => SPR 948 (Power 2.04 emb)
2576 * DABRX => 1015 (Power 2.04 hypv)
2577 * FPECR => SPR 1022 (?)
2578 * ... and more (thermal management, performance counters, ...)
2579 */
2580
2581 /*****************************************************************************/
2582 /* Exception vectors models */
2583 static void init_excp_4xx_real (CPUPPCState *env)
2584 {
2585 #if !defined(CONFIG_USER_ONLY)
2586 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2587 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2588 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2589 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2590 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2591 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2592 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2593 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2594 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2595 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2596 env->excp_prefix = 0x00000000UL;
2597 env->ivor_mask = 0x0000FFF0UL;
2598 env->ivpr_mask = 0xFFFF0000UL;
2599 /* Hardware reset vector */
2600 env->hreset_vector = 0xFFFFFFFCUL;
2601 #endif
2602 }
2603
2604 static void init_excp_4xx_softmmu (CPUPPCState *env)
2605 {
2606 #if !defined(CONFIG_USER_ONLY)
2607 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2608 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2609 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2610 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2611 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2612 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2613 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2614 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2615 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2616 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2617 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2618 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2619 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2620 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2621 env->excp_prefix = 0x00000000UL;
2622 env->ivor_mask = 0x0000FFF0UL;
2623 env->ivpr_mask = 0xFFFF0000UL;
2624 /* Hardware reset vector */
2625 env->hreset_vector = 0xFFFFFFFCUL;
2626 #endif
2627 }
2628
2629 static void init_excp_MPC5xx (CPUPPCState *env)
2630 {
2631 #if !defined(CONFIG_USER_ONLY)
2632 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2633 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2634 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2635 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2636 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2637 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2638 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2639 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2640 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2641 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2642 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2643 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2644 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2645 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2646 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2647 env->excp_prefix = 0x00000000UL;
2648 env->ivor_mask = 0x0000FFF0UL;
2649 env->ivpr_mask = 0xFFFF0000UL;
2650 /* Hardware reset vector */
2651 env->hreset_vector = 0xFFFFFFFCUL;
2652 #endif
2653 }
2654
2655 static void init_excp_MPC8xx (CPUPPCState *env)
2656 {
2657 #if !defined(CONFIG_USER_ONLY)
2658 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2659 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2660 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2661 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2662 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2663 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2664 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2665 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2666 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2667 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2668 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2669 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2670 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2671 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2672 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2673 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2674 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2675 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2676 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2677 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2678 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2679 env->excp_prefix = 0x00000000UL;
2680 env->ivor_mask = 0x0000FFF0UL;
2681 env->ivpr_mask = 0xFFFF0000UL;
2682 /* Hardware reset vector */
2683 env->hreset_vector = 0xFFFFFFFCUL;
2684 #endif
2685 }
2686
2687 static void init_excp_G2 (CPUPPCState *env)
2688 {
2689 #if !defined(CONFIG_USER_ONLY)
2690 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2691 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2692 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2693 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2694 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2695 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2696 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2697 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2698 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2699 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2700 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2701 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2702 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2703 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2704 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2705 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2706 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2707 env->excp_prefix = 0x00000000UL;
2708 /* Hardware reset vector */
2709 env->hreset_vector = 0xFFFFFFFCUL;
2710 #endif
2711 }
2712
2713 static void init_excp_e200 (CPUPPCState *env)
2714 {
2715 #if !defined(CONFIG_USER_ONLY)
2716 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2717 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2718 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2719 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2720 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2721 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2722 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2723 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2724 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2725 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2726 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2727 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2728 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2729 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2730 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2731 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2732 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2733 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2734 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2735 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2736 env->excp_prefix = 0x00000000UL;
2737 env->ivor_mask = 0x0000FFF7UL;
2738 env->ivpr_mask = 0xFFFF0000UL;
2739 /* Hardware reset vector */
2740 env->hreset_vector = 0xFFFFFFFCUL;
2741 #endif
2742 }
2743
2744 static void init_excp_BookE (CPUPPCState *env)
2745 {
2746 #if !defined(CONFIG_USER_ONLY)
2747 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2748 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2749 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2750 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2751 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2752 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2753 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2754 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2755 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2756 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2757 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2758 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2759 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2760 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2761 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2762 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2763 env->excp_prefix = 0x00000000UL;
2764 env->ivor_mask = 0x0000FFE0UL;
2765 env->ivpr_mask = 0xFFFF0000UL;
2766 /* Hardware reset vector */
2767 env->hreset_vector = 0xFFFFFFFCUL;
2768 #endif
2769 }
2770
2771 static void init_excp_601 (CPUPPCState *env)
2772 {
2773 #if !defined(CONFIG_USER_ONLY)
2774 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2775 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2776 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2777 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2778 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2779 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2780 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2781 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2782 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2783 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2784 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2785 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2786 env->excp_prefix = 0xFFF00000UL;
2787 /* Hardware reset vector */
2788 env->hreset_vector = 0x00000100UL;
2789 #endif
2790 }
2791
2792 static void init_excp_602 (CPUPPCState *env)
2793 {
2794 #if !defined(CONFIG_USER_ONLY)
2795 /* XXX: exception prefix has a special behavior on 602 */
2796 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2797 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2798 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2799 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2800 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2801 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2802 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2803 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2804 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2805 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2806 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2807 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2808 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2809 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2810 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2811 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2812 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2813 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2814 env->excp_prefix = 0xFFF00000UL;
2815 /* Hardware reset vector */
2816 env->hreset_vector = 0xFFFFFFFCUL;
2817 #endif
2818 }
2819
2820 static void init_excp_603 (CPUPPCState *env)
2821 {
2822 #if !defined(CONFIG_USER_ONLY)
2823 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2824 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2825 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2826 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2827 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2828 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2829 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2830 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2831 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2832 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2833 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2834 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2835 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2836 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2837 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2838 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2839 env->excp_prefix = 0x00000000UL;
2840 /* Hardware reset vector */
2841 env->hreset_vector = 0xFFFFFFFCUL;
2842 #endif
2843 }
2844
2845 static void init_excp_604 (CPUPPCState *env)
2846 {
2847 #if !defined(CONFIG_USER_ONLY)
2848 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2849 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2850 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2851 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2852 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2853 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2854 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2855 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2856 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2857 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2858 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2859 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2860 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2861 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2862 env->excp_prefix = 0x00000000UL;
2863 /* Hardware reset vector */
2864 env->hreset_vector = 0xFFFFFFFCUL;
2865 #endif
2866 }
2867
2868 #if defined(TARGET_PPC64)
2869 static void init_excp_620 (CPUPPCState *env)
2870 {
2871 #if !defined(CONFIG_USER_ONLY)
2872 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2873 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2874 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2875 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2876 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2877 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2878 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2879 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2880 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2881 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2882 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2883 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2884 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2885 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2886 env->excp_prefix = 0xFFF00000UL;
2887 /* Hardware reset vector */
2888 env->hreset_vector = 0x0000000000000100ULL;
2889 #endif
2890 }
2891 #endif /* defined(TARGET_PPC64) */
2892
2893 static void init_excp_7x0 (CPUPPCState *env)
2894 {
2895 #if !defined(CONFIG_USER_ONLY)
2896 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2897 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2898 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2899 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2900 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2901 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2902 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2903 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2904 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2905 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2906 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2907 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2908 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2909 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2910 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2911 env->excp_prefix = 0x00000000UL;
2912 /* Hardware reset vector */
2913 env->hreset_vector = 0xFFFFFFFCUL;
2914 #endif
2915 }
2916
2917 static void init_excp_750cl (CPUPPCState *env)
2918 {
2919 #if !defined(CONFIG_USER_ONLY)
2920 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2921 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2922 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2923 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2924 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2925 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2926 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2927 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2928 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2929 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2930 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2931 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2932 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2933 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2934 env->excp_prefix = 0x00000000UL;
2935 /* Hardware reset vector */
2936 env->hreset_vector = 0xFFFFFFFCUL;
2937 #endif
2938 }
2939
2940 static void init_excp_750cx (CPUPPCState *env)
2941 {
2942 #if !defined(CONFIG_USER_ONLY)
2943 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2944 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2945 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2946 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2947 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2948 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2949 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2950 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2951 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2952 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2953 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2954 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2955 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2956 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2957 env->excp_prefix = 0x00000000UL;
2958 /* Hardware reset vector */
2959 env->hreset_vector = 0xFFFFFFFCUL;
2960 #endif
2961 }
2962
2963 /* XXX: Check if this is correct */
2964 static void init_excp_7x5 (CPUPPCState *env)
2965 {
2966 #if !defined(CONFIG_USER_ONLY)
2967 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2968 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2969 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2970 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2971 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2972 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2973 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2974 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2975 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2976 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2977 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2978 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2979 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2980 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2981 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2982 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2983 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2984 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2985 env->excp_prefix = 0x00000000UL;
2986 /* Hardware reset vector */
2987 env->hreset_vector = 0xFFFFFFFCUL;
2988 #endif
2989 }
2990
2991 static void init_excp_7400 (CPUPPCState *env)
2992 {
2993 #if !defined(CONFIG_USER_ONLY)
2994 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2995 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2996 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2997 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2998 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2999 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3000 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3001 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3002 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3003 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3004 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3005 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3006 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3007 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3008 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3009 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3010 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3011 env->excp_prefix = 0x00000000UL;
3012 /* Hardware reset vector */
3013 env->hreset_vector = 0xFFFFFFFCUL;
3014 #endif
3015 }
3016
3017 static void init_excp_7450 (CPUPPCState *env)
3018 {
3019 #if !defined(CONFIG_USER_ONLY)
3020 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3021 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3022 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3023 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3024 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3025 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3026 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3027 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3028 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3029 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3030 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3031 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3032 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3033 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3034 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3035 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3036 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3037 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3038 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3039 env->excp_prefix = 0x00000000UL;
3040 /* Hardware reset vector */
3041 env->hreset_vector = 0xFFFFFFFCUL;
3042 #endif
3043 }
3044
3045 #if defined (TARGET_PPC64)
3046 static void init_excp_970 (CPUPPCState *env)
3047 {
3048 #if !defined(CONFIG_USER_ONLY)
3049 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3050 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3051 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3052 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3053 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3054 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3055 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3056 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3057 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3058 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3059 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3060 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3061 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3062 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3063 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3064 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3065 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3066 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3067 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3068 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3069 env->excp_prefix = 0x00000000FFF00000ULL;
3070 /* Hardware reset vector */
3071 env->hreset_vector = 0x0000000000000100ULL;
3072 #endif
3073 }
3074 #endif
3075
3076 /*****************************************************************************/
3077 /* Power management enable checks */
3078 static int check_pow_none (CPUPPCState *env)
3079 {
3080 return 0;
3081 }
3082
3083 static int check_pow_nocheck (CPUPPCState *env)
3084 {
3085 return 1;
3086 }
3087
3088 static int check_pow_hid0 (CPUPPCState *env)
3089 {
3090 if (env->spr[SPR_HID0] & 0x00E00000)
3091 return 1;
3092
3093 return 0;
3094 }
3095
3096 static int check_pow_hid0_74xx (CPUPPCState *env)
3097 {
3098 if (env->spr[SPR_HID0] & 0x00600000)
3099 return 1;
3100
3101 return 0;
3102 }
3103
3104 /*****************************************************************************/
3105 /* PowerPC implementations definitions */
3106
3107 /* PowerPC 401 */
3108 #define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3109 PPC_WRTEE | PPC_DCR | \
3110 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3111 PPC_CACHE_DCBZ | \
3112 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3113 PPC_4xx_COMMON | PPC_40x_EXCP)
3114 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
3115 #define POWERPC_MMU_401 (POWERPC_MMU_REAL)
3116 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3117 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
3118 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
3119 #define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3120 POWERPC_FLAG_BUS_CLK)
3121 #define check_pow_401 check_pow_nocheck
3122
3123 static void init_proc_401 (CPUPPCState *env)
3124 {
3125 gen_spr_40x(env);
3126 gen_spr_401_403(env);
3127 gen_spr_401(env);
3128 init_excp_4xx_real(env);
3129 env->dcache_line_size = 32;
3130 env->icache_line_size = 32;
3131 /* Allocate hardware IRQ controller */
3132 ppc40x_irq_init(env);
3133 }
3134
3135 /* PowerPC 401x2 */
3136 #define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3137 PPC_DCR | PPC_WRTEE | \
3138 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3139 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3140 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3141 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3142 PPC_4xx_COMMON | PPC_40x_EXCP)
3143 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3144 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3145 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3146 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
3147 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
3148 #define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3149 POWERPC_FLAG_BUS_CLK)
3150 #define check_pow_401x2 check_pow_nocheck
3151
3152 static void init_proc_401x2 (CPUPPCState *env)
3153 {
3154 gen_spr_40x(env);
3155 gen_spr_401_403(env);
3156 gen_spr_401x2(env);
3157 gen_spr_compress(env);
3158 /* Memory management */
3159 #if !defined(CONFIG_USER_ONLY)
3160 env->nb_tlb = 64;
3161 env->nb_ways = 1;
3162 env->id_tlbs = 0;
3163 #endif
3164 init_excp_4xx_softmmu(env);
3165 env->dcache_line_size = 32;
3166 env->icache_line_size = 32;
3167 /* Allocate hardware IRQ controller */
3168 ppc40x_irq_init(env);
3169 }
3170
3171 /* PowerPC 401x3 */
3172 #define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3173 PPC_DCR | PPC_WRTEE | \
3174 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3175 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3176 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3177 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3178 PPC_4xx_COMMON | PPC_40x_EXCP)
3179 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3180 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3181 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3182 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
3183 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
3184 #define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3185 POWERPC_FLAG_BUS_CLK)
3186 #define check_pow_401x3 check_pow_nocheck
3187
3188 __attribute__ (( unused ))
3189 static void init_proc_401x3 (CPUPPCState *env)
3190 {
3191 gen_spr_40x(env);
3192 gen_spr_401_403(env);
3193 gen_spr_401(env);
3194 gen_spr_401x2(env);
3195 gen_spr_compress(env);
3196 init_excp_4xx_softmmu(env);
3197 env->dcache_line_size = 32;
3198 env->icache_line_size = 32;
3199 /* Allocate hardware IRQ controller */
3200 ppc40x_irq_init(env);
3201 }
3202
3203 /* IOP480 */
3204 #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3205 PPC_DCR | PPC_WRTEE | \
3206 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3207 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3208 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3209 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3210 PPC_4xx_COMMON | PPC_40x_EXCP)
3211 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3212 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3213 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3214 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3215 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
3216 #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3217 POWERPC_FLAG_BUS_CLK)
3218 #define check_pow_IOP480 check_pow_nocheck
3219
3220 static void init_proc_IOP480 (CPUPPCState *env)
3221 {
3222 gen_spr_40x(env);
3223 gen_spr_401_403(env);
3224 gen_spr_401x2(env);
3225 gen_spr_compress(env);
3226 /* Memory management */
3227 #if !defined(CONFIG_USER_ONLY)
3228 env->nb_tlb = 64;
3229 env->nb_ways = 1;
3230 env->id_tlbs = 0;
3231 #endif
3232 init_excp_4xx_softmmu(env);
3233 env->dcache_line_size = 32;
3234 env->icache_line_size = 32;
3235 /* Allocate hardware IRQ controller */
3236 ppc40x_irq_init(env);
3237 }
3238
3239 /* PowerPC 403 */
3240 #define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3241 PPC_DCR | PPC_WRTEE | \
3242 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3243 PPC_CACHE_DCBZ | \
3244 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3245 PPC_4xx_COMMON | PPC_40x_EXCP)
3246 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
3247 #define POWERPC_MMU_403 (POWERPC_MMU_REAL)
3248 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3249 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
3250 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
3251 #define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3252 POWERPC_FLAG_BUS_CLK)
3253 #define check_pow_403 check_pow_nocheck
3254
3255 static void init_proc_403 (CPUPPCState *env)
3256 {
3257 gen_spr_40x(env);
3258 gen_spr_401_403(env);
3259 gen_spr_403(env);
3260 gen_spr_403_real(env);
3261 init_excp_4xx_real(env);
3262 env->dcache_line_size = 32;
3263 env->icache_line_size = 32;
3264 /* Allocate hardware IRQ controller */
3265 ppc40x_irq_init(env);
3266 }
3267
3268 /* PowerPC 403 GCX */
3269 #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3270 PPC_DCR | PPC_WRTEE | \
3271 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3272 PPC_CACHE_DCBZ | \
3273 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3274 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3275 PPC_4xx_COMMON | PPC_40x_EXCP)
3276 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3277 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3278 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3279 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3280 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
3281 #define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3282 POWERPC_FLAG_BUS_CLK)
3283 #define check_pow_403GCX check_pow_nocheck
3284
3285 static void init_proc_403GCX (CPUPPCState *env)
3286 {
3287 gen_spr_40x(env);
3288 gen_spr_401_403(env);
3289 gen_spr_403(env);
3290 gen_spr_403_real(env);
3291 gen_spr_403_mmu(env);
3292 /* Bus access control */
3293 /* not emulated, as Qemu never does speculative access */
3294 spr_register(env, SPR_40x_SGR, "SGR",
3295 SPR_NOACCESS, SPR_NOACCESS,
3296 &spr_read_generic, &spr_write_generic,
3297 0xFFFFFFFF);
3298 /* not emulated, as Qemu do not emulate caches */
3299 spr_register(env, SPR_40x_DCWR, "DCWR",
3300 SPR_NOACCESS, SPR_NOACCESS,
3301 &spr_read_generic, &spr_write_generic,
3302 0x00000000);
3303 /* Memory management */
3304 #if !defined(CONFIG_USER_ONLY)
3305 env->nb_tlb = 64;
3306 env->nb_ways = 1;
3307 env->id_tlbs = 0;
3308 #endif
3309 init_excp_4xx_softmmu(env);
3310 env->dcache_line_size = 32;
3311 env->icache_line_size = 32;
3312 /* Allocate hardware IRQ controller */
3313 ppc40x_irq_init(env);
3314 }
3315
3316 /* PowerPC 405 */
3317 #define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3318 PPC_DCR | PPC_WRTEE | \
3319 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3320 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3321 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3322 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3323 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3324 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
3325 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3326 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3327 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3328 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3329 #define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3330 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3331 #define check_pow_405 check_pow_nocheck
3332
3333 static void init_proc_405 (CPUPPCState *env)
3334 {
3335 /* Time base */
3336 gen_tbl(env);
3337 gen_spr_40x(env);
3338 gen_spr_405(env);
3339 /* Bus access control */
3340 /* not emulated, as Qemu never does speculative access */
3341 spr_register(env, SPR_40x_SGR, "SGR",
3342 SPR_NOACCESS, SPR_NOACCESS,
3343 &spr_read_generic, &spr_write_generic,
3344 0xFFFFFFFF);
3345 /* not emulated, as Qemu do not emulate caches */
3346 spr_register(env, SPR_40x_DCWR, "DCWR",
3347 SPR_NOACCESS, SPR_NOACCESS,
3348 &spr_read_generic, &spr_write_generic,
3349 0x00000000);
3350 /* Memory management */
3351 #if !defined(CONFIG_USER_ONLY)
3352 env->nb_tlb = 64;
3353 env->nb_ways = 1;
3354 env->id_tlbs = 0;
3355 #endif
3356 init_excp_4xx_softmmu(env);
3357 env->dcache_line_size = 32;
3358 env->icache_line_size = 32;
3359 /* Allocate hardware IRQ controller */
3360 ppc40x_irq_init(env);
3361 }
3362
3363 /* PowerPC 440 EP */
3364 #define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3365 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3366 PPC_CACHE | PPC_CACHE_ICBI | \
3367 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3368 PPC_MEM_TLBSYNC | \
3369 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3370 PPC_440_SPEC)
3371 #define POWERPC_MSRM_440EP (0x000000000006D630ULL)
3372 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3373 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3374 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3375 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3376 #define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3377 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3378 #define check_pow_440EP check_pow_nocheck
3379
3380 __attribute__ (( unused ))
3381 static void init_proc_440EP (CPUPPCState *env)
3382 {
3383 /* Time base */
3384 gen_tbl(env);
3385 gen_spr_BookE(env, 0x000000000000FFFFULL);
3386 gen_spr_440(env);
3387 gen_spr_usprgh(env);
3388 /* Processor identification */
3389 spr_register(env, SPR_BOOKE_PIR, "PIR",
3390 SPR_NOACCESS, SPR_NOACCESS,
3391 &spr_read_generic, &spr_write_pir,
3392 0x00000000);
3393 /* XXX : not implemented */
3394 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3395 SPR_NOACCESS, SPR_NOACCESS,
3396 &spr_read_generic, &spr_write_generic,
3397 0x00000000);
3398 /* XXX : not implemented */
3399 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3400 SPR_NOACCESS, SPR_NOACCESS,
3401 &spr_read_generic, &spr_write_generic,
3402 0x00000000);
3403 /* XXX : not implemented */
3404 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3405 SPR_NOACCESS, SPR_NOACCESS,
3406 &spr_read_generic, &spr_write_generic,
3407 0x00000000);
3408 /* XXX : not implemented */
3409 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3410 SPR_NOACCESS, SPR_NOACCESS,
3411 &spr_read_generic, &spr_write_generic,
3412 0x00000000);
3413 /* XXX : not implemented */
3414 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3415 SPR_NOACCESS, SPR_NOACCESS,
3416 &spr_read_generic, &spr_write_generic,
3417 0x00000000);
3418 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3419 SPR_NOACCESS, SPR_NOACCESS,
3420 &spr_read_generic, &spr_write_generic,
3421 0x00000000);
3422 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3423 SPR_NOACCESS, SPR_NOACCESS,
3424 &spr_read_generic, &spr_write_generic,
3425 0x00000000);
3426 /* XXX : not implemented */
3427 spr_register(env, SPR_440_CCR1, "CCR1",
3428 SPR_NOACCESS, SPR_NOACCESS,
3429 &spr_read_generic, &spr_write_generic,
3430 0x00000000);
3431 /* Memory management */
3432 #if !defined(CONFIG_USER_ONLY)
3433 env->nb_tlb = 64;
3434 env->nb_ways = 1;
3435 env->id_tlbs = 0;
3436 #endif
3437 init_excp_BookE(env);
3438 env->dcache_line_size = 32;
3439 env->icache_line_size = 32;
3440 /* XXX: TODO: allocate internal IRQ controller */
3441 }
3442
3443 /* PowerPC 440 GP */
3444 #define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3445 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3446 PPC_CACHE | PPC_CACHE_ICBI | \
3447 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3448 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3449 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3450 PPC_440_SPEC)
3451 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3452 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3453 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3454 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3455 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3456 #define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3457 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3458 #define check_pow_440GP check_pow_nocheck
3459
3460 __attribute__ (( unused ))
3461 static void init_proc_440GP (CPUPPCState *env)
3462 {
3463 /* Time base */
3464 gen_tbl(env);
3465 gen_spr_BookE(env, 0x000000000000FFFFULL);
3466 gen_spr_440(env);
3467 gen_spr_usprgh(env);
3468 /* Processor identification */
3469 spr_register(env, SPR_BOOKE_PIR, "PIR",
3470 SPR_NOACCESS, SPR_NOACCESS,
3471 &spr_read_generic, &spr_write_pir,
3472 0x00000000);
3473 /* XXX : not implemented */
3474 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3475 SPR_NOACCESS, SPR_NOACCESS,
3476 &spr_read_generic, &spr_write_generic,
3477 0x00000000);
3478 /* XXX : not implemented */
3479 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3480 SPR_NOACCESS, SPR_NOACCESS,
3481 &spr_read_generic, &spr_write_generic,
3482 0x00000000);
3483 /* XXX : not implemented */
3484 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3485 SPR_NOACCESS, SPR_NOACCESS,
3486 &spr_read_generic, &spr_write_generic,
3487 0x00000000);
3488 /* XXX : not implemented */
3489 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3490 SPR_NOACCESS, SPR_NOACCESS,
3491 &spr_read_generic, &spr_write_generic,
3492 0x00000000);
3493 /* Memory management */
3494 #if !defined(CONFIG_USER_ONLY)
3495 env->nb_tlb = 64;
3496 env->nb_ways = 1;
3497 env->id_tlbs = 0;
3498 #endif
3499 init_excp_BookE(env);
3500 env->dcache_line_size = 32;
3501 env->icache_line_size = 32;
3502 /* XXX: TODO: allocate internal IRQ controller */
3503 }
3504
3505 /* PowerPC 440x4 */
3506 #define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3507 PPC_DCR | PPC_WRTEE | \
3508 PPC_CACHE | PPC_CACHE_ICBI | \
3509 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3510 PPC_MEM_TLBSYNC | \
3511 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3512 PPC_440_SPEC)
3513 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3514 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3515 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3516 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3517 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3518 #define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3519 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3520 #define check_pow_440x4 check_pow_nocheck
3521
3522 __attribute__ (( unused ))
3523 static void init_proc_440x4 (CPUPPCState *env)
3524 {
3525 /* Time base */
3526 gen_tbl(env);
3527 gen_spr_BookE(env, 0x000000000000FFFFULL);
3528 gen_spr_440(env);
3529 gen_spr_usprgh(env);
3530 /* Processor identification */
3531 spr_register(env, SPR_BOOKE_PIR, "PIR",
3532 SPR_NOACCESS, SPR_NOACCESS,
3533 &spr_read_generic, &spr_write_pir,
3534 0x00000000);
3535 /* XXX : not implemented */
3536 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3537 SPR_NOACCESS, SPR_NOACCESS,
3538 &spr_read_generic, &spr_write_generic,
3539 0x00000000);
3540 /* XXX : not implemented */
3541 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3542 SPR_NOACCESS, SPR_NOACCESS,
3543 &spr_read_generic, &spr_write_generic,
3544 0x00000000);
3545 /* XXX : not implemented */
3546 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3547 SPR_NOACCESS, SPR_NOACCESS,
3548 &spr_read_generic, &spr_write_generic,
3549 0x00000000);
3550 /* XXX : not implemented */
3551 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3552 SPR_NOACCESS, SPR_NOACCESS,
3553 &spr_read_generic, &spr_write_generic,
3554 0x00000000);
3555 /* Memory management */
3556 #if !defined(CONFIG_USER_ONLY)
3557 env->nb_tlb = 64;
3558 env->nb_ways = 1;
3559 env->id_tlbs = 0;
3560 #endif
3561 init_excp_BookE(env);
3562 env->dcache_line_size = 32;
3563 env->icache_line_size = 32;
3564 /* XXX: TODO: allocate internal IRQ controller */
3565 }
3566
3567 /* PowerPC 440x5 */
3568 #define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3569 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3570 PPC_CACHE | PPC_CACHE_ICBI | \
3571 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3572 PPC_MEM_TLBSYNC | \
3573 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3574 PPC_440_SPEC)
3575 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3576 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3577 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3578 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3579 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3580 #define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3581 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3582 #define check_pow_440x5 check_pow_nocheck
3583
3584 __attribute__ (( unused ))
3585 static void init_proc_440x5 (CPUPPCState *env)
3586 {
3587 /* Time base */
3588 gen_tbl(env);
3589 gen_spr_BookE(env, 0x000000000000FFFFULL);
3590 gen_spr_440(env);
3591 gen_spr_usprgh(env);
3592 /* Processor identification */
3593 spr_register(env, SPR_BOOKE_PIR, "PIR",
3594 SPR_NOACCESS, SPR_NOACCESS,
3595 &spr_read_generic, &spr_write_pir,
3596 0x00000000);
3597 /* XXX : not implemented */
3598 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3599 SPR_NOACCESS, SPR_NOACCESS,
3600 &spr_read_generic, &spr_write_generic,
3601 0x00000000);
3602 /* XXX : not implemented */
3603 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3604 SPR_NOACCESS, SPR_NOACCESS,
3605 &spr_read_generic, &spr_write_generic,
3606 0x00000000);
3607 /* XXX : not implemented */
3608 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3609 SPR_NOACCESS, SPR_NOACCESS,
3610 &spr_read_generic, &spr_write_generic,
3611 0x00000000);
3612 /* XXX : not implemented */
3613 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3614 SPR_NOACCESS, SPR_NOACCESS,
3615 &spr_read_generic, &spr_write_generic,
3616 0x00000000);
3617 /* XXX : not implemented */
3618 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3619 SPR_NOACCESS, SPR_NOACCESS,
3620 &spr_read_generic, &spr_write_generic,
3621 0x00000000);
3622 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3623 SPR_NOACCESS, SPR_NOACCESS,
3624 &spr_read_generic, &spr_write_generic,
3625 0x00000000);
3626 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3627 SPR_NOACCESS, SPR_NOACCESS,
3628 &spr_read_generic, &spr_write_generic,
3629 0x00000000);
3630 /* XXX : not implemented */
3631 spr_register(env, SPR_440_CCR1, "CCR1",
3632 SPR_NOACCESS, SPR_NOACCESS,
3633 &spr_read_generic, &spr_write_generic,
3634 0x00000000);
3635 /* Memory management */
3636 #if !defined(CONFIG_USER_ONLY)
3637 env->nb_tlb = 64;
3638 env->nb_ways = 1;
3639 env->id_tlbs = 0;
3640 #endif
3641 init_excp_BookE(env);
3642 env->dcache_line_size = 32;
3643 env->icache_line_size = 32;
3644 /* XXX: TODO: allocate internal IRQ controller */
3645 }
3646
3647 /* PowerPC 460 (guessed) */
3648 #define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
3649 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3650 PPC_WRTEE | PPC_MFAPIDI | \
3651 PPC_CACHE | PPC_CACHE_ICBI | \
3652 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3653 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3654 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3655 PPC_440_SPEC)
3656 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3657 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3658 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3659 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3660 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3661 #define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3662 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3663 #define check_pow_460 check_pow_nocheck
3664
3665 __attribute__ (( unused ))
3666 static void init_proc_460 (CPUPPCState *env)
3667 {
3668 /* Time base */
3669 gen_tbl(env);
3670 gen_spr_BookE(env, 0x000000000000FFFFULL);
3671 gen_spr_440(env);
3672 gen_spr_usprgh(env);
3673 /* Processor identification */
3674 spr_register(env, SPR_BOOKE_PIR, "PIR",
3675 SPR_NOACCESS, SPR_NOACCESS,
3676 &spr_read_generic, &spr_write_pir,
3677 0x00000000);
3678 /* XXX : not implemented */
3679 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3680 SPR_NOACCESS, SPR_NOACCESS,
3681 &spr_read_generic, &spr_write_generic,
3682 0x00000000);
3683 /* XXX : not implemented */
3684 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3685 SPR_NOACCESS, SPR_NOACCESS,
3686 &spr_read_generic, &spr_write_generic,
3687 0x00000000);
3688 /* XXX : not implemented */
3689 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3690 SPR_NOACCESS, SPR_NOACCESS,
3691 &spr_read_generic, &spr_write_generic,
3692 0x00000000);
3693 /* XXX : not implemented */
3694 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3695 SPR_NOACCESS, SPR_NOACCESS,
3696 &spr_read_generic, &spr_write_generic,
3697 0x00000000);
3698 /* XXX : not implemented */
3699 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3700 SPR_NOACCESS, SPR_NOACCESS,
3701 &spr_read_generic, &spr_write_generic,
3702 0x00000000);
3703 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3704 SPR_NOACCESS, SPR_NOACCESS,
3705 &spr_read_generic, &spr_write_generic,
3706 0x00000000);
3707 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3708 SPR_NOACCESS, SPR_NOACCESS,
3709 &spr_read_generic, &spr_write_generic,
3710 0x00000000);
3711 /* XXX : not implemented */
3712 spr_register(env, SPR_440_CCR1, "CCR1",
3713 SPR_NOACCESS, SPR_NOACCESS,
3714 &spr_read_generic, &spr_write_generic,
3715 0x00000000);
3716 /* XXX : not implemented */
3717 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3718 &spr_read_generic, &spr_write_generic,
3719 &spr_read_generic, &spr_write_generic,
3720 0x00000000);
3721 /* Memory management */
3722 #if !defined(CONFIG_USER_ONLY)
3723 env->nb_tlb = 64;
3724 env->nb_ways = 1;
3725 env->id_tlbs = 0;
3726 #endif
3727 init_excp_BookE(env);
3728 env->dcache_line_size = 32;
3729 env->icache_line_size = 32;
3730 /* XXX: TODO: allocate internal IRQ controller */
3731 }
3732
3733 /* PowerPC 460F (guessed) */
3734 #define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3735 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3736 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3737 PPC_FLOAT_STFIWX | \
3738 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3739 PPC_WRTEE | PPC_MFAPIDI | \
3740 PPC_CACHE | PPC_CACHE_ICBI | \
3741 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3742 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3743 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3744 PPC_440_SPEC)
3745 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3746 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3747 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3748 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3749 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3750 #define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3751 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3752 #define check_pow_460F check_pow_nocheck
3753
3754 __attribute__ (( unused ))
3755 static void init_proc_460F (CPUPPCState *env)
3756 {
3757 /* Time base */
3758 gen_tbl(env);
3759 gen_spr_BookE(env, 0x000000000000FFFFULL);
3760 gen_spr_440(env);
3761 gen_spr_usprgh(env);
3762 /* Processor identification */
3763 spr_register(env, SPR_BOOKE_PIR, "PIR",
3764 SPR_NOACCESS, SPR_NOACCESS,
3765 &spr_read_generic, &spr_write_pir,
3766 0x00000000);
3767 /* XXX : not implemented */
3768 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3769 SPR_NOACCESS, SPR_NOACCESS,
3770 &spr_read_generic, &spr_write_generic,
3771 0x00000000);
3772 /* XXX : not implemented */
3773 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3774 SPR_NOACCESS, SPR_NOACCESS,
3775 &spr_read_generic, &spr_write_generic,
3776 0x00000000);
3777 /* XXX : not implemented */
3778 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3779 SPR_NOACCESS, SPR_NOACCESS,
3780 &spr_read_generic, &spr_write_generic,
3781 0x00000000);
3782 /* XXX : not implemented */
3783 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3784 SPR_NOACCESS, SPR_NOACCESS,
3785 &spr_read_generic, &spr_write_generic,
3786 0x00000000);
3787 /* XXX : not implemented */
3788 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3789 SPR_NOACCESS, SPR_NOACCESS,
3790 &spr_read_generic, &spr_write_generic,
3791 0x00000000);
3792 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3793 SPR_NOACCESS, SPR_NOACCESS,
3794 &spr_read_generic, &spr_write_generic,
3795 0x00000000);
3796 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3797 SPR_NOACCESS, SPR_NOACCESS,
3798 &spr_read_generic, &spr_write_generic,
3799 0x00000000);
3800 /* XXX : not implemented */
3801 spr_register(env, SPR_440_CCR1, "CCR1",
3802 SPR_NOACCESS, SPR_NOACCESS,
3803 &spr_read_generic, &spr_write_generic,
3804 0x00000000);
3805 /* XXX : not implemented */
3806 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3807 &spr_read_generic, &spr_write_generic,
3808 &spr_read_generic, &spr_write_generic,
3809 0x00000000);
3810 /* Memory management */
3811 #if !defined(CONFIG_USER_ONLY)
3812 env->nb_tlb = 64;
3813 env->nb_ways = 1;
3814 env->id_tlbs = 0;
3815 #endif
3816 init_excp_BookE(env);
3817 env->dcache_line_size = 32;
3818 env->icache_line_size = 32;
3819 /* XXX: TODO: allocate internal IRQ controller */
3820 }
3821
3822 /* Freescale 5xx cores (aka RCPU) */
3823 #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
3824 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3825 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3826 PPC_MFTB)
3827 #define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
3828 #define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
3829 #define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
3830 #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3831 #define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
3832 #define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3833 POWERPC_FLAG_BUS_CLK)
3834 #define check_pow_MPC5xx check_pow_none
3835
3836 __attribute__ (( unused ))
3837 static void init_proc_MPC5xx (CPUPPCState *env)
3838 {
3839 /* Time base */
3840 gen_tbl(env);
3841 gen_spr_5xx_8xx(env);
3842 gen_spr_5xx(env);
3843 init_excp_MPC5xx(env);
3844 env->dcache_line_size = 32;
3845 env->icache_line_size = 32;
3846 /* XXX: TODO: allocate internal IRQ controller */
3847 }
3848
3849 /* Freescale 8xx cores (aka PowerQUICC) */
3850 #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
3851 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3852 PPC_CACHE_ICBI | PPC_MFTB)
3853 #define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
3854 #define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
3855 #define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
3856 #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
3857 #define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
3858 #define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3859 POWERPC_FLAG_BUS_CLK)
3860 #define check_pow_MPC8xx check_pow_none
3861
3862 __attribute__ (( unused ))
3863 static void init_proc_MPC8xx (CPUPPCState *env)
3864 {
3865 /* Time base */
3866 gen_tbl(env);
3867 gen_spr_5xx_8xx(env);
3868 gen_spr_8xx(env);
3869 init_excp_MPC8xx(env);
3870 env->dcache_line_size = 32;
3871 env->icache_line_size = 32;
3872 /* XXX: TODO: allocate internal IRQ controller */
3873 }
3874
3875 /* Freescale 82xx cores (aka PowerQUICC-II) */
3876 /* PowerPC G2 */
3877 #define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3878 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
3879 PPC_FLOAT_STFIWX | \
3880 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
3881 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3882 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3883 PPC_SEGMENT | PPC_EXTERN)
3884 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3885 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3886 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3887 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3888 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3889 #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3890 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
3891 #define check_pow_G2 check_pow_hid0
3892
3893 static void init_proc_G2 (CPUPPCState *env)
3894 {
3895 gen_spr_ne_601(env);
3896 gen_spr_G2_755(env);
3897 gen_spr_G2(env);
3898 /* Time base */
3899 gen_tbl(env);
3900 /* External access control */
3901 /* XXX : not implemented */
3902 spr_register(env, SPR_EAR, "EAR",
3903 SPR_NOACCESS, SPR_NOACCESS,
3904 &spr_read_generic, &spr_write_generic,
3905 0x00000000);
3906 /* Hardware implementation register */
3907 /* XXX : not implemented */
3908 spr_register(env, SPR_HID0, "HID0",
3909 SPR_NOACCESS, SPR_NOACCESS,
3910 &spr_read_generic, &spr_write_generic,
3911 0x00000000);
3912 /* XXX : not implemented */
3913 spr_register(env, SPR_HID1, "HID1",
3914 SPR_NOACCESS, SPR_NOACCESS,
3915 &spr_read_generic, &spr_write_generic,
3916 0x00000000);
3917 /* XXX : not implemented */
3918 spr_register(env, SPR_HID2, "HID2",
3919 SPR_NOACCESS, SPR_NOACCESS,
3920 &spr_read_generic, &spr_write_generic,
3921 0x00000000);
3922 /* Memory management */
3923 gen_low_BATs(env);
3924 gen_high_BATs(env);
3925 gen_6xx_7xx_soft_tlb(env, 64, 2);
3926 init_excp_G2(env);
3927 env->dcache_line_size = 32;
3928 env->icache_line_size = 32;
3929 /* Allocate hardware IRQ controller */
3930 ppc6xx_irq_init(env);
3931 }
3932
3933 /* PowerPC G2LE */
3934 #define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3935 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
3936 PPC_FLOAT_STFIWX | \
3937 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
3938 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3939 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3940 PPC_SEGMENT | PPC_EXTERN)
3941 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3942 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3943 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3944 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
3945 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
3946 #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3947 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
3948 #define check_pow_G2LE check_pow_hid0
3949
3950 static void init_proc_G2LE (CPUPPCState *env)
3951 {
3952 gen_spr_ne_601(env);
3953 gen_spr_G2_755(env);
3954 gen_spr_G2(env);
3955 /* Time base */
3956 gen_tbl(env);
3957 /* External access control */
3958 /* XXX : not implemented */
3959 spr_register(env, SPR_EAR, "EAR",
3960 SPR_NOACCESS, SPR_NOACCESS,
3961 &spr_read_generic, &spr_write_generic,
3962 0x00000000);
3963 /* Hardware implementation register */
3964 /* XXX : not implemented */
3965 spr_register(env, SPR_HID0, "HID0",
3966 SPR_NOACCESS, SPR_NOACCESS,
3967 &spr_read_generic, &spr_write_generic,
3968 0x00000000);
3969 /* XXX : not implemented */
3970 spr_register(env, SPR_HID1, "HID1",
3971 SPR_NOACCESS, SPR_NOACCESS,
3972 &spr_read_generic, &spr_write_generic,
3973 0x00000000);
3974 /* XXX : not implemented */
3975 spr_register(env, SPR_HID2, "HID2",
3976 SPR_NOACCESS, SPR_NOACCESS,
3977 &spr_read_generic, &spr_write_generic,
3978 0x00000000);
3979 /* Memory management */
3980 gen_low_BATs(env);
3981 gen_high_BATs(env);
3982 gen_6xx_7xx_soft_tlb(env, 64, 2);
3983 init_excp_G2(env);
3984 env->dcache_line_size = 32;
3985 env->icache_line_size = 32;
3986 /* Allocate hardware IRQ controller */
3987 ppc6xx_irq_init(env);
3988 }
3989
3990 /* e200 core */
3991 /* XXX: unimplemented instructions:
3992 * dcblc
3993 * dcbtlst
3994 * dcbtstls
3995 * icblc
3996 * icbtls
3997 * tlbivax
3998 * all SPE multiply-accumulate instructions
3999 */
4000 #define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
4001 PPC_SPE | PPC_SPE_SINGLE | \
4002 PPC_WRTEE | PPC_RFDI | \
4003 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4004 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4005 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4006 PPC_BOOKE)
4007 #define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
4008 #define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE_FSL)
4009 #define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
4010 #define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
4011 #define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
4012 #define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4013 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4014 POWERPC_FLAG_BUS_CLK)
4015 #define check_pow_e200 check_pow_hid0
4016
4017 __attribute__ (( unused ))
4018 static void init_proc_e200 (CPUPPCState *env)
4019 {
4020 /* Time base */
4021 gen_tbl(env);
4022 gen_spr_BookE(env, 0x000000070000FFFFULL);
4023 /* XXX : not implemented */
4024 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4025 SPR_NOACCESS, SPR_NOACCESS,
4026 &spr_read_generic, &spr_write_generic,
4027 0x00000000);
4028 /* Memory management */
4029 gen_spr_BookE_FSL(env, 0x0000005D);
4030 /* XXX : not implemented */
4031 spr_register(env, SPR_HID0, "HID0",
4032 SPR_NOACCESS, SPR_NOACCESS,
4033 &spr_read_generic, &spr_write_generic,
4034 0x00000000);
4035 /* XXX : not implemented */
4036 spr_register(env, SPR_HID1, "HID1",
4037 SPR_NOACCESS, SPR_NOACCESS,
4038 &spr_read_generic, &spr_write_generic,
4039 0x00000000);
4040 /* XXX : not implemented */
4041 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4042 SPR_NOACCESS, SPR_NOACCESS,
4043 &spr_read_generic, &spr_write_generic,
4044 0x00000000);
4045 /* XXX : not implemented */
4046 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4047 SPR_NOACCESS, SPR_NOACCESS,
4048 &spr_read_generic, &spr_write_generic,
4049 0x00000000);
4050 /* XXX : not implemented */
4051 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4052 SPR_NOACCESS, SPR_NOACCESS,
4053 &spr_read_generic, &spr_write_generic,
4054 0x00000000);
4055 /* XXX : not implemented */
4056 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4057 SPR_NOACCESS, SPR_NOACCESS,
4058 &spr_read_generic, &spr_write_generic,
4059 0x00000000);
4060 /* XXX : not implemented */
4061 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4062 SPR_NOACCESS, SPR_NOACCESS,
4063 &spr_read_generic, &spr_write_generic,
4064 0x00000000);
4065 /* XXX : not implemented */
4066 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4067 SPR_NOACCESS, SPR_NOACCESS,
4068 &spr_read_generic, &spr_write_generic,
4069 0x00000000);
4070 /* XXX : not implemented */
4071 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4072 SPR_NOACCESS, SPR_NOACCESS,
4073 &spr_read_generic, &spr_write_generic,
4074 0x00000000);
4075 /* XXX : not implemented */
4076 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4077 SPR_NOACCESS, SPR_NOACCESS,
4078 &spr_read_generic, &spr_write_generic,
4079 0x00000000);
4080 /* XXX : not implemented */
4081 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4082 SPR_NOACCESS, SPR_NOACCESS,
4083 &spr_read_generic, &spr_write_generic,
4084 0x00000000);
4085 /* XXX : not implemented */
4086 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4087 SPR_NOACCESS, SPR_NOACCESS,
4088 &spr_read_generic, &spr_write_generic,
4089 0x00000000);
4090 /* XXX : not implemented */
4091 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4092 SPR_NOACCESS, SPR_NOACCESS,
4093 &spr_read_generic, &spr_write_generic,
4094 0x00000000);
4095 /* XXX : not implemented */
4096 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4097 SPR_NOACCESS, SPR_NOACCESS,
4098 &spr_read_generic, &spr_write_generic,
4099 0x00000000);
4100 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4101 SPR_NOACCESS, SPR_NOACCESS,
4102 &spr_read_generic, &spr_write_generic,
4103 0x00000000);
4104 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4105 SPR_NOACCESS, SPR_NOACCESS,
4106 &spr_read_generic, &spr_write_generic,
4107 0x00000000);
4108 #if !defined(CONFIG_USER_ONLY)
4109 env->nb_tlb = 64;
4110 env->nb_ways = 1;
4111 env->id_tlbs = 0;
4112 #endif
4113 init_excp_e200(env);
4114 env->dcache_line_size = 32;
4115 env->icache_line_size = 32;
4116 /* XXX: TODO: allocate internal IRQ controller */
4117 }
4118
4119 /* e300 core */
4120 #define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4121 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4122 PPC_FLOAT_STFIWX | \
4123 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4124 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4125 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4126 PPC_SEGMENT | PPC_EXTERN)
4127 #define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4128 #define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4129 #define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4130 #define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4131 #define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4132 #define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4133 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4134 #define check_pow_e300 check_pow_hid0
4135
4136 __attribute__ (( unused ))
4137 static void init_proc_e300 (CPUPPCState *env)
4138 {
4139 gen_spr_ne_601(env);
4140 gen_spr_603(env);
4141 /* Time base */
4142 gen_tbl(env);
4143 /* hardware implementation registers */
4144 /* XXX : not implemented */
4145 spr_register(env, SPR_HID0, "HID0",
4146 SPR_NOACCESS, SPR_NOACCESS,
4147 &spr_read_generic, &spr_write_generic,
4148 0x00000000);
4149 /* XXX : not implemented */
4150 spr_register(env, SPR_HID1, "HID1",
4151 SPR_NOACCESS, SPR_NOACCESS,
4152 &spr_read_generic, &spr_write_generic,
4153 0x00000000);
4154 /* Memory management */
4155 gen_low_BATs(env);
4156 gen_6xx_7xx_soft_tlb(env, 64, 2);
4157 init_excp_603(env);
4158 env->dcache_line_size = 32;
4159 env->icache_line_size = 32;
4160 /* Allocate hardware IRQ controller */
4161 ppc6xx_irq_init(env);
4162 }
4163
4164 /* e500v1 core */
4165 #define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4166 PPC_SPE | PPC_SPE_SINGLE | \
4167 PPC_WRTEE | PPC_RFDI | \
4168 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4169 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4170 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4171 PPC_BOOKE)
4172 #define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
4173 #define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE_FSL)
4174 #define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4175 #define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4176 #define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4177 #define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4178 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4179 POWERPC_FLAG_BUS_CLK)
4180 #define check_pow_e500v1 check_pow_hid0
4181 #define init_proc_e500v1 init_proc_e500
4182
4183 /* e500v2 core */
4184 #define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4185 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4186 PPC_WRTEE | PPC_RFDI | \
4187 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4188 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4189 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4190 PPC_BOOKE)
4191 #define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
4192 #define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE_FSL)
4193 #define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4194 #define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4195 #define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4196 #define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4197 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4198 POWERPC_FLAG_BUS_CLK)
4199 #define check_pow_e500v2 check_pow_hid0
4200 #define init_proc_e500v2 init_proc_e500
4201
4202 static void init_proc_e500 (CPUPPCState *env)
4203 {
4204 /* Time base */
4205 gen_tbl(env);
4206 gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4207 /* Processor identification */
4208 spr_register(env, SPR_BOOKE_PIR, "PIR",
4209 SPR_NOACCESS, SPR_NOACCESS,
4210 &spr_read_generic, &spr_write_pir,
4211 0x00000000);
4212 /* XXX : not implemented */
4213 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4214 SPR_NOACCESS, SPR_NOACCESS,
4215 &spr_read_generic, &spr_write_generic,
4216 0x00000000);
4217 /* Memory management */
4218 #if !defined(CONFIG_USER_ONLY)
4219 env->nb_pids = 3;
4220 #endif
4221 gen_spr_BookE_FSL(env, 0x0000005F);
4222 /* XXX : not implemented */
4223 spr_register(env, SPR_HID0, "HID0",
4224 SPR_NOACCESS, SPR_NOACCESS,
4225 &spr_read_generic, &spr_write_generic,
4226 0x00000000);
4227 /* XXX : not implemented */
4228 spr_register(env, SPR_HID1, "HID1",
4229 SPR_NOACCESS, SPR_NOACCESS,
4230 &spr_read_generic, &spr_write_generic,
4231 0x00000000);
4232 /* XXX : not implemented */
4233 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4234 SPR_NOACCESS, SPR_NOACCESS,
4235 &spr_read_generic, &spr_write_generic,
4236 0x00000000);
4237 /* XXX : not implemented */
4238 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4239 SPR_NOACCESS, SPR_NOACCESS,
4240 &spr_read_generic, &spr_write_generic,
4241 0x00000000);
4242 /* XXX : not implemented */
4243 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4244 SPR_NOACCESS, SPR_NOACCESS,
4245 &spr_read_generic, &spr_write_generic,
4246 0x00000000);
4247 /* XXX : not implemented */
4248 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4249 SPR_NOACCESS, SPR_NOACCESS,
4250 &spr_read_generic, &spr_write_generic,
4251 0x00000000);
4252 /* XXX : not implemented */
4253 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4254 SPR_NOACCESS, SPR_NOACCESS,
4255 &spr_read_generic, &spr_write_generic,
4256 0x00000000);
4257 /* XXX : not implemented */
4258 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4259 SPR_NOACCESS, SPR_NOACCESS,
4260 &spr_read_generic, &spr_write_generic,
4261 0x00000000);
4262 /* XXX : not implemented */
4263 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4264 SPR_NOACCESS, SPR_NOACCESS,
4265 &spr_read_generic, &spr_write_generic,
4266 0x00000000);
4267 /* XXX : not implemented */
4268 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4269 SPR_NOACCESS, SPR_NOACCESS,
4270 &spr_read_generic, &spr_write_generic,
4271 0x00000000);
4272 /* XXX : not implemented */
4273 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4274 SPR_NOACCESS, SPR_NOACCESS,
4275 &spr_read_generic, &spr_write_generic,
4276 0x00000000);
4277 /* XXX : not implemented */
4278 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4279 SPR_NOACCESS, SPR_NOACCESS,
4280 &spr_read_generic, &spr_write_generic,
4281 0x00000000);
4282 /* XXX : not implemented */
4283 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4284 SPR_NOACCESS, SPR_NOACCESS,
4285 &spr_read_generic, &spr_write_generic,
4286 0x00000000);
4287 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4288 SPR_NOACCESS, SPR_NOACCESS,
4289 &spr_read_generic, &spr_write_generic,
4290 0x00000000);
4291 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4292 SPR_NOACCESS, SPR_NOACCESS,
4293 &spr_read_generic, &spr_write_generic,
4294 0x00000000);
4295 #if !defined(CONFIG_USER_ONLY)
4296 env->nb_tlb = 64;
4297 env->nb_ways = 1;
4298 env->id_tlbs = 0;
4299 #endif
4300 init_excp_e200(env);
4301 env->dcache_line_size = 32;
4302 env->icache_line_size = 32;
4303 /* Allocate hardware IRQ controller */
4304 ppce500_irq_init(env);
4305 }
4306
4307 /* Non-embedded PowerPC */
4308
4309 /* POWER : same as 601, without mfmsr, mfsr */
4310 #if defined(TODO)
4311 #define POWERPC_INSNS_POWER (XXX_TODO)
4312 /* POWER RSC (from RAD6000) */
4313 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4314 #endif /* TODO */
4315
4316 /* PowerPC 601 */
4317 #define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4318 PPC_FLOAT | \
4319 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4320 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4321 PPC_SEGMENT | PPC_EXTERN)
4322 #define POWERPC_MSRM_601 (0x000000000000FD70ULL)
4323 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4324 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
4325 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4326 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
4327 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4328 #define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4329 #define check_pow_601 check_pow_none
4330
4331 static void init_proc_601 (CPUPPCState *env)
4332 {
4333 gen_spr_ne_601(env);
4334 gen_spr_601(env);
4335 /* Hardware implementation registers */
4336 /* XXX : not implemented */
4337 spr_register(env, SPR_HID0, "HID0",
4338 SPR_NOACCESS, SPR_NOACCESS,
4339 &spr_read_generic, &spr_write_hid0_601,
4340 0x80010080);
4341 /* XXX : not implemented */
4342 spr_register(env, SPR_HID1, "HID1",
4343 SPR_NOACCESS, SPR_NOACCESS,
4344 &spr_read_generic, &spr_write_generic,
4345 0x00000000);
4346 /* XXX : not implemented */
4347 spr_register(env, SPR_601_HID2, "HID2",
4348 SPR_NOACCESS, SPR_NOACCESS,
4349 &spr_read_generic, &spr_write_generic,
4350 0x00000000);
4351 /* XXX : not implemented */
4352 spr_register(env, SPR_601_HID5, "HID5",
4353 SPR_NOACCESS, SPR_NOACCESS,
4354 &spr_read_generic, &spr_write_generic,
4355 0x00000000);
4356 /* Memory management */
4357 init_excp_601(env);
4358 /* XXX: beware that dcache line size is 64
4359 * but dcbz uses 32 bytes "sectors"
4360 * XXX: this breaks clcs instruction !
4361 */
4362 env->dcache_line_size = 32;
4363 env->icache_line_size = 64;
4364 /* Allocate hardware IRQ controller */
4365 ppc6xx_irq_init(env);
4366 }
4367
4368 /* PowerPC 601v */
4369 #define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4370 PPC_FLOAT | \
4371 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4372 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4373 PPC_SEGMENT | PPC_EXTERN)
4374 #define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4375 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4376 #define POWERPC_MMU_601v (POWERPC_MMU_601)
4377 #define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4378 #define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4379 #define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4380 #define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4381 #define check_pow_601v check_pow_none
4382
4383 static void init_proc_601v (CPUPPCState *env)
4384 {
4385 init_proc_601(env);
4386 /* XXX : not implemented */
4387 spr_register(env, SPR_601_HID15, "HID15",
4388 SPR_NOACCESS, SPR_NOACCESS,
4389 &spr_read_generic, &spr_write_generic,
4390 0x00000000);
4391 }
4392
4393 /* PowerPC 602 */
4394 #define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4395 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4396 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4397 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4398 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4399 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4400 PPC_SEGMENT | PPC_602_SPEC)
4401 #define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4402 /* XXX: 602 MMU is quite specific. Should add a special case */
4403 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4404 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4405 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
4406 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
4407 #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4408 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4409 #define check_pow_602 check_pow_hid0
4410
4411 static void init_proc_602 (CPUPPCState *env)
4412 {
4413 gen_spr_ne_601(env);
4414 gen_spr_602(env);
4415 /* Time base */
4416 gen_tbl(env);
4417 /* hardware implementation registers */
4418 /* XXX : not implemented */
4419 spr_register(env, SPR_HID0, "HID0",
4420 SPR_NOACCESS, SPR_NOACCESS,
4421 &spr_read_generic, &spr_write_generic,
4422 0x00000000);
4423 /* XXX : not implemented */
4424 spr_register(env, SPR_HID1, "HID1",
4425 SPR_NOACCESS, SPR_NOACCESS,
4426 &spr_read_generic, &spr_write_generic,
4427 0x00000000);
4428 /* Memory management */
4429 gen_low_BATs(env);
4430 gen_6xx_7xx_soft_tlb(env, 64, 2);
4431 init_excp_602(env);
4432 env->dcache_line_size = 32;
4433 env->icache_line_size = 32;
4434 /* Allocate hardware IRQ controller */
4435 ppc6xx_irq_init(env);
4436 }
4437
4438 /* PowerPC 603 */
4439 #define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4440 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4441 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4442 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4443 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4444 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4445 PPC_SEGMENT | PPC_EXTERN)
4446 #define POWERPC_MSRM_603 (0x000000000007FF73ULL)
4447 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4448 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4449 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
4450 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
4451 #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4452 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4453 #define check_pow_603 check_pow_hid0
4454
4455 static void init_proc_603 (CPUPPCState *env)
4456 {
4457 gen_spr_ne_601(env);
4458 gen_spr_603(env);
4459 /* Time base */
4460 gen_tbl(env);
4461 /* hardware implementation registers */
4462 /* XXX : not implemented */
4463 spr_register(env, SPR_HID0, "HID0",
4464 SPR_NOACCESS, SPR_NOACCESS,
4465 &spr_read_generic, &spr_write_generic,
4466 0x00000000);
4467 /* XXX : not implemented */
4468 spr_register(env, SPR_HID1, "HID1",
4469 SPR_NOACCESS, SPR_NOACCESS,
4470 &spr_read_generic, &spr_write_generic,
4471 0x00000000);
4472 /* Memory management */
4473 gen_low_BATs(env);
4474 gen_6xx_7xx_soft_tlb(env, 64, 2);
4475 init_excp_603(env);
4476 env->dcache_line_size = 32;
4477 env->icache_line_size = 32;
4478 /* Allocate hardware IRQ controller */
4479 ppc6xx_irq_init(env);
4480 }
4481
4482 /* PowerPC 603e */
4483 #define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4484 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4485 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4486 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4487 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4488 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4489 PPC_SEGMENT | PPC_EXTERN)
4490 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4491 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4492 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4493 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
4494 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
4495 #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4496 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4497 #define check_pow_603E check_pow_hid0
4498
4499 static void init_proc_603E (CPUPPCState *env)
4500 {
4501 gen_spr_ne_601(env);
4502 gen_spr_603(env);
4503 /* Time base */
4504 gen_tbl(env);
4505 /* hardware implementation registers */
4506 /* XXX : not implemented */
4507 spr_register(env, SPR_HID0, "HID0",
4508 SPR_NOACCESS, SPR_NOACCESS,
4509 &spr_read_generic, &spr_write_generic,
4510 0x00000000);
4511 /* XXX : not implemented */
4512 spr_register(env, SPR_HID1, "HID1",
4513 SPR_NOACCESS, SPR_NOACCESS,
4514 &spr_read_generic, &spr_write_generic,
4515 0x00000000);
4516 /* XXX : not implemented */
4517 spr_register(env, SPR_IABR, "IABR",
4518 SPR_NOACCESS, SPR_NOACCESS,
4519 &spr_read_generic, &spr_write_generic,
4520 0x00000000);
4521 /* Memory management */
4522 gen_low_BATs(env);
4523 gen_6xx_7xx_soft_tlb(env, 64, 2);
4524 init_excp_603(env);
4525 env->dcache_line_size = 32;
4526 env->icache_line_size = 32;
4527 /* Allocate hardware IRQ controller */
4528 ppc6xx_irq_init(env);
4529 }
4530
4531 /* PowerPC 604 */
4532 #define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4533 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4534 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4535 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4536 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4537 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4538 PPC_SEGMENT | PPC_EXTERN)
4539 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4540 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
4541 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4542 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
4543 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
4544 #define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4545 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4546 #define check_pow_604 check_pow_nocheck
4547
4548 static void init_proc_604 (CPUPPCState *env)
4549 {
4550 gen_spr_ne_601(env);
4551 gen_spr_604(env);
4552 /* Time base */
4553 gen_tbl(env);
4554 /* Hardware implementation registers */
4555 /* XXX : not implemented */
4556 spr_register(env, SPR_HID0, "HID0",
4557 SPR_NOACCESS, SPR_NOACCESS,
4558 &spr_read_generic, &spr_write_generic,
4559 0x00000000);
4560 /* Memory management */
4561 gen_low_BATs(env);
4562 init_excp_604(env);
4563 env->dcache_line_size = 32;
4564 env->icache_line_size = 32;
4565 /* Allocate hardware IRQ controller */
4566 ppc6xx_irq_init(env);
4567 }
4568
4569 /* PowerPC 604E */
4570 #define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4571 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4572 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4573 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4574 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4575 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4576 PPC_SEGMENT | PPC_EXTERN)
4577 #define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4578 #define POWERPC_MMU_604E (POWERPC_MMU_32B)
4579 #define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4580 #define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4581 #define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4582 #define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4583 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4584 #define check_pow_604E check_pow_nocheck
4585
4586 static void init_proc_604E (CPUPPCState *env)
4587 {
4588 gen_spr_ne_601(env);
4589 gen_spr_604(env);
4590 /* XXX : not implemented */
4591 spr_register(env, SPR_MMCR1, "MMCR1",
4592 SPR_NOACCESS, SPR_NOACCESS,
4593 &spr_read_generic, &spr_write_generic,
4594 0x00000000);
4595 /* XXX : not implemented */
4596 spr_register(env, SPR_PMC3, "PMC3",
4597 SPR_NOACCESS, SPR_NOACCESS,
4598 &spr_read_generic, &spr_write_generic,
4599 0x00000000);
4600 /* XXX : not implemented */
4601 spr_register(env, SPR_PMC4, "PMC4",
4602 SPR_NOACCESS, SPR_NOACCESS,
4603 &spr_read_generic, &spr_write_generic,
4604 0x00000000);
4605 /* Time base */
4606 gen_tbl(env);
4607 /* Hardware implementation registers */
4608 /* XXX : not implemented */
4609 spr_register(env, SPR_HID0, "HID0",
4610 SPR_NOACCESS, SPR_NOACCESS,
4611 &spr_read_generic, &spr_write_generic,
4612 0x00000000);
4613 /* XXX : not implemented */
4614 spr_register(env, SPR_HID1, "HID1",
4615 SPR_NOACCESS, SPR_NOACCESS,
4616 &spr_read_generic, &spr_write_generic,
4617 0x00000000);
4618 /* Memory management */
4619 gen_low_BATs(env);
4620 init_excp_604(env);
4621 env->dcache_line_size = 32;
4622 env->icache_line_size = 32;
4623 /* Allocate hardware IRQ controller */
4624 ppc6xx_irq_init(env);
4625 }
4626
4627 /* PowerPC 740 */
4628 #define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4629 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4630 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4631 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4632 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4633 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4634 PPC_SEGMENT | PPC_EXTERN)
4635 #define POWERPC_MSRM_740 (0x000000000005FF77ULL)
4636 #define POWERPC_MMU_740 (POWERPC_MMU_32B)
4637 #define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
4638 #define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
4639 #define POWERPC_BFDM_740 (bfd_mach_ppc_750)
4640 #define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4641 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4642 #define check_pow_740 check_pow_hid0
4643
4644 static void init_proc_740 (CPUPPCState *env)
4645 {
4646 gen_spr_ne_601(env);
4647 gen_spr_7xx(env);
4648 /* Time base */
4649 gen_tbl(env);
4650 /* Thermal management */
4651 gen_spr_thrm(env);
4652 /* Hardware implementation registers */
4653 /* XXX : not implemented */
4654 spr_register(env, SPR_HID0, "HID0",
4655 SPR_NOACCESS, SPR_NOACCESS,
4656 &spr_read_generic, &spr_write_generic,
4657 0x00000000);
4658 /* XXX : not implemented */
4659 spr_register(env, SPR_HID1, "HID1",
4660 SPR_NOACCESS, SPR_NOACCESS,
4661 &spr_read_generic, &spr_write_generic,
4662 0x00000000);
4663 /* Memory management */
4664 gen_low_BATs(env);
4665 init_excp_7x0(env);
4666 env->dcache_line_size = 32;
4667 env->icache_line_size = 32;
4668 /* Allocate hardware IRQ controller */
4669 ppc6xx_irq_init(env);
4670 }
4671
4672 /* PowerPC 750 */
4673 #define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4674 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4675 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4676 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4677 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4678 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4679 PPC_SEGMENT | PPC_EXTERN)
4680 #define POWERPC_MSRM_750 (0x000000000005FF77ULL)
4681 #define POWERPC_MMU_750 (POWERPC_MMU_32B)
4682 #define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
4683 #define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
4684 #define POWERPC_BFDM_750 (bfd_mach_ppc_750)
4685 #define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4686 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4687 #define check_pow_750 check_pow_hid0
4688
4689 static void init_proc_750 (CPUPPCState *env)
4690 {
4691 gen_spr_ne_601(env);
4692 gen_spr_7xx(env);
4693 /* XXX : not implemented */
4694 spr_register(env, SPR_L2CR, "L2CR",
4695 SPR_NOACCESS, SPR_NOACCESS,
4696 &spr_read_generic, &spr_write_generic,
4697 0x00000000);
4698 /* Time base */
4699 gen_tbl(env);
4700 /* Thermal management */
4701 gen_spr_thrm(env);
4702 /* Hardware implementation registers */
4703 /* XXX : not implemented */
4704 spr_register(env, SPR_HID0, "HID0",
4705 SPR_NOACCESS, SPR_NOACCESS,
4706 &spr_read_generic, &spr_write_generic,
4707 0x00000000);
4708 /* XXX : not implemented */
4709 spr_register(env, SPR_HID1, "HID1",
4710 SPR_NOACCESS, SPR_NOACCESS,
4711 &spr_read_generic, &spr_write_generic,
4712 0x00000000);
4713 /* Memory management */
4714 gen_low_BATs(env);
4715 /* XXX: high BATs are also present but are known to be bugged on
4716 * die version 1.x
4717 */
4718 init_excp_7x0(env);
4719 env->dcache_line_size = 32;
4720 env->icache_line_size = 32;
4721 /* Allocate hardware IRQ controller */
4722 ppc6xx_irq_init(env);
4723 }
4724
4725 /* PowerPC 750 CL */
4726 /* XXX: not implemented:
4727 * cache lock instructions:
4728 * dcbz_l
4729 * floating point paired instructions
4730 * psq_lux
4731 * psq_lx
4732 * psq_stux
4733 * psq_stx
4734 * ps_abs
4735 * ps_add
4736 * ps_cmpo0
4737 * ps_cmpo1
4738 * ps_cmpu0
4739 * ps_cmpu1
4740 * ps_div
4741 * ps_madd
4742 * ps_madds0
4743 * ps_madds1
4744 * ps_merge00
4745 * ps_merge01
4746 * ps_merge10
4747 * ps_merge11
4748 * ps_mr
4749 * ps_msub
4750 * ps_mul
4751 * ps_muls0
4752 * ps_muls1
4753 * ps_nabs
4754 * ps_neg
4755 * ps_nmadd
4756 * ps_nmsub
4757 * ps_res
4758 * ps_rsqrte
4759 * ps_sel
4760 * ps_sub
4761 * ps_sum0
4762 * ps_sum1
4763 */
4764 #define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4765 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4766 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4767 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4768 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4769 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4770 PPC_SEGMENT | PPC_EXTERN)
4771 #define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
4772 #define POWERPC_MMU_750cl (POWERPC_MMU_32B)
4773 #define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
4774 #define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
4775 #define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
4776 #define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4777 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4778 #define check_pow_750cl check_pow_hid0
4779
4780 static void init_proc_750cl (CPUPPCState *env)
4781 {
4782 gen_spr_ne_601(env);
4783 gen_spr_7xx(env);
4784 /* XXX : not implemented */
4785 spr_register(env, SPR_L2CR, "L2CR",
4786 SPR_NOACCESS, SPR_NOACCESS,
4787 &spr_read_generic, &spr_write_generic,
4788 0x00000000);
4789 /* Time base */
4790 gen_tbl(env);
4791 /* Thermal management */
4792 /* Those registers are fake on 750CL */
4793 spr_register(env, SPR_THRM1, "THRM1",
4794 SPR_NOACCESS, SPR_NOACCESS,
4795 &spr_read_generic, &spr_write_generic,
4796 0x00000000);
4797 spr_register(env, SPR_THRM2, "THRM2",
4798 SPR_NOACCESS, SPR_NOACCESS,
4799 &spr_read_generic, &spr_write_generic,
4800 0x00000000);
4801 spr_register(env, SPR_THRM3, "THRM3",
4802 SPR_NOACCESS, SPR_NOACCESS,
4803 &spr_read_generic, &spr_write_generic,
4804 0x00000000);
4805 /* XXX: not implemented */
4806 spr_register(env, SPR_750_TDCL, "TDCL",
4807 SPR_NOACCESS, SPR_NOACCESS,
4808 &spr_read_generic, &spr_write_generic,
4809 0x00000000);
4810 spr_register(env, SPR_750_TDCH, "TDCH",
4811 SPR_NOACCESS, SPR_NOACCESS,
4812 &spr_read_generic, &spr_write_generic,
4813 0x00000000);
4814 /* DMA */
4815 /* XXX : not implemented */
4816 spr_register(env, SPR_750_WPAR, "WPAR",
4817 SPR_NOACCESS, SPR_NOACCESS,
4818 &spr_read_generic, &spr_write_generic,
4819 0x00000000);
4820 spr_register(env, SPR_750_DMAL, "DMAL",
4821 SPR_NOACCESS, SPR_NOACCESS,
4822 &spr_read_generic, &spr_write_generic,
4823 0x00000000);
4824 spr_register(env, SPR_750_DMAU, "DMAU",
4825 SPR_NOACCESS, SPR_NOACCESS,
4826 &spr_read_generic, &spr_write_generic,
4827 0x00000000);
4828 /* Hardware implementation registers */
4829 /* XXX : not implemented */
4830 spr_register(env, SPR_HID0, "HID0",
4831 SPR_NOACCESS, SPR_NOACCESS,
4832 &spr_read_generic, &spr_write_generic,
4833 0x00000000);
4834 /* XXX : not implemented */
4835 spr_register(env, SPR_HID1, "HID1",
4836 SPR_NOACCESS, SPR_NOACCESS,
4837 &spr_read_generic, &spr_write_generic,
4838 0x00000000);
4839 /* XXX : not implemented */
4840 spr_register(env, SPR_750CL_HID2, "HID2",
4841 SPR_NOACCESS, SPR_NOACCESS,
4842 &spr_read_generic, &spr_write_generic,
4843 0x00000000);
4844 /* XXX : not implemented */
4845 spr_register(env, SPR_750CL_HID4, "HID4",
4846 SPR_NOACCESS, SPR_NOACCESS,
4847 &spr_read_generic, &spr_write_generic,
4848 0x00000000);
4849 /* Quantization registers */
4850 /* XXX : not implemented */
4851 spr_register(env, SPR_750_GQR0, "GQR0",
4852 SPR_NOACCESS, SPR_NOACCESS,
4853 &spr_read_generic, &spr_write_generic,
4854 0x00000000);
4855 /* XXX : not implemented */
4856 spr_register(env, SPR_750_GQR1, "GQR1",
4857 SPR_NOACCESS, SPR_NOACCESS,
4858 &spr_read_generic, &spr_write_generic,
4859 0x00000000);
4860 /* XXX : not implemented */
4861 spr_register(env, SPR_750_GQR2, "GQR2",
4862 SPR_NOACCESS, SPR_NOACCESS,
4863 &spr_read_generic, &spr_write_generic,
4864 0x00000000);
4865 /* XXX : not implemented */
4866 spr_register(env, SPR_750_GQR3, "GQR3",
4867 SPR_NOACCESS, SPR_NOACCESS,
4868 &spr_read_generic, &spr_write_generic,
4869 0x00000000);
4870 /* XXX : not implemented */
4871 spr_register(env, SPR_750_GQR4, "GQR4",
4872 SPR_NOACCESS, SPR_NOACCESS,
4873 &spr_read_generic, &spr_write_generic,
4874 0x00000000);
4875 /* XXX : not implemented */
4876 spr_register(env, SPR_750_GQR5, "GQR5",
4877 SPR_NOACCESS, SPR_NOACCESS,
4878 &spr_read_generic, &spr_write_generic,
4879 0x00000000);
4880 /* XXX : not implemented */
4881 spr_register(env, SPR_750_GQR6, "GQR6",
4882 SPR_NOACCESS, SPR_NOACCESS,
4883 &spr_read_generic, &spr_write_generic,
4884 0x00000000);
4885 /* XXX : not implemented */
4886 spr_register(env, SPR_750_GQR7, "GQR7",
4887 SPR_NOACCESS, SPR_NOACCESS,
4888 &spr_read_generic, &spr_write_generic,
4889 0x00000000);
4890 /* Memory management */
4891 gen_low_BATs(env);
4892 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
4893 gen_high_BATs(env);
4894 init_excp_750cl(env);
4895 env->dcache_line_size = 32;
4896 env->icache_line_size = 32;
4897 /* Allocate hardware IRQ controller */
4898 ppc6xx_irq_init(env);
4899 }
4900
4901 /* PowerPC 750CX */
4902 #define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4903 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4904 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4905 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4906 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4907 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4908 PPC_SEGMENT | PPC_EXTERN)
4909 #define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
4910 #define POWERPC_MMU_750cx (POWERPC_MMU_32B)
4911 #define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
4912 #define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
4913 #define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
4914 #define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4915 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4916 #define check_pow_750cx check_pow_hid0
4917
4918 static void init_proc_750cx (CPUPPCState *env)
4919 {
4920 gen_spr_ne_601(env);
4921 gen_spr_7xx(env);
4922 /* XXX : not implemented */
4923 spr_register(env, SPR_L2CR, "L2CR",
4924 SPR_NOACCESS, SPR_NOACCESS,
4925 &spr_read_generic, &spr_write_generic,
4926 0x00000000);
4927 /* Time base */
4928 gen_tbl(env);
4929 /* Thermal management */
4930 gen_spr_thrm(env);
4931 /* This register is not implemented but is present for compatibility */
4932 spr_register(env, SPR_SDA, "SDA",
4933 SPR_NOACCESS, SPR_NOACCESS,
4934 &spr_read_generic, &spr_write_generic,
4935 0x00000000);
4936 /* Hardware implementation registers */
4937 /* XXX : not implemented */
4938 spr_register(env, SPR_HID0, "HID0",
4939 SPR_NOACCESS, SPR_NOACCESS,
4940 &spr_read_generic, &spr_write_generic,
4941 0x00000000);
4942 /* XXX : not implemented */
4943 spr_register(env, SPR_HID1, "HID1",
4944 SPR_NOACCESS, SPR_NOACCESS,
4945 &spr_read_generic, &spr_write_generic,
4946 0x00000000);
4947 /* Memory management */
4948 gen_low_BATs(env);
4949 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
4950 gen_high_BATs(env);
4951 init_excp_750cx(env);
4952 env->dcache_line_size = 32;
4953 env->icache_line_size = 32;
4954 /* Allocate hardware IRQ controller */
4955 ppc6xx_irq_init(env);
4956 }
4957
4958 /* PowerPC 750FX */
4959 #define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4960 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4961 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4962 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4963 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4964 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4965 PPC_SEGMENT | PPC_EXTERN)
4966 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
4967 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
4968 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
4969 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
4970 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
4971 #define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4972 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4973 #define check_pow_750fx check_pow_hid0
4974
4975 static void init_proc_750fx (CPUPPCState *env)
4976 {
4977 gen_spr_ne_601(env);
4978 gen_spr_7xx(env);
4979 /* XXX : not implemented */
4980 spr_register(env, SPR_L2CR, "L2CR",
4981 SPR_NOACCESS, SPR_NOACCESS,
4982 &spr_read_generic, &spr_write_generic,
4983 0x00000000);
4984 /* Time base */
4985 gen_tbl(env);
4986 /* Thermal management */
4987 gen_spr_thrm(env);
4988 /* XXX : not implemented */
4989 spr_register(env, SPR_750_THRM4, "THRM4",
4990 SPR_NOACCESS, SPR_NOACCESS,
4991 &spr_read_generic, &spr_write_generic,
4992 0x00000000);
4993 /* Hardware implementation registers */
4994 /* XXX : not implemented */
4995 spr_register(env, SPR_HID0, "HID0",
4996 SPR_NOACCESS, SPR_NOACCESS,
4997 &spr_read_generic, &spr_write_generic,
4998 0x00000000);
4999 /* XXX : not implemented */
5000 spr_register(env, SPR_HID1, "HID1",
5001 SPR_NOACCESS, SPR_NOACCESS,
5002 &spr_read_generic, &spr_write_generic,
5003 0x00000000);
5004 /* XXX : not implemented */
5005 spr_register(env, SPR_750FX_HID2, "HID2",
5006 SPR_NOACCESS, SPR_NOACCESS,
5007 &spr_read_generic, &spr_write_generic,
5008 0x00000000);
5009 /* Memory management */
5010 gen_low_BATs(env);
5011 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5012 gen_high_BATs(env);
5013 init_excp_7x0(env);
5014 env->dcache_line_size = 32;
5015 env->icache_line_size = 32;
5016 /* Allocate hardware IRQ controller */
5017 ppc6xx_irq_init(env);
5018 }
5019
5020 /* PowerPC 750GX */
5021 #define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5022 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5023 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5024 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5025 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5026 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5027 PPC_SEGMENT | PPC_EXTERN)
5028 #define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5029 #define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5030 #define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5031 #define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5032 #define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5033 #define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5034 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5035 #define check_pow_750gx check_pow_hid0
5036
5037 static void init_proc_750gx (CPUPPCState *env)
5038 {
5039 gen_spr_ne_601(env);
5040 gen_spr_7xx(env);
5041 /* XXX : not implemented (XXX: different from 750fx) */
5042 spr_register(env, SPR_L2CR, "L2CR",
5043 SPR_NOACCESS, SPR_NOACCESS,
5044 &spr_read_generic, &spr_write_generic,
5045 0x00000000);
5046 /* Time base */
5047 gen_tbl(env);
5048 /* Thermal management */
5049 gen_spr_thrm(env);
5050 /* XXX : not implemented */
5051 spr_register(env, SPR_750_THRM4, "THRM4",
5052 SPR_NOACCESS, SPR_NOACCESS,
5053 &spr_read_generic, &spr_write_generic,
5054 0x00000000);
5055 /* Hardware implementation registers */
5056 /* XXX : not implemented (XXX: different from 750fx) */
5057 spr_register(env, SPR_HID0, "HID0",
5058 SPR_NOACCESS, SPR_NOACCESS,
5059 &spr_read_generic, &spr_write_generic,
5060 0x00000000);
5061 /* XXX : not implemented */
5062 spr_register(env, SPR_HID1, "HID1",
5063 SPR_NOACCESS, SPR_NOACCESS,
5064 &spr_read_generic, &spr_write_generic,
5065 0x00000000);
5066 /* XXX : not implemented (XXX: different from 750fx) */
5067 spr_register(env, SPR_750FX_HID2, "HID2",
5068 SPR_NOACCESS, SPR_NOACCESS,
5069 &spr_read_generic, &spr_write_generic,
5070 0x00000000);
5071 /* Memory management */
5072 gen_low_BATs(env);
5073 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5074 gen_high_BATs(env);
5075 init_excp_7x0(env);
5076 env->dcache_line_size = 32;
5077 env->icache_line_size = 32;
5078 /* Allocate hardware IRQ controller */
5079 ppc6xx_irq_init(env);
5080 }
5081
5082 /* PowerPC 745 */
5083 #define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5084 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5085 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5086 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5087 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5088 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5089 PPC_SEGMENT | PPC_EXTERN)
5090 #define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5091 #define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5092 #define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5093 #define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5094 #define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5095 #define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5096 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5097 #define check_pow_745 check_pow_hid0
5098
5099 static void init_proc_745 (CPUPPCState *env)
5100 {
5101 gen_spr_ne_601(env);
5102 gen_spr_7xx(env);
5103 gen_spr_G2_755(env);
5104 /* Time base */
5105 gen_tbl(env);
5106 /* Thermal management */
5107 gen_spr_thrm(env);
5108 /* Hardware implementation registers */
5109 /* XXX : not implemented */
5110 spr_register(env, SPR_HID0, "HID0",
5111 SPR_NOACCESS, SPR_NOACCESS,
5112 &spr_read_generic, &spr_write_generic,
5113 0x00000000);
5114 /* XXX : not implemented */
5115 spr_register(env, SPR_HID1, "HID1",
5116 SPR_NOACCESS, SPR_NOACCESS,
5117 &spr_read_generic, &spr_write_generic,
5118 0x00000000);
5119 /* XXX : not implemented */
5120 spr_register(env, SPR_HID2, "HID2",
5121 SPR_NOACCESS, SPR_NOACCESS,
5122 &spr_read_generic, &spr_write_generic,
5123 0x00000000);
5124 /* Memory management */
5125 gen_low_BATs(env);
5126 gen_high_BATs(env);
5127 gen_6xx_7xx_soft_tlb(env, 64, 2);
5128 init_excp_7x5(env);
5129 env->dcache_line_size = 32;
5130 env->icache_line_size = 32;
5131 /* Allocate hardware IRQ controller */
5132 ppc6xx_irq_init(env);
5133 }
5134
5135 /* PowerPC 755 */
5136 #define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5137 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5138 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5139 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5140 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5141 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5142 PPC_SEGMENT | PPC_EXTERN)
5143 #define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5144 #define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5145 #define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5146 #define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5147 #define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5148 #define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5149 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5150 #define check_pow_755 check_pow_hid0
5151
5152 static void init_proc_755 (CPUPPCState *env)
5153 {
5154 gen_spr_ne_601(env);
5155 gen_spr_7xx(env);
5156 gen_spr_G2_755(env);
5157 /* Time base */
5158 gen_tbl(env);
5159 /* L2 cache control */
5160 /* XXX : not implemented */
5161 spr_register(env, SPR_L2CR, "L2CR",
5162 SPR_NOACCESS, SPR_NOACCESS,
5163 &spr_read_generic, &spr_write_generic,
5164 0x00000000);
5165 /* XXX : not implemented */
5166 spr_register(env, SPR_L2PMCR, "L2PMCR",
5167 SPR_NOACCESS, SPR_NOACCESS,
5168 &spr_read_generic, &spr_write_generic,
5169 0x00000000);
5170 /* Thermal management */
5171 gen_spr_thrm(env);
5172 /* Hardware implementation registers */
5173 /* XXX : not implemented */
5174 spr_register(env, SPR_HID0, "HID0",
5175 SPR_NOACCESS, SPR_NOACCESS,
5176 &spr_read_generic, &spr_write_generic,
5177 0x00000000);
5178 /* XXX : not implemented */
5179 spr_register(env, SPR_HID1, "HID1",
5180 SPR_NOACCESS, SPR_NOACCESS,
5181 &spr_read_generic, &spr_write_generic,
5182 0x00000000);
5183 /* XXX : not implemented */
5184 spr_register(env, SPR_HID2, "HID2",
5185 SPR_NOACCESS, SPR_NOACCESS,
5186 &spr_read_generic, &spr_write_generic,
5187 0x00000000);
5188 /* Memory management */
5189 gen_low_BATs(env);
5190 gen_high_BATs(env);
5191 gen_6xx_7xx_soft_tlb(env, 64, 2);
5192 init_excp_7x5(env);
5193 env->dcache_line_size = 32;
5194 env->icache_line_size = 32;
5195 /* Allocate hardware IRQ controller */
5196 ppc6xx_irq_init(env);
5197 }
5198
5199 /* PowerPC 7400 (aka G4) */
5200 #define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5201 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5202 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5203 PPC_FLOAT_STFIWX | \
5204 PPC_CACHE | PPC_CACHE_ICBI | \
5205 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5206 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5207 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5208 PPC_MEM_TLBIA | \
5209 PPC_SEGMENT | PPC_EXTERN | \
5210 PPC_ALTIVEC)
5211 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5212 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5213 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5214 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
5215 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
5216 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5217 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5218 POWERPC_FLAG_BUS_CLK)
5219 #define check_pow_7400 check_pow_hid0_74xx
5220
5221 static void init_proc_7400 (CPUPPCState *env)
5222 {
5223 gen_spr_ne_601(env);
5224 gen_spr_7xx(env);
5225 /* Time base */
5226 gen_tbl(env);
5227 /* 74xx specific SPR */
5228 gen_spr_74xx(env);
5229 /* XXX : not implemented */
5230 spr_register(env, SPR_UBAMR, "UBAMR",
5231 &spr_read_ureg, SPR_NOACCESS,
5232 &spr_read_ureg, SPR_NOACCESS,
5233 0x00000000);
5234 /* XXX: this seems not implemented on all revisions. */
5235 /* XXX : not implemented */
5236 spr_register(env, SPR_MSSCR1, "MSSCR1",
5237 SPR_NOACCESS, SPR_NOACCESS,
5238 &spr_read_generic, &spr_write_generic,
5239 0x00000000);
5240 /* Thermal management */
5241 gen_spr_thrm(env);
5242 /* Memory management */
5243 gen_low_BATs(env);
5244 init_excp_7400(env);
5245 env->dcache_line_size = 32;
5246 env->icache_line_size = 32;
5247 /* Allocate hardware IRQ controller */
5248 ppc6xx_irq_init(env);
5249 }
5250
5251 /* PowerPC 7410 (aka G4) */
5252 #define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5253 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5254 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5255 PPC_FLOAT_STFIWX | \
5256 PPC_CACHE | PPC_CACHE_ICBI | \
5257 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5258 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5259 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5260 PPC_MEM_TLBIA | \
5261 PPC_SEGMENT | PPC_EXTERN | \
5262 PPC_ALTIVEC)
5263 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5264 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5265 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5266 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
5267 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
5268 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5269 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5270 POWERPC_FLAG_BUS_CLK)
5271 #define check_pow_7410 check_pow_hid0_74xx
5272
5273 static void init_proc_7410 (CPUPPCState *env)
5274 {
5275 gen_spr_ne_601(env);
5276 gen_spr_7xx(env);
5277 /* Time base */
5278 gen_tbl(env);
5279 /* 74xx specific SPR */
5280 gen_spr_74xx(env);
5281 /* XXX : not implemented */
5282 spr_register(env, SPR_UBAMR, "UBAMR",
5283 &spr_read_ureg, SPR_NOACCESS,
5284 &spr_read_ureg, SPR_NOACCESS,
5285 0x00000000);
5286 /* Thermal management */
5287 gen_spr_thrm(env);
5288 /* L2PMCR */
5289 /* XXX : not implemented */
5290 spr_register(env, SPR_L2PMCR, "L2PMCR",
5291 SPR_NOACCESS, SPR_NOACCESS,
5292 &spr_read_generic, &spr_write_generic,
5293 0x00000000);
5294 /* LDSTDB */
5295 /* XXX : not implemented */
5296 spr_register(env, SPR_LDSTDB, "LDSTDB",
5297 SPR_NOACCESS, SPR_NOACCESS,
5298 &spr_read_generic, &spr_write_generic,
5299 0x00000000);
5300 /* Memory management */
5301 gen_low_BATs(env);
5302 init_excp_7400(env);
5303 env->dcache_line_size = 32;
5304 env->icache_line_size = 32;
5305 /* Allocate hardware IRQ controller */
5306 ppc6xx_irq_init(env);
5307 }
5308
5309 /* PowerPC 7440 (aka G4) */
5310 #define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5311 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5312 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5313 PPC_FLOAT_STFIWX | \
5314 PPC_CACHE | PPC_CACHE_ICBI | \
5315 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5316 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5317 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5318 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5319 PPC_SEGMENT | PPC_EXTERN | \
5320 PPC_ALTIVEC)
5321 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5322 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5323 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5324 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
5325 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
5326 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5327 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5328 POWERPC_FLAG_BUS_CLK)
5329 #define check_pow_7440 check_pow_hid0_74xx
5330
5331 __attribute__ (( unused ))
5332 static void init_proc_7440 (CPUPPCState *env)
5333 {
5334 gen_spr_ne_601(env);
5335 gen_spr_7xx(env);
5336 /* Time base */
5337 gen_tbl(env);
5338 /* 74xx specific SPR */
5339 gen_spr_74xx(env);
5340 /* XXX : not implemented */
5341 spr_register(env, SPR_UBAMR, "UBAMR",
5342 &spr_read_ureg, SPR_NOACCESS,
5343 &spr_read_ureg, SPR_NOACCESS,
5344 0x00000000);
5345 /* LDSTCR */
5346 /* XXX : not implemented */
5347 spr_register(env, SPR_LDSTCR, "LDSTCR",
5348 SPR_NOACCESS, SPR_NOACCESS,
5349 &spr_read_generic, &spr_write_generic,
5350 0x00000000);
5351 /* ICTRL */
5352 /* XXX : not implemented */
5353 spr_register(env, SPR_ICTRL, "ICTRL",
5354 SPR_NOACCESS, SPR_NOACCESS,
5355 &spr_read_generic, &spr_write_generic,
5356 0x00000000);
5357 /* MSSSR0 */
5358 /* XXX : not implemented */
5359 spr_register(env, SPR_MSSSR0, "MSSSR0",
5360 SPR_NOACCESS, SPR_NOACCESS,
5361 &spr_read_generic, &spr_write_generic,
5362 0x00000000);
5363 /* PMC */
5364 /* XXX : not implemented */
5365 spr_register(env, SPR_PMC5, "PMC5",
5366 SPR_NOACCESS, SPR_NOACCESS,
5367 &spr_read_generic, &spr_write_generic,
5368 0x00000000);
5369 /* XXX : not implemented */
5370 spr_register(env, SPR_UPMC5, "UPMC5",
5371 &spr_read_ureg, SPR_NOACCESS,
5372 &spr_read_ureg, SPR_NOACCESS,
5373 0x00000000);
5374 /* XXX : not implemented */
5375 spr_register(env, SPR_PMC6, "PMC6",
5376 SPR_NOACCESS, SPR_NOACCESS,
5377 &spr_read_generic, &spr_write_generic,
5378 0x00000000);
5379 /* XXX : not implemented */
5380 spr_register(env, SPR_UPMC6, "UPMC6",
5381 &spr_read_ureg, SPR_NOACCESS,
5382 &spr_read_ureg, SPR_NOACCESS,
5383 0x00000000);
5384 /* Memory management */
5385 gen_low_BATs(env);
5386 gen_74xx_soft_tlb(env, 128, 2);
5387 init_excp_7450(env);
5388 env->dcache_line_size = 32;
5389 env->icache_line_size = 32;
5390 /* Allocate hardware IRQ controller */
5391 ppc6xx_irq_init(env);
5392 }
5393
5394 /* PowerPC 7450 (aka G4) */
5395 #define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5396 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5397 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5398 PPC_FLOAT_STFIWX | \
5399 PPC_CACHE | PPC_CACHE_ICBI | \
5400 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5401 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5402 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5403 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5404 PPC_SEGMENT | PPC_EXTERN | \
5405 PPC_ALTIVEC)
5406 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5407 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5408 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5409 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
5410 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
5411 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5412 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5413 POWERPC_FLAG_BUS_CLK)
5414 #define check_pow_7450 check_pow_hid0_74xx
5415
5416 __attribute__ (( unused ))
5417 static void init_proc_7450 (CPUPPCState *env)
5418 {
5419 gen_spr_ne_601(env);
5420 gen_spr_7xx(env);
5421 /* Time base */
5422 gen_tbl(env);
5423 /* 74xx specific SPR */
5424 gen_spr_74xx(env);
5425 /* Level 3 cache control */
5426 gen_l3_ctrl(env);
5427 /* L3ITCR1 */
5428 /* XXX : not implemented */
5429 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5430 SPR_NOACCESS, SPR_NOACCESS,
5431 &spr_read_generic, &spr_write_generic,
5432 0x00000000);
5433 /* L3ITCR2 */
5434 /* XXX : not implemented */
5435 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5436 SPR_NOACCESS, SPR_NOACCESS,
5437 &spr_read_generic, &spr_write_generic,
5438 0x00000000);
5439 /* L3ITCR3 */
5440 /* XXX : not implemented */
5441 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5442 SPR_NOACCESS, SPR_NOACCESS,
5443 &spr_read_generic, &spr_write_generic,
5444 0x00000000);
5445 /* L3OHCR */
5446 /* XXX : not implemented */
5447 spr_register(env, SPR_L3OHCR, "L3OHCR",
5448 SPR_NOACCESS, SPR_NOACCESS,
5449 &spr_read_generic, &spr_write_generic,
5450 0x00000000);
5451 /* XXX : not implemented */
5452 spr_register(env, SPR_UBAMR, "UBAMR",
5453 &spr_read_ureg, SPR_NOACCESS,
5454 &spr_read_ureg, SPR_NOACCESS,
5455 0x00000000);
5456 /* LDSTCR */
5457 /* XXX : not implemented */
5458 spr_register(env, SPR_LDSTCR, "LDSTCR",
5459 SPR_NOACCESS, SPR_NOACCESS,
5460 &spr_read_generic, &spr_write_generic,
5461 0x00000000);
5462 /* ICTRL */
5463 /* XXX : not implemented */
5464 spr_register(env, SPR_ICTRL, "ICTRL",
5465 SPR_NOACCESS, SPR_NOACCESS,
5466 &spr_read_generic, &spr_write_generic,
5467 0x00000000);
5468 /* MSSSR0 */
5469 /* XXX : not implemented */
5470 spr_register(env, SPR_MSSSR0, "MSSSR0",
5471 SPR_NOACCESS, SPR_NOACCESS,
5472 &spr_read_generic, &spr_write_generic,
5473 0x00000000);
5474 /* PMC */
5475 /* XXX : not implemented */
5476 spr_register(env, SPR_PMC5, "PMC5",
5477 SPR_NOACCESS, SPR_NOACCESS,
5478 &spr_read_generic, &spr_write_generic,
5479 0x00000000);
5480 /* XXX : not implemented */
5481 spr_register(env, SPR_UPMC5, "UPMC5",
5482 &spr_read_ureg, SPR_NOACCESS,
5483 &spr_read_ureg, SPR_NOACCESS,
5484 0x00000000);
5485 /* XXX : not implemented */
5486 spr_register(env, SPR_PMC6, "PMC6",
5487 SPR_NOACCESS, SPR_NOACCESS,
5488 &spr_read_generic, &spr_write_generic,
5489 0x00000000);
5490 /* XXX : not implemented */
5491 spr_register(env, SPR_UPMC6, "UPMC6",
5492 &spr_read_ureg, SPR_NOACCESS,
5493 &spr_read_ureg, SPR_NOACCESS,
5494 0x00000000);
5495 /* Memory management */
5496 gen_low_BATs(env);
5497 gen_74xx_soft_tlb(env, 128, 2);
5498 init_excp_7450(env);
5499 env->dcache_line_size = 32;
5500 env->icache_line_size = 32;
5501 /* Allocate hardware IRQ controller */
5502 ppc6xx_irq_init(env);
5503 }
5504
5505 /* PowerPC 7445 (aka G4) */
5506 #define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5507 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5508 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5509 PPC_FLOAT_STFIWX | \
5510 PPC_CACHE | PPC_CACHE_ICBI | \
5511 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5512 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5513 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5514 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5515 PPC_SEGMENT | PPC_EXTERN | \
5516 PPC_ALTIVEC)
5517 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5518 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5519 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5520 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
5521 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
5522 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5523 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5524 POWERPC_FLAG_BUS_CLK)
5525 #define check_pow_7445 check_pow_hid0_74xx
5526
5527 __attribute__ (( unused ))
5528 static void init_proc_7445 (CPUPPCState *env)
5529 {
5530 gen_spr_ne_601(env);
5531 gen_spr_7xx(env);
5532 /* Time base */
5533 gen_tbl(env);
5534 /* 74xx specific SPR */
5535 gen_spr_74xx(env);
5536 /* LDSTCR */
5537 /* XXX : not implemented */
5538 spr_register(env, SPR_LDSTCR, "LDSTCR",
5539 SPR_NOACCESS, SPR_NOACCESS,
5540 &spr_read_generic, &spr_write_generic,
5541 0x00000000);
5542 /* ICTRL */
5543 /* XXX : not implemented */
5544 spr_register(env, SPR_ICTRL, "ICTRL",
5545 SPR_NOACCESS, SPR_NOACCESS,
5546 &spr_read_generic, &spr_write_generic,
5547 0x00000000);
5548 /* MSSSR0 */
5549 /* XXX : not implemented */
5550 spr_register(env, SPR_MSSSR0, "MSSSR0",
5551 SPR_NOACCESS, SPR_NOACCESS,
5552 &spr_read_generic, &spr_write_generic,
5553 0x00000000);
5554 /* PMC */
5555 /* XXX : not implemented */
5556 spr_register(env, SPR_PMC5, "PMC5",
5557 SPR_NOACCESS, SPR_NOACCESS,
5558 &spr_read_generic, &spr_write_generic,
5559 0x00000000);
5560 /* XXX : not implemented */
5561 spr_register(env, SPR_UPMC5, "UPMC5",
5562 &spr_read_ureg, SPR_NOACCESS,
5563 &spr_read_ureg, SPR_NOACCESS,
5564 0x00000000);
5565 /* XXX : not implemented */
5566 spr_register(env, SPR_PMC6, "PMC6",
5567 SPR_NOACCESS, SPR_NOACCESS,
5568 &spr_read_generic, &spr_write_generic,
5569 0x00000000);
5570 /* XXX : not implemented */
5571 spr_register(env, SPR_UPMC6, "UPMC6",
5572 &spr_read_ureg, SPR_NOACCESS,
5573 &spr_read_ureg, SPR_NOACCESS,
5574 0x00000000);
5575 /* SPRGs */
5576 spr_register(env, SPR_SPRG4, "SPRG4",
5577 SPR_NOACCESS, SPR_NOACCESS,
5578 &spr_read_generic, &spr_write_generic,
5579 0x00000000);
5580 spr_register(env, SPR_USPRG4, "USPRG4",
5581 &spr_read_ureg, SPR_NOACCESS,
5582 &spr_read_ureg, SPR_NOACCESS,
5583 0x00000000);
5584 spr_register(env, SPR_SPRG5, "SPRG5",
5585 SPR_NOACCESS, SPR_NOACCESS,
5586 &spr_read_generic, &spr_write_generic,
5587 0x00000000);
5588 spr_register(env, SPR_USPRG5, "USPRG5",
5589 &spr_read_ureg, SPR_NOACCESS,
5590 &spr_read_ureg, SPR_NOACCESS,
5591 0x00000000);
5592 spr_register(env, SPR_SPRG6, "SPRG6",
5593 SPR_NOACCESS, SPR_NOACCESS,
5594 &spr_read_generic, &spr_write_generic,
5595 0x00000000);
5596 spr_register(env, SPR_USPRG6, "USPRG6",
5597 &spr_read_ureg, SPR_NOACCESS,
5598 &spr_read_ureg, SPR_NOACCESS,
5599 0x00000000);
5600 spr_register(env, SPR_SPRG7, "SPRG7",
5601 SPR_NOACCESS, SPR_NOACCESS,
5602 &spr_read_generic, &spr_write_generic,
5603 0x00000000);
5604 spr_register(env, SPR_USPRG7, "USPRG7",
5605 &spr_read_ureg, SPR_NOACCESS,
5606 &spr_read_ureg, SPR_NOACCESS,
5607 0x00000000);
5608 /* Memory management */
5609 gen_low_BATs(env);
5610 gen_high_BATs(env);
5611 gen_74xx_soft_tlb(env, 128, 2);
5612 init_excp_7450(env);
5613 env->dcache_line_size = 32;
5614 env->icache_line_size = 32;
5615 /* Allocate hardware IRQ controller */
5616 ppc6xx_irq_init(env);
5617 }
5618
5619 /* PowerPC 7455 (aka G4) */
5620 #define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5621 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5622 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5623 PPC_FLOAT_STFIWX | \
5624 PPC_CACHE | PPC_CACHE_ICBI | \
5625 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5626 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5627 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5628 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5629 PPC_SEGMENT | PPC_EXTERN | \
5630 PPC_ALTIVEC)
5631 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
5632 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
5633 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
5634 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
5635 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
5636 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5637 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5638 POWERPC_FLAG_BUS_CLK)
5639 #define check_pow_7455 check_pow_hid0_74xx
5640
5641 __attribute__ (( unused ))
5642 static void init_proc_7455 (CPUPPCState *env)
5643 {
5644 gen_spr_ne_601(env);
5645 gen_spr_7xx(env);
5646 /* Time base */
5647 gen_tbl(env);
5648 /* 74xx specific SPR */
5649 gen_spr_74xx(env);
5650 /* Level 3 cache control */
5651 gen_l3_ctrl(env);
5652 /* LDSTCR */
5653 /* XXX : not implemented */
5654 spr_register(env, SPR_LDSTCR, "LDSTCR",
5655 SPR_NOACCESS, SPR_NOACCESS,
5656 &spr_read_generic, &spr_write_generic,
5657 0x00000000);
5658 /* ICTRL */
5659 /* XXX : not implemented */
5660 spr_register(env, SPR_ICTRL, "ICTRL",
5661 SPR_NOACCESS, SPR_NOACCESS,
5662 &spr_read_generic, &spr_write_generic,
5663 0x00000000);
5664 /* MSSSR0 */
5665 /* XXX : not implemented */
5666 spr_register(env, SPR_MSSSR0, "MSSSR0",
5667 SPR_NOACCESS, SPR_NOACCESS,
5668 &spr_read_generic, &spr_write_generic,
5669 0x00000000);
5670 /* PMC */
5671 /* XXX : not implemented */
5672 spr_register(env, SPR_PMC5, "PMC5",
5673 SPR_NOACCESS, SPR_NOACCESS,
5674 &spr_read_generic, &spr_write_generic,
5675 0x00000000);
5676 /* XXX : not implemented */
5677 spr_register(env, SPR_UPMC5, "UPMC5",
5678 &spr_read_ureg, SPR_NOACCESS,
5679 &spr_read_ureg, SPR_NOACCESS,
5680 0x00000000);
5681 /* XXX : not implemented */
5682 spr_register(env, SPR_PMC6, "PMC6",
5683 SPR_NOACCESS, SPR_NOACCESS,
5684 &spr_read_generic, &spr_write_generic,
5685 0x00000000);
5686 /* XXX : not implemented */
5687 spr_register(env, SPR_UPMC6, "UPMC6",
5688 &spr_read_ureg, SPR_NOACCESS,
5689 &spr_read_ureg, SPR_NOACCESS,
5690 0x00000000);
5691 /* SPRGs */
5692 spr_register(env, SPR_SPRG4, "SPRG4",
5693 SPR_NOACCESS, SPR_NOACCESS,
5694 &spr_read_generic, &spr_write_generic,
5695 0x00000000);
5696 spr_register(env, SPR_USPRG4, "USPRG4",
5697 &spr_read_ureg, SPR_NOACCESS,
5698 &spr_read_ureg, SPR_NOACCESS,
5699 0x00000000);
5700 spr_register(env, SPR_SPRG5, "SPRG5",
5701 SPR_NOACCESS, SPR_NOACCESS,
5702 &spr_read_generic, &spr_write_generic,
5703 0x00000000);
5704 spr_register(env, SPR_USPRG5, "USPRG5",
5705 &spr_read_ureg, SPR_NOACCESS,
5706 &spr_read_ureg, SPR_NOACCESS,
5707 0x00000000);
5708 spr_register(env, SPR_SPRG6, "SPRG6",
5709 SPR_NOACCESS, SPR_NOACCESS,
5710 &spr_read_generic, &spr_write_generic,
5711 0x00000000);
5712 spr_register(env, SPR_USPRG6, "USPRG6",
5713 &spr_read_ureg, SPR_NOACCESS,
5714 &spr_read_ureg, SPR_NOACCESS,
5715 0x00000000);
5716 spr_register(env, SPR_SPRG7, "SPRG7",
5717 SPR_NOACCESS, SPR_NOACCESS,
5718 &spr_read_generic, &spr_write_generic,
5719 0x00000000);
5720 spr_register(env, SPR_USPRG7, "USPRG7",
5721 &spr_read_ureg, SPR_NOACCESS,
5722 &spr_read_ureg, SPR_NOACCESS,
5723 0x00000000);
5724 /* Memory management */
5725 gen_low_BATs(env);
5726 gen_high_BATs(env);
5727 gen_74xx_soft_tlb(env, 128, 2);
5728 init_excp_7450(env);
5729 env->dcache_line_size = 32;
5730 env->icache_line_size = 32;
5731 /* Allocate hardware IRQ controller */
5732 ppc6xx_irq_init(env);
5733 }
5734
5735 /* PowerPC 7457 (aka G4) */
5736 #define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5737 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5738 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5739 PPC_FLOAT_STFIWX | \
5740 PPC_CACHE | PPC_CACHE_ICBI | \
5741 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5742 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5743 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5744 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5745 PPC_SEGMENT | PPC_EXTERN | \
5746 PPC_ALTIVEC)
5747 #define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
5748 #define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
5749 #define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
5750 #define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
5751 #define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
5752 #define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5753 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5754 POWERPC_FLAG_BUS_CLK)
5755 #define check_pow_7457 check_pow_hid0_74xx
5756
5757 __attribute__ (( unused ))
5758 static void init_proc_7457 (CPUPPCState *env)
5759 {
5760 gen_spr_ne_601(env);
5761 gen_spr_7xx(env);
5762 /* Time base */
5763 gen_tbl(env);
5764 /* 74xx specific SPR */
5765 gen_spr_74xx(env);
5766 /* Level 3 cache control */
5767 gen_l3_ctrl(env);
5768 /* L3ITCR1 */
5769 /* XXX : not implemented */
5770 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5771 SPR_NOACCESS, SPR_NOACCESS,
5772 &spr_read_generic, &spr_write_generic,
5773 0x00000000);
5774 /* L3ITCR2 */
5775 /* XXX : not implemented */
5776 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5777 SPR_NOACCESS, SPR_NOACCESS,
5778 &spr_read_generic, &spr_write_generic,
5779 0x00000000);
5780 /* L3ITCR3 */
5781 /* XXX : not implemented */
5782 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5783 SPR_NOACCESS, SPR_NOACCESS,
5784 &spr_read_generic, &spr_write_generic,
5785 0x00000000);
5786 /* L3OHCR */
5787 /* XXX : not implemented */
5788 spr_register(env, SPR_L3OHCR, "L3OHCR",
5789 SPR_NOACCESS, SPR_NOACCESS,
5790 &spr_read_generic, &spr_write_generic,
5791 0x00000000);
5792 /* LDSTCR */
5793 /* XXX : not implemented */
5794 spr_register(env, SPR_LDSTCR, "LDSTCR",
5795 SPR_NOACCESS, SPR_NOACCESS,
5796 &spr_read_generic, &spr_write_generic,
5797 0x00000000);
5798 /* ICTRL */
5799 /* XXX : not implemented */
5800 spr_register(env, SPR_ICTRL, "ICTRL",
5801 SPR_NOACCESS, SPR_NOACCESS,
5802 &spr_read_generic, &spr_write_generic,
5803 0x00000000);
5804 /* MSSSR0 */
5805 /* XXX : not implemented */
5806 spr_register(env, SPR_MSSSR0, "MSSSR0",
5807 SPR_NOACCESS, SPR_NOACCESS,
5808 &spr_read_generic, &spr_write_generic,
5809 0x00000000);
5810 /* PMC */
5811 /* XXX : not implemented */
5812 spr_register(env, SPR_PMC5, "PMC5",
5813 SPR_NOACCESS, SPR_NOACCESS,
5814 &spr_read_generic, &spr_write_generic,
5815 0x00000000);
5816 /* XXX : not implemented */
5817 spr_register(env, SPR_UPMC5, "UPMC5",
5818 &spr_read_ureg, SPR_NOACCESS,
5819 &spr_read_ureg, SPR_NOACCESS,
5820 0x00000000);
5821 /* XXX : not implemented */
5822 spr_register(env, SPR_PMC6, "PMC6",
5823 SPR_NOACCESS, SPR_NOACCESS,
5824 &spr_read_generic, &spr_write_generic,
5825 0x00000000);
5826 /* XXX : not implemented */
5827 spr_register(env, SPR_UPMC6, "UPMC6",
5828 &spr_read_ureg, SPR_NOACCESS,
5829 &spr_read_ureg, SPR_NOACCESS,
5830 0x00000000);
5831 /* SPRGs */
5832 spr_register(env, SPR_SPRG4, "SPRG4",
5833 SPR_NOACCESS, SPR_NOACCESS,
5834 &spr_read_generic, &spr_write_generic,
5835 0x00000000);
5836 spr_register(env, SPR_USPRG4, "USPRG4",
5837 &spr_read_ureg, SPR_NOACCESS,
5838 &spr_read_ureg, SPR_NOACCESS,
5839 0x00000000);
5840 spr_register(env, SPR_SPRG5, "SPRG5",
5841 SPR_NOACCESS, SPR_NOACCESS,
5842 &spr_read_generic, &spr_write_generic,
5843 0x00000000);
5844 spr_register(env, SPR_USPRG5, "USPRG5",
5845 &spr_read_ureg, SPR_NOACCESS,
5846 &spr_read_ureg, SPR_NOACCESS,
5847 0x00000000);
5848 spr_register(env, SPR_SPRG6, "SPRG6",
5849 SPR_NOACCESS, SPR_NOACCESS,
5850 &spr_read_generic, &spr_write_generic,
5851 0x00000000);
5852 spr_register(env, SPR_USPRG6, "USPRG6",
5853 &spr_read_ureg, SPR_NOACCESS,
5854 &spr_read_ureg, SPR_NOACCESS,
5855 0x00000000);
5856 spr_register(env, SPR_SPRG7, "SPRG7",
5857 SPR_NOACCESS, SPR_NOACCESS,
5858 &spr_read_generic, &spr_write_generic,
5859 0x00000000);
5860 spr_register(env, SPR_USPRG7, "USPRG7",
5861 &spr_read_ureg, SPR_NOACCESS,
5862 &spr_read_ureg, SPR_NOACCESS,
5863 0x00000000);
5864 /* Memory management */
5865 gen_low_BATs(env);
5866 gen_high_BATs(env);
5867 gen_74xx_soft_tlb(env, 128, 2);
5868 init_excp_7450(env);
5869 env->dcache_line_size = 32;
5870 env->icache_line_size = 32;
5871 /* Allocate hardware IRQ controller */
5872 ppc6xx_irq_init(env);
5873 }
5874
5875 #if defined (TARGET_PPC64)
5876 /* PowerPC 970 */
5877 #define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5878 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5879 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5880 PPC_FLOAT_STFIWX | \
5881 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5882 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5883 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5884 PPC_64B | PPC_ALTIVEC | \
5885 PPC_SEGMENT_64B | PPC_SLBI)
5886 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
5887 #define POWERPC_MMU_970 (POWERPC_MMU_64B)
5888 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
5889 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
5890 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
5891 #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5892 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5893 POWERPC_FLAG_BUS_CLK)
5894
5895 #if defined(CONFIG_USER_ONLY)
5896 #define POWERPC970_HID5_INIT 0x00000080
5897 #else
5898 #define POWERPC970_HID5_INIT 0x00000000
5899 #endif
5900
5901 static int check_pow_970 (CPUPPCState *env)
5902 {
5903 if (env->spr[SPR_HID0] & 0x00600000)
5904 return 1;
5905
5906 return 0;
5907 }
5908
5909 static void init_proc_970 (CPUPPCState *env)
5910 {
5911 gen_spr_ne_601(env);
5912 gen_spr_7xx(env);
5913 /* Time base */
5914 gen_tbl(env);
5915 /* Hardware implementation registers */
5916 /* XXX : not implemented */
5917 spr_register(env, SPR_HID0, "HID0",
5918 SPR_NOACCESS, SPR_NOACCESS,
5919 &spr_read_generic, &spr_write_clear,
5920 0x60000000);
5921 /* XXX : not implemented */
5922 spr_register(env, SPR_HID1, "HID1",
5923 SPR_NOACCESS, SPR_NOACCESS,
5924 &spr_read_generic, &spr_write_generic,
5925 0x00000000);
5926 /* XXX : not implemented */
5927 spr_register(env, SPR_750FX_HID2, "HID2",
5928 SPR_NOACCESS, SPR_NOACCESS,
5929 &spr_read_generic, &spr_write_generic,
5930 0x00000000);
5931 /* XXX : not implemented */
5932 spr_register(env, SPR_970_HID5, "HID5",
5933 SPR_NOACCESS, SPR_NOACCESS,
5934 &spr_read_generic, &spr_write_generic,
5935 POWERPC970_HID5_INIT);
5936 /* XXX : not implemented */
5937 spr_register(env, SPR_L2CR, "L2CR",
5938 SPR_NOACCESS, SPR_NOACCESS,
5939 &spr_read_generic, &spr_write_generic,
5940 0x00000000);
5941 /* Memory management */
5942 /* XXX: not correct */
5943 gen_low_BATs(env);
5944 /* XXX : not implemented */
5945 spr_register(env, SPR_MMUCFG, "MMUCFG",
5946 SPR_NOACCESS, SPR_NOACCESS,
5947 &spr_read_generic, SPR_NOACCESS,
5948 0x00000000); /* TOFIX */
5949 /* XXX : not implemented */
5950 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5951 SPR_NOACCESS, SPR_NOACCESS,
5952 &spr_read_generic, &spr_write_generic,
5953 0x00000000); /* TOFIX */
5954 spr_register(env, SPR_HIOR, "SPR_HIOR",
5955 SPR_NOACCESS, SPR_NOACCESS,
5956 &spr_read_hior, &spr_write_hior,
5957 0x00000000);
5958 #if !defined(CONFIG_USER_ONLY)
5959 env->slb_nr = 32;
5960 #endif
5961 init_excp_970(env);
5962 env->dcache_line_size = 128;
5963 env->icache_line_size = 128;
5964 /* Allocate hardware IRQ controller */
5965 ppc970_irq_init(env);
5966 /* Can't find information on what this should be on reset. This
5967 * value is the one used by 74xx processors. */
5968 vscr_init(env, 0x00010000);
5969 }
5970
5971 /* PowerPC 970FX (aka G5) */
5972 #define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5973 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5974 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5975 PPC_FLOAT_STFIWX | \
5976 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5977 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5978 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5979 PPC_64B | PPC_ALTIVEC | \
5980 PPC_SEGMENT_64B | PPC_SLBI)
5981 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
5982 #define POWERPC_MMU_970FX (POWERPC_MMU_64B)
5983 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
5984 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
5985 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
5986 #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5987 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5988 POWERPC_FLAG_BUS_CLK)
5989
5990 static int check_pow_970FX (CPUPPCState *env)
5991 {
5992 if (env->spr[SPR_HID0] & 0x00600000)
5993 return 1;
5994
5995 return 0;
5996 }
5997
5998 static void init_proc_970FX (CPUPPCState *env)
5999 {
6000 gen_spr_ne_601(env);
6001 gen_spr_7xx(env);
6002 /* Time base */
6003 gen_tbl(env);
6004 /* Hardware implementation registers */
6005 /* XXX : not implemented */
6006 spr_register(env, SPR_HID0, "HID0",
6007 SPR_NOACCESS, SPR_NOACCESS,
6008 &spr_read_generic, &spr_write_clear,
6009 0x60000000);
6010 /* XXX : not implemented */
6011 spr_register(env, SPR_HID1, "HID1",
6012 SPR_NOACCESS, SPR_NOACCESS,
6013 &spr_read_generic, &spr_write_generic,
6014 0x00000000);
6015 /* XXX : not implemented */
6016 spr_register(env, SPR_750FX_HID2, "HID2",
6017 SPR_NOACCESS, SPR_NOACCESS,
6018 &spr_read_generic, &spr_write_generic,
6019 0x00000000);
6020 /* XXX : not implemented */
6021 spr_register(env, SPR_970_HID5, "HID5",
6022 SPR_NOACCESS, SPR_NOACCESS,
6023 &spr_read_generic, &spr_write_generic,
6024 POWERPC970_HID5_INIT);
6025 /* XXX : not implemented */
6026 spr_register(env, SPR_L2CR, "L2CR",
6027 SPR_NOACCESS, SPR_NOACCESS,
6028 &spr_read_generic, &spr_write_generic,
6029 0x00000000);
6030 /* Memory management */
6031 /* XXX: not correct */
6032 gen_low_BATs(env);
6033 /* XXX : not implemented */
6034 spr_register(env, SPR_MMUCFG, "MMUCFG",
6035 SPR_NOACCESS, SPR_NOACCESS,
6036 &spr_read_generic, SPR_NOACCESS,
6037 0x00000000); /* TOFIX */
6038 /* XXX : not implemented */
6039 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6040 SPR_NOACCESS, SPR_NOACCESS,
6041 &spr_read_generic, &spr_write_generic,
6042 0x00000000); /* TOFIX */
6043 spr_register(env, SPR_HIOR, "SPR_HIOR",
6044 SPR_NOACCESS, SPR_NOACCESS,
6045 &spr_read_hior, &spr_write_hior,
6046 0x00000000);
6047 #if !defined(CONFIG_USER_ONLY)
6048 env->slb_nr = 32;
6049 #endif
6050 init_excp_970(env);
6051 env->dcache_line_size = 128;
6052 env->icache_line_size = 128;
6053 /* Allocate hardware IRQ controller */
6054 ppc970_irq_init(env);
6055 /* Can't find information on what this should be on reset. This
6056 * value is the one used by 74xx processors. */
6057 vscr_init(env, 0x00010000);
6058 }
6059
6060 /* PowerPC 970 GX */
6061 #define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6062 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6063 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6064 PPC_FLOAT_STFIWX | \
6065 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6066 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6067 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6068 PPC_64B | PPC_ALTIVEC | \
6069 PPC_SEGMENT_64B | PPC_SLBI)
6070 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
6071 #define POWERPC_MMU_970GX (POWERPC_MMU_64B)
6072 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6073 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
6074 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
6075 #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6076 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6077 POWERPC_FLAG_BUS_CLK)
6078
6079 static int check_pow_970GX (CPUPPCState *env)
6080 {
6081 if (env->spr[SPR_HID0] & 0x00600000)
6082 return 1;
6083
6084 return 0;
6085 }
6086
6087 static void init_proc_970GX (CPUPPCState *env)
6088 {
6089 gen_spr_ne_601(env);
6090 gen_spr_7xx(env);
6091 /* Time base */
6092 gen_tbl(env);
6093 /* Hardware implementation registers */
6094 /* XXX : not implemented */
6095 spr_register(env, SPR_HID0, "HID0",
6096 SPR_NOACCESS, SPR_NOACCESS,
6097 &spr_read_generic, &spr_write_clear,
6098 0x60000000);
6099 /* XXX : not implemented */
6100 spr_register(env, SPR_HID1, "HID1",
6101 SPR_NOACCESS, SPR_NOACCESS,
6102 &spr_read_generic, &spr_write_generic,
6103 0x00000000);
6104 /* XXX : not implemented */
6105 spr_register(env, SPR_750FX_HID2, "HID2",
6106 SPR_NOACCESS, SPR_NOACCESS,
6107 &spr_read_generic, &spr_write_generic,
6108 0x00000000);
6109 /* XXX : not implemented */
6110 spr_register(env, SPR_970_HID5, "HID5",
6111 SPR_NOACCESS, SPR_NOACCESS,
6112 &spr_read_generic, &spr_write_generic,
6113 POWERPC970_HID5_INIT);
6114 /* XXX : not implemented */
6115 spr_register(env, SPR_L2CR, "L2CR",
6116 SPR_NOACCESS, SPR_NOACCESS,
6117 &spr_read_generic, &spr_write_generic,
6118 0x00000000);
6119 /* Memory management */
6120 /* XXX: not correct */
6121 gen_low_BATs(env);
6122 /* XXX : not implemented */
6123 spr_register(env, SPR_MMUCFG, "MMUCFG",
6124 SPR_NOACCESS, SPR_NOACCESS,
6125 &spr_read_generic, SPR_NOACCESS,
6126 0x00000000); /* TOFIX */
6127 /* XXX : not implemented */
6128 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6129 SPR_NOACCESS, SPR_NOACCESS,
6130 &spr_read_generic, &spr_write_generic,
6131 0x00000000); /* TOFIX */
6132 spr_register(env, SPR_HIOR, "SPR_HIOR",
6133 SPR_NOACCESS, SPR_NOACCESS,
6134 &spr_read_hior, &spr_write_hior,
6135 0x00000000);
6136 #if !defined(CONFIG_USER_ONLY)
6137 env->slb_nr = 32;
6138 #endif
6139 init_excp_970(env);
6140 env->dcache_line_size = 128;
6141 env->icache_line_size = 128;
6142 /* Allocate hardware IRQ controller */
6143 ppc970_irq_init(env);
6144 /* Can't find information on what this should be on reset. This
6145 * value is the one used by 74xx processors. */
6146 vscr_init(env, 0x00010000);
6147 }
6148
6149 /* PowerPC 970 MP */
6150 #define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6151 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6152 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6153 PPC_FLOAT_STFIWX | \
6154 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6155 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6156 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6157 PPC_64B | PPC_ALTIVEC | \
6158 PPC_SEGMENT_64B | PPC_SLBI)
6159 #define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6160 #define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6161 #define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6162 #define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6163 #define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6164 #define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6165 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6166 POWERPC_FLAG_BUS_CLK)
6167
6168 static int check_pow_970MP (CPUPPCState *env)
6169 {
6170 if (env->spr[SPR_HID0] & 0x01C00000)
6171 return 1;
6172
6173 return 0;
6174 }
6175
6176 static void init_proc_970MP (CPUPPCState *env)
6177 {
6178 gen_spr_ne_601(env);
6179 gen_spr_7xx(env);
6180 /* Time base */
6181 gen_tbl(env);
6182 /* Hardware implementation registers */
6183 /* XXX : not implemented */
6184 spr_register(env, SPR_HID0, "HID0",
6185 SPR_NOACCESS, SPR_NOACCESS,
6186 &spr_read_generic, &spr_write_clear,
6187 0x60000000);
6188 /* XXX : not implemented */
6189 spr_register(env, SPR_HID1, "HID1",
6190 SPR_NOACCESS, SPR_NOACCESS,
6191 &spr_read_generic, &spr_write_generic,
6192 0x00000000);
6193 /* XXX : not implemented */
6194 spr_register(env, SPR_750FX_HID2, "HID2",
6195 SPR_NOACCESS, SPR_NOACCESS,
6196 &spr_read_generic, &spr_write_generic,
6197 0x00000000);
6198 /* XXX : not implemented */
6199 spr_register(env, SPR_970_HID5, "HID5",
6200 SPR_NOACCESS, SPR_NOACCESS,
6201 &spr_read_generic, &spr_write_generic,
6202 POWERPC970_HID5_INIT);
6203 /* XXX : not implemented */
6204 spr_register(env, SPR_L2CR, "L2CR",
6205 SPR_NOACCESS, SPR_NOACCESS,
6206 &spr_read_generic, &spr_write_generic,
6207 0x00000000);
6208 /* Memory management */
6209 /* XXX: not correct */
6210 gen_low_BATs(env);
6211 /* XXX : not implemented */
6212 spr_register(env, SPR_MMUCFG, "MMUCFG",
6213 SPR_NOACCESS, SPR_NOACCESS,
6214 &spr_read_generic, SPR_NOACCESS,
6215 0x00000000); /* TOFIX */
6216 /* XXX : not implemented */
6217 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6218 SPR_NOACCESS, SPR_NOACCESS,
6219 &spr_read_generic, &spr_write_generic,
6220 0x00000000); /* TOFIX */
6221 spr_register(env, SPR_HIOR, "SPR_HIOR",
6222 SPR_NOACCESS, SPR_NOACCESS,
6223 &spr_read_hior, &spr_write_hior,
6224 0x00000000);
6225 #if !defined(CONFIG_USER_ONLY)
6226 env->slb_nr = 32;
6227 #endif
6228 init_excp_970(env);
6229 env->dcache_line_size = 128;
6230 env->icache_line_size = 128;
6231 /* Allocate hardware IRQ controller */
6232 ppc970_irq_init(env);
6233 /* Can't find information on what this should be on reset. This
6234 * value is the one used by 74xx processors. */
6235 vscr_init(env, 0x00010000);
6236 }
6237
6238 /* PowerPC 620 */
6239 #define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6240 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6241 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6242 PPC_FLOAT_STFIWX | \
6243 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6244 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6245 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6246 PPC_SEGMENT | PPC_EXTERN | \
6247 PPC_64B | PPC_SLBI)
6248 #define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6249 //#define POWERPC_MMU_620 (POWERPC_MMU_620)
6250 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
6251 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
6252 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
6253 #define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
6254 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
6255 #define check_pow_620 check_pow_nocheck /* Check this */
6256
6257 __attribute__ (( unused ))
6258 static void init_proc_620 (CPUPPCState *env)
6259 {
6260 gen_spr_ne_601(env);
6261 gen_spr_620(env);
6262 /* Time base */
6263 gen_tbl(env);
6264 /* Hardware implementation registers */
6265 /* XXX : not implemented */
6266 spr_register(env, SPR_HID0, "HID0",
6267 SPR_NOACCESS, SPR_NOACCESS,
6268 &spr_read_generic, &spr_write_generic,
6269 0x00000000);
6270 /* Memory management */
6271 gen_low_BATs(env);
6272 init_excp_620(env);
6273 env->dcache_line_size = 64;
6274 env->icache_line_size = 64;
6275 /* Allocate hardware IRQ controller */
6276 ppc6xx_irq_init(env);
6277 }
6278 #endif /* defined (TARGET_PPC64) */
6279
6280 /* Default 32 bits PowerPC target will be 604 */
6281 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
6282 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
6283 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6284 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
6285 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6286 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
6287 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
6288 #define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
6289 #define check_pow_PPC32 check_pow_604
6290 #define init_proc_PPC32 init_proc_604
6291
6292 /* Default 64 bits PowerPC target will be 970 FX */
6293 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6294 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
6295 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6296 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6297 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6298 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
6299 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
6300 #define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
6301 #define check_pow_PPC64 check_pow_970FX
6302 #define init_proc_PPC64 init_proc_970FX
6303
6304 /* Default PowerPC target will be PowerPC 32 */
6305 #if defined (TARGET_PPC64) && 0 // XXX: TODO
6306 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6307 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6308 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6309 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6310 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6311 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6312 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
6313 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
6314 #define check_pow_DEFAULT check_pow_PPC64
6315 #define init_proc_DEFAULT init_proc_PPC64
6316 #else
6317 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6318 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6319 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6320 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6321 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6322 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6323 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
6324 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
6325 #define check_pow_DEFAULT check_pow_PPC32
6326 #define init_proc_DEFAULT init_proc_PPC32
6327 #endif
6328
6329 /*****************************************************************************/
6330 /* PVR definitions for most known PowerPC */
6331 enum {
6332 /* PowerPC 401 family */
6333 /* Generic PowerPC 401 */
6334 #define CPU_POWERPC_401 CPU_POWERPC_401G2
6335 /* PowerPC 401 cores */
6336 CPU_POWERPC_401A1 = 0x00210000,
6337 CPU_POWERPC_401B2 = 0x00220000,
6338 #if 0
6339 CPU_POWERPC_401B3 = xxx,
6340 #endif
6341 CPU_POWERPC_401C2 = 0x00230000,
6342 CPU_POWERPC_401D2 = 0x00240000,
6343 CPU_POWERPC_401E2 = 0x00250000,
6344 CPU_POWERPC_401F2 = 0x00260000,
6345 CPU_POWERPC_401G2 = 0x00270000,
6346 /* PowerPC 401 microcontrolers */
6347 #if 0
6348 CPU_POWERPC_401GF = xxx,
6349 #endif
6350 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
6351 /* IBM Processor for Network Resources */
6352 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
6353 #if 0
6354 CPU_POWERPC_XIPCHIP = xxx,
6355 #endif
6356 /* PowerPC 403 family */
6357 /* Generic PowerPC 403 */
6358 #define CPU_POWERPC_403 CPU_POWERPC_403GC
6359 /* PowerPC 403 microcontrollers */
6360 CPU_POWERPC_403GA = 0x00200011,
6361 CPU_POWERPC_403GB = 0x00200100,
6362 CPU_POWERPC_403GC = 0x00200200,
6363 CPU_POWERPC_403GCX = 0x00201400,
6364 #if 0
6365 CPU_POWERPC_403GP = xxx,
6366 #endif
6367 /* PowerPC 405 family */
6368 /* Generic PowerPC 405 */
6369 #define CPU_POWERPC_405 CPU_POWERPC_405D4
6370 /* PowerPC 405 cores */
6371 #if 0
6372 CPU_POWERPC_405A3 = xxx,
6373 #endif
6374 #if 0
6375 CPU_POWERPC_405A4 = xxx,
6376 #endif
6377 #if 0
6378 CPU_POWERPC_405B3 = xxx,
6379 #endif
6380 #if 0
6381 CPU_POWERPC_405B4 = xxx,
6382 #endif
6383 #if 0
6384 CPU_POWERPC_405C3 = xxx,
6385 #endif
6386 #if 0
6387 CPU_POWERPC_405C4 = xxx,
6388 #endif
6389 CPU_POWERPC_405D2 = 0x20010000,
6390 #if 0
6391 CPU_POWERPC_405D3 = xxx,
6392 #endif
6393 CPU_POWERPC_405D4 = 0x41810000,
6394 #if 0
6395 CPU_POWERPC_405D5 = xxx,
6396 #endif
6397 #if 0
6398 CPU_POWERPC_405E4 = xxx,
6399 #endif
6400 #if 0
6401 CPU_POWERPC_405F4 = xxx,
6402 #endif
6403 #if 0
6404 CPU_POWERPC_405F5 = xxx,
6405 #endif
6406 #if 0
6407 CPU_POWERPC_405F6 = xxx,
6408 #endif
6409 /* PowerPC 405 microcontrolers */
6410 /* XXX: missing 0x200108a0 */
6411 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6412 CPU_POWERPC_405CRa = 0x40110041,
6413 CPU_POWERPC_405CRb = 0x401100C5,
6414 CPU_POWERPC_405CRc = 0x40110145,
6415 CPU_POWERPC_405EP = 0x51210950,
6416 #if 0
6417 CPU_POWERPC_405EXr = xxx,
6418 #endif
6419 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
6420 #if 0
6421 CPU_POWERPC_405FX = xxx,
6422 #endif
6423 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6424 CPU_POWERPC_405GPa = 0x40110000,
6425 CPU_POWERPC_405GPb = 0x40110040,
6426 CPU_POWERPC_405GPc = 0x40110082,
6427 CPU_POWERPC_405GPd = 0x401100C4,
6428 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6429 CPU_POWERPC_405GPR = 0x50910951,
6430 #if 0
6431 CPU_POWERPC_405H = xxx,
6432 #endif
6433 #if 0
6434 CPU_POWERPC_405L = xxx,
6435 #endif
6436 CPU_POWERPC_405LP = 0x41F10000,
6437 #if 0
6438 CPU_POWERPC_405PM = xxx,
6439 #endif
6440 #if 0
6441 CPU_POWERPC_405PS = xxx,
6442 #endif
6443 #if 0
6444 CPU_POWERPC_405S = xxx,
6445 #endif
6446 /* IBM network processors */
6447 CPU_POWERPC_NPE405H = 0x414100C0,
6448 CPU_POWERPC_NPE405H2 = 0x41410140,
6449 CPU_POWERPC_NPE405L = 0x416100C0,
6450 CPU_POWERPC_NPE4GS3 = 0x40B10000,
6451 #if 0
6452 CPU_POWERPC_NPCxx1 = xxx,
6453 #endif
6454 #if 0
6455 CPU_POWERPC_NPR161 = xxx,
6456 #endif
6457 #if 0
6458 CPU_POWERPC_LC77700 = xxx,
6459 #endif
6460 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6461 #if 0
6462 CPU_POWERPC_STB01000 = xxx,
6463 #endif
6464 #if 0
6465 CPU_POWERPC_STB01010 = xxx,
6466 #endif
6467 #if 0
6468 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
6469 #endif
6470 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
6471 #if 0
6472 CPU_POWERPC_STB043 = xxx,
6473 #endif
6474 #if 0
6475 CPU_POWERPC_STB045 = xxx,
6476 #endif
6477 CPU_POWERPC_STB04 = 0x41810000,
6478 CPU_POWERPC_STB25 = 0x51510950,
6479 #if 0
6480 CPU_POWERPC_STB130 = xxx,
6481 #endif
6482 /* Xilinx cores */
6483 CPU_POWERPC_X2VP4 = 0x20010820,
6484 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
6485 CPU_POWERPC_X2VP20 = 0x20010860,
6486 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
6487 #if 0
6488 CPU_POWERPC_ZL10310 = xxx,
6489 #endif
6490 #if 0
6491 CPU_POWERPC_ZL10311 = xxx,
6492 #endif
6493 #if 0
6494 CPU_POWERPC_ZL10320 = xxx,
6495 #endif
6496 #if 0
6497 CPU_POWERPC_ZL10321 = xxx,
6498 #endif
6499 /* PowerPC 440 family */
6500 /* Generic PowerPC 440 */
6501 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
6502 /* PowerPC 440 cores */
6503 #if 0
6504 CPU_POWERPC_440A4 = xxx,
6505 #endif
6506 #if 0
6507 CPU_POWERPC_440A5 = xxx,
6508 #endif
6509 #if 0
6510 CPU_POWERPC_440B4 = xxx,
6511 #endif
6512 #if 0
6513 CPU_POWERPC_440F5 = xxx,
6514 #endif
6515 #if 0
6516 CPU_POWERPC_440G5 = xxx,
6517 #endif
6518 #if 0
6519 CPU_POWERPC_440H4 = xxx,
6520 #endif
6521 #if 0
6522 CPU_POWERPC_440H6 = xxx,
6523 #endif
6524 /* PowerPC 440 microcontrolers */
6525 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
6526 CPU_POWERPC_440EPa = 0x42221850,
6527 CPU_POWERPC_440EPb = 0x422218D3,
6528 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
6529 CPU_POWERPC_440GPb = 0x40120440,
6530 CPU_POWERPC_440GPc = 0x40120481,
6531 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
6532 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
6533 CPU_POWERPC_440GRX = 0x200008D0,
6534 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
6535 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
6536 CPU_POWERPC_440GXa = 0x51B21850,
6537 CPU_POWERPC_440GXb = 0x51B21851,
6538 CPU_POWERPC_440GXc = 0x51B21892,
6539 CPU_POWERPC_440GXf = 0x51B21894,
6540 #if 0
6541 CPU_POWERPC_440S = xxx,
6542 #endif
6543 CPU_POWERPC_440SP = 0x53221850,
6544 CPU_POWERPC_440SP2 = 0x53221891,
6545 CPU_POWERPC_440SPE = 0x53421890,
6546 /* PowerPC 460 family */
6547 #if 0
6548 /* Generic PowerPC 464 */
6549 #define CPU_POWERPC_464 CPU_POWERPC_464H90
6550 #endif
6551 /* PowerPC 464 microcontrolers */
6552 #if 0
6553 CPU_POWERPC_464H90 = xxx,
6554 #endif
6555 #if 0
6556 CPU_POWERPC_464H90FP = xxx,
6557 #endif
6558 /* Freescale embedded PowerPC cores */
6559 /* PowerPC MPC 5xx cores (aka RCPU) */
6560 CPU_POWERPC_MPC5xx = 0x00020020,
6561 #define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
6562 #define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
6563 #define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
6564 #define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
6565 #define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
6566 #define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
6567 #define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
6568 #define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
6569 #define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
6570 #define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
6571 #define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
6572 #define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
6573 #define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
6574 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
6575 CPU_POWERPC_MPC8xx = 0x00500000,
6576 #define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
6577 #define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
6578 #define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
6579 #define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
6580 #define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
6581 #define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
6582 #define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
6583 #define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
6584 #define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
6585 #define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
6586 #define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
6587 #define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
6588 #define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
6589 #define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
6590 #define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
6591 /* G2 cores (aka PowerQUICC-II) */
6592 CPU_POWERPC_G2 = 0x00810011,
6593 CPU_POWERPC_G2H4 = 0x80811010,
6594 CPU_POWERPC_G2gp = 0x80821010,
6595 CPU_POWERPC_G2ls = 0x90810010,
6596 CPU_POWERPC_MPC603 = 0x00810100,
6597 CPU_POWERPC_G2_HIP3 = 0x00810101,
6598 CPU_POWERPC_G2_HIP4 = 0x80811014,
6599 /* G2_LE core (aka PowerQUICC-II) */
6600 CPU_POWERPC_G2LE = 0x80820010,
6601 CPU_POWERPC_G2LEgp = 0x80822010,
6602 CPU_POWERPC_G2LEls = 0xA0822010,
6603 CPU_POWERPC_G2LEgp1 = 0x80822011,
6604 CPU_POWERPC_G2LEgp3 = 0x80822013,
6605 /* MPC52xx microcontrollers */
6606 /* XXX: MPC 5121 ? */
6607 #define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
6608 #define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
6609 #define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
6610 #define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
6611 #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
6612 #define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
6613 #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
6614 #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
6615 /* MPC82xx microcontrollers */
6616 #define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
6617 #define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
6618 #define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
6619 #define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
6620 #define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
6621 #define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
6622 #define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
6623 #define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
6624 #define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
6625 #define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
6626 #define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
6627 #define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
6628 #define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
6629 #define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
6630 #define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
6631 #define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
6632 #define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
6633 #define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
6634 #define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
6635 #define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
6636 #define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
6637 #define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
6638 #define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
6639 #define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
6640 #define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
6641 #define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
6642 #define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
6643 #define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
6644 #define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
6645 /* e200 family */
6646 /* e200 cores */
6647 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
6648 #if 0
6649 CPU_POWERPC_e200z0 = xxx,
6650 #endif
6651 #if 0
6652 CPU_POWERPC_e200z1 = xxx,
6653 #endif
6654 #if 0 /* ? */
6655 CPU_POWERPC_e200z3 = 0x81120000,
6656 #endif
6657 CPU_POWERPC_e200z5 = 0x81000000,
6658 CPU_POWERPC_e200z6 = 0x81120000,
6659 /* MPC55xx microcontrollers */
6660 #define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
6661 #if 0
6662 #define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
6663 #define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
6664 #define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
6665 #define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
6666 #define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
6667 #define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
6668 #define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
6669 #define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
6670 #define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
6671 #define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
6672 #define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
6673 #define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
6674 #define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
6675 #define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
6676 #endif
6677 #if 0
6678 #define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
6679 #define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
6680 #endif
6681 #define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
6682 #define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
6683 #define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
6684 #define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
6685 #define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
6686 #define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
6687 /* e300 family */
6688 /* e300 cores */
6689 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
6690 CPU_POWERPC_e300c1 = 0x00830010,
6691 CPU_POWERPC_e300c2 = 0x00840010,
6692 CPU_POWERPC_e300c3 = 0x00850010,
6693 CPU_POWERPC_e300c4 = 0x00860010,
6694 /* MPC83xx microcontrollers */
6695 #define CPU_POWERPC_MPC8313 CPU_POWERPC_e300c3
6696 #define CPU_POWERPC_MPC8313E CPU_POWERPC_e300c3
6697 #define CPU_POWERPC_MPC8314 CPU_POWERPC_e300c3
6698 #define CPU_POWERPC_MPC8314E CPU_POWERPC_e300c3
6699 #define CPU_POWERPC_MPC8315 CPU_POWERPC_e300c3
6700 #define CPU_POWERPC_MPC8315E CPU_POWERPC_e300c3
6701 #define CPU_POWERPC_MPC8321 CPU_POWERPC_e300c2
6702 #define CPU_POWERPC_MPC8321E CPU_POWERPC_e300c2
6703 #define CPU_POWERPC_MPC8323 CPU_POWERPC_e300c2
6704 #define CPU_POWERPC_MPC8323E CPU_POWERPC_e300c2
6705 #define CPU_POWERPC_MPC8343A CPU_POWERPC_e300c1
6706 #define CPU_POWERPC_MPC8343EA CPU_POWERPC_e300c1
6707 #define CPU_POWERPC_MPC8347A CPU_POWERPC_e300c1
6708 #define CPU_POWERPC_MPC8347AT CPU_POWERPC_e300c1
6709 #define CPU_POWERPC_MPC8347AP CPU_POWERPC_e300c1
6710 #define CPU_POWERPC_MPC8347EA CPU_POWERPC_e300c1
6711 #define CPU_POWERPC_MPC8347EAT CPU_POWERPC_e300c1
6712 #define CPU_POWERPC_MPC8347EAP CPU_POWERPC_e300c1
6713 #define CPU_POWERPC_MPC8349 CPU_POWERPC_e300c1
6714 #define CPU_POWERPC_MPC8349A CPU_POWERPC_e300c1
6715 #define CPU_POWERPC_MPC8349E CPU_POWERPC_e300c1
6716 #define CPU_POWERPC_MPC8349EA CPU_POWERPC_e300c1
6717 #define CPU_POWERPC_MPC8358E CPU_POWERPC_e300c1
6718 #define CPU_POWERPC_MPC8360E CPU_POWERPC_e300c1
6719 #define CPU_POWERPC_MPC8377 CPU_POWERPC_e300c4
6720 #define CPU_POWERPC_MPC8377E CPU_POWERPC_e300c4
6721 #define CPU_POWERPC_MPC8378 CPU_POWERPC_e300c4
6722 #define CPU_POWERPC_MPC8378E CPU_POWERPC_e300c4
6723 #define CPU_POWERPC_MPC8379 CPU_POWERPC_e300c4
6724 #define CPU_POWERPC_MPC8379E CPU_POWERPC_e300c4
6725 /* e500 family */
6726 /* e500 cores */
6727 #define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
6728 #define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
6729 #define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
6730 CPU_POWERPC_e500v1_v10 = 0x80200010,
6731 CPU_POWERPC_e500v1_v20 = 0x80200020,
6732 CPU_POWERPC_e500v2_v10 = 0x80210010,
6733 CPU_POWERPC_e500v2_v11 = 0x80210011,
6734 CPU_POWERPC_e500v2_v20 = 0x80210020,
6735 CPU_POWERPC_e500v2_v21 = 0x80210021,
6736 CPU_POWERPC_e500v2_v22 = 0x80210022,
6737 CPU_POWERPC_e500v2_v30 = 0x80210030,
6738 /* MPC85xx microcontrollers */
6739 #define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
6740 #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
6741 #define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
6742 #define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
6743 #define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
6744 #define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
6745 #define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
6746 #define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
6747 #define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
6748 #define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
6749 #define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
6750 #define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
6751 #define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
6752 #define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
6753 #define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
6754 #define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
6755 #define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
6756 #define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
6757 #define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
6758 #define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
6759 #define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
6760 #define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
6761 #define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
6762 #define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
6763 #define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
6764 #define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
6765 #define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
6766 #define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
6767 #define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
6768 #define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
6769 #define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
6770 #define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
6771 #define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
6772 #define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
6773 #define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
6774 #define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
6775 #define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
6776 #define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
6777 #define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
6778 #define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
6779 #define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
6780 #define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
6781 #define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
6782 #define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
6783 #define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
6784 #define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
6785 #define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
6786 #define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
6787 #define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
6788 #define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
6789 #define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
6790 #define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
6791 #define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
6792 #define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
6793 #define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
6794 #define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
6795 #define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
6796 #define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
6797 #define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
6798 #define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
6799 #define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
6800 #define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
6801 #define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
6802 #define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
6803 #define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
6804 #define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
6805 #define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
6806 #define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
6807 #define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
6808 #define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
6809 /* e600 family */
6810 /* e600 cores */
6811 CPU_POWERPC_e600 = 0x80040010,
6812 /* MPC86xx microcontrollers */
6813 #define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
6814 #define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
6815 #define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
6816 /* PowerPC 6xx cores */
6817 #define CPU_POWERPC_601 CPU_POWERPC_601_v2
6818 CPU_POWERPC_601_v0 = 0x00010001,
6819 CPU_POWERPC_601_v1 = 0x00010001,
6820 #define CPU_POWERPC_601v CPU_POWERPC_601_v2
6821 CPU_POWERPC_601_v2 = 0x00010002,
6822 CPU_POWERPC_602 = 0x00050100,
6823 CPU_POWERPC_603 = 0x00030100,
6824 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
6825 CPU_POWERPC_603E_v11 = 0x00060101,
6826 CPU_POWERPC_603E_v12 = 0x00060102,
6827 CPU_POWERPC_603E_v13 = 0x00060103,
6828 CPU_POWERPC_603E_v14 = 0x00060104,
6829 CPU_POWERPC_603E_v22 = 0x00060202,
6830 CPU_POWERPC_603E_v3 = 0x00060300,
6831 CPU_POWERPC_603E_v4 = 0x00060400,
6832 CPU_POWERPC_603E_v41 = 0x00060401,
6833 CPU_POWERPC_603E7t = 0x00071201,
6834 CPU_POWERPC_603E7v = 0x00070100,
6835 CPU_POWERPC_603E7v1 = 0x00070101,
6836 CPU_POWERPC_603E7v2 = 0x00070201,
6837 CPU_POWERPC_603E7 = 0x00070200,
6838 CPU_POWERPC_603P = 0x00070000,
6839 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
6840 /* XXX: missing 0x00040303 (604) */
6841 CPU_POWERPC_604 = 0x00040103,
6842 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
6843 /* XXX: missing 0x00091203 */
6844 /* XXX: missing 0x00092110 */
6845 /* XXX: missing 0x00092120 */
6846 CPU_POWERPC_604E_v10 = 0x00090100,
6847 CPU_POWERPC_604E_v22 = 0x00090202,
6848 CPU_POWERPC_604E_v24 = 0x00090204,
6849 /* XXX: missing 0x000a0100 */
6850 /* XXX: missing 0x00093102 */
6851 CPU_POWERPC_604R = 0x000a0101,
6852 #if 0
6853 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
6854 #endif
6855 /* PowerPC 740/750 cores (aka G3) */
6856 /* XXX: missing 0x00084202 */
6857 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
6858 CPU_POWERPC_7x0_v10 = 0x00080100,
6859 CPU_POWERPC_7x0_v20 = 0x00080200,
6860 CPU_POWERPC_7x0_v21 = 0x00080201,
6861 CPU_POWERPC_7x0_v22 = 0x00080202,
6862 CPU_POWERPC_7x0_v30 = 0x00080300,
6863 CPU_POWERPC_7x0_v31 = 0x00080301,
6864 CPU_POWERPC_740E = 0x00080100,
6865 CPU_POWERPC_750E = 0x00080200,
6866 CPU_POWERPC_7x0P = 0x10080000,
6867 /* XXX: missing 0x00087010 (CL ?) */
6868 #define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
6869 CPU_POWERPC_750CL_v10 = 0x00087200,
6870 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
6871 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
6872 CPU_POWERPC_750CX_v10 = 0x00082100,
6873 CPU_POWERPC_750CX_v20 = 0x00082200,
6874 CPU_POWERPC_750CX_v21 = 0x00082201,
6875 CPU_POWERPC_750CX_v22 = 0x00082202,
6876 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
6877 CPU_POWERPC_750CXE_v21 = 0x00082211,
6878 CPU_POWERPC_750CXE_v22 = 0x00082212,
6879 CPU_POWERPC_750CXE_v23 = 0x00082213,
6880 CPU_POWERPC_750CXE_v24 = 0x00082214,
6881 CPU_POWERPC_750CXE_v24b = 0x00083214,
6882 CPU_POWERPC_750CXE_v30 = 0x00082310,
6883 CPU_POWERPC_750CXE_v31 = 0x00082311,
6884 CPU_POWERPC_750CXE_v31b = 0x00083311,
6885 CPU_POWERPC_750CXR = 0x00083410,
6886 CPU_POWERPC_750FL = 0x70000203,
6887 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
6888 CPU_POWERPC_750FX_v10 = 0x70000100,
6889 CPU_POWERPC_750FX_v20 = 0x70000200,
6890 CPU_POWERPC_750FX_v21 = 0x70000201,
6891 CPU_POWERPC_750FX_v22 = 0x70000202,
6892 CPU_POWERPC_750FX_v23 = 0x70000203,
6893 CPU_POWERPC_750GL = 0x70020102,
6894 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
6895 CPU_POWERPC_750GX_v10 = 0x70020100,
6896 CPU_POWERPC_750GX_v11 = 0x70020101,
6897 CPU_POWERPC_750GX_v12 = 0x70020102,
6898 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
6899 CPU_POWERPC_750L_v20 = 0x00088200,
6900 CPU_POWERPC_750L_v21 = 0x00088201,
6901 CPU_POWERPC_750L_v22 = 0x00088202,
6902 CPU_POWERPC_750L_v30 = 0x00088300,
6903 CPU_POWERPC_750L_v32 = 0x00088302,
6904 /* PowerPC 745/755 cores */
6905 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
6906 CPU_POWERPC_7x5_v10 = 0x00083100,
6907 CPU_POWERPC_7x5_v11 = 0x00083101,
6908 CPU_POWERPC_7x5_v20 = 0x00083200,
6909 CPU_POWERPC_7x5_v21 = 0x00083201,
6910 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
6911 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
6912 CPU_POWERPC_7x5_v24 = 0x00083204,
6913 CPU_POWERPC_7x5_v25 = 0x00083205,
6914 CPU_POWERPC_7x5_v26 = 0x00083206,
6915 CPU_POWERPC_7x5_v27 = 0x00083207,
6916 CPU_POWERPC_7x5_v28 = 0x00083208,
6917 #if 0
6918 CPU_POWERPC_7x5P = xxx,
6919 #endif
6920 /* PowerPC 74xx cores (aka G4) */
6921 /* XXX: missing 0x000C1101 */
6922 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
6923 CPU_POWERPC_7400_v10 = 0x000C0100,
6924 CPU_POWERPC_7400_v11 = 0x000C0101,
6925 CPU_POWERPC_7400_v20 = 0x000C0200,
6926 CPU_POWERPC_7400_v21 = 0x000C0201,
6927 CPU_POWERPC_7400_v22 = 0x000C0202,
6928 CPU_POWERPC_7400_v26 = 0x000C0206,
6929 CPU_POWERPC_7400_v27 = 0x000C0207,
6930 CPU_POWERPC_7400_v28 = 0x000C0208,
6931 CPU_POWERPC_7400_v29 = 0x000C0209,
6932 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
6933 CPU_POWERPC_7410_v10 = 0x800C1100,
6934 CPU_POWERPC_7410_v11 = 0x800C1101,
6935 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
6936 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
6937 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
6938 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
6939 CPU_POWERPC_7448_v10 = 0x80040100,
6940 CPU_POWERPC_7448_v11 = 0x80040101,
6941 CPU_POWERPC_7448_v20 = 0x80040200,
6942 CPU_POWERPC_7448_v21 = 0x80040201,
6943 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
6944 CPU_POWERPC_7450_v10 = 0x80000100,
6945 CPU_POWERPC_7450_v11 = 0x80000101,
6946 CPU_POWERPC_7450_v12 = 0x80000102,
6947 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
6948 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
6949 #define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
6950 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
6951 /* XXX: this entry might be a bug in some documentation */
6952 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
6953 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
6954 CPU_POWERPC_74x5_v10 = 0x80010100,
6955 /* XXX: missing 0x80010200 */
6956 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
6957 CPU_POWERPC_74x5_v32 = 0x80010302,
6958 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
6959 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
6960 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
6961 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
6962 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
6963 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
6964 #define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
6965 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
6966 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
6967 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
6968 /* 64 bits PowerPC */
6969 #if defined(TARGET_PPC64)
6970 CPU_POWERPC_620 = 0x00140000,
6971 CPU_POWERPC_630 = 0x00400000,
6972 CPU_POWERPC_631 = 0x00410104,
6973 CPU_POWERPC_POWER4 = 0x00350000,
6974 CPU_POWERPC_POWER4P = 0x00380000,
6975 /* XXX: missing 0x003A0201 */
6976 CPU_POWERPC_POWER5 = 0x003A0203,
6977 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
6978 CPU_POWERPC_POWER5P = 0x003B0000,
6979 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
6980 CPU_POWERPC_POWER6 = 0x003E0000,
6981 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
6982 CPU_POWERPC_POWER6A = 0x0F000002,
6983 CPU_POWERPC_970 = 0x00390202,
6984 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
6985 CPU_POWERPC_970FX_v10 = 0x00391100,
6986 CPU_POWERPC_970FX_v20 = 0x003C0200,
6987 CPU_POWERPC_970FX_v21 = 0x003C0201,
6988 CPU_POWERPC_970FX_v30 = 0x003C0300,
6989 CPU_POWERPC_970FX_v31 = 0x003C0301,
6990 CPU_POWERPC_970GX = 0x00450000,
6991 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
6992 CPU_POWERPC_970MP_v10 = 0x00440100,
6993 CPU_POWERPC_970MP_v11 = 0x00440101,
6994 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
6995 CPU_POWERPC_CELL_v10 = 0x00700100,
6996 CPU_POWERPC_CELL_v20 = 0x00700400,
6997 CPU_POWERPC_CELL_v30 = 0x00700500,
6998 CPU_POWERPC_CELL_v31 = 0x00700501,
6999 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
7000 CPU_POWERPC_RS64 = 0x00330000,
7001 CPU_POWERPC_RS64II = 0x00340000,
7002 CPU_POWERPC_RS64III = 0x00360000,
7003 CPU_POWERPC_RS64IV = 0x00370000,
7004 #endif /* defined(TARGET_PPC64) */
7005 /* Original POWER */
7006 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7007 * POWER2 (RIOS2) & RSC2 (P2SC) here
7008 */
7009 #if 0
7010 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
7011 #endif
7012 #if 0
7013 CPU_POWER2 = xxx, /* 0x40000 ? */
7014 #endif
7015 /* PA Semi core */
7016 CPU_POWERPC_PA6T = 0x00900000,
7017 };
7018
7019 /* System version register (used on MPC 8xxx) */
7020 enum {
7021 POWERPC_SVR_NONE = 0x00000000,
7022 #define POWERPC_SVR_52xx POWERPC_SVR_5200
7023 #define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7024 POWERPC_SVR_5200_v10 = 0x80110010,
7025 POWERPC_SVR_5200_v11 = 0x80110011,
7026 POWERPC_SVR_5200_v12 = 0x80110012,
7027 #define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7028 POWERPC_SVR_5200B_v20 = 0x80110020,
7029 POWERPC_SVR_5200B_v21 = 0x80110021,
7030 #define POWERPC_SVR_55xx POWERPC_SVR_5567
7031 #if 0
7032 POWERPC_SVR_5533 = xxx,
7033 #endif
7034 #if 0
7035 POWERPC_SVR_5534 = xxx,
7036 #endif
7037 #if 0
7038 POWERPC_SVR_5553 = xxx,
7039 #endif
7040 #if 0
7041 POWERPC_SVR_5554 = xxx,
7042 #endif
7043 #if 0
7044 POWERPC_SVR_5561 = xxx,
7045 #endif
7046 #if 0
7047 POWERPC_SVR_5565 = xxx,
7048 #endif
7049 #if 0
7050 POWERPC_SVR_5566 = xxx,
7051 #endif
7052 #if 0
7053 POWERPC_SVR_5567 = xxx,
7054 #endif
7055 #if 0
7056 POWERPC_SVR_8313 = xxx,
7057 #endif
7058 #if 0
7059 POWERPC_SVR_8313E = xxx,
7060 #endif
7061 #if 0
7062 POWERPC_SVR_8314 = xxx,
7063 #endif
7064 #if 0
7065 POWERPC_SVR_8314E = xxx,
7066 #endif
7067 #if 0
7068 POWERPC_SVR_8315 = xxx,
7069 #endif
7070 #if 0
7071 POWERPC_SVR_8315E = xxx,
7072 #endif
7073 #if 0
7074 POWERPC_SVR_8321 = xxx,
7075 #endif
7076 #if 0
7077 POWERPC_SVR_8321E = xxx,
7078 #endif
7079 #if 0
7080 POWERPC_SVR_8323 = xxx,
7081 #endif
7082 #if 0
7083 POWERPC_SVR_8323E = xxx,
7084 #endif
7085 POWERPC_SVR_8343A = 0x80570030,
7086 POWERPC_SVR_8343EA = 0x80560030,
7087 #define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7088 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7089 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
7090 #define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7091 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7092 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7093 POWERPC_SVR_8349 = 0x80510010,
7094 POWERPC_SVR_8349A = 0x80510030,
7095 POWERPC_SVR_8349E = 0x80500010,
7096 POWERPC_SVR_8349EA = 0x80500030,
7097 #if 0
7098 POWERPC_SVR_8358E = xxx,
7099 #endif
7100 #if 0
7101 POWERPC_SVR_8360E = xxx,
7102 #endif
7103 #define POWERPC_SVR_E500 0x40000000
7104 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7105 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7106 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7107 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7108 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7109 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7110 #define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7111 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7112 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7113 #define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7114 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7115 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7116 #define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7117 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7118 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7119 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7120 #define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7121 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7122 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7123 #define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7124 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7125 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7126 #define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7127 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7128 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7129 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7130 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7131 #define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7132 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7133 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7134 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7135 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7136 #define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7137 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7138 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7139 #define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7140 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7141 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7142 #define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7143 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7144 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7145 #define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7146 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7147 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7148 #define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7149 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7150 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7151 #define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7152 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7153 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7154 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7155 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7156 #define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7157 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7158 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7159 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7160 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7161 #define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7162 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7163 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7164 #define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7165 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7166 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7167 #define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7168 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7169 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7170 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7171 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7172 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7173 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7174 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7175 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7176 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
7177 #if 0
7178 POWERPC_SVR_8610 = xxx,
7179 #endif
7180 POWERPC_SVR_8641 = 0x80900021,
7181 POWERPC_SVR_8641D = 0x80900121,
7182 };
7183
7184 /*****************************************************************************/
7185 /* PowerPC CPU definitions */
7186 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
7187 { \
7188 .name = _name, \
7189 .pvr = _pvr, \
7190 .svr = _svr, \
7191 .insns_flags = glue(POWERPC_INSNS_,_type), \
7192 .msr_mask = glue(POWERPC_MSRM_,_type), \
7193 .mmu_model = glue(POWERPC_MMU_,_type), \
7194 .excp_model = glue(POWERPC_EXCP_,_type), \
7195 .bus_model = glue(POWERPC_INPUT_,_type), \
7196 .bfd_mach = glue(POWERPC_BFDM_,_type), \
7197 .flags = glue(POWERPC_FLAG_,_type), \
7198 .init_proc = &glue(init_proc_,_type), \
7199 .check_pow = &glue(check_pow_,_type), \
7200 }
7201 #define POWERPC_DEF(_name, _pvr, _type) \
7202 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
7203
7204 static const ppc_def_t ppc_defs[] = {
7205 /* Embedded PowerPC */
7206 /* PowerPC 401 family */
7207 /* Generic PowerPC 401 */
7208 POWERPC_DEF("401", CPU_POWERPC_401, 401),
7209 /* PowerPC 401 cores */
7210 /* PowerPC 401A1 */
7211 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
7212 /* PowerPC 401B2 */
7213 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
7214 #if defined (TODO)
7215 /* PowerPC 401B3 */
7216 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
7217 #endif
7218 /* PowerPC 401C2 */
7219 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
7220 /* PowerPC 401D2 */
7221 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
7222 /* PowerPC 401E2 */
7223 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
7224 /* PowerPC 401F2 */
7225 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
7226 /* PowerPC 401G2 */
7227 /* XXX: to be checked */
7228 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
7229 /* PowerPC 401 microcontrolers */
7230 #if defined (TODO)
7231 /* PowerPC 401GF */
7232 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
7233 #endif
7234 /* IOP480 (401 microcontroler) */
7235 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
7236 /* IBM Processor for Network Resources */
7237 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
7238 #if defined (TODO)
7239 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
7240 #endif
7241 /* PowerPC 403 family */
7242 /* Generic PowerPC 403 */
7243 POWERPC_DEF("403", CPU_POWERPC_403, 403),
7244 /* PowerPC 403 microcontrolers */
7245 /* PowerPC 403 GA */
7246 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
7247 /* PowerPC 403 GB */
7248 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
7249 /* PowerPC 403 GC */
7250 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
7251 /* PowerPC 403 GCX */
7252 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
7253 #if defined (TODO)
7254 /* PowerPC 403 GP */
7255 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
7256 #endif
7257 /* PowerPC 405 family */
7258 /* Generic PowerPC 405 */
7259 POWERPC_DEF("405", CPU_POWERPC_405, 405),
7260 /* PowerPC 405 cores */
7261 #if defined (TODO)
7262 /* PowerPC 405 A3 */
7263 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
7264 #endif
7265 #if defined (TODO)
7266 /* PowerPC 405 A4 */
7267 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
7268 #endif
7269 #if defined (TODO)
7270 /* PowerPC 405 B3 */
7271 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
7272 #endif
7273 #if defined (TODO)
7274 /* PowerPC 405 B4 */
7275 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
7276 #endif
7277 #if defined (TODO)
7278 /* PowerPC 405 C3 */
7279 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
7280 #endif
7281 #if defined (TODO)
7282 /* PowerPC 405 C4 */
7283 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
7284 #endif
7285 /* PowerPC 405 D2 */
7286 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
7287 #if defined (TODO)
7288 /* PowerPC 405 D3 */
7289 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
7290 #endif
7291 /* PowerPC 405 D4 */
7292 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
7293 #if defined (TODO)
7294 /* PowerPC 405 D5 */
7295 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
7296 #endif
7297 #if defined (TODO)
7298 /* PowerPC 405 E4 */
7299 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
7300 #endif
7301 #if defined (TODO)
7302 /* PowerPC 405 F4 */
7303 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
7304 #endif
7305 #if defined (TODO)
7306 /* PowerPC 405 F5 */
7307 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
7308 #endif
7309 #if defined (TODO)
7310 /* PowerPC 405 F6 */
7311 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
7312 #endif
7313 /* PowerPC 405 microcontrolers */
7314 /* PowerPC 405 CR */
7315 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
7316 /* PowerPC 405 CRa */
7317 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
7318 /* PowerPC 405 CRb */
7319 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
7320 /* PowerPC 405 CRc */
7321 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
7322 /* PowerPC 405 EP */
7323 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
7324 #if defined(TODO)
7325 /* PowerPC 405 EXr */
7326 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
7327 #endif
7328 /* PowerPC 405 EZ */
7329 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
7330 #if defined(TODO)
7331 /* PowerPC 405 FX */
7332 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
7333 #endif
7334 /* PowerPC 405 GP */
7335 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
7336 /* PowerPC 405 GPa */
7337 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
7338 /* PowerPC 405 GPb */
7339 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
7340 /* PowerPC 405 GPc */
7341 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
7342 /* PowerPC 405 GPd */
7343 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
7344 /* PowerPC 405 GPe */
7345 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
7346 /* PowerPC 405 GPR */
7347 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
7348 #if defined(TODO)
7349 /* PowerPC 405 H */
7350 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
7351 #endif
7352 #if defined(TODO)
7353 /* PowerPC 405 L */
7354 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
7355 #endif
7356 /* PowerPC 405 LP */
7357 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
7358 #if defined(TODO)
7359 /* PowerPC 405 PM */
7360 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
7361 #endif
7362 #if defined(TODO)
7363 /* PowerPC 405 PS */
7364 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
7365 #endif
7366 #if defined(TODO)
7367 /* PowerPC 405 S */
7368 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
7369 #endif
7370 /* Npe405 H */
7371 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
7372 /* Npe405 H2 */
7373 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
7374 /* Npe405 L */
7375 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
7376 /* Npe4GS3 */
7377 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
7378 #if defined (TODO)
7379 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
7380 #endif
7381 #if defined (TODO)
7382 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
7383 #endif
7384 #if defined (TODO)
7385 /* PowerPC LC77700 (Sanyo) */
7386 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
7387 #endif
7388 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7389 #if defined (TODO)
7390 /* STB010000 */
7391 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
7392 #endif
7393 #if defined (TODO)
7394 /* STB01010 */
7395 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
7396 #endif
7397 #if defined (TODO)
7398 /* STB0210 */
7399 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
7400 #endif
7401 /* STB03xx */
7402 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
7403 #if defined (TODO)
7404 /* STB043x */
7405 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
7406 #endif
7407 #if defined (TODO)
7408 /* STB045x */
7409 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
7410 #endif
7411 /* STB04xx */
7412 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
7413 /* STB25xx */
7414 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
7415 #if defined (TODO)
7416 /* STB130 */
7417 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
7418 #endif
7419 /* Xilinx PowerPC 405 cores */
7420 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
7421 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
7422 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
7423 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
7424 #if defined (TODO)
7425 /* Zarlink ZL10310 */
7426 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
7427 #endif
7428 #if defined (TODO)
7429 /* Zarlink ZL10311 */
7430 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
7431 #endif
7432 #if defined (TODO)
7433 /* Zarlink ZL10320 */
7434 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
7435 #endif
7436 #if defined (TODO)
7437 /* Zarlink ZL10321 */
7438 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
7439 #endif
7440 /* PowerPC 440 family */
7441 #if defined(TODO_USER_ONLY)
7442 /* Generic PowerPC 440 */
7443 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
7444 #endif
7445 /* PowerPC 440 cores */
7446 #if defined (TODO)
7447 /* PowerPC 440 A4 */
7448 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
7449 #endif
7450 #if defined (TODO)
7451 /* PowerPC 440 A5 */
7452 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
7453 #endif
7454 #if defined (TODO)
7455 /* PowerPC 440 B4 */
7456 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
7457 #endif
7458 #if defined (TODO)
7459 /* PowerPC 440 G4 */
7460 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
7461 #endif
7462 #if defined (TODO)
7463 /* PowerPC 440 F5 */
7464 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
7465 #endif
7466 #if defined (TODO)
7467 /* PowerPC 440 G5 */
7468 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
7469 #endif
7470 #if defined (TODO)
7471 /* PowerPC 440H4 */
7472 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
7473 #endif
7474 #if defined (TODO)
7475 /* PowerPC 440H6 */
7476 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
7477 #endif
7478 /* PowerPC 440 microcontrolers */
7479 #if defined(TODO_USER_ONLY)
7480 /* PowerPC 440 EP */
7481 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
7482 #endif
7483 #if defined(TODO_USER_ONLY)
7484 /* PowerPC 440 EPa */
7485 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
7486 #endif
7487 #if defined(TODO_USER_ONLY)
7488 /* PowerPC 440 EPb */
7489 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
7490 #endif
7491 #if defined(TODO_USER_ONLY)
7492 /* PowerPC 440 EPX */
7493 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
7494 #endif
7495 #if defined(TODO_USER_ONLY)
7496 /* PowerPC 440 GP */
7497 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
7498 #endif
7499 #if defined(TODO_USER_ONLY)
7500 /* PowerPC 440 GPb */
7501 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
7502 #endif
7503 #if defined(TODO_USER_ONLY)
7504 /* PowerPC 440 GPc */
7505 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
7506 #endif
7507 #if defined(TODO_USER_ONLY)
7508 /* PowerPC 440 GR */
7509 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
7510 #endif
7511 #if defined(TODO_USER_ONLY)
7512 /* PowerPC 440 GRa */
7513 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
7514 #endif
7515 #if defined(TODO_USER_ONLY)
7516 /* PowerPC 440 GRX */
7517 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
7518 #endif
7519 #if defined(TODO_USER_ONLY)
7520 /* PowerPC 440 GX */
7521 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
7522 #endif
7523 #if defined(TODO_USER_ONLY)
7524 /* PowerPC 440 GXa */
7525 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
7526 #endif
7527 #if defined(TODO_USER_ONLY)
7528 /* PowerPC 440 GXb */
7529 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
7530 #endif
7531 #if defined(TODO_USER_ONLY)
7532 /* PowerPC 440 GXc */
7533 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
7534 #endif
7535 #if defined(TODO_USER_ONLY)
7536 /* PowerPC 440 GXf */
7537 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
7538 #endif
7539 #if defined(TODO)
7540 /* PowerPC 440 S */
7541 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
7542 #endif
7543 #if defined(TODO_USER_ONLY)
7544 /* PowerPC 440 SP */
7545 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
7546 #endif
7547 #if defined(TODO_USER_ONLY)
7548 /* PowerPC 440 SP2 */
7549 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
7550 #endif
7551 #if defined(TODO_USER_ONLY)
7552 /* PowerPC 440 SPE */
7553 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
7554 #endif
7555 /* PowerPC 460 family */
7556 #if defined (TODO)
7557 /* Generic PowerPC 464 */
7558 POWERPC_DEF("464", CPU_POWERPC_464, 460),
7559 #endif
7560 /* PowerPC 464 microcontrolers */
7561 #if defined (TODO)
7562 /* PowerPC 464H90 */
7563 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
7564 #endif
7565 #if defined (TODO)
7566 /* PowerPC 464H90F */
7567 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
7568 #endif
7569 /* Freescale embedded PowerPC cores */
7570 /* MPC5xx family (aka RCPU) */
7571 #if defined(TODO_USER_ONLY)
7572 /* Generic MPC5xx core */
7573 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
7574 #endif
7575 #if defined(TODO_USER_ONLY)
7576 /* Codename for MPC5xx core */
7577 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
7578 #endif
7579 /* MPC5xx microcontrollers */
7580 #if defined(TODO_USER_ONLY)
7581 /* MGT560 */
7582 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
7583 #endif
7584 #if defined(TODO_USER_ONLY)
7585 /* MPC509 */
7586 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
7587 #endif
7588 #if defined(TODO_USER_ONLY)
7589 /* MPC533 */
7590 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
7591 #endif
7592 #if defined(TODO_USER_ONLY)
7593 /* MPC534 */
7594 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
7595 #endif
7596 #if defined(TODO_USER_ONLY)
7597 /* MPC555 */
7598 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
7599 #endif
7600 #if defined(TODO_USER_ONLY)
7601 /* MPC556 */
7602 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
7603 #endif
7604 #if defined(TODO_USER_ONLY)
7605 /* MPC560 */
7606 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
7607 #endif
7608 #if defined(TODO_USER_ONLY)
7609 /* MPC561 */
7610 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
7611 #endif
7612 #if defined(TODO_USER_ONLY)
7613 /* MPC562 */
7614 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
7615 #endif
7616 #if defined(TODO_USER_ONLY)
7617 /* MPC563 */
7618 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
7619 #endif
7620 #if defined(TODO_USER_ONLY)
7621 /* MPC564 */
7622 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
7623 #endif
7624 #if defined(TODO_USER_ONLY)
7625 /* MPC565 */
7626 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
7627 #endif
7628 #if defined(TODO_USER_ONLY)
7629 /* MPC566 */
7630 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
7631 #endif
7632 /* MPC8xx family (aka PowerQUICC) */
7633 #if defined(TODO_USER_ONLY)
7634 /* Generic MPC8xx core */
7635 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
7636 #endif
7637 #if defined(TODO_USER_ONLY)
7638 /* Codename for MPC8xx core */
7639 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
7640 #endif
7641 /* MPC8xx microcontrollers */
7642 #if defined(TODO_USER_ONLY)
7643 /* MGT823 */
7644 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
7645 #endif
7646 #if defined(TODO_USER_ONLY)
7647 /* MPC821 */
7648 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
7649 #endif
7650 #if defined(TODO_USER_ONLY)
7651 /* MPC823 */
7652 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
7653 #endif
7654 #if defined(TODO_USER_ONLY)
7655 /* MPC850 */
7656 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
7657 #endif
7658 #if defined(TODO_USER_ONLY)
7659 /* MPC852T */
7660 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
7661 #endif
7662 #if defined(TODO_USER_ONLY)
7663 /* MPC855T */
7664 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
7665 #endif
7666 #if defined(TODO_USER_ONLY)
7667 /* MPC857 */
7668 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
7669 #endif
7670 #if defined(TODO_USER_ONLY)
7671 /* MPC859 */
7672 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
7673 #endif
7674 #if defined(TODO_USER_ONLY)
7675 /* MPC860 */
7676 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
7677 #endif
7678 #if defined(TODO_USER_ONLY)
7679 /* MPC862 */
7680 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
7681 #endif
7682 #if defined(TODO_USER_ONLY)
7683 /* MPC866 */
7684 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
7685 #endif
7686 #if defined(TODO_USER_ONLY)
7687 /* MPC870 */
7688 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
7689 #endif
7690 #if defined(TODO_USER_ONLY)
7691 /* MPC875 */
7692 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
7693 #endif
7694 #if defined(TODO_USER_ONLY)
7695 /* MPC880 */
7696 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
7697 #endif
7698 #if defined(TODO_USER_ONLY)
7699 /* MPC885 */
7700 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
7701 #endif
7702 /* MPC82xx family (aka PowerQUICC-II) */
7703 /* Generic MPC52xx core */
7704 POWERPC_DEF_SVR("MPC52xx",
7705 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
7706 /* Generic MPC82xx core */
7707 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
7708 /* Codename for MPC82xx */
7709 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
7710 /* PowerPC G2 core */
7711 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
7712 /* PowerPC G2 H4 core */
7713 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
7714 /* PowerPC G2 GP core */
7715 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
7716 /* PowerPC G2 LS core */
7717 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
7718 /* PowerPC G2 HiP3 core */
7719 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
7720 /* PowerPC G2 HiP4 core */
7721 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
7722 /* PowerPC MPC603 core */
7723 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
7724 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
7725 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
7726 /* PowerPC G2LE GP core */
7727 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
7728 /* PowerPC G2LE LS core */
7729 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
7730 /* PowerPC G2LE GP1 core */
7731 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
7732 /* PowerPC G2LE GP3 core */
7733 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
7734 /* PowerPC MPC603 microcontrollers */
7735 /* MPC8240 */
7736 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
7737 /* PowerPC G2 microcontrollers */
7738 #if defined(TODO)
7739 /* MPC5121 */
7740 POWERPC_DEF_SVR("MPC5121",
7741 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
7742 #endif
7743 /* MPC5200 */
7744 POWERPC_DEF_SVR("MPC5200",
7745 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
7746 /* MPC5200 v1.0 */
7747 POWERPC_DEF_SVR("MPC5200_v10",
7748 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
7749 /* MPC5200 v1.1 */
7750 POWERPC_DEF_SVR("MPC5200_v11",
7751 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
7752 /* MPC5200 v1.2 */
7753 POWERPC_DEF_SVR("MPC5200_v12",
7754 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
7755 /* MPC5200B */
7756 POWERPC_DEF_SVR("MPC5200B",
7757 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
7758 /* MPC5200B v2.0 */
7759 POWERPC_DEF_SVR("MPC5200B_v20",
7760 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
7761 /* MPC5200B v2.1 */
7762 POWERPC_DEF_SVR("MPC5200B_v21",
7763 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
7764 /* MPC8241 */
7765 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
7766 /* MPC8245 */
7767 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
7768 /* MPC8247 */
7769 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
7770 /* MPC8248 */
7771 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
7772 /* MPC8250 */
7773 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
7774 /* MPC8250 HiP3 */
7775 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
7776 /* MPC8250 HiP4 */
7777 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
7778 /* MPC8255 */
7779 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
7780 /* MPC8255 HiP3 */
7781 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
7782 /* MPC8255 HiP4 */
7783 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
7784 /* MPC8260 */
7785 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
7786 /* MPC8260 HiP3 */
7787 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
7788 /* MPC8260 HiP4 */
7789 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
7790 /* MPC8264 */
7791 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
7792 /* MPC8264 HiP3 */
7793 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
7794 /* MPC8264 HiP4 */
7795 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
7796 /* MPC8265 */
7797 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
7798 /* MPC8265 HiP3 */
7799 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
7800 /* MPC8265 HiP4 */
7801 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
7802 /* MPC8266 */
7803 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
7804 /* MPC8266 HiP3 */
7805 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
7806 /* MPC8266 HiP4 */
7807 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
7808 /* MPC8270 */
7809 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
7810 /* MPC8271 */
7811 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
7812 /* MPC8272 */
7813 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
7814 /* MPC8275 */
7815 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
7816 /* MPC8280 */
7817 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
7818 /* e200 family */
7819 /* Generic PowerPC e200 core */
7820 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
7821 /* Generic MPC55xx core */
7822 #if defined (TODO)
7823 POWERPC_DEF_SVR("MPC55xx",
7824 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
7825 #endif
7826 #if defined (TODO)
7827 /* PowerPC e200z0 core */
7828 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
7829 #endif
7830 #if defined (TODO)
7831 /* PowerPC e200z1 core */
7832 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
7833 #endif
7834 #if defined (TODO)
7835 /* PowerPC e200z3 core */
7836 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
7837 #endif
7838 /* PowerPC e200z5 core */
7839 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
7840 /* PowerPC e200z6 core */
7841 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
7842 /* PowerPC e200 microcontrollers */
7843 #if defined (TODO)
7844 /* MPC5514E */
7845 POWERPC_DEF_SVR("MPC5514E",
7846 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
7847 #endif
7848 #if defined (TODO)
7849 /* MPC5514E v0 */
7850 POWERPC_DEF_SVR("MPC5514E_v0",
7851 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
7852 #endif
7853 #if defined (TODO)
7854 /* MPC5514E v1 */
7855 POWERPC_DEF_SVR("MPC5514E_v1",
7856 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
7857 #endif
7858 #if defined (TODO)
7859 /* MPC5514G */
7860 POWERPC_DEF_SVR("MPC5514G",
7861 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
7862 #endif
7863 #if defined (TODO)
7864 /* MPC5514G v0 */
7865 POWERPC_DEF_SVR("MPC5514G_v0",
7866 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
7867 #endif
7868 #if defined (TODO)
7869 /* MPC5514G v1 */
7870 POWERPC_DEF_SVR("MPC5514G_v1",
7871 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
7872 #endif
7873 #if defined (TODO)
7874 /* MPC5515S */
7875 POWERPC_DEF_SVR("MPC5515S",
7876 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
7877 #endif
7878 #if defined (TODO)
7879 /* MPC5516E */
7880 POWERPC_DEF_SVR("MPC5516E",
7881 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
7882 #endif
7883 #if defined (TODO)
7884 /* MPC5516E v0 */
7885 POWERPC_DEF_SVR("MPC5516E_v0",
7886 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
7887 #endif
7888 #if defined (TODO)
7889 /* MPC5516E v1 */
7890 POWERPC_DEF_SVR("MPC5516E_v1",
7891 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
7892 #endif
7893 #if defined (TODO)
7894 /* MPC5516G */
7895 POWERPC_DEF_SVR("MPC5516G",
7896 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
7897 #endif
7898 #if defined (TODO)
7899 /* MPC5516G v0 */
7900 POWERPC_DEF_SVR("MPC5516G_v0",
7901 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
7902 #endif
7903 #if defined (TODO)
7904 /* MPC5516G v1 */
7905 POWERPC_DEF_SVR("MPC5516G_v1",
7906 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
7907 #endif
7908 #if defined (TODO)
7909 /* MPC5516S */
7910 POWERPC_DEF_SVR("MPC5516S",
7911 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
7912 #endif
7913 #if defined (TODO)
7914 /* MPC5533 */
7915 POWERPC_DEF_SVR("MPC5533",
7916 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
7917 #endif
7918 #if defined (TODO)
7919 /* MPC5534 */
7920 POWERPC_DEF_SVR("MPC5534",
7921 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
7922 #endif
7923 #if defined (TODO)
7924 /* MPC5553 */
7925 POWERPC_DEF_SVR("MPC5553",
7926 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
7927 #endif
7928 #if defined (TODO)
7929 /* MPC5554 */
7930 POWERPC_DEF_SVR("MPC5554",
7931 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
7932 #endif
7933 #if defined (TODO)
7934 /* MPC5561 */
7935 POWERPC_DEF_SVR("MPC5561",
7936 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
7937 #endif
7938 #if defined (TODO)
7939 /* MPC5565 */
7940 POWERPC_DEF_SVR("MPC5565",
7941 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
7942 #endif
7943 #if defined (TODO)
7944 /* MPC5566 */
7945 POWERPC_DEF_SVR("MPC5566",
7946 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
7947 #endif
7948 #if defined (TODO)
7949 /* MPC5567 */
7950 POWERPC_DEF_SVR("MPC5567",
7951 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
7952 #endif
7953 /* e300 family */
7954 /* Generic PowerPC e300 core */
7955 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
7956 /* PowerPC e300c1 core */
7957 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
7958 /* PowerPC e300c2 core */
7959 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
7960 /* PowerPC e300c3 core */
7961 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
7962 /* PowerPC e300c4 core */
7963 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
7964 /* PowerPC e300 microcontrollers */
7965 #if defined (TODO)
7966 /* MPC8313 */
7967 POWERPC_DEF_SVR("MPC8313",
7968 CPU_POWERPC_MPC8313, POWERPC_SVR_8313, e300),
7969 #endif
7970 #if defined (TODO)
7971 /* MPC8313E */
7972 POWERPC_DEF_SVR("MPC8313E",
7973 CPU_POWERPC_MPC8313E, POWERPC_SVR_8313E, e300),
7974 #endif
7975 #if defined (TODO)
7976 /* MPC8314 */
7977 POWERPC_DEF_SVR("MPC8314",
7978 CPU_POWERPC_MPC8314, POWERPC_SVR_8314, e300),
7979 #endif
7980 #if defined (TODO)
7981 /* MPC8314E */
7982 POWERPC_DEF_SVR("MPC8314E",
7983 CPU_POWERPC_MPC8314E, POWERPC_SVR_8314E, e300),
7984 #endif
7985 #if defined (TODO)
7986 /* MPC8315 */
7987 POWERPC_DEF_SVR("MPC8315",
7988 CPU_POWERPC_MPC8315, POWERPC_SVR_8315, e300),
7989 #endif
7990 #if defined (TODO)
7991 /* MPC8315E */
7992 POWERPC_DEF_SVR("MPC8315E",
7993 CPU_POWERPC_MPC8315E, POWERPC_SVR_8315E, e300),
7994 #endif
7995 #if defined (TODO)
7996 /* MPC8321 */
7997 POWERPC_DEF_SVR("MPC8321",
7998 CPU_POWERPC_MPC8321, POWERPC_SVR_8321, e300),
7999 #endif
8000 #if defined (TODO)
8001 /* MPC8321E */
8002 POWERPC_DEF_SVR("MPC8321E",
8003 CPU_POWERPC_MPC8321E, POWERPC_SVR_8321E, e300),
8004 #endif
8005 #if defined (TODO)
8006 /* MPC8323 */
8007 POWERPC_DEF_SVR("MPC8323",
8008 CPU_POWERPC_MPC8323, POWERPC_SVR_8323, e300),
8009 #endif
8010 #if defined (TODO)
8011 /* MPC8323E */
8012 POWERPC_DEF_SVR("MPC8323E",
8013 CPU_POWERPC_MPC8323E, POWERPC_SVR_8323E, e300),
8014 #endif
8015 /* MPC8343A */
8016 POWERPC_DEF_SVR("MPC8343A",
8017 CPU_POWERPC_MPC8343A, POWERPC_SVR_8343A, e300),
8018 /* MPC8343EA */
8019 POWERPC_DEF_SVR("MPC8343EA",
8020 CPU_POWERPC_MPC8343EA, POWERPC_SVR_8343EA, e300),
8021 /* MPC8347A */
8022 POWERPC_DEF_SVR("MPC8347A",
8023 CPU_POWERPC_MPC8347A, POWERPC_SVR_8347A, e300),
8024 /* MPC8347AT */
8025 POWERPC_DEF_SVR("MPC8347AT",
8026 CPU_POWERPC_MPC8347AT, POWERPC_SVR_8347AT, e300),
8027 /* MPC8347AP */
8028 POWERPC_DEF_SVR("MPC8347AP",
8029 CPU_POWERPC_MPC8347AP, POWERPC_SVR_8347AP, e300),
8030 /* MPC8347EA */
8031 POWERPC_DEF_SVR("MPC8347EA",
8032 CPU_POWERPC_MPC8347EA, POWERPC_SVR_8347EA, e300),
8033 /* MPC8347EAT */
8034 POWERPC_DEF_SVR("MPC8347EAT",
8035 CPU_POWERPC_MPC8347EAT, POWERPC_SVR_8347EAT, e300),
8036 /* MPC8343EAP */
8037 POWERPC_DEF_SVR("MPC8347EAP",
8038 CPU_POWERPC_MPC8347EAP, POWERPC_SVR_8347EAP, e300),
8039 /* MPC8349 */
8040 POWERPC_DEF_SVR("MPC8349",
8041 CPU_POWERPC_MPC8349, POWERPC_SVR_8349, e300),
8042 /* MPC8349A */
8043 POWERPC_DEF_SVR("MPC8349A",
8044 CPU_POWERPC_MPC8349A, POWERPC_SVR_8349A, e300),
8045 /* MPC8349E */
8046 POWERPC_DEF_SVR("MPC8349E",
8047 CPU_POWERPC_MPC8349E, POWERPC_SVR_8349E, e300),
8048 /* MPC8349EA */
8049 POWERPC_DEF_SVR("MPC8349EA",
8050 CPU_POWERPC_MPC8349EA, POWERPC_SVR_8349EA, e300),
8051 #if defined (TODO)
8052 /* MPC8358E */
8053 POWERPC_DEF_SVR("MPC8358E",
8054 CPU_POWERPC_MPC8358E, POWERPC_SVR_8358E, e300),
8055 #endif
8056 #if defined (TODO)
8057 /* MPC8360E */
8058 POWERPC_DEF_SVR("MPC8360E",
8059 CPU_POWERPC_MPC8360E, POWERPC_SVR_8360E, e300),
8060 #endif
8061 /* MPC8377 */
8062 POWERPC_DEF_SVR("MPC8377",
8063 CPU_POWERPC_MPC8377, POWERPC_SVR_8377, e300),
8064 /* MPC8377E */
8065 POWERPC_DEF_SVR("MPC8377E",
8066 CPU_POWERPC_MPC8377E, POWERPC_SVR_8377E, e300),
8067 /* MPC8378 */
8068 POWERPC_DEF_SVR("MPC8378",
8069 CPU_POWERPC_MPC8378, POWERPC_SVR_8378, e300),
8070 /* MPC8378E */
8071 POWERPC_DEF_SVR("MPC8378E",
8072 CPU_POWERPC_MPC8378E, POWERPC_SVR_8378E, e300),
8073 /* MPC8379 */
8074 POWERPC_DEF_SVR("MPC8379",
8075 CPU_POWERPC_MPC8379, POWERPC_SVR_8379, e300),
8076 /* MPC8379E */
8077 POWERPC_DEF_SVR("MPC8379E",
8078 CPU_POWERPC_MPC8379E, POWERPC_SVR_8379E, e300),
8079 /* e500 family */
8080 /* PowerPC e500 core */
8081 POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
8082 /* PowerPC e500v1 core */
8083 POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
8084 /* PowerPC e500 v1.0 core */
8085 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
8086 /* PowerPC e500 v2.0 core */
8087 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
8088 /* PowerPC e500v2 core */
8089 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
8090 /* PowerPC e500v2 v1.0 core */
8091 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
8092 /* PowerPC e500v2 v2.0 core */
8093 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
8094 /* PowerPC e500v2 v2.1 core */
8095 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
8096 /* PowerPC e500v2 v2.2 core */
8097 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
8098 /* PowerPC e500v2 v3.0 core */
8099 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
8100 /* PowerPC e500 microcontrollers */
8101 /* MPC8533 */
8102 POWERPC_DEF_SVR("MPC8533",
8103 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2),
8104 /* MPC8533 v1.0 */
8105 POWERPC_DEF_SVR("MPC8533_v10",
8106 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2),
8107 /* MPC8533 v1.1 */
8108 POWERPC_DEF_SVR("MPC8533_v11",
8109 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2),
8110 /* MPC8533E */
8111 POWERPC_DEF_SVR("MPC8533E",
8112 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2),
8113 /* MPC8533E v1.0 */
8114 POWERPC_DEF_SVR("MPC8533E_v10",
8115 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
8116 POWERPC_DEF_SVR("MPC8533E_v11",
8117 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
8118 /* MPC8540 */
8119 POWERPC_DEF_SVR("MPC8540",
8120 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1),
8121 /* MPC8540 v1.0 */
8122 POWERPC_DEF_SVR("MPC8540_v10",
8123 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1),
8124 /* MPC8540 v2.0 */
8125 POWERPC_DEF_SVR("MPC8540_v20",
8126 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1),
8127 /* MPC8540 v2.1 */
8128 POWERPC_DEF_SVR("MPC8540_v21",
8129 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1),
8130 /* MPC8541 */
8131 POWERPC_DEF_SVR("MPC8541",
8132 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1),
8133 /* MPC8541 v1.0 */
8134 POWERPC_DEF_SVR("MPC8541_v10",
8135 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1),
8136 /* MPC8541 v1.1 */
8137 POWERPC_DEF_SVR("MPC8541_v11",
8138 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1),
8139 /* MPC8541E */
8140 POWERPC_DEF_SVR("MPC8541E",
8141 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1),
8142 /* MPC8541E v1.0 */
8143 POWERPC_DEF_SVR("MPC8541E_v10",
8144 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
8145 /* MPC8541E v1.1 */
8146 POWERPC_DEF_SVR("MPC8541E_v11",
8147 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
8148 /* MPC8543 */
8149 POWERPC_DEF_SVR("MPC8543",
8150 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2),
8151 /* MPC8543 v1.0 */
8152 POWERPC_DEF_SVR("MPC8543_v10",
8153 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2),
8154 /* MPC8543 v1.1 */
8155 POWERPC_DEF_SVR("MPC8543_v11",
8156 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2),
8157 /* MPC8543 v2.0 */
8158 POWERPC_DEF_SVR("MPC8543_v20",
8159 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2),
8160 /* MPC8543 v2.1 */
8161 POWERPC_DEF_SVR("MPC8543_v21",
8162 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2),
8163 /* MPC8543E */
8164 POWERPC_DEF_SVR("MPC8543E",
8165 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2),
8166 /* MPC8543E v1.0 */
8167 POWERPC_DEF_SVR("MPC8543E_v10",
8168 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
8169 /* MPC8543E v1.1 */
8170 POWERPC_DEF_SVR("MPC8543E_v11",
8171 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
8172 /* MPC8543E v2.0 */
8173 POWERPC_DEF_SVR("MPC8543E_v20",
8174 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
8175 /* MPC8543E v2.1 */
8176 POWERPC_DEF_SVR("MPC8543E_v21",
8177 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
8178 /* MPC8544 */
8179 POWERPC_DEF_SVR("MPC8544",
8180 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2),
8181 /* MPC8544 v1.0 */
8182 POWERPC_DEF_SVR("MPC8544_v10",
8183 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2),
8184 /* MPC8544 v1.1 */
8185 POWERPC_DEF_SVR("MPC8544_v11",
8186 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2),
8187 /* MPC8544E */
8188 POWERPC_DEF_SVR("MPC8544E",
8189 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2),
8190 /* MPC8544E v1.0 */
8191 POWERPC_DEF_SVR("MPC8544E_v10",
8192 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
8193 /* MPC8544E v1.1 */
8194 POWERPC_DEF_SVR("MPC8544E_v11",
8195 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
8196 /* MPC8545 */
8197 POWERPC_DEF_SVR("MPC8545",
8198 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2),
8199 /* MPC8545 v2.0 */
8200 POWERPC_DEF_SVR("MPC8545_v20",
8201 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2),
8202 /* MPC8545 v2.1 */
8203 POWERPC_DEF_SVR("MPC8545_v21",
8204 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2),
8205 /* MPC8545E */
8206 POWERPC_DEF_SVR("MPC8545E",
8207 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2),
8208 /* MPC8545E v2.0 */
8209 POWERPC_DEF_SVR("MPC8545E_v20",
8210 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
8211 /* MPC8545E v2.1 */
8212 POWERPC_DEF_SVR("MPC8545E_v21",
8213 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
8214 /* MPC8547E */
8215 POWERPC_DEF_SVR("MPC8547E",
8216 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2),
8217 /* MPC8547E v2.0 */
8218 POWERPC_DEF_SVR("MPC8547E_v20",
8219 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
8220 /* MPC8547E v2.1 */
8221 POWERPC_DEF_SVR("MPC8547E_v21",
8222 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
8223 /* MPC8548 */
8224 POWERPC_DEF_SVR("MPC8548",
8225 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2),
8226 /* MPC8548 v1.0 */
8227 POWERPC_DEF_SVR("MPC8548_v10",
8228 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2),
8229 /* MPC8548 v1.1 */
8230 POWERPC_DEF_SVR("MPC8548_v11",
8231 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2),
8232 /* MPC8548 v2.0 */
8233 POWERPC_DEF_SVR("MPC8548_v20",
8234 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2),
8235 /* MPC8548 v2.1 */
8236 POWERPC_DEF_SVR("MPC8548_v21",
8237 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2),
8238 /* MPC8548E */
8239 POWERPC_DEF_SVR("MPC8548E",
8240 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2),
8241 /* MPC8548E v1.0 */
8242 POWERPC_DEF_SVR("MPC8548E_v10",
8243 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
8244 /* MPC8548E v1.1 */
8245 POWERPC_DEF_SVR("MPC8548E_v11",
8246 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
8247 /* MPC8548E v2.0 */
8248 POWERPC_DEF_SVR("MPC8548E_v20",
8249 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
8250 /* MPC8548E v2.1 */
8251 POWERPC_DEF_SVR("MPC8548E_v21",
8252 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
8253 /* MPC8555 */
8254 POWERPC_DEF_SVR("MPC8555",
8255 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2),
8256 /* MPC8555 v1.0 */
8257 POWERPC_DEF_SVR("MPC8555_v10",
8258 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2),
8259 /* MPC8555 v1.1 */
8260 POWERPC_DEF_SVR("MPC8555_v11",
8261 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2),
8262 /* MPC8555E */
8263 POWERPC_DEF_SVR("MPC8555E",
8264 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2),
8265 /* MPC8555E v1.0 */
8266 POWERPC_DEF_SVR("MPC8555E_v10",
8267 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
8268 /* MPC8555E v1.1 */
8269 POWERPC_DEF_SVR("MPC8555E_v11",
8270 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
8271 /* MPC8560 */
8272 POWERPC_DEF_SVR("MPC8560",
8273 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2),
8274 /* MPC8560 v1.0 */
8275 POWERPC_DEF_SVR("MPC8560_v10",
8276 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2),
8277 /* MPC8560 v2.0 */
8278 POWERPC_DEF_SVR("MPC8560_v20",
8279 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2),
8280 /* MPC8560 v2.1 */
8281 POWERPC_DEF_SVR("MPC8560_v21",
8282 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2),
8283 /* MPC8567 */
8284 POWERPC_DEF_SVR("MPC8567",
8285 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2),
8286 /* MPC8567E */
8287 POWERPC_DEF_SVR("MPC8567E",
8288 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2),
8289 /* MPC8568 */
8290 POWERPC_DEF_SVR("MPC8568",
8291 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2),
8292 /* MPC8568E */
8293 POWERPC_DEF_SVR("MPC8568E",
8294 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2),
8295 /* MPC8572 */
8296 POWERPC_DEF_SVR("MPC8572",
8297 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2),
8298 /* MPC8572E */
8299 POWERPC_DEF_SVR("MPC8572E",
8300 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
8301 /* e600 family */
8302 /* PowerPC e600 core */
8303 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
8304 /* PowerPC e600 microcontrollers */
8305 #if defined (TODO)
8306 /* MPC8610 */
8307 POWERPC_DEF_SVR("MPC8610",
8308 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
8309 #endif
8310 /* MPC8641 */
8311 POWERPC_DEF_SVR("MPC8641",
8312 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
8313 /* MPC8641D */
8314 POWERPC_DEF_SVR("MPC8641D",
8315 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
8316 /* 32 bits "classic" PowerPC */
8317 /* PowerPC 6xx family */
8318 /* PowerPC 601 */
8319 POWERPC_DEF("601", CPU_POWERPC_601, 601v),
8320 /* PowerPC 601v0 */
8321 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
8322 /* PowerPC 601v1 */
8323 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
8324 /* PowerPC 601v */
8325 POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
8326 /* PowerPC 601v2 */
8327 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
8328 /* PowerPC 602 */
8329 POWERPC_DEF("602", CPU_POWERPC_602, 602),
8330 /* PowerPC 603 */
8331 POWERPC_DEF("603", CPU_POWERPC_603, 603),
8332 /* Code name for PowerPC 603 */
8333 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
8334 /* PowerPC 603e (aka PID6) */
8335 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
8336 /* Code name for PowerPC 603e */
8337 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
8338 /* PowerPC 603e v1.1 */
8339 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
8340 /* PowerPC 603e v1.2 */
8341 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
8342 /* PowerPC 603e v1.3 */
8343 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
8344 /* PowerPC 603e v1.4 */
8345 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
8346 /* PowerPC 603e v2.2 */
8347 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
8348 /* PowerPC 603e v3 */
8349 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
8350 /* PowerPC 603e v4 */
8351 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
8352 /* PowerPC 603e v4.1 */
8353 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
8354 /* PowerPC 603e (aka PID7) */
8355 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
8356 /* PowerPC 603e7t */
8357 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
8358 /* PowerPC 603e7v */
8359 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
8360 /* Code name for PowerPC 603ev */
8361 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
8362 /* PowerPC 603e7v1 */
8363 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
8364 /* PowerPC 603e7v2 */
8365 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
8366 /* PowerPC 603p (aka PID7v) */
8367 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
8368 /* PowerPC 603r (aka PID7t) */
8369 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
8370 /* Code name for PowerPC 603r */
8371 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
8372 /* PowerPC 604 */
8373 POWERPC_DEF("604", CPU_POWERPC_604, 604),
8374 /* PowerPC 604e (aka PID9) */
8375 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
8376 /* Code name for PowerPC 604e */
8377 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
8378 /* PowerPC 604e v1.0 */
8379 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
8380 /* PowerPC 604e v2.2 */
8381 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
8382 /* PowerPC 604e v2.4 */
8383 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
8384 /* PowerPC 604r (aka PIDA) */
8385 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
8386 /* Code name for PowerPC 604r */
8387 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
8388 #if defined(TODO)
8389 /* PowerPC 604ev */
8390 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
8391 #endif
8392 /* PowerPC 7xx family */
8393 /* Generic PowerPC 740 (G3) */
8394 POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
8395 /* Code name for PowerPC 740 */
8396 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
8397 /* Generic PowerPC 750 (G3) */
8398 POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
8399 /* Code name for PowerPC 750 */
8400 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
8401 /* PowerPC 740/750 is also known as G3 */
8402 POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
8403 /* PowerPC 740 v1.0 (G3) */
8404 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
8405 /* PowerPC 750 v1.0 (G3) */
8406 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
8407 /* PowerPC 740 v2.0 (G3) */
8408 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
8409 /* PowerPC 750 v2.0 (G3) */
8410 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
8411 /* PowerPC 740 v2.1 (G3) */
8412 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
8413 /* PowerPC 750 v2.1 (G3) */
8414 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
8415 /* PowerPC 740 v2.2 (G3) */
8416 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
8417 /* PowerPC 750 v2.2 (G3) */
8418 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
8419 /* PowerPC 740 v3.0 (G3) */
8420 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
8421 /* PowerPC 750 v3.0 (G3) */
8422 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
8423 /* PowerPC 740 v3.1 (G3) */
8424 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
8425 /* PowerPC 750 v3.1 (G3) */
8426 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
8427 /* PowerPC 740E (G3) */
8428 POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
8429 /* PowerPC 750E (G3) */
8430 POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
8431 /* PowerPC 740P (G3) */
8432 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
8433 /* PowerPC 750P (G3) */
8434 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
8435 /* Code name for PowerPC 740P/750P (G3) */
8436 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
8437 /* PowerPC 750CL (G3 embedded) */
8438 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
8439 /* PowerPC 750CL v1.0 */
8440 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
8441 /* PowerPC 750CL v2.0 */
8442 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
8443 /* PowerPC 750CX (G3 embedded) */
8444 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
8445 /* PowerPC 750CX v1.0 (G3 embedded) */
8446 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
8447 /* PowerPC 750CX v2.1 (G3 embedded) */
8448 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
8449 /* PowerPC 750CX v2.1 (G3 embedded) */
8450 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
8451 /* PowerPC 750CX v2.2 (G3 embedded) */
8452 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
8453 /* PowerPC 750CXe (G3 embedded) */
8454 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
8455 /* PowerPC 750CXe v2.1 (G3 embedded) */
8456 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
8457 /* PowerPC 750CXe v2.2 (G3 embedded) */
8458 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
8459 /* PowerPC 750CXe v2.3 (G3 embedded) */
8460 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
8461 /* PowerPC 750CXe v2.4 (G3 embedded) */
8462 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
8463 /* PowerPC 750CXe v2.4b (G3 embedded) */
8464 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
8465 /* PowerPC 750CXe v3.0 (G3 embedded) */
8466 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
8467 /* PowerPC 750CXe v3.1 (G3 embedded) */
8468 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
8469 /* PowerPC 750CXe v3.1b (G3 embedded) */
8470 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
8471 /* PowerPC 750CXr (G3 embedded) */
8472 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
8473 /* PowerPC 750FL (G3 embedded) */
8474 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
8475 /* PowerPC 750FX (G3 embedded) */
8476 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
8477 /* PowerPC 750FX v1.0 (G3 embedded) */
8478 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
8479 /* PowerPC 750FX v2.0 (G3 embedded) */
8480 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
8481 /* PowerPC 750FX v2.1 (G3 embedded) */
8482 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
8483 /* PowerPC 750FX v2.2 (G3 embedded) */
8484 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
8485 /* PowerPC 750FX v2.3 (G3 embedded) */
8486 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
8487 /* PowerPC 750GL (G3 embedded) */
8488 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
8489 /* PowerPC 750GX (G3 embedded) */
8490 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
8491 /* PowerPC 750GX v1.0 (G3 embedded) */
8492 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
8493 /* PowerPC 750GX v1.1 (G3 embedded) */
8494 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
8495 /* PowerPC 750GX v1.2 (G3 embedded) */
8496 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
8497 /* PowerPC 750L (G3 embedded) */
8498 POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
8499 /* Code name for PowerPC 750L (G3 embedded) */
8500 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
8501 /* PowerPC 750L v2.0 (G3 embedded) */
8502 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
8503 /* PowerPC 750L v2.1 (G3 embedded) */
8504 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
8505 /* PowerPC 750L v2.2 (G3 embedded) */
8506 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
8507 /* PowerPC 750L v3.0 (G3 embedded) */
8508 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
8509 /* PowerPC 750L v3.2 (G3 embedded) */
8510 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
8511 /* Generic PowerPC 745 */
8512 POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
8513 /* Generic PowerPC 755 */
8514 POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
8515 /* Code name for PowerPC 745/755 */
8516 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
8517 /* PowerPC 745 v1.0 */
8518 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
8519 /* PowerPC 755 v1.0 */
8520 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
8521 /* PowerPC 745 v1.1 */
8522 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
8523 /* PowerPC 755 v1.1 */
8524 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
8525 /* PowerPC 745 v2.0 */
8526 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
8527 /* PowerPC 755 v2.0 */
8528 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
8529 /* PowerPC 745 v2.1 */
8530 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
8531 /* PowerPC 755 v2.1 */
8532 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
8533 /* PowerPC 745 v2.2 */
8534 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
8535 /* PowerPC 755 v2.2 */
8536 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
8537 /* PowerPC 745 v2.3 */
8538 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
8539 /* PowerPC 755 v2.3 */
8540 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
8541 /* PowerPC 745 v2.4 */
8542 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
8543 /* PowerPC 755 v2.4 */
8544 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
8545 /* PowerPC 745 v2.5 */
8546 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
8547 /* PowerPC 755 v2.5 */
8548 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
8549 /* PowerPC 745 v2.6 */
8550 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
8551 /* PowerPC 755 v2.6 */
8552 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
8553 /* PowerPC 745 v2.7 */
8554 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
8555 /* PowerPC 755 v2.7 */
8556 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
8557 /* PowerPC 745 v2.8 */
8558 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
8559 /* PowerPC 755 v2.8 */
8560 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
8561 #if defined (TODO)
8562 /* PowerPC 745P (G3) */
8563 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
8564 /* PowerPC 755P (G3) */
8565 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
8566 #endif
8567 /* PowerPC 74xx family */
8568 /* PowerPC 7400 (G4) */
8569 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
8570 /* Code name for PowerPC 7400 */
8571 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
8572 /* PowerPC 74xx is also well known as G4 */
8573 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
8574 /* PowerPC 7400 v1.0 (G4) */
8575 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
8576 /* PowerPC 7400 v1.1 (G4) */
8577 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
8578 /* PowerPC 7400 v2.0 (G4) */
8579 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
8580 /* PowerPC 7400 v2.1 (G4) */
8581 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
8582 /* PowerPC 7400 v2.2 (G4) */
8583 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
8584 /* PowerPC 7400 v2.6 (G4) */
8585 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
8586 /* PowerPC 7400 v2.7 (G4) */
8587 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
8588 /* PowerPC 7400 v2.8 (G4) */
8589 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
8590 /* PowerPC 7400 v2.9 (G4) */
8591 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
8592 /* PowerPC 7410 (G4) */
8593 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
8594 /* Code name for PowerPC 7410 */
8595 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
8596 /* PowerPC 7410 v1.0 (G4) */
8597 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
8598 /* PowerPC 7410 v1.1 (G4) */
8599 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
8600 /* PowerPC 7410 v1.2 (G4) */
8601 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
8602 /* PowerPC 7410 v1.3 (G4) */
8603 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
8604 /* PowerPC 7410 v1.4 (G4) */
8605 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
8606 /* PowerPC 7448 (G4) */
8607 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
8608 /* PowerPC 7448 v1.0 (G4) */
8609 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
8610 /* PowerPC 7448 v1.1 (G4) */
8611 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
8612 /* PowerPC 7448 v2.0 (G4) */
8613 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
8614 /* PowerPC 7448 v2.1 (G4) */
8615 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
8616 /* PowerPC 7450 (G4) */
8617 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
8618 /* Code name for PowerPC 7450 */
8619 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
8620 /* PowerPC 7450 v1.0 (G4) */
8621 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
8622 /* PowerPC 7450 v1.1 (G4) */
8623 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
8624 /* PowerPC 7450 v1.2 (G4) */
8625 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
8626 /* PowerPC 7450 v2.0 (G4) */
8627 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
8628 /* PowerPC 7450 v2.1 (G4) */
8629 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
8630 /* PowerPC 7441 (G4) */
8631 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
8632 /* PowerPC 7451 (G4) */
8633 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
8634 /* PowerPC 7441 v2.1 (G4) */
8635 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
8636 /* PowerPC 7441 v2.3 (G4) */
8637 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
8638 /* PowerPC 7451 v2.3 (G4) */
8639 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
8640 /* PowerPC 7441 v2.10 (G4) */
8641 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
8642 /* PowerPC 7451 v2.10 (G4) */
8643 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
8644 /* PowerPC 7445 (G4) */
8645 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
8646 /* PowerPC 7455 (G4) */
8647 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
8648 /* Code name for PowerPC 7445/7455 */
8649 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
8650 /* PowerPC 7445 v1.0 (G4) */
8651 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
8652 /* PowerPC 7455 v1.0 (G4) */
8653 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
8654 /* PowerPC 7445 v2.1 (G4) */
8655 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
8656 /* PowerPC 7455 v2.1 (G4) */
8657 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
8658 /* PowerPC 7445 v3.2 (G4) */
8659 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
8660 /* PowerPC 7455 v3.2 (G4) */
8661 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
8662 /* PowerPC 7445 v3.3 (G4) */
8663 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
8664 /* PowerPC 7455 v3.3 (G4) */
8665 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
8666 /* PowerPC 7445 v3.4 (G4) */
8667 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
8668 /* PowerPC 7455 v3.4 (G4) */
8669 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
8670 /* PowerPC 7447 (G4) */
8671 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
8672 /* PowerPC 7457 (G4) */
8673 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
8674 /* Code name for PowerPC 7447/7457 */
8675 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
8676 /* PowerPC 7447 v1.0 (G4) */
8677 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
8678 /* PowerPC 7457 v1.0 (G4) */
8679 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
8680 /* PowerPC 7447 v1.1 (G4) */
8681 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
8682 /* PowerPC 7457 v1.1 (G4) */
8683 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
8684 /* PowerPC 7457 v1.2 (G4) */
8685 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
8686 /* PowerPC 7447A (G4) */
8687 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
8688 /* PowerPC 7457A (G4) */
8689 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
8690 /* PowerPC 7447A v1.0 (G4) */
8691 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
8692 /* PowerPC 7457A v1.0 (G4) */
8693 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
8694 /* Code name for PowerPC 7447A/7457A */
8695 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
8696 /* PowerPC 7447A v1.1 (G4) */
8697 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
8698 /* PowerPC 7457A v1.1 (G4) */
8699 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
8700 /* PowerPC 7447A v1.2 (G4) */
8701 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
8702 /* PowerPC 7457A v1.2 (G4) */
8703 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
8704 /* 64 bits PowerPC */
8705 #if defined (TARGET_PPC64)
8706 /* PowerPC 620 */
8707 POWERPC_DEF("620", CPU_POWERPC_620, 620),
8708 /* Code name for PowerPC 620 */
8709 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
8710 #if defined (TODO)
8711 /* PowerPC 630 (POWER3) */
8712 POWERPC_DEF("630", CPU_POWERPC_630, 630),
8713 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
8714 /* Code names for POWER3 */
8715 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
8716 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
8717 #endif
8718 #if defined (TODO)
8719 /* PowerPC 631 (Power 3+) */
8720 POWERPC_DEF("631", CPU_POWERPC_631, 631),
8721 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
8722 #endif
8723 #if defined (TODO)
8724 /* POWER4 */
8725 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
8726 #endif
8727 #if defined (TODO)
8728 /* POWER4p */
8729 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
8730 #endif
8731 #if defined (TODO)
8732 /* POWER5 */
8733 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
8734 /* POWER5GR */
8735 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
8736 #endif
8737 #if defined (TODO)
8738 /* POWER5+ */
8739 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
8740 /* POWER5GS */
8741 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
8742 #endif
8743 #if defined (TODO)
8744 /* POWER6 */
8745 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
8746 /* POWER6 running in POWER5 mode */
8747 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
8748 /* POWER6A */
8749 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
8750 #endif
8751 /* PowerPC 970 */
8752 POWERPC_DEF("970", CPU_POWERPC_970, 970),
8753 /* PowerPC 970FX (G5) */
8754 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
8755 /* PowerPC 970FX v1.0 (G5) */
8756 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
8757 /* PowerPC 970FX v2.0 (G5) */
8758 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
8759 /* PowerPC 970FX v2.1 (G5) */
8760 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
8761 /* PowerPC 970FX v3.0 (G5) */
8762 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
8763 /* PowerPC 970FX v3.1 (G5) */
8764 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
8765 /* PowerPC 970GX (G5) */
8766 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
8767 /* PowerPC 970MP */
8768 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
8769 /* PowerPC 970MP v1.0 */
8770 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
8771 /* PowerPC 970MP v1.1 */
8772 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
8773 #if defined (TODO)
8774 /* PowerPC Cell */
8775 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
8776 #endif
8777 #if defined (TODO)
8778 /* PowerPC Cell v1.0 */
8779 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
8780 #endif
8781 #if defined (TODO)
8782 /* PowerPC Cell v2.0 */
8783 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
8784 #endif
8785 #if defined (TODO)
8786 /* PowerPC Cell v3.0 */
8787 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
8788 #endif
8789 #if defined (TODO)
8790 /* PowerPC Cell v3.1 */
8791 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
8792 #endif
8793 #if defined (TODO)
8794 /* PowerPC Cell v3.2 */
8795 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
8796 #endif
8797 #if defined (TODO)
8798 /* RS64 (Apache/A35) */
8799 /* This one seems to support the whole POWER2 instruction set
8800 * and the PowerPC 64 one.
8801 */
8802 /* What about A10 & A30 ? */
8803 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
8804 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
8805 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
8806 #endif
8807 #if defined (TODO)
8808 /* RS64-II (NorthStar/A50) */
8809 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
8810 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
8811 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
8812 #endif
8813 #if defined (TODO)
8814 /* RS64-III (Pulsar) */
8815 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
8816 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
8817 #endif
8818 #if defined (TODO)
8819 /* RS64-IV (IceStar/IStar/SStar) */
8820 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
8821 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
8822 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
8823 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
8824 #endif
8825 #endif /* defined (TARGET_PPC64) */
8826 /* POWER */
8827 #if defined (TODO)
8828 /* Original POWER */
8829 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
8830 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
8831 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
8832 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
8833 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
8834 #endif
8835 #if defined (TODO)
8836 /* POWER2 */
8837 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
8838 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
8839 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
8840 #endif
8841 /* PA semi cores */
8842 #if defined (TODO)
8843 /* PA PA6T */
8844 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
8845 #endif
8846 /* Generic PowerPCs */
8847 #if defined (TARGET_PPC64)
8848 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
8849 #endif
8850 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
8851 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
8852 /* Fallback */
8853 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
8854 };
8855
8856 /*****************************************************************************/
8857 /* Generic CPU instanciation routine */
8858 static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
8859 {
8860 #if !defined(CONFIG_USER_ONLY)
8861 int i;
8862
8863 env->irq_inputs = NULL;
8864 /* Set all exception vectors to an invalid address */
8865 for (i = 0; i < POWERPC_EXCP_NB; i++)
8866 env->excp_vectors[i] = (target_ulong)(-1ULL);
8867 env->excp_prefix = 0x00000000;
8868 env->ivor_mask = 0x00000000;
8869 env->ivpr_mask = 0x00000000;
8870 /* Default MMU definitions */
8871 env->nb_BATs = 0;
8872 env->nb_tlb = 0;
8873 env->nb_ways = 0;
8874 #endif
8875 /* Register SPR common to all PowerPC implementations */
8876 gen_spr_generic(env);
8877 spr_register(env, SPR_PVR, "PVR",
8878 SPR_NOACCESS, SPR_NOACCESS,
8879 &spr_read_generic, SPR_NOACCESS,
8880 def->pvr);
8881 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8882 if (def->svr != POWERPC_SVR_NONE) {
8883 if (def->svr & POWERPC_SVR_E500) {
8884 spr_register(env, SPR_E500_SVR, "SVR",
8885 SPR_NOACCESS, SPR_NOACCESS,
8886 &spr_read_generic, SPR_NOACCESS,
8887 def->svr & ~POWERPC_SVR_E500);
8888 } else {
8889 spr_register(env, SPR_SVR, "SVR",
8890 SPR_NOACCESS, SPR_NOACCESS,
8891 &spr_read_generic, SPR_NOACCESS,
8892 def->svr);
8893 }
8894 }
8895 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8896 (*def->init_proc)(env);
8897 /* MSR bits & flags consistency checks */
8898 if (env->msr_mask & (1 << 25)) {
8899 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8900 case POWERPC_FLAG_SPE:
8901 case POWERPC_FLAG_VRE:
8902 break;
8903 default:
8904 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8905 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8906 exit(1);
8907 }
8908 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8909 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8910 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8911 exit(1);
8912 }
8913 if (env->msr_mask & (1 << 17)) {
8914 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8915 case POWERPC_FLAG_TGPR:
8916 case POWERPC_FLAG_CE:
8917 break;
8918 default:
8919 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8920 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8921 exit(1);
8922 }
8923 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8924 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8925 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8926 exit(1);
8927 }
8928 if (env->msr_mask & (1 << 10)) {
8929 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8930 POWERPC_FLAG_UBLE)) {
8931 case POWERPC_FLAG_SE:
8932 case POWERPC_FLAG_DWE:
8933 case POWERPC_FLAG_UBLE:
8934 break;
8935 default:
8936 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8937 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8938 "POWERPC_FLAG_UBLE\n");
8939 exit(1);
8940 }
8941 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8942 POWERPC_FLAG_UBLE)) {
8943 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8944 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8945 "POWERPC_FLAG_UBLE\n");
8946 exit(1);
8947 }
8948 if (env->msr_mask & (1 << 9)) {
8949 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8950 case POWERPC_FLAG_BE:
8951 case POWERPC_FLAG_DE:
8952 break;
8953 default:
8954 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8955 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8956 exit(1);
8957 }
8958 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8959 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8960 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8961 exit(1);
8962 }
8963 if (env->msr_mask & (1 << 2)) {
8964 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8965 case POWERPC_FLAG_PX:
8966 case POWERPC_FLAG_PMM:
8967 break;
8968 default:
8969 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8970 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8971 exit(1);
8972 }
8973 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8974 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8975 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8976 exit(1);
8977 }
8978 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
8979 fprintf(stderr, "PowerPC flags inconsistency\n"
8980 "Should define the time-base and decrementer clock source\n");
8981 exit(1);
8982 }
8983 /* Allocate TLBs buffer when needed */
8984 #if !defined(CONFIG_USER_ONLY)
8985 if (env->nb_tlb != 0) {
8986 int nb_tlb = env->nb_tlb;
8987 if (env->id_tlbs != 0)
8988 nb_tlb *= 2;
8989 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
8990 /* Pre-compute some useful values */
8991 env->tlb_per_way = env->nb_tlb / env->nb_ways;
8992 }
8993 if (env->irq_inputs == NULL) {
8994 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
8995 " Attempt Qemu to crash very soon !\n");
8996 }
8997 #endif
8998 if (env->check_pow == NULL) {
8999 fprintf(stderr, "WARNING: no power management check handler "
9000 "registered.\n"
9001 " Attempt Qemu to crash very soon !\n");
9002 }
9003 }
9004
9005 #if defined(PPC_DUMP_CPU)
9006 static void dump_ppc_sprs (CPUPPCState *env)
9007 {
9008 ppc_spr_t *spr;
9009 #if !defined(CONFIG_USER_ONLY)
9010 uint32_t sr, sw;
9011 #endif
9012 uint32_t ur, uw;
9013 int i, j, n;
9014
9015 printf("Special purpose registers:\n");
9016 for (i = 0; i < 32; i++) {
9017 for (j = 0; j < 32; j++) {
9018 n = (i << 5) | j;
9019 spr = &env->spr_cb[n];
9020 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9021 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9022 #if !defined(CONFIG_USER_ONLY)
9023 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9024 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9025 if (sw || sr || uw || ur) {
9026 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9027 (i << 5) | j, (i << 5) | j, spr->name,
9028 sw ? 'w' : '-', sr ? 'r' : '-',
9029 uw ? 'w' : '-', ur ? 'r' : '-');
9030 }
9031 #else
9032 if (uw || ur) {
9033 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9034 (i << 5) | j, (i << 5) | j, spr->name,
9035 uw ? 'w' : '-', ur ? 'r' : '-');
9036 }
9037 #endif
9038 }
9039 }
9040 fflush(stdout);
9041 fflush(stderr);
9042 }
9043 #endif
9044
9045 /*****************************************************************************/
9046 #include <stdlib.h>
9047 #include <string.h>
9048
9049 /* Opcode types */
9050 enum {
9051 PPC_DIRECT = 0, /* Opcode routine */
9052 PPC_INDIRECT = 1, /* Indirect opcode table */
9053 };
9054
9055 static inline int is_indirect_opcode (void *handler)
9056 {
9057 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
9058 }
9059
9060 static inline opc_handler_t **ind_table(void *handler)
9061 {
9062 return (opc_handler_t **)((unsigned long)handler & ~3);
9063 }
9064
9065 /* Instruction table creation */
9066 /* Opcodes tables creation */
9067 static void fill_new_table (opc_handler_t **table, int len)
9068 {
9069 int i;
9070
9071 for (i = 0; i < len; i++)
9072 table[i] = &invalid_handler;
9073 }
9074
9075 static int create_new_table (opc_handler_t **table, unsigned char idx)
9076 {
9077 opc_handler_t **tmp;
9078
9079 tmp = malloc(0x20 * sizeof(opc_handler_t));
9080 fill_new_table(tmp, 0x20);
9081 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
9082
9083 return 0;
9084 }
9085
9086 static int insert_in_table (opc_handler_t **table, unsigned char idx,
9087 opc_handler_t *handler)
9088 {
9089 if (table[idx] != &invalid_handler)
9090 return -1;
9091 table[idx] = handler;
9092
9093 return 0;
9094 }
9095
9096 static int register_direct_insn (opc_handler_t **ppc_opcodes,
9097 unsigned char idx, opc_handler_t *handler)
9098 {
9099 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9100 printf("*** ERROR: opcode %02x already assigned in main "
9101 "opcode table\n", idx);
9102 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9103 printf(" Registered handler '%s' - new handler '%s'\n",
9104 ppc_opcodes[idx]->oname, handler->oname);
9105 #endif
9106 return -1;
9107 }
9108
9109 return 0;
9110 }
9111
9112 static int register_ind_in_table (opc_handler_t **table,
9113 unsigned char idx1, unsigned char idx2,
9114 opc_handler_t *handler)
9115 {
9116 if (table[idx1] == &invalid_handler) {
9117 if (create_new_table(table, idx1) < 0) {
9118 printf("*** ERROR: unable to create indirect table "
9119 "idx=%02x\n", idx1);
9120 return -1;
9121 }
9122 } else {
9123 if (!is_indirect_opcode(table[idx1])) {
9124 printf("*** ERROR: idx %02x already assigned to a direct "
9125 "opcode\n", idx1);
9126 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9127 printf(" Registered handler '%s' - new handler '%s'\n",
9128 ind_table(table[idx1])[idx2]->oname, handler->oname);
9129 #endif
9130 return -1;
9131 }
9132 }
9133 if (handler != NULL &&
9134 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9135 printf("*** ERROR: opcode %02x already assigned in "
9136 "opcode table %02x\n", idx2, idx1);
9137 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9138 printf(" Registered handler '%s' - new handler '%s'\n",
9139 ind_table(table[idx1])[idx2]->oname, handler->oname);
9140 #endif
9141 return -1;
9142 }
9143
9144 return 0;
9145 }
9146
9147 static int register_ind_insn (opc_handler_t **ppc_opcodes,
9148 unsigned char idx1, unsigned char idx2,
9149 opc_handler_t *handler)
9150 {
9151 int ret;
9152
9153 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9154
9155 return ret;
9156 }
9157
9158 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9159 unsigned char idx1, unsigned char idx2,
9160 unsigned char idx3, opc_handler_t *handler)
9161 {
9162 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9163 printf("*** ERROR: unable to join indirect table idx "
9164 "[%02x-%02x]\n", idx1, idx2);
9165 return -1;
9166 }
9167 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9168 handler) < 0) {
9169 printf("*** ERROR: unable to insert opcode "
9170 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9171 return -1;
9172 }
9173
9174 return 0;
9175 }
9176
9177 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9178 {
9179 if (insn->opc2 != 0xFF) {
9180 if (insn->opc3 != 0xFF) {
9181 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9182 insn->opc3, &insn->handler) < 0)
9183 return -1;
9184 } else {
9185 if (register_ind_insn(ppc_opcodes, insn->opc1,
9186 insn->opc2, &insn->handler) < 0)
9187 return -1;
9188 }
9189 } else {
9190 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9191 return -1;
9192 }
9193
9194 return 0;
9195 }
9196
9197 static int test_opcode_table (opc_handler_t **table, int len)
9198 {
9199 int i, count, tmp;
9200
9201 for (i = 0, count = 0; i < len; i++) {
9202 /* Consistency fixup */
9203 if (table[i] == NULL)
9204 table[i] = &invalid_handler;
9205 if (table[i] != &invalid_handler) {
9206 if (is_indirect_opcode(table[i])) {
9207 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9208 if (tmp == 0) {
9209 free(table[i]);
9210 table[i] = &invalid_handler;
9211 } else {
9212 count++;
9213 }
9214 } else {
9215 count++;
9216 }
9217 }
9218 }
9219
9220 return count;
9221 }
9222
9223 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9224 {
9225 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9226 printf("*** WARNING: no opcode defined !\n");
9227 }
9228
9229 /*****************************************************************************/
9230 static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
9231 {
9232 opcode_t *opc, *start, *end;
9233
9234 fill_new_table(env->opcodes, 0x40);
9235 if (&opc_start < &opc_end) {
9236 start = &opc_start;
9237 end = &opc_end;
9238 } else {
9239 start = &opc_end;
9240 end = &opc_start;
9241 }
9242 for (opc = start + 1; opc != end; opc++) {
9243 if ((opc->handler.type & def->insns_flags) != 0) {
9244 if (register_insn(env->opcodes, opc) < 0) {
9245 printf("*** ERROR initializing PowerPC instruction "
9246 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9247 opc->opc3);
9248 return -1;
9249 }
9250 }
9251 }
9252 fix_opcode_tables(env->opcodes);
9253 fflush(stdout);
9254 fflush(stderr);
9255
9256 return 0;
9257 }
9258
9259 #if defined(PPC_DUMP_CPU)
9260 static void dump_ppc_insns (CPUPPCState *env)
9261 {
9262 opc_handler_t **table, *handler;
9263 const char *p, *q;
9264 uint8_t opc1, opc2, opc3;
9265
9266 printf("Instructions set:\n");
9267 /* opc1 is 6 bits long */
9268 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9269 table = env->opcodes;
9270 handler = table[opc1];
9271 if (is_indirect_opcode(handler)) {
9272 /* opc2 is 5 bits long */
9273 for (opc2 = 0; opc2 < 0x20; opc2++) {
9274 table = env->opcodes;
9275 handler = env->opcodes[opc1];
9276 table = ind_table(handler);
9277 handler = table[opc2];
9278 if (is_indirect_opcode(handler)) {
9279 table = ind_table(handler);
9280 /* opc3 is 5 bits long */
9281 for (opc3 = 0; opc3 < 0x20; opc3++) {
9282 handler = table[opc3];
9283 if (handler->handler != &gen_invalid) {
9284 /* Special hack to properly dump SPE insns */
9285 p = strchr(handler->oname, '_');
9286 if (p == NULL) {
9287 printf("INSN: %02x %02x %02x (%02d %04d) : "
9288 "%s\n",
9289 opc1, opc2, opc3, opc1,
9290 (opc3 << 5) | opc2,
9291 handler->oname);
9292 } else {
9293 q = "speundef";
9294 if ((p - handler->oname) != strlen(q) ||
9295 memcmp(handler->oname, q, strlen(q)) != 0) {
9296 /* First instruction */
9297 printf("INSN: %02x %02x %02x (%02d %04d) : "
9298 "%.*s\n",
9299 opc1, opc2 << 1, opc3, opc1,
9300 (opc3 << 6) | (opc2 << 1),
9301 (int)(p - handler->oname),
9302 handler->oname);
9303 }
9304 if (strcmp(p + 1, q) != 0) {
9305 /* Second instruction */
9306 printf("INSN: %02x %02x %02x (%02d %04d) : "
9307 "%s\n",
9308 opc1, (opc2 << 1) | 1, opc3, opc1,
9309 (opc3 << 6) | (opc2 << 1) | 1,
9310 p + 1);
9311 }
9312 }
9313 }
9314 }
9315 } else {
9316 if (handler->handler != &gen_invalid) {
9317 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9318 opc1, opc2, opc1, opc2, handler->oname);
9319 }
9320 }
9321 }
9322 } else {
9323 if (handler->handler != &gen_invalid) {
9324 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9325 opc1, opc1, handler->oname);
9326 }
9327 }
9328 }
9329 }
9330 #endif
9331
9332 static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9333 {
9334 if (n < 32) {
9335 stfq_p(mem_buf, env->fpr[n]);
9336 return 8;
9337 }
9338 if (n == 32) {
9339 /* FPSCR not implemented */
9340 memset(mem_buf, 0, 4);
9341 return 4;
9342 }
9343 return 0;
9344 }
9345
9346 static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9347 {
9348 if (n < 32) {
9349 env->fpr[n] = ldfq_p(mem_buf);
9350 return 8;
9351 }
9352 if (n == 32) {
9353 /* FPSCR not implemented */
9354 return 4;
9355 }
9356 return 0;
9357 }
9358
9359 static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9360 {
9361 if (n < 32) {
9362 #ifdef WORDS_BIGENDIAN
9363 stq_p(mem_buf, env->avr[n].u64[0]);
9364 stq_p(mem_buf+8, env->avr[n].u64[1]);
9365 #else
9366 stq_p(mem_buf, env->avr[n].u64[1]);
9367 stq_p(mem_buf+8, env->avr[n].u64[0]);
9368 #endif
9369 return 16;
9370 }
9371 if (n == 33) {
9372 stl_p(mem_buf, env->vscr);
9373 return 4;
9374 }
9375 if (n == 34) {
9376 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9377 return 4;
9378 }
9379 return 0;
9380 }
9381
9382 static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9383 {
9384 if (n < 32) {
9385 #ifdef WORDS_BIGENDIAN
9386 env->avr[n].u64[0] = ldq_p(mem_buf);
9387 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9388 #else
9389 env->avr[n].u64[1] = ldq_p(mem_buf);
9390 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9391 #endif
9392 return 16;
9393 }
9394 if (n == 33) {
9395 env->vscr = ldl_p(mem_buf);
9396 return 4;
9397 }
9398 if (n == 34) {
9399 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9400 return 4;
9401 }
9402 return 0;
9403 }
9404
9405 static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9406 {
9407 if (n < 32) {
9408 #if defined(TARGET_PPC64)
9409 stl_p(mem_buf, env->gpr[n] >> 32);
9410 #else
9411 stl_p(mem_buf, env->gprh[n]);
9412 #endif
9413 return 4;
9414 }
9415 if (n == 33) {
9416 stq_p(mem_buf, env->spe_acc);
9417 return 8;
9418 }
9419 if (n == 34) {
9420 /* SPEFSCR not implemented */
9421 memset(mem_buf, 0, 4);
9422 return 4;
9423 }
9424 return 0;
9425 }
9426
9427 static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9428 {
9429 if (n < 32) {
9430 #if defined(TARGET_PPC64)
9431 target_ulong lo = (uint32_t)env->gpr[n];
9432 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9433 env->gpr[n] = lo | hi;
9434 #else
9435 env->gprh[n] = ldl_p(mem_buf);
9436 #endif
9437 return 4;
9438 }
9439 if (n == 33) {
9440 env->spe_acc = ldq_p(mem_buf);
9441 return 8;
9442 }
9443 if (n == 34) {
9444 /* SPEFSCR not implemented */
9445 return 4;
9446 }
9447 return 0;
9448 }
9449
9450 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
9451 {
9452 env->msr_mask = def->msr_mask;
9453 env->mmu_model = def->mmu_model;
9454 env->excp_model = def->excp_model;
9455 env->bus_model = def->bus_model;
9456 env->flags = def->flags;
9457 env->bfd_mach = def->bfd_mach;
9458 env->check_pow = def->check_pow;
9459 if (create_ppc_opcodes(env, def) < 0)
9460 return -1;
9461 init_ppc_proc(env, def);
9462
9463 if (def->insns_flags & PPC_FLOAT) {
9464 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9465 33, "power-fpu.xml", 0);
9466 }
9467 if (def->insns_flags & PPC_ALTIVEC) {
9468 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9469 34, "power-altivec.xml", 0);
9470 }
9471 if (def->insns_flags & PPC_SPE) {
9472 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9473 34, "power-spe.xml", 0);
9474 }
9475
9476 #if defined(PPC_DUMP_CPU)
9477 {
9478 const char *mmu_model, *excp_model, *bus_model;
9479 switch (env->mmu_model) {
9480 case POWERPC_MMU_32B:
9481 mmu_model = "PowerPC 32";
9482 break;
9483 case POWERPC_MMU_SOFT_6xx:
9484 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9485 break;
9486 case POWERPC_MMU_SOFT_74xx:
9487 mmu_model = "PowerPC 74xx with software driven TLBs";
9488 break;
9489 case POWERPC_MMU_SOFT_4xx:
9490 mmu_model = "PowerPC 4xx with software driven TLBs";
9491 break;
9492 case POWERPC_MMU_SOFT_4xx_Z:
9493 mmu_model = "PowerPC 4xx with software driven TLBs "
9494 "and zones protections";
9495 break;
9496 case POWERPC_MMU_REAL:
9497 mmu_model = "PowerPC real mode only";
9498 break;
9499 case POWERPC_MMU_MPC8xx:
9500 mmu_model = "PowerPC MPC8xx";
9501 break;
9502 case POWERPC_MMU_BOOKE:
9503 mmu_model = "PowerPC BookE";
9504 break;
9505 case POWERPC_MMU_BOOKE_FSL:
9506 mmu_model = "PowerPC BookE FSL";
9507 break;
9508 case POWERPC_MMU_601:
9509 mmu_model = "PowerPC 601";
9510 break;
9511 #if defined (TARGET_PPC64)
9512 case POWERPC_MMU_64B:
9513 mmu_model = "PowerPC 64";
9514 break;
9515 case POWERPC_MMU_620:
9516 mmu_model = "PowerPC 620";
9517 break;
9518 #endif
9519 default:
9520 mmu_model = "Unknown or invalid";
9521 break;
9522 }
9523 switch (env->excp_model) {
9524 case POWERPC_EXCP_STD:
9525 excp_model = "PowerPC";
9526 break;
9527 case POWERPC_EXCP_40x:
9528 excp_model = "PowerPC 40x";
9529 break;
9530 case POWERPC_EXCP_601:
9531 excp_model = "PowerPC 601";
9532 break;
9533 case POWERPC_EXCP_602:
9534 excp_model = "PowerPC 602";
9535 break;
9536 case POWERPC_EXCP_603:
9537 excp_model = "PowerPC 603";
9538 break;
9539 case POWERPC_EXCP_603E:
9540 excp_model = "PowerPC 603e";
9541 break;
9542 case POWERPC_EXCP_604:
9543 excp_model = "PowerPC 604";
9544 break;
9545 case POWERPC_EXCP_7x0:
9546 excp_model = "PowerPC 740/750";
9547 break;
9548 case POWERPC_EXCP_7x5:
9549 excp_model = "PowerPC 745/755";
9550 break;
9551 case POWERPC_EXCP_74xx:
9552 excp_model = "PowerPC 74xx";
9553 break;
9554 case POWERPC_EXCP_BOOKE:
9555 excp_model = "PowerPC BookE";
9556 break;
9557 #if defined (TARGET_PPC64)
9558 case POWERPC_EXCP_970:
9559 excp_model = "PowerPC 970";
9560 break;
9561 #endif
9562 default:
9563 excp_model = "Unknown or invalid";
9564 break;
9565 }
9566 switch (env->bus_model) {
9567 case PPC_FLAGS_INPUT_6xx:
9568 bus_model = "PowerPC 6xx";
9569 break;
9570 case PPC_FLAGS_INPUT_BookE:
9571 bus_model = "PowerPC BookE";
9572 break;
9573 case PPC_FLAGS_INPUT_405:
9574 bus_model = "PowerPC 405";
9575 break;
9576 case PPC_FLAGS_INPUT_401:
9577 bus_model = "PowerPC 401/403";
9578 break;
9579 case PPC_FLAGS_INPUT_RCPU:
9580 bus_model = "RCPU / MPC8xx";
9581 break;
9582 #if defined (TARGET_PPC64)
9583 case PPC_FLAGS_INPUT_970:
9584 bus_model = "PowerPC 970";
9585 break;
9586 #endif
9587 default:
9588 bus_model = "Unknown or invalid";
9589 break;
9590 }
9591 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9592 " MMU model : %s\n",
9593 def->name, def->pvr, def->msr_mask, mmu_model);
9594 #if !defined(CONFIG_USER_ONLY)
9595 if (env->tlb != NULL) {
9596 printf(" %d %s TLB in %d ways\n",
9597 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9598 env->nb_ways);
9599 }
9600 #endif
9601 printf(" Exceptions model : %s\n"
9602 " Bus model : %s\n",
9603 excp_model, bus_model);
9604 printf(" MSR features :\n");
9605 if (env->flags & POWERPC_FLAG_SPE)
9606 printf(" signal processing engine enable"
9607 "\n");
9608 else if (env->flags & POWERPC_FLAG_VRE)
9609 printf(" vector processor enable\n");
9610 if (env->flags & POWERPC_FLAG_TGPR)
9611 printf(" temporary GPRs\n");
9612 else if (env->flags & POWERPC_FLAG_CE)
9613 printf(" critical input enable\n");
9614 if (env->flags & POWERPC_FLAG_SE)
9615 printf(" single-step trace mode\n");
9616 else if (env->flags & POWERPC_FLAG_DWE)
9617 printf(" debug wait enable\n");
9618 else if (env->flags & POWERPC_FLAG_UBLE)
9619 printf(" user BTB lock enable\n");
9620 if (env->flags & POWERPC_FLAG_BE)
9621 printf(" branch-step trace mode\n");
9622 else if (env->flags & POWERPC_FLAG_DE)
9623 printf(" debug interrupt enable\n");
9624 if (env->flags & POWERPC_FLAG_PX)
9625 printf(" inclusive protection\n");
9626 else if (env->flags & POWERPC_FLAG_PMM)
9627 printf(" performance monitor mark\n");
9628 if (env->flags == POWERPC_FLAG_NONE)
9629 printf(" none\n");
9630 printf(" Time-base/decrementer clock source: %s\n",
9631 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
9632 }
9633 dump_ppc_insns(env);
9634 dump_ppc_sprs(env);
9635 fflush(stdout);
9636 #endif
9637
9638 return 0;
9639 }
9640
9641 static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
9642 {
9643 const ppc_def_t *ret;
9644 uint32_t pvr_rev;
9645 int i, best, match, best_match, max;
9646
9647 ret = NULL;
9648 max = ARRAY_SIZE(ppc_defs);
9649 best = -1;
9650 pvr_rev = pvr & 0xFFFF;
9651 /* We want all specified bits to match */
9652 best_match = 32 - ctz32(pvr_rev);
9653 for (i = 0; i < max; i++) {
9654 /* We check that the 16 higher bits are the same to ensure the CPU
9655 * model will be the choosen one.
9656 */
9657 if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
9658 /* We want as much as possible of the low-level 16 bits
9659 * to be the same but we allow inexact matches.
9660 */
9661 match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
9662 /* We check '>=' instead of '>' because the PPC_defs table
9663 * is ordered by increasing revision.
9664 * Then, we will match the higher revision compatible
9665 * with the requested PVR
9666 */
9667 if (match >= best_match) {
9668 best = i;
9669 best_match = match;
9670 }
9671 }
9672 }
9673 if (best != -1)
9674 ret = &ppc_defs[best];
9675
9676 return ret;
9677 }
9678
9679 #include <ctype.h>
9680
9681 const ppc_def_t *cpu_ppc_find_by_name (const char *name)
9682 {
9683 const ppc_def_t *ret;
9684 const char *p;
9685 int i, max, len;
9686
9687 /* Check if the given name is a PVR */
9688 len = strlen(name);
9689 if (len == 10 && name[0] == '0' && name[1] == 'x') {
9690 p = name + 2;
9691 goto check_pvr;
9692 } else if (len == 8) {
9693 p = name;
9694 check_pvr:
9695 for (i = 0; i < 8; i++) {
9696 if (!qemu_isxdigit(*p++))
9697 break;
9698 }
9699 if (i == 8)
9700 return ppc_find_by_pvr(strtoul(name, NULL, 16));
9701 }
9702 ret = NULL;
9703 max = ARRAY_SIZE(ppc_defs);
9704 for (i = 0; i < max; i++) {
9705 if (strcasecmp(name, ppc_defs[i].name) == 0) {
9706 ret = &ppc_defs[i];
9707 break;
9708 }
9709 }
9710
9711 return ret;
9712 }
9713
9714 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
9715 {
9716 int i, max;
9717
9718 max = ARRAY_SIZE(ppc_defs);
9719 for (i = 0; i < max; i++) {
9720 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
9721 ppc_defs[i].name, ppc_defs[i].pvr);
9722 }
9723 }
Qemu copy for testing