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Merge branch 'for-upstream' of git://git.serverraum.org/git/mw/qemu-lm32
[qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 /* A lot of PowerPC definition have been included here.
21 * Most of them are not usable for now but have been kept
22 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
23 */
24
25 #include "dis-asm.h"
26 #include "gdbstub.h"
27
28 //#define PPC_DUMP_CPU
29 //#define PPC_DEBUG_SPR
30 //#define PPC_DUMP_SPR_ACCESSES
31 #if defined(CONFIG_USER_ONLY)
32 #define TODO_USER_ONLY 1
33 #endif
34
35 struct ppc_def_t {
36 const char *name;
37 uint32_t pvr;
38 uint32_t svr;
39 uint64_t insns_flags;
40 uint64_t insns_flags2;
41 uint64_t msr_mask;
42 powerpc_mmu_t mmu_model;
43 powerpc_excp_t excp_model;
44 powerpc_input_t bus_model;
45 uint32_t flags;
46 int bfd_mach;
47 void (*init_proc)(CPUPPCState *env);
48 int (*check_pow)(CPUPPCState *env);
49 };
50
51 /* For user-mode emulation, we don't emulate any IRQ controller */
52 #if defined(CONFIG_USER_ONLY)
53 #define PPC_IRQ_INIT_FN(name) \
54 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
55 { \
56 }
57 #else
58 #define PPC_IRQ_INIT_FN(name) \
59 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
60 #endif
61
62 PPC_IRQ_INIT_FN(40x);
63 PPC_IRQ_INIT_FN(6xx);
64 PPC_IRQ_INIT_FN(970);
65 PPC_IRQ_INIT_FN(POWER7);
66 PPC_IRQ_INIT_FN(e500);
67
68 /* Generic callbacks:
69 * do nothing but store/retrieve spr value
70 */
71 static void spr_read_generic (void *opaque, int gprn, int sprn)
72 {
73 gen_load_spr(cpu_gpr[gprn], sprn);
74 #ifdef PPC_DUMP_SPR_ACCESSES
75 {
76 TCGv_i32 t0 = tcg_const_i32(sprn);
77 gen_helper_load_dump_spr(t0);
78 tcg_temp_free_i32(t0);
79 }
80 #endif
81 }
82
83 static void spr_write_generic (void *opaque, int sprn, int gprn)
84 {
85 gen_store_spr(sprn, cpu_gpr[gprn]);
86 #ifdef PPC_DUMP_SPR_ACCESSES
87 {
88 TCGv_i32 t0 = tcg_const_i32(sprn);
89 gen_helper_store_dump_spr(t0);
90 tcg_temp_free_i32(t0);
91 }
92 #endif
93 }
94
95 #if !defined(CONFIG_USER_ONLY)
96 static void spr_write_clear (void *opaque, int sprn, int gprn)
97 {
98 TCGv t0 = tcg_temp_new();
99 TCGv t1 = tcg_temp_new();
100 gen_load_spr(t0, sprn);
101 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
102 tcg_gen_and_tl(t0, t0, t1);
103 gen_store_spr(sprn, t0);
104 tcg_temp_free(t0);
105 tcg_temp_free(t1);
106 }
107 #endif
108
109 /* SPR common to all PowerPC */
110 /* XER */
111 static void spr_read_xer (void *opaque, int gprn, int sprn)
112 {
113 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
114 }
115
116 static void spr_write_xer (void *opaque, int sprn, int gprn)
117 {
118 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
119 }
120
121 /* LR */
122 static void spr_read_lr (void *opaque, int gprn, int sprn)
123 {
124 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
125 }
126
127 static void spr_write_lr (void *opaque, int sprn, int gprn)
128 {
129 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
130 }
131
132 /* CFAR */
133 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
134 static void spr_read_cfar (void *opaque, int gprn, int sprn)
135 {
136 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
137 }
138
139 static void spr_write_cfar (void *opaque, int sprn, int gprn)
140 {
141 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
142 }
143 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
144
145 /* CTR */
146 static void spr_read_ctr (void *opaque, int gprn, int sprn)
147 {
148 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
149 }
150
151 static void spr_write_ctr (void *opaque, int sprn, int gprn)
152 {
153 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
154 }
155
156 /* User read access to SPR */
157 /* USPRx */
158 /* UMMCRx */
159 /* UPMCx */
160 /* USIA */
161 /* UDECR */
162 static void spr_read_ureg (void *opaque, int gprn, int sprn)
163 {
164 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
165 }
166
167 /* SPR common to all non-embedded PowerPC */
168 /* DECR */
169 #if !defined(CONFIG_USER_ONLY)
170 static void spr_read_decr (void *opaque, int gprn, int sprn)
171 {
172 if (use_icount) {
173 gen_io_start();
174 }
175 gen_helper_load_decr(cpu_gpr[gprn]);
176 if (use_icount) {
177 gen_io_end();
178 gen_stop_exception(opaque);
179 }
180 }
181
182 static void spr_write_decr (void *opaque, int sprn, int gprn)
183 {
184 if (use_icount) {
185 gen_io_start();
186 }
187 gen_helper_store_decr(cpu_gpr[gprn]);
188 if (use_icount) {
189 gen_io_end();
190 gen_stop_exception(opaque);
191 }
192 }
193 #endif
194
195 /* SPR common to all non-embedded PowerPC, except 601 */
196 /* Time base */
197 static void spr_read_tbl (void *opaque, int gprn, int sprn)
198 {
199 if (use_icount) {
200 gen_io_start();
201 }
202 gen_helper_load_tbl(cpu_gpr[gprn]);
203 if (use_icount) {
204 gen_io_end();
205 gen_stop_exception(opaque);
206 }
207 }
208
209 static void spr_read_tbu (void *opaque, int gprn, int sprn)
210 {
211 if (use_icount) {
212 gen_io_start();
213 }
214 gen_helper_load_tbu(cpu_gpr[gprn]);
215 if (use_icount) {
216 gen_io_end();
217 gen_stop_exception(opaque);
218 }
219 }
220
221 __attribute__ (( unused ))
222 static void spr_read_atbl (void *opaque, int gprn, int sprn)
223 {
224 gen_helper_load_atbl(cpu_gpr[gprn]);
225 }
226
227 __attribute__ (( unused ))
228 static void spr_read_atbu (void *opaque, int gprn, int sprn)
229 {
230 gen_helper_load_atbu(cpu_gpr[gprn]);
231 }
232
233 #if !defined(CONFIG_USER_ONLY)
234 static void spr_write_tbl (void *opaque, int sprn, int gprn)
235 {
236 if (use_icount) {
237 gen_io_start();
238 }
239 gen_helper_store_tbl(cpu_gpr[gprn]);
240 if (use_icount) {
241 gen_io_end();
242 gen_stop_exception(opaque);
243 }
244 }
245
246 static void spr_write_tbu (void *opaque, int sprn, int gprn)
247 {
248 if (use_icount) {
249 gen_io_start();
250 }
251 gen_helper_store_tbu(cpu_gpr[gprn]);
252 if (use_icount) {
253 gen_io_end();
254 gen_stop_exception(opaque);
255 }
256 }
257
258 __attribute__ (( unused ))
259 static void spr_write_atbl (void *opaque, int sprn, int gprn)
260 {
261 gen_helper_store_atbl(cpu_gpr[gprn]);
262 }
263
264 __attribute__ (( unused ))
265 static void spr_write_atbu (void *opaque, int sprn, int gprn)
266 {
267 gen_helper_store_atbu(cpu_gpr[gprn]);
268 }
269
270 #if defined(TARGET_PPC64)
271 __attribute__ (( unused ))
272 static void spr_read_purr (void *opaque, int gprn, int sprn)
273 {
274 gen_helper_load_purr(cpu_gpr[gprn]);
275 }
276 #endif
277 #endif
278
279 #if !defined(CONFIG_USER_ONLY)
280 /* IBAT0U...IBAT0U */
281 /* IBAT0L...IBAT7L */
282 static void spr_read_ibat (void *opaque, int gprn, int sprn)
283 {
284 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
285 }
286
287 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
288 {
289 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
290 }
291
292 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
293 {
294 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
295 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
296 tcg_temp_free_i32(t0);
297 }
298
299 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
300 {
301 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
302 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
303 tcg_temp_free_i32(t0);
304 }
305
306 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
307 {
308 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
309 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
310 tcg_temp_free_i32(t0);
311 }
312
313 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
314 {
315 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
316 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
317 tcg_temp_free_i32(t0);
318 }
319
320 /* DBAT0U...DBAT7U */
321 /* DBAT0L...DBAT7L */
322 static void spr_read_dbat (void *opaque, int gprn, int sprn)
323 {
324 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
325 }
326
327 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
328 {
329 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
330 }
331
332 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
333 {
334 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
335 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
336 tcg_temp_free_i32(t0);
337 }
338
339 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
340 {
341 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
342 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
343 tcg_temp_free_i32(t0);
344 }
345
346 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
347 {
348 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
349 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
350 tcg_temp_free_i32(t0);
351 }
352
353 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
354 {
355 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
356 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
357 tcg_temp_free_i32(t0);
358 }
359
360 /* SDR1 */
361 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
362 {
363 gen_helper_store_sdr1(cpu_gpr[gprn]);
364 }
365
366 /* 64 bits PowerPC specific SPRs */
367 /* ASR */
368 #if defined(TARGET_PPC64)
369 static void spr_read_hior (void *opaque, int gprn, int sprn)
370 {
371 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
372 }
373
374 static void spr_write_hior (void *opaque, int sprn, int gprn)
375 {
376 TCGv t0 = tcg_temp_new();
377 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
378 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
379 tcg_temp_free(t0);
380 }
381
382 static void spr_read_asr (void *opaque, int gprn, int sprn)
383 {
384 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
385 }
386
387 static void spr_write_asr (void *opaque, int sprn, int gprn)
388 {
389 gen_helper_store_asr(cpu_gpr[gprn]);
390 }
391 #endif
392 #endif
393
394 /* PowerPC 601 specific registers */
395 /* RTC */
396 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
397 {
398 gen_helper_load_601_rtcl(cpu_gpr[gprn]);
399 }
400
401 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
402 {
403 gen_helper_load_601_rtcu(cpu_gpr[gprn]);
404 }
405
406 #if !defined(CONFIG_USER_ONLY)
407 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
408 {
409 gen_helper_store_601_rtcu(cpu_gpr[gprn]);
410 }
411
412 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
413 {
414 gen_helper_store_601_rtcl(cpu_gpr[gprn]);
415 }
416
417 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
418 {
419 DisasContext *ctx = opaque;
420
421 gen_helper_store_hid0_601(cpu_gpr[gprn]);
422 /* Must stop the translation as endianness may have changed */
423 gen_stop_exception(ctx);
424 }
425 #endif
426
427 /* Unified bats */
428 #if !defined(CONFIG_USER_ONLY)
429 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
430 {
431 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
432 }
433
434 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
435 {
436 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
437 gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
438 tcg_temp_free_i32(t0);
439 }
440
441 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
442 {
443 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
444 gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
445 tcg_temp_free_i32(t0);
446 }
447 #endif
448
449 /* PowerPC 40x specific registers */
450 #if !defined(CONFIG_USER_ONLY)
451 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
452 {
453 gen_helper_load_40x_pit(cpu_gpr[gprn]);
454 }
455
456 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
457 {
458 gen_helper_store_40x_pit(cpu_gpr[gprn]);
459 }
460
461 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
462 {
463 DisasContext *ctx = opaque;
464
465 gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
466 /* We must stop translation as we may have rebooted */
467 gen_stop_exception(ctx);
468 }
469
470 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
471 {
472 gen_helper_store_40x_sler(cpu_gpr[gprn]);
473 }
474
475 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
476 {
477 gen_helper_store_booke_tcr(cpu_gpr[gprn]);
478 }
479
480 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
481 {
482 gen_helper_store_booke_tsr(cpu_gpr[gprn]);
483 }
484 #endif
485
486 /* PowerPC 403 specific registers */
487 /* PBL1 / PBU1 / PBL2 / PBU2 */
488 #if !defined(CONFIG_USER_ONLY)
489 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
490 {
491 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
492 }
493
494 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
495 {
496 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
497 gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
498 tcg_temp_free_i32(t0);
499 }
500
501 static void spr_write_pir (void *opaque, int sprn, int gprn)
502 {
503 TCGv t0 = tcg_temp_new();
504 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
505 gen_store_spr(SPR_PIR, t0);
506 tcg_temp_free(t0);
507 }
508 #endif
509
510 /* SPE specific registers */
511 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
512 {
513 TCGv_i32 t0 = tcg_temp_new_i32();
514 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
515 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
516 tcg_temp_free_i32(t0);
517 }
518
519 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
520 {
521 TCGv_i32 t0 = tcg_temp_new_i32();
522 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
523 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
524 tcg_temp_free_i32(t0);
525 }
526
527 #if !defined(CONFIG_USER_ONLY)
528 /* Callback used to write the exception vector base */
529 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
530 {
531 TCGv t0 = tcg_temp_new();
532 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
533 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
534 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
535 gen_store_spr(sprn, t0);
536 tcg_temp_free(t0);
537 }
538
539 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
540 {
541 DisasContext *ctx = opaque;
542
543 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
544 TCGv t0 = tcg_temp_new();
545 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
546 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
547 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
548 gen_store_spr(sprn, t0);
549 tcg_temp_free(t0);
550 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
551 TCGv t0 = tcg_temp_new();
552 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
553 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
554 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
555 gen_store_spr(sprn, t0);
556 tcg_temp_free(t0);
557 } else {
558 printf("Trying to write an unknown exception vector %d %03x\n",
559 sprn, sprn);
560 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
561 }
562 }
563 #endif
564
565 static inline void vscr_init (CPUPPCState *env, uint32_t val)
566 {
567 env->vscr = val;
568 /* Altivec always uses round-to-nearest */
569 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
570 set_flush_to_zero(vscr_nj, &env->vec_status);
571 }
572
573 #if defined(CONFIG_USER_ONLY)
574 #define spr_register(env, num, name, uea_read, uea_write, \
575 oea_read, oea_write, initial_value) \
576 do { \
577 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
578 } while (0)
579 static inline void _spr_register (CPUPPCState *env, int num,
580 const char *name,
581 void (*uea_read)(void *opaque, int gprn, int sprn),
582 void (*uea_write)(void *opaque, int sprn, int gprn),
583 target_ulong initial_value)
584 #else
585 static inline void spr_register (CPUPPCState *env, int num,
586 const char *name,
587 void (*uea_read)(void *opaque, int gprn, int sprn),
588 void (*uea_write)(void *opaque, int sprn, int gprn),
589 void (*oea_read)(void *opaque, int gprn, int sprn),
590 void (*oea_write)(void *opaque, int sprn, int gprn),
591 target_ulong initial_value)
592 #endif
593 {
594 ppc_spr_t *spr;
595
596 spr = &env->spr_cb[num];
597 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
598 #if !defined(CONFIG_USER_ONLY)
599 spr->oea_read != NULL || spr->oea_write != NULL ||
600 #endif
601 spr->uea_read != NULL || spr->uea_write != NULL) {
602 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
603 exit(1);
604 }
605 #if defined(PPC_DEBUG_SPR)
606 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
607 name, initial_value);
608 #endif
609 spr->name = name;
610 spr->uea_read = uea_read;
611 spr->uea_write = uea_write;
612 #if !defined(CONFIG_USER_ONLY)
613 spr->oea_read = oea_read;
614 spr->oea_write = oea_write;
615 #endif
616 env->spr[num] = initial_value;
617 }
618
619 /* Generic PowerPC SPRs */
620 static void gen_spr_generic (CPUPPCState *env)
621 {
622 /* Integer processing */
623 spr_register(env, SPR_XER, "XER",
624 &spr_read_xer, &spr_write_xer,
625 &spr_read_xer, &spr_write_xer,
626 0x00000000);
627 /* Branch contol */
628 spr_register(env, SPR_LR, "LR",
629 &spr_read_lr, &spr_write_lr,
630 &spr_read_lr, &spr_write_lr,
631 0x00000000);
632 spr_register(env, SPR_CTR, "CTR",
633 &spr_read_ctr, &spr_write_ctr,
634 &spr_read_ctr, &spr_write_ctr,
635 0x00000000);
636 /* Interrupt processing */
637 spr_register(env, SPR_SRR0, "SRR0",
638 SPR_NOACCESS, SPR_NOACCESS,
639 &spr_read_generic, &spr_write_generic,
640 0x00000000);
641 spr_register(env, SPR_SRR1, "SRR1",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_generic, &spr_write_generic,
644 0x00000000);
645 /* Processor control */
646 spr_register(env, SPR_SPRG0, "SPRG0",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_generic, &spr_write_generic,
649 0x00000000);
650 spr_register(env, SPR_SPRG1, "SPRG1",
651 SPR_NOACCESS, SPR_NOACCESS,
652 &spr_read_generic, &spr_write_generic,
653 0x00000000);
654 spr_register(env, SPR_SPRG2, "SPRG2",
655 SPR_NOACCESS, SPR_NOACCESS,
656 &spr_read_generic, &spr_write_generic,
657 0x00000000);
658 spr_register(env, SPR_SPRG3, "SPRG3",
659 SPR_NOACCESS, SPR_NOACCESS,
660 &spr_read_generic, &spr_write_generic,
661 0x00000000);
662 }
663
664 /* SPR common to all non-embedded PowerPC, including 601 */
665 static void gen_spr_ne_601 (CPUPPCState *env)
666 {
667 /* Exception processing */
668 spr_register(env, SPR_DSISR, "DSISR",
669 SPR_NOACCESS, SPR_NOACCESS,
670 &spr_read_generic, &spr_write_generic,
671 0x00000000);
672 spr_register(env, SPR_DAR, "DAR",
673 SPR_NOACCESS, SPR_NOACCESS,
674 &spr_read_generic, &spr_write_generic,
675 0x00000000);
676 /* Timer */
677 spr_register(env, SPR_DECR, "DECR",
678 SPR_NOACCESS, SPR_NOACCESS,
679 &spr_read_decr, &spr_write_decr,
680 0x00000000);
681 /* Memory management */
682 spr_register(env, SPR_SDR1, "SDR1",
683 SPR_NOACCESS, SPR_NOACCESS,
684 &spr_read_generic, &spr_write_sdr1,
685 0x00000000);
686 }
687
688 /* BATs 0-3 */
689 static void gen_low_BATs (CPUPPCState *env)
690 {
691 #if !defined(CONFIG_USER_ONLY)
692 spr_register(env, SPR_IBAT0U, "IBAT0U",
693 SPR_NOACCESS, SPR_NOACCESS,
694 &spr_read_ibat, &spr_write_ibatu,
695 0x00000000);
696 spr_register(env, SPR_IBAT0L, "IBAT0L",
697 SPR_NOACCESS, SPR_NOACCESS,
698 &spr_read_ibat, &spr_write_ibatl,
699 0x00000000);
700 spr_register(env, SPR_IBAT1U, "IBAT1U",
701 SPR_NOACCESS, SPR_NOACCESS,
702 &spr_read_ibat, &spr_write_ibatu,
703 0x00000000);
704 spr_register(env, SPR_IBAT1L, "IBAT1L",
705 SPR_NOACCESS, SPR_NOACCESS,
706 &spr_read_ibat, &spr_write_ibatl,
707 0x00000000);
708 spr_register(env, SPR_IBAT2U, "IBAT2U",
709 SPR_NOACCESS, SPR_NOACCESS,
710 &spr_read_ibat, &spr_write_ibatu,
711 0x00000000);
712 spr_register(env, SPR_IBAT2L, "IBAT2L",
713 SPR_NOACCESS, SPR_NOACCESS,
714 &spr_read_ibat, &spr_write_ibatl,
715 0x00000000);
716 spr_register(env, SPR_IBAT3U, "IBAT3U",
717 SPR_NOACCESS, SPR_NOACCESS,
718 &spr_read_ibat, &spr_write_ibatu,
719 0x00000000);
720 spr_register(env, SPR_IBAT3L, "IBAT3L",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_ibat, &spr_write_ibatl,
723 0x00000000);
724 spr_register(env, SPR_DBAT0U, "DBAT0U",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_dbat, &spr_write_dbatu,
727 0x00000000);
728 spr_register(env, SPR_DBAT0L, "DBAT0L",
729 SPR_NOACCESS, SPR_NOACCESS,
730 &spr_read_dbat, &spr_write_dbatl,
731 0x00000000);
732 spr_register(env, SPR_DBAT1U, "DBAT1U",
733 SPR_NOACCESS, SPR_NOACCESS,
734 &spr_read_dbat, &spr_write_dbatu,
735 0x00000000);
736 spr_register(env, SPR_DBAT1L, "DBAT1L",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_dbat, &spr_write_dbatl,
739 0x00000000);
740 spr_register(env, SPR_DBAT2U, "DBAT2U",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_dbat, &spr_write_dbatu,
743 0x00000000);
744 spr_register(env, SPR_DBAT2L, "DBAT2L",
745 SPR_NOACCESS, SPR_NOACCESS,
746 &spr_read_dbat, &spr_write_dbatl,
747 0x00000000);
748 spr_register(env, SPR_DBAT3U, "DBAT3U",
749 SPR_NOACCESS, SPR_NOACCESS,
750 &spr_read_dbat, &spr_write_dbatu,
751 0x00000000);
752 spr_register(env, SPR_DBAT3L, "DBAT3L",
753 SPR_NOACCESS, SPR_NOACCESS,
754 &spr_read_dbat, &spr_write_dbatl,
755 0x00000000);
756 env->nb_BATs += 4;
757 #endif
758 }
759
760 /* BATs 4-7 */
761 static void gen_high_BATs (CPUPPCState *env)
762 {
763 #if !defined(CONFIG_USER_ONLY)
764 spr_register(env, SPR_IBAT4U, "IBAT4U",
765 SPR_NOACCESS, SPR_NOACCESS,
766 &spr_read_ibat_h, &spr_write_ibatu_h,
767 0x00000000);
768 spr_register(env, SPR_IBAT4L, "IBAT4L",
769 SPR_NOACCESS, SPR_NOACCESS,
770 &spr_read_ibat_h, &spr_write_ibatl_h,
771 0x00000000);
772 spr_register(env, SPR_IBAT5U, "IBAT5U",
773 SPR_NOACCESS, SPR_NOACCESS,
774 &spr_read_ibat_h, &spr_write_ibatu_h,
775 0x00000000);
776 spr_register(env, SPR_IBAT5L, "IBAT5L",
777 SPR_NOACCESS, SPR_NOACCESS,
778 &spr_read_ibat_h, &spr_write_ibatl_h,
779 0x00000000);
780 spr_register(env, SPR_IBAT6U, "IBAT6U",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_ibat_h, &spr_write_ibatu_h,
783 0x00000000);
784 spr_register(env, SPR_IBAT6L, "IBAT6L",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_ibat_h, &spr_write_ibatl_h,
787 0x00000000);
788 spr_register(env, SPR_IBAT7U, "IBAT7U",
789 SPR_NOACCESS, SPR_NOACCESS,
790 &spr_read_ibat_h, &spr_write_ibatu_h,
791 0x00000000);
792 spr_register(env, SPR_IBAT7L, "IBAT7L",
793 SPR_NOACCESS, SPR_NOACCESS,
794 &spr_read_ibat_h, &spr_write_ibatl_h,
795 0x00000000);
796 spr_register(env, SPR_DBAT4U, "DBAT4U",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_dbat_h, &spr_write_dbatu_h,
799 0x00000000);
800 spr_register(env, SPR_DBAT4L, "DBAT4L",
801 SPR_NOACCESS, SPR_NOACCESS,
802 &spr_read_dbat_h, &spr_write_dbatl_h,
803 0x00000000);
804 spr_register(env, SPR_DBAT5U, "DBAT5U",
805 SPR_NOACCESS, SPR_NOACCESS,
806 &spr_read_dbat_h, &spr_write_dbatu_h,
807 0x00000000);
808 spr_register(env, SPR_DBAT5L, "DBAT5L",
809 SPR_NOACCESS, SPR_NOACCESS,
810 &spr_read_dbat_h, &spr_write_dbatl_h,
811 0x00000000);
812 spr_register(env, SPR_DBAT6U, "DBAT6U",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_dbat_h, &spr_write_dbatu_h,
815 0x00000000);
816 spr_register(env, SPR_DBAT6L, "DBAT6L",
817 SPR_NOACCESS, SPR_NOACCESS,
818 &spr_read_dbat_h, &spr_write_dbatl_h,
819 0x00000000);
820 spr_register(env, SPR_DBAT7U, "DBAT7U",
821 SPR_NOACCESS, SPR_NOACCESS,
822 &spr_read_dbat_h, &spr_write_dbatu_h,
823 0x00000000);
824 spr_register(env, SPR_DBAT7L, "DBAT7L",
825 SPR_NOACCESS, SPR_NOACCESS,
826 &spr_read_dbat_h, &spr_write_dbatl_h,
827 0x00000000);
828 env->nb_BATs += 4;
829 #endif
830 }
831
832 /* Generic PowerPC time base */
833 static void gen_tbl (CPUPPCState *env)
834 {
835 spr_register(env, SPR_VTBL, "TBL",
836 &spr_read_tbl, SPR_NOACCESS,
837 &spr_read_tbl, SPR_NOACCESS,
838 0x00000000);
839 spr_register(env, SPR_TBL, "TBL",
840 &spr_read_tbl, SPR_NOACCESS,
841 &spr_read_tbl, &spr_write_tbl,
842 0x00000000);
843 spr_register(env, SPR_VTBU, "TBU",
844 &spr_read_tbu, SPR_NOACCESS,
845 &spr_read_tbu, SPR_NOACCESS,
846 0x00000000);
847 spr_register(env, SPR_TBU, "TBU",
848 &spr_read_tbu, SPR_NOACCESS,
849 &spr_read_tbu, &spr_write_tbu,
850 0x00000000);
851 }
852
853 /* Softare table search registers */
854 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
855 {
856 #if !defined(CONFIG_USER_ONLY)
857 env->nb_tlb = nb_tlbs;
858 env->nb_ways = nb_ways;
859 env->id_tlbs = 1;
860 env->tlb_type = TLB_6XX;
861 spr_register(env, SPR_DMISS, "DMISS",
862 SPR_NOACCESS, SPR_NOACCESS,
863 &spr_read_generic, SPR_NOACCESS,
864 0x00000000);
865 spr_register(env, SPR_DCMP, "DCMP",
866 SPR_NOACCESS, SPR_NOACCESS,
867 &spr_read_generic, SPR_NOACCESS,
868 0x00000000);
869 spr_register(env, SPR_HASH1, "HASH1",
870 SPR_NOACCESS, SPR_NOACCESS,
871 &spr_read_generic, SPR_NOACCESS,
872 0x00000000);
873 spr_register(env, SPR_HASH2, "HASH2",
874 SPR_NOACCESS, SPR_NOACCESS,
875 &spr_read_generic, SPR_NOACCESS,
876 0x00000000);
877 spr_register(env, SPR_IMISS, "IMISS",
878 SPR_NOACCESS, SPR_NOACCESS,
879 &spr_read_generic, SPR_NOACCESS,
880 0x00000000);
881 spr_register(env, SPR_ICMP, "ICMP",
882 SPR_NOACCESS, SPR_NOACCESS,
883 &spr_read_generic, SPR_NOACCESS,
884 0x00000000);
885 spr_register(env, SPR_RPA, "RPA",
886 SPR_NOACCESS, SPR_NOACCESS,
887 &spr_read_generic, &spr_write_generic,
888 0x00000000);
889 #endif
890 }
891
892 /* SPR common to MPC755 and G2 */
893 static void gen_spr_G2_755 (CPUPPCState *env)
894 {
895 /* SGPRs */
896 spr_register(env, SPR_SPRG4, "SPRG4",
897 SPR_NOACCESS, SPR_NOACCESS,
898 &spr_read_generic, &spr_write_generic,
899 0x00000000);
900 spr_register(env, SPR_SPRG5, "SPRG5",
901 SPR_NOACCESS, SPR_NOACCESS,
902 &spr_read_generic, &spr_write_generic,
903 0x00000000);
904 spr_register(env, SPR_SPRG6, "SPRG6",
905 SPR_NOACCESS, SPR_NOACCESS,
906 &spr_read_generic, &spr_write_generic,
907 0x00000000);
908 spr_register(env, SPR_SPRG7, "SPRG7",
909 SPR_NOACCESS, SPR_NOACCESS,
910 &spr_read_generic, &spr_write_generic,
911 0x00000000);
912 }
913
914 /* SPR common to all 7xx PowerPC implementations */
915 static void gen_spr_7xx (CPUPPCState *env)
916 {
917 /* Breakpoints */
918 /* XXX : not implemented */
919 spr_register(env, SPR_DABR, "DABR",
920 SPR_NOACCESS, SPR_NOACCESS,
921 &spr_read_generic, &spr_write_generic,
922 0x00000000);
923 /* XXX : not implemented */
924 spr_register(env, SPR_IABR, "IABR",
925 SPR_NOACCESS, SPR_NOACCESS,
926 &spr_read_generic, &spr_write_generic,
927 0x00000000);
928 /* Cache management */
929 /* XXX : not implemented */
930 spr_register(env, SPR_ICTC, "ICTC",
931 SPR_NOACCESS, SPR_NOACCESS,
932 &spr_read_generic, &spr_write_generic,
933 0x00000000);
934 /* Performance monitors */
935 /* XXX : not implemented */
936 spr_register(env, SPR_MMCR0, "MMCR0",
937 SPR_NOACCESS, SPR_NOACCESS,
938 &spr_read_generic, &spr_write_generic,
939 0x00000000);
940 /* XXX : not implemented */
941 spr_register(env, SPR_MMCR1, "MMCR1",
942 SPR_NOACCESS, SPR_NOACCESS,
943 &spr_read_generic, &spr_write_generic,
944 0x00000000);
945 /* XXX : not implemented */
946 spr_register(env, SPR_PMC1, "PMC1",
947 SPR_NOACCESS, SPR_NOACCESS,
948 &spr_read_generic, &spr_write_generic,
949 0x00000000);
950 /* XXX : not implemented */
951 spr_register(env, SPR_PMC2, "PMC2",
952 SPR_NOACCESS, SPR_NOACCESS,
953 &spr_read_generic, &spr_write_generic,
954 0x00000000);
955 /* XXX : not implemented */
956 spr_register(env, SPR_PMC3, "PMC3",
957 SPR_NOACCESS, SPR_NOACCESS,
958 &spr_read_generic, &spr_write_generic,
959 0x00000000);
960 /* XXX : not implemented */
961 spr_register(env, SPR_PMC4, "PMC4",
962 SPR_NOACCESS, SPR_NOACCESS,
963 &spr_read_generic, &spr_write_generic,
964 0x00000000);
965 /* XXX : not implemented */
966 spr_register(env, SPR_SIAR, "SIAR",
967 SPR_NOACCESS, SPR_NOACCESS,
968 &spr_read_generic, SPR_NOACCESS,
969 0x00000000);
970 /* XXX : not implemented */
971 spr_register(env, SPR_UMMCR0, "UMMCR0",
972 &spr_read_ureg, SPR_NOACCESS,
973 &spr_read_ureg, SPR_NOACCESS,
974 0x00000000);
975 /* XXX : not implemented */
976 spr_register(env, SPR_UMMCR1, "UMMCR1",
977 &spr_read_ureg, SPR_NOACCESS,
978 &spr_read_ureg, SPR_NOACCESS,
979 0x00000000);
980 /* XXX : not implemented */
981 spr_register(env, SPR_UPMC1, "UPMC1",
982 &spr_read_ureg, SPR_NOACCESS,
983 &spr_read_ureg, SPR_NOACCESS,
984 0x00000000);
985 /* XXX : not implemented */
986 spr_register(env, SPR_UPMC2, "UPMC2",
987 &spr_read_ureg, SPR_NOACCESS,
988 &spr_read_ureg, SPR_NOACCESS,
989 0x00000000);
990 /* XXX : not implemented */
991 spr_register(env, SPR_UPMC3, "UPMC3",
992 &spr_read_ureg, SPR_NOACCESS,
993 &spr_read_ureg, SPR_NOACCESS,
994 0x00000000);
995 /* XXX : not implemented */
996 spr_register(env, SPR_UPMC4, "UPMC4",
997 &spr_read_ureg, SPR_NOACCESS,
998 &spr_read_ureg, SPR_NOACCESS,
999 0x00000000);
1000 /* XXX : not implemented */
1001 spr_register(env, SPR_USIAR, "USIAR",
1002 &spr_read_ureg, SPR_NOACCESS,
1003 &spr_read_ureg, SPR_NOACCESS,
1004 0x00000000);
1005 /* External access control */
1006 /* XXX : not implemented */
1007 spr_register(env, SPR_EAR, "EAR",
1008 SPR_NOACCESS, SPR_NOACCESS,
1009 &spr_read_generic, &spr_write_generic,
1010 0x00000000);
1011 }
1012
1013 static void gen_spr_thrm (CPUPPCState *env)
1014 {
1015 /* Thermal management */
1016 /* XXX : not implemented */
1017 spr_register(env, SPR_THRM1, "THRM1",
1018 SPR_NOACCESS, SPR_NOACCESS,
1019 &spr_read_generic, &spr_write_generic,
1020 0x00000000);
1021 /* XXX : not implemented */
1022 spr_register(env, SPR_THRM2, "THRM2",
1023 SPR_NOACCESS, SPR_NOACCESS,
1024 &spr_read_generic, &spr_write_generic,
1025 0x00000000);
1026 /* XXX : not implemented */
1027 spr_register(env, SPR_THRM3, "THRM3",
1028 SPR_NOACCESS, SPR_NOACCESS,
1029 &spr_read_generic, &spr_write_generic,
1030 0x00000000);
1031 }
1032
1033 /* SPR specific to PowerPC 604 implementation */
1034 static void gen_spr_604 (CPUPPCState *env)
1035 {
1036 /* Processor identification */
1037 spr_register(env, SPR_PIR, "PIR",
1038 SPR_NOACCESS, SPR_NOACCESS,
1039 &spr_read_generic, &spr_write_pir,
1040 0x00000000);
1041 /* Breakpoints */
1042 /* XXX : not implemented */
1043 spr_register(env, SPR_IABR, "IABR",
1044 SPR_NOACCESS, SPR_NOACCESS,
1045 &spr_read_generic, &spr_write_generic,
1046 0x00000000);
1047 /* XXX : not implemented */
1048 spr_register(env, SPR_DABR, "DABR",
1049 SPR_NOACCESS, SPR_NOACCESS,
1050 &spr_read_generic, &spr_write_generic,
1051 0x00000000);
1052 /* Performance counters */
1053 /* XXX : not implemented */
1054 spr_register(env, SPR_MMCR0, "MMCR0",
1055 SPR_NOACCESS, SPR_NOACCESS,
1056 &spr_read_generic, &spr_write_generic,
1057 0x00000000);
1058 /* XXX : not implemented */
1059 spr_register(env, SPR_PMC1, "PMC1",
1060 SPR_NOACCESS, SPR_NOACCESS,
1061 &spr_read_generic, &spr_write_generic,
1062 0x00000000);
1063 /* XXX : not implemented */
1064 spr_register(env, SPR_PMC2, "PMC2",
1065 SPR_NOACCESS, SPR_NOACCESS,
1066 &spr_read_generic, &spr_write_generic,
1067 0x00000000);
1068 /* XXX : not implemented */
1069 spr_register(env, SPR_SIAR, "SIAR",
1070 SPR_NOACCESS, SPR_NOACCESS,
1071 &spr_read_generic, SPR_NOACCESS,
1072 0x00000000);
1073 /* XXX : not implemented */
1074 spr_register(env, SPR_SDA, "SDA",
1075 SPR_NOACCESS, SPR_NOACCESS,
1076 &spr_read_generic, SPR_NOACCESS,
1077 0x00000000);
1078 /* External access control */
1079 /* XXX : not implemented */
1080 spr_register(env, SPR_EAR, "EAR",
1081 SPR_NOACCESS, SPR_NOACCESS,
1082 &spr_read_generic, &spr_write_generic,
1083 0x00000000);
1084 }
1085
1086 /* SPR specific to PowerPC 603 implementation */
1087 static void gen_spr_603 (CPUPPCState *env)
1088 {
1089 /* External access control */
1090 /* XXX : not implemented */
1091 spr_register(env, SPR_EAR, "EAR",
1092 SPR_NOACCESS, SPR_NOACCESS,
1093 &spr_read_generic, &spr_write_generic,
1094 0x00000000);
1095 }
1096
1097 /* SPR specific to PowerPC G2 implementation */
1098 static void gen_spr_G2 (CPUPPCState *env)
1099 {
1100 /* Memory base address */
1101 /* MBAR */
1102 /* XXX : not implemented */
1103 spr_register(env, SPR_MBAR, "MBAR",
1104 SPR_NOACCESS, SPR_NOACCESS,
1105 &spr_read_generic, &spr_write_generic,
1106 0x00000000);
1107 /* Exception processing */
1108 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1109 SPR_NOACCESS, SPR_NOACCESS,
1110 &spr_read_generic, &spr_write_generic,
1111 0x00000000);
1112 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1113 SPR_NOACCESS, SPR_NOACCESS,
1114 &spr_read_generic, &spr_write_generic,
1115 0x00000000);
1116 /* Breakpoints */
1117 /* XXX : not implemented */
1118 spr_register(env, SPR_DABR, "DABR",
1119 SPR_NOACCESS, SPR_NOACCESS,
1120 &spr_read_generic, &spr_write_generic,
1121 0x00000000);
1122 /* XXX : not implemented */
1123 spr_register(env, SPR_DABR2, "DABR2",
1124 SPR_NOACCESS, SPR_NOACCESS,
1125 &spr_read_generic, &spr_write_generic,
1126 0x00000000);
1127 /* XXX : not implemented */
1128 spr_register(env, SPR_IABR, "IABR",
1129 SPR_NOACCESS, SPR_NOACCESS,
1130 &spr_read_generic, &spr_write_generic,
1131 0x00000000);
1132 /* XXX : not implemented */
1133 spr_register(env, SPR_IABR2, "IABR2",
1134 SPR_NOACCESS, SPR_NOACCESS,
1135 &spr_read_generic, &spr_write_generic,
1136 0x00000000);
1137 /* XXX : not implemented */
1138 spr_register(env, SPR_IBCR, "IBCR",
1139 SPR_NOACCESS, SPR_NOACCESS,
1140 &spr_read_generic, &spr_write_generic,
1141 0x00000000);
1142 /* XXX : not implemented */
1143 spr_register(env, SPR_DBCR, "DBCR",
1144 SPR_NOACCESS, SPR_NOACCESS,
1145 &spr_read_generic, &spr_write_generic,
1146 0x00000000);
1147 }
1148
1149 /* SPR specific to PowerPC 602 implementation */
1150 static void gen_spr_602 (CPUPPCState *env)
1151 {
1152 /* ESA registers */
1153 /* XXX : not implemented */
1154 spr_register(env, SPR_SER, "SER",
1155 SPR_NOACCESS, SPR_NOACCESS,
1156 &spr_read_generic, &spr_write_generic,
1157 0x00000000);
1158 /* XXX : not implemented */
1159 spr_register(env, SPR_SEBR, "SEBR",
1160 SPR_NOACCESS, SPR_NOACCESS,
1161 &spr_read_generic, &spr_write_generic,
1162 0x00000000);
1163 /* XXX : not implemented */
1164 spr_register(env, SPR_ESASRR, "ESASRR",
1165 SPR_NOACCESS, SPR_NOACCESS,
1166 &spr_read_generic, &spr_write_generic,
1167 0x00000000);
1168 /* Floating point status */
1169 /* XXX : not implemented */
1170 spr_register(env, SPR_SP, "SP",
1171 SPR_NOACCESS, SPR_NOACCESS,
1172 &spr_read_generic, &spr_write_generic,
1173 0x00000000);
1174 /* XXX : not implemented */
1175 spr_register(env, SPR_LT, "LT",
1176 SPR_NOACCESS, SPR_NOACCESS,
1177 &spr_read_generic, &spr_write_generic,
1178 0x00000000);
1179 /* Watchdog timer */
1180 /* XXX : not implemented */
1181 spr_register(env, SPR_TCR, "TCR",
1182 SPR_NOACCESS, SPR_NOACCESS,
1183 &spr_read_generic, &spr_write_generic,
1184 0x00000000);
1185 /* Interrupt base */
1186 spr_register(env, SPR_IBR, "IBR",
1187 SPR_NOACCESS, SPR_NOACCESS,
1188 &spr_read_generic, &spr_write_generic,
1189 0x00000000);
1190 /* XXX : not implemented */
1191 spr_register(env, SPR_IABR, "IABR",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
1195 }
1196
1197 /* SPR specific to PowerPC 601 implementation */
1198 static void gen_spr_601 (CPUPPCState *env)
1199 {
1200 /* Multiplication/division register */
1201 /* MQ */
1202 spr_register(env, SPR_MQ, "MQ",
1203 &spr_read_generic, &spr_write_generic,
1204 &spr_read_generic, &spr_write_generic,
1205 0x00000000);
1206 /* RTC registers */
1207 spr_register(env, SPR_601_RTCU, "RTCU",
1208 SPR_NOACCESS, SPR_NOACCESS,
1209 SPR_NOACCESS, &spr_write_601_rtcu,
1210 0x00000000);
1211 spr_register(env, SPR_601_VRTCU, "RTCU",
1212 &spr_read_601_rtcu, SPR_NOACCESS,
1213 &spr_read_601_rtcu, SPR_NOACCESS,
1214 0x00000000);
1215 spr_register(env, SPR_601_RTCL, "RTCL",
1216 SPR_NOACCESS, SPR_NOACCESS,
1217 SPR_NOACCESS, &spr_write_601_rtcl,
1218 0x00000000);
1219 spr_register(env, SPR_601_VRTCL, "RTCL",
1220 &spr_read_601_rtcl, SPR_NOACCESS,
1221 &spr_read_601_rtcl, SPR_NOACCESS,
1222 0x00000000);
1223 /* Timer */
1224 #if 0 /* ? */
1225 spr_register(env, SPR_601_UDECR, "UDECR",
1226 &spr_read_decr, SPR_NOACCESS,
1227 &spr_read_decr, SPR_NOACCESS,
1228 0x00000000);
1229 #endif
1230 /* External access control */
1231 /* XXX : not implemented */
1232 spr_register(env, SPR_EAR, "EAR",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_generic, &spr_write_generic,
1235 0x00000000);
1236 /* Memory management */
1237 #if !defined(CONFIG_USER_ONLY)
1238 spr_register(env, SPR_IBAT0U, "IBAT0U",
1239 SPR_NOACCESS, SPR_NOACCESS,
1240 &spr_read_601_ubat, &spr_write_601_ubatu,
1241 0x00000000);
1242 spr_register(env, SPR_IBAT0L, "IBAT0L",
1243 SPR_NOACCESS, SPR_NOACCESS,
1244 &spr_read_601_ubat, &spr_write_601_ubatl,
1245 0x00000000);
1246 spr_register(env, SPR_IBAT1U, "IBAT1U",
1247 SPR_NOACCESS, SPR_NOACCESS,
1248 &spr_read_601_ubat, &spr_write_601_ubatu,
1249 0x00000000);
1250 spr_register(env, SPR_IBAT1L, "IBAT1L",
1251 SPR_NOACCESS, SPR_NOACCESS,
1252 &spr_read_601_ubat, &spr_write_601_ubatl,
1253 0x00000000);
1254 spr_register(env, SPR_IBAT2U, "IBAT2U",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_601_ubat, &spr_write_601_ubatu,
1257 0x00000000);
1258 spr_register(env, SPR_IBAT2L, "IBAT2L",
1259 SPR_NOACCESS, SPR_NOACCESS,
1260 &spr_read_601_ubat, &spr_write_601_ubatl,
1261 0x00000000);
1262 spr_register(env, SPR_IBAT3U, "IBAT3U",
1263 SPR_NOACCESS, SPR_NOACCESS,
1264 &spr_read_601_ubat, &spr_write_601_ubatu,
1265 0x00000000);
1266 spr_register(env, SPR_IBAT3L, "IBAT3L",
1267 SPR_NOACCESS, SPR_NOACCESS,
1268 &spr_read_601_ubat, &spr_write_601_ubatl,
1269 0x00000000);
1270 env->nb_BATs = 4;
1271 #endif
1272 }
1273
1274 static void gen_spr_74xx (CPUPPCState *env)
1275 {
1276 /* Processor identification */
1277 spr_register(env, SPR_PIR, "PIR",
1278 SPR_NOACCESS, SPR_NOACCESS,
1279 &spr_read_generic, &spr_write_pir,
1280 0x00000000);
1281 /* XXX : not implemented */
1282 spr_register(env, SPR_MMCR2, "MMCR2",
1283 SPR_NOACCESS, SPR_NOACCESS,
1284 &spr_read_generic, &spr_write_generic,
1285 0x00000000);
1286 /* XXX : not implemented */
1287 spr_register(env, SPR_UMMCR2, "UMMCR2",
1288 &spr_read_ureg, SPR_NOACCESS,
1289 &spr_read_ureg, SPR_NOACCESS,
1290 0x00000000);
1291 /* XXX: not implemented */
1292 spr_register(env, SPR_BAMR, "BAMR",
1293 SPR_NOACCESS, SPR_NOACCESS,
1294 &spr_read_generic, &spr_write_generic,
1295 0x00000000);
1296 /* XXX : not implemented */
1297 spr_register(env, SPR_MSSCR0, "MSSCR0",
1298 SPR_NOACCESS, SPR_NOACCESS,
1299 &spr_read_generic, &spr_write_generic,
1300 0x00000000);
1301 /* Hardware implementation registers */
1302 /* XXX : not implemented */
1303 spr_register(env, SPR_HID0, "HID0",
1304 SPR_NOACCESS, SPR_NOACCESS,
1305 &spr_read_generic, &spr_write_generic,
1306 0x00000000);
1307 /* XXX : not implemented */
1308 spr_register(env, SPR_HID1, "HID1",
1309 SPR_NOACCESS, SPR_NOACCESS,
1310 &spr_read_generic, &spr_write_generic,
1311 0x00000000);
1312 /* Altivec */
1313 spr_register(env, SPR_VRSAVE, "VRSAVE",
1314 &spr_read_generic, &spr_write_generic,
1315 &spr_read_generic, &spr_write_generic,
1316 0x00000000);
1317 /* XXX : not implemented */
1318 spr_register(env, SPR_L2CR, "L2CR",
1319 SPR_NOACCESS, SPR_NOACCESS,
1320 &spr_read_generic, &spr_write_generic,
1321 0x00000000);
1322 /* Not strictly an SPR */
1323 vscr_init(env, 0x00010000);
1324 }
1325
1326 static void gen_l3_ctrl (CPUPPCState *env)
1327 {
1328 /* L3CR */
1329 /* XXX : not implemented */
1330 spr_register(env, SPR_L3CR, "L3CR",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1333 0x00000000);
1334 /* L3ITCR0 */
1335 /* XXX : not implemented */
1336 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1337 SPR_NOACCESS, SPR_NOACCESS,
1338 &spr_read_generic, &spr_write_generic,
1339 0x00000000);
1340 /* L3PM */
1341 /* XXX : not implemented */
1342 spr_register(env, SPR_L3PM, "L3PM",
1343 SPR_NOACCESS, SPR_NOACCESS,
1344 &spr_read_generic, &spr_write_generic,
1345 0x00000000);
1346 }
1347
1348 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1349 {
1350 #if !defined(CONFIG_USER_ONLY)
1351 env->nb_tlb = nb_tlbs;
1352 env->nb_ways = nb_ways;
1353 env->id_tlbs = 1;
1354 env->tlb_type = TLB_6XX;
1355 /* XXX : not implemented */
1356 spr_register(env, SPR_PTEHI, "PTEHI",
1357 SPR_NOACCESS, SPR_NOACCESS,
1358 &spr_read_generic, &spr_write_generic,
1359 0x00000000);
1360 /* XXX : not implemented */
1361 spr_register(env, SPR_PTELO, "PTELO",
1362 SPR_NOACCESS, SPR_NOACCESS,
1363 &spr_read_generic, &spr_write_generic,
1364 0x00000000);
1365 /* XXX : not implemented */
1366 spr_register(env, SPR_TLBMISS, "TLBMISS",
1367 SPR_NOACCESS, SPR_NOACCESS,
1368 &spr_read_generic, &spr_write_generic,
1369 0x00000000);
1370 #endif
1371 }
1372
1373 #if !defined(CONFIG_USER_ONLY)
1374 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1375 {
1376 TCGv t0 = tcg_temp_new();
1377
1378 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1379 gen_store_spr(sprn, t0);
1380 tcg_temp_free(t0);
1381 }
1382
1383 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1384 {
1385 TCGv_i32 t0 = tcg_const_i32(sprn);
1386 gen_helper_booke206_tlbflush(t0);
1387 tcg_temp_free_i32(t0);
1388 }
1389
1390 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1391 {
1392 TCGv_i32 t0 = tcg_const_i32(sprn);
1393 gen_helper_booke_setpid(t0, cpu_gpr[gprn]);
1394 tcg_temp_free_i32(t0);
1395 }
1396 #endif
1397
1398 static void gen_spr_usprgh (CPUPPCState *env)
1399 {
1400 spr_register(env, SPR_USPRG4, "USPRG4",
1401 &spr_read_ureg, SPR_NOACCESS,
1402 &spr_read_ureg, SPR_NOACCESS,
1403 0x00000000);
1404 spr_register(env, SPR_USPRG5, "USPRG5",
1405 &spr_read_ureg, SPR_NOACCESS,
1406 &spr_read_ureg, SPR_NOACCESS,
1407 0x00000000);
1408 spr_register(env, SPR_USPRG6, "USPRG6",
1409 &spr_read_ureg, SPR_NOACCESS,
1410 &spr_read_ureg, SPR_NOACCESS,
1411 0x00000000);
1412 spr_register(env, SPR_USPRG7, "USPRG7",
1413 &spr_read_ureg, SPR_NOACCESS,
1414 &spr_read_ureg, SPR_NOACCESS,
1415 0x00000000);
1416 }
1417
1418 /* PowerPC BookE SPR */
1419 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1420 {
1421 const char *ivor_names[64] = {
1422 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1423 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1424 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1425 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1426 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1427 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1428 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1429 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1430 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1431 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1432 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1433 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1434 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1435 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1436 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1437 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1438 };
1439 #define SPR_BOOKE_IVORxx (-1)
1440 int ivor_sprn[64] = {
1441 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1442 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1443 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1444 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1445 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1446 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1447 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1448 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1449 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1450 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1451 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1452 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1453 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1454 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1455 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1456 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1457 };
1458 int i;
1459
1460 /* Interrupt processing */
1461 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1462 SPR_NOACCESS, SPR_NOACCESS,
1463 &spr_read_generic, &spr_write_generic,
1464 0x00000000);
1465 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1466 SPR_NOACCESS, SPR_NOACCESS,
1467 &spr_read_generic, &spr_write_generic,
1468 0x00000000);
1469 /* Debug */
1470 /* XXX : not implemented */
1471 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1472 SPR_NOACCESS, SPR_NOACCESS,
1473 &spr_read_generic, &spr_write_generic,
1474 0x00000000);
1475 /* XXX : not implemented */
1476 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1477 SPR_NOACCESS, SPR_NOACCESS,
1478 &spr_read_generic, &spr_write_generic,
1479 0x00000000);
1480 /* XXX : not implemented */
1481 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1482 SPR_NOACCESS, SPR_NOACCESS,
1483 &spr_read_generic, &spr_write_generic,
1484 0x00000000);
1485 /* XXX : not implemented */
1486 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1487 SPR_NOACCESS, SPR_NOACCESS,
1488 &spr_read_generic, &spr_write_generic,
1489 0x00000000);
1490 /* XXX : not implemented */
1491 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1492 SPR_NOACCESS, SPR_NOACCESS,
1493 &spr_read_generic, &spr_write_generic,
1494 0x00000000);
1495 /* XXX : not implemented */
1496 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1497 SPR_NOACCESS, SPR_NOACCESS,
1498 &spr_read_generic, &spr_write_generic,
1499 0x00000000);
1500 /* XXX : not implemented */
1501 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1502 SPR_NOACCESS, SPR_NOACCESS,
1503 &spr_read_generic, &spr_write_generic,
1504 0x00000000);
1505 /* XXX : not implemented */
1506 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1507 SPR_NOACCESS, SPR_NOACCESS,
1508 &spr_read_generic, &spr_write_clear,
1509 0x00000000);
1510 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1511 SPR_NOACCESS, SPR_NOACCESS,
1512 &spr_read_generic, &spr_write_generic,
1513 0x00000000);
1514 spr_register(env, SPR_BOOKE_ESR, "ESR",
1515 SPR_NOACCESS, SPR_NOACCESS,
1516 &spr_read_generic, &spr_write_generic,
1517 0x00000000);
1518 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1519 SPR_NOACCESS, SPR_NOACCESS,
1520 &spr_read_generic, &spr_write_excp_prefix,
1521 0x00000000);
1522 /* Exception vectors */
1523 for (i = 0; i < 64; i++) {
1524 if (ivor_mask & (1ULL << i)) {
1525 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1526 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1527 exit(1);
1528 }
1529 spr_register(env, ivor_sprn[i], ivor_names[i],
1530 SPR_NOACCESS, SPR_NOACCESS,
1531 &spr_read_generic, &spr_write_excp_vector,
1532 0x00000000);
1533 }
1534 }
1535 spr_register(env, SPR_BOOKE_PID, "PID",
1536 SPR_NOACCESS, SPR_NOACCESS,
1537 &spr_read_generic, &spr_write_booke_pid,
1538 0x00000000);
1539 spr_register(env, SPR_BOOKE_TCR, "TCR",
1540 SPR_NOACCESS, SPR_NOACCESS,
1541 &spr_read_generic, &spr_write_booke_tcr,
1542 0x00000000);
1543 spr_register(env, SPR_BOOKE_TSR, "TSR",
1544 SPR_NOACCESS, SPR_NOACCESS,
1545 &spr_read_generic, &spr_write_booke_tsr,
1546 0x00000000);
1547 /* Timer */
1548 spr_register(env, SPR_DECR, "DECR",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_decr, &spr_write_decr,
1551 0x00000000);
1552 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1553 SPR_NOACCESS, SPR_NOACCESS,
1554 SPR_NOACCESS, &spr_write_generic,
1555 0x00000000);
1556 /* SPRGs */
1557 spr_register(env, SPR_USPRG0, "USPRG0",
1558 &spr_read_generic, &spr_write_generic,
1559 &spr_read_generic, &spr_write_generic,
1560 0x00000000);
1561 spr_register(env, SPR_SPRG4, "SPRG4",
1562 SPR_NOACCESS, SPR_NOACCESS,
1563 &spr_read_generic, &spr_write_generic,
1564 0x00000000);
1565 spr_register(env, SPR_SPRG5, "SPRG5",
1566 SPR_NOACCESS, SPR_NOACCESS,
1567 &spr_read_generic, &spr_write_generic,
1568 0x00000000);
1569 spr_register(env, SPR_SPRG6, "SPRG6",
1570 SPR_NOACCESS, SPR_NOACCESS,
1571 &spr_read_generic, &spr_write_generic,
1572 0x00000000);
1573 spr_register(env, SPR_SPRG7, "SPRG7",
1574 SPR_NOACCESS, SPR_NOACCESS,
1575 &spr_read_generic, &spr_write_generic,
1576 0x00000000);
1577 }
1578
1579 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1580 uint32_t maxsize, uint32_t flags,
1581 uint32_t nentries)
1582 {
1583 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1584 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1585 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1586 flags | nentries;
1587 }
1588
1589 /* BookE 2.06 storage control registers */
1590 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1591 uint32_t *tlbncfg)
1592 {
1593 #if !defined(CONFIG_USER_ONLY)
1594 const char *mas_names[8] = {
1595 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1596 };
1597 int mas_sprn[8] = {
1598 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1599 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1600 };
1601 int i;
1602
1603 /* TLB assist registers */
1604 /* XXX : not implemented */
1605 for (i = 0; i < 8; i++) {
1606 if (mas_mask & (1 << i)) {
1607 spr_register(env, mas_sprn[i], mas_names[i],
1608 SPR_NOACCESS, SPR_NOACCESS,
1609 &spr_read_generic, &spr_write_generic,
1610 0x00000000);
1611 }
1612 }
1613 if (env->nb_pids > 1) {
1614 /* XXX : not implemented */
1615 spr_register(env, SPR_BOOKE_PID1, "PID1",
1616 SPR_NOACCESS, SPR_NOACCESS,
1617 &spr_read_generic, &spr_write_booke_pid,
1618 0x00000000);
1619 }
1620 if (env->nb_pids > 2) {
1621 /* XXX : not implemented */
1622 spr_register(env, SPR_BOOKE_PID2, "PID2",
1623 SPR_NOACCESS, SPR_NOACCESS,
1624 &spr_read_generic, &spr_write_booke_pid,
1625 0x00000000);
1626 }
1627 /* XXX : not implemented */
1628 spr_register(env, SPR_MMUCFG, "MMUCFG",
1629 SPR_NOACCESS, SPR_NOACCESS,
1630 &spr_read_generic, SPR_NOACCESS,
1631 0x00000000); /* TOFIX */
1632 switch (env->nb_ways) {
1633 case 4:
1634 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_generic, SPR_NOACCESS,
1637 tlbncfg[3]);
1638 /* Fallthru */
1639 case 3:
1640 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1641 SPR_NOACCESS, SPR_NOACCESS,
1642 &spr_read_generic, SPR_NOACCESS,
1643 tlbncfg[2]);
1644 /* Fallthru */
1645 case 2:
1646 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1647 SPR_NOACCESS, SPR_NOACCESS,
1648 &spr_read_generic, SPR_NOACCESS,
1649 tlbncfg[1]);
1650 /* Fallthru */
1651 case 1:
1652 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1653 SPR_NOACCESS, SPR_NOACCESS,
1654 &spr_read_generic, SPR_NOACCESS,
1655 tlbncfg[0]);
1656 /* Fallthru */
1657 case 0:
1658 default:
1659 break;
1660 }
1661 #endif
1662
1663 gen_spr_usprgh(env);
1664 }
1665
1666 /* SPR specific to PowerPC 440 implementation */
1667 static void gen_spr_440 (CPUPPCState *env)
1668 {
1669 /* Cache control */
1670 /* XXX : not implemented */
1671 spr_register(env, SPR_440_DNV0, "DNV0",
1672 SPR_NOACCESS, SPR_NOACCESS,
1673 &spr_read_generic, &spr_write_generic,
1674 0x00000000);
1675 /* XXX : not implemented */
1676 spr_register(env, SPR_440_DNV1, "DNV1",
1677 SPR_NOACCESS, SPR_NOACCESS,
1678 &spr_read_generic, &spr_write_generic,
1679 0x00000000);
1680 /* XXX : not implemented */
1681 spr_register(env, SPR_440_DNV2, "DNV2",
1682 SPR_NOACCESS, SPR_NOACCESS,
1683 &spr_read_generic, &spr_write_generic,
1684 0x00000000);
1685 /* XXX : not implemented */
1686 spr_register(env, SPR_440_DNV3, "DNV3",
1687 SPR_NOACCESS, SPR_NOACCESS,
1688 &spr_read_generic, &spr_write_generic,
1689 0x00000000);
1690 /* XXX : not implemented */
1691 spr_register(env, SPR_440_DTV0, "DTV0",
1692 SPR_NOACCESS, SPR_NOACCESS,
1693 &spr_read_generic, &spr_write_generic,
1694 0x00000000);
1695 /* XXX : not implemented */
1696 spr_register(env, SPR_440_DTV1, "DTV1",
1697 SPR_NOACCESS, SPR_NOACCESS,
1698 &spr_read_generic, &spr_write_generic,
1699 0x00000000);
1700 /* XXX : not implemented */
1701 spr_register(env, SPR_440_DTV2, "DTV2",
1702 SPR_NOACCESS, SPR_NOACCESS,
1703 &spr_read_generic, &spr_write_generic,
1704 0x00000000);
1705 /* XXX : not implemented */
1706 spr_register(env, SPR_440_DTV3, "DTV3",
1707 SPR_NOACCESS, SPR_NOACCESS,
1708 &spr_read_generic, &spr_write_generic,
1709 0x00000000);
1710 /* XXX : not implemented */
1711 spr_register(env, SPR_440_DVLIM, "DVLIM",
1712 SPR_NOACCESS, SPR_NOACCESS,
1713 &spr_read_generic, &spr_write_generic,
1714 0x00000000);
1715 /* XXX : not implemented */
1716 spr_register(env, SPR_440_INV0, "INV0",
1717 SPR_NOACCESS, SPR_NOACCESS,
1718 &spr_read_generic, &spr_write_generic,
1719 0x00000000);
1720 /* XXX : not implemented */
1721 spr_register(env, SPR_440_INV1, "INV1",
1722 SPR_NOACCESS, SPR_NOACCESS,
1723 &spr_read_generic, &spr_write_generic,
1724 0x00000000);
1725 /* XXX : not implemented */
1726 spr_register(env, SPR_440_INV2, "INV2",
1727 SPR_NOACCESS, SPR_NOACCESS,
1728 &spr_read_generic, &spr_write_generic,
1729 0x00000000);
1730 /* XXX : not implemented */
1731 spr_register(env, SPR_440_INV3, "INV3",
1732 SPR_NOACCESS, SPR_NOACCESS,
1733 &spr_read_generic, &spr_write_generic,
1734 0x00000000);
1735 /* XXX : not implemented */
1736 spr_register(env, SPR_440_ITV0, "ITV0",
1737 SPR_NOACCESS, SPR_NOACCESS,
1738 &spr_read_generic, &spr_write_generic,
1739 0x00000000);
1740 /* XXX : not implemented */
1741 spr_register(env, SPR_440_ITV1, "ITV1",
1742 SPR_NOACCESS, SPR_NOACCESS,
1743 &spr_read_generic, &spr_write_generic,
1744 0x00000000);
1745 /* XXX : not implemented */
1746 spr_register(env, SPR_440_ITV2, "ITV2",
1747 SPR_NOACCESS, SPR_NOACCESS,
1748 &spr_read_generic, &spr_write_generic,
1749 0x00000000);
1750 /* XXX : not implemented */
1751 spr_register(env, SPR_440_ITV3, "ITV3",
1752 SPR_NOACCESS, SPR_NOACCESS,
1753 &spr_read_generic, &spr_write_generic,
1754 0x00000000);
1755 /* XXX : not implemented */
1756 spr_register(env, SPR_440_IVLIM, "IVLIM",
1757 SPR_NOACCESS, SPR_NOACCESS,
1758 &spr_read_generic, &spr_write_generic,
1759 0x00000000);
1760 /* Cache debug */
1761 /* XXX : not implemented */
1762 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1763 SPR_NOACCESS, SPR_NOACCESS,
1764 &spr_read_generic, SPR_NOACCESS,
1765 0x00000000);
1766 /* XXX : not implemented */
1767 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1768 SPR_NOACCESS, SPR_NOACCESS,
1769 &spr_read_generic, SPR_NOACCESS,
1770 0x00000000);
1771 /* XXX : not implemented */
1772 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1773 SPR_NOACCESS, SPR_NOACCESS,
1774 &spr_read_generic, SPR_NOACCESS,
1775 0x00000000);
1776 /* XXX : not implemented */
1777 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1778 SPR_NOACCESS, SPR_NOACCESS,
1779 &spr_read_generic, SPR_NOACCESS,
1780 0x00000000);
1781 /* XXX : not implemented */
1782 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1783 SPR_NOACCESS, SPR_NOACCESS,
1784 &spr_read_generic, SPR_NOACCESS,
1785 0x00000000);
1786 /* XXX : not implemented */
1787 spr_register(env, SPR_440_DBDR, "DBDR",
1788 SPR_NOACCESS, SPR_NOACCESS,
1789 &spr_read_generic, &spr_write_generic,
1790 0x00000000);
1791 /* Processor control */
1792 spr_register(env, SPR_4xx_CCR0, "CCR0",
1793 SPR_NOACCESS, SPR_NOACCESS,
1794 &spr_read_generic, &spr_write_generic,
1795 0x00000000);
1796 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1797 SPR_NOACCESS, SPR_NOACCESS,
1798 &spr_read_generic, SPR_NOACCESS,
1799 0x00000000);
1800 /* Storage control */
1801 spr_register(env, SPR_440_MMUCR, "MMUCR",
1802 SPR_NOACCESS, SPR_NOACCESS,
1803 &spr_read_generic, &spr_write_generic,
1804 0x00000000);
1805 }
1806
1807 /* SPR shared between PowerPC 40x implementations */
1808 static void gen_spr_40x (CPUPPCState *env)
1809 {
1810 /* Cache */
1811 /* not emulated, as Qemu do not emulate caches */
1812 spr_register(env, SPR_40x_DCCR, "DCCR",
1813 SPR_NOACCESS, SPR_NOACCESS,
1814 &spr_read_generic, &spr_write_generic,
1815 0x00000000);
1816 /* not emulated, as Qemu do not emulate caches */
1817 spr_register(env, SPR_40x_ICCR, "ICCR",
1818 SPR_NOACCESS, SPR_NOACCESS,
1819 &spr_read_generic, &spr_write_generic,
1820 0x00000000);
1821 /* not emulated, as Qemu do not emulate caches */
1822 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1823 SPR_NOACCESS, SPR_NOACCESS,
1824 &spr_read_generic, SPR_NOACCESS,
1825 0x00000000);
1826 /* Exception */
1827 spr_register(env, SPR_40x_DEAR, "DEAR",
1828 SPR_NOACCESS, SPR_NOACCESS,
1829 &spr_read_generic, &spr_write_generic,
1830 0x00000000);
1831 spr_register(env, SPR_40x_ESR, "ESR",
1832 SPR_NOACCESS, SPR_NOACCESS,
1833 &spr_read_generic, &spr_write_generic,
1834 0x00000000);
1835 spr_register(env, SPR_40x_EVPR, "EVPR",
1836 SPR_NOACCESS, SPR_NOACCESS,
1837 &spr_read_generic, &spr_write_excp_prefix,
1838 0x00000000);
1839 spr_register(env, SPR_40x_SRR2, "SRR2",
1840 &spr_read_generic, &spr_write_generic,
1841 &spr_read_generic, &spr_write_generic,
1842 0x00000000);
1843 spr_register(env, SPR_40x_SRR3, "SRR3",
1844 &spr_read_generic, &spr_write_generic,
1845 &spr_read_generic, &spr_write_generic,
1846 0x00000000);
1847 /* Timers */
1848 spr_register(env, SPR_40x_PIT, "PIT",
1849 SPR_NOACCESS, SPR_NOACCESS,
1850 &spr_read_40x_pit, &spr_write_40x_pit,
1851 0x00000000);
1852 spr_register(env, SPR_40x_TCR, "TCR",
1853 SPR_NOACCESS, SPR_NOACCESS,
1854 &spr_read_generic, &spr_write_booke_tcr,
1855 0x00000000);
1856 spr_register(env, SPR_40x_TSR, "TSR",
1857 SPR_NOACCESS, SPR_NOACCESS,
1858 &spr_read_generic, &spr_write_booke_tsr,
1859 0x00000000);
1860 }
1861
1862 /* SPR specific to PowerPC 405 implementation */
1863 static void gen_spr_405 (CPUPPCState *env)
1864 {
1865 /* MMU */
1866 spr_register(env, SPR_40x_PID, "PID",
1867 SPR_NOACCESS, SPR_NOACCESS,
1868 &spr_read_generic, &spr_write_generic,
1869 0x00000000);
1870 spr_register(env, SPR_4xx_CCR0, "CCR0",
1871 SPR_NOACCESS, SPR_NOACCESS,
1872 &spr_read_generic, &spr_write_generic,
1873 0x00700000);
1874 /* Debug interface */
1875 /* XXX : not implemented */
1876 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1877 SPR_NOACCESS, SPR_NOACCESS,
1878 &spr_read_generic, &spr_write_40x_dbcr0,
1879 0x00000000);
1880 /* XXX : not implemented */
1881 spr_register(env, SPR_405_DBCR1, "DBCR1",
1882 SPR_NOACCESS, SPR_NOACCESS,
1883 &spr_read_generic, &spr_write_generic,
1884 0x00000000);
1885 /* XXX : not implemented */
1886 spr_register(env, SPR_40x_DBSR, "DBSR",
1887 SPR_NOACCESS, SPR_NOACCESS,
1888 &spr_read_generic, &spr_write_clear,
1889 /* Last reset was system reset */
1890 0x00000300);
1891 /* XXX : not implemented */
1892 spr_register(env, SPR_40x_DAC1, "DAC1",
1893 SPR_NOACCESS, SPR_NOACCESS,
1894 &spr_read_generic, &spr_write_generic,
1895 0x00000000);
1896 spr_register(env, SPR_40x_DAC2, "DAC2",
1897 SPR_NOACCESS, SPR_NOACCESS,
1898 &spr_read_generic, &spr_write_generic,
1899 0x00000000);
1900 /* XXX : not implemented */
1901 spr_register(env, SPR_405_DVC1, "DVC1",
1902 SPR_NOACCESS, SPR_NOACCESS,
1903 &spr_read_generic, &spr_write_generic,
1904 0x00000000);
1905 /* XXX : not implemented */
1906 spr_register(env, SPR_405_DVC2, "DVC2",
1907 SPR_NOACCESS, SPR_NOACCESS,
1908 &spr_read_generic, &spr_write_generic,
1909 0x00000000);
1910 /* XXX : not implemented */
1911 spr_register(env, SPR_40x_IAC1, "IAC1",
1912 SPR_NOACCESS, SPR_NOACCESS,
1913 &spr_read_generic, &spr_write_generic,
1914 0x00000000);
1915 spr_register(env, SPR_40x_IAC2, "IAC2",
1916 SPR_NOACCESS, SPR_NOACCESS,
1917 &spr_read_generic, &spr_write_generic,
1918 0x00000000);
1919 /* XXX : not implemented */
1920 spr_register(env, SPR_405_IAC3, "IAC3",
1921 SPR_NOACCESS, SPR_NOACCESS,
1922 &spr_read_generic, &spr_write_generic,
1923 0x00000000);
1924 /* XXX : not implemented */
1925 spr_register(env, SPR_405_IAC4, "IAC4",
1926 SPR_NOACCESS, SPR_NOACCESS,
1927 &spr_read_generic, &spr_write_generic,
1928 0x00000000);
1929 /* Storage control */
1930 /* XXX: TODO: not implemented */
1931 spr_register(env, SPR_405_SLER, "SLER",
1932 SPR_NOACCESS, SPR_NOACCESS,
1933 &spr_read_generic, &spr_write_40x_sler,
1934 0x00000000);
1935 spr_register(env, SPR_40x_ZPR, "ZPR",
1936 SPR_NOACCESS, SPR_NOACCESS,
1937 &spr_read_generic, &spr_write_generic,
1938 0x00000000);
1939 /* XXX : not implemented */
1940 spr_register(env, SPR_405_SU0R, "SU0R",
1941 SPR_NOACCESS, SPR_NOACCESS,
1942 &spr_read_generic, &spr_write_generic,
1943 0x00000000);
1944 /* SPRG */
1945 spr_register(env, SPR_USPRG0, "USPRG0",
1946 &spr_read_ureg, SPR_NOACCESS,
1947 &spr_read_ureg, SPR_NOACCESS,
1948 0x00000000);
1949 spr_register(env, SPR_SPRG4, "SPRG4",
1950 SPR_NOACCESS, SPR_NOACCESS,
1951 &spr_read_generic, &spr_write_generic,
1952 0x00000000);
1953 spr_register(env, SPR_SPRG5, "SPRG5",
1954 SPR_NOACCESS, SPR_NOACCESS,
1955 spr_read_generic, &spr_write_generic,
1956 0x00000000);
1957 spr_register(env, SPR_SPRG6, "SPRG6",
1958 SPR_NOACCESS, SPR_NOACCESS,
1959 spr_read_generic, &spr_write_generic,
1960 0x00000000);
1961 spr_register(env, SPR_SPRG7, "SPRG7",
1962 SPR_NOACCESS, SPR_NOACCESS,
1963 spr_read_generic, &spr_write_generic,
1964 0x00000000);
1965 gen_spr_usprgh(env);
1966 }
1967
1968 /* SPR shared between PowerPC 401 & 403 implementations */
1969 static void gen_spr_401_403 (CPUPPCState *env)
1970 {
1971 /* Time base */
1972 spr_register(env, SPR_403_VTBL, "TBL",
1973 &spr_read_tbl, SPR_NOACCESS,
1974 &spr_read_tbl, SPR_NOACCESS,
1975 0x00000000);
1976 spr_register(env, SPR_403_TBL, "TBL",
1977 SPR_NOACCESS, SPR_NOACCESS,
1978 SPR_NOACCESS, &spr_write_tbl,
1979 0x00000000);
1980 spr_register(env, SPR_403_VTBU, "TBU",
1981 &spr_read_tbu, SPR_NOACCESS,
1982 &spr_read_tbu, SPR_NOACCESS,
1983 0x00000000);
1984 spr_register(env, SPR_403_TBU, "TBU",
1985 SPR_NOACCESS, SPR_NOACCESS,
1986 SPR_NOACCESS, &spr_write_tbu,
1987 0x00000000);
1988 /* Debug */
1989 /* not emulated, as Qemu do not emulate caches */
1990 spr_register(env, SPR_403_CDBCR, "CDBCR",
1991 SPR_NOACCESS, SPR_NOACCESS,
1992 &spr_read_generic, &spr_write_generic,
1993 0x00000000);
1994 }
1995
1996 /* SPR specific to PowerPC 401 implementation */
1997 static void gen_spr_401 (CPUPPCState *env)
1998 {
1999 /* Debug interface */
2000 /* XXX : not implemented */
2001 spr_register(env, SPR_40x_DBCR0, "DBCR",
2002 SPR_NOACCESS, SPR_NOACCESS,
2003 &spr_read_generic, &spr_write_40x_dbcr0,
2004 0x00000000);
2005 /* XXX : not implemented */
2006 spr_register(env, SPR_40x_DBSR, "DBSR",
2007 SPR_NOACCESS, SPR_NOACCESS,
2008 &spr_read_generic, &spr_write_clear,
2009 /* Last reset was system reset */
2010 0x00000300);
2011 /* XXX : not implemented */
2012 spr_register(env, SPR_40x_DAC1, "DAC",
2013 SPR_NOACCESS, SPR_NOACCESS,
2014 &spr_read_generic, &spr_write_generic,
2015 0x00000000);
2016 /* XXX : not implemented */
2017 spr_register(env, SPR_40x_IAC1, "IAC",
2018 SPR_NOACCESS, SPR_NOACCESS,
2019 &spr_read_generic, &spr_write_generic,
2020 0x00000000);
2021 /* Storage control */
2022 /* XXX: TODO: not implemented */
2023 spr_register(env, SPR_405_SLER, "SLER",
2024 SPR_NOACCESS, SPR_NOACCESS,
2025 &spr_read_generic, &spr_write_40x_sler,
2026 0x00000000);
2027 /* not emulated, as Qemu never does speculative access */
2028 spr_register(env, SPR_40x_SGR, "SGR",
2029 SPR_NOACCESS, SPR_NOACCESS,
2030 &spr_read_generic, &spr_write_generic,
2031 0xFFFFFFFF);
2032 /* not emulated, as Qemu do not emulate caches */
2033 spr_register(env, SPR_40x_DCWR, "DCWR",
2034 SPR_NOACCESS, SPR_NOACCESS,
2035 &spr_read_generic, &spr_write_generic,
2036 0x00000000);
2037 }
2038
2039 static void gen_spr_401x2 (CPUPPCState *env)
2040 {
2041 gen_spr_401(env);
2042 spr_register(env, SPR_40x_PID, "PID",
2043 SPR_NOACCESS, SPR_NOACCESS,
2044 &spr_read_generic, &spr_write_generic,
2045 0x00000000);
2046 spr_register(env, SPR_40x_ZPR, "ZPR",
2047 SPR_NOACCESS, SPR_NOACCESS,
2048 &spr_read_generic, &spr_write_generic,
2049 0x00000000);
2050 }
2051
2052 /* SPR specific to PowerPC 403 implementation */
2053 static void gen_spr_403 (CPUPPCState *env)
2054 {
2055 /* Debug interface */
2056 /* XXX : not implemented */
2057 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2058 SPR_NOACCESS, SPR_NOACCESS,
2059 &spr_read_generic, &spr_write_40x_dbcr0,
2060 0x00000000);
2061 /* XXX : not implemented */
2062 spr_register(env, SPR_40x_DBSR, "DBSR",
2063 SPR_NOACCESS, SPR_NOACCESS,
2064 &spr_read_generic, &spr_write_clear,
2065 /* Last reset was system reset */
2066 0x00000300);
2067 /* XXX : not implemented */
2068 spr_register(env, SPR_40x_DAC1, "DAC1",
2069 SPR_NOACCESS, SPR_NOACCESS,
2070 &spr_read_generic, &spr_write_generic,
2071 0x00000000);
2072 /* XXX : not implemented */
2073 spr_register(env, SPR_40x_DAC2, "DAC2",
2074 SPR_NOACCESS, SPR_NOACCESS,
2075 &spr_read_generic, &spr_write_generic,
2076 0x00000000);
2077 /* XXX : not implemented */
2078 spr_register(env, SPR_40x_IAC1, "IAC1",
2079 SPR_NOACCESS, SPR_NOACCESS,
2080 &spr_read_generic, &spr_write_generic,
2081 0x00000000);
2082 /* XXX : not implemented */
2083 spr_register(env, SPR_40x_IAC2, "IAC2",
2084 SPR_NOACCESS, SPR_NOACCESS,
2085 &spr_read_generic, &spr_write_generic,
2086 0x00000000);
2087 }
2088
2089 static void gen_spr_403_real (CPUPPCState *env)
2090 {
2091 spr_register(env, SPR_403_PBL1, "PBL1",
2092 SPR_NOACCESS, SPR_NOACCESS,
2093 &spr_read_403_pbr, &spr_write_403_pbr,
2094 0x00000000);
2095 spr_register(env, SPR_403_PBU1, "PBU1",
2096 SPR_NOACCESS, SPR_NOACCESS,
2097 &spr_read_403_pbr, &spr_write_403_pbr,
2098 0x00000000);
2099 spr_register(env, SPR_403_PBL2, "PBL2",
2100 SPR_NOACCESS, SPR_NOACCESS,
2101 &spr_read_403_pbr, &spr_write_403_pbr,
2102 0x00000000);
2103 spr_register(env, SPR_403_PBU2, "PBU2",
2104 SPR_NOACCESS, SPR_NOACCESS,
2105 &spr_read_403_pbr, &spr_write_403_pbr,
2106 0x00000000);
2107 }
2108
2109 static void gen_spr_403_mmu (CPUPPCState *env)
2110 {
2111 /* MMU */
2112 spr_register(env, SPR_40x_PID, "PID",
2113 SPR_NOACCESS, SPR_NOACCESS,
2114 &spr_read_generic, &spr_write_generic,
2115 0x00000000);
2116 spr_register(env, SPR_40x_ZPR, "ZPR",
2117 SPR_NOACCESS, SPR_NOACCESS,
2118 &spr_read_generic, &spr_write_generic,
2119 0x00000000);
2120 }
2121
2122 /* SPR specific to PowerPC compression coprocessor extension */
2123 static void gen_spr_compress (CPUPPCState *env)
2124 {
2125 /* XXX : not implemented */
2126 spr_register(env, SPR_401_SKR, "SKR",
2127 SPR_NOACCESS, SPR_NOACCESS,
2128 &spr_read_generic, &spr_write_generic,
2129 0x00000000);
2130 }
2131
2132 #if defined (TARGET_PPC64)
2133 /* SPR specific to PowerPC 620 */
2134 static void gen_spr_620 (CPUPPCState *env)
2135 {
2136 /* Processor identification */
2137 spr_register(env, SPR_PIR, "PIR",
2138 SPR_NOACCESS, SPR_NOACCESS,
2139 &spr_read_generic, &spr_write_pir,
2140 0x00000000);
2141 spr_register(env, SPR_ASR, "ASR",
2142 SPR_NOACCESS, SPR_NOACCESS,
2143 &spr_read_asr, &spr_write_asr,
2144 0x00000000);
2145 /* Breakpoints */
2146 /* XXX : not implemented */
2147 spr_register(env, SPR_IABR, "IABR",
2148 SPR_NOACCESS, SPR_NOACCESS,
2149 &spr_read_generic, &spr_write_generic,
2150 0x00000000);
2151 /* XXX : not implemented */
2152 spr_register(env, SPR_DABR, "DABR",
2153 SPR_NOACCESS, SPR_NOACCESS,
2154 &spr_read_generic, &spr_write_generic,
2155 0x00000000);
2156 /* XXX : not implemented */
2157 spr_register(env, SPR_SIAR, "SIAR",
2158 SPR_NOACCESS, SPR_NOACCESS,
2159 &spr_read_generic, SPR_NOACCESS,
2160 0x00000000);
2161 /* XXX : not implemented */
2162 spr_register(env, SPR_SDA, "SDA",
2163 SPR_NOACCESS, SPR_NOACCESS,
2164 &spr_read_generic, SPR_NOACCESS,
2165 0x00000000);
2166 /* XXX : not implemented */
2167 spr_register(env, SPR_620_PMC1R, "PMC1",
2168 SPR_NOACCESS, SPR_NOACCESS,
2169 &spr_read_generic, SPR_NOACCESS,
2170 0x00000000);
2171 spr_register(env, SPR_620_PMC1W, "PMC1",
2172 SPR_NOACCESS, SPR_NOACCESS,
2173 SPR_NOACCESS, &spr_write_generic,
2174 0x00000000);
2175 /* XXX : not implemented */
2176 spr_register(env, SPR_620_PMC2R, "PMC2",
2177 SPR_NOACCESS, SPR_NOACCESS,
2178 &spr_read_generic, SPR_NOACCESS,
2179 0x00000000);
2180 spr_register(env, SPR_620_PMC2W, "PMC2",
2181 SPR_NOACCESS, SPR_NOACCESS,
2182 SPR_NOACCESS, &spr_write_generic,
2183 0x00000000);
2184 /* XXX : not implemented */
2185 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2186 SPR_NOACCESS, SPR_NOACCESS,
2187 &spr_read_generic, SPR_NOACCESS,
2188 0x00000000);
2189 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 SPR_NOACCESS, &spr_write_generic,
2192 0x00000000);
2193 /* External access control */
2194 /* XXX : not implemented */
2195 spr_register(env, SPR_EAR, "EAR",
2196 SPR_NOACCESS, SPR_NOACCESS,
2197 &spr_read_generic, &spr_write_generic,
2198 0x00000000);
2199 #if 0 // XXX: check this
2200 /* XXX : not implemented */
2201 spr_register(env, SPR_620_PMR0, "PMR0",
2202 SPR_NOACCESS, SPR_NOACCESS,
2203 &spr_read_generic, &spr_write_generic,
2204 0x00000000);
2205 /* XXX : not implemented */
2206 spr_register(env, SPR_620_PMR1, "PMR1",
2207 SPR_NOACCESS, SPR_NOACCESS,
2208 &spr_read_generic, &spr_write_generic,
2209 0x00000000);
2210 /* XXX : not implemented */
2211 spr_register(env, SPR_620_PMR2, "PMR2",
2212 SPR_NOACCESS, SPR_NOACCESS,
2213 &spr_read_generic, &spr_write_generic,
2214 0x00000000);
2215 /* XXX : not implemented */
2216 spr_register(env, SPR_620_PMR3, "PMR3",
2217 SPR_NOACCESS, SPR_NOACCESS,
2218 &spr_read_generic, &spr_write_generic,
2219 0x00000000);
2220 /* XXX : not implemented */
2221 spr_register(env, SPR_620_PMR4, "PMR4",
2222 SPR_NOACCESS, SPR_NOACCESS,
2223 &spr_read_generic, &spr_write_generic,
2224 0x00000000);
2225 /* XXX : not implemented */
2226 spr_register(env, SPR_620_PMR5, "PMR5",
2227 SPR_NOACCESS, SPR_NOACCESS,
2228 &spr_read_generic, &spr_write_generic,
2229 0x00000000);
2230 /* XXX : not implemented */
2231 spr_register(env, SPR_620_PMR6, "PMR6",
2232 SPR_NOACCESS, SPR_NOACCESS,
2233 &spr_read_generic, &spr_write_generic,
2234 0x00000000);
2235 /* XXX : not implemented */
2236 spr_register(env, SPR_620_PMR7, "PMR7",
2237 SPR_NOACCESS, SPR_NOACCESS,
2238 &spr_read_generic, &spr_write_generic,
2239 0x00000000);
2240 /* XXX : not implemented */
2241 spr_register(env, SPR_620_PMR8, "PMR8",
2242 SPR_NOACCESS, SPR_NOACCESS,
2243 &spr_read_generic, &spr_write_generic,
2244 0x00000000);
2245 /* XXX : not implemented */
2246 spr_register(env, SPR_620_PMR9, "PMR9",
2247 SPR_NOACCESS, SPR_NOACCESS,
2248 &spr_read_generic, &spr_write_generic,
2249 0x00000000);
2250 /* XXX : not implemented */
2251 spr_register(env, SPR_620_PMRA, "PMR10",
2252 SPR_NOACCESS, SPR_NOACCESS,
2253 &spr_read_generic, &spr_write_generic,
2254 0x00000000);
2255 /* XXX : not implemented */
2256 spr_register(env, SPR_620_PMRB, "PMR11",
2257 SPR_NOACCESS, SPR_NOACCESS,
2258 &spr_read_generic, &spr_write_generic,
2259 0x00000000);
2260 /* XXX : not implemented */
2261 spr_register(env, SPR_620_PMRC, "PMR12",
2262 SPR_NOACCESS, SPR_NOACCESS,
2263 &spr_read_generic, &spr_write_generic,
2264 0x00000000);
2265 /* XXX : not implemented */
2266 spr_register(env, SPR_620_PMRD, "PMR13",
2267 SPR_NOACCESS, SPR_NOACCESS,
2268 &spr_read_generic, &spr_write_generic,
2269 0x00000000);
2270 /* XXX : not implemented */
2271 spr_register(env, SPR_620_PMRE, "PMR14",
2272 SPR_NOACCESS, SPR_NOACCESS,
2273 &spr_read_generic, &spr_write_generic,
2274 0x00000000);
2275 /* XXX : not implemented */
2276 spr_register(env, SPR_620_PMRF, "PMR15",
2277 SPR_NOACCESS, SPR_NOACCESS,
2278 &spr_read_generic, &spr_write_generic,
2279 0x00000000);
2280 #endif
2281 /* XXX : not implemented */
2282 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2283 SPR_NOACCESS, SPR_NOACCESS,
2284 &spr_read_generic, &spr_write_generic,
2285 0x00000000);
2286 /* XXX : not implemented */
2287 spr_register(env, SPR_620_L2CR, "L2CR",
2288 SPR_NOACCESS, SPR_NOACCESS,
2289 &spr_read_generic, &spr_write_generic,
2290 0x00000000);
2291 /* XXX : not implemented */
2292 spr_register(env, SPR_620_L2SR, "L2SR",
2293 SPR_NOACCESS, SPR_NOACCESS,
2294 &spr_read_generic, &spr_write_generic,
2295 0x00000000);
2296 }
2297 #endif /* defined (TARGET_PPC64) */
2298
2299 static void gen_spr_5xx_8xx (CPUPPCState *env)
2300 {
2301 /* Exception processing */
2302 spr_register(env, SPR_DSISR, "DSISR",
2303 SPR_NOACCESS, SPR_NOACCESS,
2304 &spr_read_generic, &spr_write_generic,
2305 0x00000000);
2306 spr_register(env, SPR_DAR, "DAR",
2307 SPR_NOACCESS, SPR_NOACCESS,
2308 &spr_read_generic, &spr_write_generic,
2309 0x00000000);
2310 /* Timer */
2311 spr_register(env, SPR_DECR, "DECR",
2312 SPR_NOACCESS, SPR_NOACCESS,
2313 &spr_read_decr, &spr_write_decr,
2314 0x00000000);
2315 /* XXX : not implemented */
2316 spr_register(env, SPR_MPC_EIE, "EIE",
2317 SPR_NOACCESS, SPR_NOACCESS,
2318 &spr_read_generic, &spr_write_generic,
2319 0x00000000);
2320 /* XXX : not implemented */
2321 spr_register(env, SPR_MPC_EID, "EID",
2322 SPR_NOACCESS, SPR_NOACCESS,
2323 &spr_read_generic, &spr_write_generic,
2324 0x00000000);
2325 /* XXX : not implemented */
2326 spr_register(env, SPR_MPC_NRI, "NRI",
2327 SPR_NOACCESS, SPR_NOACCESS,
2328 &spr_read_generic, &spr_write_generic,
2329 0x00000000);
2330 /* XXX : not implemented */
2331 spr_register(env, SPR_MPC_CMPA, "CMPA",
2332 SPR_NOACCESS, SPR_NOACCESS,
2333 &spr_read_generic, &spr_write_generic,
2334 0x00000000);
2335 /* XXX : not implemented */
2336 spr_register(env, SPR_MPC_CMPB, "CMPB",
2337 SPR_NOACCESS, SPR_NOACCESS,
2338 &spr_read_generic, &spr_write_generic,
2339 0x00000000);
2340 /* XXX : not implemented */
2341 spr_register(env, SPR_MPC_CMPC, "CMPC",
2342 SPR_NOACCESS, SPR_NOACCESS,
2343 &spr_read_generic, &spr_write_generic,
2344 0x00000000);
2345 /* XXX : not implemented */
2346 spr_register(env, SPR_MPC_CMPD, "CMPD",
2347 SPR_NOACCESS, SPR_NOACCESS,
2348 &spr_read_generic, &spr_write_generic,
2349 0x00000000);
2350 /* XXX : not implemented */
2351 spr_register(env, SPR_MPC_ECR, "ECR",
2352 SPR_NOACCESS, SPR_NOACCESS,
2353 &spr_read_generic, &spr_write_generic,
2354 0x00000000);
2355 /* XXX : not implemented */
2356 spr_register(env, SPR_MPC_DER, "DER",
2357 SPR_NOACCESS, SPR_NOACCESS,
2358 &spr_read_generic, &spr_write_generic,
2359 0x00000000);
2360 /* XXX : not implemented */
2361 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2362 SPR_NOACCESS, SPR_NOACCESS,
2363 &spr_read_generic, &spr_write_generic,
2364 0x00000000);
2365 /* XXX : not implemented */
2366 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2367 SPR_NOACCESS, SPR_NOACCESS,
2368 &spr_read_generic, &spr_write_generic,
2369 0x00000000);
2370 /* XXX : not implemented */
2371 spr_register(env, SPR_MPC_CMPE, "CMPE",
2372 SPR_NOACCESS, SPR_NOACCESS,
2373 &spr_read_generic, &spr_write_generic,
2374 0x00000000);
2375 /* XXX : not implemented */
2376 spr_register(env, SPR_MPC_CMPF, "CMPF",
2377 SPR_NOACCESS, SPR_NOACCESS,
2378 &spr_read_generic, &spr_write_generic,
2379 0x00000000);
2380 /* XXX : not implemented */
2381 spr_register(env, SPR_MPC_CMPG, "CMPG",
2382 SPR_NOACCESS, SPR_NOACCESS,
2383 &spr_read_generic, &spr_write_generic,
2384 0x00000000);
2385 /* XXX : not implemented */
2386 spr_register(env, SPR_MPC_CMPH, "CMPH",
2387 SPR_NOACCESS, SPR_NOACCESS,
2388 &spr_read_generic, &spr_write_generic,
2389 0x00000000);
2390 /* XXX : not implemented */
2391 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2392 SPR_NOACCESS, SPR_NOACCESS,
2393 &spr_read_generic, &spr_write_generic,
2394 0x00000000);
2395 /* XXX : not implemented */
2396 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2397 SPR_NOACCESS, SPR_NOACCESS,
2398 &spr_read_generic, &spr_write_generic,
2399 0x00000000);
2400 /* XXX : not implemented */
2401 spr_register(env, SPR_MPC_BAR, "BAR",
2402 SPR_NOACCESS, SPR_NOACCESS,
2403 &spr_read_generic, &spr_write_generic,
2404 0x00000000);
2405 /* XXX : not implemented */
2406 spr_register(env, SPR_MPC_DPDR, "DPDR",
2407 SPR_NOACCESS, SPR_NOACCESS,
2408 &spr_read_generic, &spr_write_generic,
2409 0x00000000);
2410 /* XXX : not implemented */
2411 spr_register(env, SPR_MPC_IMMR, "IMMR",
2412 SPR_NOACCESS, SPR_NOACCESS,
2413 &spr_read_generic, &spr_write_generic,
2414 0x00000000);
2415 }
2416
2417 static void gen_spr_5xx (CPUPPCState *env)
2418 {
2419 /* XXX : not implemented */
2420 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2421 SPR_NOACCESS, SPR_NOACCESS,
2422 &spr_read_generic, &spr_write_generic,
2423 0x00000000);
2424 /* XXX : not implemented */
2425 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2426 SPR_NOACCESS, SPR_NOACCESS,
2427 &spr_read_generic, &spr_write_generic,
2428 0x00000000);
2429 /* XXX : not implemented */
2430 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2431 SPR_NOACCESS, SPR_NOACCESS,
2432 &spr_read_generic, &spr_write_generic,
2433 0x00000000);
2434 /* XXX : not implemented */
2435 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2436 SPR_NOACCESS, SPR_NOACCESS,
2437 &spr_read_generic, &spr_write_generic,
2438 0x00000000);
2439 /* XXX : not implemented */
2440 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2441 SPR_NOACCESS, SPR_NOACCESS,
2442 &spr_read_generic, &spr_write_generic,
2443 0x00000000);
2444 /* XXX : not implemented */
2445 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2446 SPR_NOACCESS, SPR_NOACCESS,
2447 &spr_read_generic, &spr_write_generic,
2448 0x00000000);
2449 /* XXX : not implemented */
2450 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2451 SPR_NOACCESS, SPR_NOACCESS,
2452 &spr_read_generic, &spr_write_generic,
2453 0x00000000);
2454 /* XXX : not implemented */
2455 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2456 SPR_NOACCESS, SPR_NOACCESS,
2457 &spr_read_generic, &spr_write_generic,
2458 0x00000000);
2459 /* XXX : not implemented */
2460 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2461 SPR_NOACCESS, SPR_NOACCESS,
2462 &spr_read_generic, &spr_write_generic,
2463 0x00000000);
2464 /* XXX : not implemented */
2465 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2466 SPR_NOACCESS, SPR_NOACCESS,
2467 &spr_read_generic, &spr_write_generic,
2468 0x00000000);
2469 /* XXX : not implemented */
2470 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2471 SPR_NOACCESS, SPR_NOACCESS,
2472 &spr_read_generic, &spr_write_generic,
2473 0x00000000);
2474 /* XXX : not implemented */
2475 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2476 SPR_NOACCESS, SPR_NOACCESS,
2477 &spr_read_generic, &spr_write_generic,
2478 0x00000000);
2479 /* XXX : not implemented */
2480 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2481 SPR_NOACCESS, SPR_NOACCESS,
2482 &spr_read_generic, &spr_write_generic,
2483 0x00000000);
2484 /* XXX : not implemented */
2485 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2486 SPR_NOACCESS, SPR_NOACCESS,
2487 &spr_read_generic, &spr_write_generic,
2488 0x00000000);
2489 /* XXX : not implemented */
2490 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2491 SPR_NOACCESS, SPR_NOACCESS,
2492 &spr_read_generic, &spr_write_generic,
2493 0x00000000);
2494 /* XXX : not implemented */
2495 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2496 SPR_NOACCESS, SPR_NOACCESS,
2497 &spr_read_generic, &spr_write_generic,
2498 0x00000000);
2499 /* XXX : not implemented */
2500 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2501 SPR_NOACCESS, SPR_NOACCESS,
2502 &spr_read_generic, &spr_write_generic,
2503 0x00000000);
2504 /* XXX : not implemented */
2505 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2506 SPR_NOACCESS, SPR_NOACCESS,
2507 &spr_read_generic, &spr_write_generic,
2508 0x00000000);
2509 /* XXX : not implemented */
2510 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2511 SPR_NOACCESS, SPR_NOACCESS,
2512 &spr_read_generic, &spr_write_generic,
2513 0x00000000);
2514 /* XXX : not implemented */
2515 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2516 SPR_NOACCESS, SPR_NOACCESS,
2517 &spr_read_generic, &spr_write_generic,
2518 0x00000000);
2519 /* XXX : not implemented */
2520 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2521 SPR_NOACCESS, SPR_NOACCESS,
2522 &spr_read_generic, &spr_write_generic,
2523 0x00000000);
2524 }
2525
2526 static void gen_spr_8xx (CPUPPCState *env)
2527 {
2528 /* XXX : not implemented */
2529 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2530 SPR_NOACCESS, SPR_NOACCESS,
2531 &spr_read_generic, &spr_write_generic,
2532 0x00000000);
2533 /* XXX : not implemented */
2534 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2535 SPR_NOACCESS, SPR_NOACCESS,
2536 &spr_read_generic, &spr_write_generic,
2537 0x00000000);
2538 /* XXX : not implemented */
2539 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2540 SPR_NOACCESS, SPR_NOACCESS,
2541 &spr_read_generic, &spr_write_generic,
2542 0x00000000);
2543 /* XXX : not implemented */
2544 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2545 SPR_NOACCESS, SPR_NOACCESS,
2546 &spr_read_generic, &spr_write_generic,
2547 0x00000000);
2548 /* XXX : not implemented */
2549 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2550 SPR_NOACCESS, SPR_NOACCESS,
2551 &spr_read_generic, &spr_write_generic,
2552 0x00000000);
2553 /* XXX : not implemented */
2554 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2555 SPR_NOACCESS, SPR_NOACCESS,
2556 &spr_read_generic, &spr_write_generic,
2557 0x00000000);
2558 /* XXX : not implemented */
2559 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2560 SPR_NOACCESS, SPR_NOACCESS,
2561 &spr_read_generic, &spr_write_generic,
2562 0x00000000);
2563 /* XXX : not implemented */
2564 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2565 SPR_NOACCESS, SPR_NOACCESS,
2566 &spr_read_generic, &spr_write_generic,
2567 0x00000000);
2568 /* XXX : not implemented */
2569 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2570 SPR_NOACCESS, SPR_NOACCESS,
2571 &spr_read_generic, &spr_write_generic,
2572 0x00000000);
2573 /* XXX : not implemented */
2574 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2575 SPR_NOACCESS, SPR_NOACCESS,
2576 &spr_read_generic, &spr_write_generic,
2577 0x00000000);
2578 /* XXX : not implemented */
2579 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2580 SPR_NOACCESS, SPR_NOACCESS,
2581 &spr_read_generic, &spr_write_generic,
2582 0x00000000);
2583 /* XXX : not implemented */
2584 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2585 SPR_NOACCESS, SPR_NOACCESS,
2586 &spr_read_generic, &spr_write_generic,
2587 0x00000000);
2588 /* XXX : not implemented */
2589 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2590 SPR_NOACCESS, SPR_NOACCESS,
2591 &spr_read_generic, &spr_write_generic,
2592 0x00000000);
2593 /* XXX : not implemented */
2594 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2595 SPR_NOACCESS, SPR_NOACCESS,
2596 &spr_read_generic, &spr_write_generic,
2597 0x00000000);
2598 /* XXX : not implemented */
2599 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2600 SPR_NOACCESS, SPR_NOACCESS,
2601 &spr_read_generic, &spr_write_generic,
2602 0x00000000);
2603 /* XXX : not implemented */
2604 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2605 SPR_NOACCESS, SPR_NOACCESS,
2606 &spr_read_generic, &spr_write_generic,
2607 0x00000000);
2608 /* XXX : not implemented */
2609 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2610 SPR_NOACCESS, SPR_NOACCESS,
2611 &spr_read_generic, &spr_write_generic,
2612 0x00000000);
2613 /* XXX : not implemented */
2614 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2615 SPR_NOACCESS, SPR_NOACCESS,
2616 &spr_read_generic, &spr_write_generic,
2617 0x00000000);
2618 /* XXX : not implemented */
2619 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2620 SPR_NOACCESS, SPR_NOACCESS,
2621 &spr_read_generic, &spr_write_generic,
2622 0x00000000);
2623 /* XXX : not implemented */
2624 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2625 SPR_NOACCESS, SPR_NOACCESS,
2626 &spr_read_generic, &spr_write_generic,
2627 0x00000000);
2628 /* XXX : not implemented */
2629 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2630 SPR_NOACCESS, SPR_NOACCESS,
2631 &spr_read_generic, &spr_write_generic,
2632 0x00000000);
2633 /* XXX : not implemented */
2634 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2635 SPR_NOACCESS, SPR_NOACCESS,
2636 &spr_read_generic, &spr_write_generic,
2637 0x00000000);
2638 /* XXX : not implemented */
2639 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2640 SPR_NOACCESS, SPR_NOACCESS,
2641 &spr_read_generic, &spr_write_generic,
2642 0x00000000);
2643 /* XXX : not implemented */
2644 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2645 SPR_NOACCESS, SPR_NOACCESS,
2646 &spr_read_generic, &spr_write_generic,
2647 0x00000000);
2648 /* XXX : not implemented */
2649 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2650 SPR_NOACCESS, SPR_NOACCESS,
2651 &spr_read_generic, &spr_write_generic,
2652 0x00000000);
2653 }
2654
2655 // XXX: TODO
2656 /*
2657 * AMR => SPR 29 (Power 2.04)
2658 * CTRL => SPR 136 (Power 2.04)
2659 * CTRL => SPR 152 (Power 2.04)
2660 * SCOMC => SPR 276 (64 bits ?)
2661 * SCOMD => SPR 277 (64 bits ?)
2662 * TBU40 => SPR 286 (Power 2.04 hypv)
2663 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2664 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2665 * HDSISR => SPR 306 (Power 2.04 hypv)
2666 * HDAR => SPR 307 (Power 2.04 hypv)
2667 * PURR => SPR 309 (Power 2.04 hypv)
2668 * HDEC => SPR 310 (Power 2.04 hypv)
2669 * HIOR => SPR 311 (hypv)
2670 * RMOR => SPR 312 (970)
2671 * HRMOR => SPR 313 (Power 2.04 hypv)
2672 * HSRR0 => SPR 314 (Power 2.04 hypv)
2673 * HSRR1 => SPR 315 (Power 2.04 hypv)
2674 * LPCR => SPR 316 (970)
2675 * LPIDR => SPR 317 (970)
2676 * EPR => SPR 702 (Power 2.04 emb)
2677 * perf => 768-783 (Power 2.04)
2678 * perf => 784-799 (Power 2.04)
2679 * PPR => SPR 896 (Power 2.04)
2680 * EPLC => SPR 947 (Power 2.04 emb)
2681 * EPSC => SPR 948 (Power 2.04 emb)
2682 * DABRX => 1015 (Power 2.04 hypv)
2683 * FPECR => SPR 1022 (?)
2684 * ... and more (thermal management, performance counters, ...)
2685 */
2686
2687 /*****************************************************************************/
2688 /* Exception vectors models */
2689 static void init_excp_4xx_real (CPUPPCState *env)
2690 {
2691 #if !defined(CONFIG_USER_ONLY)
2692 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2693 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2694 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2695 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2696 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2697 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2698 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2699 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2700 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2701 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2702 env->hreset_excp_prefix = 0x00000000UL;
2703 env->ivor_mask = 0x0000FFF0UL;
2704 env->ivpr_mask = 0xFFFF0000UL;
2705 /* Hardware reset vector */
2706 env->hreset_vector = 0xFFFFFFFCUL;
2707 #endif
2708 }
2709
2710 static void init_excp_4xx_softmmu (CPUPPCState *env)
2711 {
2712 #if !defined(CONFIG_USER_ONLY)
2713 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2714 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2715 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2716 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2717 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2718 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2719 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2720 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2721 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2722 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2723 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2724 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2725 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2726 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2727 env->hreset_excp_prefix = 0x00000000UL;
2728 env->ivor_mask = 0x0000FFF0UL;
2729 env->ivpr_mask = 0xFFFF0000UL;
2730 /* Hardware reset vector */
2731 env->hreset_vector = 0xFFFFFFFCUL;
2732 #endif
2733 }
2734
2735 static void init_excp_MPC5xx (CPUPPCState *env)
2736 {
2737 #if !defined(CONFIG_USER_ONLY)
2738 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2739 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2740 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2741 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2742 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2743 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2744 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2745 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2746 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2747 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2748 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2749 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2750 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2751 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2752 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2753 env->hreset_excp_prefix = 0x00000000UL;
2754 env->ivor_mask = 0x0000FFF0UL;
2755 env->ivpr_mask = 0xFFFF0000UL;
2756 /* Hardware reset vector */
2757 env->hreset_vector = 0xFFFFFFFCUL;
2758 #endif
2759 }
2760
2761 static void init_excp_MPC8xx (CPUPPCState *env)
2762 {
2763 #if !defined(CONFIG_USER_ONLY)
2764 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2765 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2766 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2767 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2768 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2769 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2770 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2771 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2772 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2773 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2774 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2775 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2776 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2777 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2778 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2779 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2780 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2781 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2782 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2783 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2784 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2785 env->hreset_excp_prefix = 0x00000000UL;
2786 env->ivor_mask = 0x0000FFF0UL;
2787 env->ivpr_mask = 0xFFFF0000UL;
2788 /* Hardware reset vector */
2789 env->hreset_vector = 0xFFFFFFFCUL;
2790 #endif
2791 }
2792
2793 static void init_excp_G2 (CPUPPCState *env)
2794 {
2795 #if !defined(CONFIG_USER_ONLY)
2796 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2797 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2798 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2799 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2800 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2801 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2802 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2803 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2804 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2805 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2806 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2807 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2808 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2809 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2810 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2811 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2812 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2813 env->hreset_excp_prefix = 0x00000000UL;
2814 /* Hardware reset vector */
2815 env->hreset_vector = 0xFFFFFFFCUL;
2816 #endif
2817 }
2818
2819 static void init_excp_e200 (CPUPPCState *env)
2820 {
2821 #if !defined(CONFIG_USER_ONLY)
2822 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2823 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2824 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2825 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2826 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2827 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2828 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2829 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2830 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2831 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2832 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2833 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2834 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2835 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2836 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2837 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2838 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2839 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2840 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2841 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2842 env->hreset_excp_prefix = 0x00000000UL;
2843 env->ivor_mask = 0x0000FFF7UL;
2844 env->ivpr_mask = 0xFFFF0000UL;
2845 /* Hardware reset vector */
2846 env->hreset_vector = 0xFFFFFFFCUL;
2847 #endif
2848 }
2849
2850 static void init_excp_BookE (CPUPPCState *env)
2851 {
2852 #if !defined(CONFIG_USER_ONLY)
2853 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2854 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2855 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2856 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2857 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2858 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2859 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2860 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2861 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2862 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2863 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2864 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2865 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2866 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2867 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2868 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2869 env->hreset_excp_prefix = 0x00000000UL;
2870 env->ivor_mask = 0x0000FFE0UL;
2871 env->ivpr_mask = 0xFFFF0000UL;
2872 /* Hardware reset vector */
2873 env->hreset_vector = 0xFFFFFFFCUL;
2874 #endif
2875 }
2876
2877 static void init_excp_601 (CPUPPCState *env)
2878 {
2879 #if !defined(CONFIG_USER_ONLY)
2880 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2881 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2882 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2883 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2884 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2885 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2886 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2887 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2888 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2889 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2890 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2891 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2892 env->hreset_excp_prefix = 0xFFF00000UL;
2893 /* Hardware reset vector */
2894 env->hreset_vector = 0x00000100UL;
2895 #endif
2896 }
2897
2898 static void init_excp_602 (CPUPPCState *env)
2899 {
2900 #if !defined(CONFIG_USER_ONLY)
2901 /* XXX: exception prefix has a special behavior on 602 */
2902 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2903 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2904 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2905 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2906 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2907 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2908 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2909 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2910 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2911 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2912 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2913 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2914 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2915 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2916 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2917 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2918 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2919 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2920 env->hreset_excp_prefix = 0xFFF00000UL;
2921 /* Hardware reset vector */
2922 env->hreset_vector = 0xFFFFFFFCUL;
2923 #endif
2924 }
2925
2926 static void init_excp_603 (CPUPPCState *env)
2927 {
2928 #if !defined(CONFIG_USER_ONLY)
2929 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2930 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2931 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2932 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2933 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2934 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2935 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2936 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2937 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2938 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2939 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2940 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2941 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2942 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2943 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2944 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2945 env->hreset_excp_prefix = 0x00000000UL;
2946 /* Hardware reset vector */
2947 env->hreset_vector = 0xFFFFFFFCUL;
2948 #endif
2949 }
2950
2951 static void init_excp_604 (CPUPPCState *env)
2952 {
2953 #if !defined(CONFIG_USER_ONLY)
2954 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2955 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2956 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2957 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2958 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2959 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2960 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2961 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2962 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2963 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2964 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2965 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2966 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2967 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2968 env->hreset_excp_prefix = 0xFFF00000UL;
2969 /* Hardware reset vector */
2970 env->hreset_vector = 0x00000100UL;
2971 #endif
2972 }
2973
2974 #if defined(TARGET_PPC64)
2975 static void init_excp_620 (CPUPPCState *env)
2976 {
2977 #if !defined(CONFIG_USER_ONLY)
2978 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2979 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2980 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2981 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2982 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2983 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2984 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2985 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2986 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2987 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2988 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2989 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2990 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2991 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2992 env->hreset_excp_prefix = 0xFFF00000UL;
2993 /* Hardware reset vector */
2994 env->hreset_vector = 0x0000000000000100ULL;
2995 #endif
2996 }
2997 #endif /* defined(TARGET_PPC64) */
2998
2999 static void init_excp_7x0 (CPUPPCState *env)
3000 {
3001 #if !defined(CONFIG_USER_ONLY)
3002 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3003 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3004 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3005 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3006 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3007 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3008 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3009 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3010 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3011 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3012 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3013 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3014 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3015 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3016 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3017 env->hreset_excp_prefix = 0x00000000UL;
3018 /* Hardware reset vector */
3019 env->hreset_vector = 0xFFFFFFFCUL;
3020 #endif
3021 }
3022
3023 static void init_excp_750cl (CPUPPCState *env)
3024 {
3025 #if !defined(CONFIG_USER_ONLY)
3026 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3027 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3028 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3029 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3030 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3031 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3032 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3033 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3034 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3035 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3036 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3037 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3038 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3039 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3040 env->hreset_excp_prefix = 0x00000000UL;
3041 /* Hardware reset vector */
3042 env->hreset_vector = 0xFFFFFFFCUL;
3043 #endif
3044 }
3045
3046 static void init_excp_750cx (CPUPPCState *env)
3047 {
3048 #if !defined(CONFIG_USER_ONLY)
3049 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3050 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3051 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3052 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3053 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3054 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3055 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3056 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3057 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3058 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3059 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3060 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3061 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3062 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3063 env->hreset_excp_prefix = 0x00000000UL;
3064 /* Hardware reset vector */
3065 env->hreset_vector = 0xFFFFFFFCUL;
3066 #endif
3067 }
3068
3069 /* XXX: Check if this is correct */
3070 static void init_excp_7x5 (CPUPPCState *env)
3071 {
3072 #if !defined(CONFIG_USER_ONLY)
3073 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3074 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3075 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3076 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3077 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3078 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3079 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3080 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3081 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3082 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3083 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3084 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3085 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3086 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3087 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3088 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3089 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3090 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3091 env->hreset_excp_prefix = 0x00000000UL;
3092 /* Hardware reset vector */
3093 env->hreset_vector = 0xFFFFFFFCUL;
3094 #endif
3095 }
3096
3097 static void init_excp_7400 (CPUPPCState *env)
3098 {
3099 #if !defined(CONFIG_USER_ONLY)
3100 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3101 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3102 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3103 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3104 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3105 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3106 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3107 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3108 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3109 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3110 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3111 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3112 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3113 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3114 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3115 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3116 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3117 env->hreset_excp_prefix = 0x00000000UL;
3118 /* Hardware reset vector */
3119 env->hreset_vector = 0xFFFFFFFCUL;
3120 #endif
3121 }
3122
3123 static void init_excp_7450 (CPUPPCState *env)
3124 {
3125 #if !defined(CONFIG_USER_ONLY)
3126 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3127 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3128 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3129 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3130 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3131 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3132 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3133 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3134 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3135 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3136 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3137 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3138 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3139 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3140 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3141 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3142 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3143 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3144 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3145 env->hreset_excp_prefix = 0x00000000UL;
3146 /* Hardware reset vector */
3147 env->hreset_vector = 0xFFFFFFFCUL;
3148 #endif
3149 }
3150
3151 #if defined (TARGET_PPC64)
3152 static void init_excp_970 (CPUPPCState *env)
3153 {
3154 #if !defined(CONFIG_USER_ONLY)
3155 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3156 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3157 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3158 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3159 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3160 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3161 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3162 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3163 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3164 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3165 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3166 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3167 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3168 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3169 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3170 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3171 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3172 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3173 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3174 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3175 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
3176 /* Hardware reset vector */
3177 env->hreset_vector = 0x0000000000000100ULL;
3178 #endif
3179 }
3180
3181 static void init_excp_POWER7 (CPUPPCState *env)
3182 {
3183 #if !defined(CONFIG_USER_ONLY)
3184 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3185 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3186 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3187 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3188 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3189 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3190 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3191 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3192 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3193 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3194 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3195 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3196 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3197 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3198 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3199 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3200 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3201 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3202 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3203 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3204 env->hreset_excp_prefix = 0;
3205 /* Hardware reset vector */
3206 env->hreset_vector = 0x0000000000000100ULL;
3207 #endif
3208 }
3209 #endif
3210
3211 /*****************************************************************************/
3212 /* Power management enable checks */
3213 static int check_pow_none (CPUPPCState *env)
3214 {
3215 return 0;
3216 }
3217
3218 static int check_pow_nocheck (CPUPPCState *env)
3219 {
3220 return 1;
3221 }
3222
3223 static int check_pow_hid0 (CPUPPCState *env)
3224 {
3225 if (env->spr[SPR_HID0] & 0x00E00000)
3226 return 1;
3227
3228 return 0;
3229 }
3230
3231 static int check_pow_hid0_74xx (CPUPPCState *env)
3232 {
3233 if (env->spr[SPR_HID0] & 0x00600000)
3234 return 1;
3235
3236 return 0;
3237 }
3238
3239 /*****************************************************************************/
3240 /* PowerPC implementations definitions */
3241
3242 /* PowerPC 401 */
3243 #define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3244 PPC_WRTEE | PPC_DCR | \
3245 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3246 PPC_CACHE_DCBZ | \
3247 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3248 PPC_4xx_COMMON | PPC_40x_EXCP)
3249 #define POWERPC_INSNS2_401 (PPC_NONE)
3250 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
3251 #define POWERPC_MMU_401 (POWERPC_MMU_REAL)
3252 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3253 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
3254 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
3255 #define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3256 POWERPC_FLAG_BUS_CLK)
3257 #define check_pow_401 check_pow_nocheck
3258
3259 static void init_proc_401 (CPUPPCState *env)
3260 {
3261 gen_spr_40x(env);
3262 gen_spr_401_403(env);
3263 gen_spr_401(env);
3264 init_excp_4xx_real(env);
3265 env->dcache_line_size = 32;
3266 env->icache_line_size = 32;
3267 /* Allocate hardware IRQ controller */
3268 ppc40x_irq_init(env);
3269
3270 SET_FIT_PERIOD(12, 16, 20, 24);
3271 SET_WDT_PERIOD(16, 20, 24, 28);
3272 }
3273
3274 /* PowerPC 401x2 */
3275 #define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3276 PPC_DCR | PPC_WRTEE | \
3277 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3278 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3279 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3280 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3281 PPC_4xx_COMMON | PPC_40x_EXCP)
3282 #define POWERPC_INSNS2_401x2 (PPC_NONE)
3283 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3284 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3285 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3286 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
3287 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
3288 #define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3289 POWERPC_FLAG_BUS_CLK)
3290 #define check_pow_401x2 check_pow_nocheck
3291
3292 static void init_proc_401x2 (CPUPPCState *env)
3293 {
3294 gen_spr_40x(env);
3295 gen_spr_401_403(env);
3296 gen_spr_401x2(env);
3297 gen_spr_compress(env);
3298 /* Memory management */
3299 #if !defined(CONFIG_USER_ONLY)
3300 env->nb_tlb = 64;
3301 env->nb_ways = 1;
3302 env->id_tlbs = 0;
3303 env->tlb_type = TLB_EMB;
3304 #endif
3305 init_excp_4xx_softmmu(env);
3306 env->dcache_line_size = 32;
3307 env->icache_line_size = 32;
3308 /* Allocate hardware IRQ controller */
3309 ppc40x_irq_init(env);
3310
3311 SET_FIT_PERIOD(12, 16, 20, 24);
3312 SET_WDT_PERIOD(16, 20, 24, 28);
3313 }
3314
3315 /* PowerPC 401x3 */
3316 #define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3317 PPC_DCR | PPC_WRTEE | \
3318 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3319 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3320 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3321 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3322 PPC_4xx_COMMON | PPC_40x_EXCP)
3323 #define POWERPC_INSNS2_401x3 (PPC_NONE)
3324 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3325 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3326 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3327 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
3328 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
3329 #define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3330 POWERPC_FLAG_BUS_CLK)
3331 #define check_pow_401x3 check_pow_nocheck
3332
3333 __attribute__ (( unused ))
3334 static void init_proc_401x3 (CPUPPCState *env)
3335 {
3336 gen_spr_40x(env);
3337 gen_spr_401_403(env);
3338 gen_spr_401(env);
3339 gen_spr_401x2(env);
3340 gen_spr_compress(env);
3341 init_excp_4xx_softmmu(env);
3342 env->dcache_line_size = 32;
3343 env->icache_line_size = 32;
3344 /* Allocate hardware IRQ controller */
3345 ppc40x_irq_init(env);
3346
3347 SET_FIT_PERIOD(12, 16, 20, 24);
3348 SET_WDT_PERIOD(16, 20, 24, 28);
3349 }
3350
3351 /* IOP480 */
3352 #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3353 PPC_DCR | PPC_WRTEE | \
3354 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3355 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3356 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3357 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3358 PPC_4xx_COMMON | PPC_40x_EXCP)
3359 #define POWERPC_INSNS2_IOP480 (PPC_NONE)
3360 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3361 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3362 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3363 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3364 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
3365 #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3366 POWERPC_FLAG_BUS_CLK)
3367 #define check_pow_IOP480 check_pow_nocheck
3368
3369 static void init_proc_IOP480 (CPUPPCState *env)
3370 {
3371 gen_spr_40x(env);
3372 gen_spr_401_403(env);
3373 gen_spr_401x2(env);
3374 gen_spr_compress(env);
3375 /* Memory management */
3376 #if !defined(CONFIG_USER_ONLY)
3377 env->nb_tlb = 64;
3378 env->nb_ways = 1;
3379 env->id_tlbs = 0;
3380 env->tlb_type = TLB_EMB;
3381 #endif
3382 init_excp_4xx_softmmu(env);
3383 env->dcache_line_size = 32;
3384 env->icache_line_size = 32;
3385 /* Allocate hardware IRQ controller */
3386 ppc40x_irq_init(env);
3387
3388 SET_FIT_PERIOD(8, 12, 16, 20);
3389 SET_WDT_PERIOD(16, 20, 24, 28);
3390 }
3391
3392 /* PowerPC 403 */
3393 #define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3394 PPC_DCR | PPC_WRTEE | \
3395 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3396 PPC_CACHE_DCBZ | \
3397 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3398 PPC_4xx_COMMON | PPC_40x_EXCP)
3399 #define POWERPC_INSNS2_403 (PPC_NONE)
3400 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
3401 #define POWERPC_MMU_403 (POWERPC_MMU_REAL)
3402 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3403 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
3404 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
3405 #define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3406 POWERPC_FLAG_BUS_CLK)
3407 #define check_pow_403 check_pow_nocheck
3408
3409 static void init_proc_403 (CPUPPCState *env)
3410 {
3411 gen_spr_40x(env);
3412 gen_spr_401_403(env);
3413 gen_spr_403(env);
3414 gen_spr_403_real(env);
3415 init_excp_4xx_real(env);
3416 env->dcache_line_size = 32;
3417 env->icache_line_size = 32;
3418 /* Allocate hardware IRQ controller */
3419 ppc40x_irq_init(env);
3420
3421 SET_FIT_PERIOD(8, 12, 16, 20);
3422 SET_WDT_PERIOD(16, 20, 24, 28);
3423 }
3424
3425 /* PowerPC 403 GCX */
3426 #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3427 PPC_DCR | PPC_WRTEE | \
3428 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3429 PPC_CACHE_DCBZ | \
3430 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3431 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3432 PPC_4xx_COMMON | PPC_40x_EXCP)
3433 #define POWERPC_INSNS2_403GCX (PPC_NONE)
3434 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3435 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3436 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3437 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3438 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
3439 #define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3440 POWERPC_FLAG_BUS_CLK)
3441 #define check_pow_403GCX check_pow_nocheck
3442
3443 static void init_proc_403GCX (CPUPPCState *env)
3444 {
3445 gen_spr_40x(env);
3446 gen_spr_401_403(env);
3447 gen_spr_403(env);
3448 gen_spr_403_real(env);
3449 gen_spr_403_mmu(env);
3450 /* Bus access control */
3451 /* not emulated, as Qemu never does speculative access */
3452 spr_register(env, SPR_40x_SGR, "SGR",
3453 SPR_NOACCESS, SPR_NOACCESS,
3454 &spr_read_generic, &spr_write_generic,
3455 0xFFFFFFFF);
3456 /* not emulated, as Qemu do not emulate caches */
3457 spr_register(env, SPR_40x_DCWR, "DCWR",
3458 SPR_NOACCESS, SPR_NOACCESS,
3459 &spr_read_generic, &spr_write_generic,
3460 0x00000000);
3461 /* Memory management */
3462 #if !defined(CONFIG_USER_ONLY)
3463 env->nb_tlb = 64;
3464 env->nb_ways = 1;
3465 env->id_tlbs = 0;
3466 env->tlb_type = TLB_EMB;
3467 #endif
3468 init_excp_4xx_softmmu(env);
3469 env->dcache_line_size = 32;
3470 env->icache_line_size = 32;
3471 /* Allocate hardware IRQ controller */
3472 ppc40x_irq_init(env);
3473
3474 SET_FIT_PERIOD(8, 12, 16, 20);
3475 SET_WDT_PERIOD(16, 20, 24, 28);
3476 }
3477
3478 /* PowerPC 405 */
3479 #define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3480 PPC_DCR | PPC_WRTEE | \
3481 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3482 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3483 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3484 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3485 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3486 #define POWERPC_INSNS2_405 (PPC_NONE)
3487 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
3488 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3489 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3490 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3491 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3492 #define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3493 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3494 #define check_pow_405 check_pow_nocheck
3495
3496 static void init_proc_405 (CPUPPCState *env)
3497 {
3498 /* Time base */
3499 gen_tbl(env);
3500 gen_spr_40x(env);
3501 gen_spr_405(env);
3502 /* Bus access control */
3503 /* not emulated, as Qemu never does speculative access */
3504 spr_register(env, SPR_40x_SGR, "SGR",
3505 SPR_NOACCESS, SPR_NOACCESS,
3506 &spr_read_generic, &spr_write_generic,
3507 0xFFFFFFFF);
3508 /* not emulated, as Qemu do not emulate caches */
3509 spr_register(env, SPR_40x_DCWR, "DCWR",
3510 SPR_NOACCESS, SPR_NOACCESS,
3511 &spr_read_generic, &spr_write_generic,
3512 0x00000000);
3513 /* Memory management */
3514 #if !defined(CONFIG_USER_ONLY)
3515 env->nb_tlb = 64;
3516 env->nb_ways = 1;
3517 env->id_tlbs = 0;
3518 env->tlb_type = TLB_EMB;
3519 #endif
3520 init_excp_4xx_softmmu(env);
3521 env->dcache_line_size = 32;
3522 env->icache_line_size = 32;
3523 /* Allocate hardware IRQ controller */
3524 ppc40x_irq_init(env);
3525
3526 SET_FIT_PERIOD(8, 12, 16, 20);
3527 SET_WDT_PERIOD(16, 20, 24, 28);
3528 }
3529
3530 /* PowerPC 440 EP */
3531 #define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3532 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3533 PPC_CACHE | PPC_CACHE_ICBI | \
3534 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3535 PPC_MEM_TLBSYNC | PPC_MFTB | \
3536 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3537 PPC_440_SPEC)
3538 #define POWERPC_INSNS2_440EP (PPC_NONE)
3539 #define POWERPC_MSRM_440EP (0x000000000006D630ULL)
3540 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3541 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3542 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3543 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3544 #define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3545 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3546 #define check_pow_440EP check_pow_nocheck
3547
3548 __attribute__ (( unused ))
3549 static void init_proc_440EP (CPUPPCState *env)
3550 {
3551 /* Time base */
3552 gen_tbl(env);
3553 gen_spr_BookE(env, 0x000000000000FFFFULL);
3554 gen_spr_440(env);
3555 gen_spr_usprgh(env);
3556 /* Processor identification */
3557 spr_register(env, SPR_BOOKE_PIR, "PIR",
3558 SPR_NOACCESS, SPR_NOACCESS,
3559 &spr_read_generic, &spr_write_pir,
3560 0x00000000);
3561 /* XXX : not implemented */
3562 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3563 SPR_NOACCESS, SPR_NOACCESS,
3564 &spr_read_generic, &spr_write_generic,
3565 0x00000000);
3566 /* XXX : not implemented */
3567 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3568 SPR_NOACCESS, SPR_NOACCESS,
3569 &spr_read_generic, &spr_write_generic,
3570 0x00000000);
3571 /* XXX : not implemented */
3572 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3573 SPR_NOACCESS, SPR_NOACCESS,
3574 &spr_read_generic, &spr_write_generic,
3575 0x00000000);
3576 /* XXX : not implemented */
3577 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3578 SPR_NOACCESS, SPR_NOACCESS,
3579 &spr_read_generic, &spr_write_generic,
3580 0x00000000);
3581 /* XXX : not implemented */
3582 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3583 SPR_NOACCESS, SPR_NOACCESS,
3584 &spr_read_generic, &spr_write_generic,
3585 0x00000000);
3586 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3587 SPR_NOACCESS, SPR_NOACCESS,
3588 &spr_read_generic, &spr_write_generic,
3589 0x00000000);
3590 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3591 SPR_NOACCESS, SPR_NOACCESS,
3592 &spr_read_generic, &spr_write_generic,
3593 0x00000000);
3594 /* XXX : not implemented */
3595 spr_register(env, SPR_440_CCR1, "CCR1",
3596 SPR_NOACCESS, SPR_NOACCESS,
3597 &spr_read_generic, &spr_write_generic,
3598 0x00000000);
3599 /* Memory management */
3600 #if !defined(CONFIG_USER_ONLY)
3601 env->nb_tlb = 64;
3602 env->nb_ways = 1;
3603 env->id_tlbs = 0;
3604 env->tlb_type = TLB_EMB;
3605 #endif
3606 init_excp_BookE(env);
3607 env->dcache_line_size = 32;
3608 env->icache_line_size = 32;
3609 /* XXX: TODO: allocate internal IRQ controller */
3610
3611 SET_FIT_PERIOD(12, 16, 20, 24);
3612 SET_WDT_PERIOD(20, 24, 28, 32);
3613 }
3614
3615 /* PowerPC 440 GP */
3616 #define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3617 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3618 PPC_CACHE | PPC_CACHE_ICBI | \
3619 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3620 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \
3621 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3622 PPC_440_SPEC)
3623 #define POWERPC_INSNS2_440GP (PPC_NONE)
3624 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3625 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3626 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3627 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3628 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3629 #define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3630 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3631 #define check_pow_440GP check_pow_nocheck
3632
3633 __attribute__ (( unused ))
3634 static void init_proc_440GP (CPUPPCState *env)
3635 {
3636 /* Time base */
3637 gen_tbl(env);
3638 gen_spr_BookE(env, 0x000000000000FFFFULL);
3639 gen_spr_440(env);
3640 gen_spr_usprgh(env);
3641 /* Processor identification */
3642 spr_register(env, SPR_BOOKE_PIR, "PIR",
3643 SPR_NOACCESS, SPR_NOACCESS,
3644 &spr_read_generic, &spr_write_pir,
3645 0x00000000);
3646 /* XXX : not implemented */
3647 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3648 SPR_NOACCESS, SPR_NOACCESS,
3649 &spr_read_generic, &spr_write_generic,
3650 0x00000000);
3651 /* XXX : not implemented */
3652 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3653 SPR_NOACCESS, SPR_NOACCESS,
3654 &spr_read_generic, &spr_write_generic,
3655 0x00000000);
3656 /* XXX : not implemented */
3657 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3658 SPR_NOACCESS, SPR_NOACCESS,
3659 &spr_read_generic, &spr_write_generic,
3660 0x00000000);
3661 /* XXX : not implemented */
3662 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3663 SPR_NOACCESS, SPR_NOACCESS,
3664 &spr_read_generic, &spr_write_generic,
3665 0x00000000);
3666 /* Memory management */
3667 #if !defined(CONFIG_USER_ONLY)
3668 env->nb_tlb = 64;
3669 env->nb_ways = 1;
3670 env->id_tlbs = 0;
3671 env->tlb_type = TLB_EMB;
3672 #endif
3673 init_excp_BookE(env);
3674 env->dcache_line_size = 32;
3675 env->icache_line_size = 32;
3676 /* XXX: TODO: allocate internal IRQ controller */
3677
3678 SET_FIT_PERIOD(12, 16, 20, 24);
3679 SET_WDT_PERIOD(20, 24, 28, 32);
3680 }
3681
3682 /* PowerPC 440x4 */
3683 #define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3684 PPC_DCR | PPC_WRTEE | \
3685 PPC_CACHE | PPC_CACHE_ICBI | \
3686 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3687 PPC_MEM_TLBSYNC | PPC_MFTB | \
3688 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3689 PPC_440_SPEC)
3690 #define POWERPC_INSNS2_440x4 (PPC_NONE)
3691 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3692 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3693 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3694 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3695 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3696 #define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3697 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3698 #define check_pow_440x4 check_pow_nocheck
3699
3700 __attribute__ (( unused ))
3701 static void init_proc_440x4 (CPUPPCState *env)
3702 {
3703 /* Time base */
3704 gen_tbl(env);
3705 gen_spr_BookE(env, 0x000000000000FFFFULL);
3706 gen_spr_440(env);
3707 gen_spr_usprgh(env);
3708 /* Processor identification */
3709 spr_register(env, SPR_BOOKE_PIR, "PIR",
3710 SPR_NOACCESS, SPR_NOACCESS,
3711 &spr_read_generic, &spr_write_pir,
3712 0x00000000);
3713 /* XXX : not implemented */
3714 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3715 SPR_NOACCESS, SPR_NOACCESS,
3716 &spr_read_generic, &spr_write_generic,
3717 0x00000000);
3718 /* XXX : not implemented */
3719 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3720 SPR_NOACCESS, SPR_NOACCESS,
3721 &spr_read_generic, &spr_write_generic,
3722 0x00000000);
3723 /* XXX : not implemented */
3724 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3725 SPR_NOACCESS, SPR_NOACCESS,
3726 &spr_read_generic, &spr_write_generic,
3727 0x00000000);
3728 /* XXX : not implemented */
3729 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3730 SPR_NOACCESS, SPR_NOACCESS,
3731 &spr_read_generic, &spr_write_generic,
3732 0x00000000);
3733 /* Memory management */
3734 #if !defined(CONFIG_USER_ONLY)
3735 env->nb_tlb = 64;
3736 env->nb_ways = 1;
3737 env->id_tlbs = 0;
3738 env->tlb_type = TLB_EMB;
3739 #endif
3740 init_excp_BookE(env);
3741 env->dcache_line_size = 32;
3742 env->icache_line_size = 32;
3743 /* XXX: TODO: allocate internal IRQ controller */
3744
3745 SET_FIT_PERIOD(12, 16, 20, 24);
3746 SET_WDT_PERIOD(20, 24, 28, 32);
3747 }
3748
3749 /* PowerPC 440x5 */
3750 #define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3751 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3752 PPC_CACHE | PPC_CACHE_ICBI | \
3753 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3754 PPC_MEM_TLBSYNC | PPC_MFTB | \
3755 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3756 PPC_440_SPEC)
3757 #define POWERPC_INSNS2_440x5 (PPC_NONE)
3758 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3759 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3760 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3761 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3762 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3763 #define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3764 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3765 #define check_pow_440x5 check_pow_nocheck
3766
3767 static void init_proc_440x5 (CPUPPCState *env)
3768 {
3769 /* Time base */
3770 gen_tbl(env);
3771 gen_spr_BookE(env, 0x000000000000FFFFULL);
3772 gen_spr_440(env);
3773 gen_spr_usprgh(env);
3774 /* Processor identification */
3775 spr_register(env, SPR_BOOKE_PIR, "PIR",
3776 SPR_NOACCESS, SPR_NOACCESS,
3777 &spr_read_generic, &spr_write_pir,
3778 0x00000000);
3779 /* XXX : not implemented */
3780 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3781 SPR_NOACCESS, SPR_NOACCESS,
3782 &spr_read_generic, &spr_write_generic,
3783 0x00000000);
3784 /* XXX : not implemented */
3785 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3786 SPR_NOACCESS, SPR_NOACCESS,
3787 &spr_read_generic, &spr_write_generic,
3788 0x00000000);
3789 /* XXX : not implemented */
3790 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3791 SPR_NOACCESS, SPR_NOACCESS,
3792 &spr_read_generic, &spr_write_generic,
3793 0x00000000);
3794 /* XXX : not implemented */
3795 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3796 SPR_NOACCESS, SPR_NOACCESS,
3797 &spr_read_generic, &spr_write_generic,
3798 0x00000000);
3799 /* XXX : not implemented */
3800 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3801 SPR_NOACCESS, SPR_NOACCESS,
3802 &spr_read_generic, &spr_write_generic,
3803 0x00000000);
3804 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3805 SPR_NOACCESS, SPR_NOACCESS,
3806 &spr_read_generic, &spr_write_generic,
3807 0x00000000);
3808 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3809 SPR_NOACCESS, SPR_NOACCESS,
3810 &spr_read_generic, &spr_write_generic,
3811 0x00000000);
3812 /* XXX : not implemented */
3813 spr_register(env, SPR_440_CCR1, "CCR1",
3814 SPR_NOACCESS, SPR_NOACCESS,
3815 &spr_read_generic, &spr_write_generic,
3816 0x00000000);
3817 /* Memory management */
3818 #if !defined(CONFIG_USER_ONLY)
3819 env->nb_tlb = 64;
3820 env->nb_ways = 1;
3821 env->id_tlbs = 0;
3822 env->tlb_type = TLB_EMB;
3823 #endif
3824 init_excp_BookE(env);
3825 env->dcache_line_size = 32;
3826 env->icache_line_size = 32;
3827 ppc40x_irq_init(env);
3828
3829 SET_FIT_PERIOD(12, 16, 20, 24);
3830 SET_WDT_PERIOD(20, 24, 28, 32);
3831 }
3832
3833 /* PowerPC 460 (guessed) */
3834 #define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
3835 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3836 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \
3837 PPC_CACHE | PPC_CACHE_ICBI | \
3838 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3839 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3840 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3841 PPC_440_SPEC)
3842 #define POWERPC_INSNS2_460 (PPC_NONE)
3843 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3844 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3845 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3846 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3847 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3848 #define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3849 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3850 #define check_pow_460 check_pow_nocheck
3851
3852 __attribute__ (( unused ))
3853 static void init_proc_460 (CPUPPCState *env)
3854 {
3855 /* Time base */
3856 gen_tbl(env);
3857 gen_spr_BookE(env, 0x000000000000FFFFULL);
3858 gen_spr_440(env);
3859 gen_spr_usprgh(env);
3860 /* Processor identification */
3861 spr_register(env, SPR_BOOKE_PIR, "PIR",
3862 SPR_NOACCESS, SPR_NOACCESS,
3863 &spr_read_generic, &spr_write_pir,
3864 0x00000000);
3865 /* XXX : not implemented */
3866 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3867 SPR_NOACCESS, SPR_NOACCESS,
3868 &spr_read_generic, &spr_write_generic,
3869 0x00000000);
3870 /* XXX : not implemented */
3871 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3872 SPR_NOACCESS, SPR_NOACCESS,
3873 &spr_read_generic, &spr_write_generic,
3874 0x00000000);
3875 /* XXX : not implemented */
3876 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3877 SPR_NOACCESS, SPR_NOACCESS,
3878 &spr_read_generic, &spr_write_generic,
3879 0x00000000);
3880 /* XXX : not implemented */
3881 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3882 SPR_NOACCESS, SPR_NOACCESS,
3883 &spr_read_generic, &spr_write_generic,
3884 0x00000000);
3885 /* XXX : not implemented */
3886 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3887 SPR_NOACCESS, SPR_NOACCESS,
3888 &spr_read_generic, &spr_write_generic,
3889 0x00000000);
3890 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3891 SPR_NOACCESS, SPR_NOACCESS,
3892 &spr_read_generic, &spr_write_generic,
3893 0x00000000);
3894 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3895 SPR_NOACCESS, SPR_NOACCESS,
3896 &spr_read_generic, &spr_write_generic,
3897 0x00000000);
3898 /* XXX : not implemented */
3899 spr_register(env, SPR_440_CCR1, "CCR1",
3900 SPR_NOACCESS, SPR_NOACCESS,
3901 &spr_read_generic, &spr_write_generic,
3902 0x00000000);
3903 /* XXX : not implemented */
3904 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3905 &spr_read_generic, &spr_write_generic,
3906 &spr_read_generic, &spr_write_generic,
3907 0x00000000);
3908 /* Memory management */
3909 #if !defined(CONFIG_USER_ONLY)
3910 env->nb_tlb = 64;
3911 env->nb_ways = 1;
3912 env->id_tlbs = 0;
3913 env->tlb_type = TLB_EMB;
3914 #endif
3915 init_excp_BookE(env);
3916 env->dcache_line_size = 32;
3917 env->icache_line_size = 32;
3918 /* XXX: TODO: allocate internal IRQ controller */
3919
3920 SET_FIT_PERIOD(12, 16, 20, 24);
3921 SET_WDT_PERIOD(20, 24, 28, 32);
3922 }
3923
3924 /* PowerPC 460F (guessed) */
3925 #define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3926 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3927 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3928 PPC_FLOAT_STFIWX | PPC_MFTB | \
3929 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3930 PPC_WRTEE | PPC_MFAPIDI | \
3931 PPC_CACHE | PPC_CACHE_ICBI | \
3932 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3933 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3934 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3935 PPC_440_SPEC)
3936 #define POWERPC_INSNS2_460F (PPC_NONE)
3937 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3938 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3939 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3940 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3941 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3942 #define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3943 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3944 #define check_pow_460F check_pow_nocheck
3945
3946 __attribute__ (( unused ))
3947 static void init_proc_460F (CPUPPCState *env)
3948 {
3949 /* Time base */
3950 gen_tbl(env);
3951 gen_spr_BookE(env, 0x000000000000FFFFULL);
3952 gen_spr_440(env);
3953 gen_spr_usprgh(env);
3954 /* Processor identification */
3955 spr_register(env, SPR_BOOKE_PIR, "PIR",
3956 SPR_NOACCESS, SPR_NOACCESS,
3957 &spr_read_generic, &spr_write_pir,
3958 0x00000000);
3959 /* XXX : not implemented */
3960 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3961 SPR_NOACCESS, SPR_NOACCESS,
3962 &spr_read_generic, &spr_write_generic,
3963 0x00000000);
3964 /* XXX : not implemented */
3965 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3966 SPR_NOACCESS, SPR_NOACCESS,
3967 &spr_read_generic, &spr_write_generic,
3968 0x00000000);
3969 /* XXX : not implemented */
3970 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3971 SPR_NOACCESS, SPR_NOACCESS,
3972 &spr_read_generic, &spr_write_generic,
3973 0x00000000);
3974 /* XXX : not implemented */
3975 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3976 SPR_NOACCESS, SPR_NOACCESS,
3977 &spr_read_generic, &spr_write_generic,
3978 0x00000000);
3979 /* XXX : not implemented */
3980 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3981 SPR_NOACCESS, SPR_NOACCESS,
3982 &spr_read_generic, &spr_write_generic,
3983 0x00000000);
3984 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3985 SPR_NOACCESS, SPR_NOACCESS,
3986 &spr_read_generic, &spr_write_generic,
3987 0x00000000);
3988 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3989 SPR_NOACCESS, SPR_NOACCESS,
3990 &spr_read_generic, &spr_write_generic,
3991 0x00000000);
3992 /* XXX : not implemented */
3993 spr_register(env, SPR_440_CCR1, "CCR1",
3994 SPR_NOACCESS, SPR_NOACCESS,
3995 &spr_read_generic, &spr_write_generic,
3996 0x00000000);
3997 /* XXX : not implemented */
3998 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3999 &spr_read_generic, &spr_write_generic,
4000 &spr_read_generic, &spr_write_generic,
4001 0x00000000);
4002 /* Memory management */
4003 #if !defined(CONFIG_USER_ONLY)
4004 env->nb_tlb = 64;
4005 env->nb_ways = 1;
4006 env->id_tlbs = 0;
4007 env->tlb_type = TLB_EMB;
4008 #endif
4009 init_excp_BookE(env);
4010 env->dcache_line_size = 32;
4011 env->icache_line_size = 32;
4012 /* XXX: TODO: allocate internal IRQ controller */
4013
4014 SET_FIT_PERIOD(12, 16, 20, 24);
4015 SET_WDT_PERIOD(20, 24, 28, 32);
4016 }
4017
4018 /* Freescale 5xx cores (aka RCPU) */
4019 #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
4020 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4021 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
4022 PPC_MFTB)
4023 #define POWERPC_INSNS2_MPC5xx (PPC_NONE)
4024 #define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
4025 #define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
4026 #define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
4027 #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
4028 #define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4029 #define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4030 POWERPC_FLAG_BUS_CLK)
4031 #define check_pow_MPC5xx check_pow_none
4032
4033 __attribute__ (( unused ))
4034 static void init_proc_MPC5xx (CPUPPCState *env)
4035 {
4036 /* Time base */
4037 gen_tbl(env);
4038 gen_spr_5xx_8xx(env);
4039 gen_spr_5xx(env);
4040 init_excp_MPC5xx(env);
4041 env->dcache_line_size = 32;
4042 env->icache_line_size = 32;
4043 /* XXX: TODO: allocate internal IRQ controller */
4044 }
4045
4046 /* Freescale 8xx cores (aka PowerQUICC) */
4047 #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
4048 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4049 PPC_CACHE_ICBI | PPC_MFTB)
4050 #define POWERPC_INSNS2_MPC8xx (PPC_NONE)
4051 #define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
4052 #define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
4053 #define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
4054 #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
4055 #define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4056 #define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4057 POWERPC_FLAG_BUS_CLK)
4058 #define check_pow_MPC8xx check_pow_none
4059
4060 __attribute__ (( unused ))
4061 static void init_proc_MPC8xx (CPUPPCState *env)
4062 {
4063 /* Time base */
4064 gen_tbl(env);
4065 gen_spr_5xx_8xx(env);
4066 gen_spr_8xx(env);
4067 init_excp_MPC8xx(env);
4068 env->dcache_line_size = 32;
4069 env->icache_line_size = 32;
4070 /* XXX: TODO: allocate internal IRQ controller */
4071 }
4072
4073 /* Freescale 82xx cores (aka PowerQUICC-II) */
4074 /* PowerPC G2 */
4075 #define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4076 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4077 PPC_FLOAT_STFIWX | \
4078 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4079 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4080 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4081 PPC_SEGMENT | PPC_EXTERN)
4082 #define POWERPC_INSNS2_G2 (PPC_NONE)
4083 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
4084 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
4085 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
4086 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
4087 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
4088 #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4089 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4090 #define check_pow_G2 check_pow_hid0
4091
4092 static void init_proc_G2 (CPUPPCState *env)
4093 {
4094 gen_spr_ne_601(env);
4095 gen_spr_G2_755(env);
4096 gen_spr_G2(env);
4097 /* Time base */
4098 gen_tbl(env);
4099 /* External access control */
4100 /* XXX : not implemented */
4101 spr_register(env, SPR_EAR, "EAR",
4102 SPR_NOACCESS, SPR_NOACCESS,
4103 &spr_read_generic, &spr_write_generic,
4104 0x00000000);
4105 /* Hardware implementation register */
4106 /* XXX : not implemented */
4107 spr_register(env, SPR_HID0, "HID0",
4108 SPR_NOACCESS, SPR_NOACCESS,
4109 &spr_read_generic, &spr_write_generic,
4110 0x00000000);
4111 /* XXX : not implemented */
4112 spr_register(env, SPR_HID1, "HID1",
4113 SPR_NOACCESS, SPR_NOACCESS,
4114 &spr_read_generic, &spr_write_generic,
4115 0x00000000);
4116 /* XXX : not implemented */
4117 spr_register(env, SPR_HID2, "HID2",
4118 SPR_NOACCESS, SPR_NOACCESS,
4119 &spr_read_generic, &spr_write_generic,
4120 0x00000000);
4121 /* Memory management */
4122 gen_low_BATs(env);
4123 gen_high_BATs(env);
4124 gen_6xx_7xx_soft_tlb(env, 64, 2);
4125 init_excp_G2(env);
4126 env->dcache_line_size = 32;
4127 env->icache_line_size = 32;
4128 /* Allocate hardware IRQ controller */
4129 ppc6xx_irq_init(env);
4130 }
4131
4132 /* PowerPC G2LE */
4133 #define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4134 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4135 PPC_FLOAT_STFIWX | \
4136 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4137 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4138 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4139 PPC_SEGMENT | PPC_EXTERN)
4140 #define POWERPC_INSNS2_G2LE (PPC_NONE)
4141 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
4142 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
4143 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
4144 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
4145 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
4146 #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4147 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4148 #define check_pow_G2LE check_pow_hid0
4149
4150 static void init_proc_G2LE (CPUPPCState *env)
4151 {
4152 gen_spr_ne_601(env);
4153 gen_spr_G2_755(env);
4154 gen_spr_G2(env);
4155 /* Time base */
4156 gen_tbl(env);
4157 /* External access control */
4158 /* XXX : not implemented */
4159 spr_register(env, SPR_EAR, "EAR",
4160 SPR_NOACCESS, SPR_NOACCESS,
4161 &spr_read_generic, &spr_write_generic,
4162 0x00000000);
4163 /* Hardware implementation register */
4164 /* XXX : not implemented */
4165 spr_register(env, SPR_HID0, "HID0",
4166 SPR_NOACCESS, SPR_NOACCESS,
4167 &spr_read_generic, &spr_write_generic,
4168 0x00000000);
4169 /* XXX : not implemented */
4170 spr_register(env, SPR_HID1, "HID1",
4171 SPR_NOACCESS, SPR_NOACCESS,
4172 &spr_read_generic, &spr_write_generic,
4173 0x00000000);
4174 /* XXX : not implemented */
4175 spr_register(env, SPR_HID2, "HID2",
4176 SPR_NOACCESS, SPR_NOACCESS,
4177 &spr_read_generic, &spr_write_generic,
4178 0x00000000);
4179 /* Memory management */
4180 gen_low_BATs(env);
4181 gen_high_BATs(env);
4182 gen_6xx_7xx_soft_tlb(env, 64, 2);
4183 init_excp_G2(env);
4184 env->dcache_line_size = 32;
4185 env->icache_line_size = 32;
4186 /* Allocate hardware IRQ controller */
4187 ppc6xx_irq_init(env);
4188 }
4189
4190 /* e200 core */
4191 /* XXX: unimplemented instructions:
4192 * dcblc
4193 * dcbtlst
4194 * dcbtstls
4195 * icblc
4196 * icbtls
4197 * tlbivax
4198 * all SPE multiply-accumulate instructions
4199 */
4200 #define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
4201 PPC_SPE | PPC_SPE_SINGLE | \
4202 PPC_WRTEE | PPC_RFDI | \
4203 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4204 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4205 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4206 PPC_BOOKE)
4207 #define POWERPC_INSNS2_e200 (PPC_NONE)
4208 #define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
4209 #define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
4210 #define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
4211 #define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
4212 #define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
4213 #define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4214 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4215 POWERPC_FLAG_BUS_CLK)
4216 #define check_pow_e200 check_pow_hid0
4217
4218 __attribute__ (( unused ))
4219 static void init_proc_e200 (CPUPPCState *env)
4220 {
4221 /* Time base */
4222 gen_tbl(env);
4223 gen_spr_BookE(env, 0x000000070000FFFFULL);
4224 /* XXX : not implemented */
4225 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4226 &spr_read_spefscr, &spr_write_spefscr,
4227 &spr_read_spefscr, &spr_write_spefscr,
4228 0x00000000);
4229 /* Memory management */
4230 gen_spr_BookE206(env, 0x0000005D, NULL);
4231 /* XXX : not implemented */
4232 spr_register(env, SPR_HID0, "HID0",
4233 SPR_NOACCESS, SPR_NOACCESS,
4234 &spr_read_generic, &spr_write_generic,
4235 0x00000000);
4236 /* XXX : not implemented */
4237 spr_register(env, SPR_HID1, "HID1",
4238 SPR_NOACCESS, SPR_NOACCESS,
4239 &spr_read_generic, &spr_write_generic,
4240 0x00000000);
4241 /* XXX : not implemented */
4242 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4243 SPR_NOACCESS, SPR_NOACCESS,
4244 &spr_read_generic, &spr_write_generic,
4245 0x00000000);
4246 /* XXX : not implemented */
4247 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4248 SPR_NOACCESS, SPR_NOACCESS,
4249 &spr_read_generic, &spr_write_generic,
4250 0x00000000);
4251 /* XXX : not implemented */
4252 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4253 SPR_NOACCESS, SPR_NOACCESS,
4254 &spr_read_generic, &spr_write_generic,
4255 0x00000000);
4256 /* XXX : not implemented */
4257 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4258 SPR_NOACCESS, SPR_NOACCESS,
4259 &spr_read_generic, &spr_write_generic,
4260 0x00000000);
4261 /* XXX : not implemented */
4262 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4263 SPR_NOACCESS, SPR_NOACCESS,
4264 &spr_read_generic, &spr_write_generic,
4265 0x00000000);
4266 /* XXX : not implemented */
4267 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4268 SPR_NOACCESS, SPR_NOACCESS,
4269 &spr_read_generic, &spr_write_generic,
4270 0x00000000);
4271 /* XXX : not implemented */
4272 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4273 SPR_NOACCESS, SPR_NOACCESS,
4274 &spr_read_generic, &spr_write_generic,
4275 0x00000000);
4276 /* XXX : not implemented */
4277 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4278 SPR_NOACCESS, SPR_NOACCESS,
4279 &spr_read_generic, &spr_write_generic,
4280 0x00000000);
4281 /* XXX : not implemented */
4282 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4283 SPR_NOACCESS, SPR_NOACCESS,
4284 &spr_read_generic, &spr_write_generic,
4285 0x00000000);
4286 /* XXX : not implemented */
4287 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4288 SPR_NOACCESS, SPR_NOACCESS,
4289 &spr_read_generic, &spr_write_generic,
4290 0x00000000);
4291 /* XXX : not implemented */
4292 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4293 SPR_NOACCESS, SPR_NOACCESS,
4294 &spr_read_generic, &spr_write_generic,
4295 0x00000000);
4296 /* XXX : not implemented */
4297 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4298 SPR_NOACCESS, SPR_NOACCESS,
4299 &spr_read_generic, &spr_write_generic,
4300 0x00000000);
4301 /* XXX : not implemented */
4302 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4303 SPR_NOACCESS, SPR_NOACCESS,
4304 &spr_read_generic, &spr_write_generic,
4305 0x00000000); /* TOFIX */
4306 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4307 SPR_NOACCESS, SPR_NOACCESS,
4308 &spr_read_generic, &spr_write_generic,
4309 0x00000000);
4310 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4311 SPR_NOACCESS, SPR_NOACCESS,
4312 &spr_read_generic, &spr_write_generic,
4313 0x00000000);
4314 #if !defined(CONFIG_USER_ONLY)
4315 env->nb_tlb = 64;
4316 env->nb_ways = 1;
4317 env->id_tlbs = 0;
4318 env->tlb_type = TLB_EMB;
4319 #endif
4320 init_excp_e200(env);
4321 env->dcache_line_size = 32;
4322 env->icache_line_size = 32;
4323 /* XXX: TODO: allocate internal IRQ controller */
4324 }
4325
4326 /* e300 core */
4327 #define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4328 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4329 PPC_FLOAT_STFIWX | \
4330 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4331 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4332 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4333 PPC_SEGMENT | PPC_EXTERN)
4334 #define POWERPC_INSNS2_e300 (PPC_NONE)
4335 #define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4336 #define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4337 #define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4338 #define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4339 #define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4340 #define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4341 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4342 #define check_pow_e300 check_pow_hid0
4343
4344 __attribute__ (( unused ))
4345 static void init_proc_e300 (CPUPPCState *env)
4346 {
4347 gen_spr_ne_601(env);
4348 gen_spr_603(env);
4349 /* Time base */
4350 gen_tbl(env);
4351 /* hardware implementation registers */
4352 /* XXX : not implemented */
4353 spr_register(env, SPR_HID0, "HID0",
4354 SPR_NOACCESS, SPR_NOACCESS,
4355 &spr_read_generic, &spr_write_generic,
4356 0x00000000);
4357 /* XXX : not implemented */
4358 spr_register(env, SPR_HID1, "HID1",
4359 SPR_NOACCESS, SPR_NOACCESS,
4360 &spr_read_generic, &spr_write_generic,
4361 0x00000000);
4362 /* XXX : not implemented */
4363 spr_register(env, SPR_HID2, "HID2",
4364 SPR_NOACCESS, SPR_NOACCESS,
4365 &spr_read_generic, &spr_write_generic,
4366 0x00000000);
4367 /* Memory management */
4368 gen_low_BATs(env);
4369 gen_high_BATs(env);
4370 gen_6xx_7xx_soft_tlb(env, 64, 2);
4371 init_excp_603(env);
4372 env->dcache_line_size = 32;
4373 env->icache_line_size = 32;
4374 /* Allocate hardware IRQ controller */
4375 ppc6xx_irq_init(env);
4376 }
4377
4378 /* e500v1 core */
4379 #define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4380 PPC_SPE | PPC_SPE_SINGLE | \
4381 PPC_WRTEE | PPC_RFDI | \
4382 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4383 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4384 PPC_MEM_TLBSYNC | PPC_TLBIVAX)
4385 #define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206)
4386 #define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
4387 #define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
4388 #define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4389 #define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4390 #define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4391 #define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4392 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4393 POWERPC_FLAG_BUS_CLK)
4394 #define check_pow_e500v1 check_pow_hid0
4395 #define init_proc_e500v1 init_proc_e500v1
4396
4397 /* e500v2 core */
4398 #define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4399 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4400 PPC_WRTEE | PPC_RFDI | \
4401 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4402 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4403 PPC_MEM_TLBSYNC | PPC_TLBIVAX)
4404 #define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206)
4405 #define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
4406 #define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
4407 #define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4408 #define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4409 #define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4410 #define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4411 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4412 POWERPC_FLAG_BUS_CLK)
4413 #define check_pow_e500v2 check_pow_hid0
4414 #define init_proc_e500v2 init_proc_e500v2
4415
4416 static void init_proc_e500 (CPUPPCState *env, int version)
4417 {
4418 uint32_t tlbncfg[2];
4419 #if !defined(CONFIG_USER_ONLY)
4420 int i;
4421 #endif
4422
4423 /* Time base */
4424 gen_tbl(env);
4425 /*
4426 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4427 * complain when accessing them.
4428 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4429 */
4430 gen_spr_BookE(env, 0x0000000F0000FFFFULL);
4431 /* Processor identification */
4432 spr_register(env, SPR_BOOKE_PIR, "PIR",
4433 SPR_NOACCESS, SPR_NOACCESS,
4434 &spr_read_generic, &spr_write_pir,
4435 0x00000000);
4436 /* XXX : not implemented */
4437 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4438 &spr_read_spefscr, &spr_write_spefscr,
4439 &spr_read_spefscr, &spr_write_spefscr,
4440 0x00000000);
4441 /* Memory management */
4442 #if !defined(CONFIG_USER_ONLY)
4443 env->nb_pids = 3;
4444 env->nb_ways = 2;
4445 env->id_tlbs = 0;
4446 switch (version) {
4447 case 1:
4448 /* e500v1 */
4449 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4450 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4451 break;
4452 case 2:
4453 /* e500v2 */
4454 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4455 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4456 break;
4457 default:
4458 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4459 }
4460 #endif
4461 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4462 /* XXX : not implemented */
4463 spr_register(env, SPR_HID0, "HID0",
4464 SPR_NOACCESS, SPR_NOACCESS,
4465 &spr_read_generic, &spr_write_generic,
4466 0x00000000);
4467 /* XXX : not implemented */
4468 spr_register(env, SPR_HID1, "HID1",
4469 SPR_NOACCESS, SPR_NOACCESS,
4470 &spr_read_generic, &spr_write_generic,
4471 0x00000000);
4472 /* XXX : not implemented */
4473 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4474 SPR_NOACCESS, SPR_NOACCESS,
4475 &spr_read_generic, &spr_write_generic,
4476 0x00000000);
4477 /* XXX : not implemented */
4478 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4479 SPR_NOACCESS, SPR_NOACCESS,
4480 &spr_read_generic, &spr_write_generic,
4481 0x00000000);
4482 /* XXX : not implemented */
4483 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4484 SPR_NOACCESS, SPR_NOACCESS,
4485 &spr_read_generic, &spr_write_generic,
4486 0x00000000);
4487 /* XXX : not implemented */
4488 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4489 SPR_NOACCESS, SPR_NOACCESS,
4490 &spr_read_generic, &spr_write_generic,
4491 0x00000000);
4492 /* XXX : not implemented */
4493 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4494 SPR_NOACCESS, SPR_NOACCESS,
4495 &spr_read_generic, &spr_write_generic,
4496 0x00000000);
4497 /* XXX : not implemented */
4498 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4499 SPR_NOACCESS, SPR_NOACCESS,
4500 &spr_read_generic, &spr_write_generic,
4501 0x00000000);
4502 /* XXX : not implemented */
4503 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4504 SPR_NOACCESS, SPR_NOACCESS,
4505 &spr_read_generic, &spr_write_generic,
4506 0x00000000);
4507 /* XXX : not implemented */
4508 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4509 SPR_NOACCESS, SPR_NOACCESS,
4510 &spr_read_generic, &spr_write_e500_l1csr0,
4511 0x00000000);
4512 /* XXX : not implemented */
4513 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4514 SPR_NOACCESS, SPR_NOACCESS,
4515 &spr_read_generic, &spr_write_generic,
4516 0x00000000);
4517 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4518 SPR_NOACCESS, SPR_NOACCESS,
4519 &spr_read_generic, &spr_write_generic,
4520 0x00000000);
4521 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4522 SPR_NOACCESS, SPR_NOACCESS,
4523 &spr_read_generic, &spr_write_generic,
4524 0x00000000);
4525 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4526 SPR_NOACCESS, SPR_NOACCESS,
4527 &spr_read_generic, &spr_write_booke206_mmucsr0,
4528 0x00000000);
4529
4530 #if !defined(CONFIG_USER_ONLY)
4531 env->nb_tlb = 0;
4532 env->tlb_type = TLB_MAS;
4533 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4534 env->nb_tlb += booke206_tlb_size(env, i);
4535 }
4536 #endif
4537
4538 init_excp_e200(env);
4539 env->dcache_line_size = 32;
4540 env->icache_line_size = 32;
4541 /* Allocate hardware IRQ controller */
4542 ppce500_irq_init(env);
4543 }
4544
4545 static void init_proc_e500v1(CPUPPCState *env)
4546 {
4547 init_proc_e500(env, 1);
4548 }
4549
4550 static void init_proc_e500v2(CPUPPCState *env)
4551 {
4552 init_proc_e500(env, 2);
4553 }
4554
4555 /* Non-embedded PowerPC */
4556
4557 /* POWER : same as 601, without mfmsr, mfsr */
4558 #if defined(TODO)
4559 #define POWERPC_INSNS_POWER (XXX_TODO)
4560 /* POWER RSC (from RAD6000) */
4561 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4562 #endif /* TODO */
4563
4564 /* PowerPC 601 */
4565 #define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4566 PPC_FLOAT | \
4567 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4568 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4569 PPC_SEGMENT | PPC_EXTERN)
4570 #define POWERPC_INSNS2_601 (PPC_NONE)
4571 #define POWERPC_MSRM_601 (0x000000000000FD70ULL)
4572 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4573 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
4574 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4575 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
4576 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4577 #define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4578 #define check_pow_601 check_pow_none
4579
4580 static void init_proc_601 (CPUPPCState *env)
4581 {
4582 gen_spr_ne_601(env);
4583 gen_spr_601(env);
4584 /* Hardware implementation registers */
4585 /* XXX : not implemented */
4586 spr_register(env, SPR_HID0, "HID0",
4587 SPR_NOACCESS, SPR_NOACCESS,
4588 &spr_read_generic, &spr_write_hid0_601,
4589 0x80010080);
4590 /* XXX : not implemented */
4591 spr_register(env, SPR_HID1, "HID1",
4592 SPR_NOACCESS, SPR_NOACCESS,
4593 &spr_read_generic, &spr_write_generic,
4594 0x00000000);
4595 /* XXX : not implemented */
4596 spr_register(env, SPR_601_HID2, "HID2",
4597 SPR_NOACCESS, SPR_NOACCESS,
4598 &spr_read_generic, &spr_write_generic,
4599 0x00000000);
4600 /* XXX : not implemented */
4601 spr_register(env, SPR_601_HID5, "HID5",
4602 SPR_NOACCESS, SPR_NOACCESS,
4603 &spr_read_generic, &spr_write_generic,
4604 0x00000000);
4605 /* Memory management */
4606 init_excp_601(env);
4607 /* XXX: beware that dcache line size is 64
4608 * but dcbz uses 32 bytes "sectors"
4609 * XXX: this breaks clcs instruction !
4610 */
4611 env->dcache_line_size = 32;
4612 env->icache_line_size = 64;
4613 /* Allocate hardware IRQ controller */
4614 ppc6xx_irq_init(env);
4615 }
4616
4617 /* PowerPC 601v */
4618 #define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4619 PPC_FLOAT | \
4620 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4621 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4622 PPC_SEGMENT | PPC_EXTERN)
4623 #define POWERPC_INSNS2_601v (PPC_NONE)
4624 #define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4625 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4626 #define POWERPC_MMU_601v (POWERPC_MMU_601)
4627 #define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4628 #define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4629 #define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4630 #define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4631 #define check_pow_601v check_pow_none
4632
4633 static void init_proc_601v (CPUPPCState *env)
4634 {
4635 init_proc_601(env);
4636 /* XXX : not implemented */
4637 spr_register(env, SPR_601_HID15, "HID15",
4638 SPR_NOACCESS, SPR_NOACCESS,
4639 &spr_read_generic, &spr_write_generic,
4640 0x00000000);
4641 }
4642
4643 /* PowerPC 602 */
4644 #define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4645 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4646 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4647 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4648 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4649 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4650 PPC_SEGMENT | PPC_602_SPEC)
4651 #define POWERPC_INSNS2_602 (PPC_NONE)
4652 #define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4653 /* XXX: 602 MMU is quite specific. Should add a special case */
4654 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4655 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4656 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
4657 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
4658 #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4659 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4660 #define check_pow_602 check_pow_hid0
4661
4662 static void init_proc_602 (CPUPPCState *env)
4663 {
4664 gen_spr_ne_601(env);
4665 gen_spr_602(env);
4666 /* Time base */
4667 gen_tbl(env);
4668 /* hardware implementation registers */
4669 /* XXX : not implemented */
4670 spr_register(env, SPR_HID0, "HID0",
4671 SPR_NOACCESS, SPR_NOACCESS,
4672 &spr_read_generic, &spr_write_generic,
4673 0x00000000);
4674 /* XXX : not implemented */
4675 spr_register(env, SPR_HID1, "HID1",
4676 SPR_NOACCESS, SPR_NOACCESS,
4677 &spr_read_generic, &spr_write_generic,
4678 0x00000000);
4679 /* Memory management */
4680 gen_low_BATs(env);
4681 gen_6xx_7xx_soft_tlb(env, 64, 2);
4682 init_excp_602(env);
4683 env->dcache_line_size = 32;
4684 env->icache_line_size = 32;
4685 /* Allocate hardware IRQ controller */
4686 ppc6xx_irq_init(env);
4687 }
4688
4689 /* PowerPC 603 */
4690 #define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4691 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4692 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4693 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4694 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4695 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4696 PPC_SEGMENT | PPC_EXTERN)
4697 #define POWERPC_INSNS2_603 (PPC_NONE)
4698 #define POWERPC_MSRM_603 (0x000000000007FF73ULL)
4699 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4700 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4701 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
4702 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
4703 #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4704 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4705 #define check_pow_603 check_pow_hid0
4706
4707 static void init_proc_603 (CPUPPCState *env)
4708 {
4709 gen_spr_ne_601(env);
4710 gen_spr_603(env);
4711 /* Time base */
4712 gen_tbl(env);
4713 /* hardware implementation registers */
4714 /* XXX : not implemented */
4715 spr_register(env, SPR_HID0, "HID0",
4716 SPR_NOACCESS, SPR_NOACCESS,
4717 &spr_read_generic, &spr_write_generic,
4718 0x00000000);
4719 /* XXX : not implemented */
4720 spr_register(env, SPR_HID1, "HID1",
4721 SPR_NOACCESS, SPR_NOACCESS,
4722 &spr_read_generic, &spr_write_generic,
4723 0x00000000);
4724 /* Memory management */
4725 gen_low_BATs(env);
4726 gen_6xx_7xx_soft_tlb(env, 64, 2);
4727 init_excp_603(env);
4728 env->dcache_line_size = 32;
4729 env->icache_line_size = 32;
4730 /* Allocate hardware IRQ controller */
4731 ppc6xx_irq_init(env);
4732 }
4733
4734 /* PowerPC 603e */
4735 #define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4736 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4737 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4738 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4739 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4740 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4741 PPC_SEGMENT | PPC_EXTERN)
4742 #define POWERPC_INSNS2_603E (PPC_NONE)
4743 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4744 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4745 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4746 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
4747 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
4748 #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4749 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4750 #define check_pow_603E check_pow_hid0
4751
4752 static void init_proc_603E (CPUPPCState *env)
4753 {
4754 gen_spr_ne_601(env);
4755 gen_spr_603(env);
4756 /* Time base */
4757 gen_tbl(env);
4758 /* hardware implementation registers */
4759 /* XXX : not implemented */
4760 spr_register(env, SPR_HID0, "HID0",
4761 SPR_NOACCESS, SPR_NOACCESS,
4762 &spr_read_generic, &spr_write_generic,
4763 0x00000000);
4764 /* XXX : not implemented */
4765 spr_register(env, SPR_HID1, "HID1",
4766 SPR_NOACCESS, SPR_NOACCESS,
4767 &spr_read_generic, &spr_write_generic,
4768 0x00000000);
4769 /* XXX : not implemented */
4770 spr_register(env, SPR_IABR, "IABR",
4771 SPR_NOACCESS, SPR_NOACCESS,
4772 &spr_read_generic, &spr_write_generic,
4773 0x00000000);
4774 /* Memory management */
4775 gen_low_BATs(env);
4776 gen_6xx_7xx_soft_tlb(env, 64, 2);
4777 init_excp_603(env);
4778 env->dcache_line_size = 32;
4779 env->icache_line_size = 32;
4780 /* Allocate hardware IRQ controller */
4781 ppc6xx_irq_init(env);
4782 }
4783
4784 /* PowerPC 604 */
4785 #define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4786 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4787 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4788 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4789 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4790 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4791 PPC_SEGMENT | PPC_EXTERN)
4792 #define POWERPC_INSNS2_604 (PPC_NONE)
4793 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4794 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
4795 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4796 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
4797 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
4798 #define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4799 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4800 #define check_pow_604 check_pow_nocheck
4801
4802 static void init_proc_604 (CPUPPCState *env)
4803 {
4804 gen_spr_ne_601(env);
4805 gen_spr_604(env);
4806 /* Time base */
4807 gen_tbl(env);
4808 /* Hardware implementation registers */
4809 /* XXX : not implemented */
4810 spr_register(env, SPR_HID0, "HID0",
4811 SPR_NOACCESS, SPR_NOACCESS,
4812 &spr_read_generic, &spr_write_generic,
4813 0x00000000);
4814 /* Memory management */
4815 gen_low_BATs(env);
4816 init_excp_604(env);
4817 env->dcache_line_size = 32;
4818 env->icache_line_size = 32;
4819 /* Allocate hardware IRQ controller */
4820 ppc6xx_irq_init(env);
4821 }
4822
4823 /* PowerPC 604E */
4824 #define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4825 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4826 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4827 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4828 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4829 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4830 PPC_SEGMENT | PPC_EXTERN)
4831 #define POWERPC_INSNS2_604E (PPC_NONE)
4832 #define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4833 #define POWERPC_MMU_604E (POWERPC_MMU_32B)
4834 #define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4835 #define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4836 #define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4837 #define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4838 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4839 #define check_pow_604E check_pow_nocheck
4840
4841 static void init_proc_604E (CPUPPCState *env)
4842 {
4843 gen_spr_ne_601(env);
4844 gen_spr_604(env);
4845 /* XXX : not implemented */
4846 spr_register(env, SPR_MMCR1, "MMCR1",
4847 SPR_NOACCESS, SPR_NOACCESS,
4848 &spr_read_generic, &spr_write_generic,
4849 0x00000000);
4850 /* XXX : not implemented */
4851 spr_register(env, SPR_PMC3, "PMC3",
4852 SPR_NOACCESS, SPR_NOACCESS,
4853 &spr_read_generic, &spr_write_generic,
4854 0x00000000);
4855 /* XXX : not implemented */
4856 spr_register(env, SPR_PMC4, "PMC4",
4857 SPR_NOACCESS, SPR_NOACCESS,
4858 &spr_read_generic, &spr_write_generic,
4859 0x00000000);
4860 /* Time base */
4861 gen_tbl(env);
4862 /* Hardware implementation registers */
4863 /* XXX : not implemented */
4864 spr_register(env, SPR_HID0, "HID0",
4865 SPR_NOACCESS, SPR_NOACCESS,
4866 &spr_read_generic, &spr_write_generic,
4867 0x00000000);
4868 /* XXX : not implemented */
4869 spr_register(env, SPR_HID1, "HID1",
4870 SPR_NOACCESS, SPR_NOACCESS,
4871 &spr_read_generic, &spr_write_generic,
4872 0x00000000);
4873 /* Memory management */
4874 gen_low_BATs(env);
4875 init_excp_604(env);
4876 env->dcache_line_size = 32;
4877 env->icache_line_size = 32;
4878 /* Allocate hardware IRQ controller */
4879 ppc6xx_irq_init(env);
4880 }
4881
4882 /* PowerPC 740 */
4883 #define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4884 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4885 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4886 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4887 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4888 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4889 PPC_SEGMENT | PPC_EXTERN)
4890 #define POWERPC_INSNS2_740 (PPC_NONE)
4891 #define POWERPC_MSRM_740 (0x000000000005FF77ULL)
4892 #define POWERPC_MMU_740 (POWERPC_MMU_32B)
4893 #define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
4894 #define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
4895 #define POWERPC_BFDM_740 (bfd_mach_ppc_750)
4896 #define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4897 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4898 #define check_pow_740 check_pow_hid0
4899
4900 static void init_proc_740 (CPUPPCState *env)
4901 {
4902 gen_spr_ne_601(env);
4903 gen_spr_7xx(env);
4904 /* Time base */
4905 gen_tbl(env);
4906 /* Thermal management */
4907 gen_spr_thrm(env);
4908 /* Hardware implementation registers */
4909 /* XXX : not implemented */
4910 spr_register(env, SPR_HID0, "HID0",
4911 SPR_NOACCESS, SPR_NOACCESS,
4912 &spr_read_generic, &spr_write_generic,
4913 0x00000000);
4914 /* XXX : not implemented */
4915 spr_register(env, SPR_HID1, "HID1",
4916 SPR_NOACCESS, SPR_NOACCESS,
4917 &spr_read_generic, &spr_write_generic,
4918 0x00000000);
4919 /* Memory management */
4920 gen_low_BATs(env);
4921 init_excp_7x0(env);
4922 env->dcache_line_size = 32;
4923 env->icache_line_size = 32;
4924 /* Allocate hardware IRQ controller */
4925 ppc6xx_irq_init(env);
4926 }
4927
4928 /* PowerPC 750 */
4929 #define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4930 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4931 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4932 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4933 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4934 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4935 PPC_SEGMENT | PPC_EXTERN)
4936 #define POWERPC_INSNS2_750 (PPC_NONE)
4937 #define POWERPC_MSRM_750 (0x000000000005FF77ULL)
4938 #define POWERPC_MMU_750 (POWERPC_MMU_32B)
4939 #define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
4940 #define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
4941 #define POWERPC_BFDM_750 (bfd_mach_ppc_750)
4942 #define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4943 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4944 #define check_pow_750 check_pow_hid0
4945
4946 static void init_proc_750 (CPUPPCState *env)
4947 {
4948 gen_spr_ne_601(env);
4949 gen_spr_7xx(env);
4950 /* XXX : not implemented */
4951 spr_register(env, SPR_L2CR, "L2CR",
4952 SPR_NOACCESS, SPR_NOACCESS,
4953 &spr_read_generic, &spr_write_generic,
4954 0x00000000);
4955 /* Time base */
4956 gen_tbl(env);
4957 /* Thermal management */
4958 gen_spr_thrm(env);
4959 /* Hardware implementation registers */
4960 /* XXX : not implemented */
4961 spr_register(env, SPR_HID0, "HID0",
4962 SPR_NOACCESS, SPR_NOACCESS,
4963 &spr_read_generic, &spr_write_generic,
4964 0x00000000);
4965 /* XXX : not implemented */
4966 spr_register(env, SPR_HID1, "HID1",
4967 SPR_NOACCESS, SPR_NOACCESS,
4968 &spr_read_generic, &spr_write_generic,
4969 0x00000000);
4970 /* Memory management */
4971 gen_low_BATs(env);
4972 /* XXX: high BATs are also present but are known to be bugged on
4973 * die version 1.x
4974 */
4975 init_excp_7x0(env);
4976 env->dcache_line_size = 32;
4977 env->icache_line_size = 32;
4978 /* Allocate hardware IRQ controller */
4979 ppc6xx_irq_init(env);
4980 }
4981
4982 /* PowerPC 750 CL */
4983 /* XXX: not implemented:
4984 * cache lock instructions:
4985 * dcbz_l
4986 * floating point paired instructions
4987 * psq_lux
4988 * psq_lx
4989 * psq_stux
4990 * psq_stx
4991 * ps_abs
4992 * ps_add
4993 * ps_cmpo0
4994 * ps_cmpo1
4995 * ps_cmpu0
4996 * ps_cmpu1
4997 * ps_div
4998 * ps_madd
4999 * ps_madds0
5000 * ps_madds1
5001 * ps_merge00
5002 * ps_merge01
5003 * ps_merge10
5004 * ps_merge11
5005 * ps_mr
5006 * ps_msub
5007 * ps_mul
5008 * ps_muls0
5009 * ps_muls1
5010 * ps_nabs
5011 * ps_neg
5012 * ps_nmadd
5013 * ps_nmsub
5014 * ps_res
5015 * ps_rsqrte
5016 * ps_sel
5017 * ps_sub
5018 * ps_sum0
5019 * ps_sum1
5020 */
5021 #define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5022 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5023 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5024 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5025 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5026 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5027 PPC_SEGMENT | PPC_EXTERN)
5028 #define POWERPC_INSNS2_750cl (PPC_NONE)
5029 #define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
5030 #define POWERPC_MMU_750cl (POWERPC_MMU_32B)
5031 #define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
5032 #define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
5033 #define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
5034 #define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5035 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5036 #define check_pow_750cl check_pow_hid0
5037
5038 static void init_proc_750cl (CPUPPCState *env)
5039 {
5040 gen_spr_ne_601(env);
5041 gen_spr_7xx(env);
5042 /* XXX : not implemented */
5043 spr_register(env, SPR_L2CR, "L2CR",
5044 SPR_NOACCESS, SPR_NOACCESS,
5045 &spr_read_generic, &spr_write_generic,
5046 0x00000000);
5047 /* Time base */
5048 gen_tbl(env);
5049 /* Thermal management */
5050 /* Those registers are fake on 750CL */
5051 spr_register(env, SPR_THRM1, "THRM1",
5052 SPR_NOACCESS, SPR_NOACCESS,
5053 &spr_read_generic, &spr_write_generic,
5054 0x00000000);
5055 spr_register(env, SPR_THRM2, "THRM2",
5056 SPR_NOACCESS, SPR_NOACCESS,
5057 &spr_read_generic, &spr_write_generic,
5058 0x00000000);
5059 spr_register(env, SPR_THRM3, "THRM3",
5060 SPR_NOACCESS, SPR_NOACCESS,
5061 &spr_read_generic, &spr_write_generic,
5062 0x00000000);
5063 /* XXX: not implemented */
5064 spr_register(env, SPR_750_TDCL, "TDCL",
5065 SPR_NOACCESS, SPR_NOACCESS,
5066 &spr_read_generic, &spr_write_generic,
5067 0x00000000);
5068 spr_register(env, SPR_750_TDCH, "TDCH",
5069 SPR_NOACCESS, SPR_NOACCESS,
5070 &spr_read_generic, &spr_write_generic,
5071 0x00000000);
5072 /* DMA */
5073 /* XXX : not implemented */
5074 spr_register(env, SPR_750_WPAR, "WPAR",
5075 SPR_NOACCESS, SPR_NOACCESS,
5076 &spr_read_generic, &spr_write_generic,
5077 0x00000000);
5078 spr_register(env, SPR_750_DMAL, "DMAL",
5079 SPR_NOACCESS, SPR_NOACCESS,
5080 &spr_read_generic, &spr_write_generic,
5081 0x00000000);
5082 spr_register(env, SPR_750_DMAU, "DMAU",
5083 SPR_NOACCESS, SPR_NOACCESS,
5084 &spr_read_generic, &spr_write_generic,
5085 0x00000000);
5086 /* Hardware implementation registers */
5087 /* XXX : not implemented */
5088 spr_register(env, SPR_HID0, "HID0",
5089 SPR_NOACCESS, SPR_NOACCESS,
5090 &spr_read_generic, &spr_write_generic,
5091 0x00000000);
5092 /* XXX : not implemented */
5093 spr_register(env, SPR_HID1, "HID1",
5094 SPR_NOACCESS, SPR_NOACCESS,
5095 &spr_read_generic, &spr_write_generic,
5096 0x00000000);
5097 /* XXX : not implemented */
5098 spr_register(env, SPR_750CL_HID2, "HID2",
5099 SPR_NOACCESS, SPR_NOACCESS,
5100 &spr_read_generic, &spr_write_generic,
5101 0x00000000);
5102 /* XXX : not implemented */
5103 spr_register(env, SPR_750CL_HID4, "HID4",
5104 SPR_NOACCESS, SPR_NOACCESS,
5105 &spr_read_generic, &spr_write_generic,
5106 0x00000000);
5107 /* Quantization registers */
5108 /* XXX : not implemented */
5109 spr_register(env, SPR_750_GQR0, "GQR0",
5110 SPR_NOACCESS, SPR_NOACCESS,
5111 &spr_read_generic, &spr_write_generic,
5112 0x00000000);
5113 /* XXX : not implemented */
5114 spr_register(env, SPR_750_GQR1, "GQR1",
5115 SPR_NOACCESS, SPR_NOACCESS,
5116 &spr_read_generic, &spr_write_generic,
5117 0x00000000);
5118 /* XXX : not implemented */
5119 spr_register(env, SPR_750_GQR2, "GQR2",
5120 SPR_NOACCESS, SPR_NOACCESS,
5121 &spr_read_generic, &spr_write_generic,
5122 0x00000000);
5123 /* XXX : not implemented */
5124 spr_register(env, SPR_750_GQR3, "GQR3",
5125 SPR_NOACCESS, SPR_NOACCESS,
5126 &spr_read_generic, &spr_write_generic,
5127 0x00000000);
5128 /* XXX : not implemented */
5129 spr_register(env, SPR_750_GQR4, "GQR4",
5130 SPR_NOACCESS, SPR_NOACCESS,
5131 &spr_read_generic, &spr_write_generic,
5132 0x00000000);
5133 /* XXX : not implemented */
5134 spr_register(env, SPR_750_GQR5, "GQR5",
5135 SPR_NOACCESS, SPR_NOACCESS,
5136 &spr_read_generic, &spr_write_generic,
5137 0x00000000);
5138 /* XXX : not implemented */
5139 spr_register(env, SPR_750_GQR6, "GQR6",
5140 SPR_NOACCESS, SPR_NOACCESS,
5141 &spr_read_generic, &spr_write_generic,
5142 0x00000000);
5143 /* XXX : not implemented */
5144 spr_register(env, SPR_750_GQR7, "GQR7",
5145 SPR_NOACCESS, SPR_NOACCESS,
5146 &spr_read_generic, &spr_write_generic,
5147 0x00000000);
5148 /* Memory management */
5149 gen_low_BATs(env);
5150 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5151 gen_high_BATs(env);
5152 init_excp_750cl(env);
5153 env->dcache_line_size = 32;
5154 env->icache_line_size = 32;
5155 /* Allocate hardware IRQ controller */
5156 ppc6xx_irq_init(env);
5157 }
5158
5159 /* PowerPC 750CX */
5160 #define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5161 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5162 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5163 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5164 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5165 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5166 PPC_SEGMENT | PPC_EXTERN)
5167 #define POWERPC_INSNS2_750cx (PPC_NONE)
5168 #define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
5169 #define POWERPC_MMU_750cx (POWERPC_MMU_32B)
5170 #define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
5171 #define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
5172 #define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
5173 #define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5174 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5175 #define check_pow_750cx check_pow_hid0
5176
5177 static void init_proc_750cx (CPUPPCState *env)
5178 {
5179 gen_spr_ne_601(env);
5180 gen_spr_7xx(env);
5181 /* XXX : not implemented */
5182 spr_register(env, SPR_L2CR, "L2CR",
5183 SPR_NOACCESS, SPR_NOACCESS,
5184 &spr_read_generic, &spr_write_generic,
5185 0x00000000);
5186 /* Time base */
5187 gen_tbl(env);
5188 /* Thermal management */
5189 gen_spr_thrm(env);
5190 /* This register is not implemented but is present for compatibility */
5191 spr_register(env, SPR_SDA, "SDA",
5192 SPR_NOACCESS, SPR_NOACCESS,
5193 &spr_read_generic, &spr_write_generic,
5194 0x00000000);
5195 /* Hardware implementation registers */
5196 /* XXX : not implemented */
5197 spr_register(env, SPR_HID0, "HID0",
5198 SPR_NOACCESS, SPR_NOACCESS,
5199 &spr_read_generic, &spr_write_generic,
5200 0x00000000);
5201 /* XXX : not implemented */
5202 spr_register(env, SPR_HID1, "HID1",
5203 SPR_NOACCESS, SPR_NOACCESS,
5204 &spr_read_generic, &spr_write_generic,
5205 0x00000000);
5206 /* Memory management */
5207 gen_low_BATs(env);
5208 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5209 gen_high_BATs(env);
5210 init_excp_750cx(env);
5211 env->dcache_line_size = 32;
5212 env->icache_line_size = 32;
5213 /* Allocate hardware IRQ controller */
5214 ppc6xx_irq_init(env);
5215 }
5216
5217 /* PowerPC 750FX */
5218 #define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5219 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5220 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5221 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5222 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5223 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5224 PPC_SEGMENT | PPC_EXTERN)
5225 #define POWERPC_INSNS2_750fx (PPC_NONE)
5226 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
5227 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
5228 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
5229 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
5230 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
5231 #define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5232 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5233 #define check_pow_750fx check_pow_hid0
5234
5235 static void init_proc_750fx (CPUPPCState *env)
5236 {
5237 gen_spr_ne_601(env);
5238 gen_spr_7xx(env);
5239 /* XXX : not implemented */
5240 spr_register(env, SPR_L2CR, "L2CR",
5241 SPR_NOACCESS, SPR_NOACCESS,
5242 &spr_read_generic, &spr_write_generic,
5243 0x00000000);
5244 /* Time base */
5245 gen_tbl(env);
5246 /* Thermal management */
5247 gen_spr_thrm(env);
5248 /* XXX : not implemented */
5249 spr_register(env, SPR_750_THRM4, "THRM4",
5250 SPR_NOACCESS, SPR_NOACCESS,
5251 &spr_read_generic, &spr_write_generic,
5252 0x00000000);
5253 /* Hardware implementation registers */
5254 /* XXX : not implemented */
5255 spr_register(env, SPR_HID0, "HID0",
5256 SPR_NOACCESS, SPR_NOACCESS,
5257 &spr_read_generic, &spr_write_generic,
5258 0x00000000);
5259 /* XXX : not implemented */
5260 spr_register(env, SPR_HID1, "HID1",
5261 SPR_NOACCESS, SPR_NOACCESS,
5262 &spr_read_generic, &spr_write_generic,
5263 0x00000000);
5264 /* XXX : not implemented */
5265 spr_register(env, SPR_750FX_HID2, "HID2",
5266 SPR_NOACCESS, SPR_NOACCESS,
5267 &spr_read_generic, &spr_write_generic,
5268 0x00000000);
5269 /* Memory management */
5270 gen_low_BATs(env);
5271 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5272 gen_high_BATs(env);
5273 init_excp_7x0(env);
5274 env->dcache_line_size = 32;
5275 env->icache_line_size = 32;
5276 /* Allocate hardware IRQ controller */
5277 ppc6xx_irq_init(env);
5278 }
5279
5280 /* PowerPC 750GX */
5281 #define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5282 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5283 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5284 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5285 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5286 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5287 PPC_SEGMENT | PPC_EXTERN)
5288 #define POWERPC_INSNS2_750gx (PPC_NONE)
5289 #define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5290 #define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5291 #define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5292 #define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5293 #define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5294 #define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5295 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5296 #define check_pow_750gx check_pow_hid0
5297
5298 static void init_proc_750gx (CPUPPCState *env)
5299 {
5300 gen_spr_ne_601(env);
5301 gen_spr_7xx(env);
5302 /* XXX : not implemented (XXX: different from 750fx) */
5303 spr_register(env, SPR_L2CR, "L2CR",
5304 SPR_NOACCESS, SPR_NOACCESS,
5305 &spr_read_generic, &spr_write_generic,
5306 0x00000000);
5307 /* Time base */
5308 gen_tbl(env);
5309 /* Thermal management */
5310 gen_spr_thrm(env);
5311 /* XXX : not implemented */
5312 spr_register(env, SPR_750_THRM4, "THRM4",
5313 SPR_NOACCESS, SPR_NOACCESS,
5314 &spr_read_generic, &spr_write_generic,
5315 0x00000000);
5316 /* Hardware implementation registers */
5317 /* XXX : not implemented (XXX: different from 750fx) */
5318 spr_register(env, SPR_HID0, "HID0",
5319 SPR_NOACCESS, SPR_NOACCESS,
5320 &spr_read_generic, &spr_write_generic,
5321 0x00000000);
5322 /* XXX : not implemented */
5323 spr_register(env, SPR_HID1, "HID1",
5324 SPR_NOACCESS, SPR_NOACCESS,
5325 &spr_read_generic, &spr_write_generic,
5326 0x00000000);
5327 /* XXX : not implemented (XXX: different from 750fx) */
5328 spr_register(env, SPR_750FX_HID2, "HID2",
5329 SPR_NOACCESS, SPR_NOACCESS,
5330 &spr_read_generic, &spr_write_generic,
5331 0x00000000);
5332 /* Memory management */
5333 gen_low_BATs(env);
5334 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5335 gen_high_BATs(env);
5336 init_excp_7x0(env);
5337 env->dcache_line_size = 32;
5338 env->icache_line_size = 32;
5339 /* Allocate hardware IRQ controller */
5340 ppc6xx_irq_init(env);
5341 }
5342
5343 /* PowerPC 745 */
5344 #define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5345 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5346 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5347 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5348 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5349 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5350 PPC_SEGMENT | PPC_EXTERN)
5351 #define POWERPC_INSNS2_745 (PPC_NONE)
5352 #define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5353 #define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5354 #define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5355 #define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5356 #define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5357 #define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5358 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5359 #define check_pow_745 check_pow_hid0
5360
5361 static void init_proc_745 (CPUPPCState *env)
5362 {
5363 gen_spr_ne_601(env);
5364 gen_spr_7xx(env);
5365 gen_spr_G2_755(env);
5366 /* Time base */
5367 gen_tbl(env);
5368 /* Thermal management */
5369 gen_spr_thrm(env);
5370 /* Hardware implementation registers */
5371 /* XXX : not implemented */
5372 spr_register(env, SPR_HID0, "HID0",
5373 SPR_NOACCESS, SPR_NOACCESS,
5374 &spr_read_generic, &spr_write_generic,
5375 0x00000000);
5376 /* XXX : not implemented */
5377 spr_register(env, SPR_HID1, "HID1",
5378 SPR_NOACCESS, SPR_NOACCESS,
5379 &spr_read_generic, &spr_write_generic,
5380 0x00000000);
5381 /* XXX : not implemented */
5382 spr_register(env, SPR_HID2, "HID2",
5383 SPR_NOACCESS, SPR_NOACCESS,
5384 &spr_read_generic, &spr_write_generic,
5385 0x00000000);
5386 /* Memory management */
5387 gen_low_BATs(env);
5388 gen_high_BATs(env);
5389 gen_6xx_7xx_soft_tlb(env, 64, 2);
5390 init_excp_7x5(env);
5391 env->dcache_line_size = 32;
5392 env->icache_line_size = 32;
5393 /* Allocate hardware IRQ controller */
5394 ppc6xx_irq_init(env);
5395 }
5396
5397 /* PowerPC 755 */
5398 #define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5399 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5400 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5401 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5402 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5403 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5404 PPC_SEGMENT | PPC_EXTERN)
5405 #define POWERPC_INSNS2_755 (PPC_NONE)
5406 #define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5407 #define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5408 #define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5409 #define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5410 #define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5411 #define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5412 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5413 #define check_pow_755 check_pow_hid0
5414
5415 static void init_proc_755 (CPUPPCState *env)
5416 {
5417 gen_spr_ne_601(env);
5418 gen_spr_7xx(env);
5419 gen_spr_G2_755(env);
5420 /* Time base */
5421 gen_tbl(env);
5422 /* L2 cache control */
5423 /* XXX : not implemented */
5424 spr_register(env, SPR_L2CR, "L2CR",
5425 SPR_NOACCESS, SPR_NOACCESS,
5426 &spr_read_generic, &spr_write_generic,
5427 0x00000000);
5428 /* XXX : not implemented */
5429 spr_register(env, SPR_L2PMCR, "L2PMCR",
5430 SPR_NOACCESS, SPR_NOACCESS,
5431 &spr_read_generic, &spr_write_generic,
5432 0x00000000);
5433 /* Thermal management */
5434 gen_spr_thrm(env);
5435 /* Hardware implementation registers */
5436 /* XXX : not implemented */
5437 spr_register(env, SPR_HID0, "HID0",
5438 SPR_NOACCESS, SPR_NOACCESS,
5439 &spr_read_generic, &spr_write_generic,
5440 0x00000000);
5441 /* XXX : not implemented */
5442 spr_register(env, SPR_HID1, "HID1",
5443 SPR_NOACCESS, SPR_NOACCESS,
5444 &spr_read_generic, &spr_write_generic,
5445 0x00000000);
5446 /* XXX : not implemented */
5447 spr_register(env, SPR_HID2, "HID2",
5448 SPR_NOACCESS, SPR_NOACCESS,
5449 &spr_read_generic, &spr_write_generic,
5450 0x00000000);
5451 /* Memory management */
5452 gen_low_BATs(env);
5453 gen_high_BATs(env);
5454 gen_6xx_7xx_soft_tlb(env, 64, 2);
5455 init_excp_7x5(env);
5456 env->dcache_line_size = 32;
5457 env->icache_line_size = 32;
5458 /* Allocate hardware IRQ controller */
5459 ppc6xx_irq_init(env);
5460 }
5461
5462 /* PowerPC 7400 (aka G4) */
5463 #define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5464 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5465 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5466 PPC_FLOAT_STFIWX | \
5467 PPC_CACHE | PPC_CACHE_ICBI | \
5468 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5469 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5470 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5471 PPC_MEM_TLBIA | \
5472 PPC_SEGMENT | PPC_EXTERN | \
5473 PPC_ALTIVEC)
5474 #define POWERPC_INSNS2_7400 (PPC_NONE)
5475 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5476 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5477 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5478 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
5479 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
5480 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5481 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5482 POWERPC_FLAG_BUS_CLK)
5483 #define check_pow_7400 check_pow_hid0
5484
5485 static void init_proc_7400 (CPUPPCState *env)
5486 {
5487 gen_spr_ne_601(env);
5488 gen_spr_7xx(env);
5489 /* Time base */
5490 gen_tbl(env);
5491 /* 74xx specific SPR */
5492 gen_spr_74xx(env);
5493 /* XXX : not implemented */
5494 spr_register(env, SPR_UBAMR, "UBAMR",
5495 &spr_read_ureg, SPR_NOACCESS,
5496 &spr_read_ureg, SPR_NOACCESS,
5497 0x00000000);
5498 /* XXX: this seems not implemented on all revisions. */
5499 /* XXX : not implemented */
5500 spr_register(env, SPR_MSSCR1, "MSSCR1",
5501 SPR_NOACCESS, SPR_NOACCESS,
5502 &spr_read_generic, &spr_write_generic,
5503 0x00000000);
5504 /* Thermal management */
5505 gen_spr_thrm(env);
5506 /* Memory management */
5507 gen_low_BATs(env);
5508 init_excp_7400(env);
5509 env->dcache_line_size = 32;
5510 env->icache_line_size = 32;
5511 /* Allocate hardware IRQ controller */
5512 ppc6xx_irq_init(env);
5513 }
5514
5515 /* PowerPC 7410 (aka G4) */
5516 #define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5517 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5518 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5519 PPC_FLOAT_STFIWX | \
5520 PPC_CACHE | PPC_CACHE_ICBI | \
5521 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5522 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5523 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5524 PPC_MEM_TLBIA | \
5525 PPC_SEGMENT | PPC_EXTERN | \
5526 PPC_ALTIVEC)
5527 #define POWERPC_INSNS2_7410 (PPC_NONE)
5528 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5529 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5530 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5531 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
5532 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
5533 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5534 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5535 POWERPC_FLAG_BUS_CLK)
5536 #define check_pow_7410 check_pow_hid0
5537
5538 static void init_proc_7410 (CPUPPCState *env)
5539 {
5540 gen_spr_ne_601(env);
5541 gen_spr_7xx(env);
5542 /* Time base */
5543 gen_tbl(env);
5544 /* 74xx specific SPR */
5545 gen_spr_74xx(env);
5546 /* XXX : not implemented */
5547 spr_register(env, SPR_UBAMR, "UBAMR",
5548 &spr_read_ureg, SPR_NOACCESS,
5549 &spr_read_ureg, SPR_NOACCESS,
5550 0x00000000);
5551 /* Thermal management */
5552 gen_spr_thrm(env);
5553 /* L2PMCR */
5554 /* XXX : not implemented */
5555 spr_register(env, SPR_L2PMCR, "L2PMCR",
5556 SPR_NOACCESS, SPR_NOACCESS,
5557 &spr_read_generic, &spr_write_generic,
5558 0x00000000);
5559 /* LDSTDB */
5560 /* XXX : not implemented */
5561 spr_register(env, SPR_LDSTDB, "LDSTDB",
5562 SPR_NOACCESS, SPR_NOACCESS,
5563 &spr_read_generic, &spr_write_generic,
5564 0x00000000);
5565 /* Memory management */
5566 gen_low_BATs(env);
5567 init_excp_7400(env);
5568 env->dcache_line_size = 32;
5569 env->icache_line_size = 32;
5570 /* Allocate hardware IRQ controller */
5571 ppc6xx_irq_init(env);
5572 }
5573
5574 /* PowerPC 7440 (aka G4) */
5575 #define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5576 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5577 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5578 PPC_FLOAT_STFIWX | \
5579 PPC_CACHE | PPC_CACHE_ICBI | \
5580 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5581 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5582 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5583 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5584 PPC_SEGMENT | PPC_EXTERN | \
5585 PPC_ALTIVEC)
5586 #define POWERPC_INSNS2_7440 (PPC_NONE)
5587 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5588 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5589 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5590 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
5591 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
5592 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5593 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5594 POWERPC_FLAG_BUS_CLK)
5595 #define check_pow_7440 check_pow_hid0_74xx
5596
5597 __attribute__ (( unused ))
5598 static void init_proc_7440 (CPUPPCState *env)
5599 {
5600 gen_spr_ne_601(env);
5601 gen_spr_7xx(env);
5602 /* Time base */
5603 gen_tbl(env);
5604 /* 74xx specific SPR */
5605 gen_spr_74xx(env);
5606 /* XXX : not implemented */
5607 spr_register(env, SPR_UBAMR, "UBAMR",
5608 &spr_read_ureg, SPR_NOACCESS,
5609 &spr_read_ureg, SPR_NOACCESS,
5610 0x00000000);
5611 /* LDSTCR */
5612 /* XXX : not implemented */
5613 spr_register(env, SPR_LDSTCR, "LDSTCR",
5614 SPR_NOACCESS, SPR_NOACCESS,
5615 &spr_read_generic, &spr_write_generic,
5616 0x00000000);
5617 /* ICTRL */
5618 /* XXX : not implemented */
5619 spr_register(env, SPR_ICTRL, "ICTRL",
5620 SPR_NOACCESS, SPR_NOACCESS,
5621 &spr_read_generic, &spr_write_generic,
5622 0x00000000);
5623 /* MSSSR0 */
5624 /* XXX : not implemented */
5625 spr_register(env, SPR_MSSSR0, "MSSSR0",
5626 SPR_NOACCESS, SPR_NOACCESS,
5627 &spr_read_generic, &spr_write_generic,
5628 0x00000000);
5629 /* PMC */
5630 /* XXX : not implemented */
5631 spr_register(env, SPR_PMC5, "PMC5",
5632 SPR_NOACCESS, SPR_NOACCESS,
5633 &spr_read_generic, &spr_write_generic,
5634 0x00000000);
5635 /* XXX : not implemented */
5636 spr_register(env, SPR_UPMC5, "UPMC5",
5637 &spr_read_ureg, SPR_NOACCESS,
5638 &spr_read_ureg, SPR_NOACCESS,
5639 0x00000000);
5640 /* XXX : not implemented */
5641 spr_register(env, SPR_PMC6, "PMC6",
5642 SPR_NOACCESS, SPR_NOACCESS,
5643 &spr_read_generic, &spr_write_generic,
5644 0x00000000);
5645 /* XXX : not implemented */
5646 spr_register(env, SPR_UPMC6, "UPMC6",
5647 &spr_read_ureg, SPR_NOACCESS,
5648 &spr_read_ureg, SPR_NOACCESS,
5649 0x00000000);
5650 /* Memory management */
5651 gen_low_BATs(env);
5652 gen_74xx_soft_tlb(env, 128, 2);
5653 init_excp_7450(env);
5654 env->dcache_line_size = 32;
5655 env->icache_line_size = 32;
5656 /* Allocate hardware IRQ controller */
5657 ppc6xx_irq_init(env);
5658 }
5659
5660 /* PowerPC 7450 (aka G4) */
5661 #define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5662 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5663 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5664 PPC_FLOAT_STFIWX | \
5665 PPC_CACHE | PPC_CACHE_ICBI | \
5666 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5667 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5668 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5669 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5670 PPC_SEGMENT | PPC_EXTERN | \
5671 PPC_ALTIVEC)
5672 #define POWERPC_INSNS2_7450 (PPC_NONE)
5673 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5674 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5675 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5676 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
5677 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
5678 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5679 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5680 POWERPC_FLAG_BUS_CLK)
5681 #define check_pow_7450 check_pow_hid0_74xx
5682
5683 __attribute__ (( unused ))
5684 static void init_proc_7450 (CPUPPCState *env)
5685 {
5686 gen_spr_ne_601(env);
5687 gen_spr_7xx(env);
5688 /* Time base */
5689 gen_tbl(env);
5690 /* 74xx specific SPR */
5691 gen_spr_74xx(env);
5692 /* Level 3 cache control */
5693 gen_l3_ctrl(env);
5694 /* L3ITCR1 */
5695 /* XXX : not implemented */
5696 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5697 SPR_NOACCESS, SPR_NOACCESS,
5698 &spr_read_generic, &spr_write_generic,
5699 0x00000000);
5700 /* L3ITCR2 */
5701 /* XXX : not implemented */
5702 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5703 SPR_NOACCESS, SPR_NOACCESS,
5704 &spr_read_generic, &spr_write_generic,
5705 0x00000000);
5706 /* L3ITCR3 */
5707 /* XXX : not implemented */
5708 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5709 SPR_NOACCESS, SPR_NOACCESS,
5710 &spr_read_generic, &spr_write_generic,
5711 0x00000000);
5712 /* L3OHCR */
5713 /* XXX : not implemented */
5714 spr_register(env, SPR_L3OHCR, "L3OHCR",
5715 SPR_NOACCESS, SPR_NOACCESS,
5716 &spr_read_generic, &spr_write_generic,
5717 0x00000000);
5718 /* XXX : not implemented */
5719 spr_register(env, SPR_UBAMR, "UBAMR",
5720 &spr_read_ureg, SPR_NOACCESS,
5721 &spr_read_ureg, SPR_NOACCESS,
5722 0x00000000);
5723 /* LDSTCR */
5724 /* XXX : not implemented */
5725 spr_register(env, SPR_LDSTCR, "LDSTCR",
5726 SPR_NOACCESS, SPR_NOACCESS,
5727 &spr_read_generic, &spr_write_generic,
5728 0x00000000);
5729 /* ICTRL */
5730 /* XXX : not implemented */
5731 spr_register(env, SPR_ICTRL, "ICTRL",
5732 SPR_NOACCESS, SPR_NOACCESS,
5733 &spr_read_generic, &spr_write_generic,
5734 0x00000000);
5735 /* MSSSR0 */
5736 /* XXX : not implemented */
5737 spr_register(env, SPR_MSSSR0, "MSSSR0",
5738 SPR_NOACCESS, SPR_NOACCESS,
5739 &spr_read_generic, &spr_write_generic,
5740 0x00000000);
5741 /* PMC */
5742 /* XXX : not implemented */
5743 spr_register(env, SPR_PMC5, "PMC5",
5744 SPR_NOACCESS, SPR_NOACCESS,
5745 &spr_read_generic, &spr_write_generic,
5746 0x00000000);
5747 /* XXX : not implemented */
5748 spr_register(env, SPR_UPMC5, "UPMC5",
5749 &spr_read_ureg, SPR_NOACCESS,
5750 &spr_read_ureg, SPR_NOACCESS,
5751 0x00000000);
5752 /* XXX : not implemented */
5753 spr_register(env, SPR_PMC6, "PMC6",
5754 SPR_NOACCESS, SPR_NOACCESS,
5755 &spr_read_generic, &spr_write_generic,
5756 0x00000000);
5757 /* XXX : not implemented */
5758 spr_register(env, SPR_UPMC6, "UPMC6",
5759 &spr_read_ureg, SPR_NOACCESS,
5760 &spr_read_ureg, SPR_NOACCESS,
5761 0x00000000);
5762 /* Memory management */
5763 gen_low_BATs(env);
5764 gen_74xx_soft_tlb(env, 128, 2);
5765 init_excp_7450(env);
5766 env->dcache_line_size = 32;
5767 env->icache_line_size = 32;
5768 /* Allocate hardware IRQ controller */
5769 ppc6xx_irq_init(env);
5770 }
5771
5772 /* PowerPC 7445 (aka G4) */
5773 #define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5774 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5775 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5776 PPC_FLOAT_STFIWX | \
5777 PPC_CACHE | PPC_CACHE_ICBI | \
5778 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5779 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5780 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5781 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5782 PPC_SEGMENT | PPC_EXTERN | \
5783 PPC_ALTIVEC)
5784 #define POWERPC_INSNS2_7445 (PPC_NONE)
5785 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5786 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5787 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5788 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
5789 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
5790 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5791 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5792 POWERPC_FLAG_BUS_CLK)
5793 #define check_pow_7445 check_pow_hid0_74xx
5794
5795 __attribute__ (( unused ))
5796 static void init_proc_7445 (CPUPPCState *env)
5797 {
5798 gen_spr_ne_601(env);
5799 gen_spr_7xx(env);
5800 /* Time base */
5801 gen_tbl(env);
5802 /* 74xx specific SPR */
5803 gen_spr_74xx(env);
5804 /* LDSTCR */
5805 /* XXX : not implemented */
5806 spr_register(env, SPR_LDSTCR, "LDSTCR",
5807 SPR_NOACCESS, SPR_NOACCESS,
5808 &spr_read_generic, &spr_write_generic,
5809 0x00000000);
5810 /* ICTRL */
5811 /* XXX : not implemented */
5812 spr_register(env, SPR_ICTRL, "ICTRL",
5813 SPR_NOACCESS, SPR_NOACCESS,
5814 &spr_read_generic, &spr_write_generic,
5815 0x00000000);
5816 /* MSSSR0 */
5817 /* XXX : not implemented */
5818 spr_register(env, SPR_MSSSR0, "MSSSR0",
5819 SPR_NOACCESS, SPR_NOACCESS,
5820 &spr_read_generic, &spr_write_generic,
5821 0x00000000);
5822 /* PMC */
5823 /* XXX : not implemented */
5824 spr_register(env, SPR_PMC5, "PMC5",
5825 SPR_NOACCESS, SPR_NOACCESS,
5826 &spr_read_generic, &spr_write_generic,
5827 0x00000000);
5828 /* XXX : not implemented */
5829 spr_register(env, SPR_UPMC5, "UPMC5",
5830 &spr_read_ureg, SPR_NOACCESS,
5831 &spr_read_ureg, SPR_NOACCESS,
5832 0x00000000);
5833 /* XXX : not implemented */
5834 spr_register(env, SPR_PMC6, "PMC6",
5835 SPR_NOACCESS, SPR_NOACCESS,
5836 &spr_read_generic, &spr_write_generic,
5837 0x00000000);
5838 /* XXX : not implemented */
5839 spr_register(env, SPR_UPMC6, "UPMC6",
5840 &spr_read_ureg, SPR_NOACCESS,
5841 &spr_read_ureg, SPR_NOACCESS,
5842 0x00000000);
5843 /* SPRGs */
5844 spr_register(env, SPR_SPRG4, "SPRG4",
5845 SPR_NOACCESS, SPR_NOACCESS,
5846 &spr_read_generic, &spr_write_generic,
5847 0x00000000);
5848 spr_register(env, SPR_USPRG4, "USPRG4",
5849 &spr_read_ureg, SPR_NOACCESS,
5850 &spr_read_ureg, SPR_NOACCESS,
5851 0x00000000);
5852 spr_register(env, SPR_SPRG5, "SPRG5",
5853 SPR_NOACCESS, SPR_NOACCESS,
5854 &spr_read_generic, &spr_write_generic,
5855 0x00000000);
5856 spr_register(env, SPR_USPRG5, "USPRG5",
5857 &spr_read_ureg, SPR_NOACCESS,
5858 &spr_read_ureg, SPR_NOACCESS,
5859 0x00000000);
5860 spr_register(env, SPR_SPRG6, "SPRG6",
5861 SPR_NOACCESS, SPR_NOACCESS,
5862 &spr_read_generic, &spr_write_generic,
5863 0x00000000);
5864 spr_register(env, SPR_USPRG6, "USPRG6",
5865 &spr_read_ureg, SPR_NOACCESS,
5866 &spr_read_ureg, SPR_NOACCESS,
5867 0x00000000);
5868 spr_register(env, SPR_SPRG7, "SPRG7",
5869 SPR_NOACCESS, SPR_NOACCESS,
5870 &spr_read_generic, &spr_write_generic,
5871 0x00000000);
5872 spr_register(env, SPR_USPRG7, "USPRG7",
5873 &spr_read_ureg, SPR_NOACCESS,
5874 &spr_read_ureg, SPR_NOACCESS,
5875 0x00000000);
5876 /* Memory management */
5877 gen_low_BATs(env);
5878 gen_high_BATs(env);
5879 gen_74xx_soft_tlb(env, 128, 2);
5880 init_excp_7450(env);
5881 env->dcache_line_size = 32;
5882 env->icache_line_size = 32;
5883 /* Allocate hardware IRQ controller */
5884 ppc6xx_irq_init(env);
5885 }
5886
5887 /* PowerPC 7455 (aka G4) */
5888 #define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5889 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5890 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5891 PPC_FLOAT_STFIWX | \
5892 PPC_CACHE | PPC_CACHE_ICBI | \
5893 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5894 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5895 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5896 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5897 PPC_SEGMENT | PPC_EXTERN | \
5898 PPC_ALTIVEC)
5899 #define POWERPC_INSNS2_7455 (PPC_NONE)
5900 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
5901 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
5902 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
5903 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
5904 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
5905 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5906 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5907 POWERPC_FLAG_BUS_CLK)
5908 #define check_pow_7455 check_pow_hid0_74xx
5909
5910 __attribute__ (( unused ))
5911 static void init_proc_7455 (CPUPPCState *env)
5912 {
5913 gen_spr_ne_601(env);
5914 gen_spr_7xx(env);
5915 /* Time base */
5916 gen_tbl(env);
5917 /* 74xx specific SPR */
5918 gen_spr_74xx(env);
5919 /* Level 3 cache control */
5920 gen_l3_ctrl(env);
5921 /* LDSTCR */
5922 /* XXX : not implemented */
5923 spr_register(env, SPR_LDSTCR, "LDSTCR",
5924 SPR_NOACCESS, SPR_NOACCESS,
5925 &spr_read_generic, &spr_write_generic,
5926 0x00000000);
5927 /* ICTRL */
5928 /* XXX : not implemented */
5929 spr_register(env, SPR_ICTRL, "ICTRL",
5930 SPR_NOACCESS, SPR_NOACCESS,
5931 &spr_read_generic, &spr_write_generic,
5932 0x00000000);
5933 /* MSSSR0 */
5934 /* XXX : not implemented */
5935 spr_register(env, SPR_MSSSR0, "MSSSR0",
5936 SPR_NOACCESS, SPR_NOACCESS,
5937 &spr_read_generic, &spr_write_generic,
5938 0x00000000);
5939 /* PMC */
5940 /* XXX : not implemented */
5941 spr_register(env, SPR_PMC5, "PMC5",
5942 SPR_NOACCESS, SPR_NOACCESS,
5943 &spr_read_generic, &spr_write_generic,
5944 0x00000000);
5945 /* XXX : not implemented */
5946 spr_register(env, SPR_UPMC5, "UPMC5",
5947 &spr_read_ureg, SPR_NOACCESS,
5948 &spr_read_ureg, SPR_NOACCESS,
5949 0x00000000);
5950 /* XXX : not implemented */
5951 spr_register(env, SPR_PMC6, "PMC6",
5952 SPR_NOACCESS, SPR_NOACCESS,
5953 &spr_read_generic, &spr_write_generic,
5954 0x00000000);
5955 /* XXX : not implemented */
5956 spr_register(env, SPR_UPMC6, "UPMC6",
5957 &spr_read_ureg, SPR_NOACCESS,
5958 &spr_read_ureg, SPR_NOACCESS,
5959 0x00000000);
5960 /* SPRGs */
5961 spr_register(env, SPR_SPRG4, "SPRG4",
5962 SPR_NOACCESS, SPR_NOACCESS,
5963 &spr_read_generic, &spr_write_generic,
5964 0x00000000);
5965 spr_register(env, SPR_USPRG4, "USPRG4",
5966 &spr_read_ureg, SPR_NOACCESS,
5967 &spr_read_ureg, SPR_NOACCESS,
5968 0x00000000);
5969 spr_register(env, SPR_SPRG5, "SPRG5",
5970 SPR_NOACCESS, SPR_NOACCESS,
5971 &spr_read_generic, &spr_write_generic,
5972 0x00000000);
5973 spr_register(env, SPR_USPRG5, "USPRG5",
5974 &spr_read_ureg, SPR_NOACCESS,
5975 &spr_read_ureg, SPR_NOACCESS,
5976 0x00000000);
5977 spr_register(env, SPR_SPRG6, "SPRG6",
5978 SPR_NOACCESS, SPR_NOACCESS,
5979 &spr_read_generic, &spr_write_generic,
5980 0x00000000);
5981 spr_register(env, SPR_USPRG6, "USPRG6",
5982 &spr_read_ureg, SPR_NOACCESS,
5983 &spr_read_ureg, SPR_NOACCESS,
5984 0x00000000);
5985 spr_register(env, SPR_SPRG7, "SPRG7",
5986 SPR_NOACCESS, SPR_NOACCESS,
5987 &spr_read_generic, &spr_write_generic,
5988 0x00000000);
5989 spr_register(env, SPR_USPRG7, "USPRG7",
5990 &spr_read_ureg, SPR_NOACCESS,
5991 &spr_read_ureg, SPR_NOACCESS,
5992 0x00000000);
5993 /* Memory management */
5994 gen_low_BATs(env);
5995 gen_high_BATs(env);
5996 gen_74xx_soft_tlb(env, 128, 2);
5997 init_excp_7450(env);
5998 env->dcache_line_size = 32;
5999 env->icache_line_size = 32;
6000 /* Allocate hardware IRQ controller */
6001 ppc6xx_irq_init(env);
6002 }
6003
6004 /* PowerPC 7457 (aka G4) */
6005 #define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6006 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6007 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6008 PPC_FLOAT_STFIWX | \
6009 PPC_CACHE | PPC_CACHE_ICBI | \
6010 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
6011 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6012 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6013 PPC_MEM_TLBIA | PPC_74xx_TLB | \
6014 PPC_SEGMENT | PPC_EXTERN | \
6015 PPC_ALTIVEC)
6016 #define POWERPC_INSNS2_7457 (PPC_NONE)
6017 #define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
6018 #define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
6019 #define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
6020 #define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
6021 #define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
6022 #define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6023 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6024 POWERPC_FLAG_BUS_CLK)
6025 #define check_pow_7457 check_pow_hid0_74xx
6026
6027 __attribute__ (( unused ))
6028 static void init_proc_7457 (CPUPPCState *env)
6029 {
6030 gen_spr_ne_601(env);
6031 gen_spr_7xx(env);
6032 /* Time base */
6033 gen_tbl(env);
6034 /* 74xx specific SPR */
6035 gen_spr_74xx(env);
6036 /* Level 3 cache control */
6037 gen_l3_ctrl(env);
6038 /* L3ITCR1 */
6039 /* XXX : not implemented */
6040 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6041 SPR_NOACCESS, SPR_NOACCESS,
6042 &spr_read_generic, &spr_write_generic,
6043 0x00000000);
6044 /* L3ITCR2 */
6045 /* XXX : not implemented */
6046 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6047 SPR_NOACCESS, SPR_NOACCESS,
6048 &spr_read_generic, &spr_write_generic,
6049 0x00000000);
6050 /* L3ITCR3 */
6051 /* XXX : not implemented */
6052 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6053 SPR_NOACCESS, SPR_NOACCESS,
6054 &spr_read_generic, &spr_write_generic,
6055 0x00000000);
6056 /* L3OHCR */
6057 /* XXX : not implemented */
6058 spr_register(env, SPR_L3OHCR, "L3OHCR",
6059 SPR_NOACCESS, SPR_NOACCESS,
6060 &spr_read_generic, &spr_write_generic,
6061 0x00000000);
6062 /* LDSTCR */
6063 /* XXX : not implemented */
6064 spr_register(env, SPR_LDSTCR, "LDSTCR",
6065 SPR_NOACCESS, SPR_NOACCESS,
6066 &spr_read_generic, &spr_write_generic,
6067 0x00000000);
6068 /* ICTRL */
6069 /* XXX : not implemented */
6070 spr_register(env, SPR_ICTRL, "ICTRL",
6071 SPR_NOACCESS, SPR_NOACCESS,
6072 &spr_read_generic, &spr_write_generic,
6073 0x00000000);
6074 /* MSSSR0 */
6075 /* XXX : not implemented */
6076 spr_register(env, SPR_MSSSR0, "MSSSR0",
6077 SPR_NOACCESS, SPR_NOACCESS,
6078 &spr_read_generic, &spr_write_generic,
6079 0x00000000);
6080 /* PMC */
6081 /* XXX : not implemented */
6082 spr_register(env, SPR_PMC5, "PMC5",
6083 SPR_NOACCESS, SPR_NOACCESS,
6084 &spr_read_generic, &spr_write_generic,
6085 0x00000000);
6086 /* XXX : not implemented */
6087 spr_register(env, SPR_UPMC5, "UPMC5",
6088 &spr_read_ureg, SPR_NOACCESS,
6089 &spr_read_ureg, SPR_NOACCESS,
6090 0x00000000);
6091 /* XXX : not implemented */
6092 spr_register(env, SPR_PMC6, "PMC6",
6093 SPR_NOACCESS, SPR_NOACCESS,
6094 &spr_read_generic, &spr_write_generic,
6095 0x00000000);
6096 /* XXX : not implemented */
6097 spr_register(env, SPR_UPMC6, "UPMC6",
6098 &spr_read_ureg, SPR_NOACCESS,
6099 &spr_read_ureg, SPR_NOACCESS,
6100 0x00000000);
6101 /* SPRGs */
6102 spr_register(env, SPR_SPRG4, "SPRG4",
6103 SPR_NOACCESS, SPR_NOACCESS,
6104 &spr_read_generic, &spr_write_generic,
6105 0x00000000);
6106 spr_register(env, SPR_USPRG4, "USPRG4",
6107 &spr_read_ureg, SPR_NOACCESS,
6108 &spr_read_ureg, SPR_NOACCESS,
6109 0x00000000);
6110 spr_register(env, SPR_SPRG5, "SPRG5",
6111 SPR_NOACCESS, SPR_NOACCESS,
6112 &spr_read_generic, &spr_write_generic,
6113 0x00000000);
6114 spr_register(env, SPR_USPRG5, "USPRG5",
6115 &spr_read_ureg, SPR_NOACCESS,
6116 &spr_read_ureg, SPR_NOACCESS,
6117 0x00000000);
6118 spr_register(env, SPR_SPRG6, "SPRG6",
6119 SPR_NOACCESS, SPR_NOACCESS,
6120 &spr_read_generic, &spr_write_generic,
6121 0x00000000);
6122 spr_register(env, SPR_USPRG6, "USPRG6",
6123 &spr_read_ureg, SPR_NOACCESS,
6124 &spr_read_ureg, SPR_NOACCESS,
6125 0x00000000);
6126 spr_register(env, SPR_SPRG7, "SPRG7",
6127 SPR_NOACCESS, SPR_NOACCESS,
6128 &spr_read_generic, &spr_write_generic,
6129 0x00000000);
6130 spr_register(env, SPR_USPRG7, "USPRG7",
6131 &spr_read_ureg, SPR_NOACCESS,
6132 &spr_read_ureg, SPR_NOACCESS,
6133 0x00000000);
6134 /* Memory management */
6135 gen_low_BATs(env);
6136 gen_high_BATs(env);
6137 gen_74xx_soft_tlb(env, 128, 2);
6138 init_excp_7450(env);
6139 env->dcache_line_size = 32;
6140 env->icache_line_size = 32;
6141 /* Allocate hardware IRQ controller */
6142 ppc6xx_irq_init(env);
6143 }
6144
6145 #if defined (TARGET_PPC64)
6146 /* PowerPC 970 */
6147 #define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6148 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6149 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6150 PPC_FLOAT_STFIWX | \
6151 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6152 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6153 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6154 PPC_64B | PPC_ALTIVEC | \
6155 PPC_SEGMENT_64B | PPC_SLBI)
6156 #define POWERPC_INSNS2_970 (PPC_NONE)
6157 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
6158 #define POWERPC_MMU_970 (POWERPC_MMU_64B)
6159 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
6160 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
6161 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
6162 #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6163 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6164 POWERPC_FLAG_BUS_CLK)
6165
6166 #if defined(CONFIG_USER_ONLY)
6167 #define POWERPC970_HID5_INIT 0x00000080
6168 #else
6169 #define POWERPC970_HID5_INIT 0x00000000
6170 #endif
6171
6172 static int check_pow_970 (CPUPPCState *env)
6173 {
6174 if (env->spr[SPR_HID0] & 0x00600000)
6175 return 1;
6176
6177 return 0;
6178 }
6179
6180 static void init_proc_970 (CPUPPCState *env)
6181 {
6182 gen_spr_ne_601(env);
6183 gen_spr_7xx(env);
6184 /* Time base */
6185 gen_tbl(env);
6186 /* Hardware implementation registers */
6187 /* XXX : not implemented */
6188 spr_register(env, SPR_HID0, "HID0",
6189 SPR_NOACCESS, SPR_NOACCESS,
6190 &spr_read_generic, &spr_write_clear,
6191 0x60000000);
6192 /* XXX : not implemented */
6193 spr_register(env, SPR_HID1, "HID1",
6194 SPR_NOACCESS, SPR_NOACCESS,
6195 &spr_read_generic, &spr_write_generic,
6196 0x00000000);
6197 /* XXX : not implemented */
6198 spr_register(env, SPR_750FX_HID2, "HID2",
6199 SPR_NOACCESS, SPR_NOACCESS,
6200 &spr_read_generic, &spr_write_generic,
6201 0x00000000);
6202 /* XXX : not implemented */
6203 spr_register(env, SPR_970_HID5, "HID5",
6204 SPR_NOACCESS, SPR_NOACCESS,
6205 &spr_read_generic, &spr_write_generic,
6206 POWERPC970_HID5_INIT);
6207 /* XXX : not implemented */
6208 spr_register(env, SPR_L2CR, "L2CR",
6209 SPR_NOACCESS, SPR_NOACCESS,
6210 &spr_read_generic, &spr_write_generic,
6211 0x00000000);
6212 /* Memory management */
6213 /* XXX: not correct */
6214 gen_low_BATs(env);
6215 /* XXX : not implemented */
6216 spr_register(env, SPR_MMUCFG, "MMUCFG",
6217 SPR_NOACCESS, SPR_NOACCESS,
6218 &spr_read_generic, SPR_NOACCESS,
6219 0x00000000); /* TOFIX */
6220 /* XXX : not implemented */
6221 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6222 SPR_NOACCESS, SPR_NOACCESS,
6223 &spr_read_generic, &spr_write_generic,
6224 0x00000000); /* TOFIX */
6225 spr_register(env, SPR_HIOR, "SPR_HIOR",
6226 SPR_NOACCESS, SPR_NOACCESS,
6227 &spr_read_hior, &spr_write_hior,
6228 0x00000000);
6229 #if !defined(CONFIG_USER_ONLY)
6230 env->slb_nr = 32;
6231 #endif
6232 init_excp_970(env);
6233 env->dcache_line_size = 128;
6234 env->icache_line_size = 128;
6235 /* Allocate hardware IRQ controller */
6236 ppc970_irq_init(env);
6237 /* Can't find information on what this should be on reset. This
6238 * value is the one used by 74xx processors. */
6239 vscr_init(env, 0x00010000);
6240 }
6241
6242 /* PowerPC 970FX (aka G5) */
6243 #define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6244 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6245 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6246 PPC_FLOAT_STFIWX | \
6247 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6248 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6249 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6250 PPC_64B | PPC_ALTIVEC | \
6251 PPC_SEGMENT_64B | PPC_SLBI)
6252 #define POWERPC_INSNS2_970FX (PPC_NONE)
6253 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
6254 #define POWERPC_MMU_970FX (POWERPC_MMU_64B)
6255 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
6256 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
6257 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
6258 #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6259 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6260 POWERPC_FLAG_BUS_CLK)
6261
6262 static int check_pow_970FX (CPUPPCState *env)
6263 {
6264 if (env->spr[SPR_HID0] & 0x00600000)
6265 return 1;
6266
6267 return 0;
6268 }
6269
6270 static void init_proc_970FX (CPUPPCState *env)
6271 {
6272 gen_spr_ne_601(env);
6273 gen_spr_7xx(env);
6274 /* Time base */
6275 gen_tbl(env);
6276 /* Hardware implementation registers */
6277 /* XXX : not implemented */
6278 spr_register(env, SPR_HID0, "HID0",
6279 SPR_NOACCESS, SPR_NOACCESS,
6280 &spr_read_generic, &spr_write_clear,
6281 0x60000000);
6282 /* XXX : not implemented */
6283 spr_register(env, SPR_HID1, "HID1",
6284 SPR_NOACCESS, SPR_NOACCESS,
6285 &spr_read_generic, &spr_write_generic,
6286 0x00000000);
6287 /* XXX : not implemented */
6288 spr_register(env, SPR_750FX_HID2, "HID2",
6289 SPR_NOACCESS, SPR_NOACCESS,
6290 &spr_read_generic, &spr_write_generic,
6291 0x00000000);
6292 /* XXX : not implemented */
6293 spr_register(env, SPR_970_HID5, "HID5",
6294 SPR_NOACCESS, SPR_NOACCESS,
6295 &spr_read_generic, &spr_write_generic,
6296 POWERPC970_HID5_INIT);
6297 /* XXX : not implemented */
6298 spr_register(env, SPR_L2CR, "L2CR",
6299 SPR_NOACCESS, SPR_NOACCESS,
6300 &spr_read_generic, &spr_write_generic,
6301 0x00000000);
6302 /* Memory management */
6303 /* XXX: not correct */
6304 gen_low_BATs(env);
6305 /* XXX : not implemented */
6306 spr_register(env, SPR_MMUCFG, "MMUCFG",
6307 SPR_NOACCESS, SPR_NOACCESS,
6308 &spr_read_generic, SPR_NOACCESS,
6309 0x00000000); /* TOFIX */
6310 /* XXX : not implemented */
6311 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6312 SPR_NOACCESS, SPR_NOACCESS,
6313 &spr_read_generic, &spr_write_generic,
6314 0x00000000); /* TOFIX */
6315 spr_register(env, SPR_HIOR, "SPR_HIOR",
6316 SPR_NOACCESS, SPR_NOACCESS,
6317 &spr_read_hior, &spr_write_hior,
6318 0x00000000);
6319 spr_register(env, SPR_CTRL, "SPR_CTRL",
6320 SPR_NOACCESS, SPR_NOACCESS,
6321 &spr_read_generic, &spr_write_generic,
6322 0x00000000);
6323 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6324 SPR_NOACCESS, SPR_NOACCESS,
6325 &spr_read_generic, &spr_write_generic,
6326 0x00000000);
6327 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6328 &spr_read_generic, &spr_write_generic,
6329 &spr_read_generic, &spr_write_generic,
6330 0x00000000);
6331 #if !defined(CONFIG_USER_ONLY)
6332 env->slb_nr = 64;
6333 #endif
6334 init_excp_970(env);
6335 env->dcache_line_size = 128;
6336 env->icache_line_size = 128;
6337 /* Allocate hardware IRQ controller */
6338 ppc970_irq_init(env);
6339 /* Can't find information on what this should be on reset. This
6340 * value is the one used by 74xx processors. */
6341 vscr_init(env, 0x00010000);
6342 }
6343
6344 /* PowerPC 970 GX */
6345 #define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6346 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6347 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6348 PPC_FLOAT_STFIWX | \
6349 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6350 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6351 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6352 PPC_64B | PPC_ALTIVEC | \
6353 PPC_SEGMENT_64B | PPC_SLBI)
6354 #define POWERPC_INSNS2_970GX (PPC_NONE)
6355 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
6356 #define POWERPC_MMU_970GX (POWERPC_MMU_64B)
6357 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6358 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
6359 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
6360 #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6361 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6362 POWERPC_FLAG_BUS_CLK)
6363
6364 static int check_pow_970GX (CPUPPCState *env)
6365 {
6366 if (env->spr[SPR_HID0] & 0x00600000)
6367 return 1;
6368
6369 return 0;
6370 }
6371
6372 static void init_proc_970GX (CPUPPCState *env)
6373 {
6374 gen_spr_ne_601(env);
6375 gen_spr_7xx(env);
6376 /* Time base */
6377 gen_tbl(env);
6378 /* Hardware implementation registers */
6379 /* XXX : not implemented */
6380 spr_register(env, SPR_HID0, "HID0",
6381 SPR_NOACCESS, SPR_NOACCESS,
6382 &spr_read_generic, &spr_write_clear,
6383 0x60000000);
6384 /* XXX : not implemented */
6385 spr_register(env, SPR_HID1, "HID1",
6386 SPR_NOACCESS, SPR_NOACCESS,
6387 &spr_read_generic, &spr_write_generic,
6388 0x00000000);
6389 /* XXX : not implemented */
6390 spr_register(env, SPR_750FX_HID2, "HID2",
6391 SPR_NOACCESS, SPR_NOACCESS,
6392 &spr_read_generic, &spr_write_generic,
6393 0x00000000);
6394 /* XXX : not implemented */
6395 spr_register(env, SPR_970_HID5, "HID5",
6396 SPR_NOACCESS, SPR_NOACCESS,
6397 &spr_read_generic, &spr_write_generic,
6398 POWERPC970_HID5_INIT);
6399 /* XXX : not implemented */
6400 spr_register(env, SPR_L2CR, "L2CR",
6401 SPR_NOACCESS, SPR_NOACCESS,
6402 &spr_read_generic, &spr_write_generic,
6403 0x00000000);
6404 /* Memory management */
6405 /* XXX: not correct */
6406 gen_low_BATs(env);
6407 /* XXX : not implemented */
6408 spr_register(env, SPR_MMUCFG, "MMUCFG",
6409 SPR_NOACCESS, SPR_NOACCESS,
6410 &spr_read_generic, SPR_NOACCESS,
6411 0x00000000); /* TOFIX */
6412 /* XXX : not implemented */
6413 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6414 SPR_NOACCESS, SPR_NOACCESS,
6415 &spr_read_generic, &spr_write_generic,
6416 0x00000000); /* TOFIX */
6417 spr_register(env, SPR_HIOR, "SPR_HIOR",
6418 SPR_NOACCESS, SPR_NOACCESS,
6419 &spr_read_hior, &spr_write_hior,
6420 0x00000000);
6421 #if !defined(CONFIG_USER_ONLY)
6422 env->slb_nr = 32;
6423 #endif
6424 init_excp_970(env);
6425 env->dcache_line_size = 128;
6426 env->icache_line_size = 128;
6427 /* Allocate hardware IRQ controller */
6428 ppc970_irq_init(env);
6429 /* Can't find information on what this should be on reset. This
6430 * value is the one used by 74xx processors. */
6431 vscr_init(env, 0x00010000);
6432 }
6433
6434 /* PowerPC 970 MP */
6435 #define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6436 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6437 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6438 PPC_FLOAT_STFIWX | \
6439 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6440 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6441 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6442 PPC_64B | PPC_ALTIVEC | \
6443 PPC_SEGMENT_64B | PPC_SLBI)
6444 #define POWERPC_INSNS2_970MP (PPC_NONE)
6445 #define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6446 #define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6447 #define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6448 #define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6449 #define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6450 #define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6451 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6452 POWERPC_FLAG_BUS_CLK)
6453
6454 static int check_pow_970MP (CPUPPCState *env)
6455 {
6456 if (env->spr[SPR_HID0] & 0x01C00000)
6457 return 1;
6458
6459 return 0;
6460 }
6461
6462 static void init_proc_970MP (CPUPPCState *env)
6463 {
6464 gen_spr_ne_601(env);
6465 gen_spr_7xx(env);
6466 /* Time base */
6467 gen_tbl(env);
6468 /* Hardware implementation registers */
6469 /* XXX : not implemented */
6470 spr_register(env, SPR_HID0, "HID0",
6471 SPR_NOACCESS, SPR_NOACCESS,
6472 &spr_read_generic, &spr_write_clear,
6473 0x60000000);
6474 /* XXX : not implemented */
6475 spr_register(env, SPR_HID1, "HID1",
6476 SPR_NOACCESS, SPR_NOACCESS,
6477 &spr_read_generic, &spr_write_generic,
6478 0x00000000);
6479 /* XXX : not implemented */
6480 spr_register(env, SPR_750FX_HID2, "HID2",
6481 SPR_NOACCESS, SPR_NOACCESS,
6482 &spr_read_generic, &spr_write_generic,
6483 0x00000000);
6484 /* XXX : not implemented */
6485 spr_register(env, SPR_970_HID5, "HID5",
6486 SPR_NOACCESS, SPR_NOACCESS,
6487 &spr_read_generic, &spr_write_generic,
6488 POWERPC970_HID5_INIT);
6489 /* XXX : not implemented */
6490 spr_register(env, SPR_L2CR, "L2CR",
6491 SPR_NOACCESS, SPR_NOACCESS,
6492 &spr_read_generic, &spr_write_generic,
6493 0x00000000);
6494 /* Memory management */
6495 /* XXX: not correct */
6496 gen_low_BATs(env);
6497 /* XXX : not implemented */
6498 spr_register(env, SPR_MMUCFG, "MMUCFG",
6499 SPR_NOACCESS, SPR_NOACCESS,
6500 &spr_read_generic, SPR_NOACCESS,
6501 0x00000000); /* TOFIX */
6502 /* XXX : not implemented */
6503 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6504 SPR_NOACCESS, SPR_NOACCESS,
6505 &spr_read_generic, &spr_write_generic,
6506 0x00000000); /* TOFIX */
6507 spr_register(env, SPR_HIOR, "SPR_HIOR",
6508 SPR_NOACCESS, SPR_NOACCESS,
6509 &spr_read_hior, &spr_write_hior,
6510 0x00000000);
6511 #if !defined(CONFIG_USER_ONLY)
6512 env->slb_nr = 32;
6513 #endif
6514 init_excp_970(env);
6515 env->dcache_line_size = 128;
6516 env->icache_line_size = 128;
6517 /* Allocate hardware IRQ controller */
6518 ppc970_irq_init(env);
6519 /* Can't find information on what this should be on reset. This
6520 * value is the one used by 74xx processors. */
6521 vscr_init(env, 0x00010000);
6522 }
6523
6524 #if defined(TARGET_PPC64)
6525 /* POWER7 */
6526 #define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6527 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6528 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6529 PPC_FLOAT_STFIWX | \
6530 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6531 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6532 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6533 PPC_64B | PPC_ALTIVEC | \
6534 PPC_SEGMENT_64B | PPC_SLBI | \
6535 PPC_POPCNTB | PPC_POPCNTWD)
6536 #define POWERPC_INSNS2_POWER7 (PPC_NONE)
6537 #define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
6538 #define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
6539 #define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
6540 #define POWERPC_INPUT_POWER7 (PPC_FLAGS_INPUT_POWER7)
6541 #define POWERPC_BFDM_POWER7 (bfd_mach_ppc64)
6542 #define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6543 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6544 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR)
6545 #define check_pow_POWER7 check_pow_nocheck
6546
6547 static void init_proc_POWER7 (CPUPPCState *env)
6548 {
6549 gen_spr_ne_601(env);
6550 gen_spr_7xx(env);
6551 /* Time base */
6552 gen_tbl(env);
6553 #if !defined(CONFIG_USER_ONLY)
6554 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6555 spr_register(env, SPR_PURR, "PURR",
6556 &spr_read_purr, SPR_NOACCESS,
6557 &spr_read_purr, SPR_NOACCESS,
6558 0x00000000);
6559 spr_register(env, SPR_SPURR, "SPURR",
6560 &spr_read_purr, SPR_NOACCESS,
6561 &spr_read_purr, SPR_NOACCESS,
6562 0x00000000);
6563 spr_register(env, SPR_CFAR, "SPR_CFAR",
6564 SPR_NOACCESS, SPR_NOACCESS,
6565 &spr_read_cfar, &spr_write_cfar,
6566 0x00000000);
6567 spr_register(env, SPR_DSCR, "SPR_DSCR",
6568 SPR_NOACCESS, SPR_NOACCESS,
6569 &spr_read_generic, &spr_write_generic,
6570 0x00000000);
6571 #endif /* !CONFIG_USER_ONLY */
6572 /* Memory management */
6573 /* XXX : not implemented */
6574 spr_register(env, SPR_MMUCFG, "MMUCFG",
6575 SPR_NOACCESS, SPR_NOACCESS,
6576 &spr_read_generic, SPR_NOACCESS,
6577 0x00000000); /* TOFIX */
6578 /* XXX : not implemented */
6579 spr_register(env, SPR_CTRL, "SPR_CTRLT",
6580 SPR_NOACCESS, SPR_NOACCESS,
6581 &spr_read_generic, &spr_write_generic,
6582 0x80800000);
6583 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
6584 SPR_NOACCESS, SPR_NOACCESS,
6585 &spr_read_generic, &spr_write_generic,
6586 0x80800000);
6587 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6588 &spr_read_generic, &spr_write_generic,
6589 &spr_read_generic, &spr_write_generic,
6590 0x00000000);
6591 #if !defined(CONFIG_USER_ONLY)
6592 env->slb_nr = 32;
6593 #endif
6594 init_excp_POWER7(env);
6595 env->dcache_line_size = 128;
6596 env->icache_line_size = 128;
6597 /* Allocate hardware IRQ controller */
6598 ppcPOWER7_irq_init(env);
6599 /* Can't find information on what this should be on reset. This
6600 * value is the one used by 74xx processors. */
6601 vscr_init(env, 0x00010000);
6602 }
6603 #endif /* TARGET_PPC64 */
6604
6605 /* PowerPC 620 */
6606 #define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6607 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6608 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6609 PPC_FLOAT_STFIWX | \
6610 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6611 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6612 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6613 PPC_SEGMENT | PPC_EXTERN | \
6614 PPC_64B | PPC_SLBI)
6615 #define POWERPC_INSNS2_620 (PPC_NONE)
6616 #define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6617 //#define POWERPC_MMU_620 (POWERPC_MMU_620)
6618 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
6619 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
6620 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
6621 #define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
6622 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
6623 #define check_pow_620 check_pow_nocheck /* Check this */
6624
6625 __attribute__ (( unused ))
6626 static void init_proc_620 (CPUPPCState *env)
6627 {
6628 gen_spr_ne_601(env);
6629 gen_spr_620(env);
6630 /* Time base */
6631 gen_tbl(env);
6632 /* Hardware implementation registers */
6633 /* XXX : not implemented */
6634 spr_register(env, SPR_HID0, "HID0",
6635 SPR_NOACCESS, SPR_NOACCESS,
6636 &spr_read_generic, &spr_write_generic,
6637 0x00000000);
6638 /* Memory management */
6639 gen_low_BATs(env);
6640 init_excp_620(env);
6641 env->dcache_line_size = 64;
6642 env->icache_line_size = 64;
6643 /* Allocate hardware IRQ controller */
6644 ppc6xx_irq_init(env);
6645 }
6646 #endif /* defined (TARGET_PPC64) */
6647
6648 /* Default 32 bits PowerPC target will be 604 */
6649 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
6650 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
6651 #define POWERPC_INSNS2_PPC32 POWERPC_INSNS2_604
6652 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6653 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
6654 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6655 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
6656 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
6657 #define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
6658 #define check_pow_PPC32 check_pow_604
6659 #define init_proc_PPC32 init_proc_604
6660
6661 /* Default 64 bits PowerPC target will be 970 FX */
6662 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6663 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
6664 #define POWERPC_INSNS2_PPC64 POWERPC_INSNS2_970FX
6665 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6666 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6667 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6668 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
6669 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
6670 #define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
6671 #define check_pow_PPC64 check_pow_970FX
6672 #define init_proc_PPC64 init_proc_970FX
6673
6674 /* Default PowerPC target will be PowerPC 32 */
6675 #if defined (TARGET_PPC64) && 0 // XXX: TODO
6676 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6677 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6678 #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC64
6679 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6680 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6681 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6682 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6683 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
6684 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
6685 #define check_pow_DEFAULT check_pow_PPC64
6686 #define init_proc_DEFAULT init_proc_PPC64
6687 #else
6688 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6689 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6690 #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC32
6691 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6692 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6693 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6694 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6695 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
6696 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
6697 #define check_pow_DEFAULT check_pow_PPC32
6698 #define init_proc_DEFAULT init_proc_PPC32
6699 #endif
6700
6701 /*****************************************************************************/
6702 /* PVR definitions for most known PowerPC */
6703 enum {
6704 /* PowerPC 401 family */
6705 /* Generic PowerPC 401 */
6706 #define CPU_POWERPC_401 CPU_POWERPC_401G2
6707 /* PowerPC 401 cores */
6708 CPU_POWERPC_401A1 = 0x00210000,
6709 CPU_POWERPC_401B2 = 0x00220000,
6710 #if 0
6711 CPU_POWERPC_401B3 = xxx,
6712 #endif
6713 CPU_POWERPC_401C2 = 0x00230000,
6714 CPU_POWERPC_401D2 = 0x00240000,
6715 CPU_POWERPC_401E2 = 0x00250000,
6716 CPU_POWERPC_401F2 = 0x00260000,
6717 CPU_POWERPC_401G2 = 0x00270000,
6718 /* PowerPC 401 microcontrolers */
6719 #if 0
6720 CPU_POWERPC_401GF = xxx,
6721 #endif
6722 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
6723 /* IBM Processor for Network Resources */
6724 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
6725 #if 0
6726 CPU_POWERPC_XIPCHIP = xxx,
6727 #endif
6728 /* PowerPC 403 family */
6729 /* Generic PowerPC 403 */
6730 #define CPU_POWERPC_403 CPU_POWERPC_403GC
6731 /* PowerPC 403 microcontrollers */
6732 CPU_POWERPC_403GA = 0x00200011,
6733 CPU_POWERPC_403GB = 0x00200100,
6734 CPU_POWERPC_403GC = 0x00200200,
6735 CPU_POWERPC_403GCX = 0x00201400,
6736 #if 0
6737 CPU_POWERPC_403GP = xxx,
6738 #endif
6739 /* PowerPC 405 family */
6740 /* Generic PowerPC 405 */
6741 #define CPU_POWERPC_405 CPU_POWERPC_405D4
6742 /* PowerPC 405 cores */
6743 #if 0
6744 CPU_POWERPC_405A3 = xxx,
6745 #endif
6746 #if 0
6747 CPU_POWERPC_405A4 = xxx,
6748 #endif
6749 #if 0
6750 CPU_POWERPC_405B3 = xxx,
6751 #endif
6752 #if 0
6753 CPU_POWERPC_405B4 = xxx,
6754 #endif
6755 #if 0
6756 CPU_POWERPC_405C3 = xxx,
6757 #endif
6758 #if 0
6759 CPU_POWERPC_405C4 = xxx,
6760 #endif
6761 CPU_POWERPC_405D2 = 0x20010000,
6762 #if 0
6763 CPU_POWERPC_405D3 = xxx,
6764 #endif
6765 CPU_POWERPC_405D4 = 0x41810000,
6766 #if 0
6767 CPU_POWERPC_405D5 = xxx,
6768 #endif
6769 #if 0
6770 CPU_POWERPC_405E4 = xxx,
6771 #endif
6772 #if 0
6773 CPU_POWERPC_405F4 = xxx,
6774 #endif
6775 #if 0
6776 CPU_POWERPC_405F5 = xxx,
6777 #endif
6778 #if 0
6779 CPU_POWERPC_405F6 = xxx,
6780 #endif
6781 /* PowerPC 405 microcontrolers */
6782 /* XXX: missing 0x200108a0 */
6783 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6784 CPU_POWERPC_405CRa = 0x40110041,
6785 CPU_POWERPC_405CRb = 0x401100C5,
6786 CPU_POWERPC_405CRc = 0x40110145,
6787 CPU_POWERPC_405EP = 0x51210950,
6788 #if 0
6789 CPU_POWERPC_405EXr = xxx,
6790 #endif
6791 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
6792 #if 0
6793 CPU_POWERPC_405FX = xxx,
6794 #endif
6795 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6796 CPU_POWERPC_405GPa = 0x40110000,
6797 CPU_POWERPC_405GPb = 0x40110040,
6798 CPU_POWERPC_405GPc = 0x40110082,
6799 CPU_POWERPC_405GPd = 0x401100C4,
6800 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6801 CPU_POWERPC_405GPR = 0x50910951,
6802 #if 0
6803 CPU_POWERPC_405H = xxx,
6804 #endif
6805 #if 0
6806 CPU_POWERPC_405L = xxx,
6807 #endif
6808 CPU_POWERPC_405LP = 0x41F10000,
6809 #if 0
6810 CPU_POWERPC_405PM = xxx,
6811 #endif
6812 #if 0
6813 CPU_POWERPC_405PS = xxx,
6814 #endif
6815 #if 0
6816 CPU_POWERPC_405S = xxx,
6817 #endif
6818 /* IBM network processors */
6819 CPU_POWERPC_NPE405H = 0x414100C0,
6820 CPU_POWERPC_NPE405H2 = 0x41410140,
6821 CPU_POWERPC_NPE405L = 0x416100C0,
6822 CPU_POWERPC_NPE4GS3 = 0x40B10000,
6823 #if 0
6824 CPU_POWERPC_NPCxx1 = xxx,
6825 #endif
6826 #if 0
6827 CPU_POWERPC_NPR161 = xxx,
6828 #endif
6829 #if 0
6830 CPU_POWERPC_LC77700 = xxx,
6831 #endif
6832 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6833 #if 0
6834 CPU_POWERPC_STB01000 = xxx,
6835 #endif
6836 #if 0
6837 CPU_POWERPC_STB01010 = xxx,
6838 #endif
6839 #if 0
6840 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
6841 #endif
6842 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
6843 #if 0
6844 CPU_POWERPC_STB043 = xxx,
6845 #endif
6846 #if 0
6847 CPU_POWERPC_STB045 = xxx,
6848 #endif
6849 CPU_POWERPC_STB04 = 0x41810000,
6850 CPU_POWERPC_STB25 = 0x51510950,
6851 #if 0
6852 CPU_POWERPC_STB130 = xxx,
6853 #endif
6854 /* Xilinx cores */
6855 CPU_POWERPC_X2VP4 = 0x20010820,
6856 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
6857 CPU_POWERPC_X2VP20 = 0x20010860,
6858 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
6859 #if 0
6860 CPU_POWERPC_ZL10310 = xxx,
6861 #endif
6862 #if 0
6863 CPU_POWERPC_ZL10311 = xxx,
6864 #endif
6865 #if 0
6866 CPU_POWERPC_ZL10320 = xxx,
6867 #endif
6868 #if 0
6869 CPU_POWERPC_ZL10321 = xxx,
6870 #endif
6871 /* PowerPC 440 family */
6872 /* Generic PowerPC 440 */
6873 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
6874 /* PowerPC 440 cores */
6875 #if 0
6876 CPU_POWERPC_440A4 = xxx,
6877 #endif
6878 CPU_POWERPC_440_XILINX = 0x7ff21910,
6879 #if 0
6880 CPU_POWERPC_440A5 = xxx,
6881 #endif
6882 #if 0
6883 CPU_POWERPC_440B4 = xxx,
6884 #endif
6885 #if 0
6886 CPU_POWERPC_440F5 = xxx,
6887 #endif
6888 #if 0
6889 CPU_POWERPC_440G5 = xxx,
6890 #endif
6891 #if 0
6892 CPU_POWERPC_440H4 = xxx,
6893 #endif
6894 #if 0
6895 CPU_POWERPC_440H6 = xxx,
6896 #endif
6897 /* PowerPC 440 microcontrolers */
6898 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
6899 CPU_POWERPC_440EPa = 0x42221850,
6900 CPU_POWERPC_440EPb = 0x422218D3,
6901 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
6902 CPU_POWERPC_440GPb = 0x40120440,
6903 CPU_POWERPC_440GPc = 0x40120481,
6904 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
6905 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
6906 CPU_POWERPC_440GRX = 0x200008D0,
6907 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
6908 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
6909 CPU_POWERPC_440GXa = 0x51B21850,
6910 CPU_POWERPC_440GXb = 0x51B21851,
6911 CPU_POWERPC_440GXc = 0x51B21892,
6912 CPU_POWERPC_440GXf = 0x51B21894,
6913 #if 0
6914 CPU_POWERPC_440S = xxx,
6915 #endif
6916 CPU_POWERPC_440SP = 0x53221850,
6917 CPU_POWERPC_440SP2 = 0x53221891,
6918 CPU_POWERPC_440SPE = 0x53421890,
6919 /* PowerPC 460 family */
6920 #if 0
6921 /* Generic PowerPC 464 */
6922 #define CPU_POWERPC_464 CPU_POWERPC_464H90
6923 #endif
6924 /* PowerPC 464 microcontrolers */
6925 #if 0
6926 CPU_POWERPC_464H90 = xxx,
6927 #endif
6928 #if 0
6929 CPU_POWERPC_464H90FP = xxx,
6930 #endif
6931 /* Freescale embedded PowerPC cores */
6932 /* PowerPC MPC 5xx cores (aka RCPU) */
6933 CPU_POWERPC_MPC5xx = 0x00020020,
6934 #define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
6935 #define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
6936 #define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
6937 #define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
6938 #define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
6939 #define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
6940 #define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
6941 #define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
6942 #define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
6943 #define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
6944 #define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
6945 #define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
6946 #define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
6947 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
6948 CPU_POWERPC_MPC8xx = 0x00500000,
6949 #define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
6950 #define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
6951 #define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
6952 #define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
6953 #define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
6954 #define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
6955 #define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
6956 #define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
6957 #define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
6958 #define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
6959 #define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
6960 #define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
6961 #define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
6962 #define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
6963 #define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
6964 /* G2 cores (aka PowerQUICC-II) */
6965 CPU_POWERPC_G2 = 0x00810011,
6966 CPU_POWERPC_G2H4 = 0x80811010,
6967 CPU_POWERPC_G2gp = 0x80821010,
6968 CPU_POWERPC_G2ls = 0x90810010,
6969 CPU_POWERPC_MPC603 = 0x00810100,
6970 CPU_POWERPC_G2_HIP3 = 0x00810101,
6971 CPU_POWERPC_G2_HIP4 = 0x80811014,
6972 /* G2_LE core (aka PowerQUICC-II) */
6973 CPU_POWERPC_G2LE = 0x80820010,
6974 CPU_POWERPC_G2LEgp = 0x80822010,
6975 CPU_POWERPC_G2LEls = 0xA0822010,
6976 CPU_POWERPC_G2LEgp1 = 0x80822011,
6977 CPU_POWERPC_G2LEgp3 = 0x80822013,
6978 /* MPC52xx microcontrollers */
6979 /* XXX: MPC 5121 ? */
6980 #define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
6981 #define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
6982 #define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
6983 #define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
6984 #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
6985 #define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
6986 #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
6987 #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
6988 /* MPC82xx microcontrollers */
6989 #define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
6990 #define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
6991 #define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
6992 #define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
6993 #define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
6994 #define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
6995 #define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
6996 #define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
6997 #define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
6998 #define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
6999 #define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
7000 #define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
7001 #define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
7002 #define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
7003 #define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
7004 #define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
7005 #define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
7006 #define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
7007 #define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
7008 #define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
7009 #define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
7010 #define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
7011 #define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
7012 #define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
7013 #define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
7014 #define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
7015 #define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
7016 #define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
7017 #define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
7018 /* e200 family */
7019 /* e200 cores */
7020 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
7021 #if 0
7022 CPU_POWERPC_e200z0 = xxx,
7023 #endif
7024 #if 0
7025 CPU_POWERPC_e200z1 = xxx,
7026 #endif
7027 #if 0 /* ? */
7028 CPU_POWERPC_e200z3 = 0x81120000,
7029 #endif
7030 CPU_POWERPC_e200z5 = 0x81000000,
7031 CPU_POWERPC_e200z6 = 0x81120000,
7032 /* MPC55xx microcontrollers */
7033 #define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
7034 #if 0
7035 #define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
7036 #define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
7037 #define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
7038 #define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
7039 #define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
7040 #define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
7041 #define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
7042 #define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
7043 #define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
7044 #define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
7045 #define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
7046 #define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
7047 #define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
7048 #define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
7049 #endif
7050 #if 0
7051 #define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
7052 #define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
7053 #endif
7054 #define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
7055 #define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
7056 #define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
7057 #define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
7058 #define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
7059 #define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
7060 /* e300 family */
7061 /* e300 cores */
7062 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
7063 CPU_POWERPC_e300c1 = 0x00830010,
7064 CPU_POWERPC_e300c2 = 0x00840010,
7065 CPU_POWERPC_e300c3 = 0x00850010,
7066 CPU_POWERPC_e300c4 = 0x00860010,
7067 /* MPC83xx microcontrollers */
7068 #define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
7069 #define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
7070 #define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
7071 #define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
7072 #define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
7073 #define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
7074 /* e500 family */
7075 /* e500 cores */
7076 #define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
7077 #define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
7078 #define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
7079 CPU_POWERPC_e500v1_v10 = 0x80200010,
7080 CPU_POWERPC_e500v1_v20 = 0x80200020,
7081 CPU_POWERPC_e500v2_v10 = 0x80210010,
7082 CPU_POWERPC_e500v2_v11 = 0x80210011,
7083 CPU_POWERPC_e500v2_v20 = 0x80210020,
7084 CPU_POWERPC_e500v2_v21 = 0x80210021,
7085 CPU_POWERPC_e500v2_v22 = 0x80210022,
7086 CPU_POWERPC_e500v2_v30 = 0x80210030,
7087 /* MPC85xx microcontrollers */
7088 #define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
7089 #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
7090 #define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
7091 #define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
7092 #define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
7093 #define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
7094 #define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
7095 #define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
7096 #define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
7097 #define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
7098 #define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
7099 #define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
7100 #define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
7101 #define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
7102 #define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
7103 #define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
7104 #define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
7105 #define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
7106 #define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
7107 #define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
7108 #define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
7109 #define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
7110 #define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
7111 #define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
7112 #define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
7113 #define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
7114 #define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
7115 #define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
7116 #define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
7117 #define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
7118 #define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
7119 #define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
7120 #define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
7121 #define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
7122 #define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
7123 #define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
7124 #define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
7125 #define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
7126 #define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
7127 #define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
7128 #define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
7129 #define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
7130 #define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
7131 #define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
7132 #define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
7133 #define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
7134 #define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
7135 #define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
7136 #define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
7137 #define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
7138 #define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
7139 #define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
7140 #define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
7141 #define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
7142 #define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
7143 #define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
7144 #define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
7145 #define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
7146 #define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
7147 #define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
7148 #define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
7149 #define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
7150 #define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
7151 #define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
7152 #define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
7153 #define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
7154 #define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
7155 #define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
7156 #define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
7157 #define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
7158 /* e600 family */
7159 /* e600 cores */
7160 CPU_POWERPC_e600 = 0x80040010,
7161 /* MPC86xx microcontrollers */
7162 #define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
7163 #define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
7164 #define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
7165 /* PowerPC 6xx cores */
7166 #define CPU_POWERPC_601 CPU_POWERPC_601_v2
7167 CPU_POWERPC_601_v0 = 0x00010001,
7168 CPU_POWERPC_601_v1 = 0x00010001,
7169 #define CPU_POWERPC_601v CPU_POWERPC_601_v2
7170 CPU_POWERPC_601_v2 = 0x00010002,
7171 CPU_POWERPC_602 = 0x00050100,
7172 CPU_POWERPC_603 = 0x00030100,
7173 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
7174 CPU_POWERPC_603E_v11 = 0x00060101,
7175 CPU_POWERPC_603E_v12 = 0x00060102,
7176 CPU_POWERPC_603E_v13 = 0x00060103,
7177 CPU_POWERPC_603E_v14 = 0x00060104,
7178 CPU_POWERPC_603E_v22 = 0x00060202,
7179 CPU_POWERPC_603E_v3 = 0x00060300,
7180 CPU_POWERPC_603E_v4 = 0x00060400,
7181 CPU_POWERPC_603E_v41 = 0x00060401,
7182 CPU_POWERPC_603E7t = 0x00071201,
7183 CPU_POWERPC_603E7v = 0x00070100,
7184 CPU_POWERPC_603E7v1 = 0x00070101,
7185 CPU_POWERPC_603E7v2 = 0x00070201,
7186 CPU_POWERPC_603E7 = 0x00070200,
7187 CPU_POWERPC_603P = 0x00070000,
7188 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
7189 /* XXX: missing 0x00040303 (604) */
7190 CPU_POWERPC_604 = 0x00040103,
7191 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
7192 /* XXX: missing 0x00091203 */
7193 /* XXX: missing 0x00092110 */
7194 /* XXX: missing 0x00092120 */
7195 CPU_POWERPC_604E_v10 = 0x00090100,
7196 CPU_POWERPC_604E_v22 = 0x00090202,
7197 CPU_POWERPC_604E_v24 = 0x00090204,
7198 /* XXX: missing 0x000a0100 */
7199 /* XXX: missing 0x00093102 */
7200 CPU_POWERPC_604R = 0x000a0101,
7201 #if 0
7202 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
7203 #endif
7204 /* PowerPC 740/750 cores (aka G3) */
7205 /* XXX: missing 0x00084202 */
7206 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
7207 CPU_POWERPC_7x0_v10 = 0x00080100,
7208 CPU_POWERPC_7x0_v20 = 0x00080200,
7209 CPU_POWERPC_7x0_v21 = 0x00080201,
7210 CPU_POWERPC_7x0_v22 = 0x00080202,
7211 CPU_POWERPC_7x0_v30 = 0x00080300,
7212 CPU_POWERPC_7x0_v31 = 0x00080301,
7213 CPU_POWERPC_740E = 0x00080100,
7214 CPU_POWERPC_750E = 0x00080200,
7215 CPU_POWERPC_7x0P = 0x10080000,
7216 /* XXX: missing 0x00087010 (CL ?) */
7217 #define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
7218 CPU_POWERPC_750CL_v10 = 0x00087200,
7219 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
7220 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
7221 CPU_POWERPC_750CX_v10 = 0x00082100,
7222 CPU_POWERPC_750CX_v20 = 0x00082200,
7223 CPU_POWERPC_750CX_v21 = 0x00082201,
7224 CPU_POWERPC_750CX_v22 = 0x00082202,
7225 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
7226 CPU_POWERPC_750CXE_v21 = 0x00082211,
7227 CPU_POWERPC_750CXE_v22 = 0x00082212,
7228 CPU_POWERPC_750CXE_v23 = 0x00082213,
7229 CPU_POWERPC_750CXE_v24 = 0x00082214,
7230 CPU_POWERPC_750CXE_v24b = 0x00083214,
7231 CPU_POWERPC_750CXE_v30 = 0x00082310,
7232 CPU_POWERPC_750CXE_v31 = 0x00082311,
7233 CPU_POWERPC_750CXE_v31b = 0x00083311,
7234 CPU_POWERPC_750CXR = 0x00083410,
7235 CPU_POWERPC_750FL = 0x70000203,
7236 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
7237 CPU_POWERPC_750FX_v10 = 0x70000100,
7238 CPU_POWERPC_750FX_v20 = 0x70000200,
7239 CPU_POWERPC_750FX_v21 = 0x70000201,
7240 CPU_POWERPC_750FX_v22 = 0x70000202,
7241 CPU_POWERPC_750FX_v23 = 0x70000203,
7242 CPU_POWERPC_750GL = 0x70020102,
7243 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
7244 CPU_POWERPC_750GX_v10 = 0x70020100,
7245 CPU_POWERPC_750GX_v11 = 0x70020101,
7246 CPU_POWERPC_750GX_v12 = 0x70020102,
7247 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
7248 CPU_POWERPC_750L_v20 = 0x00088200,
7249 CPU_POWERPC_750L_v21 = 0x00088201,
7250 CPU_POWERPC_750L_v22 = 0x00088202,
7251 CPU_POWERPC_750L_v30 = 0x00088300,
7252 CPU_POWERPC_750L_v32 = 0x00088302,
7253 /* PowerPC 745/755 cores */
7254 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
7255 CPU_POWERPC_7x5_v10 = 0x00083100,
7256 CPU_POWERPC_7x5_v11 = 0x00083101,
7257 CPU_POWERPC_7x5_v20 = 0x00083200,
7258 CPU_POWERPC_7x5_v21 = 0x00083201,
7259 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
7260 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
7261 CPU_POWERPC_7x5_v24 = 0x00083204,
7262 CPU_POWERPC_7x5_v25 = 0x00083205,
7263 CPU_POWERPC_7x5_v26 = 0x00083206,
7264 CPU_POWERPC_7x5_v27 = 0x00083207,
7265 CPU_POWERPC_7x5_v28 = 0x00083208,
7266 #if 0
7267 CPU_POWERPC_7x5P = xxx,
7268 #endif
7269 /* PowerPC 74xx cores (aka G4) */
7270 /* XXX: missing 0x000C1101 */
7271 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
7272 CPU_POWERPC_7400_v10 = 0x000C0100,
7273 CPU_POWERPC_7400_v11 = 0x000C0101,
7274 CPU_POWERPC_7400_v20 = 0x000C0200,
7275 CPU_POWERPC_7400_v21 = 0x000C0201,
7276 CPU_POWERPC_7400_v22 = 0x000C0202,
7277 CPU_POWERPC_7400_v26 = 0x000C0206,
7278 CPU_POWERPC_7400_v27 = 0x000C0207,
7279 CPU_POWERPC_7400_v28 = 0x000C0208,
7280 CPU_POWERPC_7400_v29 = 0x000C0209,
7281 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
7282 CPU_POWERPC_7410_v10 = 0x800C1100,
7283 CPU_POWERPC_7410_v11 = 0x800C1101,
7284 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
7285 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
7286 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
7287 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
7288 CPU_POWERPC_7448_v10 = 0x80040100,
7289 CPU_POWERPC_7448_v11 = 0x80040101,
7290 CPU_POWERPC_7448_v20 = 0x80040200,
7291 CPU_POWERPC_7448_v21 = 0x80040201,
7292 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
7293 CPU_POWERPC_7450_v10 = 0x80000100,
7294 CPU_POWERPC_7450_v11 = 0x80000101,
7295 CPU_POWERPC_7450_v12 = 0x80000102,
7296 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
7297 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
7298 #define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
7299 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
7300 /* XXX: this entry might be a bug in some documentation */
7301 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
7302 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
7303 CPU_POWERPC_74x5_v10 = 0x80010100,
7304 /* XXX: missing 0x80010200 */
7305 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
7306 CPU_POWERPC_74x5_v32 = 0x80010302,
7307 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
7308 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
7309 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
7310 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
7311 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
7312 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
7313 #define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
7314 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
7315 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
7316 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
7317 /* 64 bits PowerPC */
7318 #if defined(TARGET_PPC64)
7319 CPU_POWERPC_620 = 0x00140000,
7320 CPU_POWERPC_630 = 0x00400000,
7321 CPU_POWERPC_631 = 0x00410104,
7322 CPU_POWERPC_POWER4 = 0x00350000,
7323 CPU_POWERPC_POWER4P = 0x00380000,
7324 /* XXX: missing 0x003A0201 */
7325 CPU_POWERPC_POWER5 = 0x003A0203,
7326 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
7327 CPU_POWERPC_POWER5P = 0x003B0000,
7328 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
7329 CPU_POWERPC_POWER6 = 0x003E0000,
7330 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
7331 CPU_POWERPC_POWER6A = 0x0F000002,
7332 #define CPU_POWERPC_POWER7 CPU_POWERPC_POWER7_v20
7333 CPU_POWERPC_POWER7_v20 = 0x003F0200,
7334 CPU_POWERPC_970 = 0x00390202,
7335 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
7336 CPU_POWERPC_970FX_v10 = 0x00391100,
7337 CPU_POWERPC_970FX_v20 = 0x003C0200,
7338 CPU_POWERPC_970FX_v21 = 0x003C0201,
7339 CPU_POWERPC_970FX_v30 = 0x003C0300,
7340 CPU_POWERPC_970FX_v31 = 0x003C0301,
7341 CPU_POWERPC_970GX = 0x00450000,
7342 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
7343 CPU_POWERPC_970MP_v10 = 0x00440100,
7344 CPU_POWERPC_970MP_v11 = 0x00440101,
7345 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
7346 CPU_POWERPC_CELL_v10 = 0x00700100,
7347 CPU_POWERPC_CELL_v20 = 0x00700400,
7348 CPU_POWERPC_CELL_v30 = 0x00700500,
7349 CPU_POWERPC_CELL_v31 = 0x00700501,
7350 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
7351 CPU_POWERPC_RS64 = 0x00330000,
7352 CPU_POWERPC_RS64II = 0x00340000,
7353 CPU_POWERPC_RS64III = 0x00360000,
7354 CPU_POWERPC_RS64IV = 0x00370000,
7355 #endif /* defined(TARGET_PPC64) */
7356 /* Original POWER */
7357 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7358 * POWER2 (RIOS2) & RSC2 (P2SC) here
7359 */
7360 #if 0
7361 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
7362 #endif
7363 #if 0
7364 CPU_POWER2 = xxx, /* 0x40000 ? */
7365 #endif
7366 /* PA Semi core */
7367 CPU_POWERPC_PA6T = 0x00900000,
7368 };
7369
7370 /* System version register (used on MPC 8xxx) */
7371 enum {
7372 POWERPC_SVR_NONE = 0x00000000,
7373 #define POWERPC_SVR_52xx POWERPC_SVR_5200
7374 #define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7375 POWERPC_SVR_5200_v10 = 0x80110010,
7376 POWERPC_SVR_5200_v11 = 0x80110011,
7377 POWERPC_SVR_5200_v12 = 0x80110012,
7378 #define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7379 POWERPC_SVR_5200B_v20 = 0x80110020,
7380 POWERPC_SVR_5200B_v21 = 0x80110021,
7381 #define POWERPC_SVR_55xx POWERPC_SVR_5567
7382 #if 0
7383 POWERPC_SVR_5533 = xxx,
7384 #endif
7385 #if 0
7386 POWERPC_SVR_5534 = xxx,
7387 #endif
7388 #if 0
7389 POWERPC_SVR_5553 = xxx,
7390 #endif
7391 #if 0
7392 POWERPC_SVR_5554 = xxx,
7393 #endif
7394 #if 0
7395 POWERPC_SVR_5561 = xxx,
7396 #endif
7397 #if 0
7398 POWERPC_SVR_5565 = xxx,
7399 #endif
7400 #if 0
7401 POWERPC_SVR_5566 = xxx,
7402 #endif
7403 #if 0
7404 POWERPC_SVR_5567 = xxx,
7405 #endif
7406 #if 0
7407 POWERPC_SVR_8313 = xxx,
7408 #endif
7409 #if 0
7410 POWERPC_SVR_8313E = xxx,
7411 #endif
7412 #if 0
7413 POWERPC_SVR_8314 = xxx,
7414 #endif
7415 #if 0
7416 POWERPC_SVR_8314E = xxx,
7417 #endif
7418 #if 0
7419 POWERPC_SVR_8315 = xxx,
7420 #endif
7421 #if 0
7422 POWERPC_SVR_8315E = xxx,
7423 #endif
7424 #if 0
7425 POWERPC_SVR_8321 = xxx,
7426 #endif
7427 #if 0
7428 POWERPC_SVR_8321E = xxx,
7429 #endif
7430 #if 0
7431 POWERPC_SVR_8323 = xxx,
7432 #endif
7433 #if 0
7434 POWERPC_SVR_8323E = xxx,
7435 #endif
7436 POWERPC_SVR_8343 = 0x80570010,
7437 POWERPC_SVR_8343A = 0x80570030,
7438 POWERPC_SVR_8343E = 0x80560010,
7439 POWERPC_SVR_8343EA = 0x80560030,
7440 #define POWERPC_SVR_8347 POWERPC_SVR_8347T
7441 POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
7442 POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
7443 #define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7444 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7445 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
7446 #define POWERPC_SVR_8347E POWERPC_SVR_8347ET
7447 POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
7448 POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
7449 #define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7450 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7451 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7452 POWERPC_SVR_8349 = 0x80510010,
7453 POWERPC_SVR_8349A = 0x80510030,
7454 POWERPC_SVR_8349E = 0x80500010,
7455 POWERPC_SVR_8349EA = 0x80500030,
7456 #if 0
7457 POWERPC_SVR_8358E = xxx,
7458 #endif
7459 #if 0
7460 POWERPC_SVR_8360E = xxx,
7461 #endif
7462 #define POWERPC_SVR_E500 0x40000000
7463 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7464 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7465 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7466 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7467 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7468 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7469 #define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7470 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7471 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7472 #define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7473 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7474 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7475 #define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7476 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7477 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7478 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7479 #define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7480 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7481 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7482 #define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7483 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7484 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7485 #define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7486 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7487 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7488 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7489 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7490 #define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7491 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7492 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7493 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7494 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7495 #define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7496 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7497 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7498 #define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7499 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7500 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7501 #define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7502 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7503 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7504 #define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7505 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7506 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7507 #define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7508 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7509 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7510 #define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7511 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7512 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7513 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7514 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7515 #define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7516 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7517 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7518 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7519 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7520 #define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7521 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7522 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7523 #define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7524 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7525 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7526 #define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7527 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7528 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7529 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7530 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7531 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7532 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7533 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7534 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7535 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
7536 #if 0
7537 POWERPC_SVR_8610 = xxx,
7538 #endif
7539 POWERPC_SVR_8641 = 0x80900021,
7540 POWERPC_SVR_8641D = 0x80900121,
7541 };
7542
7543 /*****************************************************************************/
7544 /* PowerPC CPU definitions */
7545 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
7546 { \
7547 .name = _name, \
7548 .pvr = _pvr, \
7549 .svr = _svr, \
7550 .insns_flags = glue(POWERPC_INSNS_,_type), \
7551 .insns_flags2 = glue(POWERPC_INSNS2_,_type), \
7552 .msr_mask = glue(POWERPC_MSRM_,_type), \
7553 .mmu_model = glue(POWERPC_MMU_,_type), \
7554 .excp_model = glue(POWERPC_EXCP_,_type), \
7555 .bus_model = glue(POWERPC_INPUT_,_type), \
7556 .bfd_mach = glue(POWERPC_BFDM_,_type), \
7557 .flags = glue(POWERPC_FLAG_,_type), \
7558 .init_proc = &glue(init_proc_,_type), \
7559 .check_pow = &glue(check_pow_,_type), \
7560 }
7561 #define POWERPC_DEF(_name, _pvr, _type) \
7562 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
7563
7564 static const ppc_def_t ppc_defs[] = {
7565 /* Embedded PowerPC */
7566 /* PowerPC 401 family */
7567 /* Generic PowerPC 401 */
7568 POWERPC_DEF("401", CPU_POWERPC_401, 401),
7569 /* PowerPC 401 cores */
7570 /* PowerPC 401A1 */
7571 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
7572 /* PowerPC 401B2 */
7573 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
7574 #if defined (TODO)
7575 /* PowerPC 401B3 */
7576 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
7577 #endif
7578 /* PowerPC 401C2 */
7579 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
7580 /* PowerPC 401D2 */
7581 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
7582 /* PowerPC 401E2 */
7583 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
7584 /* PowerPC 401F2 */
7585 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
7586 /* PowerPC 401G2 */
7587 /* XXX: to be checked */
7588 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
7589 /* PowerPC 401 microcontrolers */
7590 #if defined (TODO)
7591 /* PowerPC 401GF */
7592 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
7593 #endif
7594 /* IOP480 (401 microcontroler) */
7595 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
7596 /* IBM Processor for Network Resources */
7597 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
7598 #if defined (TODO)
7599 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
7600 #endif
7601 /* PowerPC 403 family */
7602 /* Generic PowerPC 403 */
7603 POWERPC_DEF("403", CPU_POWERPC_403, 403),
7604 /* PowerPC 403 microcontrolers */
7605 /* PowerPC 403 GA */
7606 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
7607 /* PowerPC 403 GB */
7608 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
7609 /* PowerPC 403 GC */
7610 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
7611 /* PowerPC 403 GCX */
7612 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
7613 #if defined (TODO)
7614 /* PowerPC 403 GP */
7615 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
7616 #endif
7617 /* PowerPC 405 family */
7618 /* Generic PowerPC 405 */
7619 POWERPC_DEF("405", CPU_POWERPC_405, 405),
7620 /* PowerPC 405 cores */
7621 #if defined (TODO)
7622 /* PowerPC 405 A3 */
7623 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
7624 #endif
7625 #if defined (TODO)
7626 /* PowerPC 405 A4 */
7627 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
7628 #endif
7629 #if defined (TODO)
7630 /* PowerPC 405 B3 */
7631 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
7632 #endif
7633 #if defined (TODO)
7634 /* PowerPC 405 B4 */
7635 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
7636 #endif
7637 #if defined (TODO)
7638 /* PowerPC 405 C3 */
7639 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
7640 #endif
7641 #if defined (TODO)
7642 /* PowerPC 405 C4 */
7643 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
7644 #endif
7645 /* PowerPC 405 D2 */
7646 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
7647 #if defined (TODO)
7648 /* PowerPC 405 D3 */
7649 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
7650 #endif
7651 /* PowerPC 405 D4 */
7652 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
7653 #if defined (TODO)
7654 /* PowerPC 405 D5 */
7655 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
7656 #endif
7657 #if defined (TODO)
7658 /* PowerPC 405 E4 */
7659 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
7660 #endif
7661 #if defined (TODO)
7662 /* PowerPC 405 F4 */
7663 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
7664 #endif
7665 #if defined (TODO)
7666 /* PowerPC 405 F5 */
7667 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
7668 #endif
7669 #if defined (TODO)
7670 /* PowerPC 405 F6 */
7671 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
7672 #endif
7673 /* PowerPC 405 microcontrolers */
7674 /* PowerPC 405 CR */
7675 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
7676 /* PowerPC 405 CRa */
7677 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
7678 /* PowerPC 405 CRb */
7679 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
7680 /* PowerPC 405 CRc */
7681 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
7682 /* PowerPC 405 EP */
7683 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
7684 #if defined(TODO)
7685 /* PowerPC 405 EXr */
7686 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
7687 #endif
7688 /* PowerPC 405 EZ */
7689 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
7690 #if defined(TODO)
7691 /* PowerPC 405 FX */
7692 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
7693 #endif
7694 /* PowerPC 405 GP */
7695 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
7696 /* PowerPC 405 GPa */
7697 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
7698 /* PowerPC 405 GPb */
7699 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
7700 /* PowerPC 405 GPc */
7701 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
7702 /* PowerPC 405 GPd */
7703 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
7704 /* PowerPC 405 GPe */
7705 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
7706 /* PowerPC 405 GPR */
7707 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
7708 #if defined(TODO)
7709 /* PowerPC 405 H */
7710 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
7711 #endif
7712 #if defined(TODO)
7713 /* PowerPC 405 L */
7714 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
7715 #endif
7716 /* PowerPC 405 LP */
7717 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
7718 #if defined(TODO)
7719 /* PowerPC 405 PM */
7720 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
7721 #endif
7722 #if defined(TODO)
7723 /* PowerPC 405 PS */
7724 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
7725 #endif
7726 #if defined(TODO)
7727 /* PowerPC 405 S */
7728 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
7729 #endif
7730 /* Npe405 H */
7731 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
7732 /* Npe405 H2 */
7733 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
7734 /* Npe405 L */
7735 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
7736 /* Npe4GS3 */
7737 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
7738 #if defined (TODO)
7739 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
7740 #endif
7741 #if defined (TODO)
7742 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
7743 #endif
7744 #if defined (TODO)
7745 /* PowerPC LC77700 (Sanyo) */
7746 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
7747 #endif
7748 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7749 #if defined (TODO)
7750 /* STB010000 */
7751 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
7752 #endif
7753 #if defined (TODO)
7754 /* STB01010 */
7755 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
7756 #endif
7757 #if defined (TODO)
7758 /* STB0210 */
7759 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
7760 #endif
7761 /* STB03xx */
7762 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
7763 #if defined (TODO)
7764 /* STB043x */
7765 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
7766 #endif
7767 #if defined (TODO)
7768 /* STB045x */
7769 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
7770 #endif
7771 /* STB04xx */
7772 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
7773 /* STB25xx */
7774 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
7775 #if defined (TODO)
7776 /* STB130 */
7777 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
7778 #endif
7779 /* Xilinx PowerPC 405 cores */
7780 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
7781 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
7782 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
7783 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
7784 #if defined (TODO)
7785 /* Zarlink ZL10310 */
7786 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
7787 #endif
7788 #if defined (TODO)
7789 /* Zarlink ZL10311 */
7790 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
7791 #endif
7792 #if defined (TODO)
7793 /* Zarlink ZL10320 */
7794 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
7795 #endif
7796 #if defined (TODO)
7797 /* Zarlink ZL10321 */
7798 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
7799 #endif
7800 /* PowerPC 440 family */
7801 #if defined(TODO_USER_ONLY)
7802 /* Generic PowerPC 440 */
7803 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
7804 #endif
7805 /* PowerPC 440 cores */
7806 #if defined (TODO)
7807 /* PowerPC 440 A4 */
7808 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
7809 #endif
7810 /* PowerPC 440 Xilinx 5 */
7811 POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5),
7812 #if defined (TODO)
7813 /* PowerPC 440 A5 */
7814 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
7815 #endif
7816 #if defined (TODO)
7817 /* PowerPC 440 B4 */
7818 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
7819 #endif
7820 #if defined (TODO)
7821 /* PowerPC 440 G4 */
7822 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
7823 #endif
7824 #if defined (TODO)
7825 /* PowerPC 440 F5 */
7826 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
7827 #endif
7828 #if defined (TODO)
7829 /* PowerPC 440 G5 */
7830 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
7831 #endif
7832 #if defined (TODO)
7833 /* PowerPC 440H4 */
7834 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
7835 #endif
7836 #if defined (TODO)
7837 /* PowerPC 440H6 */
7838 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
7839 #endif
7840 /* PowerPC 440 microcontrolers */
7841 #if defined(TODO_USER_ONLY)
7842 /* PowerPC 440 EP */
7843 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
7844 #endif
7845 #if defined(TODO_USER_ONLY)
7846 /* PowerPC 440 EPa */
7847 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
7848 #endif
7849 #if defined(TODO_USER_ONLY)
7850 /* PowerPC 440 EPb */
7851 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
7852 #endif
7853 #if defined(TODO_USER_ONLY)
7854 /* PowerPC 440 EPX */
7855 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
7856 #endif
7857 #if defined(TODO_USER_ONLY)
7858 /* PowerPC 440 GP */
7859 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
7860 #endif
7861 #if defined(TODO_USER_ONLY)
7862 /* PowerPC 440 GPb */
7863 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
7864 #endif
7865 #if defined(TODO_USER_ONLY)
7866 /* PowerPC 440 GPc */
7867 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
7868 #endif
7869 #if defined(TODO_USER_ONLY)
7870 /* PowerPC 440 GR */
7871 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
7872 #endif
7873 #if defined(TODO_USER_ONLY)
7874 /* PowerPC 440 GRa */
7875 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
7876 #endif
7877 #if defined(TODO_USER_ONLY)
7878 /* PowerPC 440 GRX */
7879 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
7880 #endif
7881 #if defined(TODO_USER_ONLY)
7882 /* PowerPC 440 GX */
7883 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
7884 #endif
7885 #if defined(TODO_USER_ONLY)
7886 /* PowerPC 440 GXa */
7887 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
7888 #endif
7889 #if defined(TODO_USER_ONLY)
7890 /* PowerPC 440 GXb */
7891 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
7892 #endif
7893 #if defined(TODO_USER_ONLY)
7894 /* PowerPC 440 GXc */
7895 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
7896 #endif
7897 #if defined(TODO_USER_ONLY)
7898 /* PowerPC 440 GXf */
7899 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
7900 #endif
7901 #if defined(TODO)
7902 /* PowerPC 440 S */
7903 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
7904 #endif
7905 #if defined(TODO_USER_ONLY)
7906 /* PowerPC 440 SP */
7907 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
7908 #endif
7909 #if defined(TODO_USER_ONLY)
7910 /* PowerPC 440 SP2 */
7911 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
7912 #endif
7913 #if defined(TODO_USER_ONLY)
7914 /* PowerPC 440 SPE */
7915 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
7916 #endif
7917 /* PowerPC 460 family */
7918 #if defined (TODO)
7919 /* Generic PowerPC 464 */
7920 POWERPC_DEF("464", CPU_POWERPC_464, 460),
7921 #endif
7922 /* PowerPC 464 microcontrolers */
7923 #if defined (TODO)
7924 /* PowerPC 464H90 */
7925 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
7926 #endif
7927 #if defined (TODO)
7928 /* PowerPC 464H90F */
7929 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
7930 #endif
7931 /* Freescale embedded PowerPC cores */
7932 /* MPC5xx family (aka RCPU) */
7933 #if defined(TODO_USER_ONLY)
7934 /* Generic MPC5xx core */
7935 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
7936 #endif
7937 #if defined(TODO_USER_ONLY)
7938 /* Codename for MPC5xx core */
7939 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
7940 #endif
7941 /* MPC5xx microcontrollers */
7942 #if defined(TODO_USER_ONLY)
7943 /* MGT560 */
7944 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
7945 #endif
7946 #if defined(TODO_USER_ONLY)
7947 /* MPC509 */
7948 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
7949 #endif
7950 #if defined(TODO_USER_ONLY)
7951 /* MPC533 */
7952 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
7953 #endif
7954 #if defined(TODO_USER_ONLY)
7955 /* MPC534 */
7956 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
7957 #endif
7958 #if defined(TODO_USER_ONLY)
7959 /* MPC555 */
7960 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
7961 #endif
7962 #if defined(TODO_USER_ONLY)
7963 /* MPC556 */
7964 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
7965 #endif
7966 #if defined(TODO_USER_ONLY)
7967 /* MPC560 */
7968 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
7969 #endif
7970 #if defined(TODO_USER_ONLY)
7971 /* MPC561 */
7972 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
7973 #endif
7974 #if defined(TODO_USER_ONLY)
7975 /* MPC562 */
7976 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
7977 #endif
7978 #if defined(TODO_USER_ONLY)
7979 /* MPC563 */
7980 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
7981 #endif
7982 #if defined(TODO_USER_ONLY)
7983 /* MPC564 */
7984 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
7985 #endif
7986 #if defined(TODO_USER_ONLY)
7987 /* MPC565 */
7988 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
7989 #endif
7990 #if defined(TODO_USER_ONLY)
7991 /* MPC566 */
7992 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
7993 #endif
7994 /* MPC8xx family (aka PowerQUICC) */
7995 #if defined(TODO_USER_ONLY)
7996 /* Generic MPC8xx core */
7997 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
7998 #endif
7999 #if defined(TODO_USER_ONLY)
8000 /* Codename for MPC8xx core */
8001 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
8002 #endif
8003 /* MPC8xx microcontrollers */
8004 #if defined(TODO_USER_ONLY)
8005 /* MGT823 */
8006 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
8007 #endif
8008 #if defined(TODO_USER_ONLY)
8009 /* MPC821 */
8010 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
8011 #endif
8012 #if defined(TODO_USER_ONLY)
8013 /* MPC823 */
8014 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
8015 #endif
8016 #if defined(TODO_USER_ONLY)
8017 /* MPC850 */
8018 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
8019 #endif
8020 #if defined(TODO_USER_ONLY)
8021 /* MPC852T */
8022 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
8023 #endif
8024 #if defined(TODO_USER_ONLY)
8025 /* MPC855T */
8026 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
8027 #endif
8028 #if defined(TODO_USER_ONLY)
8029 /* MPC857 */
8030 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
8031 #endif
8032 #if defined(TODO_USER_ONLY)
8033 /* MPC859 */
8034 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
8035 #endif
8036 #if defined(TODO_USER_ONLY)
8037 /* MPC860 */
8038 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
8039 #endif
8040 #if defined(TODO_USER_ONLY)
8041 /* MPC862 */
8042 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
8043 #endif
8044 #if defined(TODO_USER_ONLY)
8045 /* MPC866 */
8046 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
8047 #endif
8048 #if defined(TODO_USER_ONLY)
8049 /* MPC870 */
8050 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
8051 #endif
8052 #if defined(TODO_USER_ONLY)
8053 /* MPC875 */
8054 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
8055 #endif
8056 #if defined(TODO_USER_ONLY)
8057 /* MPC880 */
8058 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
8059 #endif
8060 #if defined(TODO_USER_ONLY)
8061 /* MPC885 */
8062 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
8063 #endif
8064 /* MPC82xx family (aka PowerQUICC-II) */
8065 /* Generic MPC52xx core */
8066 POWERPC_DEF_SVR("MPC52xx",
8067 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
8068 /* Generic MPC82xx core */
8069 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
8070 /* Codename for MPC82xx */
8071 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
8072 /* PowerPC G2 core */
8073 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
8074 /* PowerPC G2 H4 core */
8075 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
8076 /* PowerPC G2 GP core */
8077 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
8078 /* PowerPC G2 LS core */
8079 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
8080 /* PowerPC G2 HiP3 core */
8081 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
8082 /* PowerPC G2 HiP4 core */
8083 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
8084 /* PowerPC MPC603 core */
8085 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
8086 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
8087 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
8088 /* PowerPC G2LE GP core */
8089 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
8090 /* PowerPC G2LE LS core */
8091 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
8092 /* PowerPC G2LE GP1 core */
8093 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
8094 /* PowerPC G2LE GP3 core */
8095 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
8096 /* PowerPC MPC603 microcontrollers */
8097 /* MPC8240 */
8098 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
8099 /* PowerPC G2 microcontrollers */
8100 #if defined(TODO)
8101 /* MPC5121 */
8102 POWERPC_DEF_SVR("MPC5121",
8103 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
8104 #endif
8105 /* MPC5200 */
8106 POWERPC_DEF_SVR("MPC5200",
8107 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
8108 /* MPC5200 v1.0 */
8109 POWERPC_DEF_SVR("MPC5200_v10",
8110 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
8111 /* MPC5200 v1.1 */
8112 POWERPC_DEF_SVR("MPC5200_v11",
8113 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
8114 /* MPC5200 v1.2 */
8115 POWERPC_DEF_SVR("MPC5200_v12",
8116 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
8117 /* MPC5200B */
8118 POWERPC_DEF_SVR("MPC5200B",
8119 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
8120 /* MPC5200B v2.0 */
8121 POWERPC_DEF_SVR("MPC5200B_v20",
8122 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
8123 /* MPC5200B v2.1 */
8124 POWERPC_DEF_SVR("MPC5200B_v21",
8125 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
8126 /* MPC8241 */
8127 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
8128 /* MPC8245 */
8129 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
8130 /* MPC8247 */
8131 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
8132 /* MPC8248 */
8133 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
8134 /* MPC8250 */
8135 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
8136 /* MPC8250 HiP3 */
8137 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
8138 /* MPC8250 HiP4 */
8139 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
8140 /* MPC8255 */
8141 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
8142 /* MPC8255 HiP3 */
8143 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
8144 /* MPC8255 HiP4 */
8145 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
8146 /* MPC8260 */
8147 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
8148 /* MPC8260 HiP3 */
8149 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
8150 /* MPC8260 HiP4 */
8151 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
8152 /* MPC8264 */
8153 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
8154 /* MPC8264 HiP3 */
8155 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
8156 /* MPC8264 HiP4 */
8157 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
8158 /* MPC8265 */
8159 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
8160 /* MPC8265 HiP3 */
8161 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
8162 /* MPC8265 HiP4 */
8163 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
8164 /* MPC8266 */
8165 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
8166 /* MPC8266 HiP3 */
8167 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
8168 /* MPC8266 HiP4 */
8169 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
8170 /* MPC8270 */
8171 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
8172 /* MPC8271 */
8173 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
8174 /* MPC8272 */
8175 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
8176 /* MPC8275 */
8177 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
8178 /* MPC8280 */
8179 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
8180 /* e200 family */
8181 /* Generic PowerPC e200 core */
8182 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
8183 /* Generic MPC55xx core */
8184 #if defined (TODO)
8185 POWERPC_DEF_SVR("MPC55xx",
8186 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
8187 #endif
8188 #if defined (TODO)
8189 /* PowerPC e200z0 core */
8190 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
8191 #endif
8192 #if defined (TODO)
8193 /* PowerPC e200z1 core */
8194 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
8195 #endif
8196 #if defined (TODO)
8197 /* PowerPC e200z3 core */
8198 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
8199 #endif
8200 /* PowerPC e200z5 core */
8201 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
8202 /* PowerPC e200z6 core */
8203 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
8204 /* PowerPC e200 microcontrollers */
8205 #if defined (TODO)
8206 /* MPC5514E */
8207 POWERPC_DEF_SVR("MPC5514E",
8208 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
8209 #endif
8210 #if defined (TODO)
8211 /* MPC5514E v0 */
8212 POWERPC_DEF_SVR("MPC5514E_v0",
8213 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
8214 #endif
8215 #if defined (TODO)
8216 /* MPC5514E v1 */
8217 POWERPC_DEF_SVR("MPC5514E_v1",
8218 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
8219 #endif
8220 #if defined (TODO)
8221 /* MPC5514G */
8222 POWERPC_DEF_SVR("MPC5514G",
8223 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
8224 #endif
8225 #if defined (TODO)
8226 /* MPC5514G v0 */
8227 POWERPC_DEF_SVR("MPC5514G_v0",
8228 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
8229 #endif
8230 #if defined (TODO)
8231 /* MPC5514G v1 */
8232 POWERPC_DEF_SVR("MPC5514G_v1",
8233 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
8234 #endif
8235 #if defined (TODO)
8236 /* MPC5515S */
8237 POWERPC_DEF_SVR("MPC5515S",
8238 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
8239 #endif
8240 #if defined (TODO)
8241 /* MPC5516E */
8242 POWERPC_DEF_SVR("MPC5516E",
8243 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
8244 #endif
8245 #if defined (TODO)
8246 /* MPC5516E v0 */
8247 POWERPC_DEF_SVR("MPC5516E_v0",
8248 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
8249 #endif
8250 #if defined (TODO)
8251 /* MPC5516E v1 */
8252 POWERPC_DEF_SVR("MPC5516E_v1",
8253 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
8254 #endif
8255 #if defined (TODO)
8256 /* MPC5516G */
8257 POWERPC_DEF_SVR("MPC5516G",
8258 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
8259 #endif
8260 #if defined (TODO)
8261 /* MPC5516G v0 */
8262 POWERPC_DEF_SVR("MPC5516G_v0",
8263 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
8264 #endif
8265 #if defined (TODO)
8266 /* MPC5516G v1 */
8267 POWERPC_DEF_SVR("MPC5516G_v1",
8268 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
8269 #endif
8270 #if defined (TODO)
8271 /* MPC5516S */
8272 POWERPC_DEF_SVR("MPC5516S",
8273 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
8274 #endif
8275 #if defined (TODO)
8276 /* MPC5533 */
8277 POWERPC_DEF_SVR("MPC5533",
8278 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
8279 #endif
8280 #if defined (TODO)
8281 /* MPC5534 */
8282 POWERPC_DEF_SVR("MPC5534",
8283 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
8284 #endif
8285 #if defined (TODO)
8286 /* MPC5553 */
8287 POWERPC_DEF_SVR("MPC5553",
8288 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
8289 #endif
8290 #if defined (TODO)
8291 /* MPC5554 */
8292 POWERPC_DEF_SVR("MPC5554",
8293 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
8294 #endif
8295 #if defined (TODO)
8296 /* MPC5561 */
8297 POWERPC_DEF_SVR("MPC5561",
8298 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
8299 #endif
8300 #if defined (TODO)
8301 /* MPC5565 */
8302 POWERPC_DEF_SVR("MPC5565",
8303 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
8304 #endif
8305 #if defined (TODO)
8306 /* MPC5566 */
8307 POWERPC_DEF_SVR("MPC5566",
8308 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
8309 #endif
8310 #if defined (TODO)
8311 /* MPC5567 */
8312 POWERPC_DEF_SVR("MPC5567",
8313 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
8314 #endif
8315 /* e300 family */
8316 /* Generic PowerPC e300 core */
8317 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
8318 /* PowerPC e300c1 core */
8319 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
8320 /* PowerPC e300c2 core */
8321 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
8322 /* PowerPC e300c3 core */
8323 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
8324 /* PowerPC e300c4 core */
8325 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
8326 /* PowerPC e300 microcontrollers */
8327 #if defined (TODO)
8328 /* MPC8313 */
8329 POWERPC_DEF_SVR("MPC8313",
8330 CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300),
8331 #endif
8332 #if defined (TODO)
8333 /* MPC8313E */
8334 POWERPC_DEF_SVR("MPC8313E",
8335 CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300),
8336 #endif
8337 #if defined (TODO)
8338 /* MPC8314 */
8339 POWERPC_DEF_SVR("MPC8314",
8340 CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300),
8341 #endif
8342 #if defined (TODO)
8343 /* MPC8314E */
8344 POWERPC_DEF_SVR("MPC8314E",
8345 CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300),
8346 #endif
8347 #if defined (TODO)
8348 /* MPC8315 */
8349 POWERPC_DEF_SVR("MPC8315",
8350 CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300),
8351 #endif
8352 #if defined (TODO)
8353 /* MPC8315E */
8354 POWERPC_DEF_SVR("MPC8315E",
8355 CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300),
8356 #endif
8357 #if defined (TODO)
8358 /* MPC8321 */
8359 POWERPC_DEF_SVR("MPC8321",
8360 CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300),
8361 #endif
8362 #if defined (TODO)
8363 /* MPC8321E */
8364 POWERPC_DEF_SVR("MPC8321E",
8365 CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300),
8366 #endif
8367 #if defined (TODO)
8368 /* MPC8323 */
8369 POWERPC_DEF_SVR("MPC8323",
8370 CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300),
8371 #endif
8372 #if defined (TODO)
8373 /* MPC8323E */
8374 POWERPC_DEF_SVR("MPC8323E",
8375 CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300),
8376 #endif
8377 /* MPC8343 */
8378 POWERPC_DEF_SVR("MPC8343",
8379 CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300),
8380 /* MPC8343A */
8381 POWERPC_DEF_SVR("MPC8343A",
8382 CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300),
8383 /* MPC8343E */
8384 POWERPC_DEF_SVR("MPC8343E",
8385 CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300),
8386 /* MPC8343EA */
8387 POWERPC_DEF_SVR("MPC8343EA",
8388 CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300),
8389 /* MPC8347 */
8390 POWERPC_DEF_SVR("MPC8347",
8391 CPU_POWERPC_MPC834x, POWERPC_SVR_8347, e300),
8392 /* MPC8347T */
8393 POWERPC_DEF_SVR("MPC8347T",
8394 CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300),
8395 /* MPC8347P */
8396 POWERPC_DEF_SVR("MPC8347P",
8397 CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300),
8398 /* MPC8347A */
8399 POWERPC_DEF_SVR("MPC8347A",
8400 CPU_POWERPC_MPC834x, POWERPC_SVR_8347A, e300),
8401 /* MPC8347AT */
8402 POWERPC_DEF_SVR("MPC8347AT",
8403 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300),
8404 /* MPC8347AP */
8405 POWERPC_DEF_SVR("MPC8347AP",
8406 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300),
8407 /* MPC8347E */
8408 POWERPC_DEF_SVR("MPC8347E",
8409 CPU_POWERPC_MPC834x, POWERPC_SVR_8347E, e300),
8410 /* MPC8347ET */
8411 POWERPC_DEF_SVR("MPC8347ET",
8412 CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300),
8413 /* MPC8343EP */
8414 POWERPC_DEF_SVR("MPC8347EP",
8415 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300),
8416 /* MPC8347EA */
8417 POWERPC_DEF_SVR("MPC8347EA",
8418 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EA, e300),
8419 /* MPC8347EAT */
8420 POWERPC_DEF_SVR("MPC8347EAT",
8421 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300),
8422 /* MPC8343EAP */
8423 POWERPC_DEF_SVR("MPC8347EAP",
8424 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300),
8425 /* MPC8349 */
8426 POWERPC_DEF_SVR("MPC8349",
8427 CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300),
8428 /* MPC8349A */
8429 POWERPC_DEF_SVR("MPC8349A",
8430 CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300),
8431 /* MPC8349E */
8432 POWERPC_DEF_SVR("MPC8349E",
8433 CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300),
8434 /* MPC8349EA */
8435 POWERPC_DEF_SVR("MPC8349EA",
8436 CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300),
8437 #if defined (TODO)
8438 /* MPC8358E */
8439 POWERPC_DEF_SVR("MPC8358E",
8440 CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300),
8441 #endif
8442 #if defined (TODO)
8443 /* MPC8360E */
8444 POWERPC_DEF_SVR("MPC8360E",
8445 CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300),
8446 #endif
8447 /* MPC8377 */
8448 POWERPC_DEF_SVR("MPC8377",
8449 CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300),
8450 /* MPC8377E */
8451 POWERPC_DEF_SVR("MPC8377E",
8452 CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300),
8453 /* MPC8378 */
8454 POWERPC_DEF_SVR("MPC8378",
8455 CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300),
8456 /* MPC8378E */
8457 POWERPC_DEF_SVR("MPC8378E",
8458 CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300),
8459 /* MPC8379 */
8460 POWERPC_DEF_SVR("MPC8379",
8461 CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300),
8462 /* MPC8379E */
8463 POWERPC_DEF_SVR("MPC8379E",
8464 CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300),
8465 /* e500 family */
8466 /* PowerPC e500 core */
8467 POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
8468 /* PowerPC e500v1 core */
8469 POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
8470 /* PowerPC e500 v1.0 core */
8471 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
8472 /* PowerPC e500 v2.0 core */
8473 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
8474 /* PowerPC e500v2 core */
8475 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
8476 /* PowerPC e500v2 v1.0 core */
8477 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
8478 /* PowerPC e500v2 v2.0 core */
8479 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
8480 /* PowerPC e500v2 v2.1 core */
8481 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
8482 /* PowerPC e500v2 v2.2 core */
8483 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
8484 /* PowerPC e500v2 v3.0 core */
8485 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
8486 /* PowerPC e500 microcontrollers */
8487 /* MPC8533 */
8488 POWERPC_DEF_SVR("MPC8533",
8489 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2),
8490 /* MPC8533 v1.0 */
8491 POWERPC_DEF_SVR("MPC8533_v10",
8492 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2),
8493 /* MPC8533 v1.1 */
8494 POWERPC_DEF_SVR("MPC8533_v11",
8495 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2),
8496 /* MPC8533E */
8497 POWERPC_DEF_SVR("MPC8533E",
8498 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2),
8499 /* MPC8533E v1.0 */
8500 POWERPC_DEF_SVR("MPC8533E_v10",
8501 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
8502 POWERPC_DEF_SVR("MPC8533E_v11",
8503 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
8504 /* MPC8540 */
8505 POWERPC_DEF_SVR("MPC8540",
8506 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1),
8507 /* MPC8540 v1.0 */
8508 POWERPC_DEF_SVR("MPC8540_v10",
8509 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1),
8510 /* MPC8540 v2.0 */
8511 POWERPC_DEF_SVR("MPC8540_v20",
8512 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1),
8513 /* MPC8540 v2.1 */
8514 POWERPC_DEF_SVR("MPC8540_v21",
8515 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1),
8516 /* MPC8541 */
8517 POWERPC_DEF_SVR("MPC8541",
8518 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1),
8519 /* MPC8541 v1.0 */
8520 POWERPC_DEF_SVR("MPC8541_v10",
8521 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1),
8522 /* MPC8541 v1.1 */
8523 POWERPC_DEF_SVR("MPC8541_v11",
8524 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1),
8525 /* MPC8541E */
8526 POWERPC_DEF_SVR("MPC8541E",
8527 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1),
8528 /* MPC8541E v1.0 */
8529 POWERPC_DEF_SVR("MPC8541E_v10",
8530 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
8531 /* MPC8541E v1.1 */
8532 POWERPC_DEF_SVR("MPC8541E_v11",
8533 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
8534 /* MPC8543 */
8535 POWERPC_DEF_SVR("MPC8543",
8536 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2),
8537 /* MPC8543 v1.0 */
8538 POWERPC_DEF_SVR("MPC8543_v10",
8539 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2),
8540 /* MPC8543 v1.1 */
8541 POWERPC_DEF_SVR("MPC8543_v11",
8542 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2),
8543 /* MPC8543 v2.0 */
8544 POWERPC_DEF_SVR("MPC8543_v20",
8545 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2),
8546 /* MPC8543 v2.1 */
8547 POWERPC_DEF_SVR("MPC8543_v21",
8548 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2),
8549 /* MPC8543E */
8550 POWERPC_DEF_SVR("MPC8543E",
8551 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2),
8552 /* MPC8543E v1.0 */
8553 POWERPC_DEF_SVR("MPC8543E_v10",
8554 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
8555 /* MPC8543E v1.1 */
8556 POWERPC_DEF_SVR("MPC8543E_v11",
8557 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
8558 /* MPC8543E v2.0 */
8559 POWERPC_DEF_SVR("MPC8543E_v20",
8560 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
8561 /* MPC8543E v2.1 */
8562 POWERPC_DEF_SVR("MPC8543E_v21",
8563 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
8564 /* MPC8544 */
8565 POWERPC_DEF_SVR("MPC8544",
8566 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2),
8567 /* MPC8544 v1.0 */
8568 POWERPC_DEF_SVR("MPC8544_v10",
8569 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2),
8570 /* MPC8544 v1.1 */
8571 POWERPC_DEF_SVR("MPC8544_v11",
8572 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2),
8573 /* MPC8544E */
8574 POWERPC_DEF_SVR("MPC8544E",
8575 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2),
8576 /* MPC8544E v1.0 */
8577 POWERPC_DEF_SVR("MPC8544E_v10",
8578 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
8579 /* MPC8544E v1.1 */
8580 POWERPC_DEF_SVR("MPC8544E_v11",
8581 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
8582 /* MPC8545 */
8583 POWERPC_DEF_SVR("MPC8545",
8584 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2),
8585 /* MPC8545 v2.0 */
8586 POWERPC_DEF_SVR("MPC8545_v20",
8587 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2),
8588 /* MPC8545 v2.1 */
8589 POWERPC_DEF_SVR("MPC8545_v21",
8590 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2),
8591 /* MPC8545E */
8592 POWERPC_DEF_SVR("MPC8545E",
8593 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2),
8594 /* MPC8545E v2.0 */
8595 POWERPC_DEF_SVR("MPC8545E_v20",
8596 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
8597 /* MPC8545E v2.1 */
8598 POWERPC_DEF_SVR("MPC8545E_v21",
8599 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
8600 /* MPC8547E */
8601 POWERPC_DEF_SVR("MPC8547E",
8602 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2),
8603 /* MPC8547E v2.0 */
8604 POWERPC_DEF_SVR("MPC8547E_v20",
8605 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
8606 /* MPC8547E v2.1 */
8607 POWERPC_DEF_SVR("MPC8547E_v21",
8608 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
8609 /* MPC8548 */
8610 POWERPC_DEF_SVR("MPC8548",
8611 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2),
8612 /* MPC8548 v1.0 */
8613 POWERPC_DEF_SVR("MPC8548_v10",
8614 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2),
8615 /* MPC8548 v1.1 */
8616 POWERPC_DEF_SVR("MPC8548_v11",
8617 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2),
8618 /* MPC8548 v2.0 */
8619 POWERPC_DEF_SVR("MPC8548_v20",
8620 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2),
8621 /* MPC8548 v2.1 */
8622 POWERPC_DEF_SVR("MPC8548_v21",
8623 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2),
8624 /* MPC8548E */
8625 POWERPC_DEF_SVR("MPC8548E",
8626 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2),
8627 /* MPC8548E v1.0 */
8628 POWERPC_DEF_SVR("MPC8548E_v10",
8629 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
8630 /* MPC8548E v1.1 */
8631 POWERPC_DEF_SVR("MPC8548E_v11",
8632 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
8633 /* MPC8548E v2.0 */
8634 POWERPC_DEF_SVR("MPC8548E_v20",
8635 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
8636 /* MPC8548E v2.1 */
8637 POWERPC_DEF_SVR("MPC8548E_v21",
8638 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
8639 /* MPC8555 */
8640 POWERPC_DEF_SVR("MPC8555",
8641 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2),
8642 /* MPC8555 v1.0 */
8643 POWERPC_DEF_SVR("MPC8555_v10",
8644 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2),
8645 /* MPC8555 v1.1 */
8646 POWERPC_DEF_SVR("MPC8555_v11",
8647 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2),
8648 /* MPC8555E */
8649 POWERPC_DEF_SVR("MPC8555E",
8650 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2),
8651 /* MPC8555E v1.0 */
8652 POWERPC_DEF_SVR("MPC8555E_v10",
8653 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
8654 /* MPC8555E v1.1 */
8655 POWERPC_DEF_SVR("MPC8555E_v11",
8656 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
8657 /* MPC8560 */
8658 POWERPC_DEF_SVR("MPC8560",
8659 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2),
8660 /* MPC8560 v1.0 */
8661 POWERPC_DEF_SVR("MPC8560_v10",
8662 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2),
8663 /* MPC8560 v2.0 */
8664 POWERPC_DEF_SVR("MPC8560_v20",
8665 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2),
8666 /* MPC8560 v2.1 */
8667 POWERPC_DEF_SVR("MPC8560_v21",
8668 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2),
8669 /* MPC8567 */
8670 POWERPC_DEF_SVR("MPC8567",
8671 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2),
8672 /* MPC8567E */
8673 POWERPC_DEF_SVR("MPC8567E",
8674 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2),
8675 /* MPC8568 */
8676 POWERPC_DEF_SVR("MPC8568",
8677 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2),
8678 /* MPC8568E */
8679 POWERPC_DEF_SVR("MPC8568E",
8680 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2),
8681 /* MPC8572 */
8682 POWERPC_DEF_SVR("MPC8572",
8683 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2),
8684 /* MPC8572E */
8685 POWERPC_DEF_SVR("MPC8572E",
8686 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
8687 /* e600 family */
8688 /* PowerPC e600 core */
8689 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
8690 /* PowerPC e600 microcontrollers */
8691 #if defined (TODO)
8692 /* MPC8610 */
8693 POWERPC_DEF_SVR("MPC8610",
8694 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
8695 #endif
8696 /* MPC8641 */
8697 POWERPC_DEF_SVR("MPC8641",
8698 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
8699 /* MPC8641D */
8700 POWERPC_DEF_SVR("MPC8641D",
8701 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
8702 /* 32 bits "classic" PowerPC */
8703 /* PowerPC 6xx family */
8704 /* PowerPC 601 */
8705 POWERPC_DEF("601", CPU_POWERPC_601, 601v),
8706 /* PowerPC 601v0 */
8707 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
8708 /* PowerPC 601v1 */
8709 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
8710 /* PowerPC 601v */
8711 POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
8712 /* PowerPC 601v2 */
8713 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
8714 /* PowerPC 602 */
8715 POWERPC_DEF("602", CPU_POWERPC_602, 602),
8716 /* PowerPC 603 */
8717 POWERPC_DEF("603", CPU_POWERPC_603, 603),
8718 /* Code name for PowerPC 603 */
8719 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
8720 /* PowerPC 603e (aka PID6) */
8721 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
8722 /* Code name for PowerPC 603e */
8723 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
8724 /* PowerPC 603e v1.1 */
8725 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
8726 /* PowerPC 603e v1.2 */
8727 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
8728 /* PowerPC 603e v1.3 */
8729 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
8730 /* PowerPC 603e v1.4 */
8731 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
8732 /* PowerPC 603e v2.2 */
8733 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
8734 /* PowerPC 603e v3 */
8735 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
8736 /* PowerPC 603e v4 */
8737 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
8738 /* PowerPC 603e v4.1 */
8739 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
8740 /* PowerPC 603e (aka PID7) */
8741 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
8742 /* PowerPC 603e7t */
8743 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
8744 /* PowerPC 603e7v */
8745 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
8746 /* Code name for PowerPC 603ev */
8747 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
8748 /* PowerPC 603e7v1 */
8749 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
8750 /* PowerPC 603e7v2 */
8751 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
8752 /* PowerPC 603p (aka PID7v) */
8753 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
8754 /* PowerPC 603r (aka PID7t) */
8755 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
8756 /* Code name for PowerPC 603r */
8757 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
8758 /* PowerPC 604 */
8759 POWERPC_DEF("604", CPU_POWERPC_604, 604),
8760 /* PowerPC 604e (aka PID9) */
8761 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
8762 /* Code name for PowerPC 604e */
8763 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
8764 /* PowerPC 604e v1.0 */
8765 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
8766 /* PowerPC 604e v2.2 */
8767 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
8768 /* PowerPC 604e v2.4 */
8769 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
8770 /* PowerPC 604r (aka PIDA) */
8771 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
8772 /* Code name for PowerPC 604r */
8773 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
8774 #if defined(TODO)
8775 /* PowerPC 604ev */
8776 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
8777 #endif
8778 /* PowerPC 7xx family */
8779 /* Generic PowerPC 740 (G3) */
8780 POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
8781 /* Code name for PowerPC 740 */
8782 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
8783 /* Generic PowerPC 750 (G3) */
8784 POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
8785 /* Code name for PowerPC 750 */
8786 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
8787 /* PowerPC 740/750 is also known as G3 */
8788 POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
8789 /* PowerPC 740 v1.0 (G3) */
8790 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
8791 /* PowerPC 750 v1.0 (G3) */
8792 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
8793 /* PowerPC 740 v2.0 (G3) */
8794 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
8795 /* PowerPC 750 v2.0 (G3) */
8796 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
8797 /* PowerPC 740 v2.1 (G3) */
8798 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
8799 /* PowerPC 750 v2.1 (G3) */
8800 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
8801 /* PowerPC 740 v2.2 (G3) */
8802 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
8803 /* PowerPC 750 v2.2 (G3) */
8804 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
8805 /* PowerPC 740 v3.0 (G3) */
8806 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
8807 /* PowerPC 750 v3.0 (G3) */
8808 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
8809 /* PowerPC 740 v3.1 (G3) */
8810 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
8811 /* PowerPC 750 v3.1 (G3) */
8812 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
8813 /* PowerPC 740E (G3) */
8814 POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
8815 /* PowerPC 750E (G3) */
8816 POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
8817 /* PowerPC 740P (G3) */
8818 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
8819 /* PowerPC 750P (G3) */
8820 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
8821 /* Code name for PowerPC 740P/750P (G3) */
8822 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
8823 /* PowerPC 750CL (G3 embedded) */
8824 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
8825 /* PowerPC 750CL v1.0 */
8826 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
8827 /* PowerPC 750CL v2.0 */
8828 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
8829 /* PowerPC 750CX (G3 embedded) */
8830 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
8831 /* PowerPC 750CX v1.0 (G3 embedded) */
8832 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
8833 /* PowerPC 750CX v2.1 (G3 embedded) */
8834 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
8835 /* PowerPC 750CX v2.1 (G3 embedded) */
8836 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
8837 /* PowerPC 750CX v2.2 (G3 embedded) */
8838 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
8839 /* PowerPC 750CXe (G3 embedded) */
8840 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
8841 /* PowerPC 750CXe v2.1 (G3 embedded) */
8842 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
8843 /* PowerPC 750CXe v2.2 (G3 embedded) */
8844 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
8845 /* PowerPC 750CXe v2.3 (G3 embedded) */
8846 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
8847 /* PowerPC 750CXe v2.4 (G3 embedded) */
8848 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
8849 /* PowerPC 750CXe v2.4b (G3 embedded) */
8850 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
8851 /* PowerPC 750CXe v3.0 (G3 embedded) */
8852 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
8853 /* PowerPC 750CXe v3.1 (G3 embedded) */
8854 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
8855 /* PowerPC 750CXe v3.1b (G3 embedded) */
8856 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
8857 /* PowerPC 750CXr (G3 embedded) */
8858 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
8859 /* PowerPC 750FL (G3 embedded) */
8860 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
8861 /* PowerPC 750FX (G3 embedded) */
8862 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
8863 /* PowerPC 750FX v1.0 (G3 embedded) */
8864 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
8865 /* PowerPC 750FX v2.0 (G3 embedded) */
8866 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
8867 /* PowerPC 750FX v2.1 (G3 embedded) */
8868 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
8869 /* PowerPC 750FX v2.2 (G3 embedded) */
8870 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
8871 /* PowerPC 750FX v2.3 (G3 embedded) */
8872 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
8873 /* PowerPC 750GL (G3 embedded) */
8874 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
8875 /* PowerPC 750GX (G3 embedded) */
8876 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
8877 /* PowerPC 750GX v1.0 (G3 embedded) */
8878 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
8879 /* PowerPC 750GX v1.1 (G3 embedded) */
8880 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
8881 /* PowerPC 750GX v1.2 (G3 embedded) */
8882 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
8883 /* PowerPC 750L (G3 embedded) */
8884 POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
8885 /* Code name for PowerPC 750L (G3 embedded) */
8886 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
8887 /* PowerPC 750L v2.0 (G3 embedded) */
8888 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
8889 /* PowerPC 750L v2.1 (G3 embedded) */
8890 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
8891 /* PowerPC 750L v2.2 (G3 embedded) */
8892 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
8893 /* PowerPC 750L v3.0 (G3 embedded) */
8894 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
8895 /* PowerPC 750L v3.2 (G3 embedded) */
8896 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
8897 /* Generic PowerPC 745 */
8898 POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
8899 /* Generic PowerPC 755 */
8900 POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
8901 /* Code name for PowerPC 745/755 */
8902 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
8903 /* PowerPC 745 v1.0 */
8904 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
8905 /* PowerPC 755 v1.0 */
8906 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
8907 /* PowerPC 745 v1.1 */
8908 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
8909 /* PowerPC 755 v1.1 */
8910 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
8911 /* PowerPC 745 v2.0 */
8912 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
8913 /* PowerPC 755 v2.0 */
8914 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
8915 /* PowerPC 745 v2.1 */
8916 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
8917 /* PowerPC 755 v2.1 */
8918 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
8919 /* PowerPC 745 v2.2 */
8920 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
8921 /* PowerPC 755 v2.2 */
8922 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
8923 /* PowerPC 745 v2.3 */
8924 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
8925 /* PowerPC 755 v2.3 */
8926 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
8927 /* PowerPC 745 v2.4 */
8928 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
8929 /* PowerPC 755 v2.4 */
8930 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
8931 /* PowerPC 745 v2.5 */
8932 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
8933 /* PowerPC 755 v2.5 */
8934 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
8935 /* PowerPC 745 v2.6 */
8936 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
8937 /* PowerPC 755 v2.6 */
8938 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
8939 /* PowerPC 745 v2.7 */
8940 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
8941 /* PowerPC 755 v2.7 */
8942 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
8943 /* PowerPC 745 v2.8 */
8944 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
8945 /* PowerPC 755 v2.8 */
8946 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
8947 #if defined (TODO)
8948 /* PowerPC 745P (G3) */
8949 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
8950 /* PowerPC 755P (G3) */
8951 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
8952 #endif
8953 /* PowerPC 74xx family */
8954 /* PowerPC 7400 (G4) */
8955 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
8956 /* Code name for PowerPC 7400 */
8957 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
8958 /* PowerPC 74xx is also well known as G4 */
8959 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
8960 /* PowerPC 7400 v1.0 (G4) */
8961 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
8962 /* PowerPC 7400 v1.1 (G4) */
8963 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
8964 /* PowerPC 7400 v2.0 (G4) */
8965 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
8966 /* PowerPC 7400 v2.1 (G4) */
8967 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
8968 /* PowerPC 7400 v2.2 (G4) */
8969 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
8970 /* PowerPC 7400 v2.6 (G4) */
8971 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
8972 /* PowerPC 7400 v2.7 (G4) */
8973 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
8974 /* PowerPC 7400 v2.8 (G4) */
8975 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
8976 /* PowerPC 7400 v2.9 (G4) */
8977 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
8978 /* PowerPC 7410 (G4) */
8979 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
8980 /* Code name for PowerPC 7410 */
8981 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
8982 /* PowerPC 7410 v1.0 (G4) */
8983 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
8984 /* PowerPC 7410 v1.1 (G4) */
8985 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
8986 /* PowerPC 7410 v1.2 (G4) */
8987 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
8988 /* PowerPC 7410 v1.3 (G4) */
8989 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
8990 /* PowerPC 7410 v1.4 (G4) */
8991 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
8992 /* PowerPC 7448 (G4) */
8993 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
8994 /* PowerPC 7448 v1.0 (G4) */
8995 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
8996 /* PowerPC 7448 v1.1 (G4) */
8997 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
8998 /* PowerPC 7448 v2.0 (G4) */
8999 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
9000 /* PowerPC 7448 v2.1 (G4) */
9001 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
9002 /* PowerPC 7450 (G4) */
9003 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
9004 /* Code name for PowerPC 7450 */
9005 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
9006 /* PowerPC 7450 v1.0 (G4) */
9007 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
9008 /* PowerPC 7450 v1.1 (G4) */
9009 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
9010 /* PowerPC 7450 v1.2 (G4) */
9011 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
9012 /* PowerPC 7450 v2.0 (G4) */
9013 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
9014 /* PowerPC 7450 v2.1 (G4) */
9015 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
9016 /* PowerPC 7441 (G4) */
9017 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
9018 /* PowerPC 7451 (G4) */
9019 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
9020 /* PowerPC 7441 v2.1 (G4) */
9021 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
9022 /* PowerPC 7441 v2.3 (G4) */
9023 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
9024 /* PowerPC 7451 v2.3 (G4) */
9025 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
9026 /* PowerPC 7441 v2.10 (G4) */
9027 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
9028 /* PowerPC 7451 v2.10 (G4) */
9029 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
9030 /* PowerPC 7445 (G4) */
9031 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
9032 /* PowerPC 7455 (G4) */
9033 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
9034 /* Code name for PowerPC 7445/7455 */
9035 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
9036 /* PowerPC 7445 v1.0 (G4) */
9037 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
9038 /* PowerPC 7455 v1.0 (G4) */
9039 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
9040 /* PowerPC 7445 v2.1 (G4) */
9041 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
9042 /* PowerPC 7455 v2.1 (G4) */
9043 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
9044 /* PowerPC 7445 v3.2 (G4) */
9045 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
9046 /* PowerPC 7455 v3.2 (G4) */
9047 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
9048 /* PowerPC 7445 v3.3 (G4) */
9049 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
9050 /* PowerPC 7455 v3.3 (G4) */
9051 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
9052 /* PowerPC 7445 v3.4 (G4) */
9053 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
9054 /* PowerPC 7455 v3.4 (G4) */
9055 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
9056 /* PowerPC 7447 (G4) */
9057 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
9058 /* PowerPC 7457 (G4) */
9059 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
9060 /* Code name for PowerPC 7447/7457 */
9061 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
9062 /* PowerPC 7447 v1.0 (G4) */
9063 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
9064 /* PowerPC 7457 v1.0 (G4) */
9065 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
9066 /* PowerPC 7447 v1.1 (G4) */
9067 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
9068 /* PowerPC 7457 v1.1 (G4) */
9069 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
9070 /* PowerPC 7457 v1.2 (G4) */
9071 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
9072 /* PowerPC 7447A (G4) */
9073 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
9074 /* PowerPC 7457A (G4) */
9075 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
9076 /* PowerPC 7447A v1.0 (G4) */
9077 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
9078 /* PowerPC 7457A v1.0 (G4) */
9079 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
9080 /* Code name for PowerPC 7447A/7457A */
9081 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
9082 /* PowerPC 7447A v1.1 (G4) */
9083 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
9084 /* PowerPC 7457A v1.1 (G4) */
9085 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
9086 /* PowerPC 7447A v1.2 (G4) */
9087 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
9088 /* PowerPC 7457A v1.2 (G4) */
9089 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
9090 /* 64 bits PowerPC */
9091 #if defined (TARGET_PPC64)
9092 /* PowerPC 620 */
9093 POWERPC_DEF("620", CPU_POWERPC_620, 620),
9094 /* Code name for PowerPC 620 */
9095 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
9096 #if defined (TODO)
9097 /* PowerPC 630 (POWER3) */
9098 POWERPC_DEF("630", CPU_POWERPC_630, 630),
9099 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
9100 /* Code names for POWER3 */
9101 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
9102 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
9103 #endif
9104 #if defined (TODO)
9105 /* PowerPC 631 (Power 3+) */
9106 POWERPC_DEF("631", CPU_POWERPC_631, 631),
9107 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
9108 #endif
9109 #if defined (TODO)
9110 /* POWER4 */
9111 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
9112 #endif
9113 #if defined (TODO)
9114 /* POWER4p */
9115 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
9116 #endif
9117 #if defined (TODO)
9118 /* POWER5 */
9119 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
9120 /* POWER5GR */
9121 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
9122 #endif
9123 #if defined (TODO)
9124 /* POWER5+ */
9125 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
9126 /* POWER5GS */
9127 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
9128 #endif
9129 #if defined (TODO)
9130 /* POWER6 */
9131 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
9132 /* POWER6 running in POWER5 mode */
9133 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
9134 /* POWER6A */
9135 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
9136 #endif
9137 /* POWER7 */
9138 POWERPC_DEF("POWER7", CPU_POWERPC_POWER7, POWER7),
9139 POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7),
9140 /* PowerPC 970 */
9141 POWERPC_DEF("970", CPU_POWERPC_970, 970),
9142 /* PowerPC 970FX (G5) */
9143 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
9144 /* PowerPC 970FX v1.0 (G5) */
9145 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
9146 /* PowerPC 970FX v2.0 (G5) */
9147 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
9148 /* PowerPC 970FX v2.1 (G5) */
9149 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
9150 /* PowerPC 970FX v3.0 (G5) */
9151 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
9152 /* PowerPC 970FX v3.1 (G5) */
9153 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
9154 /* PowerPC 970GX (G5) */
9155 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
9156 /* PowerPC 970MP */
9157 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
9158 /* PowerPC 970MP v1.0 */
9159 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
9160 /* PowerPC 970MP v1.1 */
9161 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
9162 #if defined (TODO)
9163 /* PowerPC Cell */
9164 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
9165 #endif
9166 #if defined (TODO)
9167 /* PowerPC Cell v1.0 */
9168 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
9169 #endif
9170 #if defined (TODO)
9171 /* PowerPC Cell v2.0 */
9172 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
9173 #endif
9174 #if defined (TODO)
9175 /* PowerPC Cell v3.0 */
9176 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
9177 #endif
9178 #if defined (TODO)
9179 /* PowerPC Cell v3.1 */
9180 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
9181 #endif
9182 #if defined (TODO)
9183 /* PowerPC Cell v3.2 */
9184 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
9185 #endif
9186 #if defined (TODO)
9187 /* RS64 (Apache/A35) */
9188 /* This one seems to support the whole POWER2 instruction set
9189 * and the PowerPC 64 one.
9190 */
9191 /* What about A10 & A30 ? */
9192 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
9193 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
9194 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
9195 #endif
9196 #if defined (TODO)
9197 /* RS64-II (NorthStar/A50) */
9198 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
9199 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
9200 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
9201 #endif
9202 #if defined (TODO)
9203 /* RS64-III (Pulsar) */
9204 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
9205 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
9206 #endif
9207 #if defined (TODO)
9208 /* RS64-IV (IceStar/IStar/SStar) */
9209 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
9210 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
9211 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
9212 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
9213 #endif
9214 #endif /* defined (TARGET_PPC64) */
9215 /* POWER */
9216 #if defined (TODO)
9217 /* Original POWER */
9218 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
9219 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
9220 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
9221 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
9222 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
9223 #endif
9224 #if defined (TODO)
9225 /* POWER2 */
9226 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
9227 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
9228 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
9229 #endif
9230 /* PA semi cores */
9231 #if defined (TODO)
9232 /* PA PA6T */
9233 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
9234 #endif
9235 /* Generic PowerPCs */
9236 #if defined (TARGET_PPC64)
9237 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
9238 #endif
9239 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
9240 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
9241 /* Fallback */
9242 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
9243 };
9244
9245 /*****************************************************************************/
9246 /* Generic CPU instantiation routine */
9247 static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
9248 {
9249 #if !defined(CONFIG_USER_ONLY)
9250 int i;
9251
9252 env->irq_inputs = NULL;
9253 /* Set all exception vectors to an invalid address */
9254 for (i = 0; i < POWERPC_EXCP_NB; i++)
9255 env->excp_vectors[i] = (target_ulong)(-1ULL);
9256 env->hreset_excp_prefix = 0x00000000;
9257 env->ivor_mask = 0x00000000;
9258 env->ivpr_mask = 0x00000000;
9259 /* Default MMU definitions */
9260 env->nb_BATs = 0;
9261 env->nb_tlb = 0;
9262 env->nb_ways = 0;
9263 env->tlb_type = TLB_NONE;
9264 #endif
9265 /* Register SPR common to all PowerPC implementations */
9266 gen_spr_generic(env);
9267 spr_register(env, SPR_PVR, "PVR",
9268 /* Linux permits userspace to read PVR */
9269 #if defined(CONFIG_LINUX_USER)
9270 &spr_read_generic,
9271 #else
9272 SPR_NOACCESS,
9273 #endif
9274 SPR_NOACCESS,
9275 &spr_read_generic, SPR_NOACCESS,
9276 def->pvr);
9277 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9278 if (def->svr != POWERPC_SVR_NONE) {
9279 if (def->svr & POWERPC_SVR_E500) {
9280 spr_register(env, SPR_E500_SVR, "SVR",
9281 SPR_NOACCESS, SPR_NOACCESS,
9282 &spr_read_generic, SPR_NOACCESS,
9283 def->svr & ~POWERPC_SVR_E500);
9284 } else {
9285 spr_register(env, SPR_SVR, "SVR",
9286 SPR_NOACCESS, SPR_NOACCESS,
9287 &spr_read_generic, SPR_NOACCESS,
9288 def->svr);
9289 }
9290 }
9291 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9292 (*def->init_proc)(env);
9293 #if !defined(CONFIG_USER_ONLY)
9294 env->excp_prefix = env->hreset_excp_prefix;
9295 #endif
9296 /* MSR bits & flags consistency checks */
9297 if (env->msr_mask & (1 << 25)) {
9298 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9299 case POWERPC_FLAG_SPE:
9300 case POWERPC_FLAG_VRE:
9301 break;
9302 default:
9303 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9304 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9305 exit(1);
9306 }
9307 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9308 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9309 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9310 exit(1);
9311 }
9312 if (env->msr_mask & (1 << 17)) {
9313 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9314 case POWERPC_FLAG_TGPR:
9315 case POWERPC_FLAG_CE:
9316 break;
9317 default:
9318 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9319 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9320 exit(1);
9321 }
9322 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9323 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9324 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9325 exit(1);
9326 }
9327 if (env->msr_mask & (1 << 10)) {
9328 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9329 POWERPC_FLAG_UBLE)) {
9330 case POWERPC_FLAG_SE:
9331 case POWERPC_FLAG_DWE:
9332 case POWERPC_FLAG_UBLE:
9333 break;
9334 default:
9335 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9336 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9337 "POWERPC_FLAG_UBLE\n");
9338 exit(1);
9339 }
9340 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9341 POWERPC_FLAG_UBLE)) {
9342 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9343 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9344 "POWERPC_FLAG_UBLE\n");
9345 exit(1);
9346 }
9347 if (env->msr_mask & (1 << 9)) {
9348 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9349 case POWERPC_FLAG_BE:
9350 case POWERPC_FLAG_DE:
9351 break;
9352 default:
9353 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9354 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9355 exit(1);
9356 }
9357 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9358 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9359 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9360 exit(1);
9361 }
9362 if (env->msr_mask & (1 << 2)) {
9363 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9364 case POWERPC_FLAG_PX:
9365 case POWERPC_FLAG_PMM:
9366 break;
9367 default:
9368 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9369 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9370 exit(1);
9371 }
9372 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9373 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9374 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9375 exit(1);
9376 }
9377 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9378 fprintf(stderr, "PowerPC flags inconsistency\n"
9379 "Should define the time-base and decrementer clock source\n");
9380 exit(1);
9381 }
9382 /* Allocate TLBs buffer when needed */
9383 #if !defined(CONFIG_USER_ONLY)
9384 if (env->nb_tlb != 0) {
9385 int nb_tlb = env->nb_tlb;
9386 if (env->id_tlbs != 0)
9387 nb_tlb *= 2;
9388 switch (env->tlb_type) {
9389 case TLB_6XX:
9390 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
9391 break;
9392 case TLB_EMB:
9393 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
9394 break;
9395 case TLB_MAS:
9396 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
9397 break;
9398 }
9399 /* Pre-compute some useful values */
9400 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9401 }
9402 if (env->irq_inputs == NULL) {
9403 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
9404 " Attempt Qemu to crash very soon !\n");
9405 }
9406 #endif
9407 if (env->check_pow == NULL) {
9408 fprintf(stderr, "WARNING: no power management check handler "
9409 "registered.\n"
9410 " Attempt Qemu to crash very soon !\n");
9411 }
9412 }
9413
9414 #if defined(PPC_DUMP_CPU)
9415 static void dump_ppc_sprs (CPUPPCState *env)
9416 {
9417 ppc_spr_t *spr;
9418 #if !defined(CONFIG_USER_ONLY)
9419 uint32_t sr, sw;
9420 #endif
9421 uint32_t ur, uw;
9422 int i, j, n;
9423
9424 printf("Special purpose registers:\n");
9425 for (i = 0; i < 32; i++) {
9426 for (j = 0; j < 32; j++) {
9427 n = (i << 5) | j;
9428 spr = &env->spr_cb[n];
9429 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9430 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9431 #if !defined(CONFIG_USER_ONLY)
9432 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9433 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9434 if (sw || sr || uw || ur) {
9435 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9436 (i << 5) | j, (i << 5) | j, spr->name,
9437 sw ? 'w' : '-', sr ? 'r' : '-',
9438 uw ? 'w' : '-', ur ? 'r' : '-');
9439 }
9440 #else
9441 if (uw || ur) {
9442 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9443 (i << 5) | j, (i << 5) | j, spr->name,
9444 uw ? 'w' : '-', ur ? 'r' : '-');
9445 }
9446 #endif
9447 }
9448 }
9449 fflush(stdout);
9450 fflush(stderr);
9451 }
9452 #endif
9453
9454 /*****************************************************************************/
9455 #include <stdlib.h>
9456 #include <string.h>
9457
9458 /* Opcode types */
9459 enum {
9460 PPC_DIRECT = 0, /* Opcode routine */
9461 PPC_INDIRECT = 1, /* Indirect opcode table */
9462 };
9463
9464 static inline int is_indirect_opcode (void *handler)
9465 {
9466 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
9467 }
9468
9469 static inline opc_handler_t **ind_table(void *handler)
9470 {
9471 return (opc_handler_t **)((unsigned long)handler & ~3);
9472 }
9473
9474 /* Instruction table creation */
9475 /* Opcodes tables creation */
9476 static void fill_new_table (opc_handler_t **table, int len)
9477 {
9478 int i;
9479
9480 for (i = 0; i < len; i++)
9481 table[i] = &invalid_handler;
9482 }
9483
9484 static int create_new_table (opc_handler_t **table, unsigned char idx)
9485 {
9486 opc_handler_t **tmp;
9487
9488 tmp = malloc(0x20 * sizeof(opc_handler_t));
9489 fill_new_table(tmp, 0x20);
9490 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
9491
9492 return 0;
9493 }
9494
9495 static int insert_in_table (opc_handler_t **table, unsigned char idx,
9496 opc_handler_t *handler)
9497 {
9498 if (table[idx] != &invalid_handler)
9499 return -1;
9500 table[idx] = handler;
9501
9502 return 0;
9503 }
9504
9505 static int register_direct_insn (opc_handler_t **ppc_opcodes,
9506 unsigned char idx, opc_handler_t *handler)
9507 {
9508 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9509 printf("*** ERROR: opcode %02x already assigned in main "
9510 "opcode table\n", idx);
9511 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9512 printf(" Registered handler '%s' - new handler '%s'\n",
9513 ppc_opcodes[idx]->oname, handler->oname);
9514 #endif
9515 return -1;
9516 }
9517
9518 return 0;
9519 }
9520
9521 static int register_ind_in_table (opc_handler_t **table,
9522 unsigned char idx1, unsigned char idx2,
9523 opc_handler_t *handler)
9524 {
9525 if (table[idx1] == &invalid_handler) {
9526 if (create_new_table(table, idx1) < 0) {
9527 printf("*** ERROR: unable to create indirect table "
9528 "idx=%02x\n", idx1);
9529 return -1;
9530 }
9531 } else {
9532 if (!is_indirect_opcode(table[idx1])) {
9533 printf("*** ERROR: idx %02x already assigned to a direct "
9534 "opcode\n", idx1);
9535 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9536 printf(" Registered handler '%s' - new handler '%s'\n",
9537 ind_table(table[idx1])[idx2]->oname, handler->oname);
9538 #endif
9539 return -1;
9540 }
9541 }
9542 if (handler != NULL &&
9543 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9544 printf("*** ERROR: opcode %02x already assigned in "
9545 "opcode table %02x\n", idx2, idx1);
9546 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9547 printf(" Registered handler '%s' - new handler '%s'\n",
9548 ind_table(table[idx1])[idx2]->oname, handler->oname);
9549 #endif
9550 return -1;
9551 }
9552
9553 return 0;
9554 }
9555
9556 static int register_ind_insn (opc_handler_t **ppc_opcodes,
9557 unsigned char idx1, unsigned char idx2,
9558 opc_handler_t *handler)
9559 {
9560 int ret;
9561
9562 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9563
9564 return ret;
9565 }
9566
9567 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9568 unsigned char idx1, unsigned char idx2,
9569 unsigned char idx3, opc_handler_t *handler)
9570 {
9571 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9572 printf("*** ERROR: unable to join indirect table idx "
9573 "[%02x-%02x]\n", idx1, idx2);
9574 return -1;
9575 }
9576 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9577 handler) < 0) {
9578 printf("*** ERROR: unable to insert opcode "
9579 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9580 return -1;
9581 }
9582
9583 return 0;
9584 }
9585
9586 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9587 {
9588 if (insn->opc2 != 0xFF) {
9589 if (insn->opc3 != 0xFF) {
9590 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9591 insn->opc3, &insn->handler) < 0)
9592 return -1;
9593 } else {
9594 if (register_ind_insn(ppc_opcodes, insn->opc1,
9595 insn->opc2, &insn->handler) < 0)
9596 return -1;
9597 }
9598 } else {
9599 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9600 return -1;
9601 }
9602
9603 return 0;
9604 }
9605
9606 static int test_opcode_table (opc_handler_t **table, int len)
9607 {
9608 int i, count, tmp;
9609
9610 for (i = 0, count = 0; i < len; i++) {
9611 /* Consistency fixup */
9612 if (table[i] == NULL)
9613 table[i] = &invalid_handler;
9614 if (table[i] != &invalid_handler) {
9615 if (is_indirect_opcode(table[i])) {
9616 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9617 if (tmp == 0) {
9618 free(table[i]);
9619 table[i] = &invalid_handler;
9620 } else {
9621 count++;
9622 }
9623 } else {
9624 count++;
9625 }
9626 }
9627 }
9628
9629 return count;
9630 }
9631
9632 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9633 {
9634 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9635 printf("*** WARNING: no opcode defined !\n");
9636 }
9637
9638 /*****************************************************************************/
9639 static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
9640 {
9641 opcode_t *opc;
9642
9643 fill_new_table(env->opcodes, 0x40);
9644 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9645 if (((opc->handler.type & def->insns_flags) != 0) ||
9646 ((opc->handler.type2 & def->insns_flags2) != 0)) {
9647 if (register_insn(env->opcodes, opc) < 0) {
9648 printf("*** ERROR initializing PowerPC instruction "
9649 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9650 opc->opc3);
9651 return -1;
9652 }
9653 }
9654 }
9655 fix_opcode_tables(env->opcodes);
9656 fflush(stdout);
9657 fflush(stderr);
9658
9659 return 0;
9660 }
9661
9662 #if defined(PPC_DUMP_CPU)
9663 static void dump_ppc_insns (CPUPPCState *env)
9664 {
9665 opc_handler_t **table, *handler;
9666 const char *p, *q;
9667 uint8_t opc1, opc2, opc3;
9668
9669 printf("Instructions set:\n");
9670 /* opc1 is 6 bits long */
9671 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9672 table = env->opcodes;
9673 handler = table[opc1];
9674 if (is_indirect_opcode(handler)) {
9675 /* opc2 is 5 bits long */
9676 for (opc2 = 0; opc2 < 0x20; opc2++) {
9677 table = env->opcodes;
9678 handler = env->opcodes[opc1];
9679 table = ind_table(handler);
9680 handler = table[opc2];
9681 if (is_indirect_opcode(handler)) {
9682 table = ind_table(handler);
9683 /* opc3 is 5 bits long */
9684 for (opc3 = 0; opc3 < 0x20; opc3++) {
9685 handler = table[opc3];
9686 if (handler->handler != &gen_invalid) {
9687 /* Special hack to properly dump SPE insns */
9688 p = strchr(handler->oname, '_');
9689 if (p == NULL) {
9690 printf("INSN: %02x %02x %02x (%02d %04d) : "
9691 "%s\n",
9692 opc1, opc2, opc3, opc1,
9693 (opc3 << 5) | opc2,
9694 handler->oname);
9695 } else {
9696 q = "speundef";
9697 if ((p - handler->oname) != strlen(q) ||
9698 memcmp(handler->oname, q, strlen(q)) != 0) {
9699 /* First instruction */
9700 printf("INSN: %02x %02x %02x (%02d %04d) : "
9701 "%.*s\n",
9702 opc1, opc2 << 1, opc3, opc1,
9703 (opc3 << 6) | (opc2 << 1),
9704 (int)(p - handler->oname),
9705 handler->oname);
9706 }
9707 if (strcmp(p + 1, q) != 0) {
9708 /* Second instruction */
9709 printf("INSN: %02x %02x %02x (%02d %04d) : "
9710 "%s\n",
9711 opc1, (opc2 << 1) | 1, opc3, opc1,
9712 (opc3 << 6) | (opc2 << 1) | 1,
9713 p + 1);
9714 }
9715 }
9716 }
9717 }
9718 } else {
9719 if (handler->handler != &gen_invalid) {
9720 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9721 opc1, opc2, opc1, opc2, handler->oname);
9722 }
9723 }
9724 }
9725 } else {
9726 if (handler->handler != &gen_invalid) {
9727 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9728 opc1, opc1, handler->oname);
9729 }
9730 }
9731 }
9732 }
9733 #endif
9734
9735 static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9736 {
9737 if (n < 32) {
9738 stfq_p(mem_buf, env->fpr[n]);
9739 return 8;
9740 }
9741 if (n == 32) {
9742 stl_p(mem_buf, env->fpscr);
9743 return 4;
9744 }
9745 return 0;
9746 }
9747
9748 static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9749 {
9750 if (n < 32) {
9751 env->fpr[n] = ldfq_p(mem_buf);
9752 return 8;
9753 }
9754 if (n == 32) {
9755 /* FPSCR not implemented */
9756 return 4;
9757 }
9758 return 0;
9759 }
9760
9761 static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9762 {
9763 if (n < 32) {
9764 #ifdef HOST_WORDS_BIGENDIAN
9765 stq_p(mem_buf, env->avr[n].u64[0]);
9766 stq_p(mem_buf+8, env->avr[n].u64[1]);
9767 #else
9768 stq_p(mem_buf, env->avr[n].u64[1]);
9769 stq_p(mem_buf+8, env->avr[n].u64[0]);
9770 #endif
9771 return 16;
9772 }
9773 if (n == 32) {
9774 stl_p(mem_buf, env->vscr);
9775 return 4;
9776 }
9777 if (n == 33) {
9778 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9779 return 4;
9780 }
9781 return 0;
9782 }
9783
9784 static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9785 {
9786 if (n < 32) {
9787 #ifdef HOST_WORDS_BIGENDIAN
9788 env->avr[n].u64[0] = ldq_p(mem_buf);
9789 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9790 #else
9791 env->avr[n].u64[1] = ldq_p(mem_buf);
9792 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9793 #endif
9794 return 16;
9795 }
9796 if (n == 32) {
9797 env->vscr = ldl_p(mem_buf);
9798 return 4;
9799 }
9800 if (n == 33) {
9801 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9802 return 4;
9803 }
9804 return 0;
9805 }
9806
9807 static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9808 {
9809 if (n < 32) {
9810 #if defined(TARGET_PPC64)
9811 stl_p(mem_buf, env->gpr[n] >> 32);
9812 #else
9813 stl_p(mem_buf, env->gprh[n]);
9814 #endif
9815 return 4;
9816 }
9817 if (n == 32) {
9818 stq_p(mem_buf, env->spe_acc);
9819 return 8;
9820 }
9821 if (n == 33) {
9822 stl_p(mem_buf, env->spe_fscr);
9823 return 4;
9824 }
9825 return 0;
9826 }
9827
9828 static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9829 {
9830 if (n < 32) {
9831 #if defined(TARGET_PPC64)
9832 target_ulong lo = (uint32_t)env->gpr[n];
9833 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9834 env->gpr[n] = lo | hi;
9835 #else
9836 env->gprh[n] = ldl_p(mem_buf);
9837 #endif
9838 return 4;
9839 }
9840 if (n == 32) {
9841 env->spe_acc = ldq_p(mem_buf);
9842 return 8;
9843 }
9844 if (n == 33) {
9845 env->spe_fscr = ldl_p(mem_buf);
9846 return 4;
9847 }
9848 return 0;
9849 }
9850
9851 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
9852 {
9853 env->msr_mask = def->msr_mask;
9854 env->mmu_model = def->mmu_model;
9855 env->excp_model = def->excp_model;
9856 env->bus_model = def->bus_model;
9857 env->insns_flags = def->insns_flags;
9858 env->insns_flags2 = def->insns_flags2;
9859 env->flags = def->flags;
9860 env->bfd_mach = def->bfd_mach;
9861 env->check_pow = def->check_pow;
9862 if (create_ppc_opcodes(env, def) < 0)
9863 return -1;
9864 init_ppc_proc(env, def);
9865
9866 if (def->insns_flags & PPC_FLOAT) {
9867 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9868 33, "power-fpu.xml", 0);
9869 }
9870 if (def->insns_flags & PPC_ALTIVEC) {
9871 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9872 34, "power-altivec.xml", 0);
9873 }
9874 if (def->insns_flags & PPC_SPE) {
9875 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9876 34, "power-spe.xml", 0);
9877 }
9878
9879 #if defined(PPC_DUMP_CPU)
9880 {
9881 const char *mmu_model, *excp_model, *bus_model;
9882 switch (env->mmu_model) {
9883 case POWERPC_MMU_32B:
9884 mmu_model = "PowerPC 32";
9885 break;
9886 case POWERPC_MMU_SOFT_6xx:
9887 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9888 break;
9889 case POWERPC_MMU_SOFT_74xx:
9890 mmu_model = "PowerPC 74xx with software driven TLBs";
9891 break;
9892 case POWERPC_MMU_SOFT_4xx:
9893 mmu_model = "PowerPC 4xx with software driven TLBs";
9894 break;
9895 case POWERPC_MMU_SOFT_4xx_Z:
9896 mmu_model = "PowerPC 4xx with software driven TLBs "
9897 "and zones protections";
9898 break;
9899 case POWERPC_MMU_REAL:
9900 mmu_model = "PowerPC real mode only";
9901 break;
9902 case POWERPC_MMU_MPC8xx:
9903 mmu_model = "PowerPC MPC8xx";
9904 break;
9905 case POWERPC_MMU_BOOKE:
9906 mmu_model = "PowerPC BookE";
9907 break;
9908 case POWERPC_MMU_BOOKE206:
9909 mmu_model = "PowerPC BookE 2.06";
9910 break;
9911 case POWERPC_MMU_601:
9912 mmu_model = "PowerPC 601";
9913 break;
9914 #if defined (TARGET_PPC64)
9915 case POWERPC_MMU_64B:
9916 mmu_model = "PowerPC 64";
9917 break;
9918 case POWERPC_MMU_620:
9919 mmu_model = "PowerPC 620";
9920 break;
9921 #endif
9922 default:
9923 mmu_model = "Unknown or invalid";
9924 break;
9925 }
9926 switch (env->excp_model) {
9927 case POWERPC_EXCP_STD:
9928 excp_model = "PowerPC";
9929 break;
9930 case POWERPC_EXCP_40x:
9931 excp_model = "PowerPC 40x";
9932 break;
9933 case POWERPC_EXCP_601:
9934 excp_model = "PowerPC 601";
9935 break;
9936 case POWERPC_EXCP_602:
9937 excp_model = "PowerPC 602";
9938 break;
9939 case POWERPC_EXCP_603:
9940 excp_model = "PowerPC 603";
9941 break;
9942 case POWERPC_EXCP_603E:
9943 excp_model = "PowerPC 603e";
9944 break;
9945 case POWERPC_EXCP_604:
9946 excp_model = "PowerPC 604";
9947 break;
9948 case POWERPC_EXCP_7x0:
9949 excp_model = "PowerPC 740/750";
9950 break;
9951 case POWERPC_EXCP_7x5:
9952 excp_model = "PowerPC 745/755";
9953 break;
9954 case POWERPC_EXCP_74xx:
9955 excp_model = "PowerPC 74xx";
9956 break;
9957 case POWERPC_EXCP_BOOKE:
9958 excp_model = "PowerPC BookE";
9959 break;
9960 #if defined (TARGET_PPC64)
9961 case POWERPC_EXCP_970:
9962 excp_model = "PowerPC 970";
9963 break;
9964 #endif
9965 default:
9966 excp_model = "Unknown or invalid";
9967 break;
9968 }
9969 switch (env->bus_model) {
9970 case PPC_FLAGS_INPUT_6xx:
9971 bus_model = "PowerPC 6xx";
9972 break;
9973 case PPC_FLAGS_INPUT_BookE:
9974 bus_model = "PowerPC BookE";
9975 break;
9976 case PPC_FLAGS_INPUT_405:
9977 bus_model = "PowerPC 405";
9978 break;
9979 case PPC_FLAGS_INPUT_401:
9980 bus_model = "PowerPC 401/403";
9981 break;
9982 case PPC_FLAGS_INPUT_RCPU:
9983 bus_model = "RCPU / MPC8xx";
9984 break;
9985 #if defined (TARGET_PPC64)
9986 case PPC_FLAGS_INPUT_970:
9987 bus_model = "PowerPC 970";
9988 break;
9989 #endif
9990 default:
9991 bus_model = "Unknown or invalid";
9992 break;
9993 }
9994 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9995 " MMU model : %s\n",
9996 def->name, def->pvr, def->msr_mask, mmu_model);
9997 #if !defined(CONFIG_USER_ONLY)
9998 if (env->tlb != NULL) {
9999 printf(" %d %s TLB in %d ways\n",
10000 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
10001 env->nb_ways);
10002 }
10003 #endif
10004 printf(" Exceptions model : %s\n"
10005 " Bus model : %s\n",
10006 excp_model, bus_model);
10007 printf(" MSR features :\n");
10008 if (env->flags & POWERPC_FLAG_SPE)
10009 printf(" signal processing engine enable"
10010 "\n");
10011 else if (env->flags & POWERPC_FLAG_VRE)
10012 printf(" vector processor enable\n");
10013 if (env->flags & POWERPC_FLAG_TGPR)
10014 printf(" temporary GPRs\n");
10015 else if (env->flags & POWERPC_FLAG_CE)
10016 printf(" critical input enable\n");
10017 if (env->flags & POWERPC_FLAG_SE)
10018 printf(" single-step trace mode\n");
10019 else if (env->flags & POWERPC_FLAG_DWE)
10020 printf(" debug wait enable\n");
10021 else if (env->flags & POWERPC_FLAG_UBLE)
10022 printf(" user BTB lock enable\n");
10023 if (env->flags & POWERPC_FLAG_BE)
10024 printf(" branch-step trace mode\n");
10025 else if (env->flags & POWERPC_FLAG_DE)
10026 printf(" debug interrupt enable\n");
10027 if (env->flags & POWERPC_FLAG_PX)
10028 printf(" inclusive protection\n");
10029 else if (env->flags & POWERPC_FLAG_PMM)
10030 printf(" performance monitor mark\n");
10031 if (env->flags == POWERPC_FLAG_NONE)
10032 printf(" none\n");
10033 printf(" Time-base/decrementer clock source: %s\n",
10034 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
10035 }
10036 dump_ppc_insns(env);
10037 dump_ppc_sprs(env);
10038 fflush(stdout);
10039 #endif
10040
10041 return 0;
10042 }
10043
10044 static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
10045 {
10046 const ppc_def_t *ret;
10047 uint32_t pvr_rev;
10048 int i, best, match, best_match, max;
10049
10050 ret = NULL;
10051 max = ARRAY_SIZE(ppc_defs);
10052 best = -1;
10053 pvr_rev = pvr & 0xFFFF;
10054 /* We want all specified bits to match */
10055 best_match = 32 - ctz32(pvr_rev);
10056 for (i = 0; i < max; i++) {
10057 /* We check that the 16 higher bits are the same to ensure the CPU
10058 * model will be the choosen one.
10059 */
10060 if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
10061 /* We want as much as possible of the low-level 16 bits
10062 * to be the same but we allow inexact matches.
10063 */
10064 match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
10065 /* We check '>=' instead of '>' because the PPC_defs table
10066 * is ordered by increasing revision.
10067 * Then, we will match the higher revision compatible
10068 * with the requested PVR
10069 */
10070 if (match >= best_match) {
10071 best = i;
10072 best_match = match;
10073 }
10074 }
10075 }
10076 if (best != -1)
10077 ret = &ppc_defs[best];
10078
10079 return ret;
10080 }
10081
10082 #include <ctype.h>
10083
10084 const ppc_def_t *cpu_ppc_find_by_name (const char *name)
10085 {
10086 const ppc_def_t *ret;
10087 const char *p;
10088 int i, max, len;
10089
10090 /* Check if the given name is a PVR */
10091 len = strlen(name);
10092 if (len == 10 && name[0] == '0' && name[1] == 'x') {
10093 p = name + 2;
10094 goto check_pvr;
10095 } else if (len == 8) {
10096 p = name;
10097 check_pvr:
10098 for (i = 0; i < 8; i++) {
10099 if (!qemu_isxdigit(*p++))
10100 break;
10101 }
10102 if (i == 8)
10103 return ppc_find_by_pvr(strtoul(name, NULL, 16));
10104 }
10105 ret = NULL;
10106 max = ARRAY_SIZE(ppc_defs);
10107 for (i = 0; i < max; i++) {
10108 if (strcasecmp(name, ppc_defs[i].name) == 0) {
10109 ret = &ppc_defs[i];
10110 break;
10111 }
10112 }
10113
10114 return ret;
10115 }
10116
10117 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
10118 {
10119 int i, max;
10120
10121 max = ARRAY_SIZE(ppc_defs);
10122 for (i = 0; i < max; i++) {
10123 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
10124 ppc_defs[i].name, ppc_defs[i].pvr);
10125 }
10126 }
Qemu copy for testing