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PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
[qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "disas/bfd.h"
22 #include "exec/gdbstub.h"
23 #include <sysemu/kvm.h>
24 #include "kvm_ppc.h"
25 #include "sysemu/arch_init.h"
26 #include "sysemu/cpus.h"
27 #include "cpu-models.h"
28 #include "mmu-hash32.h"
29 #include "mmu-hash64.h"
30
31 //#define PPC_DUMP_CPU
32 //#define PPC_DEBUG_SPR
33 //#define PPC_DUMP_SPR_ACCESSES
34
35 /* For user-mode emulation, we don't emulate any IRQ controller */
36 #if defined(CONFIG_USER_ONLY)
37 #define PPC_IRQ_INIT_FN(name) \
38 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
39 { \
40 }
41 #else
42 #define PPC_IRQ_INIT_FN(name) \
43 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
44 #endif
45
46 PPC_IRQ_INIT_FN(40x);
47 PPC_IRQ_INIT_FN(6xx);
48 PPC_IRQ_INIT_FN(970);
49 PPC_IRQ_INIT_FN(POWER7);
50 PPC_IRQ_INIT_FN(e500);
51
52 /* Generic callbacks:
53 * do nothing but store/retrieve spr value
54 */
55 static void spr_load_dump_spr(int sprn)
56 {
57 #ifdef PPC_DUMP_SPR_ACCESSES
58 TCGv_i32 t0 = tcg_const_i32(sprn);
59 gen_helper_load_dump_spr(cpu_env, t0);
60 tcg_temp_free_i32(t0);
61 #endif
62 }
63
64 static void spr_read_generic (void *opaque, int gprn, int sprn)
65 {
66 gen_load_spr(cpu_gpr[gprn], sprn);
67 spr_load_dump_spr(sprn);
68 }
69
70 static void spr_store_dump_spr(int sprn)
71 {
72 #ifdef PPC_DUMP_SPR_ACCESSES
73 TCGv_i32 t0 = tcg_const_i32(sprn);
74 gen_helper_store_dump_spr(cpu_env, t0);
75 tcg_temp_free_i32(t0);
76 #endif
77 }
78
79 static void spr_write_generic (void *opaque, int sprn, int gprn)
80 {
81 gen_store_spr(sprn, cpu_gpr[gprn]);
82 spr_store_dump_spr(sprn);
83 }
84
85 #if !defined(CONFIG_USER_ONLY)
86 static void spr_write_generic32(void *opaque, int sprn, int gprn)
87 {
88 #ifdef TARGET_PPC64
89 TCGv t0 = tcg_temp_new();
90 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
91 gen_store_spr(sprn, t0);
92 tcg_temp_free(t0);
93 spr_store_dump_spr(sprn);
94 #else
95 spr_write_generic(opaque, sprn, gprn);
96 #endif
97 }
98
99 static void spr_write_clear (void *opaque, int sprn, int gprn)
100 {
101 TCGv t0 = tcg_temp_new();
102 TCGv t1 = tcg_temp_new();
103 gen_load_spr(t0, sprn);
104 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
105 tcg_gen_and_tl(t0, t0, t1);
106 gen_store_spr(sprn, t0);
107 tcg_temp_free(t0);
108 tcg_temp_free(t1);
109 }
110 #endif
111
112 /* SPR common to all PowerPC */
113 /* XER */
114 static void spr_read_xer (void *opaque, int gprn, int sprn)
115 {
116 gen_read_xer(cpu_gpr[gprn]);
117 }
118
119 static void spr_write_xer (void *opaque, int sprn, int gprn)
120 {
121 gen_write_xer(cpu_gpr[gprn]);
122 }
123
124 /* LR */
125 static void spr_read_lr (void *opaque, int gprn, int sprn)
126 {
127 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
128 }
129
130 static void spr_write_lr (void *opaque, int sprn, int gprn)
131 {
132 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
133 }
134
135 /* CFAR */
136 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
137 static void spr_read_cfar (void *opaque, int gprn, int sprn)
138 {
139 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
140 }
141
142 static void spr_write_cfar (void *opaque, int sprn, int gprn)
143 {
144 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
145 }
146 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
147
148 /* CTR */
149 static void spr_read_ctr (void *opaque, int gprn, int sprn)
150 {
151 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
152 }
153
154 static void spr_write_ctr (void *opaque, int sprn, int gprn)
155 {
156 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
157 }
158
159 /* User read access to SPR */
160 /* USPRx */
161 /* UMMCRx */
162 /* UPMCx */
163 /* USIA */
164 /* UDECR */
165 static void spr_read_ureg (void *opaque, int gprn, int sprn)
166 {
167 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
168 }
169
170 /* SPR common to all non-embedded PowerPC */
171 /* DECR */
172 #if !defined(CONFIG_USER_ONLY)
173 static void spr_read_decr (void *opaque, int gprn, int sprn)
174 {
175 if (use_icount) {
176 gen_io_start();
177 }
178 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
179 if (use_icount) {
180 gen_io_end();
181 gen_stop_exception(opaque);
182 }
183 }
184
185 static void spr_write_decr (void *opaque, int sprn, int gprn)
186 {
187 if (use_icount) {
188 gen_io_start();
189 }
190 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
191 if (use_icount) {
192 gen_io_end();
193 gen_stop_exception(opaque);
194 }
195 }
196 #endif
197
198 /* SPR common to all non-embedded PowerPC, except 601 */
199 /* Time base */
200 static void spr_read_tbl (void *opaque, int gprn, int sprn)
201 {
202 if (use_icount) {
203 gen_io_start();
204 }
205 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
206 if (use_icount) {
207 gen_io_end();
208 gen_stop_exception(opaque);
209 }
210 }
211
212 static void spr_read_tbu (void *opaque, int gprn, int sprn)
213 {
214 if (use_icount) {
215 gen_io_start();
216 }
217 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
218 if (use_icount) {
219 gen_io_end();
220 gen_stop_exception(opaque);
221 }
222 }
223
224 __attribute__ (( unused ))
225 static void spr_read_atbl (void *opaque, int gprn, int sprn)
226 {
227 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
228 }
229
230 __attribute__ (( unused ))
231 static void spr_read_atbu (void *opaque, int gprn, int sprn)
232 {
233 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
234 }
235
236 #if !defined(CONFIG_USER_ONLY)
237 static void spr_write_tbl (void *opaque, int sprn, int gprn)
238 {
239 if (use_icount) {
240 gen_io_start();
241 }
242 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
243 if (use_icount) {
244 gen_io_end();
245 gen_stop_exception(opaque);
246 }
247 }
248
249 static void spr_write_tbu (void *opaque, int sprn, int gprn)
250 {
251 if (use_icount) {
252 gen_io_start();
253 }
254 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
255 if (use_icount) {
256 gen_io_end();
257 gen_stop_exception(opaque);
258 }
259 }
260
261 __attribute__ (( unused ))
262 static void spr_write_atbl (void *opaque, int sprn, int gprn)
263 {
264 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
265 }
266
267 __attribute__ (( unused ))
268 static void spr_write_atbu (void *opaque, int sprn, int gprn)
269 {
270 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
271 }
272
273 #if defined(TARGET_PPC64)
274 __attribute__ (( unused ))
275 static void spr_read_purr (void *opaque, int gprn, int sprn)
276 {
277 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
278 }
279 #endif
280 #endif
281
282 #if !defined(CONFIG_USER_ONLY)
283 /* IBAT0U...IBAT0U */
284 /* IBAT0L...IBAT7L */
285 static void spr_read_ibat (void *opaque, int gprn, int sprn)
286 {
287 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
288 }
289
290 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
291 {
292 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
293 }
294
295 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
296 {
297 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
298 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
299 tcg_temp_free_i32(t0);
300 }
301
302 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
303 {
304 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
305 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
306 tcg_temp_free_i32(t0);
307 }
308
309 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
310 {
311 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
312 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
313 tcg_temp_free_i32(t0);
314 }
315
316 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
317 {
318 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
319 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
320 tcg_temp_free_i32(t0);
321 }
322
323 /* DBAT0U...DBAT7U */
324 /* DBAT0L...DBAT7L */
325 static void spr_read_dbat (void *opaque, int gprn, int sprn)
326 {
327 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
328 }
329
330 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
331 {
332 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
333 }
334
335 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
336 {
337 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
338 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
339 tcg_temp_free_i32(t0);
340 }
341
342 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
343 {
344 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
345 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
346 tcg_temp_free_i32(t0);
347 }
348
349 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
350 {
351 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
352 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
353 tcg_temp_free_i32(t0);
354 }
355
356 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
357 {
358 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
359 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
360 tcg_temp_free_i32(t0);
361 }
362
363 /* SDR1 */
364 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
365 {
366 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
367 }
368
369 /* 64 bits PowerPC specific SPRs */
370 #if defined(TARGET_PPC64)
371 static void spr_read_hior (void *opaque, int gprn, int sprn)
372 {
373 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
374 }
375
376 static void spr_write_hior (void *opaque, int sprn, int gprn)
377 {
378 TCGv t0 = tcg_temp_new();
379 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
380 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
381 tcg_temp_free(t0);
382 }
383 #endif
384 #endif
385
386 /* PowerPC 601 specific registers */
387 /* RTC */
388 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
389 {
390 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
391 }
392
393 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
394 {
395 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
396 }
397
398 #if !defined(CONFIG_USER_ONLY)
399 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
400 {
401 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
402 }
403
404 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
405 {
406 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
407 }
408
409 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
410 {
411 DisasContext *ctx = opaque;
412
413 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
414 /* Must stop the translation as endianness may have changed */
415 gen_stop_exception(ctx);
416 }
417 #endif
418
419 /* Unified bats */
420 #if !defined(CONFIG_USER_ONLY)
421 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
422 {
423 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
424 }
425
426 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
427 {
428 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
429 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
430 tcg_temp_free_i32(t0);
431 }
432
433 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
434 {
435 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
436 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
437 tcg_temp_free_i32(t0);
438 }
439 #endif
440
441 /* PowerPC 40x specific registers */
442 #if !defined(CONFIG_USER_ONLY)
443 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
444 {
445 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
446 }
447
448 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
449 {
450 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
451 }
452
453 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
454 {
455 DisasContext *ctx = opaque;
456
457 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
458 /* We must stop translation as we may have rebooted */
459 gen_stop_exception(ctx);
460 }
461
462 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
463 {
464 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
465 }
466
467 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
468 {
469 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
470 }
471
472 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
473 {
474 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
475 }
476 #endif
477
478 /* PowerPC 403 specific registers */
479 /* PBL1 / PBU1 / PBL2 / PBU2 */
480 #if !defined(CONFIG_USER_ONLY)
481 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
482 {
483 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
484 }
485
486 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
487 {
488 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
489 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
490 tcg_temp_free_i32(t0);
491 }
492
493 static void spr_write_pir (void *opaque, int sprn, int gprn)
494 {
495 TCGv t0 = tcg_temp_new();
496 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
497 gen_store_spr(SPR_PIR, t0);
498 tcg_temp_free(t0);
499 }
500 #endif
501
502 /* SPE specific registers */
503 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
504 {
505 TCGv_i32 t0 = tcg_temp_new_i32();
506 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
507 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
508 tcg_temp_free_i32(t0);
509 }
510
511 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
512 {
513 TCGv_i32 t0 = tcg_temp_new_i32();
514 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
515 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
516 tcg_temp_free_i32(t0);
517 }
518
519 #if !defined(CONFIG_USER_ONLY)
520 /* Callback used to write the exception vector base */
521 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
522 {
523 TCGv t0 = tcg_temp_new();
524 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
525 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
526 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
527 gen_store_spr(sprn, t0);
528 tcg_temp_free(t0);
529 }
530
531 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
532 {
533 DisasContext *ctx = opaque;
534 int sprn_offs;
535
536 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
537 sprn_offs = sprn - SPR_BOOKE_IVOR0;
538 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
539 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
540 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
541 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
542 } else {
543 printf("Trying to write an unknown exception vector %d %03x\n",
544 sprn, sprn);
545 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
546 return;
547 }
548
549 TCGv t0 = tcg_temp_new();
550 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
551 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
552 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
553 gen_store_spr(sprn, t0);
554 tcg_temp_free(t0);
555 }
556 #endif
557
558 static inline void vscr_init (CPUPPCState *env, uint32_t val)
559 {
560 env->vscr = val;
561 /* Altivec always uses round-to-nearest */
562 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
563 set_flush_to_zero(vscr_nj, &env->vec_status);
564 }
565
566 #ifdef CONFIG_USER_ONLY
567 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
568 oea_read, oea_write, one_reg_id, initial_value) \
569 _spr_register(env, num, name, uea_read, uea_write, initial_value)
570 #else
571 #if !defined(CONFIG_KVM)
572 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
573 oea_read, oea_write, one_reg_id, initial_value) \
574 _spr_register(env, num, name, uea_read, uea_write, \
575 oea_read, oea_write, initial_value)
576 #else
577 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
578 oea_read, oea_write, one_reg_id, initial_value) \
579 _spr_register(env, num, name, uea_read, uea_write, \
580 oea_read, oea_write, one_reg_id, initial_value)
581 #endif
582 #endif
583
584 #define spr_register(env, num, name, uea_read, uea_write, \
585 oea_read, oea_write, initial_value) \
586 spr_register_kvm(env, num, name, uea_read, uea_write, \
587 oea_read, oea_write, 0, initial_value)
588
589 static inline void _spr_register(CPUPPCState *env, int num,
590 const char *name,
591 void (*uea_read)(void *opaque, int gprn, int sprn),
592 void (*uea_write)(void *opaque, int sprn, int gprn),
593 #if !defined(CONFIG_USER_ONLY)
594
595 void (*oea_read)(void *opaque, int gprn, int sprn),
596 void (*oea_write)(void *opaque, int sprn, int gprn),
597 #endif
598 #if defined(CONFIG_KVM)
599 uint64_t one_reg_id,
600 #endif
601 target_ulong initial_value)
602 {
603 ppc_spr_t *spr;
604
605 spr = &env->spr_cb[num];
606 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
607 #if !defined(CONFIG_USER_ONLY)
608 spr->oea_read != NULL || spr->oea_write != NULL ||
609 #endif
610 spr->uea_read != NULL || spr->uea_write != NULL) {
611 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
612 exit(1);
613 }
614 #if defined(PPC_DEBUG_SPR)
615 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
616 name, initial_value);
617 #endif
618 spr->name = name;
619 spr->uea_read = uea_read;
620 spr->uea_write = uea_write;
621 #if !defined(CONFIG_USER_ONLY)
622 spr->oea_read = oea_read;
623 spr->oea_write = oea_write;
624 #endif
625 env->spr[num] = initial_value;
626 }
627
628 /* Generic PowerPC SPRs */
629 static void gen_spr_generic (CPUPPCState *env)
630 {
631 /* Integer processing */
632 spr_register(env, SPR_XER, "XER",
633 &spr_read_xer, &spr_write_xer,
634 &spr_read_xer, &spr_write_xer,
635 0x00000000);
636 /* Branch contol */
637 spr_register(env, SPR_LR, "LR",
638 &spr_read_lr, &spr_write_lr,
639 &spr_read_lr, &spr_write_lr,
640 0x00000000);
641 spr_register(env, SPR_CTR, "CTR",
642 &spr_read_ctr, &spr_write_ctr,
643 &spr_read_ctr, &spr_write_ctr,
644 0x00000000);
645 /* Interrupt processing */
646 spr_register(env, SPR_SRR0, "SRR0",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_generic, &spr_write_generic,
649 0x00000000);
650 spr_register(env, SPR_SRR1, "SRR1",
651 SPR_NOACCESS, SPR_NOACCESS,
652 &spr_read_generic, &spr_write_generic,
653 0x00000000);
654 /* Processor control */
655 spr_register(env, SPR_SPRG0, "SPRG0",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 spr_register(env, SPR_SPRG1, "SPRG1",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 spr_register(env, SPR_SPRG2, "SPRG2",
664 SPR_NOACCESS, SPR_NOACCESS,
665 &spr_read_generic, &spr_write_generic,
666 0x00000000);
667 spr_register(env, SPR_SPRG3, "SPRG3",
668 SPR_NOACCESS, SPR_NOACCESS,
669 &spr_read_generic, &spr_write_generic,
670 0x00000000);
671 }
672
673 /* SPR common to all non-embedded PowerPC, including 601 */
674 static void gen_spr_ne_601 (CPUPPCState *env)
675 {
676 /* Exception processing */
677 spr_register_kvm(env, SPR_DSISR, "DSISR",
678 SPR_NOACCESS, SPR_NOACCESS,
679 &spr_read_generic, &spr_write_generic,
680 KVM_REG_PPC_DSISR, 0x00000000);
681 spr_register_kvm(env, SPR_DAR, "DAR",
682 SPR_NOACCESS, SPR_NOACCESS,
683 &spr_read_generic, &spr_write_generic,
684 KVM_REG_PPC_DAR, 0x00000000);
685 /* Timer */
686 spr_register(env, SPR_DECR, "DECR",
687 SPR_NOACCESS, SPR_NOACCESS,
688 &spr_read_decr, &spr_write_decr,
689 0x00000000);
690 /* Memory management */
691 spr_register(env, SPR_SDR1, "SDR1",
692 SPR_NOACCESS, SPR_NOACCESS,
693 &spr_read_generic, &spr_write_sdr1,
694 0x00000000);
695 }
696
697 /* BATs 0-3 */
698 static void gen_low_BATs (CPUPPCState *env)
699 {
700 #if !defined(CONFIG_USER_ONLY)
701 spr_register(env, SPR_IBAT0U, "IBAT0U",
702 SPR_NOACCESS, SPR_NOACCESS,
703 &spr_read_ibat, &spr_write_ibatu,
704 0x00000000);
705 spr_register(env, SPR_IBAT0L, "IBAT0L",
706 SPR_NOACCESS, SPR_NOACCESS,
707 &spr_read_ibat, &spr_write_ibatl,
708 0x00000000);
709 spr_register(env, SPR_IBAT1U, "IBAT1U",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_ibat, &spr_write_ibatu,
712 0x00000000);
713 spr_register(env, SPR_IBAT1L, "IBAT1L",
714 SPR_NOACCESS, SPR_NOACCESS,
715 &spr_read_ibat, &spr_write_ibatl,
716 0x00000000);
717 spr_register(env, SPR_IBAT2U, "IBAT2U",
718 SPR_NOACCESS, SPR_NOACCESS,
719 &spr_read_ibat, &spr_write_ibatu,
720 0x00000000);
721 spr_register(env, SPR_IBAT2L, "IBAT2L",
722 SPR_NOACCESS, SPR_NOACCESS,
723 &spr_read_ibat, &spr_write_ibatl,
724 0x00000000);
725 spr_register(env, SPR_IBAT3U, "IBAT3U",
726 SPR_NOACCESS, SPR_NOACCESS,
727 &spr_read_ibat, &spr_write_ibatu,
728 0x00000000);
729 spr_register(env, SPR_IBAT3L, "IBAT3L",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_ibat, &spr_write_ibatl,
732 0x00000000);
733 spr_register(env, SPR_DBAT0U, "DBAT0U",
734 SPR_NOACCESS, SPR_NOACCESS,
735 &spr_read_dbat, &spr_write_dbatu,
736 0x00000000);
737 spr_register(env, SPR_DBAT0L, "DBAT0L",
738 SPR_NOACCESS, SPR_NOACCESS,
739 &spr_read_dbat, &spr_write_dbatl,
740 0x00000000);
741 spr_register(env, SPR_DBAT1U, "DBAT1U",
742 SPR_NOACCESS, SPR_NOACCESS,
743 &spr_read_dbat, &spr_write_dbatu,
744 0x00000000);
745 spr_register(env, SPR_DBAT1L, "DBAT1L",
746 SPR_NOACCESS, SPR_NOACCESS,
747 &spr_read_dbat, &spr_write_dbatl,
748 0x00000000);
749 spr_register(env, SPR_DBAT2U, "DBAT2U",
750 SPR_NOACCESS, SPR_NOACCESS,
751 &spr_read_dbat, &spr_write_dbatu,
752 0x00000000);
753 spr_register(env, SPR_DBAT2L, "DBAT2L",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_dbat, &spr_write_dbatl,
756 0x00000000);
757 spr_register(env, SPR_DBAT3U, "DBAT3U",
758 SPR_NOACCESS, SPR_NOACCESS,
759 &spr_read_dbat, &spr_write_dbatu,
760 0x00000000);
761 spr_register(env, SPR_DBAT3L, "DBAT3L",
762 SPR_NOACCESS, SPR_NOACCESS,
763 &spr_read_dbat, &spr_write_dbatl,
764 0x00000000);
765 env->nb_BATs += 4;
766 #endif
767 }
768
769 /* BATs 4-7 */
770 static void gen_high_BATs (CPUPPCState *env)
771 {
772 #if !defined(CONFIG_USER_ONLY)
773 spr_register(env, SPR_IBAT4U, "IBAT4U",
774 SPR_NOACCESS, SPR_NOACCESS,
775 &spr_read_ibat_h, &spr_write_ibatu_h,
776 0x00000000);
777 spr_register(env, SPR_IBAT4L, "IBAT4L",
778 SPR_NOACCESS, SPR_NOACCESS,
779 &spr_read_ibat_h, &spr_write_ibatl_h,
780 0x00000000);
781 spr_register(env, SPR_IBAT5U, "IBAT5U",
782 SPR_NOACCESS, SPR_NOACCESS,
783 &spr_read_ibat_h, &spr_write_ibatu_h,
784 0x00000000);
785 spr_register(env, SPR_IBAT5L, "IBAT5L",
786 SPR_NOACCESS, SPR_NOACCESS,
787 &spr_read_ibat_h, &spr_write_ibatl_h,
788 0x00000000);
789 spr_register(env, SPR_IBAT6U, "IBAT6U",
790 SPR_NOACCESS, SPR_NOACCESS,
791 &spr_read_ibat_h, &spr_write_ibatu_h,
792 0x00000000);
793 spr_register(env, SPR_IBAT6L, "IBAT6L",
794 SPR_NOACCESS, SPR_NOACCESS,
795 &spr_read_ibat_h, &spr_write_ibatl_h,
796 0x00000000);
797 spr_register(env, SPR_IBAT7U, "IBAT7U",
798 SPR_NOACCESS, SPR_NOACCESS,
799 &spr_read_ibat_h, &spr_write_ibatu_h,
800 0x00000000);
801 spr_register(env, SPR_IBAT7L, "IBAT7L",
802 SPR_NOACCESS, SPR_NOACCESS,
803 &spr_read_ibat_h, &spr_write_ibatl_h,
804 0x00000000);
805 spr_register(env, SPR_DBAT4U, "DBAT4U",
806 SPR_NOACCESS, SPR_NOACCESS,
807 &spr_read_dbat_h, &spr_write_dbatu_h,
808 0x00000000);
809 spr_register(env, SPR_DBAT4L, "DBAT4L",
810 SPR_NOACCESS, SPR_NOACCESS,
811 &spr_read_dbat_h, &spr_write_dbatl_h,
812 0x00000000);
813 spr_register(env, SPR_DBAT5U, "DBAT5U",
814 SPR_NOACCESS, SPR_NOACCESS,
815 &spr_read_dbat_h, &spr_write_dbatu_h,
816 0x00000000);
817 spr_register(env, SPR_DBAT5L, "DBAT5L",
818 SPR_NOACCESS, SPR_NOACCESS,
819 &spr_read_dbat_h, &spr_write_dbatl_h,
820 0x00000000);
821 spr_register(env, SPR_DBAT6U, "DBAT6U",
822 SPR_NOACCESS, SPR_NOACCESS,
823 &spr_read_dbat_h, &spr_write_dbatu_h,
824 0x00000000);
825 spr_register(env, SPR_DBAT6L, "DBAT6L",
826 SPR_NOACCESS, SPR_NOACCESS,
827 &spr_read_dbat_h, &spr_write_dbatl_h,
828 0x00000000);
829 spr_register(env, SPR_DBAT7U, "DBAT7U",
830 SPR_NOACCESS, SPR_NOACCESS,
831 &spr_read_dbat_h, &spr_write_dbatu_h,
832 0x00000000);
833 spr_register(env, SPR_DBAT7L, "DBAT7L",
834 SPR_NOACCESS, SPR_NOACCESS,
835 &spr_read_dbat_h, &spr_write_dbatl_h,
836 0x00000000);
837 env->nb_BATs += 4;
838 #endif
839 }
840
841 /* Generic PowerPC time base */
842 static void gen_tbl (CPUPPCState *env)
843 {
844 spr_register(env, SPR_VTBL, "TBL",
845 &spr_read_tbl, SPR_NOACCESS,
846 &spr_read_tbl, SPR_NOACCESS,
847 0x00000000);
848 spr_register(env, SPR_TBL, "TBL",
849 &spr_read_tbl, SPR_NOACCESS,
850 &spr_read_tbl, &spr_write_tbl,
851 0x00000000);
852 spr_register(env, SPR_VTBU, "TBU",
853 &spr_read_tbu, SPR_NOACCESS,
854 &spr_read_tbu, SPR_NOACCESS,
855 0x00000000);
856 spr_register(env, SPR_TBU, "TBU",
857 &spr_read_tbu, SPR_NOACCESS,
858 &spr_read_tbu, &spr_write_tbu,
859 0x00000000);
860 }
861
862 /* Softare table search registers */
863 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
864 {
865 #if !defined(CONFIG_USER_ONLY)
866 env->nb_tlb = nb_tlbs;
867 env->nb_ways = nb_ways;
868 env->id_tlbs = 1;
869 env->tlb_type = TLB_6XX;
870 spr_register(env, SPR_DMISS, "DMISS",
871 SPR_NOACCESS, SPR_NOACCESS,
872 &spr_read_generic, SPR_NOACCESS,
873 0x00000000);
874 spr_register(env, SPR_DCMP, "DCMP",
875 SPR_NOACCESS, SPR_NOACCESS,
876 &spr_read_generic, SPR_NOACCESS,
877 0x00000000);
878 spr_register(env, SPR_HASH1, "HASH1",
879 SPR_NOACCESS, SPR_NOACCESS,
880 &spr_read_generic, SPR_NOACCESS,
881 0x00000000);
882 spr_register(env, SPR_HASH2, "HASH2",
883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_generic, SPR_NOACCESS,
885 0x00000000);
886 spr_register(env, SPR_IMISS, "IMISS",
887 SPR_NOACCESS, SPR_NOACCESS,
888 &spr_read_generic, SPR_NOACCESS,
889 0x00000000);
890 spr_register(env, SPR_ICMP, "ICMP",
891 SPR_NOACCESS, SPR_NOACCESS,
892 &spr_read_generic, SPR_NOACCESS,
893 0x00000000);
894 spr_register(env, SPR_RPA, "RPA",
895 SPR_NOACCESS, SPR_NOACCESS,
896 &spr_read_generic, &spr_write_generic,
897 0x00000000);
898 #endif
899 }
900
901 /* SPR common to MPC755 and G2 */
902 static void gen_spr_G2_755 (CPUPPCState *env)
903 {
904 /* SGPRs */
905 spr_register(env, SPR_SPRG4, "SPRG4",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, &spr_write_generic,
908 0x00000000);
909 spr_register(env, SPR_SPRG5, "SPRG5",
910 SPR_NOACCESS, SPR_NOACCESS,
911 &spr_read_generic, &spr_write_generic,
912 0x00000000);
913 spr_register(env, SPR_SPRG6, "SPRG6",
914 SPR_NOACCESS, SPR_NOACCESS,
915 &spr_read_generic, &spr_write_generic,
916 0x00000000);
917 spr_register(env, SPR_SPRG7, "SPRG7",
918 SPR_NOACCESS, SPR_NOACCESS,
919 &spr_read_generic, &spr_write_generic,
920 0x00000000);
921 }
922
923 /* SPR common to all 7xx PowerPC implementations */
924 static void gen_spr_7xx (CPUPPCState *env)
925 {
926 /* Breakpoints */
927 /* XXX : not implemented */
928 spr_register_kvm(env, SPR_DABR, "DABR",
929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_generic, &spr_write_generic,
931 KVM_REG_PPC_DABR, 0x00000000);
932 /* XXX : not implemented */
933 spr_register(env, SPR_IABR, "IABR",
934 SPR_NOACCESS, SPR_NOACCESS,
935 &spr_read_generic, &spr_write_generic,
936 0x00000000);
937 /* Cache management */
938 /* XXX : not implemented */
939 spr_register(env, SPR_ICTC, "ICTC",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943 /* Performance monitors */
944 /* XXX : not implemented */
945 spr_register(env, SPR_MMCR0, "MMCR0",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_generic, &spr_write_generic,
948 0x00000000);
949 /* XXX : not implemented */
950 spr_register(env, SPR_MMCR1, "MMCR1",
951 SPR_NOACCESS, SPR_NOACCESS,
952 &spr_read_generic, &spr_write_generic,
953 0x00000000);
954 /* XXX : not implemented */
955 spr_register(env, SPR_PMC1, "PMC1",
956 SPR_NOACCESS, SPR_NOACCESS,
957 &spr_read_generic, &spr_write_generic,
958 0x00000000);
959 /* XXX : not implemented */
960 spr_register(env, SPR_PMC2, "PMC2",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, &spr_write_generic,
963 0x00000000);
964 /* XXX : not implemented */
965 spr_register(env, SPR_PMC3, "PMC3",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, &spr_write_generic,
968 0x00000000);
969 /* XXX : not implemented */
970 spr_register(env, SPR_PMC4, "PMC4",
971 SPR_NOACCESS, SPR_NOACCESS,
972 &spr_read_generic, &spr_write_generic,
973 0x00000000);
974 /* XXX : not implemented */
975 spr_register(env, SPR_SIAR, "SIAR",
976 SPR_NOACCESS, SPR_NOACCESS,
977 &spr_read_generic, SPR_NOACCESS,
978 0x00000000);
979 /* XXX : not implemented */
980 spr_register(env, SPR_UMMCR0, "UMMCR0",
981 &spr_read_ureg, SPR_NOACCESS,
982 &spr_read_ureg, SPR_NOACCESS,
983 0x00000000);
984 /* XXX : not implemented */
985 spr_register(env, SPR_UMMCR1, "UMMCR1",
986 &spr_read_ureg, SPR_NOACCESS,
987 &spr_read_ureg, SPR_NOACCESS,
988 0x00000000);
989 /* XXX : not implemented */
990 spr_register(env, SPR_UPMC1, "UPMC1",
991 &spr_read_ureg, SPR_NOACCESS,
992 &spr_read_ureg, SPR_NOACCESS,
993 0x00000000);
994 /* XXX : not implemented */
995 spr_register(env, SPR_UPMC2, "UPMC2",
996 &spr_read_ureg, SPR_NOACCESS,
997 &spr_read_ureg, SPR_NOACCESS,
998 0x00000000);
999 /* XXX : not implemented */
1000 spr_register(env, SPR_UPMC3, "UPMC3",
1001 &spr_read_ureg, SPR_NOACCESS,
1002 &spr_read_ureg, SPR_NOACCESS,
1003 0x00000000);
1004 /* XXX : not implemented */
1005 spr_register(env, SPR_UPMC4, "UPMC4",
1006 &spr_read_ureg, SPR_NOACCESS,
1007 &spr_read_ureg, SPR_NOACCESS,
1008 0x00000000);
1009 /* XXX : not implemented */
1010 spr_register(env, SPR_USIAR, "USIAR",
1011 &spr_read_ureg, SPR_NOACCESS,
1012 &spr_read_ureg, SPR_NOACCESS,
1013 0x00000000);
1014 /* External access control */
1015 /* XXX : not implemented */
1016 spr_register(env, SPR_EAR, "EAR",
1017 SPR_NOACCESS, SPR_NOACCESS,
1018 &spr_read_generic, &spr_write_generic,
1019 0x00000000);
1020 }
1021
1022 #ifdef TARGET_PPC64
1023 #ifndef CONFIG_USER_ONLY
1024 static void spr_read_uamr (void *opaque, int gprn, int sprn)
1025 {
1026 gen_load_spr(cpu_gpr[gprn], SPR_AMR);
1027 spr_load_dump_spr(SPR_AMR);
1028 }
1029
1030 static void spr_write_uamr (void *opaque, int sprn, int gprn)
1031 {
1032 gen_store_spr(SPR_AMR, cpu_gpr[gprn]);
1033 spr_store_dump_spr(SPR_AMR);
1034 }
1035
1036 static void spr_write_uamr_pr (void *opaque, int sprn, int gprn)
1037 {
1038 TCGv t0 = tcg_temp_new();
1039
1040 gen_load_spr(t0, SPR_UAMOR);
1041 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1042 gen_store_spr(SPR_AMR, t0);
1043 spr_store_dump_spr(SPR_AMR);
1044 }
1045 #endif /* CONFIG_USER_ONLY */
1046
1047 static void gen_spr_amr (CPUPPCState *env)
1048 {
1049 #ifndef CONFIG_USER_ONLY
1050 /* Virtual Page Class Key protection */
1051 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1052 * userspace accessible, 29 is privileged. So we only need to set
1053 * the kvm ONE_REG id on one of them, we use 29 */
1054 spr_register(env, SPR_UAMR, "UAMR",
1055 &spr_read_uamr, &spr_write_uamr_pr,
1056 &spr_read_uamr, &spr_write_uamr,
1057 0);
1058 spr_register_kvm(env, SPR_AMR, "AMR",
1059 SPR_NOACCESS, SPR_NOACCESS,
1060 &spr_read_generic, &spr_write_generic,
1061 KVM_REG_PPC_AMR, 0xffffffffffffffffULL);
1062 spr_register_kvm(env, SPR_UAMOR, "UAMOR",
1063 SPR_NOACCESS, SPR_NOACCESS,
1064 &spr_read_generic, &spr_write_generic,
1065 KVM_REG_PPC_UAMOR, 0);
1066 #endif /* !CONFIG_USER_ONLY */
1067 }
1068 #endif /* TARGET_PPC64 */
1069
1070 static void gen_spr_thrm (CPUPPCState *env)
1071 {
1072 /* Thermal management */
1073 /* XXX : not implemented */
1074 spr_register(env, SPR_THRM1, "THRM1",
1075 SPR_NOACCESS, SPR_NOACCESS,
1076 &spr_read_generic, &spr_write_generic,
1077 0x00000000);
1078 /* XXX : not implemented */
1079 spr_register(env, SPR_THRM2, "THRM2",
1080 SPR_NOACCESS, SPR_NOACCESS,
1081 &spr_read_generic, &spr_write_generic,
1082 0x00000000);
1083 /* XXX : not implemented */
1084 spr_register(env, SPR_THRM3, "THRM3",
1085 SPR_NOACCESS, SPR_NOACCESS,
1086 &spr_read_generic, &spr_write_generic,
1087 0x00000000);
1088 }
1089
1090 /* SPR specific to PowerPC 604 implementation */
1091 static void gen_spr_604 (CPUPPCState *env)
1092 {
1093 /* Processor identification */
1094 spr_register(env, SPR_PIR, "PIR",
1095 SPR_NOACCESS, SPR_NOACCESS,
1096 &spr_read_generic, &spr_write_pir,
1097 0x00000000);
1098 /* Breakpoints */
1099 /* XXX : not implemented */
1100 spr_register(env, SPR_IABR, "IABR",
1101 SPR_NOACCESS, SPR_NOACCESS,
1102 &spr_read_generic, &spr_write_generic,
1103 0x00000000);
1104 /* XXX : not implemented */
1105 spr_register_kvm(env, SPR_DABR, "DABR",
1106 SPR_NOACCESS, SPR_NOACCESS,
1107 &spr_read_generic, &spr_write_generic,
1108 KVM_REG_PPC_DABR, 0x00000000);
1109 /* Performance counters */
1110 /* XXX : not implemented */
1111 spr_register(env, SPR_MMCR0, "MMCR0",
1112 SPR_NOACCESS, SPR_NOACCESS,
1113 &spr_read_generic, &spr_write_generic,
1114 0x00000000);
1115 /* XXX : not implemented */
1116 spr_register(env, SPR_PMC1, "PMC1",
1117 SPR_NOACCESS, SPR_NOACCESS,
1118 &spr_read_generic, &spr_write_generic,
1119 0x00000000);
1120 /* XXX : not implemented */
1121 spr_register(env, SPR_PMC2, "PMC2",
1122 SPR_NOACCESS, SPR_NOACCESS,
1123 &spr_read_generic, &spr_write_generic,
1124 0x00000000);
1125 /* XXX : not implemented */
1126 spr_register(env, SPR_SIAR, "SIAR",
1127 SPR_NOACCESS, SPR_NOACCESS,
1128 &spr_read_generic, SPR_NOACCESS,
1129 0x00000000);
1130 /* XXX : not implemented */
1131 spr_register(env, SPR_SDA, "SDA",
1132 SPR_NOACCESS, SPR_NOACCESS,
1133 &spr_read_generic, SPR_NOACCESS,
1134 0x00000000);
1135 /* External access control */
1136 /* XXX : not implemented */
1137 spr_register(env, SPR_EAR, "EAR",
1138 SPR_NOACCESS, SPR_NOACCESS,
1139 &spr_read_generic, &spr_write_generic,
1140 0x00000000);
1141 }
1142
1143 /* SPR specific to PowerPC 603 implementation */
1144 static void gen_spr_603 (CPUPPCState *env)
1145 {
1146 /* External access control */
1147 /* XXX : not implemented */
1148 spr_register(env, SPR_EAR, "EAR",
1149 SPR_NOACCESS, SPR_NOACCESS,
1150 &spr_read_generic, &spr_write_generic,
1151 0x00000000);
1152 }
1153
1154 /* SPR specific to PowerPC G2 implementation */
1155 static void gen_spr_G2 (CPUPPCState *env)
1156 {
1157 /* Memory base address */
1158 /* MBAR */
1159 /* XXX : not implemented */
1160 spr_register(env, SPR_MBAR, "MBAR",
1161 SPR_NOACCESS, SPR_NOACCESS,
1162 &spr_read_generic, &spr_write_generic,
1163 0x00000000);
1164 /* Exception processing */
1165 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1166 SPR_NOACCESS, SPR_NOACCESS,
1167 &spr_read_generic, &spr_write_generic,
1168 0x00000000);
1169 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1170 SPR_NOACCESS, SPR_NOACCESS,
1171 &spr_read_generic, &spr_write_generic,
1172 0x00000000);
1173 /* Breakpoints */
1174 /* XXX : not implemented */
1175 spr_register(env, SPR_DABR, "DABR",
1176 SPR_NOACCESS, SPR_NOACCESS,
1177 &spr_read_generic, &spr_write_generic,
1178 0x00000000);
1179 /* XXX : not implemented */
1180 spr_register(env, SPR_DABR2, "DABR2",
1181 SPR_NOACCESS, SPR_NOACCESS,
1182 &spr_read_generic, &spr_write_generic,
1183 0x00000000);
1184 /* XXX : not implemented */
1185 spr_register(env, SPR_IABR, "IABR",
1186 SPR_NOACCESS, SPR_NOACCESS,
1187 &spr_read_generic, &spr_write_generic,
1188 0x00000000);
1189 /* XXX : not implemented */
1190 spr_register(env, SPR_IABR2, "IABR2",
1191 SPR_NOACCESS, SPR_NOACCESS,
1192 &spr_read_generic, &spr_write_generic,
1193 0x00000000);
1194 /* XXX : not implemented */
1195 spr_register(env, SPR_IBCR, "IBCR",
1196 SPR_NOACCESS, SPR_NOACCESS,
1197 &spr_read_generic, &spr_write_generic,
1198 0x00000000);
1199 /* XXX : not implemented */
1200 spr_register(env, SPR_DBCR, "DBCR",
1201 SPR_NOACCESS, SPR_NOACCESS,
1202 &spr_read_generic, &spr_write_generic,
1203 0x00000000);
1204 }
1205
1206 /* SPR specific to PowerPC 602 implementation */
1207 static void gen_spr_602 (CPUPPCState *env)
1208 {
1209 /* ESA registers */
1210 /* XXX : not implemented */
1211 spr_register(env, SPR_SER, "SER",
1212 SPR_NOACCESS, SPR_NOACCESS,
1213 &spr_read_generic, &spr_write_generic,
1214 0x00000000);
1215 /* XXX : not implemented */
1216 spr_register(env, SPR_SEBR, "SEBR",
1217 SPR_NOACCESS, SPR_NOACCESS,
1218 &spr_read_generic, &spr_write_generic,
1219 0x00000000);
1220 /* XXX : not implemented */
1221 spr_register(env, SPR_ESASRR, "ESASRR",
1222 SPR_NOACCESS, SPR_NOACCESS,
1223 &spr_read_generic, &spr_write_generic,
1224 0x00000000);
1225 /* Floating point status */
1226 /* XXX : not implemented */
1227 spr_register(env, SPR_SP, "SP",
1228 SPR_NOACCESS, SPR_NOACCESS,
1229 &spr_read_generic, &spr_write_generic,
1230 0x00000000);
1231 /* XXX : not implemented */
1232 spr_register(env, SPR_LT, "LT",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_generic, &spr_write_generic,
1235 0x00000000);
1236 /* Watchdog timer */
1237 /* XXX : not implemented */
1238 spr_register(env, SPR_TCR, "TCR",
1239 SPR_NOACCESS, SPR_NOACCESS,
1240 &spr_read_generic, &spr_write_generic,
1241 0x00000000);
1242 /* Interrupt base */
1243 spr_register(env, SPR_IBR, "IBR",
1244 SPR_NOACCESS, SPR_NOACCESS,
1245 &spr_read_generic, &spr_write_generic,
1246 0x00000000);
1247 /* XXX : not implemented */
1248 spr_register(env, SPR_IABR, "IABR",
1249 SPR_NOACCESS, SPR_NOACCESS,
1250 &spr_read_generic, &spr_write_generic,
1251 0x00000000);
1252 }
1253
1254 /* SPR specific to PowerPC 601 implementation */
1255 static void gen_spr_601 (CPUPPCState *env)
1256 {
1257 /* Multiplication/division register */
1258 /* MQ */
1259 spr_register(env, SPR_MQ, "MQ",
1260 &spr_read_generic, &spr_write_generic,
1261 &spr_read_generic, &spr_write_generic,
1262 0x00000000);
1263 /* RTC registers */
1264 spr_register(env, SPR_601_RTCU, "RTCU",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 SPR_NOACCESS, &spr_write_601_rtcu,
1267 0x00000000);
1268 spr_register(env, SPR_601_VRTCU, "RTCU",
1269 &spr_read_601_rtcu, SPR_NOACCESS,
1270 &spr_read_601_rtcu, SPR_NOACCESS,
1271 0x00000000);
1272 spr_register(env, SPR_601_RTCL, "RTCL",
1273 SPR_NOACCESS, SPR_NOACCESS,
1274 SPR_NOACCESS, &spr_write_601_rtcl,
1275 0x00000000);
1276 spr_register(env, SPR_601_VRTCL, "RTCL",
1277 &spr_read_601_rtcl, SPR_NOACCESS,
1278 &spr_read_601_rtcl, SPR_NOACCESS,
1279 0x00000000);
1280 /* Timer */
1281 #if 0 /* ? */
1282 spr_register(env, SPR_601_UDECR, "UDECR",
1283 &spr_read_decr, SPR_NOACCESS,
1284 &spr_read_decr, SPR_NOACCESS,
1285 0x00000000);
1286 #endif
1287 /* External access control */
1288 /* XXX : not implemented */
1289 spr_register(env, SPR_EAR, "EAR",
1290 SPR_NOACCESS, SPR_NOACCESS,
1291 &spr_read_generic, &spr_write_generic,
1292 0x00000000);
1293 /* Memory management */
1294 #if !defined(CONFIG_USER_ONLY)
1295 spr_register(env, SPR_IBAT0U, "IBAT0U",
1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_601_ubat, &spr_write_601_ubatu,
1298 0x00000000);
1299 spr_register(env, SPR_IBAT0L, "IBAT0L",
1300 SPR_NOACCESS, SPR_NOACCESS,
1301 &spr_read_601_ubat, &spr_write_601_ubatl,
1302 0x00000000);
1303 spr_register(env, SPR_IBAT1U, "IBAT1U",
1304 SPR_NOACCESS, SPR_NOACCESS,
1305 &spr_read_601_ubat, &spr_write_601_ubatu,
1306 0x00000000);
1307 spr_register(env, SPR_IBAT1L, "IBAT1L",
1308 SPR_NOACCESS, SPR_NOACCESS,
1309 &spr_read_601_ubat, &spr_write_601_ubatl,
1310 0x00000000);
1311 spr_register(env, SPR_IBAT2U, "IBAT2U",
1312 SPR_NOACCESS, SPR_NOACCESS,
1313 &spr_read_601_ubat, &spr_write_601_ubatu,
1314 0x00000000);
1315 spr_register(env, SPR_IBAT2L, "IBAT2L",
1316 SPR_NOACCESS, SPR_NOACCESS,
1317 &spr_read_601_ubat, &spr_write_601_ubatl,
1318 0x00000000);
1319 spr_register(env, SPR_IBAT3U, "IBAT3U",
1320 SPR_NOACCESS, SPR_NOACCESS,
1321 &spr_read_601_ubat, &spr_write_601_ubatu,
1322 0x00000000);
1323 spr_register(env, SPR_IBAT3L, "IBAT3L",
1324 SPR_NOACCESS, SPR_NOACCESS,
1325 &spr_read_601_ubat, &spr_write_601_ubatl,
1326 0x00000000);
1327 env->nb_BATs = 4;
1328 #endif
1329 }
1330
1331 static void gen_spr_74xx (CPUPPCState *env)
1332 {
1333 /* Processor identification */
1334 spr_register(env, SPR_PIR, "PIR",
1335 SPR_NOACCESS, SPR_NOACCESS,
1336 &spr_read_generic, &spr_write_pir,
1337 0x00000000);
1338 /* XXX : not implemented */
1339 spr_register(env, SPR_MMCR2, "MMCR2",
1340 SPR_NOACCESS, SPR_NOACCESS,
1341 &spr_read_generic, &spr_write_generic,
1342 0x00000000);
1343 /* XXX : not implemented */
1344 spr_register(env, SPR_UMMCR2, "UMMCR2",
1345 &spr_read_ureg, SPR_NOACCESS,
1346 &spr_read_ureg, SPR_NOACCESS,
1347 0x00000000);
1348 /* XXX: not implemented */
1349 spr_register(env, SPR_BAMR, "BAMR",
1350 SPR_NOACCESS, SPR_NOACCESS,
1351 &spr_read_generic, &spr_write_generic,
1352 0x00000000);
1353 /* XXX : not implemented */
1354 spr_register(env, SPR_MSSCR0, "MSSCR0",
1355 SPR_NOACCESS, SPR_NOACCESS,
1356 &spr_read_generic, &spr_write_generic,
1357 0x00000000);
1358 /* Hardware implementation registers */
1359 /* XXX : not implemented */
1360 spr_register(env, SPR_HID0, "HID0",
1361 SPR_NOACCESS, SPR_NOACCESS,
1362 &spr_read_generic, &spr_write_generic,
1363 0x00000000);
1364 /* XXX : not implemented */
1365 spr_register(env, SPR_HID1, "HID1",
1366 SPR_NOACCESS, SPR_NOACCESS,
1367 &spr_read_generic, &spr_write_generic,
1368 0x00000000);
1369 /* Altivec */
1370 spr_register(env, SPR_VRSAVE, "VRSAVE",
1371 &spr_read_generic, &spr_write_generic,
1372 &spr_read_generic, &spr_write_generic,
1373 0x00000000);
1374 /* XXX : not implemented */
1375 spr_register(env, SPR_L2CR, "L2CR",
1376 SPR_NOACCESS, SPR_NOACCESS,
1377 &spr_read_generic, &spr_write_generic,
1378 0x00000000);
1379 /* Not strictly an SPR */
1380 vscr_init(env, 0x00010000);
1381 }
1382
1383 static void gen_l3_ctrl (CPUPPCState *env)
1384 {
1385 /* L3CR */
1386 /* XXX : not implemented */
1387 spr_register(env, SPR_L3CR, "L3CR",
1388 SPR_NOACCESS, SPR_NOACCESS,
1389 &spr_read_generic, &spr_write_generic,
1390 0x00000000);
1391 /* L3ITCR0 */
1392 /* XXX : not implemented */
1393 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1394 SPR_NOACCESS, SPR_NOACCESS,
1395 &spr_read_generic, &spr_write_generic,
1396 0x00000000);
1397 /* L3PM */
1398 /* XXX : not implemented */
1399 spr_register(env, SPR_L3PM, "L3PM",
1400 SPR_NOACCESS, SPR_NOACCESS,
1401 &spr_read_generic, &spr_write_generic,
1402 0x00000000);
1403 }
1404
1405 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1406 {
1407 #if !defined(CONFIG_USER_ONLY)
1408 env->nb_tlb = nb_tlbs;
1409 env->nb_ways = nb_ways;
1410 env->id_tlbs = 1;
1411 env->tlb_type = TLB_6XX;
1412 /* XXX : not implemented */
1413 spr_register(env, SPR_PTEHI, "PTEHI",
1414 SPR_NOACCESS, SPR_NOACCESS,
1415 &spr_read_generic, &spr_write_generic,
1416 0x00000000);
1417 /* XXX : not implemented */
1418 spr_register(env, SPR_PTELO, "PTELO",
1419 SPR_NOACCESS, SPR_NOACCESS,
1420 &spr_read_generic, &spr_write_generic,
1421 0x00000000);
1422 /* XXX : not implemented */
1423 spr_register(env, SPR_TLBMISS, "TLBMISS",
1424 SPR_NOACCESS, SPR_NOACCESS,
1425 &spr_read_generic, &spr_write_generic,
1426 0x00000000);
1427 #endif
1428 }
1429
1430 #if !defined(CONFIG_USER_ONLY)
1431 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1432 {
1433 TCGv t0 = tcg_temp_new();
1434
1435 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1436 gen_store_spr(sprn, t0);
1437 tcg_temp_free(t0);
1438 }
1439
1440 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1441 {
1442 TCGv_i32 t0 = tcg_const_i32(sprn);
1443 gen_helper_booke206_tlbflush(cpu_env, t0);
1444 tcg_temp_free_i32(t0);
1445 }
1446
1447 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1448 {
1449 TCGv_i32 t0 = tcg_const_i32(sprn);
1450 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1451 tcg_temp_free_i32(t0);
1452 }
1453 #endif
1454
1455 static void gen_spr_usprgh (CPUPPCState *env)
1456 {
1457 spr_register(env, SPR_USPRG4, "USPRG4",
1458 &spr_read_ureg, SPR_NOACCESS,
1459 &spr_read_ureg, SPR_NOACCESS,
1460 0x00000000);
1461 spr_register(env, SPR_USPRG5, "USPRG5",
1462 &spr_read_ureg, SPR_NOACCESS,
1463 &spr_read_ureg, SPR_NOACCESS,
1464 0x00000000);
1465 spr_register(env, SPR_USPRG6, "USPRG6",
1466 &spr_read_ureg, SPR_NOACCESS,
1467 &spr_read_ureg, SPR_NOACCESS,
1468 0x00000000);
1469 spr_register(env, SPR_USPRG7, "USPRG7",
1470 &spr_read_ureg, SPR_NOACCESS,
1471 &spr_read_ureg, SPR_NOACCESS,
1472 0x00000000);
1473 }
1474
1475 /* PowerPC BookE SPR */
1476 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1477 {
1478 const char *ivor_names[64] = {
1479 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1480 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1481 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1482 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1483 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1484 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1485 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1486 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1487 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1488 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1489 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1490 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1491 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1492 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1493 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1494 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1495 };
1496 #define SPR_BOOKE_IVORxx (-1)
1497 int ivor_sprn[64] = {
1498 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1499 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1500 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1501 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1502 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1503 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1504 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1505 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1506 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1507 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1508 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1509 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1510 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1511 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1512 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1513 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1514 };
1515 int i;
1516
1517 /* Interrupt processing */
1518 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1519 SPR_NOACCESS, SPR_NOACCESS,
1520 &spr_read_generic, &spr_write_generic,
1521 0x00000000);
1522 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1523 SPR_NOACCESS, SPR_NOACCESS,
1524 &spr_read_generic, &spr_write_generic,
1525 0x00000000);
1526 /* Debug */
1527 /* XXX : not implemented */
1528 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1529 SPR_NOACCESS, SPR_NOACCESS,
1530 &spr_read_generic, &spr_write_generic,
1531 0x00000000);
1532 /* XXX : not implemented */
1533 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1534 SPR_NOACCESS, SPR_NOACCESS,
1535 &spr_read_generic, &spr_write_generic,
1536 0x00000000);
1537 /* XXX : not implemented */
1538 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1539 SPR_NOACCESS, SPR_NOACCESS,
1540 &spr_read_generic, &spr_write_generic,
1541 0x00000000);
1542 /* XXX : not implemented */
1543 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1544 SPR_NOACCESS, SPR_NOACCESS,
1545 &spr_read_generic, &spr_write_generic,
1546 0x00000000);
1547 /* XXX : not implemented */
1548 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_40x_dbcr0,
1551 0x00000000);
1552 /* XXX : not implemented */
1553 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
1557 /* XXX : not implemented */
1558 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_generic, &spr_write_generic,
1561 0x00000000);
1562 /* XXX : not implemented */
1563 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1564 SPR_NOACCESS, SPR_NOACCESS,
1565 &spr_read_generic, &spr_write_clear,
1566 0x00000000);
1567 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1568 SPR_NOACCESS, SPR_NOACCESS,
1569 &spr_read_generic, &spr_write_generic,
1570 0x00000000);
1571 spr_register(env, SPR_BOOKE_ESR, "ESR",
1572 SPR_NOACCESS, SPR_NOACCESS,
1573 &spr_read_generic, &spr_write_generic,
1574 0x00000000);
1575 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1576 SPR_NOACCESS, SPR_NOACCESS,
1577 &spr_read_generic, &spr_write_excp_prefix,
1578 0x00000000);
1579 /* Exception vectors */
1580 for (i = 0; i < 64; i++) {
1581 if (ivor_mask & (1ULL << i)) {
1582 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1583 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1584 exit(1);
1585 }
1586 spr_register(env, ivor_sprn[i], ivor_names[i],
1587 SPR_NOACCESS, SPR_NOACCESS,
1588 &spr_read_generic, &spr_write_excp_vector,
1589 0x00000000);
1590 }
1591 }
1592 spr_register(env, SPR_BOOKE_PID, "PID",
1593 SPR_NOACCESS, SPR_NOACCESS,
1594 &spr_read_generic, &spr_write_booke_pid,
1595 0x00000000);
1596 spr_register(env, SPR_BOOKE_TCR, "TCR",
1597 SPR_NOACCESS, SPR_NOACCESS,
1598 &spr_read_generic, &spr_write_booke_tcr,
1599 0x00000000);
1600 spr_register(env, SPR_BOOKE_TSR, "TSR",
1601 SPR_NOACCESS, SPR_NOACCESS,
1602 &spr_read_generic, &spr_write_booke_tsr,
1603 0x00000000);
1604 /* Timer */
1605 spr_register(env, SPR_DECR, "DECR",
1606 SPR_NOACCESS, SPR_NOACCESS,
1607 &spr_read_decr, &spr_write_decr,
1608 0x00000000);
1609 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1610 SPR_NOACCESS, SPR_NOACCESS,
1611 SPR_NOACCESS, &spr_write_generic,
1612 0x00000000);
1613 /* SPRGs */
1614 spr_register(env, SPR_USPRG0, "USPRG0",
1615 &spr_read_generic, &spr_write_generic,
1616 &spr_read_generic, &spr_write_generic,
1617 0x00000000);
1618 spr_register(env, SPR_SPRG4, "SPRG4",
1619 SPR_NOACCESS, SPR_NOACCESS,
1620 &spr_read_generic, &spr_write_generic,
1621 0x00000000);
1622 spr_register(env, SPR_SPRG5, "SPRG5",
1623 SPR_NOACCESS, SPR_NOACCESS,
1624 &spr_read_generic, &spr_write_generic,
1625 0x00000000);
1626 spr_register(env, SPR_SPRG6, "SPRG6",
1627 SPR_NOACCESS, SPR_NOACCESS,
1628 &spr_read_generic, &spr_write_generic,
1629 0x00000000);
1630 spr_register(env, SPR_SPRG7, "SPRG7",
1631 SPR_NOACCESS, SPR_NOACCESS,
1632 &spr_read_generic, &spr_write_generic,
1633 0x00000000);
1634 }
1635
1636 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1637 uint32_t maxsize, uint32_t flags,
1638 uint32_t nentries)
1639 {
1640 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1641 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1642 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1643 flags | nentries;
1644 }
1645
1646 /* BookE 2.06 storage control registers */
1647 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1648 uint32_t *tlbncfg)
1649 {
1650 #if !defined(CONFIG_USER_ONLY)
1651 const char *mas_names[8] = {
1652 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1653 };
1654 int mas_sprn[8] = {
1655 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1656 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1657 };
1658 int i;
1659
1660 /* TLB assist registers */
1661 /* XXX : not implemented */
1662 for (i = 0; i < 8; i++) {
1663 void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1664 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1665 uea_write = &spr_write_generic;
1666 }
1667 if (mas_mask & (1 << i)) {
1668 spr_register(env, mas_sprn[i], mas_names[i],
1669 SPR_NOACCESS, SPR_NOACCESS,
1670 &spr_read_generic, uea_write,
1671 0x00000000);
1672 }
1673 }
1674 if (env->nb_pids > 1) {
1675 /* XXX : not implemented */
1676 spr_register(env, SPR_BOOKE_PID1, "PID1",
1677 SPR_NOACCESS, SPR_NOACCESS,
1678 &spr_read_generic, &spr_write_booke_pid,
1679 0x00000000);
1680 }
1681 if (env->nb_pids > 2) {
1682 /* XXX : not implemented */
1683 spr_register(env, SPR_BOOKE_PID2, "PID2",
1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, &spr_write_booke_pid,
1686 0x00000000);
1687 }
1688 /* XXX : not implemented */
1689 spr_register(env, SPR_MMUCFG, "MMUCFG",
1690 SPR_NOACCESS, SPR_NOACCESS,
1691 &spr_read_generic, SPR_NOACCESS,
1692 0x00000000); /* TOFIX */
1693 switch (env->nb_ways) {
1694 case 4:
1695 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1696 SPR_NOACCESS, SPR_NOACCESS,
1697 &spr_read_generic, SPR_NOACCESS,
1698 tlbncfg[3]);
1699 /* Fallthru */
1700 case 3:
1701 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1702 SPR_NOACCESS, SPR_NOACCESS,
1703 &spr_read_generic, SPR_NOACCESS,
1704 tlbncfg[2]);
1705 /* Fallthru */
1706 case 2:
1707 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1708 SPR_NOACCESS, SPR_NOACCESS,
1709 &spr_read_generic, SPR_NOACCESS,
1710 tlbncfg[1]);
1711 /* Fallthru */
1712 case 1:
1713 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1714 SPR_NOACCESS, SPR_NOACCESS,
1715 &spr_read_generic, SPR_NOACCESS,
1716 tlbncfg[0]);
1717 /* Fallthru */
1718 case 0:
1719 default:
1720 break;
1721 }
1722 #endif
1723
1724 gen_spr_usprgh(env);
1725 }
1726
1727 /* SPR specific to PowerPC 440 implementation */
1728 static void gen_spr_440 (CPUPPCState *env)
1729 {
1730 /* Cache control */
1731 /* XXX : not implemented */
1732 spr_register(env, SPR_440_DNV0, "DNV0",
1733 SPR_NOACCESS, SPR_NOACCESS,
1734 &spr_read_generic, &spr_write_generic,
1735 0x00000000);
1736 /* XXX : not implemented */
1737 spr_register(env, SPR_440_DNV1, "DNV1",
1738 SPR_NOACCESS, SPR_NOACCESS,
1739 &spr_read_generic, &spr_write_generic,
1740 0x00000000);
1741 /* XXX : not implemented */
1742 spr_register(env, SPR_440_DNV2, "DNV2",
1743 SPR_NOACCESS, SPR_NOACCESS,
1744 &spr_read_generic, &spr_write_generic,
1745 0x00000000);
1746 /* XXX : not implemented */
1747 spr_register(env, SPR_440_DNV3, "DNV3",
1748 SPR_NOACCESS, SPR_NOACCESS,
1749 &spr_read_generic, &spr_write_generic,
1750 0x00000000);
1751 /* XXX : not implemented */
1752 spr_register(env, SPR_440_DTV0, "DTV0",
1753 SPR_NOACCESS, SPR_NOACCESS,
1754 &spr_read_generic, &spr_write_generic,
1755 0x00000000);
1756 /* XXX : not implemented */
1757 spr_register(env, SPR_440_DTV1, "DTV1",
1758 SPR_NOACCESS, SPR_NOACCESS,
1759 &spr_read_generic, &spr_write_generic,
1760 0x00000000);
1761 /* XXX : not implemented */
1762 spr_register(env, SPR_440_DTV2, "DTV2",
1763 SPR_NOACCESS, SPR_NOACCESS,
1764 &spr_read_generic, &spr_write_generic,
1765 0x00000000);
1766 /* XXX : not implemented */
1767 spr_register(env, SPR_440_DTV3, "DTV3",
1768 SPR_NOACCESS, SPR_NOACCESS,
1769 &spr_read_generic, &spr_write_generic,
1770 0x00000000);
1771 /* XXX : not implemented */
1772 spr_register(env, SPR_440_DVLIM, "DVLIM",
1773 SPR_NOACCESS, SPR_NOACCESS,
1774 &spr_read_generic, &spr_write_generic,
1775 0x00000000);
1776 /* XXX : not implemented */
1777 spr_register(env, SPR_440_INV0, "INV0",
1778 SPR_NOACCESS, SPR_NOACCESS,
1779 &spr_read_generic, &spr_write_generic,
1780 0x00000000);
1781 /* XXX : not implemented */
1782 spr_register(env, SPR_440_INV1, "INV1",
1783 SPR_NOACCESS, SPR_NOACCESS,
1784 &spr_read_generic, &spr_write_generic,
1785 0x00000000);
1786 /* XXX : not implemented */
1787 spr_register(env, SPR_440_INV2, "INV2",
1788 SPR_NOACCESS, SPR_NOACCESS,
1789 &spr_read_generic, &spr_write_generic,
1790 0x00000000);
1791 /* XXX : not implemented */
1792 spr_register(env, SPR_440_INV3, "INV3",
1793 SPR_NOACCESS, SPR_NOACCESS,
1794 &spr_read_generic, &spr_write_generic,
1795 0x00000000);
1796 /* XXX : not implemented */
1797 spr_register(env, SPR_440_ITV0, "ITV0",
1798 SPR_NOACCESS, SPR_NOACCESS,
1799 &spr_read_generic, &spr_write_generic,
1800 0x00000000);
1801 /* XXX : not implemented */
1802 spr_register(env, SPR_440_ITV1, "ITV1",
1803 SPR_NOACCESS, SPR_NOACCESS,
1804 &spr_read_generic, &spr_write_generic,
1805 0x00000000);
1806 /* XXX : not implemented */
1807 spr_register(env, SPR_440_ITV2, "ITV2",
1808 SPR_NOACCESS, SPR_NOACCESS,
1809 &spr_read_generic, &spr_write_generic,
1810 0x00000000);
1811 /* XXX : not implemented */
1812 spr_register(env, SPR_440_ITV3, "ITV3",
1813 SPR_NOACCESS, SPR_NOACCESS,
1814 &spr_read_generic, &spr_write_generic,
1815 0x00000000);
1816 /* XXX : not implemented */
1817 spr_register(env, SPR_440_IVLIM, "IVLIM",
1818 SPR_NOACCESS, SPR_NOACCESS,
1819 &spr_read_generic, &spr_write_generic,
1820 0x00000000);
1821 /* Cache debug */
1822 /* XXX : not implemented */
1823 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1824 SPR_NOACCESS, SPR_NOACCESS,
1825 &spr_read_generic, SPR_NOACCESS,
1826 0x00000000);
1827 /* XXX : not implemented */
1828 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1829 SPR_NOACCESS, SPR_NOACCESS,
1830 &spr_read_generic, SPR_NOACCESS,
1831 0x00000000);
1832 /* XXX : not implemented */
1833 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1834 SPR_NOACCESS, SPR_NOACCESS,
1835 &spr_read_generic, SPR_NOACCESS,
1836 0x00000000);
1837 /* XXX : not implemented */
1838 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1839 SPR_NOACCESS, SPR_NOACCESS,
1840 &spr_read_generic, SPR_NOACCESS,
1841 0x00000000);
1842 /* XXX : not implemented */
1843 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1844 SPR_NOACCESS, SPR_NOACCESS,
1845 &spr_read_generic, SPR_NOACCESS,
1846 0x00000000);
1847 /* XXX : not implemented */
1848 spr_register(env, SPR_440_DBDR, "DBDR",
1849 SPR_NOACCESS, SPR_NOACCESS,
1850 &spr_read_generic, &spr_write_generic,
1851 0x00000000);
1852 /* Processor control */
1853 spr_register(env, SPR_4xx_CCR0, "CCR0",
1854 SPR_NOACCESS, SPR_NOACCESS,
1855 &spr_read_generic, &spr_write_generic,
1856 0x00000000);
1857 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1858 SPR_NOACCESS, SPR_NOACCESS,
1859 &spr_read_generic, SPR_NOACCESS,
1860 0x00000000);
1861 /* Storage control */
1862 spr_register(env, SPR_440_MMUCR, "MMUCR",
1863 SPR_NOACCESS, SPR_NOACCESS,
1864 &spr_read_generic, &spr_write_generic,
1865 0x00000000);
1866 }
1867
1868 /* SPR shared between PowerPC 40x implementations */
1869 static void gen_spr_40x (CPUPPCState *env)
1870 {
1871 /* Cache */
1872 /* not emulated, as QEMU do not emulate caches */
1873 spr_register(env, SPR_40x_DCCR, "DCCR",
1874 SPR_NOACCESS, SPR_NOACCESS,
1875 &spr_read_generic, &spr_write_generic,
1876 0x00000000);
1877 /* not emulated, as QEMU do not emulate caches */
1878 spr_register(env, SPR_40x_ICCR, "ICCR",
1879 SPR_NOACCESS, SPR_NOACCESS,
1880 &spr_read_generic, &spr_write_generic,
1881 0x00000000);
1882 /* not emulated, as QEMU do not emulate caches */
1883 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1884 SPR_NOACCESS, SPR_NOACCESS,
1885 &spr_read_generic, SPR_NOACCESS,
1886 0x00000000);
1887 /* Exception */
1888 spr_register(env, SPR_40x_DEAR, "DEAR",
1889 SPR_NOACCESS, SPR_NOACCESS,
1890 &spr_read_generic, &spr_write_generic,
1891 0x00000000);
1892 spr_register(env, SPR_40x_ESR, "ESR",
1893 SPR_NOACCESS, SPR_NOACCESS,
1894 &spr_read_generic, &spr_write_generic,
1895 0x00000000);
1896 spr_register(env, SPR_40x_EVPR, "EVPR",
1897 SPR_NOACCESS, SPR_NOACCESS,
1898 &spr_read_generic, &spr_write_excp_prefix,
1899 0x00000000);
1900 spr_register(env, SPR_40x_SRR2, "SRR2",
1901 &spr_read_generic, &spr_write_generic,
1902 &spr_read_generic, &spr_write_generic,
1903 0x00000000);
1904 spr_register(env, SPR_40x_SRR3, "SRR3",
1905 &spr_read_generic, &spr_write_generic,
1906 &spr_read_generic, &spr_write_generic,
1907 0x00000000);
1908 /* Timers */
1909 spr_register(env, SPR_40x_PIT, "PIT",
1910 SPR_NOACCESS, SPR_NOACCESS,
1911 &spr_read_40x_pit, &spr_write_40x_pit,
1912 0x00000000);
1913 spr_register(env, SPR_40x_TCR, "TCR",
1914 SPR_NOACCESS, SPR_NOACCESS,
1915 &spr_read_generic, &spr_write_booke_tcr,
1916 0x00000000);
1917 spr_register(env, SPR_40x_TSR, "TSR",
1918 SPR_NOACCESS, SPR_NOACCESS,
1919 &spr_read_generic, &spr_write_booke_tsr,
1920 0x00000000);
1921 }
1922
1923 /* SPR specific to PowerPC 405 implementation */
1924 static void gen_spr_405 (CPUPPCState *env)
1925 {
1926 /* MMU */
1927 spr_register(env, SPR_40x_PID, "PID",
1928 SPR_NOACCESS, SPR_NOACCESS,
1929 &spr_read_generic, &spr_write_generic,
1930 0x00000000);
1931 spr_register(env, SPR_4xx_CCR0, "CCR0",
1932 SPR_NOACCESS, SPR_NOACCESS,
1933 &spr_read_generic, &spr_write_generic,
1934 0x00700000);
1935 /* Debug interface */
1936 /* XXX : not implemented */
1937 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1938 SPR_NOACCESS, SPR_NOACCESS,
1939 &spr_read_generic, &spr_write_40x_dbcr0,
1940 0x00000000);
1941 /* XXX : not implemented */
1942 spr_register(env, SPR_405_DBCR1, "DBCR1",
1943 SPR_NOACCESS, SPR_NOACCESS,
1944 &spr_read_generic, &spr_write_generic,
1945 0x00000000);
1946 /* XXX : not implemented */
1947 spr_register(env, SPR_40x_DBSR, "DBSR",
1948 SPR_NOACCESS, SPR_NOACCESS,
1949 &spr_read_generic, &spr_write_clear,
1950 /* Last reset was system reset */
1951 0x00000300);
1952 /* XXX : not implemented */
1953 spr_register(env, SPR_40x_DAC1, "DAC1",
1954 SPR_NOACCESS, SPR_NOACCESS,
1955 &spr_read_generic, &spr_write_generic,
1956 0x00000000);
1957 spr_register(env, SPR_40x_DAC2, "DAC2",
1958 SPR_NOACCESS, SPR_NOACCESS,
1959 &spr_read_generic, &spr_write_generic,
1960 0x00000000);
1961 /* XXX : not implemented */
1962 spr_register(env, SPR_405_DVC1, "DVC1",
1963 SPR_NOACCESS, SPR_NOACCESS,
1964 &spr_read_generic, &spr_write_generic,
1965 0x00000000);
1966 /* XXX : not implemented */
1967 spr_register(env, SPR_405_DVC2, "DVC2",
1968 SPR_NOACCESS, SPR_NOACCESS,
1969 &spr_read_generic, &spr_write_generic,
1970 0x00000000);
1971 /* XXX : not implemented */
1972 spr_register(env, SPR_40x_IAC1, "IAC1",
1973 SPR_NOACCESS, SPR_NOACCESS,
1974 &spr_read_generic, &spr_write_generic,
1975 0x00000000);
1976 spr_register(env, SPR_40x_IAC2, "IAC2",
1977 SPR_NOACCESS, SPR_NOACCESS,
1978 &spr_read_generic, &spr_write_generic,
1979 0x00000000);
1980 /* XXX : not implemented */
1981 spr_register(env, SPR_405_IAC3, "IAC3",
1982 SPR_NOACCESS, SPR_NOACCESS,
1983 &spr_read_generic, &spr_write_generic,
1984 0x00000000);
1985 /* XXX : not implemented */
1986 spr_register(env, SPR_405_IAC4, "IAC4",
1987 SPR_NOACCESS, SPR_NOACCESS,
1988 &spr_read_generic, &spr_write_generic,
1989 0x00000000);
1990 /* Storage control */
1991 /* XXX: TODO: not implemented */
1992 spr_register(env, SPR_405_SLER, "SLER",
1993 SPR_NOACCESS, SPR_NOACCESS,
1994 &spr_read_generic, &spr_write_40x_sler,
1995 0x00000000);
1996 spr_register(env, SPR_40x_ZPR, "ZPR",
1997 SPR_NOACCESS, SPR_NOACCESS,
1998 &spr_read_generic, &spr_write_generic,
1999 0x00000000);
2000 /* XXX : not implemented */
2001 spr_register(env, SPR_405_SU0R, "SU0R",
2002 SPR_NOACCESS, SPR_NOACCESS,
2003 &spr_read_generic, &spr_write_generic,
2004 0x00000000);
2005 /* SPRG */
2006 spr_register(env, SPR_USPRG0, "USPRG0",
2007 &spr_read_ureg, SPR_NOACCESS,
2008 &spr_read_ureg, SPR_NOACCESS,
2009 0x00000000);
2010 spr_register(env, SPR_SPRG4, "SPRG4",
2011 SPR_NOACCESS, SPR_NOACCESS,
2012 &spr_read_generic, &spr_write_generic,
2013 0x00000000);
2014 spr_register(env, SPR_SPRG5, "SPRG5",
2015 SPR_NOACCESS, SPR_NOACCESS,
2016 spr_read_generic, &spr_write_generic,
2017 0x00000000);
2018 spr_register(env, SPR_SPRG6, "SPRG6",
2019 SPR_NOACCESS, SPR_NOACCESS,
2020 spr_read_generic, &spr_write_generic,
2021 0x00000000);
2022 spr_register(env, SPR_SPRG7, "SPRG7",
2023 SPR_NOACCESS, SPR_NOACCESS,
2024 spr_read_generic, &spr_write_generic,
2025 0x00000000);
2026 gen_spr_usprgh(env);
2027 }
2028
2029 /* SPR shared between PowerPC 401 & 403 implementations */
2030 static void gen_spr_401_403 (CPUPPCState *env)
2031 {
2032 /* Time base */
2033 spr_register(env, SPR_403_VTBL, "TBL",
2034 &spr_read_tbl, SPR_NOACCESS,
2035 &spr_read_tbl, SPR_NOACCESS,
2036 0x00000000);
2037 spr_register(env, SPR_403_TBL, "TBL",
2038 SPR_NOACCESS, SPR_NOACCESS,
2039 SPR_NOACCESS, &spr_write_tbl,
2040 0x00000000);
2041 spr_register(env, SPR_403_VTBU, "TBU",
2042 &spr_read_tbu, SPR_NOACCESS,
2043 &spr_read_tbu, SPR_NOACCESS,
2044 0x00000000);
2045 spr_register(env, SPR_403_TBU, "TBU",
2046 SPR_NOACCESS, SPR_NOACCESS,
2047 SPR_NOACCESS, &spr_write_tbu,
2048 0x00000000);
2049 /* Debug */
2050 /* not emulated, as QEMU do not emulate caches */
2051 spr_register(env, SPR_403_CDBCR, "CDBCR",
2052 SPR_NOACCESS, SPR_NOACCESS,
2053 &spr_read_generic, &spr_write_generic,
2054 0x00000000);
2055 }
2056
2057 /* SPR specific to PowerPC 401 implementation */
2058 static void gen_spr_401 (CPUPPCState *env)
2059 {
2060 /* Debug interface */
2061 /* XXX : not implemented */
2062 spr_register(env, SPR_40x_DBCR0, "DBCR",
2063 SPR_NOACCESS, SPR_NOACCESS,
2064 &spr_read_generic, &spr_write_40x_dbcr0,
2065 0x00000000);
2066 /* XXX : not implemented */
2067 spr_register(env, SPR_40x_DBSR, "DBSR",
2068 SPR_NOACCESS, SPR_NOACCESS,
2069 &spr_read_generic, &spr_write_clear,
2070 /* Last reset was system reset */
2071 0x00000300);
2072 /* XXX : not implemented */
2073 spr_register(env, SPR_40x_DAC1, "DAC",
2074 SPR_NOACCESS, SPR_NOACCESS,
2075 &spr_read_generic, &spr_write_generic,
2076 0x00000000);
2077 /* XXX : not implemented */
2078 spr_register(env, SPR_40x_IAC1, "IAC",
2079 SPR_NOACCESS, SPR_NOACCESS,
2080 &spr_read_generic, &spr_write_generic,
2081 0x00000000);
2082 /* Storage control */
2083 /* XXX: TODO: not implemented */
2084 spr_register(env, SPR_405_SLER, "SLER",
2085 SPR_NOACCESS, SPR_NOACCESS,
2086 &spr_read_generic, &spr_write_40x_sler,
2087 0x00000000);
2088 /* not emulated, as QEMU never does speculative access */
2089 spr_register(env, SPR_40x_SGR, "SGR",
2090 SPR_NOACCESS, SPR_NOACCESS,
2091 &spr_read_generic, &spr_write_generic,
2092 0xFFFFFFFF);
2093 /* not emulated, as QEMU do not emulate caches */
2094 spr_register(env, SPR_40x_DCWR, "DCWR",
2095 SPR_NOACCESS, SPR_NOACCESS,
2096 &spr_read_generic, &spr_write_generic,
2097 0x00000000);
2098 }
2099
2100 static void gen_spr_401x2 (CPUPPCState *env)
2101 {
2102 gen_spr_401(env);
2103 spr_register(env, SPR_40x_PID, "PID",
2104 SPR_NOACCESS, SPR_NOACCESS,
2105 &spr_read_generic, &spr_write_generic,
2106 0x00000000);
2107 spr_register(env, SPR_40x_ZPR, "ZPR",
2108 SPR_NOACCESS, SPR_NOACCESS,
2109 &spr_read_generic, &spr_write_generic,
2110 0x00000000);
2111 }
2112
2113 /* SPR specific to PowerPC 403 implementation */
2114 static void gen_spr_403 (CPUPPCState *env)
2115 {
2116 /* Debug interface */
2117 /* XXX : not implemented */
2118 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2119 SPR_NOACCESS, SPR_NOACCESS,
2120 &spr_read_generic, &spr_write_40x_dbcr0,
2121 0x00000000);
2122 /* XXX : not implemented */
2123 spr_register(env, SPR_40x_DBSR, "DBSR",
2124 SPR_NOACCESS, SPR_NOACCESS,
2125 &spr_read_generic, &spr_write_clear,
2126 /* Last reset was system reset */
2127 0x00000300);
2128 /* XXX : not implemented */
2129 spr_register(env, SPR_40x_DAC1, "DAC1",
2130 SPR_NOACCESS, SPR_NOACCESS,
2131 &spr_read_generic, &spr_write_generic,
2132 0x00000000);
2133 /* XXX : not implemented */
2134 spr_register(env, SPR_40x_DAC2, "DAC2",
2135 SPR_NOACCESS, SPR_NOACCESS,
2136 &spr_read_generic, &spr_write_generic,
2137 0x00000000);
2138 /* XXX : not implemented */
2139 spr_register(env, SPR_40x_IAC1, "IAC1",
2140 SPR_NOACCESS, SPR_NOACCESS,
2141 &spr_read_generic, &spr_write_generic,
2142 0x00000000);
2143 /* XXX : not implemented */
2144 spr_register(env, SPR_40x_IAC2, "IAC2",
2145 SPR_NOACCESS, SPR_NOACCESS,
2146 &spr_read_generic, &spr_write_generic,
2147 0x00000000);
2148 }
2149
2150 static void gen_spr_403_real (CPUPPCState *env)
2151 {
2152 spr_register(env, SPR_403_PBL1, "PBL1",
2153 SPR_NOACCESS, SPR_NOACCESS,
2154 &spr_read_403_pbr, &spr_write_403_pbr,
2155 0x00000000);
2156 spr_register(env, SPR_403_PBU1, "PBU1",
2157 SPR_NOACCESS, SPR_NOACCESS,
2158 &spr_read_403_pbr, &spr_write_403_pbr,
2159 0x00000000);
2160 spr_register(env, SPR_403_PBL2, "PBL2",
2161 SPR_NOACCESS, SPR_NOACCESS,
2162 &spr_read_403_pbr, &spr_write_403_pbr,
2163 0x00000000);
2164 spr_register(env, SPR_403_PBU2, "PBU2",
2165 SPR_NOACCESS, SPR_NOACCESS,
2166 &spr_read_403_pbr, &spr_write_403_pbr,
2167 0x00000000);
2168 }
2169
2170 static void gen_spr_403_mmu (CPUPPCState *env)
2171 {
2172 /* MMU */
2173 spr_register(env, SPR_40x_PID, "PID",
2174 SPR_NOACCESS, SPR_NOACCESS,
2175 &spr_read_generic, &spr_write_generic,
2176 0x00000000);
2177 spr_register(env, SPR_40x_ZPR, "ZPR",
2178 SPR_NOACCESS, SPR_NOACCESS,
2179 &spr_read_generic, &spr_write_generic,
2180 0x00000000);
2181 }
2182
2183 /* SPR specific to PowerPC compression coprocessor extension */
2184 static void gen_spr_compress (CPUPPCState *env)
2185 {
2186 /* XXX : not implemented */
2187 spr_register(env, SPR_401_SKR, "SKR",
2188 SPR_NOACCESS, SPR_NOACCESS,
2189 &spr_read_generic, &spr_write_generic,
2190 0x00000000);
2191 }
2192
2193 static void gen_spr_5xx_8xx (CPUPPCState *env)
2194 {
2195 /* Exception processing */
2196 spr_register_kvm(env, SPR_DSISR, "DSISR",
2197 SPR_NOACCESS, SPR_NOACCESS,
2198 &spr_read_generic, &spr_write_generic,
2199 KVM_REG_PPC_DSISR, 0x00000000);
2200 spr_register_kvm(env, SPR_DAR, "DAR",
2201 SPR_NOACCESS, SPR_NOACCESS,
2202 &spr_read_generic, &spr_write_generic,
2203 KVM_REG_PPC_DAR, 0x00000000);
2204 /* Timer */
2205 spr_register(env, SPR_DECR, "DECR",
2206 SPR_NOACCESS, SPR_NOACCESS,
2207 &spr_read_decr, &spr_write_decr,
2208 0x00000000);
2209 /* XXX : not implemented */
2210 spr_register(env, SPR_MPC_EIE, "EIE",
2211 SPR_NOACCESS, SPR_NOACCESS,
2212 &spr_read_generic, &spr_write_generic,
2213 0x00000000);
2214 /* XXX : not implemented */
2215 spr_register(env, SPR_MPC_EID, "EID",
2216 SPR_NOACCESS, SPR_NOACCESS,
2217 &spr_read_generic, &spr_write_generic,
2218 0x00000000);
2219 /* XXX : not implemented */
2220 spr_register(env, SPR_MPC_NRI, "NRI",
2221 SPR_NOACCESS, SPR_NOACCESS,
2222 &spr_read_generic, &spr_write_generic,
2223 0x00000000);
2224 /* XXX : not implemented */
2225 spr_register(env, SPR_MPC_CMPA, "CMPA",
2226 SPR_NOACCESS, SPR_NOACCESS,
2227 &spr_read_generic, &spr_write_generic,
2228 0x00000000);
2229 /* XXX : not implemented */
2230 spr_register(env, SPR_MPC_CMPB, "CMPB",
2231 SPR_NOACCESS, SPR_NOACCESS,
2232 &spr_read_generic, &spr_write_generic,
2233 0x00000000);
2234 /* XXX : not implemented */
2235 spr_register(env, SPR_MPC_CMPC, "CMPC",
2236 SPR_NOACCESS, SPR_NOACCESS,
2237 &spr_read_generic, &spr_write_generic,
2238 0x00000000);
2239 /* XXX : not implemented */
2240 spr_register(env, SPR_MPC_CMPD, "CMPD",
2241 SPR_NOACCESS, SPR_NOACCESS,
2242 &spr_read_generic, &spr_write_generic,
2243 0x00000000);
2244 /* XXX : not implemented */
2245 spr_register(env, SPR_MPC_ECR, "ECR",
2246 SPR_NOACCESS, SPR_NOACCESS,
2247 &spr_read_generic, &spr_write_generic,
2248 0x00000000);
2249 /* XXX : not implemented */
2250 spr_register(env, SPR_MPC_DER, "DER",
2251 SPR_NOACCESS, SPR_NOACCESS,
2252 &spr_read_generic, &spr_write_generic,
2253 0x00000000);
2254 /* XXX : not implemented */
2255 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2256 SPR_NOACCESS, SPR_NOACCESS,
2257 &spr_read_generic, &spr_write_generic,
2258 0x00000000);
2259 /* XXX : not implemented */
2260 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2261 SPR_NOACCESS, SPR_NOACCESS,
2262 &spr_read_generic, &spr_write_generic,
2263 0x00000000);
2264 /* XXX : not implemented */
2265 spr_register(env, SPR_MPC_CMPE, "CMPE",
2266 SPR_NOACCESS, SPR_NOACCESS,
2267 &spr_read_generic, &spr_write_generic,
2268 0x00000000);
2269 /* XXX : not implemented */
2270 spr_register(env, SPR_MPC_CMPF, "CMPF",
2271 SPR_NOACCESS, SPR_NOACCESS,
2272 &spr_read_generic, &spr_write_generic,
2273 0x00000000);
2274 /* XXX : not implemented */
2275 spr_register(env, SPR_MPC_CMPG, "CMPG",
2276 SPR_NOACCESS, SPR_NOACCESS,
2277 &spr_read_generic, &spr_write_generic,
2278 0x00000000);
2279 /* XXX : not implemented */
2280 spr_register(env, SPR_MPC_CMPH, "CMPH",
2281 SPR_NOACCESS, SPR_NOACCESS,
2282 &spr_read_generic, &spr_write_generic,
2283 0x00000000);
2284 /* XXX : not implemented */
2285 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2286 SPR_NOACCESS, SPR_NOACCESS,
2287 &spr_read_generic, &spr_write_generic,
2288 0x00000000);
2289 /* XXX : not implemented */
2290 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2291 SPR_NOACCESS, SPR_NOACCESS,
2292 &spr_read_generic, &spr_write_generic,
2293 0x00000000);
2294 /* XXX : not implemented */
2295 spr_register(env, SPR_MPC_BAR, "BAR",
2296 SPR_NOACCESS, SPR_NOACCESS,
2297 &spr_read_generic, &spr_write_generic,
2298 0x00000000);
2299 /* XXX : not implemented */
2300 spr_register(env, SPR_MPC_DPDR, "DPDR",
2301 SPR_NOACCESS, SPR_NOACCESS,
2302 &spr_read_generic, &spr_write_generic,
2303 0x00000000);
2304 /* XXX : not implemented */
2305 spr_register(env, SPR_MPC_IMMR, "IMMR",
2306 SPR_NOACCESS, SPR_NOACCESS,
2307 &spr_read_generic, &spr_write_generic,
2308 0x00000000);
2309 }
2310
2311 static void gen_spr_5xx (CPUPPCState *env)
2312 {
2313 /* XXX : not implemented */
2314 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2315 SPR_NOACCESS, SPR_NOACCESS,
2316 &spr_read_generic, &spr_write_generic,
2317 0x00000000);
2318 /* XXX : not implemented */
2319 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2320 SPR_NOACCESS, SPR_NOACCESS,
2321 &spr_read_generic, &spr_write_generic,
2322 0x00000000);
2323 /* XXX : not implemented */
2324 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2325 SPR_NOACCESS, SPR_NOACCESS,
2326 &spr_read_generic, &spr_write_generic,
2327 0x00000000);
2328 /* XXX : not implemented */
2329 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2330 SPR_NOACCESS, SPR_NOACCESS,
2331 &spr_read_generic, &spr_write_generic,
2332 0x00000000);
2333 /* XXX : not implemented */
2334 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2335 SPR_NOACCESS, SPR_NOACCESS,
2336 &spr_read_generic, &spr_write_generic,
2337 0x00000000);
2338 /* XXX : not implemented */
2339 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2340 SPR_NOACCESS, SPR_NOACCESS,
2341 &spr_read_generic, &spr_write_generic,
2342 0x00000000);
2343 /* XXX : not implemented */
2344 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2345 SPR_NOACCESS, SPR_NOACCESS,
2346 &spr_read_generic, &spr_write_generic,
2347 0x00000000);
2348 /* XXX : not implemented */
2349 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2350 SPR_NOACCESS, SPR_NOACCESS,
2351 &spr_read_generic, &spr_write_generic,
2352 0x00000000);
2353 /* XXX : not implemented */
2354 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2355 SPR_NOACCESS, SPR_NOACCESS,
2356 &spr_read_generic, &spr_write_generic,
2357 0x00000000);
2358 /* XXX : not implemented */
2359 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2360 SPR_NOACCESS, SPR_NOACCESS,
2361 &spr_read_generic, &spr_write_generic,
2362 0x00000000);
2363 /* XXX : not implemented */
2364 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2365 SPR_NOACCESS, SPR_NOACCESS,
2366 &spr_read_generic, &spr_write_generic,
2367 0x00000000);
2368 /* XXX : not implemented */
2369 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2370 SPR_NOACCESS, SPR_NOACCESS,
2371 &spr_read_generic, &spr_write_generic,
2372 0x00000000);
2373 /* XXX : not implemented */
2374 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2375 SPR_NOACCESS, SPR_NOACCESS,
2376 &spr_read_generic, &spr_write_generic,
2377 0x00000000);
2378 /* XXX : not implemented */
2379 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2380 SPR_NOACCESS, SPR_NOACCESS,
2381 &spr_read_generic, &spr_write_generic,
2382 0x00000000);
2383 /* XXX : not implemented */
2384 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2385 SPR_NOACCESS, SPR_NOACCESS,
2386 &spr_read_generic, &spr_write_generic,
2387 0x00000000);
2388 /* XXX : not implemented */
2389 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2390 SPR_NOACCESS, SPR_NOACCESS,
2391 &spr_read_generic, &spr_write_generic,
2392 0x00000000);
2393 /* XXX : not implemented */
2394 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2395 SPR_NOACCESS, SPR_NOACCESS,
2396 &spr_read_generic, &spr_write_generic,
2397 0x00000000);
2398 /* XXX : not implemented */
2399 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2400 SPR_NOACCESS, SPR_NOACCESS,
2401 &spr_read_generic, &spr_write_generic,
2402 0x00000000);
2403 /* XXX : not implemented */
2404 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2405 SPR_NOACCESS, SPR_NOACCESS,
2406 &spr_read_generic, &spr_write_generic,
2407 0x00000000);
2408 /* XXX : not implemented */
2409 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2410 SPR_NOACCESS, SPR_NOACCESS,
2411 &spr_read_generic, &spr_write_generic,
2412 0x00000000);
2413 /* XXX : not implemented */
2414 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2415 SPR_NOACCESS, SPR_NOACCESS,
2416 &spr_read_generic, &spr_write_generic,
2417 0x00000000);
2418 }
2419
2420 static void gen_spr_8xx (CPUPPCState *env)
2421 {
2422 /* XXX : not implemented */
2423 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2424 SPR_NOACCESS, SPR_NOACCESS,
2425 &spr_read_generic, &spr_write_generic,
2426 0x00000000);
2427 /* XXX : not implemented */
2428 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2429 SPR_NOACCESS, SPR_NOACCESS,
2430 &spr_read_generic, &spr_write_generic,
2431 0x00000000);
2432 /* XXX : not implemented */
2433 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2434 SPR_NOACCESS, SPR_NOACCESS,
2435 &spr_read_generic, &spr_write_generic,
2436 0x00000000);
2437 /* XXX : not implemented */
2438 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2439 SPR_NOACCESS, SPR_NOACCESS,
2440 &spr_read_generic, &spr_write_generic,
2441 0x00000000);
2442 /* XXX : not implemented */
2443 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2444 SPR_NOACCESS, SPR_NOACCESS,
2445 &spr_read_generic, &spr_write_generic,
2446 0x00000000);
2447 /* XXX : not implemented */
2448 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2449 SPR_NOACCESS, SPR_NOACCESS,
2450 &spr_read_generic, &spr_write_generic,
2451 0x00000000);
2452 /* XXX : not implemented */
2453 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2454 SPR_NOACCESS, SPR_NOACCESS,
2455 &spr_read_generic, &spr_write_generic,
2456 0x00000000);
2457 /* XXX : not implemented */
2458 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2459 SPR_NOACCESS, SPR_NOACCESS,
2460 &spr_read_generic, &spr_write_generic,
2461 0x00000000);
2462 /* XXX : not implemented */
2463 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2464 SPR_NOACCESS, SPR_NOACCESS,
2465 &spr_read_generic, &spr_write_generic,
2466 0x00000000);
2467 /* XXX : not implemented */
2468 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2469 SPR_NOACCESS, SPR_NOACCESS,
2470 &spr_read_generic, &spr_write_generic,
2471 0x00000000);
2472 /* XXX : not implemented */
2473 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2474 SPR_NOACCESS, SPR_NOACCESS,
2475 &spr_read_generic, &spr_write_generic,
2476 0x00000000);
2477 /* XXX : not implemented */
2478 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2479 SPR_NOACCESS, SPR_NOACCESS,
2480 &spr_read_generic, &spr_write_generic,
2481 0x00000000);
2482 /* XXX : not implemented */
2483 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2484 SPR_NOACCESS, SPR_NOACCESS,
2485 &spr_read_generic, &spr_write_generic,
2486 0x00000000);
2487 /* XXX : not implemented */
2488 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2489 SPR_NOACCESS, SPR_NOACCESS,
2490 &spr_read_generic, &spr_write_generic,
2491 0x00000000);
2492 /* XXX : not implemented */
2493 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2494 SPR_NOACCESS, SPR_NOACCESS,
2495 &spr_read_generic, &spr_write_generic,
2496 0x00000000);
2497 /* XXX : not implemented */
2498 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2499 SPR_NOACCESS, SPR_NOACCESS,
2500 &spr_read_generic, &spr_write_generic,
2501 0x00000000);
2502 /* XXX : not implemented */
2503 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2504 SPR_NOACCESS, SPR_NOACCESS,
2505 &spr_read_generic, &spr_write_generic,
2506 0x00000000);
2507 /* XXX : not implemented */
2508 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2509 SPR_NOACCESS, SPR_NOACCESS,
2510 &spr_read_generic, &spr_write_generic,
2511 0x00000000);
2512 /* XXX : not implemented */
2513 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2514 SPR_NOACCESS, SPR_NOACCESS,
2515 &spr_read_generic, &spr_write_generic,
2516 0x00000000);
2517 /* XXX : not implemented */
2518 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2519 SPR_NOACCESS, SPR_NOACCESS,
2520 &spr_read_generic, &spr_write_generic,
2521 0x00000000);
2522 /* XXX : not implemented */
2523 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2524 SPR_NOACCESS, SPR_NOACCESS,
2525 &spr_read_generic, &spr_write_generic,
2526 0x00000000);
2527 /* XXX : not implemented */
2528 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2529 SPR_NOACCESS, SPR_NOACCESS,
2530 &spr_read_generic, &spr_write_generic,
2531 0x00000000);
2532 /* XXX : not implemented */
2533 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2534 SPR_NOACCESS, SPR_NOACCESS,
2535 &spr_read_generic, &spr_write_generic,
2536 0x00000000);
2537 /* XXX : not implemented */
2538 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2539 SPR_NOACCESS, SPR_NOACCESS,
2540 &spr_read_generic, &spr_write_generic,
2541 0x00000000);
2542 /* XXX : not implemented */
2543 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2544 SPR_NOACCESS, SPR_NOACCESS,
2545 &spr_read_generic, &spr_write_generic,
2546 0x00000000);
2547 }
2548
2549 // XXX: TODO
2550 /*
2551 * AMR => SPR 29 (Power 2.04)
2552 * CTRL => SPR 136 (Power 2.04)
2553 * CTRL => SPR 152 (Power 2.04)
2554 * SCOMC => SPR 276 (64 bits ?)
2555 * SCOMD => SPR 277 (64 bits ?)
2556 * TBU40 => SPR 286 (Power 2.04 hypv)
2557 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2558 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2559 * HDSISR => SPR 306 (Power 2.04 hypv)
2560 * HDAR => SPR 307 (Power 2.04 hypv)
2561 * PURR => SPR 309 (Power 2.04 hypv)
2562 * HDEC => SPR 310 (Power 2.04 hypv)
2563 * HIOR => SPR 311 (hypv)
2564 * RMOR => SPR 312 (970)
2565 * HRMOR => SPR 313 (Power 2.04 hypv)
2566 * HSRR0 => SPR 314 (Power 2.04 hypv)
2567 * HSRR1 => SPR 315 (Power 2.04 hypv)
2568 * LPCR => SPR 316 (970)
2569 * LPIDR => SPR 317 (970)
2570 * EPR => SPR 702 (Power 2.04 emb)
2571 * perf => 768-783 (Power 2.04)
2572 * perf => 784-799 (Power 2.04)
2573 * PPR => SPR 896 (Power 2.04)
2574 * EPLC => SPR 947 (Power 2.04 emb)
2575 * EPSC => SPR 948 (Power 2.04 emb)
2576 * DABRX => 1015 (Power 2.04 hypv)
2577 * FPECR => SPR 1022 (?)
2578 * ... and more (thermal management, performance counters, ...)
2579 */
2580
2581 /*****************************************************************************/
2582 /* Exception vectors models */
2583 static void init_excp_4xx_real (CPUPPCState *env)
2584 {
2585 #if !defined(CONFIG_USER_ONLY)
2586 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2587 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2588 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2589 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2590 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2591 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2592 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2593 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2594 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2595 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2596 env->ivor_mask = 0x0000FFF0UL;
2597 env->ivpr_mask = 0xFFFF0000UL;
2598 /* Hardware reset vector */
2599 env->hreset_vector = 0xFFFFFFFCUL;
2600 #endif
2601 }
2602
2603 static void init_excp_4xx_softmmu (CPUPPCState *env)
2604 {
2605 #if !defined(CONFIG_USER_ONLY)
2606 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2607 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2608 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2609 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2610 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2611 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2612 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2613 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2614 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2615 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2616 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2617 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2618 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2619 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2620 env->ivor_mask = 0x0000FFF0UL;
2621 env->ivpr_mask = 0xFFFF0000UL;
2622 /* Hardware reset vector */
2623 env->hreset_vector = 0xFFFFFFFCUL;
2624 #endif
2625 }
2626
2627 static void init_excp_MPC5xx (CPUPPCState *env)
2628 {
2629 #if !defined(CONFIG_USER_ONLY)
2630 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2631 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2632 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2633 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2634 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2635 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2636 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2637 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2638 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2639 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2640 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2641 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2642 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2643 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2644 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2645 env->ivor_mask = 0x0000FFF0UL;
2646 env->ivpr_mask = 0xFFFF0000UL;
2647 /* Hardware reset vector */
2648 env->hreset_vector = 0x00000100UL;
2649 #endif
2650 }
2651
2652 static void init_excp_MPC8xx (CPUPPCState *env)
2653 {
2654 #if !defined(CONFIG_USER_ONLY)
2655 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2656 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2657 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2658 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2659 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2660 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2661 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2662 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2663 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2664 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2665 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2666 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2667 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2668 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2669 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2670 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2671 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2672 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2673 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2674 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2675 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2676 env->ivor_mask = 0x0000FFF0UL;
2677 env->ivpr_mask = 0xFFFF0000UL;
2678 /* Hardware reset vector */
2679 env->hreset_vector = 0x00000100UL;
2680 #endif
2681 }
2682
2683 static void init_excp_G2 (CPUPPCState *env)
2684 {
2685 #if !defined(CONFIG_USER_ONLY)
2686 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2687 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2688 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2689 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2690 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2691 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2692 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2693 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2694 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2695 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2696 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2697 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2698 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2699 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2700 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2701 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2702 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2703 /* Hardware reset vector */
2704 env->hreset_vector = 0x00000100UL;
2705 #endif
2706 }
2707
2708 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2709 {
2710 #if !defined(CONFIG_USER_ONLY)
2711 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2712 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2713 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2714 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2715 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2716 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2717 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2718 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2719 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2720 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2721 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2722 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2723 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2724 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2725 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2726 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2727 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2728 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2729 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2730 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2731 env->ivor_mask = 0x0000FFF7UL;
2732 env->ivpr_mask = ivpr_mask;
2733 /* Hardware reset vector */
2734 env->hreset_vector = 0xFFFFFFFCUL;
2735 #endif
2736 }
2737
2738 static void init_excp_BookE (CPUPPCState *env)
2739 {
2740 #if !defined(CONFIG_USER_ONLY)
2741 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2742 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2743 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2744 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2745 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2746 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2747 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2748 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2749 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2750 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2751 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2752 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2753 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2754 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2755 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2756 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2757 env->ivor_mask = 0x0000FFE0UL;
2758 env->ivpr_mask = 0xFFFF0000UL;
2759 /* Hardware reset vector */
2760 env->hreset_vector = 0xFFFFFFFCUL;
2761 #endif
2762 }
2763
2764 static void init_excp_601 (CPUPPCState *env)
2765 {
2766 #if !defined(CONFIG_USER_ONLY)
2767 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2768 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2769 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2770 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2771 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2772 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2773 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2774 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2775 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2776 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2777 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2778 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2779 /* Hardware reset vector */
2780 env->hreset_vector = 0x00000100UL;
2781 #endif
2782 }
2783
2784 static void init_excp_602 (CPUPPCState *env)
2785 {
2786 #if !defined(CONFIG_USER_ONLY)
2787 /* XXX: exception prefix has a special behavior on 602 */
2788 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2789 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2790 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2791 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2792 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2793 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2794 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2795 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2796 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2797 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2798 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2799 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2800 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2801 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2802 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2803 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2804 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2805 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2806 /* Hardware reset vector */
2807 env->hreset_vector = 0x00000100UL;
2808 #endif
2809 }
2810
2811 static void init_excp_603 (CPUPPCState *env)
2812 {
2813 #if !defined(CONFIG_USER_ONLY)
2814 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2815 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2816 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2817 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2818 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2819 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2820 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2821 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2822 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2823 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2824 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2825 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2826 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2827 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2828 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2829 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2830 /* Hardware reset vector */
2831 env->hreset_vector = 0x00000100UL;
2832 #endif
2833 }
2834
2835 static void init_excp_604 (CPUPPCState *env)
2836 {
2837 #if !defined(CONFIG_USER_ONLY)
2838 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2839 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2840 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2841 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2842 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2843 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2844 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2845 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2846 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2847 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2848 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2849 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2850 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2851 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2852 /* Hardware reset vector */
2853 env->hreset_vector = 0x00000100UL;
2854 #endif
2855 }
2856
2857 static void init_excp_7x0 (CPUPPCState *env)
2858 {
2859 #if !defined(CONFIG_USER_ONLY)
2860 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2861 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2862 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2863 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2864 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2865 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2866 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2867 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2868 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2869 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2870 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2871 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2872 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2873 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2874 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2875 /* Hardware reset vector */
2876 env->hreset_vector = 0x00000100UL;
2877 #endif
2878 }
2879
2880 static void init_excp_750cl (CPUPPCState *env)
2881 {
2882 #if !defined(CONFIG_USER_ONLY)
2883 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2884 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2885 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2886 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2887 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2888 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2889 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2890 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2891 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2892 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2893 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2894 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2895 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2896 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2897 /* Hardware reset vector */
2898 env->hreset_vector = 0x00000100UL;
2899 #endif
2900 }
2901
2902 static void init_excp_750cx (CPUPPCState *env)
2903 {
2904 #if !defined(CONFIG_USER_ONLY)
2905 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2906 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2907 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2908 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2909 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2910 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2911 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2912 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2913 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2914 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2915 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2916 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2917 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2918 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2919 /* Hardware reset vector */
2920 env->hreset_vector = 0x00000100UL;
2921 #endif
2922 }
2923
2924 /* XXX: Check if this is correct */
2925 static void init_excp_7x5 (CPUPPCState *env)
2926 {
2927 #if !defined(CONFIG_USER_ONLY)
2928 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2929 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2930 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2931 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2932 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2933 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2934 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2935 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2936 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2937 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2938 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2939 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2940 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2941 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2942 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2943 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2944 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2945 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2946 /* Hardware reset vector */
2947 env->hreset_vector = 0x00000100UL;
2948 #endif
2949 }
2950
2951 static void init_excp_7400 (CPUPPCState *env)
2952 {
2953 #if !defined(CONFIG_USER_ONLY)
2954 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2955 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2956 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2957 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2958 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2959 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2960 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2961 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2962 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2963 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2964 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2965 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2966 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2967 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2968 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2969 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2970 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2971 /* Hardware reset vector */
2972 env->hreset_vector = 0x00000100UL;
2973 #endif
2974 }
2975
2976 static void init_excp_7450 (CPUPPCState *env)
2977 {
2978 #if !defined(CONFIG_USER_ONLY)
2979 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2980 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2981 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2982 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2983 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2984 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2985 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2986 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2987 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2988 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2989 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2990 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2991 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2992 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2993 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2994 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2995 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2996 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2997 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2998 /* Hardware reset vector */
2999 env->hreset_vector = 0x00000100UL;
3000 #endif
3001 }
3002
3003 #if defined (TARGET_PPC64)
3004 static void init_excp_970 (CPUPPCState *env)
3005 {
3006 #if !defined(CONFIG_USER_ONLY)
3007 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3008 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3009 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3010 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3011 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3012 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3013 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3014 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3015 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3016 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3017 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3018 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3019 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3020 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3021 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3022 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3023 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3024 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3025 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3026 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3027 /* Hardware reset vector */
3028 env->hreset_vector = 0x0000000000000100ULL;
3029 #endif
3030 }
3031
3032 static void init_excp_POWER7 (CPUPPCState *env)
3033 {
3034 #if !defined(CONFIG_USER_ONLY)
3035 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3036 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3037 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3038 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3039 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3040 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3041 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3042 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3043 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3044 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3045 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3046 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3047 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3048 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3049 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3050 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3051 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3052 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3053 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3054 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3055 /* Hardware reset vector */
3056 env->hreset_vector = 0x0000000000000100ULL;
3057 #endif
3058 }
3059 #endif
3060
3061 /*****************************************************************************/
3062 /* Power management enable checks */
3063 static int check_pow_none (CPUPPCState *env)
3064 {
3065 return 0;
3066 }
3067
3068 static int check_pow_nocheck (CPUPPCState *env)
3069 {
3070 return 1;
3071 }
3072
3073 static int check_pow_hid0 (CPUPPCState *env)
3074 {
3075 if (env->spr[SPR_HID0] & 0x00E00000)
3076 return 1;
3077
3078 return 0;
3079 }
3080
3081 static int check_pow_hid0_74xx (CPUPPCState *env)
3082 {
3083 if (env->spr[SPR_HID0] & 0x00600000)
3084 return 1;
3085
3086 return 0;
3087 }
3088
3089 /*****************************************************************************/
3090 /* PowerPC implementations definitions */
3091
3092 #define POWERPC_FAMILY(_name) \
3093 static void \
3094 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3095 \
3096 static const TypeInfo \
3097 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3098 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3099 .parent = TYPE_POWERPC_CPU, \
3100 .abstract = true, \
3101 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3102 }; \
3103 \
3104 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3105 { \
3106 type_register_static( \
3107 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3108 } \
3109 \
3110 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3111 \
3112 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3113
3114 static void init_proc_401 (CPUPPCState *env)
3115 {
3116 gen_spr_40x(env);
3117 gen_spr_401_403(env);
3118 gen_spr_401(env);
3119 init_excp_4xx_real(env);
3120 env->dcache_line_size = 32;
3121 env->icache_line_size = 32;
3122 /* Allocate hardware IRQ controller */
3123 ppc40x_irq_init(env);
3124
3125 SET_FIT_PERIOD(12, 16, 20, 24);
3126 SET_WDT_PERIOD(16, 20, 24, 28);
3127 }
3128
3129 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3130 {
3131 DeviceClass *dc = DEVICE_CLASS(oc);
3132 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3133
3134 dc->desc = "PowerPC 401";
3135 pcc->init_proc = init_proc_401;
3136 pcc->check_pow = check_pow_nocheck;
3137 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3138 PPC_WRTEE | PPC_DCR |
3139 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3140 PPC_CACHE_DCBZ |
3141 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3142 PPC_4xx_COMMON | PPC_40x_EXCP;
3143 pcc->insns_flags2 = PPC_NONE;
3144 pcc->msr_mask = 0x00000000000FD201ULL;
3145 pcc->mmu_model = POWERPC_MMU_REAL;
3146 pcc->excp_model = POWERPC_EXCP_40x;
3147 pcc->bus_model = PPC_FLAGS_INPUT_401;
3148 pcc->bfd_mach = bfd_mach_ppc_403;
3149 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3150 POWERPC_FLAG_BUS_CLK;
3151 }
3152
3153 static void init_proc_401x2 (CPUPPCState *env)
3154 {
3155 gen_spr_40x(env);
3156 gen_spr_401_403(env);
3157 gen_spr_401x2(env);
3158 gen_spr_compress(env);
3159 /* Memory management */
3160 #if !defined(CONFIG_USER_ONLY)
3161 env->nb_tlb = 64;
3162 env->nb_ways = 1;
3163 env->id_tlbs = 0;
3164 env->tlb_type = TLB_EMB;
3165 #endif
3166 init_excp_4xx_softmmu(env);
3167 env->dcache_line_size = 32;
3168 env->icache_line_size = 32;
3169 /* Allocate hardware IRQ controller */
3170 ppc40x_irq_init(env);
3171
3172 SET_FIT_PERIOD(12, 16, 20, 24);
3173 SET_WDT_PERIOD(16, 20, 24, 28);
3174 }
3175
3176 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3177 {
3178 DeviceClass *dc = DEVICE_CLASS(oc);
3179 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3180
3181 dc->desc = "PowerPC 401x2";
3182 pcc->init_proc = init_proc_401x2;
3183 pcc->check_pow = check_pow_nocheck;
3184 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3185 PPC_DCR | PPC_WRTEE |
3186 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3187 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3188 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3189 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3190 PPC_4xx_COMMON | PPC_40x_EXCP;
3191 pcc->insns_flags2 = PPC_NONE;
3192 pcc->msr_mask = 0x00000000001FD231ULL;
3193 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3194 pcc->excp_model = POWERPC_EXCP_40x;
3195 pcc->bus_model = PPC_FLAGS_INPUT_401;
3196 pcc->bfd_mach = bfd_mach_ppc_403;
3197 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3198 POWERPC_FLAG_BUS_CLK;
3199 }
3200
3201 static void init_proc_401x3 (CPUPPCState *env)
3202 {
3203 gen_spr_40x(env);
3204 gen_spr_401_403(env);
3205 gen_spr_401(env);
3206 gen_spr_401x2(env);
3207 gen_spr_compress(env);
3208 init_excp_4xx_softmmu(env);
3209 env->dcache_line_size = 32;
3210 env->icache_line_size = 32;
3211 /* Allocate hardware IRQ controller */
3212 ppc40x_irq_init(env);
3213
3214 SET_FIT_PERIOD(12, 16, 20, 24);
3215 SET_WDT_PERIOD(16, 20, 24, 28);
3216 }
3217
3218 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3219 {
3220 DeviceClass *dc = DEVICE_CLASS(oc);
3221 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3222
3223 dc->desc = "PowerPC 401x3";
3224 pcc->init_proc = init_proc_401x3;
3225 pcc->check_pow = check_pow_nocheck;
3226 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3227 PPC_DCR | PPC_WRTEE |
3228 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3229 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3230 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3231 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3232 PPC_4xx_COMMON | PPC_40x_EXCP;
3233 pcc->insns_flags2 = PPC_NONE;
3234 pcc->msr_mask = 0x00000000001FD631ULL;
3235 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3236 pcc->excp_model = POWERPC_EXCP_40x;
3237 pcc->bus_model = PPC_FLAGS_INPUT_401;
3238 pcc->bfd_mach = bfd_mach_ppc_403;
3239 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3240 POWERPC_FLAG_BUS_CLK;
3241 }
3242
3243 static void init_proc_IOP480 (CPUPPCState *env)
3244 {
3245 gen_spr_40x(env);
3246 gen_spr_401_403(env);
3247 gen_spr_401x2(env);
3248 gen_spr_compress(env);
3249 /* Memory management */
3250 #if !defined(CONFIG_USER_ONLY)
3251 env->nb_tlb = 64;
3252 env->nb_ways = 1;
3253 env->id_tlbs = 0;
3254 env->tlb_type = TLB_EMB;
3255 #endif
3256 init_excp_4xx_softmmu(env);
3257 env->dcache_line_size = 32;
3258 env->icache_line_size = 32;
3259 /* Allocate hardware IRQ controller */
3260 ppc40x_irq_init(env);
3261
3262 SET_FIT_PERIOD(8, 12, 16, 20);
3263 SET_WDT_PERIOD(16, 20, 24, 28);
3264 }
3265
3266 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3267 {
3268 DeviceClass *dc = DEVICE_CLASS(oc);
3269 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3270
3271 dc->desc = "IOP480";
3272 pcc->init_proc = init_proc_IOP480;
3273 pcc->check_pow = check_pow_nocheck;
3274 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3275 PPC_DCR | PPC_WRTEE |
3276 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3277 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3278 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3279 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3280 PPC_4xx_COMMON | PPC_40x_EXCP;
3281 pcc->insns_flags2 = PPC_NONE;
3282 pcc->msr_mask = 0x00000000001FD231ULL;
3283 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3284 pcc->excp_model = POWERPC_EXCP_40x;
3285 pcc->bus_model = PPC_FLAGS_INPUT_401;
3286 pcc->bfd_mach = bfd_mach_ppc_403;
3287 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3288 POWERPC_FLAG_BUS_CLK;
3289 }
3290
3291 static void init_proc_403 (CPUPPCState *env)
3292 {
3293 gen_spr_40x(env);
3294 gen_spr_401_403(env);
3295 gen_spr_403(env);
3296 gen_spr_403_real(env);
3297 init_excp_4xx_real(env);
3298 env->dcache_line_size = 32;
3299 env->icache_line_size = 32;
3300 /* Allocate hardware IRQ controller */
3301 ppc40x_irq_init(env);
3302
3303 SET_FIT_PERIOD(8, 12, 16, 20);
3304 SET_WDT_PERIOD(16, 20, 24, 28);
3305 }
3306
3307 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3308 {
3309 DeviceClass *dc = DEVICE_CLASS(oc);
3310 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3311
3312 dc->desc = "PowerPC 403";
3313 pcc->init_proc = init_proc_403;
3314 pcc->check_pow = check_pow_nocheck;
3315 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3316 PPC_DCR | PPC_WRTEE |
3317 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3318 PPC_CACHE_DCBZ |
3319 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3320 PPC_4xx_COMMON | PPC_40x_EXCP;
3321 pcc->insns_flags2 = PPC_NONE;
3322 pcc->msr_mask = 0x000000000007D00DULL;
3323 pcc->mmu_model = POWERPC_MMU_REAL;
3324 pcc->excp_model = POWERPC_EXCP_40x;
3325 pcc->bus_model = PPC_FLAGS_INPUT_401;
3326 pcc->bfd_mach = bfd_mach_ppc_403;
3327 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3328 POWERPC_FLAG_BUS_CLK;
3329 }
3330
3331 static void init_proc_403GCX (CPUPPCState *env)
3332 {
3333 gen_spr_40x(env);
3334 gen_spr_401_403(env);
3335 gen_spr_403(env);
3336 gen_spr_403_real(env);
3337 gen_spr_403_mmu(env);
3338 /* Bus access control */
3339 /* not emulated, as QEMU never does speculative access */
3340 spr_register(env, SPR_40x_SGR, "SGR",
3341 SPR_NOACCESS, SPR_NOACCESS,
3342 &spr_read_generic, &spr_write_generic,
3343 0xFFFFFFFF);
3344 /* not emulated, as QEMU do not emulate caches */
3345 spr_register(env, SPR_40x_DCWR, "DCWR",
3346 SPR_NOACCESS, SPR_NOACCESS,
3347 &spr_read_generic, &spr_write_generic,
3348 0x00000000);
3349 /* Memory management */
3350 #if !defined(CONFIG_USER_ONLY)
3351 env->nb_tlb = 64;
3352 env->nb_ways = 1;
3353 env->id_tlbs = 0;
3354 env->tlb_type = TLB_EMB;
3355 #endif
3356 init_excp_4xx_softmmu(env);
3357 env->dcache_line_size = 32;
3358 env->icache_line_size = 32;
3359 /* Allocate hardware IRQ controller */
3360 ppc40x_irq_init(env);
3361
3362 SET_FIT_PERIOD(8, 12, 16, 20);
3363 SET_WDT_PERIOD(16, 20, 24, 28);
3364 }
3365
3366 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3367 {
3368 DeviceClass *dc = DEVICE_CLASS(oc);
3369 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3370
3371 dc->desc = "PowerPC 403 GCX";
3372 pcc->init_proc = init_proc_403GCX;
3373 pcc->check_pow = check_pow_nocheck;
3374 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3375 PPC_DCR | PPC_WRTEE |
3376 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3377 PPC_CACHE_DCBZ |
3378 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3379 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3380 PPC_4xx_COMMON | PPC_40x_EXCP;
3381 pcc->insns_flags2 = PPC_NONE;
3382 pcc->msr_mask = 0x000000000007D00DULL;
3383 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3384 pcc->excp_model = POWERPC_EXCP_40x;
3385 pcc->bus_model = PPC_FLAGS_INPUT_401;
3386 pcc->bfd_mach = bfd_mach_ppc_403;
3387 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3388 POWERPC_FLAG_BUS_CLK;
3389 }
3390
3391 static void init_proc_405 (CPUPPCState *env)
3392 {
3393 /* Time base */
3394 gen_tbl(env);
3395 gen_spr_40x(env);
3396 gen_spr_405(env);
3397 /* Bus access control */
3398 /* not emulated, as QEMU never does speculative access */
3399 spr_register(env, SPR_40x_SGR, "SGR",
3400 SPR_NOACCESS, SPR_NOACCESS,
3401 &spr_read_generic, &spr_write_generic,
3402 0xFFFFFFFF);
3403 /* not emulated, as QEMU do not emulate caches */
3404 spr_register(env, SPR_40x_DCWR, "DCWR",
3405 SPR_NOACCESS, SPR_NOACCESS,
3406 &spr_read_generic, &spr_write_generic,
3407 0x00000000);
3408 /* Memory management */
3409 #if !defined(CONFIG_USER_ONLY)
3410 env->nb_tlb = 64;
3411 env->nb_ways = 1;
3412 env->id_tlbs = 0;
3413 env->tlb_type = TLB_EMB;
3414 #endif
3415 init_excp_4xx_softmmu(env);
3416 env->dcache_line_size = 32;
3417 env->icache_line_size = 32;
3418 /* Allocate hardware IRQ controller */
3419 ppc40x_irq_init(env);
3420
3421 SET_FIT_PERIOD(8, 12, 16, 20);
3422 SET_WDT_PERIOD(16, 20, 24, 28);
3423 }
3424
3425 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3426 {
3427 DeviceClass *dc = DEVICE_CLASS(oc);
3428 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3429
3430 dc->desc = "PowerPC 405";
3431 pcc->init_proc = init_proc_405;
3432 pcc->check_pow = check_pow_nocheck;
3433 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3434 PPC_DCR | PPC_WRTEE |
3435 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3436 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3437 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3438 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3439 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3440 pcc->insns_flags2 = PPC_NONE;
3441 pcc->msr_mask = 0x000000000006E630ULL;
3442 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3443 pcc->excp_model = POWERPC_EXCP_40x;
3444 pcc->bus_model = PPC_FLAGS_INPUT_405;
3445 pcc->bfd_mach = bfd_mach_ppc_403;
3446 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3447 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3448 }
3449
3450 static void init_proc_440EP (CPUPPCState *env)
3451 {
3452 /* Time base */
3453 gen_tbl(env);
3454 gen_spr_BookE(env, 0x000000000000FFFFULL);
3455 gen_spr_440(env);
3456 gen_spr_usprgh(env);
3457 /* Processor identification */
3458 spr_register(env, SPR_BOOKE_PIR, "PIR",
3459 SPR_NOACCESS, SPR_NOACCESS,
3460 &spr_read_generic, &spr_write_pir,
3461 0x00000000);
3462 /* XXX : not implemented */
3463 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3464 SPR_NOACCESS, SPR_NOACCESS,
3465 &spr_read_generic, &spr_write_generic,
3466 0x00000000);
3467 /* XXX : not implemented */
3468 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3469 SPR_NOACCESS, SPR_NOACCESS,
3470 &spr_read_generic, &spr_write_generic,
3471 0x00000000);
3472 /* XXX : not implemented */
3473 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3474 SPR_NOACCESS, SPR_NOACCESS,
3475 &spr_read_generic, &spr_write_generic,
3476 0x00000000);
3477 /* XXX : not implemented */
3478 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3479 SPR_NOACCESS, SPR_NOACCESS,
3480 &spr_read_generic, &spr_write_generic,
3481 0x00000000);
3482 /* XXX : not implemented */
3483 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3484 SPR_NOACCESS, SPR_NOACCESS,
3485 &spr_read_generic, &spr_write_generic,
3486 0x00000000);
3487 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3488 SPR_NOACCESS, SPR_NOACCESS,
3489 &spr_read_generic, &spr_write_generic,
3490 0x00000000);
3491 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3492 SPR_NOACCESS, SPR_NOACCESS,
3493 &spr_read_generic, &spr_write_generic,
3494 0x00000000);
3495 /* XXX : not implemented */
3496 spr_register(env, SPR_440_CCR1, "CCR1",
3497 SPR_NOACCESS, SPR_NOACCESS,
3498 &spr_read_generic, &spr_write_generic,
3499 0x00000000);
3500 /* Memory management */
3501 #if !defined(CONFIG_USER_ONLY)
3502 env->nb_tlb = 64;
3503 env->nb_ways = 1;
3504 env->id_tlbs = 0;
3505 env->tlb_type = TLB_EMB;
3506 #endif
3507 init_excp_BookE(env);
3508 env->dcache_line_size = 32;
3509 env->icache_line_size = 32;
3510 ppc40x_irq_init(env);
3511
3512 SET_FIT_PERIOD(12, 16, 20, 24);
3513 SET_WDT_PERIOD(20, 24, 28, 32);
3514 }
3515
3516 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3517 {
3518 DeviceClass *dc = DEVICE_CLASS(oc);
3519 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3520
3521 dc->desc = "PowerPC 440 EP";
3522 pcc->init_proc = init_proc_440EP;
3523 pcc->check_pow = check_pow_nocheck;
3524 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3525 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3526 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3527 PPC_FLOAT_STFIWX |
3528 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3529 PPC_CACHE | PPC_CACHE_ICBI |
3530 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3531 PPC_MEM_TLBSYNC | PPC_MFTB |
3532 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3533 PPC_440_SPEC;
3534 pcc->insns_flags2 = PPC_NONE;
3535 pcc->msr_mask = 0x000000000006FF30ULL;
3536 pcc->mmu_model = POWERPC_MMU_BOOKE;
3537 pcc->excp_model = POWERPC_EXCP_BOOKE;
3538 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3539 pcc->bfd_mach = bfd_mach_ppc_403;
3540 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3541 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3542 }
3543
3544 static void init_proc_440GP (CPUPPCState *env)
3545 {
3546 /* Time base */
3547 gen_tbl(env);
3548 gen_spr_BookE(env, 0x000000000000FFFFULL);
3549 gen_spr_440(env);
3550 gen_spr_usprgh(env);
3551 /* Processor identification */
3552 spr_register(env, SPR_BOOKE_PIR, "PIR",
3553 SPR_NOACCESS, SPR_NOACCESS,
3554 &spr_read_generic, &spr_write_pir,
3555 0x00000000);
3556 /* XXX : not implemented */
3557 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3558 SPR_NOACCESS, SPR_NOACCESS,
3559 &spr_read_generic, &spr_write_generic,
3560 0x00000000);
3561 /* XXX : not implemented */
3562 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3563 SPR_NOACCESS, SPR_NOACCESS,
3564 &spr_read_generic, &spr_write_generic,
3565 0x00000000);
3566 /* XXX : not implemented */
3567 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3568 SPR_NOACCESS, SPR_NOACCESS,
3569 &spr_read_generic, &spr_write_generic,
3570 0x00000000);
3571 /* XXX : not implemented */
3572 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3573 SPR_NOACCESS, SPR_NOACCESS,
3574 &spr_read_generic, &spr_write_generic,
3575 0x00000000);
3576 /* Memory management */
3577 #if !defined(CONFIG_USER_ONLY)
3578 env->nb_tlb = 64;
3579 env->nb_ways = 1;
3580 env->id_tlbs = 0;
3581 env->tlb_type = TLB_EMB;
3582 #endif
3583 init_excp_BookE(env);
3584 env->dcache_line_size = 32;
3585 env->icache_line_size = 32;
3586 /* XXX: TODO: allocate internal IRQ controller */
3587
3588 SET_FIT_PERIOD(12, 16, 20, 24);
3589 SET_WDT_PERIOD(20, 24, 28, 32);
3590 }
3591
3592 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3593 {
3594 DeviceClass *dc = DEVICE_CLASS(oc);
3595 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3596
3597 dc->desc = "PowerPC 440 GP";
3598 pcc->init_proc = init_proc_440GP;
3599 pcc->check_pow = check_pow_nocheck;
3600 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3601 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3602 PPC_CACHE | PPC_CACHE_ICBI |
3603 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3604 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3605 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3606 PPC_440_SPEC;
3607 pcc->insns_flags2 = PPC_NONE;
3608 pcc->msr_mask = 0x000000000006FF30ULL;
3609 pcc->mmu_model = POWERPC_MMU_BOOKE;
3610 pcc->excp_model = POWERPC_EXCP_BOOKE;
3611 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3612 pcc->bfd_mach = bfd_mach_ppc_403;
3613 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3614 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3615 }
3616
3617 static void init_proc_440x4 (CPUPPCState *env)
3618 {
3619 /* Time base */
3620 gen_tbl(env);
3621 gen_spr_BookE(env, 0x000000000000FFFFULL);
3622 gen_spr_440(env);
3623 gen_spr_usprgh(env);
3624 /* Processor identification */
3625 spr_register(env, SPR_BOOKE_PIR, "PIR",
3626 SPR_NOACCESS, SPR_NOACCESS,
3627 &spr_read_generic, &spr_write_pir,
3628 0x00000000);
3629 /* XXX : not implemented */
3630 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3631 SPR_NOACCESS, SPR_NOACCESS,
3632 &spr_read_generic, &spr_write_generic,
3633 0x00000000);
3634 /* XXX : not implemented */
3635 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3636 SPR_NOACCESS, SPR_NOACCESS,
3637 &spr_read_generic, &spr_write_generic,
3638 0x00000000);
3639 /* XXX : not implemented */
3640 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3641 SPR_NOACCESS, SPR_NOACCESS,
3642 &spr_read_generic, &spr_write_generic,
3643 0x00000000);
3644 /* XXX : not implemented */
3645 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3646 SPR_NOACCESS, SPR_NOACCESS,
3647 &spr_read_generic, &spr_write_generic,
3648 0x00000000);
3649 /* Memory management */
3650 #if !defined(CONFIG_USER_ONLY)
3651 env->nb_tlb = 64;
3652 env->nb_ways = 1;
3653 env->id_tlbs = 0;
3654 env->tlb_type = TLB_EMB;
3655 #endif
3656 init_excp_BookE(env);
3657 env->dcache_line_size = 32;
3658 env->icache_line_size = 32;
3659 /* XXX: TODO: allocate internal IRQ controller */
3660
3661 SET_FIT_PERIOD(12, 16, 20, 24);
3662 SET_WDT_PERIOD(20, 24, 28, 32);
3663 }
3664
3665 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3666 {
3667 DeviceClass *dc = DEVICE_CLASS(oc);
3668 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3669
3670 dc->desc = "PowerPC 440x4";
3671 pcc->init_proc = init_proc_440x4;
3672 pcc->check_pow = check_pow_nocheck;
3673 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3674 PPC_DCR | PPC_WRTEE |
3675 PPC_CACHE | PPC_CACHE_ICBI |
3676 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3677 PPC_MEM_TLBSYNC | PPC_MFTB |
3678 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3679 PPC_440_SPEC;
3680 pcc->insns_flags2 = PPC_NONE;
3681 pcc->msr_mask = 0x000000000006FF30ULL;
3682 pcc->mmu_model = POWERPC_MMU_BOOKE;
3683 pcc->excp_model = POWERPC_EXCP_BOOKE;
3684 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3685 pcc->bfd_mach = bfd_mach_ppc_403;
3686 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3687 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3688 }
3689
3690 static void init_proc_440x5 (CPUPPCState *env)
3691 {
3692 /* Time base */
3693 gen_tbl(env);
3694 gen_spr_BookE(env, 0x000000000000FFFFULL);
3695 gen_spr_440(env);
3696 gen_spr_usprgh(env);
3697 /* Processor identification */
3698 spr_register(env, SPR_BOOKE_PIR, "PIR",
3699 SPR_NOACCESS, SPR_NOACCESS,
3700 &spr_read_generic, &spr_write_pir,
3701 0x00000000);
3702 /* XXX : not implemented */
3703 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3704 SPR_NOACCESS, SPR_NOACCESS,
3705 &spr_read_generic, &spr_write_generic,
3706 0x00000000);
3707 /* XXX : not implemented */
3708 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3709 SPR_NOACCESS, SPR_NOACCESS,
3710 &spr_read_generic, &spr_write_generic,
3711 0x00000000);
3712 /* XXX : not implemented */
3713 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3714 SPR_NOACCESS, SPR_NOACCESS,
3715 &spr_read_generic, &spr_write_generic,
3716 0x00000000);
3717 /* XXX : not implemented */
3718 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3719 SPR_NOACCESS, SPR_NOACCESS,
3720 &spr_read_generic, &spr_write_generic,
3721 0x00000000);
3722 /* XXX : not implemented */
3723 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3724 SPR_NOACCESS, SPR_NOACCESS,
3725 &spr_read_generic, &spr_write_generic,
3726 0x00000000);
3727 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3728 SPR_NOACCESS, SPR_NOACCESS,
3729 &spr_read_generic, &spr_write_generic,
3730 0x00000000);
3731 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3732 SPR_NOACCESS, SPR_NOACCESS,
3733 &spr_read_generic, &spr_write_generic,
3734 0x00000000);
3735 /* XXX : not implemented */
3736 spr_register(env, SPR_440_CCR1, "CCR1",
3737 SPR_NOACCESS, SPR_NOACCESS,
3738 &spr_read_generic, &spr_write_generic,
3739 0x00000000);
3740 /* Memory management */
3741 #if !defined(CONFIG_USER_ONLY)
3742 env->nb_tlb = 64;
3743 env->nb_ways = 1;
3744 env->id_tlbs = 0;
3745 env->tlb_type = TLB_EMB;
3746 #endif
3747 init_excp_BookE(env);
3748 env->dcache_line_size = 32;
3749 env->icache_line_size = 32;
3750 ppc40x_irq_init(env);
3751
3752 SET_FIT_PERIOD(12, 16, 20, 24);
3753 SET_WDT_PERIOD(20, 24, 28, 32);
3754 }
3755
3756 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3757 {
3758 DeviceClass *dc = DEVICE_CLASS(oc);
3759 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3760
3761 dc->desc = "PowerPC 440x5";
3762 pcc->init_proc = init_proc_440x5;
3763 pcc->check_pow = check_pow_nocheck;
3764 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3765 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3766 PPC_CACHE | PPC_CACHE_ICBI |
3767 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3768 PPC_MEM_TLBSYNC | PPC_MFTB |
3769 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3770 PPC_440_SPEC;
3771 pcc->insns_flags2 = PPC_NONE;
3772 pcc->msr_mask = 0x000000000006FF30ULL;
3773 pcc->mmu_model = POWERPC_MMU_BOOKE;
3774 pcc->excp_model = POWERPC_EXCP_BOOKE;
3775 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3776 pcc->bfd_mach = bfd_mach_ppc_403;
3777 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3778 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3779 }
3780
3781 static void init_proc_460 (CPUPPCState *env)
3782 {
3783 /* Time base */
3784 gen_tbl(env);
3785 gen_spr_BookE(env, 0x000000000000FFFFULL);
3786 gen_spr_440(env);
3787 gen_spr_usprgh(env);
3788 /* Processor identification */
3789 spr_register(env, SPR_BOOKE_PIR, "PIR",
3790 SPR_NOACCESS, SPR_NOACCESS,
3791 &spr_read_generic, &spr_write_pir,
3792 0x00000000);
3793 /* XXX : not implemented */
3794 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3795 SPR_NOACCESS, SPR_NOACCESS,
3796 &spr_read_generic, &spr_write_generic,
3797 0x00000000);
3798 /* XXX : not implemented */
3799 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3800 SPR_NOACCESS, SPR_NOACCESS,
3801 &spr_read_generic, &spr_write_generic,
3802 0x00000000);
3803 /* XXX : not implemented */
3804 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3805 SPR_NOACCESS, SPR_NOACCESS,
3806 &spr_read_generic, &spr_write_generic,
3807 0x00000000);
3808 /* XXX : not implemented */
3809 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3810 SPR_NOACCESS, SPR_NOACCESS,
3811 &spr_read_generic, &spr_write_generic,
3812 0x00000000);
3813 /* XXX : not implemented */
3814 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3815 SPR_NOACCESS, SPR_NOACCESS,
3816 &spr_read_generic, &spr_write_generic,
3817 0x00000000);
3818 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3819 SPR_NOACCESS, SPR_NOACCESS,
3820 &spr_read_generic, &spr_write_generic,
3821 0x00000000);
3822 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3823 SPR_NOACCESS, SPR_NOACCESS,
3824 &spr_read_generic, &spr_write_generic,
3825 0x00000000);
3826 /* XXX : not implemented */
3827 spr_register(env, SPR_440_CCR1, "CCR1",
3828 SPR_NOACCESS, SPR_NOACCESS,
3829 &spr_read_generic, &spr_write_generic,
3830 0x00000000);
3831 /* XXX : not implemented */
3832 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3833 &spr_read_generic, &spr_write_generic,
3834 &spr_read_generic, &spr_write_generic,
3835 0x00000000);
3836 /* Memory management */
3837 #if !defined(CONFIG_USER_ONLY)
3838 env->nb_tlb = 64;
3839 env->nb_ways = 1;
3840 env->id_tlbs = 0;
3841 env->tlb_type = TLB_EMB;
3842 #endif
3843 init_excp_BookE(env);
3844 env->dcache_line_size = 32;
3845 env->icache_line_size = 32;
3846 /* XXX: TODO: allocate internal IRQ controller */
3847
3848 SET_FIT_PERIOD(12, 16, 20, 24);
3849 SET_WDT_PERIOD(20, 24, 28, 32);
3850 }
3851
3852 POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
3853 {
3854 DeviceClass *dc = DEVICE_CLASS(oc);
3855 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3856
3857 dc->desc = "PowerPC 460 (guessed)";
3858 pcc->init_proc = init_proc_460;
3859 pcc->check_pow = check_pow_nocheck;
3860 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3861 PPC_DCR | PPC_DCRX | PPC_DCRUX |
3862 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
3863 PPC_CACHE | PPC_CACHE_ICBI |
3864 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3865 PPC_MEM_TLBSYNC | PPC_TLBIVA |
3866 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3867 PPC_440_SPEC;
3868 pcc->insns_flags2 = PPC_NONE;
3869 pcc->msr_mask = 0x000000000006FF30ULL;
3870 pcc->mmu_model = POWERPC_MMU_BOOKE;
3871 pcc->excp_model = POWERPC_EXCP_BOOKE;
3872 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3873 pcc->bfd_mach = bfd_mach_ppc_403;
3874 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3875 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3876 }
3877
3878 static void init_proc_460F (CPUPPCState *env)
3879 {
3880 /* Time base */
3881 gen_tbl(env);
3882 gen_spr_BookE(env, 0x000000000000FFFFULL);
3883 gen_spr_440(env);
3884 gen_spr_usprgh(env);
3885 /* Processor identification */
3886 spr_register(env, SPR_BOOKE_PIR, "PIR",
3887 SPR_NOACCESS, SPR_NOACCESS,
3888 &spr_read_generic, &spr_write_pir,
3889 0x00000000);
3890 /* XXX : not implemented */
3891 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3892 SPR_NOACCESS, SPR_NOACCESS,
3893 &spr_read_generic, &spr_write_generic,
3894 0x00000000);
3895 /* XXX : not implemented */
3896 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3897 SPR_NOACCESS, SPR_NOACCESS,
3898 &spr_read_generic, &spr_write_generic,
3899 0x00000000);
3900 /* XXX : not implemented */
3901 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3902 SPR_NOACCESS, SPR_NOACCESS,
3903 &spr_read_generic, &spr_write_generic,
3904 0x00000000);
3905 /* XXX : not implemented */
3906 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3907 SPR_NOACCESS, SPR_NOACCESS,
3908 &spr_read_generic, &spr_write_generic,
3909 0x00000000);
3910 /* XXX : not implemented */
3911 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3912 SPR_NOACCESS, SPR_NOACCESS,
3913 &spr_read_generic, &spr_write_generic,
3914 0x00000000);
3915 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3916 SPR_NOACCESS, SPR_NOACCESS,
3917 &spr_read_generic, &spr_write_generic,
3918 0x00000000);
3919 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3920 SPR_NOACCESS, SPR_NOACCESS,
3921 &spr_read_generic, &spr_write_generic,
3922 0x00000000);
3923 /* XXX : not implemented */
3924 spr_register(env, SPR_440_CCR1, "CCR1",
3925 SPR_NOACCESS, SPR_NOACCESS,
3926 &spr_read_generic, &spr_write_generic,
3927 0x00000000);
3928 /* XXX : not implemented */
3929 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3930 &spr_read_generic, &spr_write_generic,
3931 &spr_read_generic, &spr_write_generic,
3932 0x00000000);
3933 /* Memory management */
3934 #if !defined(CONFIG_USER_ONLY)
3935 env->nb_tlb = 64;
3936 env->nb_ways = 1;
3937 env->id_tlbs = 0;
3938 env->tlb_type = TLB_EMB;
3939 #endif
3940 init_excp_BookE(env);
3941 env->dcache_line_size = 32;
3942 env->icache_line_size = 32;
3943 /* XXX: TODO: allocate internal IRQ controller */
3944
3945 SET_FIT_PERIOD(12, 16, 20, 24);
3946 SET_WDT_PERIOD(20, 24, 28, 32);
3947 }
3948
3949 POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
3950 {
3951 DeviceClass *dc = DEVICE_CLASS(oc);
3952 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3953
3954 dc->desc = "PowerPC 460F (guessed)";
3955 pcc->init_proc = init_proc_460F;
3956 pcc->check_pow = check_pow_nocheck;
3957 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3958 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3959 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3960 PPC_FLOAT_STFIWX | PPC_MFTB |
3961 PPC_DCR | PPC_DCRX | PPC_DCRUX |
3962 PPC_WRTEE | PPC_MFAPIDI |
3963 PPC_CACHE | PPC_CACHE_ICBI |
3964 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3965 PPC_MEM_TLBSYNC | PPC_TLBIVA |
3966 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3967 PPC_440_SPEC;
3968 pcc->insns_flags2 = PPC_NONE;
3969 pcc->msr_mask = 0x000000000006FF30ULL;
3970 pcc->mmu_model = POWERPC_MMU_BOOKE;
3971 pcc->excp_model = POWERPC_EXCP_BOOKE;
3972 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3973 pcc->bfd_mach = bfd_mach_ppc_403;
3974 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3975 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3976 }
3977
3978 static void init_proc_MPC5xx (CPUPPCState *env)
3979 {
3980 /* Time base */
3981 gen_tbl(env);
3982 gen_spr_5xx_8xx(env);
3983 gen_spr_5xx(env);
3984 init_excp_MPC5xx(env);
3985 env->dcache_line_size = 32;
3986 env->icache_line_size = 32;
3987 /* XXX: TODO: allocate internal IRQ controller */
3988 }
3989
3990 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
3991 {
3992 DeviceClass *dc = DEVICE_CLASS(oc);
3993 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3994
3995 dc->desc = "Freescale 5xx cores (aka RCPU)";
3996 pcc->init_proc = init_proc_MPC5xx;
3997 pcc->check_pow = check_pow_none;
3998 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3999 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4000 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4001 PPC_MFTB;
4002 pcc->insns_flags2 = PPC_NONE;
4003 pcc->msr_mask = 0x000000000001FF43ULL;
4004 pcc->mmu_model = POWERPC_MMU_REAL;
4005 pcc->excp_model = POWERPC_EXCP_603;
4006 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4007 pcc->bfd_mach = bfd_mach_ppc_505;
4008 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4009 POWERPC_FLAG_BUS_CLK;
4010 }
4011
4012 static void init_proc_MPC8xx (CPUPPCState *env)
4013 {
4014 /* Time base */
4015 gen_tbl(env);
4016 gen_spr_5xx_8xx(env);
4017 gen_spr_8xx(env);
4018 init_excp_MPC8xx(env);
4019 env->dcache_line_size = 32;
4020 env->icache_line_size = 32;
4021 /* XXX: TODO: allocate internal IRQ controller */
4022 }
4023
4024 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4025 {
4026 DeviceClass *dc = DEVICE_CLASS(oc);
4027 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4028
4029 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4030 pcc->init_proc = init_proc_MPC8xx;
4031 pcc->check_pow = check_pow_none;
4032 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4033 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4034 PPC_CACHE_ICBI | PPC_MFTB;
4035 pcc->insns_flags2 = PPC_NONE;
4036 pcc->msr_mask = 0x000000000001F673ULL;
4037 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4038 pcc->excp_model = POWERPC_EXCP_603;
4039 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4040 pcc->bfd_mach = bfd_mach_ppc_860;
4041 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4042 POWERPC_FLAG_BUS_CLK;
4043 }
4044
4045 /* Freescale 82xx cores (aka PowerQUICC-II) */
4046
4047 static void init_proc_G2 (CPUPPCState *env)
4048 {
4049 gen_spr_ne_601(env);
4050 gen_spr_G2_755(env);
4051 gen_spr_G2(env);
4052 /* Time base */
4053 gen_tbl(env);
4054 /* External access control */
4055 /* XXX : not implemented */
4056 spr_register(env, SPR_EAR, "EAR",
4057 SPR_NOACCESS, SPR_NOACCESS,
4058 &spr_read_generic, &spr_write_generic,
4059 0x00000000);
4060 /* Hardware implementation register */
4061 /* XXX : not implemented */
4062 spr_register(env, SPR_HID0, "HID0",
4063 SPR_NOACCESS, SPR_NOACCESS,
4064 &spr_read_generic, &spr_write_generic,
4065 0x00000000);
4066 /* XXX : not implemented */
4067 spr_register(env, SPR_HID1, "HID1",
4068 SPR_NOACCESS, SPR_NOACCESS,
4069 &spr_read_generic, &spr_write_generic,
4070 0x00000000);
4071 /* XXX : not implemented */
4072 spr_register(env, SPR_HID2, "HID2",
4073 SPR_NOACCESS, SPR_NOACCESS,
4074 &spr_read_generic, &spr_write_generic,
4075 0x00000000);
4076 /* Memory management */
4077 gen_low_BATs(env);
4078 gen_high_BATs(env);
4079 gen_6xx_7xx_soft_tlb(env, 64, 2);
4080 init_excp_G2(env);
4081 env->dcache_line_size = 32;
4082 env->icache_line_size = 32;
4083 /* Allocate hardware IRQ controller */
4084 ppc6xx_irq_init(env);
4085 }
4086
4087 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4088 {
4089 DeviceClass *dc = DEVICE_CLASS(oc);
4090 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4091
4092 dc->desc = "PowerPC G2";
4093 pcc->init_proc = init_proc_G2;
4094 pcc->check_pow = check_pow_hid0;
4095 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4096 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4097 PPC_FLOAT_STFIWX |
4098 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4099 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4100 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4101 PPC_SEGMENT | PPC_EXTERN;
4102 pcc->insns_flags2 = PPC_NONE;
4103 pcc->msr_mask = 0x000000000006FFF2ULL;
4104 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4105 pcc->excp_model = POWERPC_EXCP_G2;
4106 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4107 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4108 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4109 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4110 }
4111
4112 static void init_proc_G2LE (CPUPPCState *env)
4113 {
4114 gen_spr_ne_601(env);
4115 gen_spr_G2_755(env);
4116 gen_spr_G2(env);
4117 /* Time base */
4118 gen_tbl(env);
4119 /* External access control */
4120 /* XXX : not implemented */
4121 spr_register(env, SPR_EAR, "EAR",
4122 SPR_NOACCESS, SPR_NOACCESS,
4123 &spr_read_generic, &spr_write_generic,
4124 0x00000000);
4125 /* Hardware implementation register */
4126 /* XXX : not implemented */
4127 spr_register(env, SPR_HID0, "HID0",
4128 SPR_NOACCESS, SPR_NOACCESS,
4129 &spr_read_generic, &spr_write_generic,
4130 0x00000000);
4131 /* XXX : not implemented */
4132 spr_register(env, SPR_HID1, "HID1",
4133 SPR_NOACCESS, SPR_NOACCESS,
4134 &spr_read_generic, &spr_write_generic,
4135 0x00000000);
4136 /* XXX : not implemented */
4137 spr_register(env, SPR_HID2, "HID2",
4138 SPR_NOACCESS, SPR_NOACCESS,
4139 &spr_read_generic, &spr_write_generic,
4140 0x00000000);
4141 /* Memory management */
4142 gen_low_BATs(env);
4143 gen_high_BATs(env);
4144 gen_6xx_7xx_soft_tlb(env, 64, 2);
4145 init_excp_G2(env);
4146 env->dcache_line_size = 32;
4147 env->icache_line_size = 32;
4148 /* Allocate hardware IRQ controller */
4149 ppc6xx_irq_init(env);
4150 }
4151
4152 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4153 {
4154 DeviceClass *dc = DEVICE_CLASS(oc);
4155 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4156
4157 dc->desc = "PowerPC G2LE";
4158 pcc->init_proc = init_proc_G2LE;
4159 pcc->check_pow = check_pow_hid0;
4160 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4161 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4162 PPC_FLOAT_STFIWX |
4163 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4164 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4165 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4166 PPC_SEGMENT | PPC_EXTERN;
4167 pcc->insns_flags2 = PPC_NONE;
4168 pcc->msr_mask = 0x000000000007FFF3ULL;
4169 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4170 pcc->excp_model = POWERPC_EXCP_G2;
4171 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4172 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4173 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4174 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4175 }
4176
4177 static void init_proc_e200 (CPUPPCState *env)
4178 {
4179 /* Time base */
4180 gen_tbl(env);
4181 gen_spr_BookE(env, 0x000000070000FFFFULL);
4182 /* XXX : not implemented */
4183 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4184 &spr_read_spefscr, &spr_write_spefscr,
4185 &spr_read_spefscr, &spr_write_spefscr,
4186 0x00000000);
4187 /* Memory management */
4188 gen_spr_BookE206(env, 0x0000005D, NULL);
4189 /* XXX : not implemented */
4190 spr_register(env, SPR_HID0, "HID0",
4191 SPR_NOACCESS, SPR_NOACCESS,
4192 &spr_read_generic, &spr_write_generic,
4193 0x00000000);
4194 /* XXX : not implemented */
4195 spr_register(env, SPR_HID1, "HID1",
4196 SPR_NOACCESS, SPR_NOACCESS,
4197 &spr_read_generic, &spr_write_generic,
4198 0x00000000);
4199 /* XXX : not implemented */
4200 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4201 SPR_NOACCESS, SPR_NOACCESS,
4202 &spr_read_generic, &spr_write_generic,
4203 0x00000000);
4204 /* XXX : not implemented */
4205 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4206 SPR_NOACCESS, SPR_NOACCESS,
4207 &spr_read_generic, &spr_write_generic,
4208 0x00000000);
4209 /* XXX : not implemented */
4210 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4211 SPR_NOACCESS, SPR_NOACCESS,
4212 &spr_read_generic, &spr_write_generic,
4213 0x00000000);
4214 /* XXX : not implemented */
4215 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4216 SPR_NOACCESS, SPR_NOACCESS,
4217 &spr_read_generic, &spr_write_generic,
4218 0x00000000);
4219 /* XXX : not implemented */
4220 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4221 SPR_NOACCESS, SPR_NOACCESS,
4222 &spr_read_generic, &spr_write_generic,
4223 0x00000000);
4224 /* XXX : not implemented */
4225 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4226 SPR_NOACCESS, SPR_NOACCESS,
4227 &spr_read_generic, &spr_write_generic,
4228 0x00000000);
4229 /* XXX : not implemented */
4230 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4231 SPR_NOACCESS, SPR_NOACCESS,
4232 &spr_read_generic, &spr_write_generic,
4233 0x00000000);
4234 /* XXX : not implemented */
4235 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4236 SPR_NOACCESS, SPR_NOACCESS,
4237 &spr_read_generic, &spr_write_generic,
4238 0x00000000);
4239 /* XXX : not implemented */
4240 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4241 SPR_NOACCESS, SPR_NOACCESS,
4242 &spr_read_generic, &spr_write_generic,
4243 0x00000000);
4244 /* XXX : not implemented */
4245 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4246 SPR_NOACCESS, SPR_NOACCESS,
4247 &spr_read_generic, &spr_write_generic,
4248 0x00000000);
4249 /* XXX : not implemented */
4250 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4251 SPR_NOACCESS, SPR_NOACCESS,
4252 &spr_read_generic, &spr_write_generic,
4253 0x00000000);
4254 /* XXX : not implemented */
4255 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4256 SPR_NOACCESS, SPR_NOACCESS,
4257 &spr_read_generic, &spr_write_generic,
4258 0x00000000);
4259 /* XXX : not implemented */
4260 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4261 SPR_NOACCESS, SPR_NOACCESS,
4262 &spr_read_generic, &spr_write_generic,
4263 0x00000000); /* TOFIX */
4264 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4265 SPR_NOACCESS, SPR_NOACCESS,
4266 &spr_read_generic, &spr_write_generic,
4267 0x00000000);
4268 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4269 SPR_NOACCESS, SPR_NOACCESS,
4270 &spr_read_generic, &spr_write_generic,
4271 0x00000000);
4272 #if !defined(CONFIG_USER_ONLY)
4273 env->nb_tlb = 64;
4274 env->nb_ways = 1;
4275 env->id_tlbs = 0;
4276 env->tlb_type = TLB_EMB;
4277 #endif
4278 init_excp_e200(env, 0xFFFF0000UL);
4279 env->dcache_line_size = 32;
4280 env->icache_line_size = 32;
4281 /* XXX: TODO: allocate internal IRQ controller */
4282 }
4283
4284 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4285 {
4286 DeviceClass *dc = DEVICE_CLASS(oc);
4287 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4288
4289 dc->desc = "e200 core";
4290 pcc->init_proc = init_proc_e200;
4291 pcc->check_pow = check_pow_hid0;
4292 /* XXX: unimplemented instructions:
4293 * dcblc
4294 * dcbtlst
4295 * dcbtstls
4296 * icblc
4297 * icbtls
4298 * tlbivax
4299 * all SPE multiply-accumulate instructions
4300 */
4301 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4302 PPC_SPE | PPC_SPE_SINGLE |
4303 PPC_WRTEE | PPC_RFDI |
4304 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4305 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4306 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4307 PPC_BOOKE;
4308 pcc->insns_flags2 = PPC_NONE;
4309 pcc->msr_mask = 0x000000000606FF30ULL;
4310 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4311 pcc->excp_model = POWERPC_EXCP_BOOKE;
4312 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4313 pcc->bfd_mach = bfd_mach_ppc_860;
4314 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4315 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4316 POWERPC_FLAG_BUS_CLK;
4317 }
4318
4319 static void init_proc_e300 (CPUPPCState *env)
4320 {
4321 gen_spr_ne_601(env);
4322 gen_spr_603(env);
4323 /* Time base */
4324 gen_tbl(env);
4325 /* hardware implementation registers */
4326 /* XXX : not implemented */
4327 spr_register(env, SPR_HID0, "HID0",
4328 SPR_NOACCESS, SPR_NOACCESS,
4329 &spr_read_generic, &spr_write_generic,
4330 0x00000000);
4331 /* XXX : not implemented */
4332 spr_register(env, SPR_HID1, "HID1",
4333 SPR_NOACCESS, SPR_NOACCESS,
4334 &spr_read_generic, &spr_write_generic,
4335 0x00000000);
4336 /* XXX : not implemented */
4337 spr_register(env, SPR_HID2, "HID2",
4338 SPR_NOACCESS, SPR_NOACCESS,
4339 &spr_read_generic, &spr_write_generic,
4340 0x00000000);
4341 /* Memory management */
4342 gen_low_BATs(env);
4343 gen_high_BATs(env);
4344 gen_6xx_7xx_soft_tlb(env, 64, 2);
4345 init_excp_603(env);
4346 env->dcache_line_size = 32;
4347 env->icache_line_size = 32;
4348 /* Allocate hardware IRQ controller */
4349 ppc6xx_irq_init(env);
4350 }
4351
4352 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4353 {
4354 DeviceClass *dc = DEVICE_CLASS(oc);
4355 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4356
4357 dc->desc = "e300 core";
4358 pcc->init_proc = init_proc_e300;
4359 pcc->check_pow = check_pow_hid0;
4360 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4361 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4362 PPC_FLOAT_STFIWX |
4363 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4364 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4365 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4366 PPC_SEGMENT | PPC_EXTERN;
4367 pcc->insns_flags2 = PPC_NONE;
4368 pcc->msr_mask = 0x000000000007FFF3ULL;
4369 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4370 pcc->excp_model = POWERPC_EXCP_603;
4371 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4372 pcc->bfd_mach = bfd_mach_ppc_603;
4373 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4374 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4375 }
4376
4377 #if !defined(CONFIG_USER_ONLY)
4378 static void spr_write_mas73(void *opaque, int sprn, int gprn)
4379 {
4380 TCGv val = tcg_temp_new();
4381 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4382 gen_store_spr(SPR_BOOKE_MAS3, val);
4383 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4384 gen_store_spr(SPR_BOOKE_MAS7, val);
4385 tcg_temp_free(val);
4386 }
4387
4388 static void spr_read_mas73(void *opaque, int gprn, int sprn)
4389 {
4390 TCGv mas7 = tcg_temp_new();
4391 TCGv mas3 = tcg_temp_new();
4392 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4393 tcg_gen_shli_tl(mas7, mas7, 32);
4394 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4395 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4396 tcg_temp_free(mas3);
4397 tcg_temp_free(mas7);
4398 }
4399
4400 #endif
4401
4402 enum fsl_e500_version {
4403 fsl_e500v1,
4404 fsl_e500v2,
4405 fsl_e500mc,
4406 fsl_e5500,
4407 };
4408
4409 static void init_proc_e500 (CPUPPCState *env, int version)
4410 {
4411 uint32_t tlbncfg[2];
4412 uint64_t ivor_mask;
4413 uint64_t ivpr_mask = 0xFFFF0000ULL;
4414 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4415 | 0x0020; /* 32 kb */
4416 #if !defined(CONFIG_USER_ONLY)
4417 int i;
4418 #endif
4419
4420 /* Time base */
4421 gen_tbl(env);
4422 /*
4423 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4424 * complain when accessing them.
4425 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4426 */
4427 switch (version) {
4428 case fsl_e500v1:
4429 case fsl_e500v2:
4430 default:
4431 ivor_mask = 0x0000000F0000FFFFULL;
4432 break;
4433 case fsl_e500mc:
4434 case fsl_e5500:
4435 ivor_mask = 0x000003FE0000FFFFULL;
4436 break;
4437 }
4438 gen_spr_BookE(env, ivor_mask);
4439 /* Processor identification */
4440 spr_register(env, SPR_BOOKE_PIR, "PIR",
4441 SPR_NOACCESS, SPR_NOACCESS,
4442 &spr_read_generic, &spr_write_pir,
4443 0x00000000);
4444 /* XXX : not implemented */
4445 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4446 &spr_read_spefscr, &spr_write_spefscr,
4447 &spr_read_spefscr, &spr_write_spefscr,
4448 0x00000000);
4449 #if !defined(CONFIG_USER_ONLY)
4450 /* Memory management */
4451 env->nb_pids = 3;
4452 env->nb_ways = 2;
4453 env->id_tlbs = 0;
4454 switch (version) {
4455 case fsl_e500v1:
4456 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4457 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4458 break;
4459 case fsl_e500v2:
4460 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4461 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4462 break;
4463 case fsl_e500mc:
4464 case fsl_e5500:
4465 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4466 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4467 break;
4468 default:
4469 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4470 }
4471 #endif
4472 /* Cache sizes */
4473 switch (version) {
4474 case fsl_e500v1:
4475 case fsl_e500v2:
4476 env->dcache_line_size = 32;
4477 env->icache_line_size = 32;
4478 break;
4479 case fsl_e500mc:
4480 case fsl_e5500:
4481 env->dcache_line_size = 64;
4482 env->icache_line_size = 64;
4483 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4484 break;
4485 default:
4486 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4487 }
4488 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4489 /* XXX : not implemented */
4490 spr_register(env, SPR_HID0, "HID0",
4491 SPR_NOACCESS, SPR_NOACCESS,
4492 &spr_read_generic, &spr_write_generic,
4493 0x00000000);
4494 /* XXX : not implemented */
4495 spr_register(env, SPR_HID1, "HID1",
4496 SPR_NOACCESS, SPR_NOACCESS,
4497 &spr_read_generic, &spr_write_generic,
4498 0x00000000);
4499 /* XXX : not implemented */
4500 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4501 SPR_NOACCESS, SPR_NOACCESS,
4502 &spr_read_generic, &spr_write_generic,
4503 0x00000000);
4504 /* XXX : not implemented */
4505 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4506 SPR_NOACCESS, SPR_NOACCESS,
4507 &spr_read_generic, &spr_write_generic,
4508 0x00000000);
4509 /* XXX : not implemented */
4510 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4511 SPR_NOACCESS, SPR_NOACCESS,
4512 &spr_read_generic, &spr_write_generic,
4513 0x00000000);
4514 /* XXX : not implemented */
4515 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4516 SPR_NOACCESS, SPR_NOACCESS,
4517 &spr_read_generic, &spr_write_generic,
4518 0x00000000);
4519 /* XXX : not implemented */
4520 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4521 SPR_NOACCESS, SPR_NOACCESS,
4522 &spr_read_generic, &spr_write_generic,
4523 0x00000000);
4524 /* XXX : not implemented */
4525 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4526 SPR_NOACCESS, SPR_NOACCESS,
4527 &spr_read_generic, &spr_write_generic,
4528 0x00000000);
4529 /* XXX : not implemented */
4530 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4531 SPR_NOACCESS, SPR_NOACCESS,
4532 &spr_read_generic, &spr_write_generic,
4533 l1cfg0);
4534 /* XXX : not implemented */
4535 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4536 SPR_NOACCESS, SPR_NOACCESS,
4537 &spr_read_generic, &spr_write_e500_l1csr0,
4538 0x00000000);
4539 /* XXX : not implemented */
4540 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4541 SPR_NOACCESS, SPR_NOACCESS,
4542 &spr_read_generic, &spr_write_generic,
4543 0x00000000);
4544 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4545 SPR_NOACCESS, SPR_NOACCESS,
4546 &spr_read_generic, &spr_write_generic,
4547 0x00000000);
4548 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4549 SPR_NOACCESS, SPR_NOACCESS,
4550 &spr_read_generic, &spr_write_generic,
4551 0x00000000);
4552 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4553 SPR_NOACCESS, SPR_NOACCESS,
4554 &spr_read_generic, &spr_write_booke206_mmucsr0,
4555 0x00000000);
4556 spr_register(env, SPR_BOOKE_EPR, "EPR",
4557 SPR_NOACCESS, SPR_NOACCESS,
4558 &spr_read_generic, SPR_NOACCESS,
4559 0x00000000);
4560 /* XXX better abstract into Emb.xxx features */
4561 if (version == fsl_e5500) {
4562 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4563 SPR_NOACCESS, SPR_NOACCESS,
4564 &spr_read_generic, &spr_write_generic,
4565 0x00000000);
4566 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4567 SPR_NOACCESS, SPR_NOACCESS,
4568 &spr_read_mas73, &spr_write_mas73,
4569 0x00000000);
4570 ivpr_mask = (target_ulong)~0xFFFFULL;
4571 }
4572
4573 #if !defined(CONFIG_USER_ONLY)
4574 env->nb_tlb = 0;
4575 env->tlb_type = TLB_MAS;
4576 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4577 env->nb_tlb += booke206_tlb_size(env, i);
4578 }
4579 #endif
4580
4581 init_excp_e200(env, ivpr_mask);
4582 /* Allocate hardware IRQ controller */
4583 ppce500_irq_init(env);
4584 }
4585
4586 static void init_proc_e500v1(CPUPPCState *env)
4587 {
4588 init_proc_e500(env, fsl_e500v1);
4589 }
4590
4591 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4592 {
4593 DeviceClass *dc = DEVICE_CLASS(oc);
4594 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4595
4596 dc->desc = "e500v1 core";
4597 pcc->init_proc = init_proc_e500v1;
4598 pcc->check_pow = check_pow_hid0;
4599 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4600 PPC_SPE | PPC_SPE_SINGLE |
4601 PPC_WRTEE | PPC_RFDI |
4602 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4603 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4604 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4605 pcc->insns_flags2 = PPC2_BOOKE206;
4606 pcc->msr_mask = 0x000000000606FF30ULL;
4607 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4608 pcc->excp_model = POWERPC_EXCP_BOOKE;
4609 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4610 pcc->bfd_mach = bfd_mach_ppc_860;
4611 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4612 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4613 POWERPC_FLAG_BUS_CLK;
4614 }
4615
4616 static void init_proc_e500v2(CPUPPCState *env)
4617 {
4618 init_proc_e500(env, fsl_e500v2);
4619 }
4620
4621 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4622 {
4623 DeviceClass *dc = DEVICE_CLASS(oc);
4624 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4625
4626 dc->desc = "e500v2 core";
4627 pcc->init_proc = init_proc_e500v2;
4628 pcc->check_pow = check_pow_hid0;
4629 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4630 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4631 PPC_WRTEE | PPC_RFDI |
4632 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4633 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4634 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4635 pcc->insns_flags2 = PPC2_BOOKE206;
4636 pcc->msr_mask = 0x000000000606FF30ULL;
4637 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4638 pcc->excp_model = POWERPC_EXCP_BOOKE;
4639 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4640 pcc->bfd_mach = bfd_mach_ppc_860;
4641 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4642 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4643 POWERPC_FLAG_BUS_CLK;
4644 }
4645
4646 static void init_proc_e500mc(CPUPPCState *env)
4647 {
4648 init_proc_e500(env, fsl_e500mc);
4649 }
4650
4651 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4652 {
4653 DeviceClass *dc = DEVICE_CLASS(oc);
4654 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4655
4656 dc->desc = "e500mc core";
4657 pcc->init_proc = init_proc_e500mc;
4658 pcc->check_pow = check_pow_none;
4659 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4660 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4661 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4662 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4663 PPC_FLOAT | PPC_FLOAT_FRES |
4664 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4665 PPC_FLOAT_STFIWX | PPC_WAIT |
4666 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4667 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4668 pcc->msr_mask = 0x000000001402FB36ULL;
4669 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4670 pcc->excp_model = POWERPC_EXCP_BOOKE;
4671 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4672 /* FIXME: figure out the correct flag for e500mc */
4673 pcc->bfd_mach = bfd_mach_ppc_e500;
4674 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4675 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4676 }
4677
4678 #ifdef TARGET_PPC64
4679 static void init_proc_e5500(CPUPPCState *env)
4680 {
4681 init_proc_e500(env, fsl_e5500);
4682 }
4683
4684 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
4685 {
4686 DeviceClass *dc = DEVICE_CLASS(oc);
4687 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4688
4689 dc->desc = "e5500 core";
4690 pcc->init_proc = init_proc_e5500;
4691 pcc->check_pow = check_pow_none;
4692 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4693 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4694 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4695 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4696 PPC_FLOAT | PPC_FLOAT_FRES |
4697 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4698 PPC_FLOAT_STFIWX | PPC_WAIT |
4699 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4700 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
4701 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4702 pcc->msr_mask = 0x000000009402FB36ULL;
4703 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4704 pcc->excp_model = POWERPC_EXCP_BOOKE;
4705 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4706 /* FIXME: figure out the correct flag for e5500 */
4707 pcc->bfd_mach = bfd_mach_ppc_e500;
4708 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4709 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4710 }
4711 #endif
4712
4713 /* Non-embedded PowerPC */
4714
4715 /* POWER : same as 601, without mfmsr, mfsr */
4716 POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
4717 {
4718 DeviceClass *dc = DEVICE_CLASS(oc);
4719 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4720
4721 dc->desc = "POWER";
4722 /* pcc->insns_flags = XXX_TODO; */
4723 /* POWER RSC (from RAD6000) */
4724 pcc->msr_mask = 0x00000000FEF0ULL;
4725 }
4726
4727 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4728
4729 static void init_proc_601 (CPUPPCState *env)
4730 {
4731 gen_spr_ne_601(env);
4732 gen_spr_601(env);
4733 /* Hardware implementation registers */
4734 /* XXX : not implemented */
4735 spr_register(env, SPR_HID0, "HID0",
4736 SPR_NOACCESS, SPR_NOACCESS,
4737 &spr_read_generic, &spr_write_hid0_601,
4738 0x80010080);
4739 /* XXX : not implemented */
4740 spr_register(env, SPR_HID1, "HID1",
4741 SPR_NOACCESS, SPR_NOACCESS,
4742 &spr_read_generic, &spr_write_generic,
4743 0x00000000);
4744 /* XXX : not implemented */
4745 spr_register(env, SPR_601_HID2, "HID2",
4746 SPR_NOACCESS, SPR_NOACCESS,
4747 &spr_read_generic, &spr_write_generic,
4748 0x00000000);
4749 /* XXX : not implemented */
4750 spr_register(env, SPR_601_HID5, "HID5",
4751 SPR_NOACCESS, SPR_NOACCESS,
4752 &spr_read_generic, &spr_write_generic,
4753 0x00000000);
4754 /* Memory management */
4755 init_excp_601(env);
4756 /* XXX: beware that dcache line size is 64
4757 * but dcbz uses 32 bytes "sectors"
4758 * XXX: this breaks clcs instruction !
4759 */
4760 env->dcache_line_size = 32;
4761 env->icache_line_size = 64;
4762 /* Allocate hardware IRQ controller */
4763 ppc6xx_irq_init(env);
4764 }
4765
4766 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
4767 {
4768 DeviceClass *dc = DEVICE_CLASS(oc);
4769 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4770
4771 dc->desc = "PowerPC 601";
4772 pcc->init_proc = init_proc_601;
4773 pcc->check_pow = check_pow_none;
4774 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4775 PPC_FLOAT |
4776 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4777 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4778 PPC_SEGMENT | PPC_EXTERN;
4779 pcc->insns_flags2 = PPC_NONE;
4780 pcc->msr_mask = 0x000000000000FD70ULL;
4781 pcc->mmu_model = POWERPC_MMU_601;
4782 #if defined(CONFIG_SOFTMMU)
4783 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
4784 #endif
4785 pcc->excp_model = POWERPC_EXCP_601;
4786 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4787 pcc->bfd_mach = bfd_mach_ppc_601;
4788 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
4789 }
4790
4791 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4792
4793 static void init_proc_601v (CPUPPCState *env)
4794 {
4795 init_proc_601(env);
4796 /* XXX : not implemented */
4797 spr_register(env, SPR_601_HID15, "HID15",
4798 SPR_NOACCESS, SPR_NOACCESS,
4799 &spr_read_generic, &spr_write_generic,
4800 0x00000000);
4801 }
4802
4803 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
4804 {
4805 DeviceClass *dc = DEVICE_CLASS(oc);
4806 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4807
4808 dc->desc = "PowerPC 601v";
4809 pcc->init_proc = init_proc_601v;
4810 pcc->check_pow = check_pow_none;
4811 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4812 PPC_FLOAT |
4813 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4814 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4815 PPC_SEGMENT | PPC_EXTERN;
4816 pcc->insns_flags2 = PPC_NONE;
4817 pcc->msr_mask = 0x000000000000FD70ULL;
4818 pcc->mmu_model = POWERPC_MMU_601;
4819 #if defined(CONFIG_SOFTMMU)
4820 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
4821 #endif
4822 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4823 pcc->bfd_mach = bfd_mach_ppc_601;
4824 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
4825 }
4826
4827 static void init_proc_602 (CPUPPCState *env)
4828 {
4829 gen_spr_ne_601(env);
4830 gen_spr_602(env);
4831 /* Time base */
4832 gen_tbl(env);
4833 /* hardware implementation registers */
4834 /* XXX : not implemented */
4835 spr_register(env, SPR_HID0, "HID0",
4836 SPR_NOACCESS, SPR_NOACCESS,
4837 &spr_read_generic, &spr_write_generic,
4838 0x00000000);
4839 /* XXX : not implemented */
4840 spr_register(env, SPR_HID1, "HID1",
4841 SPR_NOACCESS, SPR_NOACCESS,
4842 &spr_read_generic, &spr_write_generic,
4843 0x00000000);
4844 /* Memory management */
4845 gen_low_BATs(env);
4846 gen_6xx_7xx_soft_tlb(env, 64, 2);
4847 init_excp_602(env);
4848 env->dcache_line_size = 32;
4849 env->icache_line_size = 32;
4850 /* Allocate hardware IRQ controller */
4851 ppc6xx_irq_init(env);
4852 }
4853
4854 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
4855 {
4856 DeviceClass *dc = DEVICE_CLASS(oc);
4857 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4858
4859 dc->desc = "PowerPC 602";
4860 pcc->init_proc = init_proc_602;
4861 pcc->check_pow = check_pow_hid0;
4862 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4863 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4864 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4865 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4866 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4867 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
4868 PPC_SEGMENT | PPC_602_SPEC;
4869 pcc->insns_flags2 = PPC_NONE;
4870 pcc->msr_mask = 0x0000000000C7FF73ULL;
4871 /* XXX: 602 MMU is quite specific. Should add a special case */
4872 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4873 pcc->excp_model = POWERPC_EXCP_602;
4874 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4875 pcc->bfd_mach = bfd_mach_ppc_602;
4876 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4877 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4878 }
4879
4880 static void init_proc_603 (CPUPPCState *env)
4881 {
4882 gen_spr_ne_601(env);
4883 gen_spr_603(env);
4884 /* Time base */
4885 gen_tbl(env);
4886 /* hardware implementation registers */
4887 /* XXX : not implemented */
4888 spr_register(env, SPR_HID0, "HID0",
4889 SPR_NOACCESS, SPR_NOACCESS,
4890 &spr_read_generic, &spr_write_generic,
4891 0x00000000);
4892 /* XXX : not implemented */
4893 spr_register(env, SPR_HID1, "HID1",
4894 SPR_NOACCESS, SPR_NOACCESS,
4895 &spr_read_generic, &spr_write_generic,
4896 0x00000000);
4897 /* Memory management */
4898 gen_low_BATs(env);
4899 gen_6xx_7xx_soft_tlb(env, 64, 2);
4900 init_excp_603(env);
4901 env->dcache_line_size = 32;
4902 env->icache_line_size = 32;
4903 /* Allocate hardware IRQ controller */
4904 ppc6xx_irq_init(env);
4905 }
4906
4907 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
4908 {
4909 DeviceClass *dc = DEVICE_CLASS(oc);
4910 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4911
4912 dc->desc = "PowerPC 603";
4913 pcc->init_proc = init_proc_603;
4914 pcc->check_pow = check_pow_hid0;
4915 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4916 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4917 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4918 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4919 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4920 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4921 PPC_SEGMENT | PPC_EXTERN;
4922 pcc->insns_flags2 = PPC_NONE;
4923 pcc->msr_mask = 0x000000000007FF73ULL;
4924 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4925 pcc->excp_model = POWERPC_EXCP_603;
4926 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4927 pcc->bfd_mach = bfd_mach_ppc_603;
4928 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4929 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4930 }
4931
4932 static void init_proc_603E (CPUPPCState *env)
4933 {
4934 gen_spr_ne_601(env);
4935 gen_spr_603(env);
4936 /* Time base */
4937 gen_tbl(env);
4938 /* hardware implementation registers */
4939 /* XXX : not implemented */
4940 spr_register(env, SPR_HID0, "HID0",
4941 SPR_NOACCESS, SPR_NOACCESS,
4942 &spr_read_generic, &spr_write_generic,
4943 0x00000000);
4944 /* XXX : not implemented */
4945 spr_register(env, SPR_HID1, "HID1",
4946 SPR_NOACCESS, SPR_NOACCESS,
4947 &spr_read_generic, &spr_write_generic,
4948 0x00000000);
4949 /* XXX : not implemented */
4950 spr_register(env, SPR_IABR, "IABR",
4951 SPR_NOACCESS, SPR_NOACCESS,
4952 &spr_read_generic, &spr_write_generic,
4953 0x00000000);
4954 /* Memory management */
4955 gen_low_BATs(env);
4956 gen_6xx_7xx_soft_tlb(env, 64, 2);
4957 init_excp_603(env);
4958 env->dcache_line_size = 32;
4959 env->icache_line_size = 32;
4960 /* Allocate hardware IRQ controller */
4961 ppc6xx_irq_init(env);
4962 }
4963
4964 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
4965 {
4966 DeviceClass *dc = DEVICE_CLASS(oc);
4967 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4968
4969 dc->desc = "PowerPC 603e";
4970 pcc->init_proc = init_proc_603E;
4971 pcc->check_pow = check_pow_hid0;
4972 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4973 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4974 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4975 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4976 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4977 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4978 PPC_SEGMENT | PPC_EXTERN;
4979 pcc->insns_flags2 = PPC_NONE;
4980 pcc->msr_mask = 0x000000000007FF73ULL;
4981 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4982 pcc->excp_model = POWERPC_EXCP_603E;
4983 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4984 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4985 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4986 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4987 }
4988
4989 static void init_proc_604 (CPUPPCState *env)
4990 {
4991 gen_spr_ne_601(env);
4992 gen_spr_604(env);
4993 /* Time base */
4994 gen_tbl(env);
4995 /* Hardware implementation registers */
4996 /* XXX : not implemented */
4997 spr_register(env, SPR_HID0, "HID0",
4998 SPR_NOACCESS, SPR_NOACCESS,
4999 &spr_read_generic, &spr_write_generic,
5000 0x00000000);
5001 /* Memory management */
5002 gen_low_BATs(env);
5003 init_excp_604(env);
5004 env->dcache_line_size = 32;
5005 env->icache_line_size = 32;
5006 /* Allocate hardware IRQ controller */
5007 ppc6xx_irq_init(env);
5008 }
5009
5010 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5011 {
5012 DeviceClass *dc = DEVICE_CLASS(oc);
5013 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5014
5015 dc->desc = "PowerPC 604";
5016 pcc->init_proc = init_proc_604;
5017 pcc->check_pow = check_pow_nocheck;
5018 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5019 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5020 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5021 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5022 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5023 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5024 PPC_SEGMENT | PPC_EXTERN;
5025 pcc->insns_flags2 = PPC_NONE;
5026 pcc->msr_mask = 0x000000000005FF77ULL;
5027 pcc->mmu_model = POWERPC_MMU_32B;
5028 #if defined(CONFIG_SOFTMMU)
5029 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5030 #endif
5031 pcc->excp_model = POWERPC_EXCP_604;
5032 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5033 pcc->bfd_mach = bfd_mach_ppc_604;
5034 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5035 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5036 }
5037
5038 static void init_proc_604E (CPUPPCState *env)
5039 {
5040 gen_spr_ne_601(env);
5041 gen_spr_604(env);
5042 /* XXX : not implemented */
5043 spr_register(env, SPR_MMCR1, "MMCR1",
5044 SPR_NOACCESS, SPR_NOACCESS,
5045 &spr_read_generic, &spr_write_generic,
5046 0x00000000);
5047 /* XXX : not implemented */
5048 spr_register(env, SPR_PMC3, "PMC3",
5049 SPR_NOACCESS, SPR_NOACCESS,
5050 &spr_read_generic, &spr_write_generic,
5051 0x00000000);
5052 /* XXX : not implemented */
5053 spr_register(env, SPR_PMC4, "PMC4",
5054 SPR_NOACCESS, SPR_NOACCESS,
5055 &spr_read_generic, &spr_write_generic,
5056 0x00000000);
5057 /* Time base */
5058 gen_tbl(env);
5059 /* Hardware implementation registers */
5060 /* XXX : not implemented */
5061 spr_register(env, SPR_HID0, "HID0",
5062 SPR_NOACCESS, SPR_NOACCESS,
5063 &spr_read_generic, &spr_write_generic,
5064 0x00000000);
5065 /* XXX : not implemented */
5066 spr_register(env, SPR_HID1, "HID1",
5067 SPR_NOACCESS, SPR_NOACCESS,
5068 &spr_read_generic, &spr_write_generic,
5069 0x00000000);
5070 /* Memory management */
5071 gen_low_BATs(env);
5072 init_excp_604(env);
5073 env->dcache_line_size = 32;
5074 env->icache_line_size = 32;
5075 /* Allocate hardware IRQ controller */
5076 ppc6xx_irq_init(env);
5077 }
5078
5079 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5080 {
5081 DeviceClass *dc = DEVICE_CLASS(oc);
5082 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5083
5084 dc->desc = "PowerPC 604E";
5085 pcc->init_proc = init_proc_604E;
5086 pcc->check_pow = check_pow_nocheck;
5087 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5088 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5089 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5090 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5091 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5092 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5093 PPC_SEGMENT | PPC_EXTERN;
5094 pcc->insns_flags2 = PPC_NONE;
5095 pcc->msr_mask = 0x000000000005FF77ULL;
5096 pcc->mmu_model = POWERPC_MMU_32B;
5097 #if defined(CONFIG_SOFTMMU)
5098 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5099 #endif
5100 pcc->excp_model = POWERPC_EXCP_604;
5101 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5102 pcc->bfd_mach = bfd_mach_ppc_604;
5103 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5104 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5105 }
5106
5107 static void init_proc_740 (CPUPPCState *env)
5108 {
5109 gen_spr_ne_601(env);
5110 gen_spr_7xx(env);
5111 /* Time base */
5112 gen_tbl(env);
5113 /* Thermal management */
5114 gen_spr_thrm(env);
5115 /* Hardware implementation registers */
5116 /* XXX : not implemented */
5117 spr_register(env, SPR_HID0, "HID0",
5118 SPR_NOACCESS, SPR_NOACCESS,
5119 &spr_read_generic, &spr_write_generic,
5120 0x00000000);
5121 /* XXX : not implemented */
5122 spr_register(env, SPR_HID1, "HID1",
5123 SPR_NOACCESS, SPR_NOACCESS,
5124 &spr_read_generic, &spr_write_generic,
5125 0x00000000);
5126 /* Memory management */
5127 gen_low_BATs(env);
5128 init_excp_7x0(env);
5129 env->dcache_line_size = 32;
5130 env->icache_line_size = 32;
5131 /* Allocate hardware IRQ controller */
5132 ppc6xx_irq_init(env);
5133 }
5134
5135 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5136 {
5137 DeviceClass *dc = DEVICE_CLASS(oc);
5138 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5139
5140 dc->desc = "PowerPC 740";
5141 pcc->init_proc = init_proc_740;
5142 pcc->check_pow = check_pow_hid0;
5143 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5144 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5145 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5146 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5147 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5148 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5149 PPC_SEGMENT | PPC_EXTERN;
5150 pcc->insns_flags2 = PPC_NONE;
5151 pcc->msr_mask = 0x000000000005FF77ULL;
5152 pcc->mmu_model = POWERPC_MMU_32B;
5153 #if defined(CONFIG_SOFTMMU)
5154 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5155 #endif
5156 pcc->excp_model = POWERPC_EXCP_7x0;
5157 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5158 pcc->bfd_mach = bfd_mach_ppc_750;
5159 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5160 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5161 }
5162
5163 static void init_proc_750 (CPUPPCState *env)
5164 {
5165 gen_spr_ne_601(env);
5166 gen_spr_7xx(env);
5167 /* XXX : not implemented */
5168 spr_register(env, SPR_L2CR, "L2CR",
5169 SPR_NOACCESS, SPR_NOACCESS,
5170 &spr_read_generic, &spr_write_generic,
5171 0x00000000);
5172 /* Time base */
5173 gen_tbl(env);
5174 /* Thermal management */
5175 gen_spr_thrm(env);
5176 /* Hardware implementation registers */
5177 /* XXX : not implemented */
5178 spr_register(env, SPR_HID0, "HID0",
5179 SPR_NOACCESS, SPR_NOACCESS,
5180 &spr_read_generic, &spr_write_generic,
5181 0x00000000);
5182 /* XXX : not implemented */
5183 spr_register(env, SPR_HID1, "HID1",
5184 SPR_NOACCESS, SPR_NOACCESS,
5185 &spr_read_generic, &spr_write_generic,
5186 0x00000000);
5187 /* Memory management */
5188 gen_low_BATs(env);
5189 /* XXX: high BATs are also present but are known to be bugged on
5190 * die version 1.x
5191 */
5192 init_excp_7x0(env);
5193 env->dcache_line_size = 32;
5194 env->icache_line_size = 32;
5195 /* Allocate hardware IRQ controller */
5196 ppc6xx_irq_init(env);
5197 }
5198
5199 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5200 {
5201 DeviceClass *dc = DEVICE_CLASS(oc);
5202 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5203
5204 dc->desc = "PowerPC 750";
5205 pcc->init_proc = init_proc_750;
5206 pcc->check_pow = check_pow_hid0;
5207 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5208 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5209 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5210 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5211 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5212 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5213 PPC_SEGMENT | PPC_EXTERN;
5214 pcc->insns_flags2 = PPC_NONE;
5215 pcc->msr_mask = 0x000000000005FF77ULL;
5216 pcc->mmu_model = POWERPC_MMU_32B;
5217 #if defined(CONFIG_SOFTMMU)
5218 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5219 #endif
5220 pcc->excp_model = POWERPC_EXCP_7x0;
5221 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5222 pcc->bfd_mach = bfd_mach_ppc_750;
5223 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5224 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5225 }
5226
5227 static void init_proc_750cl (CPUPPCState *env)
5228 {
5229 gen_spr_ne_601(env);
5230 gen_spr_7xx(env);
5231 /* XXX : not implemented */
5232 spr_register(env, SPR_L2CR, "L2CR",
5233 SPR_NOACCESS, SPR_NOACCESS,
5234 &spr_read_generic, &spr_write_generic,
5235 0x00000000);
5236 /* Time base */
5237 gen_tbl(env);
5238 /* Thermal management */
5239 /* Those registers are fake on 750CL */
5240 spr_register(env, SPR_THRM1, "THRM1",
5241 SPR_NOACCESS, SPR_NOACCESS,
5242 &spr_read_generic, &spr_write_generic,
5243 0x00000000);
5244 spr_register(env, SPR_THRM2, "THRM2",
5245 SPR_NOACCESS, SPR_NOACCESS,
5246 &spr_read_generic, &spr_write_generic,
5247 0x00000000);
5248 spr_register(env, SPR_THRM3, "THRM3",
5249 SPR_NOACCESS, SPR_NOACCESS,
5250 &spr_read_generic, &spr_write_generic,
5251 0x00000000);
5252 /* XXX: not implemented */
5253 spr_register(env, SPR_750_TDCL, "TDCL",
5254 SPR_NOACCESS, SPR_NOACCESS,
5255 &spr_read_generic, &spr_write_generic,
5256 0x00000000);
5257 spr_register(env, SPR_750_TDCH, "TDCH",
5258 SPR_NOACCESS, SPR_NOACCESS,
5259 &spr_read_generic, &spr_write_generic,
5260 0x00000000);
5261 /* DMA */
5262 /* XXX : not implemented */
5263 spr_register(env, SPR_750_WPAR, "WPAR",
5264 SPR_NOACCESS, SPR_NOACCESS,
5265 &spr_read_generic, &spr_write_generic,
5266 0x00000000);
5267 spr_register(env, SPR_750_DMAL, "DMAL",
5268 SPR_NOACCESS, SPR_NOACCESS,
5269 &spr_read_generic, &spr_write_generic,
5270 0x00000000);
5271 spr_register(env, SPR_750_DMAU, "DMAU",
5272 SPR_NOACCESS, SPR_NOACCESS,
5273 &spr_read_generic, &spr_write_generic,
5274 0x00000000);
5275 /* Hardware implementation registers */
5276 /* XXX : not implemented */
5277 spr_register(env, SPR_HID0, "HID0",
5278 SPR_NOACCESS, SPR_NOACCESS,
5279 &spr_read_generic, &spr_write_generic,
5280 0x00000000);
5281 /* XXX : not implemented */
5282 spr_register(env, SPR_HID1, "HID1",
5283 SPR_NOACCESS, SPR_NOACCESS,
5284 &spr_read_generic, &spr_write_generic,
5285 0x00000000);
5286 /* XXX : not implemented */
5287 spr_register(env, SPR_750CL_HID2, "HID2",
5288 SPR_NOACCESS, SPR_NOACCESS,
5289 &spr_read_generic, &spr_write_generic,
5290 0x00000000);
5291 /* XXX : not implemented */
5292 spr_register(env, SPR_750CL_HID4, "HID4",
5293 SPR_NOACCESS, SPR_NOACCESS,
5294 &spr_read_generic, &spr_write_generic,
5295 0x00000000);
5296 /* Quantization registers */
5297 /* XXX : not implemented */
5298 spr_register(env, SPR_750_GQR0, "GQR0",
5299 SPR_NOACCESS, SPR_NOACCESS,
5300 &spr_read_generic, &spr_write_generic,
5301 0x00000000);
5302 /* XXX : not implemented */
5303 spr_register(env, SPR_750_GQR1, "GQR1",
5304 SPR_NOACCESS, SPR_NOACCESS,
5305 &spr_read_generic, &spr_write_generic,
5306 0x00000000);
5307 /* XXX : not implemented */
5308 spr_register(env, SPR_750_GQR2, "GQR2",
5309 SPR_NOACCESS, SPR_NOACCESS,
5310 &spr_read_generic, &spr_write_generic,
5311 0x00000000);
5312 /* XXX : not implemented */
5313 spr_register(env, SPR_750_GQR3, "GQR3",
5314 SPR_NOACCESS, SPR_NOACCESS,
5315 &spr_read_generic, &spr_write_generic,
5316 0x00000000);
5317 /* XXX : not implemented */
5318 spr_register(env, SPR_750_GQR4, "GQR4",
5319 SPR_NOACCESS, SPR_NOACCESS,
5320 &spr_read_generic, &spr_write_generic,
5321 0x00000000);
5322 /* XXX : not implemented */
5323 spr_register(env, SPR_750_GQR5, "GQR5",
5324 SPR_NOACCESS, SPR_NOACCESS,
5325 &spr_read_generic, &spr_write_generic,
5326 0x00000000);
5327 /* XXX : not implemented */
5328 spr_register(env, SPR_750_GQR6, "GQR6",
5329 SPR_NOACCESS, SPR_NOACCESS,
5330 &spr_read_generic, &spr_write_generic,
5331 0x00000000);
5332 /* XXX : not implemented */
5333 spr_register(env, SPR_750_GQR7, "GQR7",
5334 SPR_NOACCESS, SPR_NOACCESS,
5335 &spr_read_generic, &spr_write_generic,
5336 0x00000000);
5337 /* Memory management */
5338 gen_low_BATs(env);
5339 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5340 gen_high_BATs(env);
5341 init_excp_750cl(env);
5342 env->dcache_line_size = 32;
5343 env->icache_line_size = 32;
5344 /* Allocate hardware IRQ controller */
5345 ppc6xx_irq_init(env);
5346 }
5347
5348 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5349 {
5350 DeviceClass *dc = DEVICE_CLASS(oc);
5351 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5352
5353 dc->desc = "PowerPC 750 CL";
5354 pcc->init_proc = init_proc_750cl;
5355 pcc->check_pow = check_pow_hid0;
5356 /* XXX: not implemented:
5357 * cache lock instructions:
5358 * dcbz_l
5359 * floating point paired instructions
5360 * psq_lux
5361 * psq_lx
5362 * psq_stux
5363 * psq_stx
5364 * ps_abs
5365 * ps_add
5366 * ps_cmpo0
5367 * ps_cmpo1
5368 * ps_cmpu0
5369 * ps_cmpu1
5370 * ps_div
5371 * ps_madd
5372 * ps_madds0
5373 * ps_madds1
5374 * ps_merge00
5375 * ps_merge01
5376 * ps_merge10
5377 * ps_merge11
5378 * ps_mr
5379 * ps_msub
5380 * ps_mul
5381 * ps_muls0
5382 * ps_muls1
5383 * ps_nabs
5384 * ps_neg
5385 * ps_nmadd
5386 * ps_nmsub
5387 * ps_res
5388 * ps_rsqrte
5389 * ps_sel
5390 * ps_sub
5391 * ps_sum0
5392 * ps_sum1
5393 */
5394 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5395 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5396 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5397 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5398 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5399 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5400 PPC_SEGMENT | PPC_EXTERN;
5401 pcc->insns_flags2 = PPC_NONE;
5402 pcc->msr_mask = 0x000000000005FF77ULL;
5403 pcc->mmu_model = POWERPC_MMU_32B;
5404 #if defined(CONFIG_SOFTMMU)
5405 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5406 #endif
5407 pcc->excp_model = POWERPC_EXCP_7x0;
5408 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5409 pcc->bfd_mach = bfd_mach_ppc_750;
5410 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5411 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5412 }
5413
5414 static void init_proc_750cx (CPUPPCState *env)
5415 {
5416 gen_spr_ne_601(env);
5417 gen_spr_7xx(env);
5418 /* XXX : not implemented */
5419 spr_register(env, SPR_L2CR, "L2CR",
5420 SPR_NOACCESS, SPR_NOACCESS,
5421 &spr_read_generic, &spr_write_generic,
5422 0x00000000);
5423 /* Time base */
5424 gen_tbl(env);
5425 /* Thermal management */
5426 gen_spr_thrm(env);
5427 /* This register is not implemented but is present for compatibility */
5428 spr_register(env, SPR_SDA, "SDA",
5429 SPR_NOACCESS, SPR_NOACCESS,
5430 &spr_read_generic, &spr_write_generic,
5431 0x00000000);
5432 /* Hardware implementation registers */
5433 /* XXX : not implemented */
5434 spr_register(env, SPR_HID0, "HID0",
5435 SPR_NOACCESS, SPR_NOACCESS,
5436 &spr_read_generic, &spr_write_generic,
5437 0x00000000);
5438 /* XXX : not implemented */
5439 spr_register(env, SPR_HID1, "HID1",
5440 SPR_NOACCESS, SPR_NOACCESS,
5441 &spr_read_generic, &spr_write_generic,
5442 0x00000000);
5443 /* Memory management */
5444 gen_low_BATs(env);
5445 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5446 gen_high_BATs(env);
5447 init_excp_750cx(env);
5448 env->dcache_line_size = 32;
5449 env->icache_line_size = 32;
5450 /* Allocate hardware IRQ controller */
5451 ppc6xx_irq_init(env);
5452 }
5453
5454 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
5455 {
5456 DeviceClass *dc = DEVICE_CLASS(oc);
5457 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5458
5459 dc->desc = "PowerPC 750CX";
5460 pcc->init_proc = init_proc_750cx;
5461 pcc->check_pow = check_pow_hid0;
5462 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5463 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5464 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5465 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5466 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5467 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5468 PPC_SEGMENT | PPC_EXTERN;
5469 pcc->insns_flags2 = PPC_NONE;
5470 pcc->msr_mask = 0x000000000005FF77ULL;
5471 pcc->mmu_model = POWERPC_MMU_32B;
5472 #if defined(CONFIG_SOFTMMU)
5473 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5474 #endif
5475 pcc->excp_model = POWERPC_EXCP_7x0;
5476 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5477 pcc->bfd_mach = bfd_mach_ppc_750;
5478 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5479 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5480 }
5481
5482 static void init_proc_750fx (CPUPPCState *env)
5483 {
5484 gen_spr_ne_601(env);
5485 gen_spr_7xx(env);
5486 /* XXX : not implemented */
5487 spr_register(env, SPR_L2CR, "L2CR",
5488 SPR_NOACCESS, SPR_NOACCESS,
5489 &spr_read_generic, &spr_write_generic,
5490 0x00000000);
5491 /* Time base */
5492 gen_tbl(env);
5493 /* Thermal management */
5494 gen_spr_thrm(env);
5495 /* XXX : not implemented */
5496 spr_register(env, SPR_750_THRM4, "THRM4",
5497 SPR_NOACCESS, SPR_NOACCESS,
5498 &spr_read_generic, &spr_write_generic,
5499 0x00000000);
5500 /* Hardware implementation registers */
5501 /* XXX : not implemented */
5502 spr_register(env, SPR_HID0, "HID0",
5503 SPR_NOACCESS, SPR_NOACCESS,
5504 &spr_read_generic, &spr_write_generic,
5505 0x00000000);
5506 /* XXX : not implemented */
5507 spr_register(env, SPR_HID1, "HID1",
5508 SPR_NOACCESS, SPR_NOACCESS,
5509 &spr_read_generic, &spr_write_generic,
5510 0x00000000);
5511 /* XXX : not implemented */
5512 spr_register(env, SPR_750FX_HID2, "HID2",
5513 SPR_NOACCESS, SPR_NOACCESS,
5514 &spr_read_generic, &spr_write_generic,
5515 0x00000000);
5516 /* Memory management */
5517 gen_low_BATs(env);
5518 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5519 gen_high_BATs(env);
5520 init_excp_7x0(env);
5521 env->dcache_line_size = 32;
5522 env->icache_line_size = 32;
5523 /* Allocate hardware IRQ controller */
5524 ppc6xx_irq_init(env);
5525 }
5526
5527 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
5528 {
5529 DeviceClass *dc = DEVICE_CLASS(oc);
5530 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5531
5532 dc->desc = "PowerPC 750FX";
5533 pcc->init_proc = init_proc_750fx;
5534 pcc->check_pow = check_pow_hid0;
5535 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5536 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5537 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5538 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5539 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5540 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5541 PPC_SEGMENT | PPC_EXTERN;
5542 pcc->insns_flags2 = PPC_NONE;
5543 pcc->msr_mask = 0x000000000005FF77ULL;
5544 pcc->mmu_model = POWERPC_MMU_32B;
5545 #if defined(CONFIG_SOFTMMU)
5546 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5547 #endif
5548 pcc->excp_model = POWERPC_EXCP_7x0;
5549 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5550 pcc->bfd_mach = bfd_mach_ppc_750;
5551 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5552 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5553 }
5554
5555 static void init_proc_750gx (CPUPPCState *env)
5556 {
5557 gen_spr_ne_601(env);
5558 gen_spr_7xx(env);
5559 /* XXX : not implemented (XXX: different from 750fx) */
5560 spr_register(env, SPR_L2CR, "L2CR",
5561 SPR_NOACCESS, SPR_NOACCESS,
5562 &spr_read_generic, &spr_write_generic,
5563 0x00000000);
5564 /* Time base */
5565 gen_tbl(env);
5566 /* Thermal management */
5567 gen_spr_thrm(env);
5568 /* XXX : not implemented */
5569 spr_register(env, SPR_750_THRM4, "THRM4",
5570 SPR_NOACCESS, SPR_NOACCESS,
5571 &spr_read_generic, &spr_write_generic,
5572 0x00000000);
5573 /* Hardware implementation registers */
5574 /* XXX : not implemented (XXX: different from 750fx) */
5575 spr_register(env, SPR_HID0, "HID0",
5576 SPR_NOACCESS, SPR_NOACCESS,
5577 &spr_read_generic, &spr_write_generic,
5578 0x00000000);
5579 /* XXX : not implemented */
5580 spr_register(env, SPR_HID1, "HID1",
5581 SPR_NOACCESS, SPR_NOACCESS,
5582 &spr_read_generic, &spr_write_generic,
5583 0x00000000);
5584 /* XXX : not implemented (XXX: different from 750fx) */
5585 spr_register(env, SPR_750FX_HID2, "HID2",
5586 SPR_NOACCESS, SPR_NOACCESS,
5587 &spr_read_generic, &spr_write_generic,
5588 0x00000000);
5589 /* Memory management */
5590 gen_low_BATs(env);
5591 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5592 gen_high_BATs(env);
5593 init_excp_7x0(env);
5594 env->dcache_line_size = 32;
5595 env->icache_line_size = 32;
5596 /* Allocate hardware IRQ controller */
5597 ppc6xx_irq_init(env);
5598 }
5599
5600 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
5601 {
5602 DeviceClass *dc = DEVICE_CLASS(oc);
5603 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5604
5605 dc->desc = "PowerPC 750GX";
5606 pcc->init_proc = init_proc_750gx;
5607 pcc->check_pow = check_pow_hid0;
5608 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5609 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5610 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5611 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5612 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5613 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5614 PPC_SEGMENT | PPC_EXTERN;
5615 pcc->insns_flags2 = PPC_NONE;
5616 pcc->msr_mask = 0x000000000005FF77ULL;
5617 pcc->mmu_model = POWERPC_MMU_32B;
5618 #if defined(CONFIG_SOFTMMU)
5619 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5620 #endif
5621 pcc->excp_model = POWERPC_EXCP_7x0;
5622 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5623 pcc->bfd_mach = bfd_mach_ppc_750;
5624 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5625 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5626 }
5627
5628 static void init_proc_745 (CPUPPCState *env)
5629 {
5630 gen_spr_ne_601(env);
5631 gen_spr_7xx(env);
5632 gen_spr_G2_755(env);
5633 /* Time base */
5634 gen_tbl(env);
5635 /* Thermal management */
5636 gen_spr_thrm(env);
5637 /* Hardware implementation registers */
5638 /* XXX : not implemented */
5639 spr_register(env, SPR_HID0, "HID0",
5640 SPR_NOACCESS, SPR_NOACCESS,
5641 &spr_read_generic, &spr_write_generic,
5642 0x00000000);
5643 /* XXX : not implemented */
5644 spr_register(env, SPR_HID1, "HID1",
5645 SPR_NOACCESS, SPR_NOACCESS,
5646 &spr_read_generic, &spr_write_generic,
5647 0x00000000);
5648 /* XXX : not implemented */
5649 spr_register(env, SPR_HID2, "HID2",
5650 SPR_NOACCESS, SPR_NOACCESS,
5651 &spr_read_generic, &spr_write_generic,
5652 0x00000000);
5653 /* Memory management */
5654 gen_low_BATs(env);
5655 gen_high_BATs(env);
5656 gen_6xx_7xx_soft_tlb(env, 64, 2);
5657 init_excp_7x5(env);
5658 env->dcache_line_size = 32;
5659 env->icache_line_size = 32;
5660 /* Allocate hardware IRQ controller */
5661 ppc6xx_irq_init(env);
5662 }
5663
5664 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
5665 {
5666 DeviceClass *dc = DEVICE_CLASS(oc);
5667 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5668
5669 dc->desc = "PowerPC 745";
5670 pcc->init_proc = init_proc_745;
5671 pcc->check_pow = check_pow_hid0;
5672 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5673 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5674 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5675 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5676 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5677 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5678 PPC_SEGMENT | PPC_EXTERN;
5679 pcc->insns_flags2 = PPC_NONE;
5680 pcc->msr_mask = 0x000000000005FF77ULL;
5681 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5682 pcc->excp_model = POWERPC_EXCP_7x5;
5683 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5684 pcc->bfd_mach = bfd_mach_ppc_750;
5685 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5686 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5687 }
5688
5689 static void init_proc_755 (CPUPPCState *env)
5690 {
5691 gen_spr_ne_601(env);
5692 gen_spr_7xx(env);
5693 gen_spr_G2_755(env);
5694 /* Time base */
5695 gen_tbl(env);
5696 /* L2 cache control */
5697 /* XXX : not implemented */
5698 spr_register(env, SPR_L2CR, "L2CR",
5699 SPR_NOACCESS, SPR_NOACCESS,
5700 &spr_read_generic, &spr_write_generic,
5701 0x00000000);
5702 /* XXX : not implemented */
5703 spr_register(env, SPR_L2PMCR, "L2PMCR",
5704 SPR_NOACCESS, SPR_NOACCESS,
5705 &spr_read_generic, &spr_write_generic,
5706 0x00000000);
5707 /* Thermal management */
5708 gen_spr_thrm(env);
5709 /* Hardware implementation registers */
5710 /* XXX : not implemented */
5711 spr_register(env, SPR_HID0, "HID0",
5712 SPR_NOACCESS, SPR_NOACCESS,
5713 &spr_read_generic, &spr_write_generic,
5714 0x00000000);
5715 /* XXX : not implemented */
5716 spr_register(env, SPR_HID1, "HID1",
5717 SPR_NOACCESS, SPR_NOACCESS,
5718 &spr_read_generic, &spr_write_generic,
5719 0x00000000);
5720 /* XXX : not implemented */
5721 spr_register(env, SPR_HID2, "HID2",
5722 SPR_NOACCESS, SPR_NOACCESS,
5723 &spr_read_generic, &spr_write_generic,
5724 0x00000000);
5725 /* Memory management */
5726 gen_low_BATs(env);
5727 gen_high_BATs(env);
5728 gen_6xx_7xx_soft_tlb(env, 64, 2);
5729 init_excp_7x5(env);
5730 env->dcache_line_size = 32;
5731 env->icache_line_size = 32;
5732 /* Allocate hardware IRQ controller */
5733 ppc6xx_irq_init(env);
5734 }
5735
5736 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
5737 {
5738 DeviceClass *dc = DEVICE_CLASS(oc);
5739 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5740
5741 dc->desc = "PowerPC 755";
5742 pcc->init_proc = init_proc_755;
5743 pcc->check_pow = check_pow_hid0;
5744 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5745 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5746 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5747 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5748 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5749 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5750 PPC_SEGMENT | PPC_EXTERN;
5751 pcc->insns_flags2 = PPC_NONE;
5752 pcc->msr_mask = 0x000000000005FF77ULL;
5753 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5754 pcc->excp_model = POWERPC_EXCP_7x5;
5755 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5756 pcc->bfd_mach = bfd_mach_ppc_750;
5757 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5758 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5759 }
5760
5761 static void init_proc_7400 (CPUPPCState *env)
5762 {
5763 gen_spr_ne_601(env);
5764 gen_spr_7xx(env);
5765 /* Time base */
5766 gen_tbl(env);
5767 /* 74xx specific SPR */
5768 gen_spr_74xx(env);
5769 /* XXX : not implemented */
5770 spr_register(env, SPR_UBAMR, "UBAMR",
5771 &spr_read_ureg, SPR_NOACCESS,
5772 &spr_read_ureg, SPR_NOACCESS,
5773 0x00000000);
5774 /* XXX: this seems not implemented on all revisions. */
5775 /* XXX : not implemented */
5776 spr_register(env, SPR_MSSCR1, "MSSCR1",
5777 SPR_NOACCESS, SPR_NOACCESS,
5778 &spr_read_generic, &spr_write_generic,
5779 0x00000000);
5780 /* Thermal management */
5781 gen_spr_thrm(env);
5782 /* Memory management */
5783 gen_low_BATs(env);
5784 init_excp_7400(env);
5785 env->dcache_line_size = 32;
5786 env->icache_line_size = 32;
5787 /* Allocate hardware IRQ controller */
5788 ppc6xx_irq_init(env);
5789 }
5790
5791 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
5792 {
5793 DeviceClass *dc = DEVICE_CLASS(oc);
5794 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5795
5796 dc->desc = "PowerPC 7400 (aka G4)";
5797 pcc->init_proc = init_proc_7400;
5798 pcc->check_pow = check_pow_hid0;
5799 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5800 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5801 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5802 PPC_FLOAT_STFIWX |
5803 PPC_CACHE | PPC_CACHE_ICBI |
5804 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5805 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5806 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5807 PPC_MEM_TLBIA |
5808 PPC_SEGMENT | PPC_EXTERN |
5809 PPC_ALTIVEC;
5810 pcc->insns_flags2 = PPC_NONE;
5811 pcc->msr_mask = 0x000000000205FF77ULL;
5812 pcc->mmu_model = POWERPC_MMU_32B;
5813 #if defined(CONFIG_SOFTMMU)
5814 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5815 #endif
5816 pcc->excp_model = POWERPC_EXCP_74xx;
5817 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5818 pcc->bfd_mach = bfd_mach_ppc_7400;
5819 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5820 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5821 POWERPC_FLAG_BUS_CLK;
5822 }
5823
5824 static void init_proc_7410 (CPUPPCState *env)
5825 {
5826 gen_spr_ne_601(env);
5827 gen_spr_7xx(env);
5828 /* Time base */
5829 gen_tbl(env);
5830 /* 74xx specific SPR */
5831 gen_spr_74xx(env);
5832 /* XXX : not implemented */
5833 spr_register(env, SPR_UBAMR, "UBAMR",
5834 &spr_read_ureg, SPR_NOACCESS,
5835 &spr_read_ureg, SPR_NOACCESS,
5836 0x00000000);
5837 /* Thermal management */
5838 gen_spr_thrm(env);
5839 /* L2PMCR */
5840 /* XXX : not implemented */
5841 spr_register(env, SPR_L2PMCR, "L2PMCR",
5842 SPR_NOACCESS, SPR_NOACCESS,
5843 &spr_read_generic, &spr_write_generic,
5844 0x00000000);
5845 /* LDSTDB */
5846 /* XXX : not implemented */
5847 spr_register(env, SPR_LDSTDB, "LDSTDB",
5848 SPR_NOACCESS, SPR_NOACCESS,
5849 &spr_read_generic, &spr_write_generic,
5850 0x00000000);
5851 /* Memory management */
5852 gen_low_BATs(env);
5853 init_excp_7400(env);
5854 env->dcache_line_size = 32;
5855 env->icache_line_size = 32;
5856 /* Allocate hardware IRQ controller */
5857 ppc6xx_irq_init(env);
5858 }
5859
5860 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
5861 {
5862 DeviceClass *dc = DEVICE_CLASS(oc);
5863 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5864
5865 dc->desc = "PowerPC 7410 (aka G4)";
5866 pcc->init_proc = init_proc_7410;
5867 pcc->check_pow = check_pow_hid0;
5868 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5869 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5870 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5871 PPC_FLOAT_STFIWX |
5872 PPC_CACHE | PPC_CACHE_ICBI |
5873 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5874 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5875 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5876 PPC_MEM_TLBIA |
5877 PPC_SEGMENT | PPC_EXTERN |
5878 PPC_ALTIVEC;
5879 pcc->insns_flags2 = PPC_NONE;
5880 pcc->msr_mask = 0x000000000205FF77ULL;
5881 pcc->mmu_model = POWERPC_MMU_32B;
5882 #if defined(CONFIG_SOFTMMU)
5883 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5884 #endif
5885 pcc->excp_model = POWERPC_EXCP_74xx;
5886 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5887 pcc->bfd_mach = bfd_mach_ppc_7400;
5888 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5889 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5890 POWERPC_FLAG_BUS_CLK;
5891 }
5892
5893 static void init_proc_7440 (CPUPPCState *env)
5894 {
5895 gen_spr_ne_601(env);
5896 gen_spr_7xx(env);
5897 /* Time base */
5898 gen_tbl(env);
5899 /* 74xx specific SPR */
5900 gen_spr_74xx(env);
5901 /* XXX : not implemented */
5902 spr_register(env, SPR_UBAMR, "UBAMR",
5903 &spr_read_ureg, SPR_NOACCESS,
5904 &spr_read_ureg, SPR_NOACCESS,
5905 0x00000000);
5906 /* LDSTCR */
5907 /* XXX : not implemented */
5908 spr_register(env, SPR_LDSTCR, "LDSTCR",
5909 SPR_NOACCESS, SPR_NOACCESS,
5910 &spr_read_generic, &spr_write_generic,
5911 0x00000000);
5912 /* ICTRL */
5913 /* XXX : not implemented */
5914 spr_register(env, SPR_ICTRL, "ICTRL",
5915 SPR_NOACCESS, SPR_NOACCESS,
5916 &spr_read_generic, &spr_write_generic,
5917 0x00000000);
5918 /* MSSSR0 */
5919 /* XXX : not implemented */
5920 spr_register(env, SPR_MSSSR0, "MSSSR0",
5921 SPR_NOACCESS, SPR_NOACCESS,
5922 &spr_read_generic, &spr_write_generic,
5923 0x00000000);
5924 /* PMC */
5925 /* XXX : not implemented */
5926 spr_register(env, SPR_PMC5, "PMC5",
5927 SPR_NOACCESS, SPR_NOACCESS,
5928 &spr_read_generic, &spr_write_generic,
5929 0x00000000);
5930 /* XXX : not implemented */
5931 spr_register(env, SPR_UPMC5, "UPMC5",
5932 &spr_read_ureg, SPR_NOACCESS,
5933 &spr_read_ureg, SPR_NOACCESS,
5934 0x00000000);
5935 /* XXX : not implemented */
5936 spr_register(env, SPR_PMC6, "PMC6",
5937 SPR_NOACCESS, SPR_NOACCESS,
5938 &spr_read_generic, &spr_write_generic,
5939 0x00000000);
5940 /* XXX : not implemented */
5941 spr_register(env, SPR_UPMC6, "UPMC6",
5942 &spr_read_ureg, SPR_NOACCESS,
5943 &spr_read_ureg, SPR_NOACCESS,
5944 0x00000000);
5945 /* Memory management */
5946 gen_low_BATs(env);
5947 gen_74xx_soft_tlb(env, 128, 2);
5948 init_excp_7450(env);
5949 env->dcache_line_size = 32;
5950 env->icache_line_size = 32;
5951 /* Allocate hardware IRQ controller */
5952 ppc6xx_irq_init(env);
5953 }
5954
5955 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
5956 {
5957 DeviceClass *dc = DEVICE_CLASS(oc);
5958 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5959
5960 dc->desc = "PowerPC 7440 (aka G4)";
5961 pcc->init_proc = init_proc_7440;
5962 pcc->check_pow = check_pow_hid0_74xx;
5963 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5964 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5965 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5966 PPC_FLOAT_STFIWX |
5967 PPC_CACHE | PPC_CACHE_ICBI |
5968 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5969 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5970 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5971 PPC_MEM_TLBIA | PPC_74xx_TLB |
5972 PPC_SEGMENT | PPC_EXTERN |
5973 PPC_ALTIVEC;
5974 pcc->insns_flags2 = PPC_NONE;
5975 pcc->msr_mask = 0x000000000205FF77ULL;
5976 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
5977 pcc->excp_model = POWERPC_EXCP_74xx;
5978 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5979 pcc->bfd_mach = bfd_mach_ppc_7400;
5980 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5981 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5982 POWERPC_FLAG_BUS_CLK;
5983 }
5984
5985 static void init_proc_7450 (CPUPPCState *env)
5986 {
5987 gen_spr_ne_601(env);
5988 gen_spr_7xx(env);
5989 /* Time base */
5990 gen_tbl(env);
5991 /* 74xx specific SPR */
5992 gen_spr_74xx(env);
5993 /* Level 3 cache control */
5994 gen_l3_ctrl(env);
5995 /* L3ITCR1 */
5996 /* XXX : not implemented */
5997 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5998 SPR_NOACCESS, SPR_NOACCESS,
5999 &spr_read_generic, &spr_write_generic,
6000 0x00000000);
6001 /* L3ITCR2 */
6002 /* XXX : not implemented */
6003 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6004 SPR_NOACCESS, SPR_NOACCESS,
6005 &spr_read_generic, &spr_write_generic,
6006 0x00000000);
6007 /* L3ITCR3 */
6008 /* XXX : not implemented */
6009 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6010 SPR_NOACCESS, SPR_NOACCESS,
6011 &spr_read_generic, &spr_write_generic,
6012 0x00000000);
6013 /* L3OHCR */
6014 /* XXX : not implemented */
6015 spr_register(env, SPR_L3OHCR, "L3OHCR",
6016 SPR_NOACCESS, SPR_NOACCESS,
6017 &spr_read_generic, &spr_write_generic,
6018 0x00000000);
6019 /* XXX : not implemented */
6020 spr_register(env, SPR_UBAMR, "UBAMR",
6021 &spr_read_ureg, SPR_NOACCESS,
6022 &spr_read_ureg, SPR_NOACCESS,
6023 0x00000000);
6024 /* LDSTCR */
6025 /* XXX : not implemented */
6026 spr_register(env, SPR_LDSTCR, "LDSTCR",
6027 SPR_NOACCESS, SPR_NOACCESS,
6028 &spr_read_generic, &spr_write_generic,
6029 0x00000000);
6030 /* ICTRL */
6031 /* XXX : not implemented */
6032 spr_register(env, SPR_ICTRL, "ICTRL",
6033 SPR_NOACCESS, SPR_NOACCESS,
6034 &spr_read_generic, &spr_write_generic,
6035 0x00000000);
6036 /* MSSSR0 */
6037 /* XXX : not implemented */
6038 spr_register(env, SPR_MSSSR0, "MSSSR0",
6039 SPR_NOACCESS, SPR_NOACCESS,
6040 &spr_read_generic, &spr_write_generic,
6041 0x00000000);
6042 /* PMC */
6043 /* XXX : not implemented */
6044 spr_register(env, SPR_PMC5, "PMC5",
6045 SPR_NOACCESS, SPR_NOACCESS,
6046 &spr_read_generic, &spr_write_generic,
6047 0x00000000);
6048 /* XXX : not implemented */
6049 spr_register(env, SPR_UPMC5, "UPMC5",
6050 &spr_read_ureg, SPR_NOACCESS,
6051 &spr_read_ureg, SPR_NOACCESS,
6052 0x00000000);
6053 /* XXX : not implemented */
6054 spr_register(env, SPR_PMC6, "PMC6",
6055 SPR_NOACCESS, SPR_NOACCESS,
6056 &spr_read_generic, &spr_write_generic,
6057 0x00000000);
6058 /* XXX : not implemented */
6059 spr_register(env, SPR_UPMC6, "UPMC6",
6060 &spr_read_ureg, SPR_NOACCESS,
6061 &spr_read_ureg, SPR_NOACCESS,
6062 0x00000000);
6063 /* Memory management */
6064 gen_low_BATs(env);
6065 gen_74xx_soft_tlb(env, 128, 2);
6066 init_excp_7450(env);
6067 env->dcache_line_size = 32;
6068 env->icache_line_size = 32;
6069 /* Allocate hardware IRQ controller */
6070 ppc6xx_irq_init(env);
6071 }
6072
6073 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6074 {
6075 DeviceClass *dc = DEVICE_CLASS(oc);
6076 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6077
6078 dc->desc = "PowerPC 7450 (aka G4)";
6079 pcc->init_proc = init_proc_7450;
6080 pcc->check_pow = check_pow_hid0_74xx;
6081 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6082 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6083 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6084 PPC_FLOAT_STFIWX |
6085 PPC_CACHE | PPC_CACHE_ICBI |
6086 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6087 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6088 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6089 PPC_MEM_TLBIA | PPC_74xx_TLB |
6090 PPC_SEGMENT | PPC_EXTERN |
6091 PPC_ALTIVEC;
6092 pcc->insns_flags2 = PPC_NONE;
6093 pcc->msr_mask = 0x000000000205FF77ULL;
6094 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6095 pcc->excp_model = POWERPC_EXCP_74xx;
6096 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6097 pcc->bfd_mach = bfd_mach_ppc_7400;
6098 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6099 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6100 POWERPC_FLAG_BUS_CLK;
6101 }
6102
6103 static void init_proc_7445 (CPUPPCState *env)
6104 {
6105 gen_spr_ne_601(env);
6106 gen_spr_7xx(env);
6107 /* Time base */
6108 gen_tbl(env);
6109 /* 74xx specific SPR */
6110 gen_spr_74xx(env);
6111 /* LDSTCR */
6112 /* XXX : not implemented */
6113 spr_register(env, SPR_LDSTCR, "LDSTCR",
6114 SPR_NOACCESS, SPR_NOACCESS,
6115 &spr_read_generic, &spr_write_generic,
6116 0x00000000);
6117 /* ICTRL */
6118 /* XXX : not implemented */
6119 spr_register(env, SPR_ICTRL, "ICTRL",
6120 SPR_NOACCESS, SPR_NOACCESS,
6121 &spr_read_generic, &spr_write_generic,
6122 0x00000000);
6123 /* MSSSR0 */
6124 /* XXX : not implemented */
6125 spr_register(env, SPR_MSSSR0, "MSSSR0",
6126 SPR_NOACCESS, SPR_NOACCESS,
6127 &spr_read_generic, &spr_write_generic,
6128 0x00000000);
6129 /* PMC */
6130 /* XXX : not implemented */
6131 spr_register(env, SPR_PMC5, "PMC5",
6132 SPR_NOACCESS, SPR_NOACCESS,
6133 &spr_read_generic, &spr_write_generic,
6134 0x00000000);
6135 /* XXX : not implemented */
6136 spr_register(env, SPR_UPMC5, "UPMC5",
6137 &spr_read_ureg, SPR_NOACCESS,
6138 &spr_read_ureg, SPR_NOACCESS,
6139 0x00000000);
6140 /* XXX : not implemented */
6141 spr_register(env, SPR_PMC6, "PMC6",
6142 SPR_NOACCESS, SPR_NOACCESS,
6143 &spr_read_generic, &spr_write_generic,
6144 0x00000000);
6145 /* XXX : not implemented */
6146 spr_register(env, SPR_UPMC6, "UPMC6",
6147 &spr_read_ureg, SPR_NOACCESS,
6148 &spr_read_ureg, SPR_NOACCESS,
6149 0x00000000);
6150 /* SPRGs */
6151 spr_register(env, SPR_SPRG4, "SPRG4",
6152 SPR_NOACCESS, SPR_NOACCESS,
6153 &spr_read_generic, &spr_write_generic,
6154 0x00000000);
6155 spr_register(env, SPR_USPRG4, "USPRG4",
6156 &spr_read_ureg, SPR_NOACCESS,
6157 &spr_read_ureg, SPR_NOACCESS,
6158 0x00000000);
6159 spr_register(env, SPR_SPRG5, "SPRG5",
6160 SPR_NOACCESS, SPR_NOACCESS,
6161 &spr_read_generic, &spr_write_generic,
6162 0x00000000);
6163 spr_register(env, SPR_USPRG5, "USPRG5",
6164 &spr_read_ureg, SPR_NOACCESS,
6165 &spr_read_ureg, SPR_NOACCESS,
6166 0x00000000);
6167 spr_register(env, SPR_SPRG6, "SPRG6",
6168 SPR_NOACCESS, SPR_NOACCESS,
6169 &spr_read_generic, &spr_write_generic,
6170 0x00000000);
6171 spr_register(env, SPR_USPRG6, "USPRG6",
6172 &spr_read_ureg, SPR_NOACCESS,
6173 &spr_read_ureg, SPR_NOACCESS,
6174 0x00000000);
6175 spr_register(env, SPR_SPRG7, "SPRG7",
6176 SPR_NOACCESS, SPR_NOACCESS,
6177 &spr_read_generic, &spr_write_generic,
6178 0x00000000);
6179 spr_register(env, SPR_USPRG7, "USPRG7",
6180 &spr_read_ureg, SPR_NOACCESS,
6181 &spr_read_ureg, SPR_NOACCESS,
6182 0x00000000);
6183 /* Memory management */
6184 gen_low_BATs(env);
6185 gen_high_BATs(env);
6186 gen_74xx_soft_tlb(env, 128, 2);
6187 init_excp_7450(env);
6188 env->dcache_line_size = 32;
6189 env->icache_line_size = 32;
6190 /* Allocate hardware IRQ controller */
6191 ppc6xx_irq_init(env);
6192 }
6193
6194 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6195 {
6196 DeviceClass *dc = DEVICE_CLASS(oc);
6197 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6198
6199 dc->desc = "PowerPC 7445 (aka G4)";
6200 pcc->init_proc = init_proc_7445;
6201 pcc->check_pow = check_pow_hid0_74xx;
6202 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6203 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6204 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6205 PPC_FLOAT_STFIWX |
6206 PPC_CACHE | PPC_CACHE_ICBI |
6207 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6208 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6209 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6210 PPC_MEM_TLBIA | PPC_74xx_TLB |
6211 PPC_SEGMENT | PPC_EXTERN |
6212 PPC_ALTIVEC;
6213 pcc->insns_flags2 = PPC_NONE;
6214 pcc->msr_mask = 0x000000000205FF77ULL;
6215 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6216 pcc->excp_model = POWERPC_EXCP_74xx;
6217 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6218 pcc->bfd_mach = bfd_mach_ppc_7400;
6219 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6220 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6221 POWERPC_FLAG_BUS_CLK;
6222 }
6223
6224 static void init_proc_7455 (CPUPPCState *env)
6225 {
6226 gen_spr_ne_601(env);
6227 gen_spr_7xx(env);
6228 /* Time base */
6229 gen_tbl(env);
6230 /* 74xx specific SPR */
6231 gen_spr_74xx(env);
6232 /* Level 3 cache control */
6233 gen_l3_ctrl(env);
6234 /* LDSTCR */
6235 /* XXX : not implemented */
6236 spr_register(env, SPR_LDSTCR, "LDSTCR",
6237 SPR_NOACCESS, SPR_NOACCESS,
6238 &spr_read_generic, &spr_write_generic,
6239 0x00000000);
6240 /* ICTRL */
6241 /* XXX : not implemented */
6242 spr_register(env, SPR_ICTRL, "ICTRL",
6243 SPR_NOACCESS, SPR_NOACCESS,
6244 &spr_read_generic, &spr_write_generic,
6245 0x00000000);
6246 /* MSSSR0 */
6247 /* XXX : not implemented */
6248 spr_register(env, SPR_MSSSR0, "MSSSR0",
6249 SPR_NOACCESS, SPR_NOACCESS,
6250 &spr_read_generic, &spr_write_generic,
6251 0x00000000);
6252 /* PMC */
6253 /* XXX : not implemented */
6254 spr_register(env, SPR_PMC5, "PMC5",
6255 SPR_NOACCESS, SPR_NOACCESS,
6256 &spr_read_generic, &spr_write_generic,
6257 0x00000000);
6258 /* XXX : not implemented */
6259 spr_register(env, SPR_UPMC5, "UPMC5",
6260 &spr_read_ureg, SPR_NOACCESS,
6261 &spr_read_ureg, SPR_NOACCESS,
6262 0x00000000);
6263 /* XXX : not implemented */
6264 spr_register(env, SPR_PMC6, "PMC6",
6265 SPR_NOACCESS, SPR_NOACCESS,
6266 &spr_read_generic, &spr_write_generic,
6267 0x00000000);
6268 /* XXX : not implemented */
6269 spr_register(env, SPR_UPMC6, "UPMC6",
6270 &spr_read_ureg, SPR_NOACCESS,
6271 &spr_read_ureg, SPR_NOACCESS,
6272 0x00000000);
6273 /* SPRGs */
6274 spr_register(env, SPR_SPRG4, "SPRG4",
6275 SPR_NOACCESS, SPR_NOACCESS,
6276 &spr_read_generic, &spr_write_generic,
6277 0x00000000);
6278 spr_register(env, SPR_USPRG4, "USPRG4",
6279 &spr_read_ureg, SPR_NOACCESS,
6280 &spr_read_ureg, SPR_NOACCESS,
6281 0x00000000);
6282 spr_register(env, SPR_SPRG5, "SPRG5",
6283 SPR_NOACCESS, SPR_NOACCESS,
6284 &spr_read_generic, &spr_write_generic,
6285 0x00000000);
6286 spr_register(env, SPR_USPRG5, "USPRG5",
6287 &spr_read_ureg, SPR_NOACCESS,
6288 &spr_read_ureg, SPR_NOACCESS,
6289 0x00000000);
6290 spr_register(env, SPR_SPRG6, "SPRG6",
6291 SPR_NOACCESS, SPR_NOACCESS,
6292 &spr_read_generic, &spr_write_generic,
6293 0x00000000);
6294 spr_register(env, SPR_USPRG6, "USPRG6",
6295 &spr_read_ureg, SPR_NOACCESS,
6296 &spr_read_ureg, SPR_NOACCESS,
6297 0x00000000);
6298 spr_register(env, SPR_SPRG7, "SPRG7",
6299 SPR_NOACCESS, SPR_NOACCESS,
6300 &spr_read_generic, &spr_write_generic,
6301 0x00000000);
6302 spr_register(env, SPR_USPRG7, "USPRG7",
6303 &spr_read_ureg, SPR_NOACCESS,
6304 &spr_read_ureg, SPR_NOACCESS,
6305 0x00000000);
6306 /* Memory management */
6307 gen_low_BATs(env);
6308 gen_high_BATs(env);
6309 gen_74xx_soft_tlb(env, 128, 2);
6310 init_excp_7450(env);
6311 env->dcache_line_size = 32;
6312 env->icache_line_size = 32;
6313 /* Allocate hardware IRQ controller */
6314 ppc6xx_irq_init(env);
6315 }
6316
6317 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
6318 {
6319 DeviceClass *dc = DEVICE_CLASS(oc);
6320 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6321
6322 dc->desc = "PowerPC 7455 (aka G4)";
6323 pcc->init_proc = init_proc_7455;
6324 pcc->check_pow = check_pow_hid0_74xx;
6325 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6326 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6327 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6328 PPC_FLOAT_STFIWX |
6329 PPC_CACHE | PPC_CACHE_ICBI |
6330 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6331 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6332 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6333 PPC_MEM_TLBIA | PPC_74xx_TLB |
6334 PPC_SEGMENT | PPC_EXTERN |
6335 PPC_ALTIVEC;
6336 pcc->insns_flags2 = PPC_NONE;
6337 pcc->msr_mask = 0x000000000205FF77ULL;
6338 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6339 pcc->excp_model = POWERPC_EXCP_74xx;
6340 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6341 pcc->bfd_mach = bfd_mach_ppc_7400;
6342 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6343 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6344 POWERPC_FLAG_BUS_CLK;
6345 }
6346
6347 static void init_proc_7457 (CPUPPCState *env)
6348 {
6349 gen_spr_ne_601(env);
6350 gen_spr_7xx(env);
6351 /* Time base */
6352 gen_tbl(env);
6353 /* 74xx specific SPR */
6354 gen_spr_74xx(env);
6355 /* Level 3 cache control */
6356 gen_l3_ctrl(env);
6357 /* L3ITCR1 */
6358 /* XXX : not implemented */
6359 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6360 SPR_NOACCESS, SPR_NOACCESS,
6361 &spr_read_generic, &spr_write_generic,
6362 0x00000000);
6363 /* L3ITCR2 */
6364 /* XXX : not implemented */
6365 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6366 SPR_NOACCESS, SPR_NOACCESS,
6367 &spr_read_generic, &spr_write_generic,
6368 0x00000000);
6369 /* L3ITCR3 */
6370 /* XXX : not implemented */
6371 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6372 SPR_NOACCESS, SPR_NOACCESS,
6373 &spr_read_generic, &spr_write_generic,
6374 0x00000000);
6375 /* L3OHCR */
6376 /* XXX : not implemented */
6377 spr_register(env, SPR_L3OHCR, "L3OHCR",
6378 SPR_NOACCESS, SPR_NOACCESS,
6379 &spr_read_generic, &spr_write_generic,
6380 0x00000000);
6381 /* LDSTCR */
6382 /* XXX : not implemented */
6383 spr_register(env, SPR_LDSTCR, "LDSTCR",
6384 SPR_NOACCESS, SPR_NOACCESS,
6385 &spr_read_generic, &spr_write_generic,
6386 0x00000000);
6387 /* ICTRL */
6388 /* XXX : not implemented */
6389 spr_register(env, SPR_ICTRL, "ICTRL",
6390 SPR_NOACCESS, SPR_NOACCESS,
6391 &spr_read_generic, &spr_write_generic,
6392 0x00000000);
6393 /* MSSSR0 */
6394 /* XXX : not implemented */
6395 spr_register(env, SPR_MSSSR0, "MSSSR0",
6396 SPR_NOACCESS, SPR_NOACCESS,
6397 &spr_read_generic, &spr_write_generic,
6398 0x00000000);
6399 /* PMC */
6400 /* XXX : not implemented */
6401 spr_register(env, SPR_PMC5, "PMC5",
6402 SPR_NOACCESS, SPR_NOACCESS,
6403 &spr_read_generic, &spr_write_generic,
6404 0x00000000);
6405 /* XXX : not implemented */
6406 spr_register(env, SPR_UPMC5, "UPMC5",
6407 &spr_read_ureg, SPR_NOACCESS,
6408 &spr_read_ureg, SPR_NOACCESS,
6409 0x00000000);
6410 /* XXX : not implemented */
6411 spr_register(env, SPR_PMC6, "PMC6",
6412 SPR_NOACCESS, SPR_NOACCESS,
6413 &spr_read_generic, &spr_write_generic,
6414 0x00000000);
6415 /* XXX : not implemented */
6416 spr_register(env, SPR_UPMC6, "UPMC6",
6417 &spr_read_ureg, SPR_NOACCESS,
6418 &spr_read_ureg, SPR_NOACCESS,
6419 0x00000000);
6420 /* SPRGs */
6421 spr_register(env, SPR_SPRG4, "SPRG4",
6422 SPR_NOACCESS, SPR_NOACCESS,
6423 &spr_read_generic, &spr_write_generic,
6424 0x00000000);
6425 spr_register(env, SPR_USPRG4, "USPRG4",
6426 &spr_read_ureg, SPR_NOACCESS,
6427 &spr_read_ureg, SPR_NOACCESS,
6428 0x00000000);
6429 spr_register(env, SPR_SPRG5, "SPRG5",
6430 SPR_NOACCESS, SPR_NOACCESS,
6431 &spr_read_generic, &spr_write_generic,
6432 0x00000000);
6433 spr_register(env, SPR_USPRG5, "USPRG5",
6434 &spr_read_ureg, SPR_NOACCESS,
6435 &spr_read_ureg, SPR_NOACCESS,
6436 0x00000000);
6437 spr_register(env, SPR_SPRG6, "SPRG6",
6438 SPR_NOACCESS, SPR_NOACCESS,
6439 &spr_read_generic, &spr_write_generic,
6440 0x00000000);
6441 spr_register(env, SPR_USPRG6, "USPRG6",
6442 &spr_read_ureg, SPR_NOACCESS,
6443 &spr_read_ureg, SPR_NOACCESS,
6444 0x00000000);
6445 spr_register(env, SPR_SPRG7, "SPRG7",
6446 SPR_NOACCESS, SPR_NOACCESS,
6447 &spr_read_generic, &spr_write_generic,
6448 0x00000000);
6449 spr_register(env, SPR_USPRG7, "USPRG7",
6450 &spr_read_ureg, SPR_NOACCESS,
6451 &spr_read_ureg, SPR_NOACCESS,
6452 0x00000000);
6453 /* Memory management */
6454 gen_low_BATs(env);
6455 gen_high_BATs(env);
6456 gen_74xx_soft_tlb(env, 128, 2);
6457 init_excp_7450(env);
6458 env->dcache_line_size = 32;
6459 env->icache_line_size = 32;
6460 /* Allocate hardware IRQ controller */
6461 ppc6xx_irq_init(env);
6462 }
6463
6464 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
6465 {
6466 DeviceClass *dc = DEVICE_CLASS(oc);
6467 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6468
6469 dc->desc = "PowerPC 7457 (aka G4)";
6470 pcc->init_proc = init_proc_7457;
6471 pcc->check_pow = check_pow_hid0_74xx;
6472 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6473 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6474 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6475 PPC_FLOAT_STFIWX |
6476 PPC_CACHE | PPC_CACHE_ICBI |
6477 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6478 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6479 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6480 PPC_MEM_TLBIA | PPC_74xx_TLB |
6481 PPC_SEGMENT | PPC_EXTERN |
6482 PPC_ALTIVEC;
6483 pcc->insns_flags2 = PPC_NONE;
6484 pcc->msr_mask = 0x000000000205FF77ULL;
6485 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6486 pcc->excp_model = POWERPC_EXCP_74xx;
6487 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6488 pcc->bfd_mach = bfd_mach_ppc_7400;
6489 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6490 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6491 POWERPC_FLAG_BUS_CLK;
6492 }
6493
6494 #if defined (TARGET_PPC64)
6495 #if defined(CONFIG_USER_ONLY)
6496 #define POWERPC970_HID5_INIT 0x00000080
6497 #else
6498 #define POWERPC970_HID5_INIT 0x00000000
6499 #endif
6500
6501 static int check_pow_970 (CPUPPCState *env)
6502 {
6503 if (env->spr[SPR_HID0] & 0x00600000)
6504 return 1;
6505
6506 return 0;
6507 }
6508
6509 static void init_proc_970 (CPUPPCState *env)
6510 {
6511 gen_spr_ne_601(env);
6512 gen_spr_7xx(env);
6513 /* Time base */
6514 gen_tbl(env);
6515 /* Hardware implementation registers */
6516 /* XXX : not implemented */
6517 spr_register(env, SPR_HID0, "HID0",
6518 SPR_NOACCESS, SPR_NOACCESS,
6519 &spr_read_generic, &spr_write_clear,
6520 0x60000000);
6521 /* XXX : not implemented */
6522 spr_register(env, SPR_HID1, "HID1",
6523 SPR_NOACCESS, SPR_NOACCESS,
6524 &spr_read_generic, &spr_write_generic,
6525 0x00000000);
6526 /* XXX : not implemented */
6527 spr_register(env, SPR_750FX_HID2, "HID2",
6528 SPR_NOACCESS, SPR_NOACCESS,
6529 &spr_read_generic, &spr_write_generic,
6530 0x00000000);
6531 /* XXX : not implemented */
6532 spr_register(env, SPR_970_HID5, "HID5",
6533 SPR_NOACCESS, SPR_NOACCESS,
6534 &spr_read_generic, &spr_write_generic,
6535 POWERPC970_HID5_INIT);
6536 /* XXX : not implemented */
6537 spr_register(env, SPR_L2CR, "L2CR",
6538 SPR_NOACCESS, SPR_NOACCESS,
6539 &spr_read_generic, &spr_write_generic,
6540 0x00000000);
6541 /* Memory management */
6542 /* XXX: not correct */
6543 gen_low_BATs(env);
6544 /* XXX : not implemented */
6545 spr_register(env, SPR_MMUCFG, "MMUCFG",
6546 SPR_NOACCESS, SPR_NOACCESS,
6547 &spr_read_generic, SPR_NOACCESS,
6548 0x00000000); /* TOFIX */
6549 /* XXX : not implemented */
6550 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6551 SPR_NOACCESS, SPR_NOACCESS,
6552 &spr_read_generic, &spr_write_generic,
6553 0x00000000); /* TOFIX */
6554 spr_register(env, SPR_HIOR, "SPR_HIOR",
6555 SPR_NOACCESS, SPR_NOACCESS,
6556 &spr_read_hior, &spr_write_hior,
6557 0x00000000);
6558 #if !defined(CONFIG_USER_ONLY)
6559 env->slb_nr = 32;
6560 #endif
6561 init_excp_970(env);
6562 env->dcache_line_size = 128;
6563 env->icache_line_size = 128;
6564 /* Allocate hardware IRQ controller */
6565 ppc970_irq_init(env);
6566 /* Can't find information on what this should be on reset. This
6567 * value is the one used by 74xx processors. */
6568 vscr_init(env, 0x00010000);
6569 }
6570
6571 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
6572 {
6573 DeviceClass *dc = DEVICE_CLASS(oc);
6574 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6575
6576 dc->desc = "PowerPC 970";
6577 pcc->init_proc = init_proc_970;
6578 pcc->check_pow = check_pow_970;
6579 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6580 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6581 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6582 PPC_FLOAT_STFIWX |
6583 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6584 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6585 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6586 PPC_64B | PPC_ALTIVEC |
6587 PPC_SEGMENT_64B | PPC_SLBI;
6588 pcc->insns_flags2 = PPC_NONE;
6589 pcc->msr_mask = 0x900000000204FF36ULL;
6590 pcc->mmu_model = POWERPC_MMU_64B;
6591 #if defined(CONFIG_SOFTMMU)
6592 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
6593 #endif
6594 pcc->excp_model = POWERPC_EXCP_970;
6595 pcc->bus_model = PPC_FLAGS_INPUT_970;
6596 pcc->bfd_mach = bfd_mach_ppc64;
6597 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6598 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6599 POWERPC_FLAG_BUS_CLK;
6600 }
6601
6602 static int check_pow_970FX (CPUPPCState *env)
6603 {
6604 if (env->spr[SPR_HID0] & 0x00600000)
6605 return 1;
6606
6607 return 0;
6608 }
6609
6610 static void init_proc_970FX (CPUPPCState *env)
6611 {
6612 gen_spr_ne_601(env);
6613 gen_spr_7xx(env);
6614 /* Time base */
6615 gen_tbl(env);
6616 /* Hardware implementation registers */
6617 /* XXX : not implemented */
6618 spr_register(env, SPR_HID0, "HID0",
6619 SPR_NOACCESS, SPR_NOACCESS,
6620 &spr_read_generic, &spr_write_clear,
6621 0x60000000);
6622 /* XXX : not implemented */
6623 spr_register(env, SPR_HID1, "HID1",
6624 SPR_NOACCESS, SPR_NOACCESS,
6625 &spr_read_generic, &spr_write_generic,
6626 0x00000000);
6627 /* XXX : not implemented */
6628 spr_register(env, SPR_750FX_HID2, "HID2",
6629 SPR_NOACCESS, SPR_NOACCESS,
6630 &spr_read_generic, &spr_write_generic,
6631 0x00000000);
6632 /* XXX : not implemented */
6633 spr_register(env, SPR_970_HID5, "HID5",
6634 SPR_NOACCESS, SPR_NOACCESS,
6635 &spr_read_generic, &spr_write_generic,
6636 POWERPC970_HID5_INIT);
6637 /* XXX : not implemented */
6638 spr_register(env, SPR_L2CR, "L2CR",
6639 SPR_NOACCESS, SPR_NOACCESS,
6640 &spr_read_generic, &spr_write_generic,
6641 0x00000000);
6642 /* Memory management */
6643 /* XXX: not correct */
6644 gen_low_BATs(env);
6645 /* XXX : not implemented */
6646 spr_register(env, SPR_MMUCFG, "MMUCFG",
6647 SPR_NOACCESS, SPR_NOACCESS,
6648 &spr_read_generic, SPR_NOACCESS,
6649 0x00000000); /* TOFIX */
6650 /* XXX : not implemented */
6651 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6652 SPR_NOACCESS, SPR_NOACCESS,
6653 &spr_read_generic, &spr_write_generic,
6654 0x00000000); /* TOFIX */
6655 spr_register(env, SPR_HIOR, "SPR_HIOR",
6656 SPR_NOACCESS, SPR_NOACCESS,
6657 &spr_read_hior, &spr_write_hior,
6658 0x00000000);
6659 spr_register(env, SPR_CTRL, "SPR_CTRL",
6660 SPR_NOACCESS, SPR_NOACCESS,
6661 &spr_read_generic, &spr_write_generic,
6662 0x00000000);
6663 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6664 SPR_NOACCESS, SPR_NOACCESS,
6665 &spr_read_generic, &spr_write_generic,
6666 0x00000000);
6667 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6668 &spr_read_generic, &spr_write_generic,
6669 &spr_read_generic, &spr_write_generic,
6670 0x00000000);
6671 #if !defined(CONFIG_USER_ONLY)
6672 env->slb_nr = 64;
6673 #endif
6674 init_excp_970(env);
6675 env->dcache_line_size = 128;
6676 env->icache_line_size = 128;
6677 /* Allocate hardware IRQ controller */
6678 ppc970_irq_init(env);
6679 /* Can't find information on what this should be on reset. This
6680 * value is the one used by 74xx processors. */
6681 vscr_init(env, 0x00010000);
6682 }
6683
6684 POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
6685 {
6686 DeviceClass *dc = DEVICE_CLASS(oc);
6687 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6688
6689 dc->desc = "PowerPC 970FX (aka G5)";
6690 pcc->init_proc = init_proc_970FX;
6691 pcc->check_pow = check_pow_970FX;
6692 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6693 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6694 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6695 PPC_FLOAT_STFIWX |
6696 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6697 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6698 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6699 PPC_64B | PPC_ALTIVEC |
6700 PPC_SEGMENT_64B | PPC_SLBI;
6701 pcc->insns_flags2 = PPC_NONE;
6702 pcc->msr_mask = 0x800000000204FF36ULL;
6703 pcc->mmu_model = POWERPC_MMU_64B;
6704 #if defined(CONFIG_SOFTMMU)
6705 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
6706 #endif
6707 pcc->excp_model = POWERPC_EXCP_970;
6708 pcc->bus_model = PPC_FLAGS_INPUT_970;
6709 pcc->bfd_mach = bfd_mach_ppc64;
6710 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6711 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6712 POWERPC_FLAG_BUS_CLK;
6713 }
6714
6715 static int check_pow_970GX (CPUPPCState *env)
6716 {
6717 if (env->spr[SPR_HID0] & 0x00600000)
6718 return 1;
6719
6720 return 0;
6721 }
6722
6723 static void init_proc_970GX (CPUPPCState *env)
6724 {
6725 gen_spr_ne_601(env);
6726 gen_spr_7xx(env);
6727 /* Time base */
6728 gen_tbl(env);
6729 /* Hardware implementation registers */
6730 /* XXX : not implemented */
6731 spr_register(env, SPR_HID0, "HID0",
6732 SPR_NOACCESS, SPR_NOACCESS,
6733 &spr_read_generic, &spr_write_clear,
6734 0x60000000);
6735 /* XXX : not implemented */
6736 spr_register(env, SPR_HID1, "HID1",
6737 SPR_NOACCESS, SPR_NOACCESS,
6738 &spr_read_generic, &spr_write_generic,
6739 0x00000000);
6740 /* XXX : not implemented */
6741 spr_register(env, SPR_750FX_HID2, "HID2",
6742 SPR_NOACCESS, SPR_NOACCESS,
6743 &spr_read_generic, &spr_write_generic,
6744 0x00000000);
6745 /* XXX : not implemented */
6746 spr_register(env, SPR_970_HID5, "HID5",
6747 SPR_NOACCESS, SPR_NOACCESS,
6748 &spr_read_generic, &spr_write_generic,
6749 POWERPC970_HID5_INIT);
6750 /* XXX : not implemented */
6751 spr_register(env, SPR_L2CR, "L2CR",
6752 SPR_NOACCESS, SPR_NOACCESS,
6753 &spr_read_generic, &spr_write_generic,
6754 0x00000000);
6755 /* Memory management */
6756 /* XXX: not correct */
6757 gen_low_BATs(env);
6758 /* XXX : not implemented */
6759 spr_register(env, SPR_MMUCFG, "MMUCFG",
6760 SPR_NOACCESS, SPR_NOACCESS,
6761 &spr_read_generic, SPR_NOACCESS,
6762 0x00000000); /* TOFIX */
6763 /* XXX : not implemented */
6764 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6765 SPR_NOACCESS, SPR_NOACCESS,
6766 &spr_read_generic, &spr_write_generic,
6767 0x00000000); /* TOFIX */
6768 spr_register(env, SPR_HIOR, "SPR_HIOR",
6769 SPR_NOACCESS, SPR_NOACCESS,
6770 &spr_read_hior, &spr_write_hior,
6771 0x00000000);
6772 #if !defined(CONFIG_USER_ONLY)
6773 env->slb_nr = 32;
6774 #endif
6775 init_excp_970(env);
6776 env->dcache_line_size = 128;
6777 env->icache_line_size = 128;
6778 /* Allocate hardware IRQ controller */
6779 ppc970_irq_init(env);
6780 /* Can't find information on what this should be on reset. This
6781 * value is the one used by 74xx processors. */
6782 vscr_init(env, 0x00010000);
6783 }
6784
6785 POWERPC_FAMILY(970GX)(ObjectClass *oc, void *data)
6786 {
6787 DeviceClass *dc = DEVICE_CLASS(oc);
6788 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6789
6790 dc->desc = "PowerPC 970 GX";
6791 pcc->init_proc = init_proc_970GX;
6792 pcc->check_pow = check_pow_970GX;
6793 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6794 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6795 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6796 PPC_FLOAT_STFIWX |
6797 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6798 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6799 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6800 PPC_64B | PPC_ALTIVEC |
6801 PPC_SEGMENT_64B | PPC_SLBI;
6802 pcc->insns_flags2 = PPC_NONE;
6803 pcc->msr_mask = 0x800000000204FF36ULL;
6804 pcc->mmu_model = POWERPC_MMU_64B;
6805 #if defined(CONFIG_SOFTMMU)
6806 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
6807 #endif
6808 pcc->excp_model = POWERPC_EXCP_970;
6809 pcc->bus_model = PPC_FLAGS_INPUT_970;
6810 pcc->bfd_mach = bfd_mach_ppc64;
6811 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6812 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6813 POWERPC_FLAG_BUS_CLK;
6814 }
6815
6816 static int check_pow_970MP (CPUPPCState *env)
6817 {
6818 if (env->spr[SPR_HID0] & 0x01C00000)
6819 return 1;
6820
6821 return 0;
6822 }
6823
6824 static void init_proc_970MP (CPUPPCState *env)
6825 {
6826 gen_spr_ne_601(env);
6827 gen_spr_7xx(env);
6828 /* Time base */
6829 gen_tbl(env);
6830 /* Hardware implementation registers */
6831 /* XXX : not implemented */
6832 spr_register(env, SPR_HID0, "HID0",
6833 SPR_NOACCESS, SPR_NOACCESS,
6834 &spr_read_generic, &spr_write_clear,
6835 0x60000000);
6836 /* XXX : not implemented */
6837 spr_register(env, SPR_HID1, "HID1",
6838 SPR_NOACCESS, SPR_NOACCESS,
6839 &spr_read_generic, &spr_write_generic,
6840 0x00000000);
6841 /* XXX : not implemented */
6842 spr_register(env, SPR_750FX_HID2, "HID2",
6843 SPR_NOACCESS, SPR_NOACCESS,
6844 &spr_read_generic, &spr_write_generic,
6845 0x00000000);
6846 /* XXX : not implemented */
6847 spr_register(env, SPR_970_HID5, "HID5",
6848 SPR_NOACCESS, SPR_NOACCESS,
6849 &spr_read_generic, &spr_write_generic,
6850 POWERPC970_HID5_INIT);
6851 /* XXX : not implemented */
6852 spr_register(env, SPR_L2CR, "L2CR",
6853 SPR_NOACCESS, SPR_NOACCESS,
6854 &spr_read_generic, &spr_write_generic,
6855 0x00000000);
6856 /* Memory management */
6857 /* XXX: not correct */
6858 gen_low_BATs(env);
6859 /* XXX : not implemented */
6860 spr_register(env, SPR_MMUCFG, "MMUCFG",
6861 SPR_NOACCESS, SPR_NOACCESS,
6862 &spr_read_generic, SPR_NOACCESS,
6863 0x00000000); /* TOFIX */
6864 /* XXX : not implemented */
6865 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6866 SPR_NOACCESS, SPR_NOACCESS,
6867 &spr_read_generic, &spr_write_generic,
6868 0x00000000); /* TOFIX */
6869 spr_register(env, SPR_HIOR, "SPR_HIOR",
6870 SPR_NOACCESS, SPR_NOACCESS,
6871 &spr_read_hior, &spr_write_hior,
6872 0x00000000);
6873 #if !defined(CONFIG_USER_ONLY)
6874 env->slb_nr = 32;
6875 #endif
6876 init_excp_970(env);
6877 env->dcache_line_size = 128;
6878 env->icache_line_size = 128;
6879 /* Allocate hardware IRQ controller */
6880 ppc970_irq_init(env);
6881 /* Can't find information on what this should be on reset. This
6882 * value is the one used by 74xx processors. */
6883 vscr_init(env, 0x00010000);
6884 }
6885
6886 POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
6887 {
6888 DeviceClass *dc = DEVICE_CLASS(oc);
6889 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6890
6891 dc->desc = "PowerPC 970 MP";
6892 pcc->init_proc = init_proc_970MP;
6893 pcc->check_pow = check_pow_970MP;
6894 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6895 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6896 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6897 PPC_FLOAT_STFIWX |
6898 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6899 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6900 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6901 PPC_64B | PPC_ALTIVEC |
6902 PPC_SEGMENT_64B | PPC_SLBI;
6903 pcc->insns_flags2 = PPC_NONE;
6904 pcc->msr_mask = 0x900000000204FF36ULL;
6905 pcc->mmu_model = POWERPC_MMU_64B;
6906 #if defined(CONFIG_SOFTMMU)
6907 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
6908 #endif
6909 pcc->excp_model = POWERPC_EXCP_970;
6910 pcc->bus_model = PPC_FLAGS_INPUT_970;
6911 pcc->bfd_mach = bfd_mach_ppc64;
6912 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6913 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6914 POWERPC_FLAG_BUS_CLK;
6915 }
6916
6917 static void init_proc_POWER7 (CPUPPCState *env)
6918 {
6919 gen_spr_ne_601(env);
6920 gen_spr_7xx(env);
6921 /* Time base */
6922 gen_tbl(env);
6923 /* Processor identification */
6924 spr_register(env, SPR_PIR, "PIR",
6925 SPR_NOACCESS, SPR_NOACCESS,
6926 &spr_read_generic, &spr_write_pir,
6927 0x00000000);
6928 #if !defined(CONFIG_USER_ONLY)
6929 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6930 spr_register_kvm(env, SPR_PURR, "PURR",
6931 &spr_read_purr, SPR_NOACCESS,
6932 &spr_read_purr, SPR_NOACCESS,
6933 KVM_REG_PPC_PURR, 0x00000000);
6934 spr_register_kvm(env, SPR_SPURR, "SPURR",
6935 &spr_read_purr, SPR_NOACCESS,
6936 &spr_read_purr, SPR_NOACCESS,
6937 KVM_REG_PPC_SPURR, 0x00000000);
6938 spr_register(env, SPR_CFAR, "SPR_CFAR",
6939 SPR_NOACCESS, SPR_NOACCESS,
6940 &spr_read_cfar, &spr_write_cfar,
6941 0x00000000);
6942 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
6943 SPR_NOACCESS, SPR_NOACCESS,
6944 &spr_read_generic, &spr_write_generic,
6945 KVM_REG_PPC_DSCR, 0x00000000);
6946 #endif /* !CONFIG_USER_ONLY */
6947 /* Memory management */
6948 /* XXX : not implemented */
6949 spr_register(env, SPR_MMUCFG, "MMUCFG",
6950 SPR_NOACCESS, SPR_NOACCESS,
6951 &spr_read_generic, SPR_NOACCESS,
6952 0x00000000); /* TOFIX */
6953 gen_spr_amr(env);
6954 /* XXX : not implemented */
6955 spr_register(env, SPR_CTRL, "SPR_CTRLT",
6956 SPR_NOACCESS, SPR_NOACCESS,
6957 &spr_read_generic, &spr_write_generic,
6958 0x80800000);
6959 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
6960 SPR_NOACCESS, SPR_NOACCESS,
6961 &spr_read_generic, &spr_write_generic,
6962 0x80800000);
6963 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6964 &spr_read_generic, &spr_write_generic,
6965 &spr_read_generic, &spr_write_generic,
6966 0x00000000);
6967 #if !defined(CONFIG_USER_ONLY)
6968 env->slb_nr = 32;
6969 #endif
6970 init_excp_POWER7(env);
6971 env->dcache_line_size = 128;
6972 env->icache_line_size = 128;
6973 /* Allocate hardware IRQ controller */
6974 ppcPOWER7_irq_init(env);
6975 /* Can't find information on what this should be on reset. This
6976 * value is the one used by 74xx processors. */
6977 vscr_init(env, 0x00010000);
6978 }
6979
6980 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
6981 {
6982 DeviceClass *dc = DEVICE_CLASS(oc);
6983 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6984
6985 dc->desc = "POWER7";
6986 pcc->init_proc = init_proc_POWER7;
6987 pcc->check_pow = check_pow_nocheck;
6988 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6989 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6990 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6991 PPC_FLOAT_STFIWX |
6992 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6993 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6994 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6995 PPC_64B | PPC_ALTIVEC |
6996 PPC_SEGMENT_64B | PPC_SLBI |
6997 PPC_POPCNTB | PPC_POPCNTWD;
6998 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX;
6999 pcc->msr_mask = 0x800000000204FF36ULL;
7000 pcc->mmu_model = POWERPC_MMU_2_06;
7001 #if defined(CONFIG_SOFTMMU)
7002 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7003 #endif
7004 pcc->excp_model = POWERPC_EXCP_POWER7;
7005 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7006 pcc->bfd_mach = bfd_mach_ppc64;
7007 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7008 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7009 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR;
7010 }
7011 #endif /* defined (TARGET_PPC64) */
7012
7013
7014 /*****************************************************************************/
7015 /* Generic CPU instantiation routine */
7016 static void init_ppc_proc(PowerPCCPU *cpu)
7017 {
7018 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7019 CPUPPCState *env = &cpu->env;
7020 #if !defined(CONFIG_USER_ONLY)
7021 int i;
7022
7023 env->irq_inputs = NULL;
7024 /* Set all exception vectors to an invalid address */
7025 for (i = 0; i < POWERPC_EXCP_NB; i++)
7026 env->excp_vectors[i] = (target_ulong)(-1ULL);
7027 env->ivor_mask = 0x00000000;
7028 env->ivpr_mask = 0x00000000;
7029 /* Default MMU definitions */
7030 env->nb_BATs = 0;
7031 env->nb_tlb = 0;
7032 env->nb_ways = 0;
7033 env->tlb_type = TLB_NONE;
7034 #endif
7035 /* Register SPR common to all PowerPC implementations */
7036 gen_spr_generic(env);
7037 spr_register(env, SPR_PVR, "PVR",
7038 /* Linux permits userspace to read PVR */
7039 #if defined(CONFIG_LINUX_USER)
7040 &spr_read_generic,
7041 #else
7042 SPR_NOACCESS,
7043 #endif
7044 SPR_NOACCESS,
7045 &spr_read_generic, SPR_NOACCESS,
7046 pcc->pvr);
7047 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
7048 if (pcc->svr != POWERPC_SVR_NONE) {
7049 if (pcc->svr & POWERPC_SVR_E500) {
7050 spr_register(env, SPR_E500_SVR, "SVR",
7051 SPR_NOACCESS, SPR_NOACCESS,
7052 &spr_read_generic, SPR_NOACCESS,
7053 pcc->svr & ~POWERPC_SVR_E500);
7054 } else {
7055 spr_register(env, SPR_SVR, "SVR",
7056 SPR_NOACCESS, SPR_NOACCESS,
7057 &spr_read_generic, SPR_NOACCESS,
7058 pcc->svr);
7059 }
7060 }
7061 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
7062 (*pcc->init_proc)(env);
7063
7064 /* MSR bits & flags consistency checks */
7065 if (env->msr_mask & (1 << 25)) {
7066 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7067 case POWERPC_FLAG_SPE:
7068 case POWERPC_FLAG_VRE:
7069 break;
7070 default:
7071 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7072 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
7073 exit(1);
7074 }
7075 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7076 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7077 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
7078 exit(1);
7079 }
7080 if (env->msr_mask & (1 << 17)) {
7081 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7082 case POWERPC_FLAG_TGPR:
7083 case POWERPC_FLAG_CE:
7084 break;
7085 default:
7086 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7087 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
7088 exit(1);
7089 }
7090 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7091 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7092 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
7093 exit(1);
7094 }
7095 if (env->msr_mask & (1 << 10)) {
7096 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7097 POWERPC_FLAG_UBLE)) {
7098 case POWERPC_FLAG_SE:
7099 case POWERPC_FLAG_DWE:
7100 case POWERPC_FLAG_UBLE:
7101 break;
7102 default:
7103 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7104 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
7105 "POWERPC_FLAG_UBLE\n");
7106 exit(1);
7107 }
7108 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7109 POWERPC_FLAG_UBLE)) {
7110 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7111 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
7112 "POWERPC_FLAG_UBLE\n");
7113 exit(1);
7114 }
7115 if (env->msr_mask & (1 << 9)) {
7116 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7117 case POWERPC_FLAG_BE:
7118 case POWERPC_FLAG_DE:
7119 break;
7120 default:
7121 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7122 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
7123 exit(1);
7124 }
7125 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7126 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7127 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
7128 exit(1);
7129 }
7130 if (env->msr_mask & (1 << 2)) {
7131 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7132 case POWERPC_FLAG_PX:
7133 case POWERPC_FLAG_PMM:
7134 break;
7135 default:
7136 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7137 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
7138 exit(1);
7139 }
7140 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7141 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7142 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
7143 exit(1);
7144 }
7145 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
7146 fprintf(stderr, "PowerPC flags inconsistency\n"
7147 "Should define the time-base and decrementer clock source\n");
7148 exit(1);
7149 }
7150 /* Allocate TLBs buffer when needed */
7151 #if !defined(CONFIG_USER_ONLY)
7152 if (env->nb_tlb != 0) {
7153 int nb_tlb = env->nb_tlb;
7154 if (env->id_tlbs != 0)
7155 nb_tlb *= 2;
7156 switch (env->tlb_type) {
7157 case TLB_6XX:
7158 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
7159 break;
7160 case TLB_EMB:
7161 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
7162 break;
7163 case TLB_MAS:
7164 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
7165 break;
7166 }
7167 /* Pre-compute some useful values */
7168 env->tlb_per_way = env->nb_tlb / env->nb_ways;
7169 }
7170 if (env->irq_inputs == NULL) {
7171 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
7172 " Attempt QEMU to crash very soon !\n");
7173 }
7174 #endif
7175 if (env->check_pow == NULL) {
7176 fprintf(stderr, "WARNING: no power management check handler "
7177 "registered.\n"
7178 " Attempt QEMU to crash very soon !\n");
7179 }
7180 }
7181
7182 #if defined(PPC_DUMP_CPU)
7183 static void dump_ppc_sprs (CPUPPCState *env)
7184 {
7185 ppc_spr_t *spr;
7186 #if !defined(CONFIG_USER_ONLY)
7187 uint32_t sr, sw;
7188 #endif
7189 uint32_t ur, uw;
7190 int i, j, n;
7191
7192 printf("Special purpose registers:\n");
7193 for (i = 0; i < 32; i++) {
7194 for (j = 0; j < 32; j++) {
7195 n = (i << 5) | j;
7196 spr = &env->spr_cb[n];
7197 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
7198 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
7199 #if !defined(CONFIG_USER_ONLY)
7200 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
7201 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
7202 if (sw || sr || uw || ur) {
7203 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
7204 (i << 5) | j, (i << 5) | j, spr->name,
7205 sw ? 'w' : '-', sr ? 'r' : '-',
7206 uw ? 'w' : '-', ur ? 'r' : '-');
7207 }
7208 #else
7209 if (uw || ur) {
7210 printf("SPR: %4d (%03x) %-8s u%c%c\n",
7211 (i << 5) | j, (i << 5) | j, spr->name,
7212 uw ? 'w' : '-', ur ? 'r' : '-');
7213 }
7214 #endif
7215 }
7216 }
7217 fflush(stdout);
7218 fflush(stderr);
7219 }
7220 #endif
7221
7222 /*****************************************************************************/
7223 #include <stdlib.h>
7224 #include <string.h>
7225
7226 /* Opcode types */
7227 enum {
7228 PPC_DIRECT = 0, /* Opcode routine */
7229 PPC_INDIRECT = 1, /* Indirect opcode table */
7230 };
7231
7232 static inline int is_indirect_opcode (void *handler)
7233 {
7234 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
7235 }
7236
7237 static inline opc_handler_t **ind_table(void *handler)
7238 {
7239 return (opc_handler_t **)((uintptr_t)handler & ~3);
7240 }
7241
7242 /* Instruction table creation */
7243 /* Opcodes tables creation */
7244 static void fill_new_table (opc_handler_t **table, int len)
7245 {
7246 int i;
7247
7248 for (i = 0; i < len; i++)
7249 table[i] = &invalid_handler;
7250 }
7251
7252 static int create_new_table (opc_handler_t **table, unsigned char idx)
7253 {
7254 opc_handler_t **tmp;
7255
7256 tmp = malloc(0x20 * sizeof(opc_handler_t));
7257 fill_new_table(tmp, 0x20);
7258 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
7259
7260 return 0;
7261 }
7262
7263 static int insert_in_table (opc_handler_t **table, unsigned char idx,
7264 opc_handler_t *handler)
7265 {
7266 if (table[idx] != &invalid_handler)
7267 return -1;
7268 table[idx] = handler;
7269
7270 return 0;
7271 }
7272
7273 static int register_direct_insn (opc_handler_t **ppc_opcodes,
7274 unsigned char idx, opc_handler_t *handler)
7275 {
7276 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
7277 printf("*** ERROR: opcode %02x already assigned in main "
7278 "opcode table\n", idx);
7279 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7280 printf(" Registered handler '%s' - new handler '%s'\n",
7281 ppc_opcodes[idx]->oname, handler->oname);
7282 #endif
7283 return -1;
7284 }
7285
7286 return 0;
7287 }
7288
7289 static int register_ind_in_table (opc_handler_t **table,
7290 unsigned char idx1, unsigned char idx2,
7291 opc_handler_t *handler)
7292 {
7293 if (table[idx1] == &invalid_handler) {
7294 if (create_new_table(table, idx1) < 0) {
7295 printf("*** ERROR: unable to create indirect table "
7296 "idx=%02x\n", idx1);
7297 return -1;
7298 }
7299 } else {
7300 if (!is_indirect_opcode(table[idx1])) {
7301 printf("*** ERROR: idx %02x already assigned to a direct "
7302 "opcode\n", idx1);
7303 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7304 printf(" Registered handler '%s' - new handler '%s'\n",
7305 ind_table(table[idx1])[idx2]->oname, handler->oname);
7306 #endif
7307 return -1;
7308 }
7309 }
7310 if (handler != NULL &&
7311 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
7312 printf("*** ERROR: opcode %02x already assigned in "
7313 "opcode table %02x\n", idx2, idx1);
7314 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7315 printf(" Registered handler '%s' - new handler '%s'\n",
7316 ind_table(table[idx1])[idx2]->oname, handler->oname);
7317 #endif
7318 return -1;
7319 }
7320
7321 return 0;
7322 }
7323
7324 static int register_ind_insn (opc_handler_t **ppc_opcodes,
7325 unsigned char idx1, unsigned char idx2,
7326 opc_handler_t *handler)
7327 {
7328 int ret;
7329
7330 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
7331
7332 return ret;
7333 }
7334
7335 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
7336 unsigned char idx1, unsigned char idx2,
7337 unsigned char idx3, opc_handler_t *handler)
7338 {
7339 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
7340 printf("*** ERROR: unable to join indirect table idx "
7341 "[%02x-%02x]\n", idx1, idx2);
7342 return -1;
7343 }
7344 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
7345 handler) < 0) {
7346 printf("*** ERROR: unable to insert opcode "
7347 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
7348 return -1;
7349 }
7350
7351 return 0;
7352 }
7353
7354 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
7355 {
7356 if (insn->opc2 != 0xFF) {
7357 if (insn->opc3 != 0xFF) {
7358 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
7359 insn->opc3, &insn->handler) < 0)
7360 return -1;
7361 } else {
7362 if (register_ind_insn(ppc_opcodes, insn->opc1,
7363 insn->opc2, &insn->handler) < 0)
7364 return -1;
7365 }
7366 } else {
7367 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
7368 return -1;
7369 }
7370
7371 return 0;
7372 }
7373
7374 static int test_opcode_table (opc_handler_t **table, int len)
7375 {
7376 int i, count, tmp;
7377
7378 for (i = 0, count = 0; i < len; i++) {
7379 /* Consistency fixup */
7380 if (table[i] == NULL)
7381 table[i] = &invalid_handler;
7382 if (table[i] != &invalid_handler) {
7383 if (is_indirect_opcode(table[i])) {
7384 tmp = test_opcode_table(ind_table(table[i]), 0x20);
7385 if (tmp == 0) {
7386 free(table[i]);
7387 table[i] = &invalid_handler;
7388 } else {
7389 count++;
7390 }
7391 } else {
7392 count++;
7393 }
7394 }
7395 }
7396
7397 return count;
7398 }
7399
7400 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
7401 {
7402 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
7403 printf("*** WARNING: no opcode defined !\n");
7404 }
7405
7406 /*****************************************************************************/
7407 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
7408 {
7409 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7410 CPUPPCState *env = &cpu->env;
7411 opcode_t *opc;
7412
7413 fill_new_table(env->opcodes, 0x40);
7414 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
7415 if (((opc->handler.type & pcc->insns_flags) != 0) ||
7416 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
7417 if (register_insn(env->opcodes, opc) < 0) {
7418 error_setg(errp, "ERROR initializing PowerPC instruction "
7419 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
7420 opc->opc3);
7421 return;
7422 }
7423 }
7424 }
7425 fix_opcode_tables(env->opcodes);
7426 fflush(stdout);
7427 fflush(stderr);
7428 }
7429
7430 #if defined(PPC_DUMP_CPU)
7431 static void dump_ppc_insns (CPUPPCState *env)
7432 {
7433 opc_handler_t **table, *handler;
7434 const char *p, *q;
7435 uint8_t opc1, opc2, opc3;
7436
7437 printf("Instructions set:\n");
7438 /* opc1 is 6 bits long */
7439 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
7440 table = env->opcodes;
7441 handler = table[opc1];
7442 if (is_indirect_opcode(handler)) {
7443 /* opc2 is 5 bits long */
7444 for (opc2 = 0; opc2 < 0x20; opc2++) {
7445 table = env->opcodes;
7446 handler = env->opcodes[opc1];
7447 table = ind_table(handler);
7448 handler = table[opc2];
7449 if (is_indirect_opcode(handler)) {
7450 table = ind_table(handler);
7451 /* opc3 is 5 bits long */
7452 for (opc3 = 0; opc3 < 0x20; opc3++) {
7453 handler = table[opc3];
7454 if (handler->handler != &gen_invalid) {
7455 /* Special hack to properly dump SPE insns */
7456 p = strchr(handler->oname, '_');
7457 if (p == NULL) {
7458 printf("INSN: %02x %02x %02x (%02d %04d) : "
7459 "%s\n",
7460 opc1, opc2, opc3, opc1,
7461 (opc3 << 5) | opc2,
7462 handler->oname);
7463 } else {
7464 q = "speundef";
7465 if ((p - handler->oname) != strlen(q) ||
7466 memcmp(handler->oname, q, strlen(q)) != 0) {
7467 /* First instruction */
7468 printf("INSN: %02x %02x %02x (%02d %04d) : "
7469 "%.*s\n",
7470 opc1, opc2 << 1, opc3, opc1,
7471 (opc3 << 6) | (opc2 << 1),
7472 (int)(p - handler->oname),
7473 handler->oname);
7474 }
7475 if (strcmp(p + 1, q) != 0) {
7476 /* Second instruction */
7477 printf("INSN: %02x %02x %02x (%02d %04d) : "
7478 "%s\n",
7479 opc1, (opc2 << 1) | 1, opc3, opc1,
7480 (opc3 << 6) | (opc2 << 1) | 1,
7481 p + 1);
7482 }
7483 }
7484 }
7485 }
7486 } else {
7487 if (handler->handler != &gen_invalid) {
7488 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
7489 opc1, opc2, opc1, opc2, handler->oname);
7490 }
7491 }
7492 }
7493 } else {
7494 if (handler->handler != &gen_invalid) {
7495 printf("INSN: %02x -- -- (%02d ----) : %s\n",
7496 opc1, opc1, handler->oname);
7497 }
7498 }
7499 }
7500 }
7501 #endif
7502
7503 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7504 {
7505 if (n < 32) {
7506 stfq_p(mem_buf, env->fpr[n]);
7507 return 8;
7508 }
7509 if (n == 32) {
7510 stl_p(mem_buf, env->fpscr);
7511 return 4;
7512 }
7513 return 0;
7514 }
7515
7516 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7517 {
7518 if (n < 32) {
7519 env->fpr[n] = ldfq_p(mem_buf);
7520 return 8;
7521 }
7522 if (n == 32) {
7523 helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
7524 return 4;
7525 }
7526 return 0;
7527 }
7528
7529 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7530 {
7531 if (n < 32) {
7532 #ifdef HOST_WORDS_BIGENDIAN
7533 stq_p(mem_buf, env->avr[n].u64[0]);
7534 stq_p(mem_buf+8, env->avr[n].u64[1]);
7535 #else
7536 stq_p(mem_buf, env->avr[n].u64[1]);
7537 stq_p(mem_buf+8, env->avr[n].u64[0]);
7538 #endif
7539 return 16;
7540 }
7541 if (n == 32) {
7542 stl_p(mem_buf, env->vscr);
7543 return 4;
7544 }
7545 if (n == 33) {
7546 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
7547 return 4;
7548 }
7549 return 0;
7550 }
7551
7552 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7553 {
7554 if (n < 32) {
7555 #ifdef HOST_WORDS_BIGENDIAN
7556 env->avr[n].u64[0] = ldq_p(mem_buf);
7557 env->avr[n].u64[1] = ldq_p(mem_buf+8);
7558 #else
7559 env->avr[n].u64[1] = ldq_p(mem_buf);
7560 env->avr[n].u64[0] = ldq_p(mem_buf+8);
7561 #endif
7562 return 16;
7563 }
7564 if (n == 32) {
7565 env->vscr = ldl_p(mem_buf);
7566 return 4;
7567 }
7568 if (n == 33) {
7569 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
7570 return 4;
7571 }
7572 return 0;
7573 }
7574
7575 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7576 {
7577 if (n < 32) {
7578 #if defined(TARGET_PPC64)
7579 stl_p(mem_buf, env->gpr[n] >> 32);
7580 #else
7581 stl_p(mem_buf, env->gprh[n]);
7582 #endif
7583 return 4;
7584 }
7585 if (n == 32) {
7586 stq_p(mem_buf, env->spe_acc);
7587 return 8;
7588 }
7589 if (n == 33) {
7590 stl_p(mem_buf, env->spe_fscr);
7591 return 4;
7592 }
7593 return 0;
7594 }
7595
7596 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7597 {
7598 if (n < 32) {
7599 #if defined(TARGET_PPC64)
7600 target_ulong lo = (uint32_t)env->gpr[n];
7601 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
7602 env->gpr[n] = lo | hi;
7603 #else
7604 env->gprh[n] = ldl_p(mem_buf);
7605 #endif
7606 return 4;
7607 }
7608 if (n == 32) {
7609 env->spe_acc = ldq_p(mem_buf);
7610 return 8;
7611 }
7612 if (n == 33) {
7613 env->spe_fscr = ldl_p(mem_buf);
7614 return 4;
7615 }
7616 return 0;
7617 }
7618
7619 static int ppc_fixup_cpu(PowerPCCPU *cpu)
7620 {
7621 CPUPPCState *env = &cpu->env;
7622
7623 /* TCG doesn't (yet) emulate some groups of instructions that
7624 * are implemented on some otherwise supported CPUs (e.g. VSX
7625 * and decimal floating point instructions on POWER7). We
7626 * remove unsupported instruction groups from the cpu state's
7627 * instruction masks and hope the guest can cope. For at
7628 * least the pseries machine, the unavailability of these
7629 * instructions can be advertised to the guest via the device
7630 * tree. */
7631 if ((env->insns_flags & ~PPC_TCG_INSNS)
7632 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
7633 fprintf(stderr, "Warning: Disabling some instructions which are not "
7634 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
7635 env->insns_flags & ~PPC_TCG_INSNS,
7636 env->insns_flags2 & ~PPC_TCG_INSNS2);
7637 }
7638 env->insns_flags &= PPC_TCG_INSNS;
7639 env->insns_flags2 &= PPC_TCG_INSNS2;
7640 return 0;
7641 }
7642
7643 static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
7644 {
7645 PowerPCCPU *cpu = POWERPC_CPU(dev);
7646 CPUPPCState *env = &cpu->env;
7647 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7648 Error *local_err = NULL;
7649 #if !defined(CONFIG_USER_ONLY)
7650 int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
7651 #endif
7652
7653 #if !defined(CONFIG_USER_ONLY)
7654 if (smp_threads > max_smt) {
7655 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
7656 max_smt, kvm_enabled() ? "KVM" : "TCG");
7657 return;
7658 }
7659 #endif
7660
7661 if (kvm_enabled()) {
7662 if (kvmppc_fixup_cpu(cpu) != 0) {
7663 error_setg(errp, "Unable to virtualize selected CPU with KVM");
7664 return;
7665 }
7666 } else {
7667 if (ppc_fixup_cpu(cpu) != 0) {
7668 error_setg(errp, "Unable to emulate selected CPU with TCG");
7669 return;
7670 }
7671 }
7672
7673 #if defined(TARGET_PPCEMB)
7674 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
7675 error_setg(errp, "CPU does not possess a BookE MMU. "
7676 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
7677 "or choose another CPU model.");
7678 return;
7679 }
7680 #endif
7681
7682 create_ppc_opcodes(cpu, &local_err);
7683 if (local_err != NULL) {
7684 error_propagate(errp, local_err);
7685 return;
7686 }
7687 init_ppc_proc(cpu);
7688
7689 if (pcc->insns_flags & PPC_FLOAT) {
7690 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
7691 33, "power-fpu.xml", 0);
7692 }
7693 if (pcc->insns_flags & PPC_ALTIVEC) {
7694 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
7695 34, "power-altivec.xml", 0);
7696 }
7697 if (pcc->insns_flags & PPC_SPE) {
7698 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
7699 34, "power-spe.xml", 0);
7700 }
7701
7702 qemu_init_vcpu(env);
7703
7704 pcc->parent_realize(dev, errp);
7705
7706 #if defined(PPC_DUMP_CPU)
7707 {
7708 const char *mmu_model, *excp_model, *bus_model;
7709 switch (env->mmu_model) {
7710 case POWERPC_MMU_32B:
7711 mmu_model = "PowerPC 32";
7712 break;
7713 case POWERPC_MMU_SOFT_6xx:
7714 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
7715 break;
7716 case POWERPC_MMU_SOFT_74xx:
7717 mmu_model = "PowerPC 74xx with software driven TLBs";
7718 break;
7719 case POWERPC_MMU_SOFT_4xx:
7720 mmu_model = "PowerPC 4xx with software driven TLBs";
7721 break;
7722 case POWERPC_MMU_SOFT_4xx_Z:
7723 mmu_model = "PowerPC 4xx with software driven TLBs "
7724 "and zones protections";
7725 break;
7726 case POWERPC_MMU_REAL:
7727 mmu_model = "PowerPC real mode only";
7728 break;
7729 case POWERPC_MMU_MPC8xx:
7730 mmu_model = "PowerPC MPC8xx";
7731 break;
7732 case POWERPC_MMU_BOOKE:
7733 mmu_model = "PowerPC BookE";
7734 break;
7735 case POWERPC_MMU_BOOKE206:
7736 mmu_model = "PowerPC BookE 2.06";
7737 break;
7738 case POWERPC_MMU_601:
7739 mmu_model = "PowerPC 601";
7740 break;
7741 #if defined (TARGET_PPC64)
7742 case POWERPC_MMU_64B:
7743 mmu_model = "PowerPC 64";
7744 break;
7745 #endif
7746 default:
7747 mmu_model = "Unknown or invalid";
7748 break;
7749 }
7750 switch (env->excp_model) {
7751 case POWERPC_EXCP_STD:
7752 excp_model = "PowerPC";
7753 break;
7754 case POWERPC_EXCP_40x:
7755 excp_model = "PowerPC 40x";
7756 break;
7757 case POWERPC_EXCP_601:
7758 excp_model = "PowerPC 601";
7759 break;
7760 case POWERPC_EXCP_602:
7761 excp_model = "PowerPC 602";
7762 break;
7763 case POWERPC_EXCP_603:
7764 excp_model = "PowerPC 603";
7765 break;
7766 case POWERPC_EXCP_603E:
7767 excp_model = "PowerPC 603e";
7768 break;
7769 case POWERPC_EXCP_604:
7770 excp_model = "PowerPC 604";
7771 break;
7772 case POWERPC_EXCP_7x0:
7773 excp_model = "PowerPC 740/750";
7774 break;
7775 case POWERPC_EXCP_7x5:
7776 excp_model = "PowerPC 745/755";
7777 break;
7778 case POWERPC_EXCP_74xx:
7779 excp_model = "PowerPC 74xx";
7780 break;
7781 case POWERPC_EXCP_BOOKE:
7782 excp_model = "PowerPC BookE";
7783 break;
7784 #if defined (TARGET_PPC64)
7785 case POWERPC_EXCP_970:
7786 excp_model = "PowerPC 970";
7787 break;
7788 #endif
7789 default:
7790 excp_model = "Unknown or invalid";
7791 break;
7792 }
7793 switch (env->bus_model) {
7794 case PPC_FLAGS_INPUT_6xx:
7795 bus_model = "PowerPC 6xx";
7796 break;
7797 case PPC_FLAGS_INPUT_BookE:
7798 bus_model = "PowerPC BookE";
7799 break;
7800 case PPC_FLAGS_INPUT_405:
7801 bus_model = "PowerPC 405";
7802 break;
7803 case PPC_FLAGS_INPUT_401:
7804 bus_model = "PowerPC 401/403";
7805 break;
7806 case PPC_FLAGS_INPUT_RCPU:
7807 bus_model = "RCPU / MPC8xx";
7808 break;
7809 #if defined (TARGET_PPC64)
7810 case PPC_FLAGS_INPUT_970:
7811 bus_model = "PowerPC 970";
7812 break;
7813 #endif
7814 default:
7815 bus_model = "Unknown or invalid";
7816 break;
7817 }
7818 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
7819 " MMU model : %s\n",
7820 pcc->name, pcc->pvr, pcc->msr_mask, mmu_model);
7821 #if !defined(CONFIG_USER_ONLY)
7822 if (env->tlb != NULL) {
7823 printf(" %d %s TLB in %d ways\n",
7824 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
7825 env->nb_ways);
7826 }
7827 #endif
7828 printf(" Exceptions model : %s\n"
7829 " Bus model : %s\n",
7830 excp_model, bus_model);
7831 printf(" MSR features :\n");
7832 if (env->flags & POWERPC_FLAG_SPE)
7833 printf(" signal processing engine enable"
7834 "\n");
7835 else if (env->flags & POWERPC_FLAG_VRE)
7836 printf(" vector processor enable\n");
7837 if (env->flags & POWERPC_FLAG_TGPR)
7838 printf(" temporary GPRs\n");
7839 else if (env->flags & POWERPC_FLAG_CE)
7840 printf(" critical input enable\n");
7841 if (env->flags & POWERPC_FLAG_SE)
7842 printf(" single-step trace mode\n");
7843 else if (env->flags & POWERPC_FLAG_DWE)
7844 printf(" debug wait enable\n");
7845 else if (env->flags & POWERPC_FLAG_UBLE)
7846 printf(" user BTB lock enable\n");
7847 if (env->flags & POWERPC_FLAG_BE)
7848 printf(" branch-step trace mode\n");
7849 else if (env->flags & POWERPC_FLAG_DE)
7850 printf(" debug interrupt enable\n");
7851 if (env->flags & POWERPC_FLAG_PX)
7852 printf(" inclusive protection\n");
7853 else if (env->flags & POWERPC_FLAG_PMM)
7854 printf(" performance monitor mark\n");
7855 if (env->flags == POWERPC_FLAG_NONE)
7856 printf(" none\n");
7857 printf(" Time-base/decrementer clock source: %s\n",
7858 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
7859 }
7860 dump_ppc_insns(env);
7861 dump_ppc_sprs(env);
7862 fflush(stdout);
7863 #endif
7864 }
7865
7866 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
7867 {
7868 ObjectClass *oc = (ObjectClass *)a;
7869 uint32_t pvr = *(uint32_t *)b;
7870 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
7871
7872 /* -cpu host does a PVR lookup during construction */
7873 if (unlikely(strcmp(object_class_get_name(oc),
7874 TYPE_HOST_POWERPC_CPU) == 0)) {
7875 return -1;
7876 }
7877
7878 #if defined(TARGET_PPCEMB)
7879 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
7880 return -1;
7881 }
7882 #endif
7883
7884 return pcc->pvr == pvr ? 0 : -1;
7885 }
7886
7887 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
7888 {
7889 GSList *list, *item;
7890 PowerPCCPUClass *pcc = NULL;
7891
7892 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7893 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
7894 if (item != NULL) {
7895 pcc = POWERPC_CPU_CLASS(item->data);
7896 }
7897 g_slist_free(list);
7898
7899 return pcc;
7900 }
7901
7902 static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
7903 {
7904 ObjectClass *oc = (ObjectClass *)a;
7905 const char *name = b;
7906 #if defined(TARGET_PPCEMB)
7907 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7908 #endif
7909
7910 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
7911 #if defined(TARGET_PPCEMB)
7912 pcc->mmu_model == POWERPC_MMU_BOOKE &&
7913 #endif
7914 strcmp(object_class_get_name(oc) + strlen(name),
7915 "-" TYPE_POWERPC_CPU) == 0) {
7916 return 0;
7917 }
7918 return -1;
7919 }
7920
7921 #include <ctype.h>
7922
7923 static ObjectClass *ppc_cpu_class_by_name(const char *name)
7924 {
7925 GSList *list, *item;
7926 ObjectClass *ret = NULL;
7927 const char *p;
7928 int i, len;
7929
7930 /* Check if the given name is a PVR */
7931 len = strlen(name);
7932 if (len == 10 && name[0] == '0' && name[1] == 'x') {
7933 p = name + 2;
7934 goto check_pvr;
7935 } else if (len == 8) {
7936 p = name;
7937 check_pvr:
7938 for (i = 0; i < 8; i++) {
7939 if (!qemu_isxdigit(*p++))
7940 break;
7941 }
7942 if (i == 8) {
7943 ret = OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
7944 return ret;
7945 }
7946 }
7947
7948 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7949 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
7950 return ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
7951 }
7952 }
7953
7954 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7955 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
7956 if (item != NULL) {
7957 ret = OBJECT_CLASS(item->data);
7958 }
7959 g_slist_free(list);
7960
7961 return ret;
7962 }
7963
7964 PowerPCCPU *cpu_ppc_init(const char *cpu_model)
7965 {
7966 PowerPCCPU *cpu;
7967 CPUPPCState *env;
7968 ObjectClass *oc;
7969 Error *err = NULL;
7970
7971 oc = ppc_cpu_class_by_name(cpu_model);
7972 if (oc == NULL) {
7973 return NULL;
7974 }
7975
7976 cpu = POWERPC_CPU(object_new(object_class_get_name(oc)));
7977 env = &cpu->env;
7978 env->cpu_model_str = cpu_model;
7979
7980 object_property_set_bool(OBJECT(cpu), true, "realized", &err);
7981 if (err != NULL) {
7982 fprintf(stderr, "%s\n", error_get_pretty(err));
7983 error_free(err);
7984 object_unref(OBJECT(cpu));
7985 return NULL;
7986 }
7987
7988 return cpu;
7989 }
7990
7991 /* Sort by PVR, ordering special case "host" last. */
7992 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
7993 {
7994 ObjectClass *oc_a = (ObjectClass *)a;
7995 ObjectClass *oc_b = (ObjectClass *)b;
7996 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
7997 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
7998 const char *name_a = object_class_get_name(oc_a);
7999 const char *name_b = object_class_get_name(oc_b);
8000
8001 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
8002 return 1;
8003 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
8004 return -1;
8005 } else {
8006 /* Avoid an integer overflow during subtraction */
8007 if (pcc_a->pvr < pcc_b->pvr) {
8008 return -1;
8009 } else if (pcc_a->pvr > pcc_b->pvr) {
8010 return 1;
8011 } else {
8012 return 0;
8013 }
8014 }
8015 }
8016
8017 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
8018 {
8019 ObjectClass *oc = data;
8020 CPUListState *s = user_data;
8021 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8022 const char *typename = object_class_get_name(oc);
8023 char *name;
8024 int i;
8025
8026 #if defined(TARGET_PPCEMB)
8027 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
8028 return;
8029 }
8030 #endif
8031 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
8032 return;
8033 }
8034
8035 name = g_strndup(typename,
8036 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
8037 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
8038 name, pcc->pvr);
8039 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8040 const PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8041 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
8042
8043 if (alias_oc != oc) {
8044 continue;
8045 }
8046 (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
8047 alias->alias, name);
8048 }
8049 g_free(name);
8050 }
8051
8052 void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
8053 {
8054 CPUListState s = {
8055 .file = f,
8056 .cpu_fprintf = cpu_fprintf,
8057 };
8058 GSList *list;
8059
8060 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8061 list = g_slist_sort(list, ppc_cpu_list_compare);
8062 g_slist_foreach(list, ppc_cpu_list_entry, &s);
8063 g_slist_free(list);
8064
8065 #ifdef CONFIG_KVM
8066 cpu_fprintf(f, "\n");
8067 cpu_fprintf(f, "PowerPC %-16s\n", "host");
8068 #endif
8069 }
8070
8071 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
8072 {
8073 ObjectClass *oc = data;
8074 CpuDefinitionInfoList **first = user_data;
8075 const char *typename;
8076 CpuDefinitionInfoList *entry;
8077 CpuDefinitionInfo *info;
8078 #if defined(TARGET_PPCEMB)
8079 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8080
8081 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
8082 return;
8083 }
8084 #endif
8085
8086 typename = object_class_get_name(oc);
8087 info = g_malloc0(sizeof(*info));
8088 info->name = g_strndup(typename,
8089 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
8090
8091 entry = g_malloc0(sizeof(*entry));
8092 entry->value = info;
8093 entry->next = *first;
8094 *first = entry;
8095 }
8096
8097 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
8098 {
8099 CpuDefinitionInfoList *cpu_list = NULL;
8100 GSList *list;
8101 int i;
8102
8103 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8104 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
8105 g_slist_free(list);
8106
8107 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8108 const PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8109 ObjectClass *oc;
8110 CpuDefinitionInfoList *entry;
8111 CpuDefinitionInfo *info;
8112
8113 oc = ppc_cpu_class_by_name(alias->model);
8114 if (oc == NULL) {
8115 continue;
8116 }
8117
8118 info = g_malloc0(sizeof(*info));
8119 info->name = g_strdup(alias->alias);
8120
8121 entry = g_malloc0(sizeof(*entry));
8122 entry->value = info;
8123 entry->next = cpu_list;
8124 cpu_list = entry;
8125 }
8126
8127 return cpu_list;
8128 }
8129
8130 /* CPUClass::reset() */
8131 static void ppc_cpu_reset(CPUState *s)
8132 {
8133 PowerPCCPU *cpu = POWERPC_CPU(s);
8134 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8135 CPUPPCState *env = &cpu->env;
8136 target_ulong msr;
8137
8138 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
8139 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
8140 log_cpu_state(env, 0);
8141 }
8142
8143 pcc->parent_reset(s);
8144
8145 msr = (target_ulong)0;
8146 if (0) {
8147 /* XXX: find a suitable condition to enable the hypervisor mode */
8148 msr |= (target_ulong)MSR_HVB;
8149 }
8150 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
8151 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
8152 msr |= (target_ulong)1 << MSR_EP;
8153 #if defined(DO_SINGLE_STEP) && 0
8154 /* Single step trace mode */
8155 msr |= (target_ulong)1 << MSR_SE;
8156 msr |= (target_ulong)1 << MSR_BE;
8157 #endif
8158 #if defined(CONFIG_USER_ONLY)
8159 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
8160 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
8161 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
8162 msr |= (target_ulong)1 << MSR_PR;
8163 #endif
8164
8165 #if defined(TARGET_PPC64)
8166 if (env->mmu_model & POWERPC_MMU_64) {
8167 env->msr |= (1ULL << MSR_SF);
8168 }
8169 #endif
8170
8171 hreg_store_msr(env, msr, 1);
8172
8173 #if !defined(CONFIG_USER_ONLY)
8174 env->nip = env->hreset_vector | env->excp_prefix;
8175 if (env->mmu_model != POWERPC_MMU_REAL) {
8176 ppc_tlb_invalidate_all(env);
8177 }
8178 #endif
8179
8180 hreg_compute_hflags(env);
8181 env->reserve_addr = (target_ulong)-1ULL;
8182 /* Be sure no exception or interrupt is pending */
8183 env->pending_interrupts = 0;
8184 env->exception_index = POWERPC_EXCP_NONE;
8185 env->error_code = 0;
8186
8187 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
8188 env->vpa_addr = 0;
8189 env->slb_shadow_addr = 0;
8190 env->slb_shadow_size = 0;
8191 env->dtl_addr = 0;
8192 env->dtl_size = 0;
8193 #endif /* TARGET_PPC64 */
8194
8195 /* Flush all TLBs */
8196 tlb_flush(env, 1);
8197 }
8198
8199 static void ppc_cpu_initfn(Object *obj)
8200 {
8201 CPUState *cs = CPU(obj);
8202 PowerPCCPU *cpu = POWERPC_CPU(obj);
8203 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8204 CPUPPCState *env = &cpu->env;
8205
8206 cs->env_ptr = env;
8207 cpu_exec_init(env);
8208
8209 env->msr_mask = pcc->msr_mask;
8210 env->mmu_model = pcc->mmu_model;
8211 env->excp_model = pcc->excp_model;
8212 env->bus_model = pcc->bus_model;
8213 env->insns_flags = pcc->insns_flags;
8214 env->insns_flags2 = pcc->insns_flags2;
8215 env->flags = pcc->flags;
8216 env->bfd_mach = pcc->bfd_mach;
8217 env->check_pow = pcc->check_pow;
8218
8219 #if defined(TARGET_PPC64)
8220 if (pcc->sps) {
8221 env->sps = *pcc->sps;
8222 } else if (env->mmu_model & POWERPC_MMU_64) {
8223 /* Use default sets of page sizes */
8224 static const struct ppc_segment_page_sizes defsps = {
8225 .sps = {
8226 { .page_shift = 12, /* 4K */
8227 .slb_enc = 0,
8228 .enc = { { .page_shift = 12, .pte_enc = 0 } }
8229 },
8230 { .page_shift = 24, /* 16M */
8231 .slb_enc = 0x100,
8232 .enc = { { .page_shift = 24, .pte_enc = 0 } }
8233 },
8234 },
8235 };
8236 env->sps = defsps;
8237 }
8238 #endif /* defined(TARGET_PPC64) */
8239
8240 if (tcg_enabled()) {
8241 ppc_translate_init();
8242 }
8243 }
8244
8245 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
8246 {
8247 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8248 CPUClass *cc = CPU_CLASS(oc);
8249 DeviceClass *dc = DEVICE_CLASS(oc);
8250
8251 pcc->parent_realize = dc->realize;
8252 dc->realize = ppc_cpu_realizefn;
8253
8254 pcc->parent_reset = cc->reset;
8255 cc->reset = ppc_cpu_reset;
8256
8257 cc->class_by_name = ppc_cpu_class_by_name;
8258 cc->do_interrupt = ppc_cpu_do_interrupt;
8259 }
8260
8261 static const TypeInfo ppc_cpu_type_info = {
8262 .name = TYPE_POWERPC_CPU,
8263 .parent = TYPE_CPU,
8264 .instance_size = sizeof(PowerPCCPU),
8265 .instance_init = ppc_cpu_initfn,
8266 .abstract = true,
8267 .class_size = sizeof(PowerPCCPUClass),
8268 .class_init = ppc_cpu_class_init,
8269 };
8270
8271 static void ppc_cpu_register_types(void)
8272 {
8273 type_register_static(&ppc_cpu_type_info);
8274 }
8275
8276 type_init(ppc_cpu_register_types)
Qemu copy for testing