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Remove synonymous in PowerPC MSR bits definitions.
[qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26 #include "dis-asm.h"
27
28 //#define PPC_DUMP_CPU
29 //#define PPC_DEBUG_SPR
30 //#define PPC_DEBUG_IRQ
31
32 struct ppc_def_t {
33 const unsigned char *name;
34 uint32_t pvr;
35 uint32_t pvr_mask;
36 uint64_t insns_flags;
37 uint64_t msr_mask;
38 uint8_t mmu_model;
39 uint8_t excp_model;
40 uint8_t bus_model;
41 uint8_t pad;
42 uint32_t flags;
43 int bfd_mach;
44 void (*init_proc)(CPUPPCState *env);
45 };
46
47 /* For user-mode emulation, we don't emulate any IRQ controller */
48 #if defined(CONFIG_USER_ONLY)
49 #define PPC_IRQ_INIT_FN(name) \
50 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
51 { \
52 }
53 #else
54 #define PPC_IRQ_INIT_FN(name) \
55 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
56 #endif
57
58 PPC_IRQ_INIT_FN(40x);
59 PPC_IRQ_INIT_FN(6xx);
60 PPC_IRQ_INIT_FN(970);
61
62 /* Generic callbacks:
63 * do nothing but store/retrieve spr value
64 */
65 #ifdef PPC_DUMP_SPR_ACCESSES
66 static void spr_read_generic (void *opaque, int sprn)
67 {
68 gen_op_load_dump_spr(sprn);
69 }
70
71 static void spr_write_generic (void *opaque, int sprn)
72 {
73 gen_op_store_dump_spr(sprn);
74 }
75 #else
76 static void spr_read_generic (void *opaque, int sprn)
77 {
78 gen_op_load_spr(sprn);
79 }
80
81 static void spr_write_generic (void *opaque, int sprn)
82 {
83 gen_op_store_spr(sprn);
84 }
85 #endif
86
87 #if !defined(CONFIG_USER_ONLY)
88 static void spr_write_clear (void *opaque, int sprn)
89 {
90 gen_op_mask_spr(sprn);
91 }
92 #endif
93
94 /* SPR common to all PowerPC */
95 /* XER */
96 static void spr_read_xer (void *opaque, int sprn)
97 {
98 gen_op_load_xer();
99 }
100
101 static void spr_write_xer (void *opaque, int sprn)
102 {
103 gen_op_store_xer();
104 }
105
106 /* LR */
107 static void spr_read_lr (void *opaque, int sprn)
108 {
109 gen_op_load_lr();
110 }
111
112 static void spr_write_lr (void *opaque, int sprn)
113 {
114 gen_op_store_lr();
115 }
116
117 /* CTR */
118 static void spr_read_ctr (void *opaque, int sprn)
119 {
120 gen_op_load_ctr();
121 }
122
123 static void spr_write_ctr (void *opaque, int sprn)
124 {
125 gen_op_store_ctr();
126 }
127
128 /* User read access to SPR */
129 /* USPRx */
130 /* UMMCRx */
131 /* UPMCx */
132 /* USIA */
133 /* UDECR */
134 static void spr_read_ureg (void *opaque, int sprn)
135 {
136 gen_op_load_spr(sprn + 0x10);
137 }
138
139 /* SPR common to all non-embedded PowerPC */
140 /* DECR */
141 #if !defined(CONFIG_USER_ONLY)
142 static void spr_read_decr (void *opaque, int sprn)
143 {
144 gen_op_load_decr();
145 }
146
147 static void spr_write_decr (void *opaque, int sprn)
148 {
149 gen_op_store_decr();
150 }
151 #endif
152
153 /* SPR common to all non-embedded PowerPC, except 601 */
154 /* Time base */
155 static void spr_read_tbl (void *opaque, int sprn)
156 {
157 gen_op_load_tbl();
158 }
159
160 static void spr_read_tbu (void *opaque, int sprn)
161 {
162 gen_op_load_tbu();
163 }
164
165 __attribute__ (( unused ))
166 static void spr_read_atbl (void *opaque, int sprn)
167 {
168 gen_op_load_atbl();
169 }
170
171 __attribute__ (( unused ))
172 static void spr_read_atbu (void *opaque, int sprn)
173 {
174 gen_op_load_atbu();
175 }
176
177 #if !defined(CONFIG_USER_ONLY)
178 static void spr_write_tbl (void *opaque, int sprn)
179 {
180 gen_op_store_tbl();
181 }
182
183 static void spr_write_tbu (void *opaque, int sprn)
184 {
185 gen_op_store_tbu();
186 }
187
188 __attribute__ (( unused ))
189 static void spr_write_atbl (void *opaque, int sprn)
190 {
191 gen_op_store_atbl();
192 }
193
194 __attribute__ (( unused ))
195 static void spr_write_atbu (void *opaque, int sprn)
196 {
197 gen_op_store_atbu();
198 }
199 #endif
200
201 #if !defined(CONFIG_USER_ONLY)
202 /* IBAT0U...IBAT0U */
203 /* IBAT0L...IBAT7L */
204 static void spr_read_ibat (void *opaque, int sprn)
205 {
206 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
207 }
208
209 static void spr_read_ibat_h (void *opaque, int sprn)
210 {
211 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
212 }
213
214 static void spr_write_ibatu (void *opaque, int sprn)
215 {
216 gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
217 }
218
219 static void spr_write_ibatu_h (void *opaque, int sprn)
220 {
221 gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
222 }
223
224 static void spr_write_ibatl (void *opaque, int sprn)
225 {
226 gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
227 }
228
229 static void spr_write_ibatl_h (void *opaque, int sprn)
230 {
231 gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
232 }
233
234 /* DBAT0U...DBAT7U */
235 /* DBAT0L...DBAT7L */
236 static void spr_read_dbat (void *opaque, int sprn)
237 {
238 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
239 }
240
241 static void spr_read_dbat_h (void *opaque, int sprn)
242 {
243 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
244 }
245
246 static void spr_write_dbatu (void *opaque, int sprn)
247 {
248 gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
249 }
250
251 static void spr_write_dbatu_h (void *opaque, int sprn)
252 {
253 gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
254 }
255
256 static void spr_write_dbatl (void *opaque, int sprn)
257 {
258 gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
259 }
260
261 static void spr_write_dbatl_h (void *opaque, int sprn)
262 {
263 gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
264 }
265
266 /* SDR1 */
267 static void spr_read_sdr1 (void *opaque, int sprn)
268 {
269 gen_op_load_sdr1();
270 }
271
272 static void spr_write_sdr1 (void *opaque, int sprn)
273 {
274 gen_op_store_sdr1();
275 }
276
277 /* 64 bits PowerPC specific SPRs */
278 /* ASR */
279 #if defined(TARGET_PPC64)
280 __attribute__ (( unused ))
281 static void spr_read_asr (void *opaque, int sprn)
282 {
283 gen_op_load_asr();
284 }
285
286 __attribute__ (( unused ))
287 static void spr_write_asr (void *opaque, int sprn)
288 {
289 gen_op_store_asr();
290 }
291 #endif
292 #endif
293
294 /* PowerPC 601 specific registers */
295 /* RTC */
296 static void spr_read_601_rtcl (void *opaque, int sprn)
297 {
298 gen_op_load_601_rtcl();
299 }
300
301 static void spr_read_601_rtcu (void *opaque, int sprn)
302 {
303 gen_op_load_601_rtcu();
304 }
305
306 #if !defined(CONFIG_USER_ONLY)
307 static void spr_write_601_rtcu (void *opaque, int sprn)
308 {
309 gen_op_store_601_rtcu();
310 }
311
312 static void spr_write_601_rtcl (void *opaque, int sprn)
313 {
314 gen_op_store_601_rtcl();
315 }
316 #endif
317
318 /* Unified bats */
319 #if !defined(CONFIG_USER_ONLY)
320 static void spr_read_601_ubat (void *opaque, int sprn)
321 {
322 gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
323 }
324
325 static void spr_write_601_ubatu (void *opaque, int sprn)
326 {
327 gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
328 }
329
330 static void spr_write_601_ubatl (void *opaque, int sprn)
331 {
332 gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
333 }
334 #endif
335
336 /* PowerPC 40x specific registers */
337 #if !defined(CONFIG_USER_ONLY)
338 static void spr_read_40x_pit (void *opaque, int sprn)
339 {
340 gen_op_load_40x_pit();
341 }
342
343 static void spr_write_40x_pit (void *opaque, int sprn)
344 {
345 gen_op_store_40x_pit();
346 }
347
348 static void spr_write_40x_dbcr0 (void *opaque, int sprn)
349 {
350 DisasContext *ctx = opaque;
351
352 gen_op_store_40x_dbcr0();
353 /* We must stop translation as we may have rebooted */
354 GEN_STOP(ctx);
355 }
356
357 static void spr_write_40x_sler (void *opaque, int sprn)
358 {
359 gen_op_store_40x_sler();
360 }
361
362 static void spr_write_booke_tcr (void *opaque, int sprn)
363 {
364 gen_op_store_booke_tcr();
365 }
366
367 static void spr_write_booke_tsr (void *opaque, int sprn)
368 {
369 gen_op_store_booke_tsr();
370 }
371 #endif
372
373 /* PowerPC 403 specific registers */
374 /* PBL1 / PBU1 / PBL2 / PBU2 */
375 #if !defined(CONFIG_USER_ONLY)
376 static void spr_read_403_pbr (void *opaque, int sprn)
377 {
378 gen_op_load_403_pb(sprn - SPR_403_PBL1);
379 }
380
381 static void spr_write_403_pbr (void *opaque, int sprn)
382 {
383 gen_op_store_403_pb(sprn - SPR_403_PBL1);
384 }
385
386 static void spr_write_pir (void *opaque, int sprn)
387 {
388 gen_op_store_pir();
389 }
390 #endif
391
392 #if !defined(CONFIG_USER_ONLY)
393 /* Callback used to write the exception vector base */
394 static void spr_write_excp_prefix (void *opaque, int sprn)
395 {
396 gen_op_store_excp_prefix();
397 gen_op_store_spr(sprn);
398 }
399
400 static void spr_write_excp_vector (void *opaque, int sprn)
401 {
402 DisasContext *ctx = opaque;
403
404 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
405 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR0);
406 gen_op_store_spr(sprn);
407 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
408 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR32 + 32);
409 gen_op_store_spr(sprn);
410 } else {
411 printf("Trying to write an unknown exception vector %d %03x\n",
412 sprn, sprn);
413 GEN_EXCP_PRIVREG(ctx);
414 }
415 }
416 #endif
417
418 #if defined(CONFIG_USER_ONLY)
419 #define spr_register(env, num, name, uea_read, uea_write, \
420 oea_read, oea_write, initial_value) \
421 do { \
422 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
423 } while (0)
424 static inline void _spr_register (CPUPPCState *env, int num,
425 const unsigned char *name,
426 void (*uea_read)(void *opaque, int sprn),
427 void (*uea_write)(void *opaque, int sprn),
428 target_ulong initial_value)
429 #else
430 static inline void spr_register (CPUPPCState *env, int num,
431 const unsigned char *name,
432 void (*uea_read)(void *opaque, int sprn),
433 void (*uea_write)(void *opaque, int sprn),
434 void (*oea_read)(void *opaque, int sprn),
435 void (*oea_write)(void *opaque, int sprn),
436 target_ulong initial_value)
437 #endif
438 {
439 ppc_spr_t *spr;
440
441 spr = &env->spr_cb[num];
442 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
443 #if !defined(CONFIG_USER_ONLY)
444 spr->oea_read != NULL || spr->oea_write != NULL ||
445 #endif
446 spr->uea_read != NULL || spr->uea_write != NULL) {
447 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
448 exit(1);
449 }
450 #if defined(PPC_DEBUG_SPR)
451 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
452 initial_value);
453 #endif
454 spr->name = name;
455 spr->uea_read = uea_read;
456 spr->uea_write = uea_write;
457 #if !defined(CONFIG_USER_ONLY)
458 spr->oea_read = oea_read;
459 spr->oea_write = oea_write;
460 #endif
461 env->spr[num] = initial_value;
462 }
463
464 /* Generic PowerPC SPRs */
465 static void gen_spr_generic (CPUPPCState *env)
466 {
467 /* Integer processing */
468 spr_register(env, SPR_XER, "XER",
469 &spr_read_xer, &spr_write_xer,
470 &spr_read_xer, &spr_write_xer,
471 0x00000000);
472 /* Branch contol */
473 spr_register(env, SPR_LR, "LR",
474 &spr_read_lr, &spr_write_lr,
475 &spr_read_lr, &spr_write_lr,
476 0x00000000);
477 spr_register(env, SPR_CTR, "CTR",
478 &spr_read_ctr, &spr_write_ctr,
479 &spr_read_ctr, &spr_write_ctr,
480 0x00000000);
481 /* Interrupt processing */
482 spr_register(env, SPR_SRR0, "SRR0",
483 SPR_NOACCESS, SPR_NOACCESS,
484 &spr_read_generic, &spr_write_generic,
485 0x00000000);
486 spr_register(env, SPR_SRR1, "SRR1",
487 SPR_NOACCESS, SPR_NOACCESS,
488 &spr_read_generic, &spr_write_generic,
489 0x00000000);
490 /* Processor control */
491 spr_register(env, SPR_SPRG0, "SPRG0",
492 SPR_NOACCESS, SPR_NOACCESS,
493 &spr_read_generic, &spr_write_generic,
494 0x00000000);
495 spr_register(env, SPR_SPRG1, "SPRG1",
496 SPR_NOACCESS, SPR_NOACCESS,
497 &spr_read_generic, &spr_write_generic,
498 0x00000000);
499 spr_register(env, SPR_SPRG2, "SPRG2",
500 SPR_NOACCESS, SPR_NOACCESS,
501 &spr_read_generic, &spr_write_generic,
502 0x00000000);
503 spr_register(env, SPR_SPRG3, "SPRG3",
504 SPR_NOACCESS, SPR_NOACCESS,
505 &spr_read_generic, &spr_write_generic,
506 0x00000000);
507 }
508
509 /* SPR common to all non-embedded PowerPC, including 601 */
510 static void gen_spr_ne_601 (CPUPPCState *env)
511 {
512 /* Exception processing */
513 spr_register(env, SPR_DSISR, "DSISR",
514 SPR_NOACCESS, SPR_NOACCESS,
515 &spr_read_generic, &spr_write_generic,
516 0x00000000);
517 spr_register(env, SPR_DAR, "DAR",
518 SPR_NOACCESS, SPR_NOACCESS,
519 &spr_read_generic, &spr_write_generic,
520 0x00000000);
521 /* Timer */
522 spr_register(env, SPR_DECR, "DECR",
523 SPR_NOACCESS, SPR_NOACCESS,
524 &spr_read_decr, &spr_write_decr,
525 0x00000000);
526 /* Memory management */
527 spr_register(env, SPR_SDR1, "SDR1",
528 SPR_NOACCESS, SPR_NOACCESS,
529 &spr_read_sdr1, &spr_write_sdr1,
530 0x00000000);
531 }
532
533 /* BATs 0-3 */
534 static void gen_low_BATs (CPUPPCState *env)
535 {
536 #if !defined(CONFIG_USER_ONLY)
537 spr_register(env, SPR_IBAT0U, "IBAT0U",
538 SPR_NOACCESS, SPR_NOACCESS,
539 &spr_read_ibat, &spr_write_ibatu,
540 0x00000000);
541 spr_register(env, SPR_IBAT0L, "IBAT0L",
542 SPR_NOACCESS, SPR_NOACCESS,
543 &spr_read_ibat, &spr_write_ibatl,
544 0x00000000);
545 spr_register(env, SPR_IBAT1U, "IBAT1U",
546 SPR_NOACCESS, SPR_NOACCESS,
547 &spr_read_ibat, &spr_write_ibatu,
548 0x00000000);
549 spr_register(env, SPR_IBAT1L, "IBAT1L",
550 SPR_NOACCESS, SPR_NOACCESS,
551 &spr_read_ibat, &spr_write_ibatl,
552 0x00000000);
553 spr_register(env, SPR_IBAT2U, "IBAT2U",
554 SPR_NOACCESS, SPR_NOACCESS,
555 &spr_read_ibat, &spr_write_ibatu,
556 0x00000000);
557 spr_register(env, SPR_IBAT2L, "IBAT2L",
558 SPR_NOACCESS, SPR_NOACCESS,
559 &spr_read_ibat, &spr_write_ibatl,
560 0x00000000);
561 spr_register(env, SPR_IBAT3U, "IBAT3U",
562 SPR_NOACCESS, SPR_NOACCESS,
563 &spr_read_ibat, &spr_write_ibatu,
564 0x00000000);
565 spr_register(env, SPR_IBAT3L, "IBAT3L",
566 SPR_NOACCESS, SPR_NOACCESS,
567 &spr_read_ibat, &spr_write_ibatl,
568 0x00000000);
569 spr_register(env, SPR_DBAT0U, "DBAT0U",
570 SPR_NOACCESS, SPR_NOACCESS,
571 &spr_read_dbat, &spr_write_dbatu,
572 0x00000000);
573 spr_register(env, SPR_DBAT0L, "DBAT0L",
574 SPR_NOACCESS, SPR_NOACCESS,
575 &spr_read_dbat, &spr_write_dbatl,
576 0x00000000);
577 spr_register(env, SPR_DBAT1U, "DBAT1U",
578 SPR_NOACCESS, SPR_NOACCESS,
579 &spr_read_dbat, &spr_write_dbatu,
580 0x00000000);
581 spr_register(env, SPR_DBAT1L, "DBAT1L",
582 SPR_NOACCESS, SPR_NOACCESS,
583 &spr_read_dbat, &spr_write_dbatl,
584 0x00000000);
585 spr_register(env, SPR_DBAT2U, "DBAT2U",
586 SPR_NOACCESS, SPR_NOACCESS,
587 &spr_read_dbat, &spr_write_dbatu,
588 0x00000000);
589 spr_register(env, SPR_DBAT2L, "DBAT2L",
590 SPR_NOACCESS, SPR_NOACCESS,
591 &spr_read_dbat, &spr_write_dbatl,
592 0x00000000);
593 spr_register(env, SPR_DBAT3U, "DBAT3U",
594 SPR_NOACCESS, SPR_NOACCESS,
595 &spr_read_dbat, &spr_write_dbatu,
596 0x00000000);
597 spr_register(env, SPR_DBAT3L, "DBAT3L",
598 SPR_NOACCESS, SPR_NOACCESS,
599 &spr_read_dbat, &spr_write_dbatl,
600 0x00000000);
601 env->nb_BATs += 4;
602 #endif
603 }
604
605 /* BATs 4-7 */
606 static void gen_high_BATs (CPUPPCState *env)
607 {
608 #if !defined(CONFIG_USER_ONLY)
609 spr_register(env, SPR_IBAT4U, "IBAT4U",
610 SPR_NOACCESS, SPR_NOACCESS,
611 &spr_read_ibat_h, &spr_write_ibatu_h,
612 0x00000000);
613 spr_register(env, SPR_IBAT4L, "IBAT4L",
614 SPR_NOACCESS, SPR_NOACCESS,
615 &spr_read_ibat_h, &spr_write_ibatl_h,
616 0x00000000);
617 spr_register(env, SPR_IBAT5U, "IBAT5U",
618 SPR_NOACCESS, SPR_NOACCESS,
619 &spr_read_ibat_h, &spr_write_ibatu_h,
620 0x00000000);
621 spr_register(env, SPR_IBAT5L, "IBAT5L",
622 SPR_NOACCESS, SPR_NOACCESS,
623 &spr_read_ibat_h, &spr_write_ibatl_h,
624 0x00000000);
625 spr_register(env, SPR_IBAT6U, "IBAT6U",
626 SPR_NOACCESS, SPR_NOACCESS,
627 &spr_read_ibat_h, &spr_write_ibatu_h,
628 0x00000000);
629 spr_register(env, SPR_IBAT6L, "IBAT6L",
630 SPR_NOACCESS, SPR_NOACCESS,
631 &spr_read_ibat_h, &spr_write_ibatl_h,
632 0x00000000);
633 spr_register(env, SPR_IBAT7U, "IBAT7U",
634 SPR_NOACCESS, SPR_NOACCESS,
635 &spr_read_ibat_h, &spr_write_ibatu_h,
636 0x00000000);
637 spr_register(env, SPR_IBAT7L, "IBAT7L",
638 SPR_NOACCESS, SPR_NOACCESS,
639 &spr_read_ibat_h, &spr_write_ibatl_h,
640 0x00000000);
641 spr_register(env, SPR_DBAT4U, "DBAT4U",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_dbat_h, &spr_write_dbatu_h,
644 0x00000000);
645 spr_register(env, SPR_DBAT4L, "DBAT4L",
646 SPR_NOACCESS, SPR_NOACCESS,
647 &spr_read_dbat_h, &spr_write_dbatl_h,
648 0x00000000);
649 spr_register(env, SPR_DBAT5U, "DBAT5U",
650 SPR_NOACCESS, SPR_NOACCESS,
651 &spr_read_dbat_h, &spr_write_dbatu_h,
652 0x00000000);
653 spr_register(env, SPR_DBAT5L, "DBAT5L",
654 SPR_NOACCESS, SPR_NOACCESS,
655 &spr_read_dbat_h, &spr_write_dbatl_h,
656 0x00000000);
657 spr_register(env, SPR_DBAT6U, "DBAT6U",
658 SPR_NOACCESS, SPR_NOACCESS,
659 &spr_read_dbat_h, &spr_write_dbatu_h,
660 0x00000000);
661 spr_register(env, SPR_DBAT6L, "DBAT6L",
662 SPR_NOACCESS, SPR_NOACCESS,
663 &spr_read_dbat_h, &spr_write_dbatl_h,
664 0x00000000);
665 spr_register(env, SPR_DBAT7U, "DBAT7U",
666 SPR_NOACCESS, SPR_NOACCESS,
667 &spr_read_dbat_h, &spr_write_dbatu_h,
668 0x00000000);
669 spr_register(env, SPR_DBAT7L, "DBAT7L",
670 SPR_NOACCESS, SPR_NOACCESS,
671 &spr_read_dbat_h, &spr_write_dbatl_h,
672 0x00000000);
673 env->nb_BATs += 4;
674 #endif
675 }
676
677 /* Generic PowerPC time base */
678 static void gen_tbl (CPUPPCState *env)
679 {
680 spr_register(env, SPR_VTBL, "TBL",
681 &spr_read_tbl, SPR_NOACCESS,
682 &spr_read_tbl, SPR_NOACCESS,
683 0x00000000);
684 spr_register(env, SPR_TBL, "TBL",
685 SPR_NOACCESS, SPR_NOACCESS,
686 SPR_NOACCESS, &spr_write_tbl,
687 0x00000000);
688 spr_register(env, SPR_VTBU, "TBU",
689 &spr_read_tbu, SPR_NOACCESS,
690 &spr_read_tbu, SPR_NOACCESS,
691 0x00000000);
692 spr_register(env, SPR_TBU, "TBU",
693 SPR_NOACCESS, SPR_NOACCESS,
694 SPR_NOACCESS, &spr_write_tbu,
695 0x00000000);
696 }
697
698 /* Softare table search registers */
699 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
700 {
701 #if !defined(CONFIG_USER_ONLY)
702 env->nb_tlb = nb_tlbs;
703 env->nb_ways = nb_ways;
704 env->id_tlbs = 1;
705 spr_register(env, SPR_DMISS, "DMISS",
706 SPR_NOACCESS, SPR_NOACCESS,
707 &spr_read_generic, SPR_NOACCESS,
708 0x00000000);
709 spr_register(env, SPR_DCMP, "DCMP",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_generic, SPR_NOACCESS,
712 0x00000000);
713 spr_register(env, SPR_HASH1, "HASH1",
714 SPR_NOACCESS, SPR_NOACCESS,
715 &spr_read_generic, SPR_NOACCESS,
716 0x00000000);
717 spr_register(env, SPR_HASH2, "HASH2",
718 SPR_NOACCESS, SPR_NOACCESS,
719 &spr_read_generic, SPR_NOACCESS,
720 0x00000000);
721 spr_register(env, SPR_IMISS, "IMISS",
722 SPR_NOACCESS, SPR_NOACCESS,
723 &spr_read_generic, SPR_NOACCESS,
724 0x00000000);
725 spr_register(env, SPR_ICMP, "ICMP",
726 SPR_NOACCESS, SPR_NOACCESS,
727 &spr_read_generic, SPR_NOACCESS,
728 0x00000000);
729 spr_register(env, SPR_RPA, "RPA",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_generic, &spr_write_generic,
732 0x00000000);
733 #endif
734 }
735
736 /* SPR common to MPC755 and G2 */
737 static void gen_spr_G2_755 (CPUPPCState *env)
738 {
739 /* SGPRs */
740 spr_register(env, SPR_SPRG4, "SPRG4",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_generic, &spr_write_generic,
743 0x00000000);
744 spr_register(env, SPR_SPRG5, "SPRG5",
745 SPR_NOACCESS, SPR_NOACCESS,
746 &spr_read_generic, &spr_write_generic,
747 0x00000000);
748 spr_register(env, SPR_SPRG6, "SPRG6",
749 SPR_NOACCESS, SPR_NOACCESS,
750 &spr_read_generic, &spr_write_generic,
751 0x00000000);
752 spr_register(env, SPR_SPRG7, "SPRG7",
753 SPR_NOACCESS, SPR_NOACCESS,
754 &spr_read_generic, &spr_write_generic,
755 0x00000000);
756 /* External access control */
757 /* XXX : not implemented */
758 spr_register(env, SPR_EAR, "EAR",
759 SPR_NOACCESS, SPR_NOACCESS,
760 &spr_read_generic, &spr_write_generic,
761 0x00000000);
762 }
763
764 /* SPR common to all 7xx PowerPC implementations */
765 static void gen_spr_7xx (CPUPPCState *env)
766 {
767 /* Breakpoints */
768 /* XXX : not implemented */
769 spr_register(env, SPR_DABR, "DABR",
770 SPR_NOACCESS, SPR_NOACCESS,
771 &spr_read_generic, &spr_write_generic,
772 0x00000000);
773 /* XXX : not implemented */
774 spr_register(env, SPR_IABR, "IABR",
775 SPR_NOACCESS, SPR_NOACCESS,
776 &spr_read_generic, &spr_write_generic,
777 0x00000000);
778 /* Cache management */
779 /* XXX : not implemented */
780 spr_register(env, SPR_ICTC, "ICTC",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_generic, &spr_write_generic,
783 0x00000000);
784 /* XXX : not implemented */
785 spr_register(env, SPR_L2CR, "L2CR",
786 SPR_NOACCESS, SPR_NOACCESS,
787 &spr_read_generic, &spr_write_generic,
788 0x00000000);
789 /* Performance monitors */
790 /* XXX : not implemented */
791 spr_register(env, SPR_MMCR0, "MMCR0",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_generic, &spr_write_generic,
794 0x00000000);
795 /* XXX : not implemented */
796 spr_register(env, SPR_MMCR1, "MMCR1",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_generic, &spr_write_generic,
799 0x00000000);
800 /* XXX : not implemented */
801 spr_register(env, SPR_PMC1, "PMC1",
802 SPR_NOACCESS, SPR_NOACCESS,
803 &spr_read_generic, &spr_write_generic,
804 0x00000000);
805 /* XXX : not implemented */
806 spr_register(env, SPR_PMC2, "PMC2",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_generic, &spr_write_generic,
809 0x00000000);
810 /* XXX : not implemented */
811 spr_register(env, SPR_PMC3, "PMC3",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_generic, &spr_write_generic,
814 0x00000000);
815 /* XXX : not implemented */
816 spr_register(env, SPR_PMC4, "PMC4",
817 SPR_NOACCESS, SPR_NOACCESS,
818 &spr_read_generic, &spr_write_generic,
819 0x00000000);
820 /* XXX : not implemented */
821 spr_register(env, SPR_SIAR, "SIAR",
822 SPR_NOACCESS, SPR_NOACCESS,
823 &spr_read_generic, SPR_NOACCESS,
824 0x00000000);
825 /* XXX : not implemented */
826 spr_register(env, SPR_UMMCR0, "UMMCR0",
827 &spr_read_ureg, SPR_NOACCESS,
828 &spr_read_ureg, SPR_NOACCESS,
829 0x00000000);
830 /* XXX : not implemented */
831 spr_register(env, SPR_UMMCR1, "UMMCR1",
832 &spr_read_ureg, SPR_NOACCESS,
833 &spr_read_ureg, SPR_NOACCESS,
834 0x00000000);
835 /* XXX : not implemented */
836 spr_register(env, SPR_UPMC1, "UPMC1",
837 &spr_read_ureg, SPR_NOACCESS,
838 &spr_read_ureg, SPR_NOACCESS,
839 0x00000000);
840 /* XXX : not implemented */
841 spr_register(env, SPR_UPMC2, "UPMC2",
842 &spr_read_ureg, SPR_NOACCESS,
843 &spr_read_ureg, SPR_NOACCESS,
844 0x00000000);
845 /* XXX : not implemented */
846 spr_register(env, SPR_UPMC3, "UPMC3",
847 &spr_read_ureg, SPR_NOACCESS,
848 &spr_read_ureg, SPR_NOACCESS,
849 0x00000000);
850 /* XXX : not implemented */
851 spr_register(env, SPR_UPMC4, "UPMC4",
852 &spr_read_ureg, SPR_NOACCESS,
853 &spr_read_ureg, SPR_NOACCESS,
854 0x00000000);
855 /* XXX : not implemented */
856 spr_register(env, SPR_USIAR, "USIAR",
857 &spr_read_ureg, SPR_NOACCESS,
858 &spr_read_ureg, SPR_NOACCESS,
859 0x00000000);
860 /* External access control */
861 /* XXX : not implemented */
862 spr_register(env, SPR_EAR, "EAR",
863 SPR_NOACCESS, SPR_NOACCESS,
864 &spr_read_generic, &spr_write_generic,
865 0x00000000);
866 }
867
868 static void gen_spr_thrm (CPUPPCState *env)
869 {
870 /* Thermal management */
871 /* XXX : not implemented */
872 spr_register(env, SPR_THRM1, "THRM1",
873 SPR_NOACCESS, SPR_NOACCESS,
874 &spr_read_generic, &spr_write_generic,
875 0x00000000);
876 /* XXX : not implemented */
877 spr_register(env, SPR_THRM2, "THRM2",
878 SPR_NOACCESS, SPR_NOACCESS,
879 &spr_read_generic, &spr_write_generic,
880 0x00000000);
881 /* XXX : not implemented */
882 spr_register(env, SPR_THRM3, "THRM3",
883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_generic, &spr_write_generic,
885 0x00000000);
886 }
887
888 /* SPR specific to PowerPC 604 implementation */
889 static void gen_spr_604 (CPUPPCState *env)
890 {
891 /* Processor identification */
892 spr_register(env, SPR_PIR, "PIR",
893 SPR_NOACCESS, SPR_NOACCESS,
894 &spr_read_generic, &spr_write_pir,
895 0x00000000);
896 /* Breakpoints */
897 /* XXX : not implemented */
898 spr_register(env, SPR_IABR, "IABR",
899 SPR_NOACCESS, SPR_NOACCESS,
900 &spr_read_generic, &spr_write_generic,
901 0x00000000);
902 /* XXX : not implemented */
903 spr_register(env, SPR_DABR, "DABR",
904 SPR_NOACCESS, SPR_NOACCESS,
905 &spr_read_generic, &spr_write_generic,
906 0x00000000);
907 /* Performance counters */
908 /* XXX : not implemented */
909 spr_register(env, SPR_MMCR0, "MMCR0",
910 SPR_NOACCESS, SPR_NOACCESS,
911 &spr_read_generic, &spr_write_generic,
912 0x00000000);
913 /* XXX : not implemented */
914 spr_register(env, SPR_MMCR1, "MMCR1",
915 SPR_NOACCESS, SPR_NOACCESS,
916 &spr_read_generic, &spr_write_generic,
917 0x00000000);
918 /* XXX : not implemented */
919 spr_register(env, SPR_PMC1, "PMC1",
920 SPR_NOACCESS, SPR_NOACCESS,
921 &spr_read_generic, &spr_write_generic,
922 0x00000000);
923 /* XXX : not implemented */
924 spr_register(env, SPR_PMC2, "PMC2",
925 SPR_NOACCESS, SPR_NOACCESS,
926 &spr_read_generic, &spr_write_generic,
927 0x00000000);
928 /* XXX : not implemented */
929 spr_register(env, SPR_PMC3, "PMC3",
930 SPR_NOACCESS, SPR_NOACCESS,
931 &spr_read_generic, &spr_write_generic,
932 0x00000000);
933 /* XXX : not implemented */
934 spr_register(env, SPR_PMC4, "PMC4",
935 SPR_NOACCESS, SPR_NOACCESS,
936 &spr_read_generic, &spr_write_generic,
937 0x00000000);
938 /* XXX : not implemented */
939 spr_register(env, SPR_SIAR, "SIAR",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, SPR_NOACCESS,
942 0x00000000);
943 /* XXX : not implemented */
944 spr_register(env, SPR_SDA, "SDA",
945 SPR_NOACCESS, SPR_NOACCESS,
946 &spr_read_generic, SPR_NOACCESS,
947 0x00000000);
948 /* External access control */
949 /* XXX : not implemented */
950 spr_register(env, SPR_EAR, "EAR",
951 SPR_NOACCESS, SPR_NOACCESS,
952 &spr_read_generic, &spr_write_generic,
953 0x00000000);
954 }
955
956 /* SPR specific to PowerPC 603 implementation */
957 static void gen_spr_603 (CPUPPCState *env)
958 {
959 /* External access control */
960 /* XXX : not implemented */
961 spr_register(env, SPR_EAR, "EAR",
962 SPR_NOACCESS, SPR_NOACCESS,
963 &spr_read_generic, &spr_write_generic,
964 0x00000000);
965 }
966
967 /* SPR specific to PowerPC G2 implementation */
968 static void gen_spr_G2 (CPUPPCState *env)
969 {
970 /* Memory base address */
971 /* MBAR */
972 /* XXX : not implemented */
973 spr_register(env, SPR_MBAR, "MBAR",
974 SPR_NOACCESS, SPR_NOACCESS,
975 &spr_read_generic, &spr_write_generic,
976 0x00000000);
977 /* System version register */
978 /* SVR */
979 /* XXX : TODO: initialize it to an appropriate value */
980 spr_register(env, SPR_SVR, "SVR",
981 SPR_NOACCESS, SPR_NOACCESS,
982 &spr_read_generic, SPR_NOACCESS,
983 0x00000000);
984 /* Exception processing */
985 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
986 SPR_NOACCESS, SPR_NOACCESS,
987 &spr_read_generic, &spr_write_generic,
988 0x00000000);
989 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
990 SPR_NOACCESS, SPR_NOACCESS,
991 &spr_read_generic, &spr_write_generic,
992 0x00000000);
993 /* Breakpoints */
994 /* XXX : not implemented */
995 spr_register(env, SPR_DABR, "DABR",
996 SPR_NOACCESS, SPR_NOACCESS,
997 &spr_read_generic, &spr_write_generic,
998 0x00000000);
999 /* XXX : not implemented */
1000 spr_register(env, SPR_DABR2, "DABR2",
1001 SPR_NOACCESS, SPR_NOACCESS,
1002 &spr_read_generic, &spr_write_generic,
1003 0x00000000);
1004 /* XXX : not implemented */
1005 spr_register(env, SPR_IABR, "IABR",
1006 SPR_NOACCESS, SPR_NOACCESS,
1007 &spr_read_generic, &spr_write_generic,
1008 0x00000000);
1009 /* XXX : not implemented */
1010 spr_register(env, SPR_IABR2, "IABR2",
1011 SPR_NOACCESS, SPR_NOACCESS,
1012 &spr_read_generic, &spr_write_generic,
1013 0x00000000);
1014 /* XXX : not implemented */
1015 spr_register(env, SPR_IBCR, "IBCR",
1016 SPR_NOACCESS, SPR_NOACCESS,
1017 &spr_read_generic, &spr_write_generic,
1018 0x00000000);
1019 /* XXX : not implemented */
1020 spr_register(env, SPR_DBCR, "DBCR",
1021 SPR_NOACCESS, SPR_NOACCESS,
1022 &spr_read_generic, &spr_write_generic,
1023 0x00000000);
1024 }
1025
1026 /* SPR specific to PowerPC 602 implementation */
1027 static void gen_spr_602 (CPUPPCState *env)
1028 {
1029 /* ESA registers */
1030 /* XXX : not implemented */
1031 spr_register(env, SPR_SER, "SER",
1032 SPR_NOACCESS, SPR_NOACCESS,
1033 &spr_read_generic, &spr_write_generic,
1034 0x00000000);
1035 /* XXX : not implemented */
1036 spr_register(env, SPR_SEBR, "SEBR",
1037 SPR_NOACCESS, SPR_NOACCESS,
1038 &spr_read_generic, &spr_write_generic,
1039 0x00000000);
1040 /* XXX : not implemented */
1041 spr_register(env, SPR_ESASRR, "ESASRR",
1042 SPR_NOACCESS, SPR_NOACCESS,
1043 &spr_read_generic, &spr_write_generic,
1044 0x00000000);
1045 /* Floating point status */
1046 /* XXX : not implemented */
1047 spr_register(env, SPR_SP, "SP",
1048 SPR_NOACCESS, SPR_NOACCESS,
1049 &spr_read_generic, &spr_write_generic,
1050 0x00000000);
1051 /* XXX : not implemented */
1052 spr_register(env, SPR_LT, "LT",
1053 SPR_NOACCESS, SPR_NOACCESS,
1054 &spr_read_generic, &spr_write_generic,
1055 0x00000000);
1056 /* Watchdog timer */
1057 /* XXX : not implemented */
1058 spr_register(env, SPR_TCR, "TCR",
1059 SPR_NOACCESS, SPR_NOACCESS,
1060 &spr_read_generic, &spr_write_generic,
1061 0x00000000);
1062 /* Interrupt base */
1063 spr_register(env, SPR_IBR, "IBR",
1064 SPR_NOACCESS, SPR_NOACCESS,
1065 &spr_read_generic, &spr_write_generic,
1066 0x00000000);
1067 /* XXX : not implemented */
1068 spr_register(env, SPR_IABR, "IABR",
1069 SPR_NOACCESS, SPR_NOACCESS,
1070 &spr_read_generic, &spr_write_generic,
1071 0x00000000);
1072 }
1073
1074 /* SPR specific to PowerPC 601 implementation */
1075 static void gen_spr_601 (CPUPPCState *env)
1076 {
1077 /* Multiplication/division register */
1078 /* MQ */
1079 spr_register(env, SPR_MQ, "MQ",
1080 &spr_read_generic, &spr_write_generic,
1081 &spr_read_generic, &spr_write_generic,
1082 0x00000000);
1083 /* RTC registers */
1084 spr_register(env, SPR_601_RTCU, "RTCU",
1085 SPR_NOACCESS, SPR_NOACCESS,
1086 SPR_NOACCESS, &spr_write_601_rtcu,
1087 0x00000000);
1088 spr_register(env, SPR_601_VRTCU, "RTCU",
1089 &spr_read_601_rtcu, SPR_NOACCESS,
1090 &spr_read_601_rtcu, SPR_NOACCESS,
1091 0x00000000);
1092 spr_register(env, SPR_601_RTCL, "RTCL",
1093 SPR_NOACCESS, SPR_NOACCESS,
1094 SPR_NOACCESS, &spr_write_601_rtcl,
1095 0x00000000);
1096 spr_register(env, SPR_601_VRTCL, "RTCL",
1097 &spr_read_601_rtcl, SPR_NOACCESS,
1098 &spr_read_601_rtcl, SPR_NOACCESS,
1099 0x00000000);
1100 /* Timer */
1101 #if 0 /* ? */
1102 spr_register(env, SPR_601_UDECR, "UDECR",
1103 &spr_read_decr, SPR_NOACCESS,
1104 &spr_read_decr, SPR_NOACCESS,
1105 0x00000000);
1106 #endif
1107 /* External access control */
1108 /* XXX : not implemented */
1109 spr_register(env, SPR_EAR, "EAR",
1110 SPR_NOACCESS, SPR_NOACCESS,
1111 &spr_read_generic, &spr_write_generic,
1112 0x00000000);
1113 /* Memory management */
1114 #if !defined(CONFIG_USER_ONLY)
1115 spr_register(env, SPR_IBAT0U, "IBAT0U",
1116 SPR_NOACCESS, SPR_NOACCESS,
1117 &spr_read_601_ubat, &spr_write_601_ubatu,
1118 0x00000000);
1119 spr_register(env, SPR_IBAT0L, "IBAT0L",
1120 SPR_NOACCESS, SPR_NOACCESS,
1121 &spr_read_601_ubat, &spr_write_601_ubatl,
1122 0x00000000);
1123 spr_register(env, SPR_IBAT1U, "IBAT1U",
1124 SPR_NOACCESS, SPR_NOACCESS,
1125 &spr_read_601_ubat, &spr_write_601_ubatu,
1126 0x00000000);
1127 spr_register(env, SPR_IBAT1L, "IBAT1L",
1128 SPR_NOACCESS, SPR_NOACCESS,
1129 &spr_read_601_ubat, &spr_write_601_ubatl,
1130 0x00000000);
1131 spr_register(env, SPR_IBAT2U, "IBAT2U",
1132 SPR_NOACCESS, SPR_NOACCESS,
1133 &spr_read_601_ubat, &spr_write_601_ubatu,
1134 0x00000000);
1135 spr_register(env, SPR_IBAT2L, "IBAT2L",
1136 SPR_NOACCESS, SPR_NOACCESS,
1137 &spr_read_601_ubat, &spr_write_601_ubatl,
1138 0x00000000);
1139 spr_register(env, SPR_IBAT3U, "IBAT3U",
1140 SPR_NOACCESS, SPR_NOACCESS,
1141 &spr_read_601_ubat, &spr_write_601_ubatu,
1142 0x00000000);
1143 spr_register(env, SPR_IBAT3L, "IBAT3L",
1144 SPR_NOACCESS, SPR_NOACCESS,
1145 &spr_read_601_ubat, &spr_write_601_ubatl,
1146 0x00000000);
1147 env->nb_BATs = 4;
1148 #endif
1149 }
1150
1151 static void gen_spr_74xx (CPUPPCState *env)
1152 {
1153 /* Processor identification */
1154 spr_register(env, SPR_PIR, "PIR",
1155 SPR_NOACCESS, SPR_NOACCESS,
1156 &spr_read_generic, &spr_write_pir,
1157 0x00000000);
1158 /* XXX : not implemented */
1159 spr_register(env, SPR_MMCR2, "MMCR2",
1160 SPR_NOACCESS, SPR_NOACCESS,
1161 &spr_read_generic, &spr_write_generic,
1162 0x00000000);
1163 /* XXX : not implemented */
1164 spr_register(env, SPR_UMMCR2, "UMMCR2",
1165 &spr_read_ureg, SPR_NOACCESS,
1166 &spr_read_ureg, SPR_NOACCESS,
1167 0x00000000);
1168 /* XXX: not implemented */
1169 spr_register(env, SPR_BAMR, "BAMR",
1170 SPR_NOACCESS, SPR_NOACCESS,
1171 &spr_read_generic, &spr_write_generic,
1172 0x00000000);
1173 /* XXX : not implemented */
1174 spr_register(env, SPR_UBAMR, "UBAMR",
1175 &spr_read_ureg, SPR_NOACCESS,
1176 &spr_read_ureg, SPR_NOACCESS,
1177 0x00000000);
1178 /* XXX : not implemented */
1179 spr_register(env, SPR_MSSCR0, "MSSCR0",
1180 SPR_NOACCESS, SPR_NOACCESS,
1181 &spr_read_generic, &spr_write_generic,
1182 0x00000000);
1183 /* Hardware implementation registers */
1184 /* XXX : not implemented */
1185 spr_register(env, SPR_HID0, "HID0",
1186 SPR_NOACCESS, SPR_NOACCESS,
1187 &spr_read_generic, &spr_write_generic,
1188 0x00000000);
1189 /* XXX : not implemented */
1190 spr_register(env, SPR_HID1, "HID1",
1191 SPR_NOACCESS, SPR_NOACCESS,
1192 &spr_read_generic, &spr_write_generic,
1193 0x00000000);
1194 /* Altivec */
1195 spr_register(env, SPR_VRSAVE, "VRSAVE",
1196 &spr_read_generic, &spr_write_generic,
1197 &spr_read_generic, &spr_write_generic,
1198 0x00000000);
1199 }
1200
1201 static void gen_l3_ctrl (CPUPPCState *env)
1202 {
1203 /* L3CR */
1204 /* XXX : not implemented */
1205 spr_register(env, SPR_L3CR, "L3CR",
1206 SPR_NOACCESS, SPR_NOACCESS,
1207 &spr_read_generic, &spr_write_generic,
1208 0x00000000);
1209 /* L3ITCR0 */
1210 /* XXX : not implemented */
1211 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1212 SPR_NOACCESS, SPR_NOACCESS,
1213 &spr_read_generic, &spr_write_generic,
1214 0x00000000);
1215 /* L3ITCR1 */
1216 /* XXX : not implemented */
1217 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1218 SPR_NOACCESS, SPR_NOACCESS,
1219 &spr_read_generic, &spr_write_generic,
1220 0x00000000);
1221 /* L3ITCR2 */
1222 /* XXX : not implemented */
1223 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1224 SPR_NOACCESS, SPR_NOACCESS,
1225 &spr_read_generic, &spr_write_generic,
1226 0x00000000);
1227 /* L3ITCR3 */
1228 /* XXX : not implemented */
1229 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1230 SPR_NOACCESS, SPR_NOACCESS,
1231 &spr_read_generic, &spr_write_generic,
1232 0x00000000);
1233 /* L3OHCR */
1234 /* XXX : not implemented */
1235 spr_register(env, SPR_L3OHCR, "L3OHCR",
1236 SPR_NOACCESS, SPR_NOACCESS,
1237 &spr_read_generic, &spr_write_generic,
1238 0x00000000);
1239 /* L3PM */
1240 /* XXX : not implemented */
1241 spr_register(env, SPR_L3PM, "L3PM",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_generic, &spr_write_generic,
1244 0x00000000);
1245 }
1246
1247 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1248 {
1249 #if !defined(CONFIG_USER_ONLY)
1250 env->nb_tlb = nb_tlbs;
1251 env->nb_ways = nb_ways;
1252 env->id_tlbs = 1;
1253 /* XXX : not implemented */
1254 spr_register(env, SPR_PTEHI, "PTEHI",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_generic, &spr_write_generic,
1257 0x00000000);
1258 /* XXX : not implemented */
1259 spr_register(env, SPR_PTELO, "PTELO",
1260 SPR_NOACCESS, SPR_NOACCESS,
1261 &spr_read_generic, &spr_write_generic,
1262 0x00000000);
1263 /* XXX : not implemented */
1264 spr_register(env, SPR_TLBMISS, "TLBMISS",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_generic,
1267 0x00000000);
1268 #endif
1269 }
1270
1271 /* PowerPC BookE SPR */
1272 static void gen_spr_BookE (CPUPPCState *env)
1273 {
1274 /* Processor identification */
1275 spr_register(env, SPR_BOOKE_PIR, "PIR",
1276 SPR_NOACCESS, SPR_NOACCESS,
1277 &spr_read_generic, &spr_write_pir,
1278 0x00000000);
1279 /* Interrupt processing */
1280 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1281 SPR_NOACCESS, SPR_NOACCESS,
1282 &spr_read_generic, &spr_write_generic,
1283 0x00000000);
1284 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_generic, &spr_write_generic,
1287 0x00000000);
1288 #if 0
1289 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1290 SPR_NOACCESS, SPR_NOACCESS,
1291 &spr_read_generic, &spr_write_generic,
1292 0x00000000);
1293 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1294 SPR_NOACCESS, SPR_NOACCESS,
1295 &spr_read_generic, &spr_write_generic,
1296 0x00000000);
1297 #endif
1298 /* Debug */
1299 /* XXX : not implemented */
1300 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1301 SPR_NOACCESS, SPR_NOACCESS,
1302 &spr_read_generic, &spr_write_generic,
1303 0x00000000);
1304 /* XXX : not implemented */
1305 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, &spr_write_generic,
1308 0x00000000);
1309 /* XXX : not implemented */
1310 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1311 SPR_NOACCESS, SPR_NOACCESS,
1312 &spr_read_generic, &spr_write_generic,
1313 0x00000000);
1314 /* XXX : not implemented */
1315 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1316 SPR_NOACCESS, SPR_NOACCESS,
1317 &spr_read_generic, &spr_write_generic,
1318 0x00000000);
1319 /* XXX : not implemented */
1320 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1321 SPR_NOACCESS, SPR_NOACCESS,
1322 &spr_read_generic, &spr_write_generic,
1323 0x00000000);
1324 /* XXX : not implemented */
1325 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1326 SPR_NOACCESS, SPR_NOACCESS,
1327 &spr_read_generic, &spr_write_generic,
1328 0x00000000);
1329 /* XXX : not implemented */
1330 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1333 0x00000000);
1334 /* XXX : not implemented */
1335 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1336 SPR_NOACCESS, SPR_NOACCESS,
1337 &spr_read_generic, &spr_write_generic,
1338 0x00000000);
1339 /* XXX : not implemented */
1340 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1341 SPR_NOACCESS, SPR_NOACCESS,
1342 &spr_read_generic, &spr_write_generic,
1343 0x00000000);
1344 /* XXX : not implemented */
1345 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1346 SPR_NOACCESS, SPR_NOACCESS,
1347 &spr_read_generic, &spr_write_generic,
1348 0x00000000);
1349 /* XXX : not implemented */
1350 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_generic,
1353 0x00000000);
1354 /* XXX : not implemented */
1355 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1356 SPR_NOACCESS, SPR_NOACCESS,
1357 &spr_read_generic, &spr_write_clear,
1358 0x00000000);
1359 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1360 SPR_NOACCESS, SPR_NOACCESS,
1361 &spr_read_generic, &spr_write_generic,
1362 0x00000000);
1363 spr_register(env, SPR_BOOKE_ESR, "ESR",
1364 SPR_NOACCESS, SPR_NOACCESS,
1365 &spr_read_generic, &spr_write_generic,
1366 0x00000000);
1367 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1368 SPR_NOACCESS, SPR_NOACCESS,
1369 &spr_read_generic, &spr_write_excp_prefix,
1370 0x00000000);
1371 /* Exception vectors */
1372 spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1373 SPR_NOACCESS, SPR_NOACCESS,
1374 &spr_read_generic, &spr_write_excp_vector,
1375 0x00000000);
1376 spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1377 SPR_NOACCESS, SPR_NOACCESS,
1378 &spr_read_generic, &spr_write_excp_vector,
1379 0x00000000);
1380 spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1381 SPR_NOACCESS, SPR_NOACCESS,
1382 &spr_read_generic, &spr_write_excp_vector,
1383 0x00000000);
1384 spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1385 SPR_NOACCESS, SPR_NOACCESS,
1386 &spr_read_generic, &spr_write_excp_vector,
1387 0x00000000);
1388 spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1389 SPR_NOACCESS, SPR_NOACCESS,
1390 &spr_read_generic, &spr_write_excp_vector,
1391 0x00000000);
1392 spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1393 SPR_NOACCESS, SPR_NOACCESS,
1394 &spr_read_generic, &spr_write_excp_vector,
1395 0x00000000);
1396 spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1397 SPR_NOACCESS, SPR_NOACCESS,
1398 &spr_read_generic, &spr_write_excp_vector,
1399 0x00000000);
1400 spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1401 SPR_NOACCESS, SPR_NOACCESS,
1402 &spr_read_generic, &spr_write_excp_vector,
1403 0x00000000);
1404 spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1405 SPR_NOACCESS, SPR_NOACCESS,
1406 &spr_read_generic, &spr_write_excp_vector,
1407 0x00000000);
1408 spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1409 SPR_NOACCESS, SPR_NOACCESS,
1410 &spr_read_generic, &spr_write_excp_vector,
1411 0x00000000);
1412 spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1413 SPR_NOACCESS, SPR_NOACCESS,
1414 &spr_read_generic, &spr_write_excp_vector,
1415 0x00000000);
1416 spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1417 SPR_NOACCESS, SPR_NOACCESS,
1418 &spr_read_generic, &spr_write_excp_vector,
1419 0x00000000);
1420 spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1421 SPR_NOACCESS, SPR_NOACCESS,
1422 &spr_read_generic, &spr_write_excp_vector,
1423 0x00000000);
1424 spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1425 SPR_NOACCESS, SPR_NOACCESS,
1426 &spr_read_generic, &spr_write_excp_vector,
1427 0x00000000);
1428 spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1429 SPR_NOACCESS, SPR_NOACCESS,
1430 &spr_read_generic, &spr_write_excp_vector,
1431 0x00000000);
1432 spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1433 SPR_NOACCESS, SPR_NOACCESS,
1434 &spr_read_generic, &spr_write_excp_vector,
1435 0x00000000);
1436 #if 0
1437 spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1438 SPR_NOACCESS, SPR_NOACCESS,
1439 &spr_read_generic, &spr_write_excp_vector,
1440 0x00000000);
1441 spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1442 SPR_NOACCESS, SPR_NOACCESS,
1443 &spr_read_generic, &spr_write_excp_vector,
1444 0x00000000);
1445 spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1446 SPR_NOACCESS, SPR_NOACCESS,
1447 &spr_read_generic, &spr_write_excp_vector,
1448 0x00000000);
1449 spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1450 SPR_NOACCESS, SPR_NOACCESS,
1451 &spr_read_generic, &spr_write_excp_vector,
1452 0x00000000);
1453 spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1454 SPR_NOACCESS, SPR_NOACCESS,
1455 &spr_read_generic, &spr_write_excp_vector,
1456 0x00000000);
1457 spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1458 SPR_NOACCESS, SPR_NOACCESS,
1459 &spr_read_generic, &spr_write_excp_vector,
1460 0x00000000);
1461 #endif
1462 spr_register(env, SPR_BOOKE_PID, "PID",
1463 SPR_NOACCESS, SPR_NOACCESS,
1464 &spr_read_generic, &spr_write_generic,
1465 0x00000000);
1466 spr_register(env, SPR_BOOKE_TCR, "TCR",
1467 SPR_NOACCESS, SPR_NOACCESS,
1468 &spr_read_generic, &spr_write_booke_tcr,
1469 0x00000000);
1470 spr_register(env, SPR_BOOKE_TSR, "TSR",
1471 SPR_NOACCESS, SPR_NOACCESS,
1472 &spr_read_generic, &spr_write_booke_tsr,
1473 0x00000000);
1474 /* Timer */
1475 spr_register(env, SPR_DECR, "DECR",
1476 SPR_NOACCESS, SPR_NOACCESS,
1477 &spr_read_decr, &spr_write_decr,
1478 0x00000000);
1479 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1480 SPR_NOACCESS, SPR_NOACCESS,
1481 SPR_NOACCESS, &spr_write_generic,
1482 0x00000000);
1483 /* SPRGs */
1484 spr_register(env, SPR_USPRG0, "USPRG0",
1485 &spr_read_generic, &spr_write_generic,
1486 &spr_read_generic, &spr_write_generic,
1487 0x00000000);
1488 spr_register(env, SPR_SPRG4, "SPRG4",
1489 SPR_NOACCESS, SPR_NOACCESS,
1490 &spr_read_generic, &spr_write_generic,
1491 0x00000000);
1492 spr_register(env, SPR_USPRG4, "USPRG4",
1493 &spr_read_ureg, SPR_NOACCESS,
1494 &spr_read_ureg, SPR_NOACCESS,
1495 0x00000000);
1496 spr_register(env, SPR_SPRG5, "SPRG5",
1497 SPR_NOACCESS, SPR_NOACCESS,
1498 &spr_read_generic, &spr_write_generic,
1499 0x00000000);
1500 spr_register(env, SPR_USPRG5, "USPRG5",
1501 &spr_read_ureg, SPR_NOACCESS,
1502 &spr_read_ureg, SPR_NOACCESS,
1503 0x00000000);
1504 spr_register(env, SPR_SPRG6, "SPRG6",
1505 SPR_NOACCESS, SPR_NOACCESS,
1506 &spr_read_generic, &spr_write_generic,
1507 0x00000000);
1508 spr_register(env, SPR_USPRG6, "USPRG6",
1509 &spr_read_ureg, SPR_NOACCESS,
1510 &spr_read_ureg, SPR_NOACCESS,
1511 0x00000000);
1512 spr_register(env, SPR_SPRG7, "SPRG7",
1513 SPR_NOACCESS, SPR_NOACCESS,
1514 &spr_read_generic, &spr_write_generic,
1515 0x00000000);
1516 spr_register(env, SPR_USPRG7, "USPRG7",
1517 &spr_read_ureg, SPR_NOACCESS,
1518 &spr_read_ureg, SPR_NOACCESS,
1519 0x00000000);
1520 }
1521
1522 /* FSL storage control registers */
1523 static void gen_spr_BookE_FSL (CPUPPCState *env)
1524 {
1525 #if !defined(CONFIG_USER_ONLY)
1526 /* TLB assist registers */
1527 /* XXX : not implemented */
1528 spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1529 SPR_NOACCESS, SPR_NOACCESS,
1530 &spr_read_generic, &spr_write_generic,
1531 0x00000000);
1532 /* XXX : not implemented */
1533 spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1534 SPR_NOACCESS, SPR_NOACCESS,
1535 &spr_read_generic, &spr_write_generic,
1536 0x00000000);
1537 /* XXX : not implemented */
1538 spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1539 SPR_NOACCESS, SPR_NOACCESS,
1540 &spr_read_generic, &spr_write_generic,
1541 0x00000000);
1542 /* XXX : not implemented */
1543 spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1544 SPR_NOACCESS, SPR_NOACCESS,
1545 &spr_read_generic, &spr_write_generic,
1546 0x00000000);
1547 /* XXX : not implemented */
1548 spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_generic,
1551 0x00000000);
1552 /* XXX : not implemented */
1553 spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
1557 /* XXX : not implemented */
1558 spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_generic, &spr_write_generic,
1561 0x00000000);
1562 if (env->nb_pids > 1) {
1563 /* XXX : not implemented */
1564 spr_register(env, SPR_BOOKE_PID1, "PID1",
1565 SPR_NOACCESS, SPR_NOACCESS,
1566 &spr_read_generic, &spr_write_generic,
1567 0x00000000);
1568 }
1569 if (env->nb_pids > 2) {
1570 /* XXX : not implemented */
1571 spr_register(env, SPR_BOOKE_PID2, "PID2",
1572 SPR_NOACCESS, SPR_NOACCESS,
1573 &spr_read_generic, &spr_write_generic,
1574 0x00000000);
1575 }
1576 /* XXX : not implemented */
1577 spr_register(env, SPR_MMUCFG, "MMUCFG",
1578 SPR_NOACCESS, SPR_NOACCESS,
1579 &spr_read_generic, SPR_NOACCESS,
1580 0x00000000); /* TOFIX */
1581 /* XXX : not implemented */
1582 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
1583 SPR_NOACCESS, SPR_NOACCESS,
1584 &spr_read_generic, &spr_write_generic,
1585 0x00000000); /* TOFIX */
1586 switch (env->nb_ways) {
1587 case 4:
1588 /* XXX : not implemented */
1589 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1590 SPR_NOACCESS, SPR_NOACCESS,
1591 &spr_read_generic, SPR_NOACCESS,
1592 0x00000000); /* TOFIX */
1593 /* Fallthru */
1594 case 3:
1595 /* XXX : not implemented */
1596 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1597 SPR_NOACCESS, SPR_NOACCESS,
1598 &spr_read_generic, SPR_NOACCESS,
1599 0x00000000); /* TOFIX */
1600 /* Fallthru */
1601 case 2:
1602 /* XXX : not implemented */
1603 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1604 SPR_NOACCESS, SPR_NOACCESS,
1605 &spr_read_generic, SPR_NOACCESS,
1606 0x00000000); /* TOFIX */
1607 /* Fallthru */
1608 case 1:
1609 /* XXX : not implemented */
1610 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1611 SPR_NOACCESS, SPR_NOACCESS,
1612 &spr_read_generic, SPR_NOACCESS,
1613 0x00000000); /* TOFIX */
1614 /* Fallthru */
1615 case 0:
1616 default:
1617 break;
1618 }
1619 #endif
1620 }
1621
1622 /* SPR specific to PowerPC 440 implementation */
1623 static void gen_spr_440 (CPUPPCState *env)
1624 {
1625 /* Cache control */
1626 /* XXX : not implemented */
1627 spr_register(env, SPR_440_DNV0, "DNV0",
1628 SPR_NOACCESS, SPR_NOACCESS,
1629 &spr_read_generic, &spr_write_generic,
1630 0x00000000);
1631 /* XXX : not implemented */
1632 spr_register(env, SPR_440_DNV1, "DNV1",
1633 SPR_NOACCESS, SPR_NOACCESS,
1634 &spr_read_generic, &spr_write_generic,
1635 0x00000000);
1636 /* XXX : not implemented */
1637 spr_register(env, SPR_440_DNV2, "DNV2",
1638 SPR_NOACCESS, SPR_NOACCESS,
1639 &spr_read_generic, &spr_write_generic,
1640 0x00000000);
1641 /* XXX : not implemented */
1642 spr_register(env, SPR_440_DNV3, "DNV3",
1643 SPR_NOACCESS, SPR_NOACCESS,
1644 &spr_read_generic, &spr_write_generic,
1645 0x00000000);
1646 /* XXX : not implemented */
1647 spr_register(env, SPR_440_DTV0, "DTV0",
1648 SPR_NOACCESS, SPR_NOACCESS,
1649 &spr_read_generic, &spr_write_generic,
1650 0x00000000);
1651 /* XXX : not implemented */
1652 spr_register(env, SPR_440_DTV1, "DTV1",
1653 SPR_NOACCESS, SPR_NOACCESS,
1654 &spr_read_generic, &spr_write_generic,
1655 0x00000000);
1656 /* XXX : not implemented */
1657 spr_register(env, SPR_440_DTV2, "DTV2",
1658 SPR_NOACCESS, SPR_NOACCESS,
1659 &spr_read_generic, &spr_write_generic,
1660 0x00000000);
1661 /* XXX : not implemented */
1662 spr_register(env, SPR_440_DTV3, "DTV3",
1663 SPR_NOACCESS, SPR_NOACCESS,
1664 &spr_read_generic, &spr_write_generic,
1665 0x00000000);
1666 /* XXX : not implemented */
1667 spr_register(env, SPR_440_DVLIM, "DVLIM",
1668 SPR_NOACCESS, SPR_NOACCESS,
1669 &spr_read_generic, &spr_write_generic,
1670 0x00000000);
1671 /* XXX : not implemented */
1672 spr_register(env, SPR_440_INV0, "INV0",
1673 SPR_NOACCESS, SPR_NOACCESS,
1674 &spr_read_generic, &spr_write_generic,
1675 0x00000000);
1676 /* XXX : not implemented */
1677 spr_register(env, SPR_440_INV1, "INV1",
1678 SPR_NOACCESS, SPR_NOACCESS,
1679 &spr_read_generic, &spr_write_generic,
1680 0x00000000);
1681 /* XXX : not implemented */
1682 spr_register(env, SPR_440_INV2, "INV2",
1683 SPR_NOACCESS, SPR_NOACCESS,
1684 &spr_read_generic, &spr_write_generic,
1685 0x00000000);
1686 /* XXX : not implemented */
1687 spr_register(env, SPR_440_INV3, "INV3",
1688 SPR_NOACCESS, SPR_NOACCESS,
1689 &spr_read_generic, &spr_write_generic,
1690 0x00000000);
1691 /* XXX : not implemented */
1692 spr_register(env, SPR_440_ITV0, "ITV0",
1693 SPR_NOACCESS, SPR_NOACCESS,
1694 &spr_read_generic, &spr_write_generic,
1695 0x00000000);
1696 /* XXX : not implemented */
1697 spr_register(env, SPR_440_ITV1, "ITV1",
1698 SPR_NOACCESS, SPR_NOACCESS,
1699 &spr_read_generic, &spr_write_generic,
1700 0x00000000);
1701 /* XXX : not implemented */
1702 spr_register(env, SPR_440_ITV2, "ITV2",
1703 SPR_NOACCESS, SPR_NOACCESS,
1704 &spr_read_generic, &spr_write_generic,
1705 0x00000000);
1706 /* XXX : not implemented */
1707 spr_register(env, SPR_440_ITV3, "ITV3",
1708 SPR_NOACCESS, SPR_NOACCESS,
1709 &spr_read_generic, &spr_write_generic,
1710 0x00000000);
1711 /* XXX : not implemented */
1712 spr_register(env, SPR_440_IVLIM, "IVLIM",
1713 SPR_NOACCESS, SPR_NOACCESS,
1714 &spr_read_generic, &spr_write_generic,
1715 0x00000000);
1716 /* Cache debug */
1717 /* XXX : not implemented */
1718 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, SPR_NOACCESS,
1721 0x00000000);
1722 /* XXX : not implemented */
1723 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_generic, SPR_NOACCESS,
1726 0x00000000);
1727 /* XXX : not implemented */
1728 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, SPR_NOACCESS,
1731 0x00000000);
1732 /* XXX : not implemented */
1733 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1734 SPR_NOACCESS, SPR_NOACCESS,
1735 &spr_read_generic, SPR_NOACCESS,
1736 0x00000000);
1737 /* XXX : not implemented */
1738 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, SPR_NOACCESS,
1741 0x00000000);
1742 /* XXX : not implemented */
1743 spr_register(env, SPR_440_DBDR, "DBDR",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, &spr_write_generic,
1746 0x00000000);
1747 /* Processor control */
1748 spr_register(env, SPR_4xx_CCR0, "CCR0",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1753 SPR_NOACCESS, SPR_NOACCESS,
1754 &spr_read_generic, SPR_NOACCESS,
1755 0x00000000);
1756 /* Storage control */
1757 spr_register(env, SPR_440_MMUCR, "MMUCR",
1758 SPR_NOACCESS, SPR_NOACCESS,
1759 &spr_read_generic, &spr_write_generic,
1760 0x00000000);
1761 }
1762
1763 /* SPR shared between PowerPC 40x implementations */
1764 static void gen_spr_40x (CPUPPCState *env)
1765 {
1766 /* Cache */
1767 /* not emulated, as Qemu do not emulate caches */
1768 spr_register(env, SPR_40x_DCCR, "DCCR",
1769 SPR_NOACCESS, SPR_NOACCESS,
1770 &spr_read_generic, &spr_write_generic,
1771 0x00000000);
1772 /* not emulated, as Qemu do not emulate caches */
1773 spr_register(env, SPR_40x_ICCR, "ICCR",
1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, &spr_write_generic,
1776 0x00000000);
1777 /* not emulated, as Qemu do not emulate caches */
1778 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1779 SPR_NOACCESS, SPR_NOACCESS,
1780 &spr_read_generic, SPR_NOACCESS,
1781 0x00000000);
1782 /* Exception */
1783 spr_register(env, SPR_40x_DEAR, "DEAR",
1784 SPR_NOACCESS, SPR_NOACCESS,
1785 &spr_read_generic, &spr_write_generic,
1786 0x00000000);
1787 spr_register(env, SPR_40x_ESR, "ESR",
1788 SPR_NOACCESS, SPR_NOACCESS,
1789 &spr_read_generic, &spr_write_generic,
1790 0x00000000);
1791 spr_register(env, SPR_40x_EVPR, "EVPR",
1792 SPR_NOACCESS, SPR_NOACCESS,
1793 &spr_read_generic, &spr_write_excp_prefix,
1794 0x00000000);
1795 spr_register(env, SPR_40x_SRR2, "SRR2",
1796 &spr_read_generic, &spr_write_generic,
1797 &spr_read_generic, &spr_write_generic,
1798 0x00000000);
1799 spr_register(env, SPR_40x_SRR3, "SRR3",
1800 &spr_read_generic, &spr_write_generic,
1801 &spr_read_generic, &spr_write_generic,
1802 0x00000000);
1803 /* Timers */
1804 spr_register(env, SPR_40x_PIT, "PIT",
1805 SPR_NOACCESS, SPR_NOACCESS,
1806 &spr_read_40x_pit, &spr_write_40x_pit,
1807 0x00000000);
1808 spr_register(env, SPR_40x_TCR, "TCR",
1809 SPR_NOACCESS, SPR_NOACCESS,
1810 &spr_read_generic, &spr_write_booke_tcr,
1811 0x00000000);
1812 spr_register(env, SPR_40x_TSR, "TSR",
1813 SPR_NOACCESS, SPR_NOACCESS,
1814 &spr_read_generic, &spr_write_booke_tsr,
1815 0x00000000);
1816 }
1817
1818 /* SPR specific to PowerPC 405 implementation */
1819 static void gen_spr_405 (CPUPPCState *env)
1820 {
1821 /* MMU */
1822 spr_register(env, SPR_40x_PID, "PID",
1823 SPR_NOACCESS, SPR_NOACCESS,
1824 &spr_read_generic, &spr_write_generic,
1825 0x00000000);
1826 spr_register(env, SPR_4xx_CCR0, "CCR0",
1827 SPR_NOACCESS, SPR_NOACCESS,
1828 &spr_read_generic, &spr_write_generic,
1829 0x00700000);
1830 /* Debug interface */
1831 /* XXX : not implemented */
1832 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1833 SPR_NOACCESS, SPR_NOACCESS,
1834 &spr_read_generic, &spr_write_40x_dbcr0,
1835 0x00000000);
1836 /* XXX : not implemented */
1837 spr_register(env, SPR_405_DBCR1, "DBCR1",
1838 SPR_NOACCESS, SPR_NOACCESS,
1839 &spr_read_generic, &spr_write_generic,
1840 0x00000000);
1841 /* XXX : not implemented */
1842 spr_register(env, SPR_40x_DBSR, "DBSR",
1843 SPR_NOACCESS, SPR_NOACCESS,
1844 &spr_read_generic, &spr_write_clear,
1845 /* Last reset was system reset */
1846 0x00000300);
1847 /* XXX : not implemented */
1848 spr_register(env, SPR_40x_DAC1, "DAC1",
1849 SPR_NOACCESS, SPR_NOACCESS,
1850 &spr_read_generic, &spr_write_generic,
1851 0x00000000);
1852 spr_register(env, SPR_40x_DAC2, "DAC2",
1853 SPR_NOACCESS, SPR_NOACCESS,
1854 &spr_read_generic, &spr_write_generic,
1855 0x00000000);
1856 /* XXX : not implemented */
1857 spr_register(env, SPR_405_DVC1, "DVC1",
1858 SPR_NOACCESS, SPR_NOACCESS,
1859 &spr_read_generic, &spr_write_generic,
1860 0x00000000);
1861 /* XXX : not implemented */
1862 spr_register(env, SPR_405_DVC2, "DVC2",
1863 SPR_NOACCESS, SPR_NOACCESS,
1864 &spr_read_generic, &spr_write_generic,
1865 0x00000000);
1866 /* XXX : not implemented */
1867 spr_register(env, SPR_40x_IAC1, "IAC1",
1868 SPR_NOACCESS, SPR_NOACCESS,
1869 &spr_read_generic, &spr_write_generic,
1870 0x00000000);
1871 spr_register(env, SPR_40x_IAC2, "IAC2",
1872 SPR_NOACCESS, SPR_NOACCESS,
1873 &spr_read_generic, &spr_write_generic,
1874 0x00000000);
1875 /* XXX : not implemented */
1876 spr_register(env, SPR_405_IAC3, "IAC3",
1877 SPR_NOACCESS, SPR_NOACCESS,
1878 &spr_read_generic, &spr_write_generic,
1879 0x00000000);
1880 /* XXX : not implemented */
1881 spr_register(env, SPR_405_IAC4, "IAC4",
1882 SPR_NOACCESS, SPR_NOACCESS,
1883 &spr_read_generic, &spr_write_generic,
1884 0x00000000);
1885 /* Storage control */
1886 /* XXX: TODO: not implemented */
1887 spr_register(env, SPR_405_SLER, "SLER",
1888 SPR_NOACCESS, SPR_NOACCESS,
1889 &spr_read_generic, &spr_write_40x_sler,
1890 0x00000000);
1891 spr_register(env, SPR_40x_ZPR, "ZPR",
1892 SPR_NOACCESS, SPR_NOACCESS,
1893 &spr_read_generic, &spr_write_generic,
1894 0x00000000);
1895 /* XXX : not implemented */
1896 spr_register(env, SPR_405_SU0R, "SU0R",
1897 SPR_NOACCESS, SPR_NOACCESS,
1898 &spr_read_generic, &spr_write_generic,
1899 0x00000000);
1900 /* SPRG */
1901 spr_register(env, SPR_USPRG0, "USPRG0",
1902 &spr_read_ureg, SPR_NOACCESS,
1903 &spr_read_ureg, SPR_NOACCESS,
1904 0x00000000);
1905 spr_register(env, SPR_SPRG4, "SPRG4",
1906 SPR_NOACCESS, SPR_NOACCESS,
1907 &spr_read_generic, &spr_write_generic,
1908 0x00000000);
1909 spr_register(env, SPR_USPRG4, "USPRG4",
1910 &spr_read_ureg, SPR_NOACCESS,
1911 &spr_read_ureg, SPR_NOACCESS,
1912 0x00000000);
1913 spr_register(env, SPR_SPRG5, "SPRG5",
1914 SPR_NOACCESS, SPR_NOACCESS,
1915 spr_read_generic, &spr_write_generic,
1916 0x00000000);
1917 spr_register(env, SPR_USPRG5, "USPRG5",
1918 &spr_read_ureg, SPR_NOACCESS,
1919 &spr_read_ureg, SPR_NOACCESS,
1920 0x00000000);
1921 spr_register(env, SPR_SPRG6, "SPRG6",
1922 SPR_NOACCESS, SPR_NOACCESS,
1923 spr_read_generic, &spr_write_generic,
1924 0x00000000);
1925 spr_register(env, SPR_USPRG6, "USPRG6",
1926 &spr_read_ureg, SPR_NOACCESS,
1927 &spr_read_ureg, SPR_NOACCESS,
1928 0x00000000);
1929 spr_register(env, SPR_SPRG7, "SPRG7",
1930 SPR_NOACCESS, SPR_NOACCESS,
1931 spr_read_generic, &spr_write_generic,
1932 0x00000000);
1933 spr_register(env, SPR_USPRG7, "USPRG7",
1934 &spr_read_ureg, SPR_NOACCESS,
1935 &spr_read_ureg, SPR_NOACCESS,
1936 0x00000000);
1937 }
1938
1939 /* SPR shared between PowerPC 401 & 403 implementations */
1940 static void gen_spr_401_403 (CPUPPCState *env)
1941 {
1942 /* Time base */
1943 spr_register(env, SPR_403_VTBL, "TBL",
1944 &spr_read_tbl, SPR_NOACCESS,
1945 &spr_read_tbl, SPR_NOACCESS,
1946 0x00000000);
1947 spr_register(env, SPR_403_TBL, "TBL",
1948 SPR_NOACCESS, SPR_NOACCESS,
1949 SPR_NOACCESS, &spr_write_tbl,
1950 0x00000000);
1951 spr_register(env, SPR_403_VTBU, "TBU",
1952 &spr_read_tbu, SPR_NOACCESS,
1953 &spr_read_tbu, SPR_NOACCESS,
1954 0x00000000);
1955 spr_register(env, SPR_403_TBU, "TBU",
1956 SPR_NOACCESS, SPR_NOACCESS,
1957 SPR_NOACCESS, &spr_write_tbu,
1958 0x00000000);
1959 /* Debug */
1960 /* not emulated, as Qemu do not emulate caches */
1961 spr_register(env, SPR_403_CDBCR, "CDBCR",
1962 SPR_NOACCESS, SPR_NOACCESS,
1963 &spr_read_generic, &spr_write_generic,
1964 0x00000000);
1965 }
1966
1967 /* SPR specific to PowerPC 401 implementation */
1968 static void gen_spr_401 (CPUPPCState *env)
1969 {
1970 /* Debug interface */
1971 /* XXX : not implemented */
1972 spr_register(env, SPR_40x_DBCR0, "DBCR",
1973 SPR_NOACCESS, SPR_NOACCESS,
1974 &spr_read_generic, &spr_write_40x_dbcr0,
1975 0x00000000);
1976 /* XXX : not implemented */
1977 spr_register(env, SPR_40x_DBSR, "DBSR",
1978 SPR_NOACCESS, SPR_NOACCESS,
1979 &spr_read_generic, &spr_write_clear,
1980 /* Last reset was system reset */
1981 0x00000300);
1982 /* XXX : not implemented */
1983 spr_register(env, SPR_40x_DAC1, "DAC",
1984 SPR_NOACCESS, SPR_NOACCESS,
1985 &spr_read_generic, &spr_write_generic,
1986 0x00000000);
1987 /* XXX : not implemented */
1988 spr_register(env, SPR_40x_IAC1, "IAC",
1989 SPR_NOACCESS, SPR_NOACCESS,
1990 &spr_read_generic, &spr_write_generic,
1991 0x00000000);
1992 /* Storage control */
1993 /* XXX: TODO: not implemented */
1994 spr_register(env, SPR_405_SLER, "SLER",
1995 SPR_NOACCESS, SPR_NOACCESS,
1996 &spr_read_generic, &spr_write_40x_sler,
1997 0x00000000);
1998 /* not emulated, as Qemu never does speculative access */
1999 spr_register(env, SPR_40x_SGR, "SGR",
2000 SPR_NOACCESS, SPR_NOACCESS,
2001 &spr_read_generic, &spr_write_generic,
2002 0xFFFFFFFF);
2003 /* not emulated, as Qemu do not emulate caches */
2004 spr_register(env, SPR_40x_DCWR, "DCWR",
2005 SPR_NOACCESS, SPR_NOACCESS,
2006 &spr_read_generic, &spr_write_generic,
2007 0x00000000);
2008 }
2009
2010 static void gen_spr_401x2 (CPUPPCState *env)
2011 {
2012 gen_spr_401(env);
2013 spr_register(env, SPR_40x_PID, "PID",
2014 SPR_NOACCESS, SPR_NOACCESS,
2015 &spr_read_generic, &spr_write_generic,
2016 0x00000000);
2017 spr_register(env, SPR_40x_ZPR, "ZPR",
2018 SPR_NOACCESS, SPR_NOACCESS,
2019 &spr_read_generic, &spr_write_generic,
2020 0x00000000);
2021 }
2022
2023 /* SPR specific to PowerPC 403 implementation */
2024 static void gen_spr_403 (CPUPPCState *env)
2025 {
2026 /* Debug interface */
2027 /* XXX : not implemented */
2028 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2029 SPR_NOACCESS, SPR_NOACCESS,
2030 &spr_read_generic, &spr_write_40x_dbcr0,
2031 0x00000000);
2032 /* XXX : not implemented */
2033 spr_register(env, SPR_40x_DBSR, "DBSR",
2034 SPR_NOACCESS, SPR_NOACCESS,
2035 &spr_read_generic, &spr_write_clear,
2036 /* Last reset was system reset */
2037 0x00000300);
2038 /* XXX : not implemented */
2039 spr_register(env, SPR_40x_DAC1, "DAC1",
2040 SPR_NOACCESS, SPR_NOACCESS,
2041 &spr_read_generic, &spr_write_generic,
2042 0x00000000);
2043 /* XXX : not implemented */
2044 spr_register(env, SPR_40x_DAC2, "DAC2",
2045 SPR_NOACCESS, SPR_NOACCESS,
2046 &spr_read_generic, &spr_write_generic,
2047 0x00000000);
2048 /* XXX : not implemented */
2049 spr_register(env, SPR_40x_IAC1, "IAC1",
2050 SPR_NOACCESS, SPR_NOACCESS,
2051 &spr_read_generic, &spr_write_generic,
2052 0x00000000);
2053 /* XXX : not implemented */
2054 spr_register(env, SPR_40x_IAC2, "IAC2",
2055 SPR_NOACCESS, SPR_NOACCESS,
2056 &spr_read_generic, &spr_write_generic,
2057 0x00000000);
2058 }
2059
2060 static void gen_spr_403_real (CPUPPCState *env)
2061 {
2062 spr_register(env, SPR_403_PBL1, "PBL1",
2063 SPR_NOACCESS, SPR_NOACCESS,
2064 &spr_read_403_pbr, &spr_write_403_pbr,
2065 0x00000000);
2066 spr_register(env, SPR_403_PBU1, "PBU1",
2067 SPR_NOACCESS, SPR_NOACCESS,
2068 &spr_read_403_pbr, &spr_write_403_pbr,
2069 0x00000000);
2070 spr_register(env, SPR_403_PBL2, "PBL2",
2071 SPR_NOACCESS, SPR_NOACCESS,
2072 &spr_read_403_pbr, &spr_write_403_pbr,
2073 0x00000000);
2074 spr_register(env, SPR_403_PBU2, "PBU2",
2075 SPR_NOACCESS, SPR_NOACCESS,
2076 &spr_read_403_pbr, &spr_write_403_pbr,
2077 0x00000000);
2078 }
2079
2080 static void gen_spr_403_mmu (CPUPPCState *env)
2081 {
2082 /* MMU */
2083 spr_register(env, SPR_40x_PID, "PID",
2084 SPR_NOACCESS, SPR_NOACCESS,
2085 &spr_read_generic, &spr_write_generic,
2086 0x00000000);
2087 spr_register(env, SPR_40x_ZPR, "ZPR",
2088 SPR_NOACCESS, SPR_NOACCESS,
2089 &spr_read_generic, &spr_write_generic,
2090 0x00000000);
2091 }
2092
2093 /* SPR specific to PowerPC compression coprocessor extension */
2094 static void gen_spr_compress (CPUPPCState *env)
2095 {
2096 /* XXX : not implemented */
2097 spr_register(env, SPR_401_SKR, "SKR",
2098 SPR_NOACCESS, SPR_NOACCESS,
2099 &spr_read_generic, &spr_write_generic,
2100 0x00000000);
2101 }
2102
2103 #if defined (TARGET_PPC64)
2104 /* SPR specific to PowerPC 620 */
2105 static void gen_spr_620 (CPUPPCState *env)
2106 {
2107 /* XXX : not implemented */
2108 spr_register(env, SPR_620_PMR0, "PMR0",
2109 SPR_NOACCESS, SPR_NOACCESS,
2110 &spr_read_generic, &spr_write_generic,
2111 0x00000000);
2112 /* XXX : not implemented */
2113 spr_register(env, SPR_620_PMR1, "PMR1",
2114 SPR_NOACCESS, SPR_NOACCESS,
2115 &spr_read_generic, &spr_write_generic,
2116 0x00000000);
2117 /* XXX : not implemented */
2118 spr_register(env, SPR_620_PMR2, "PMR2",
2119 SPR_NOACCESS, SPR_NOACCESS,
2120 &spr_read_generic, &spr_write_generic,
2121 0x00000000);
2122 /* XXX : not implemented */
2123 spr_register(env, SPR_620_PMR3, "PMR3",
2124 SPR_NOACCESS, SPR_NOACCESS,
2125 &spr_read_generic, &spr_write_generic,
2126 0x00000000);
2127 /* XXX : not implemented */
2128 spr_register(env, SPR_620_PMR4, "PMR4",
2129 SPR_NOACCESS, SPR_NOACCESS,
2130 &spr_read_generic, &spr_write_generic,
2131 0x00000000);
2132 /* XXX : not implemented */
2133 spr_register(env, SPR_620_PMR5, "PMR5",
2134 SPR_NOACCESS, SPR_NOACCESS,
2135 &spr_read_generic, &spr_write_generic,
2136 0x00000000);
2137 /* XXX : not implemented */
2138 spr_register(env, SPR_620_PMR6, "PMR6",
2139 SPR_NOACCESS, SPR_NOACCESS,
2140 &spr_read_generic, &spr_write_generic,
2141 0x00000000);
2142 /* XXX : not implemented */
2143 spr_register(env, SPR_620_PMR7, "PMR7",
2144 SPR_NOACCESS, SPR_NOACCESS,
2145 &spr_read_generic, &spr_write_generic,
2146 0x00000000);
2147 /* XXX : not implemented */
2148 spr_register(env, SPR_620_PMR8, "PMR8",
2149 SPR_NOACCESS, SPR_NOACCESS,
2150 &spr_read_generic, &spr_write_generic,
2151 0x00000000);
2152 /* XXX : not implemented */
2153 spr_register(env, SPR_620_PMR9, "PMR9",
2154 SPR_NOACCESS, SPR_NOACCESS,
2155 &spr_read_generic, &spr_write_generic,
2156 0x00000000);
2157 /* XXX : not implemented */
2158 spr_register(env, SPR_620_PMRA, "PMR10",
2159 SPR_NOACCESS, SPR_NOACCESS,
2160 &spr_read_generic, &spr_write_generic,
2161 0x00000000);
2162 /* XXX : not implemented */
2163 spr_register(env, SPR_620_PMRB, "PMR11",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 &spr_read_generic, &spr_write_generic,
2166 0x00000000);
2167 /* XXX : not implemented */
2168 spr_register(env, SPR_620_PMRC, "PMR12",
2169 SPR_NOACCESS, SPR_NOACCESS,
2170 &spr_read_generic, &spr_write_generic,
2171 0x00000000);
2172 /* XXX : not implemented */
2173 spr_register(env, SPR_620_PMRD, "PMR13",
2174 SPR_NOACCESS, SPR_NOACCESS,
2175 &spr_read_generic, &spr_write_generic,
2176 0x00000000);
2177 /* XXX : not implemented */
2178 spr_register(env, SPR_620_PMRE, "PMR14",
2179 SPR_NOACCESS, SPR_NOACCESS,
2180 &spr_read_generic, &spr_write_generic,
2181 0x00000000);
2182 /* XXX : not implemented */
2183 spr_register(env, SPR_620_PMRF, "PMR15",
2184 SPR_NOACCESS, SPR_NOACCESS,
2185 &spr_read_generic, &spr_write_generic,
2186 0x00000000);
2187 /* XXX : not implemented */
2188 spr_register(env, SPR_620_HID8, "HID8",
2189 SPR_NOACCESS, SPR_NOACCESS,
2190 &spr_read_generic, &spr_write_generic,
2191 0x00000000);
2192 /* XXX : not implemented */
2193 spr_register(env, SPR_620_HID9, "HID9",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 &spr_read_generic, &spr_write_generic,
2196 0x00000000);
2197 }
2198 #endif /* defined (TARGET_PPC64) */
2199
2200 // XXX: TODO
2201 /*
2202 * AMR => SPR 29 (Power 2.04)
2203 * CTRL => SPR 136 (Power 2.04)
2204 * CTRL => SPR 152 (Power 2.04)
2205 * SCOMC => SPR 276 (64 bits ?)
2206 * SCOMD => SPR 277 (64 bits ?)
2207 * TBU40 => SPR 286 (Power 2.04 hypv)
2208 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2209 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2210 * HDSISR => SPR 306 (Power 2.04 hypv)
2211 * HDAR => SPR 307 (Power 2.04 hypv)
2212 * PURR => SPR 309 (Power 2.04 hypv)
2213 * HDEC => SPR 310 (Power 2.04 hypv)
2214 * HIOR => SPR 311 (hypv)
2215 * RMOR => SPR 312 (970)
2216 * HRMOR => SPR 313 (Power 2.04 hypv)
2217 * HSRR0 => SPR 314 (Power 2.04 hypv)
2218 * HSRR1 => SPR 315 (Power 2.04 hypv)
2219 * LPCR => SPR 316 (970)
2220 * LPIDR => SPR 317 (970)
2221 * SPEFSCR => SPR 512 (Power 2.04 emb)
2222 * EPR => SPR 702 (Power 2.04 emb)
2223 * perf => 768-783 (Power 2.04)
2224 * perf => 784-799 (Power 2.04)
2225 * PPR => SPR 896 (Power 2.04)
2226 * EPLC => SPR 947 (Power 2.04 emb)
2227 * EPSC => SPR 948 (Power 2.04 emb)
2228 * DABRX => 1015 (Power 2.04 hypv)
2229 * FPECR => SPR 1022 (?)
2230 * ... and more (thermal management, performance counters, ...)
2231 */
2232
2233 /*****************************************************************************/
2234 /* Exception vectors models */
2235 static void init_excp_4xx_real (CPUPPCState *env)
2236 {
2237 #if !defined(CONFIG_USER_ONLY)
2238 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2239 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2240 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2241 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2242 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2243 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2244 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2245 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2246 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2247 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2248 env->excp_prefix = 0x00000000;
2249 env->ivor_mask = 0x0000FFF0;
2250 env->ivpr_mask = 0xFFFF0000;
2251 /* Hardware reset vector */
2252 env->hreset_vector = 0xFFFFFFFCUL;
2253 #endif
2254 }
2255
2256 static void init_excp_4xx_softmmu (CPUPPCState *env)
2257 {
2258 #if !defined(CONFIG_USER_ONLY)
2259 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2260 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2261 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2262 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2263 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2264 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2265 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2266 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2267 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2268 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2269 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2270 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2271 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2272 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2273 env->excp_prefix = 0x00000000;
2274 env->ivor_mask = 0x0000FFF0;
2275 env->ivpr_mask = 0xFFFF0000;
2276 /* Hardware reset vector */
2277 env->hreset_vector = 0xFFFFFFFCUL;
2278 #endif
2279 }
2280
2281 static void init_excp_BookE (CPUPPCState *env)
2282 {
2283 #if !defined(CONFIG_USER_ONLY)
2284 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2285 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2286 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2287 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2288 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2289 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2290 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2291 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2292 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2293 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2294 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2295 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2296 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2297 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2298 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2299 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2300 env->excp_prefix = 0x00000000;
2301 env->ivor_mask = 0x0000FFE0;
2302 env->ivpr_mask = 0xFFFF0000;
2303 /* Hardware reset vector */
2304 env->hreset_vector = 0xFFFFFFFCUL;
2305 #endif
2306 }
2307
2308 static void init_excp_601 (CPUPPCState *env)
2309 {
2310 #if !defined(CONFIG_USER_ONLY)
2311 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2312 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2313 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2314 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2315 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2316 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2317 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2318 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2319 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2320 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2321 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2322 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2323 env->excp_prefix = 0xFFF00000;
2324 /* Hardware reset vector */
2325 env->hreset_vector = 0x00000100UL;
2326 #endif
2327 }
2328
2329 static void init_excp_602 (CPUPPCState *env)
2330 {
2331 #if !defined(CONFIG_USER_ONLY)
2332 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2333 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2334 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2335 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2336 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2337 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2338 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2339 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2340 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2341 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2342 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2343 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2344 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2345 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2346 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2347 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2348 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2349 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2350 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2351 env->excp_prefix = 0xFFF00000;
2352 /* Hardware reset vector */
2353 env->hreset_vector = 0xFFFFFFFCUL;
2354 #endif
2355 }
2356
2357 static void init_excp_603 (CPUPPCState *env)
2358 {
2359 #if !defined(CONFIG_USER_ONLY)
2360 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2361 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2362 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2363 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2364 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2365 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2366 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2367 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2368 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2369 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2370 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2371 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2372 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2373 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2374 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2375 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2376 /* Hardware reset vector */
2377 env->hreset_vector = 0xFFFFFFFCUL;
2378 #endif
2379 }
2380
2381 static void init_excp_G2 (CPUPPCState *env)
2382 {
2383 #if !defined(CONFIG_USER_ONLY)
2384 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2385 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2386 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2387 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2388 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2389 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2390 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2391 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2392 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2393 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2394 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2395 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2396 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2397 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2398 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2399 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2400 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2401 /* Hardware reset vector */
2402 env->hreset_vector = 0xFFFFFFFCUL;
2403 #endif
2404 }
2405
2406 static void init_excp_604 (CPUPPCState *env)
2407 {
2408 #if !defined(CONFIG_USER_ONLY)
2409 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2410 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2411 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2412 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2413 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2414 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2415 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2416 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2417 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2418 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2419 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2420 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2421 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2422 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2423 /* Hardware reset vector */
2424 env->hreset_vector = 0xFFFFFFFCUL;
2425 #endif
2426 }
2427
2428 #if defined(TARGET_PPC64)
2429 static void init_excp_620 (CPUPPCState *env)
2430 {
2431 #if !defined(CONFIG_USER_ONLY)
2432 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2433 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2434 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2435 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2436 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2437 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2438 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2439 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2440 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2441 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2442 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2443 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2444 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2445 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2446 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2447 /* Hardware reset vector */
2448 env->hreset_vector = 0x0000000000000100ULL; /* ? */
2449 #endif
2450 }
2451 #endif /* defined(TARGET_PPC64) */
2452
2453 static void init_excp_7x0 (CPUPPCState *env)
2454 {
2455 #if !defined(CONFIG_USER_ONLY)
2456 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2457 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2458 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2459 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2460 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2461 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2462 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2463 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2464 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2465 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2466 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2467 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2468 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2469 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2470 /* Hardware reset vector */
2471 env->hreset_vector = 0xFFFFFFFCUL;
2472 #endif
2473 }
2474
2475 static void init_excp_750FX (CPUPPCState *env)
2476 {
2477 #if !defined(CONFIG_USER_ONLY)
2478 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2479 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2480 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2481 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2482 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2483 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2484 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2485 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2486 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2487 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2488 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2489 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2490 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2491 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2492 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2493 /* Hardware reset vector */
2494 env->hreset_vector = 0xFFFFFFFCUL;
2495 #endif
2496 }
2497
2498 /* XXX: Check if this is correct */
2499 static void init_excp_7x5 (CPUPPCState *env)
2500 {
2501 #if !defined(CONFIG_USER_ONLY)
2502 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2503 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2504 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2505 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2506 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2507 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2508 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2509 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2510 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2511 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2512 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2513 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2514 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2515 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2516 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2517 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2518 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2519 /* Hardware reset vector */
2520 env->hreset_vector = 0xFFFFFFFCUL;
2521 #endif
2522 }
2523
2524 static void init_excp_7400 (CPUPPCState *env)
2525 {
2526 #if !defined(CONFIG_USER_ONLY)
2527 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2528 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2529 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2530 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2531 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2532 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2533 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2534 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2535 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2536 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2537 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2538 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2539 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2540 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2541 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2542 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2543 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2544 /* Hardware reset vector */
2545 env->hreset_vector = 0xFFFFFFFCUL;
2546 #endif
2547 }
2548
2549 static void init_excp_7450 (CPUPPCState *env)
2550 {
2551 #if !defined(CONFIG_USER_ONLY)
2552 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2553 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2554 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2555 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2556 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2557 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2558 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2559 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2560 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2561 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2562 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2563 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2564 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2565 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2566 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2567 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2568 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2569 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2570 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2571 /* Hardware reset vector */
2572 env->hreset_vector = 0xFFFFFFFCUL;
2573 #endif
2574 }
2575
2576 #if defined (TARGET_PPC64)
2577 static void init_excp_970 (CPUPPCState *env)
2578 {
2579 #if !defined(CONFIG_USER_ONLY)
2580 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2581 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2582 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2583 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2584 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2585 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2586 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2587 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2588 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2589 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2590 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2591 #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2592 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2593 #endif
2594 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2595 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2596 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2597 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2598 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2599 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2600 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2601 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2602 /* Hardware reset vector */
2603 env->hreset_vector = 0x0000000000000100ULL;
2604 #endif
2605 }
2606 #endif
2607
2608 /*****************************************************************************/
2609 /* PowerPC implementations definitions */
2610
2611 /* PowerPC 40x instruction set */
2612 #define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_CACHE_DCBZ | PPC_EMB_COMMON)
2613
2614 /* PowerPC 401 */
2615 #define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \
2616 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2617 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2618 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
2619 #define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx)
2620 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
2621 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
2622 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
2623 #define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2624
2625 static void init_proc_401 (CPUPPCState *env)
2626 {
2627 gen_spr_40x(env);
2628 gen_spr_401_403(env);
2629 gen_spr_401(env);
2630 init_excp_4xx_real(env);
2631 env->dcache_line_size = 32;
2632 env->icache_line_size = 32;
2633 /* Allocate hardware IRQ controller */
2634 ppc40x_irq_init(env);
2635 }
2636
2637 /* PowerPC 401x2 */
2638 #define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | \
2639 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2640 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2641 PPC_CACHE_DCBA | PPC_MFTB | \
2642 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2643 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
2644 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
2645 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
2646 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
2647 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
2648 #define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2649
2650 static void init_proc_401x2 (CPUPPCState *env)
2651 {
2652 gen_spr_40x(env);
2653 gen_spr_401_403(env);
2654 gen_spr_401x2(env);
2655 gen_spr_compress(env);
2656 /* Memory management */
2657 #if !defined(CONFIG_USER_ONLY)
2658 env->nb_tlb = 64;
2659 env->nb_ways = 1;
2660 env->id_tlbs = 0;
2661 #endif
2662 init_excp_4xx_softmmu(env);
2663 env->dcache_line_size = 32;
2664 env->icache_line_size = 32;
2665 /* Allocate hardware IRQ controller */
2666 ppc40x_irq_init(env);
2667 }
2668
2669 /* PowerPC 401x3 */
2670 #define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \
2671 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2672 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2673 PPC_CACHE_DCBA | PPC_MFTB | \
2674 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2675 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
2676 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
2677 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
2678 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
2679 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
2680 #define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2681
2682 __attribute__ (( unused ))
2683 static void init_proc_401x3 (CPUPPCState *env)
2684 {
2685 gen_spr_40x(env);
2686 gen_spr_401_403(env);
2687 gen_spr_401(env);
2688 gen_spr_401x2(env);
2689 gen_spr_compress(env);
2690 init_excp_4xx_softmmu(env);
2691 env->dcache_line_size = 32;
2692 env->icache_line_size = 32;
2693 /* Allocate hardware IRQ controller */
2694 ppc40x_irq_init(env);
2695 }
2696
2697 /* IOP480 */
2698 #define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \
2699 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2700 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2701 PPC_CACHE_DCBA | \
2702 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2703 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
2704 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
2705 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
2706 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
2707 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
2708 #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2709
2710 static void init_proc_IOP480 (CPUPPCState *env)
2711 {
2712 gen_spr_40x(env);
2713 gen_spr_401_403(env);
2714 gen_spr_401x2(env);
2715 gen_spr_compress(env);
2716 /* Memory management */
2717 #if !defined(CONFIG_USER_ONLY)
2718 env->nb_tlb = 64;
2719 env->nb_ways = 1;
2720 env->id_tlbs = 0;
2721 #endif
2722 init_excp_4xx_softmmu(env);
2723 env->dcache_line_size = 32;
2724 env->icache_line_size = 32;
2725 /* Allocate hardware IRQ controller */
2726 ppc40x_irq_init(env);
2727 }
2728
2729 /* PowerPC 403 */
2730 #define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | \
2731 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2732 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2733 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
2734 #define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx)
2735 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
2736 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
2737 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
2738 #define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2739
2740 static void init_proc_403 (CPUPPCState *env)
2741 {
2742 gen_spr_40x(env);
2743 gen_spr_401_403(env);
2744 gen_spr_403(env);
2745 gen_spr_403_real(env);
2746 init_excp_4xx_real(env);
2747 env->dcache_line_size = 32;
2748 env->icache_line_size = 32;
2749 /* Allocate hardware IRQ controller */
2750 ppc40x_irq_init(env);
2751 #if !defined(CONFIG_USER_ONLY)
2752 /* Hardware reset vector */
2753 env->hreset_vector = 0xFFFFFFFCUL;
2754 #endif
2755 }
2756
2757 /* PowerPC 403 GCX */
2758 #define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | \
2759 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2760 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2761 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2762 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
2763 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
2764 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
2765 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
2766 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
2767 #define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2768
2769 static void init_proc_403GCX (CPUPPCState *env)
2770 {
2771 gen_spr_40x(env);
2772 gen_spr_401_403(env);
2773 gen_spr_403(env);
2774 gen_spr_403_real(env);
2775 gen_spr_403_mmu(env);
2776 /* Bus access control */
2777 /* not emulated, as Qemu never does speculative access */
2778 spr_register(env, SPR_40x_SGR, "SGR",
2779 SPR_NOACCESS, SPR_NOACCESS,
2780 &spr_read_generic, &spr_write_generic,
2781 0xFFFFFFFF);
2782 /* not emulated, as Qemu do not emulate caches */
2783 spr_register(env, SPR_40x_DCWR, "DCWR",
2784 SPR_NOACCESS, SPR_NOACCESS,
2785 &spr_read_generic, &spr_write_generic,
2786 0x00000000);
2787 /* Memory management */
2788 #if !defined(CONFIG_USER_ONLY)
2789 env->nb_tlb = 64;
2790 env->nb_ways = 1;
2791 env->id_tlbs = 0;
2792 #endif
2793 init_excp_4xx_softmmu(env);
2794 env->dcache_line_size = 32;
2795 env->icache_line_size = 32;
2796 /* Allocate hardware IRQ controller */
2797 ppc40x_irq_init(env);
2798 }
2799
2800 /* PowerPC 405 */
2801 #define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_MFTB | \
2802 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2803 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2804 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
2805 PPC_405_MAC)
2806 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
2807 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
2808 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
2809 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
2810 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
2811 #define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2812 POWERPC_FLAG_DE)
2813
2814 static void init_proc_405 (CPUPPCState *env)
2815 {
2816 /* Time base */
2817 gen_tbl(env);
2818 gen_spr_40x(env);
2819 gen_spr_405(env);
2820 /* Bus access control */
2821 /* not emulated, as Qemu never does speculative access */
2822 spr_register(env, SPR_40x_SGR, "SGR",
2823 SPR_NOACCESS, SPR_NOACCESS,
2824 &spr_read_generic, &spr_write_generic,
2825 0xFFFFFFFF);
2826 /* not emulated, as Qemu do not emulate caches */
2827 spr_register(env, SPR_40x_DCWR, "DCWR",
2828 SPR_NOACCESS, SPR_NOACCESS,
2829 &spr_read_generic, &spr_write_generic,
2830 0x00000000);
2831 /* Memory management */
2832 #if !defined(CONFIG_USER_ONLY)
2833 env->nb_tlb = 64;
2834 env->nb_ways = 1;
2835 env->id_tlbs = 0;
2836 #endif
2837 init_excp_4xx_softmmu(env);
2838 env->dcache_line_size = 32;
2839 env->icache_line_size = 32;
2840 /* Allocate hardware IRQ controller */
2841 ppc40x_irq_init(env);
2842 }
2843
2844 /* PowerPC 440 EP */
2845 #define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | \
2846 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2847 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2848 PPC_440_SPEC | PPC_RFMCI)
2849 #define POWERPC_MSRM_440EP (0x000000000006D630ULL)
2850 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
2851 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
2852 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
2853 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
2854 #define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2855 POWERPC_FLAG_DE)
2856
2857 static void init_proc_440EP (CPUPPCState *env)
2858 {
2859 /* Time base */
2860 gen_tbl(env);
2861 gen_spr_BookE(env);
2862 gen_spr_440(env);
2863 /* XXX : not implemented */
2864 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2865 SPR_NOACCESS, SPR_NOACCESS,
2866 &spr_read_generic, &spr_write_generic,
2867 0x00000000);
2868 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2869 SPR_NOACCESS, SPR_NOACCESS,
2870 &spr_read_generic, &spr_write_generic,
2871 0x00000000);
2872 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2873 SPR_NOACCESS, SPR_NOACCESS,
2874 &spr_read_generic, &spr_write_generic,
2875 0x00000000);
2876 /* XXX : not implemented */
2877 spr_register(env, SPR_440_CCR1, "CCR1",
2878 SPR_NOACCESS, SPR_NOACCESS,
2879 &spr_read_generic, &spr_write_generic,
2880 0x00000000);
2881 /* Memory management */
2882 #if !defined(CONFIG_USER_ONLY)
2883 env->nb_tlb = 64;
2884 env->nb_ways = 1;
2885 env->id_tlbs = 0;
2886 #endif
2887 init_excp_BookE(env);
2888 env->dcache_line_size = 32;
2889 env->icache_line_size = 32;
2890 /* XXX: TODO: allocate internal IRQ controller */
2891 }
2892
2893 /* PowerPC 440 GP */
2894 #define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | \
2895 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2896 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2897 PPC_405_MAC | PPC_440_SPEC)
2898 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
2899 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
2900 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
2901 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
2902 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
2903 #define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2904 POWERPC_FLAG_DE)
2905
2906 static void init_proc_440GP (CPUPPCState *env)
2907 {
2908 /* Time base */
2909 gen_tbl(env);
2910 gen_spr_BookE(env);
2911 gen_spr_440(env);
2912 /* Memory management */
2913 #if !defined(CONFIG_USER_ONLY)
2914 env->nb_tlb = 64;
2915 env->nb_ways = 1;
2916 env->id_tlbs = 0;
2917 #endif
2918 init_excp_BookE(env);
2919 env->dcache_line_size = 32;
2920 env->icache_line_size = 32;
2921 /* XXX: TODO: allocate internal IRQ controller */
2922 }
2923
2924 /* PowerPC 440x4 */
2925 #define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \
2926 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2927 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2928 PPC_440_SPEC)
2929 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
2930 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
2931 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
2932 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
2933 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
2934 #define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2935 POWERPC_FLAG_DE)
2936
2937 __attribute__ (( unused ))
2938 static void init_proc_440x4 (CPUPPCState *env)
2939 {
2940 /* Time base */
2941 gen_tbl(env);
2942 gen_spr_BookE(env);
2943 gen_spr_440(env);
2944 /* Memory management */
2945 #if !defined(CONFIG_USER_ONLY)
2946 env->nb_tlb = 64;
2947 env->nb_ways = 1;
2948 env->id_tlbs = 0;
2949 #endif
2950 init_excp_BookE(env);
2951 env->dcache_line_size = 32;
2952 env->icache_line_size = 32;
2953 /* XXX: TODO: allocate internal IRQ controller */
2954 }
2955
2956 /* PowerPC 440x5 */
2957 #define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \
2958 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2959 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2960 PPC_440_SPEC | PPC_RFMCI)
2961 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
2962 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
2963 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
2964 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
2965 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
2966 #define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2967 POWERPC_FLAG_DE)
2968
2969 static void init_proc_440x5 (CPUPPCState *env)
2970 {
2971 /* Time base */
2972 gen_tbl(env);
2973 gen_spr_BookE(env);
2974 gen_spr_440(env);
2975 /* XXX : not implemented */
2976 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2977 SPR_NOACCESS, SPR_NOACCESS,
2978 &spr_read_generic, &spr_write_generic,
2979 0x00000000);
2980 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2981 SPR_NOACCESS, SPR_NOACCESS,
2982 &spr_read_generic, &spr_write_generic,
2983 0x00000000);
2984 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2985 SPR_NOACCESS, SPR_NOACCESS,
2986 &spr_read_generic, &spr_write_generic,
2987 0x00000000);
2988 /* XXX : not implemented */
2989 spr_register(env, SPR_440_CCR1, "CCR1",
2990 SPR_NOACCESS, SPR_NOACCESS,
2991 &spr_read_generic, &spr_write_generic,
2992 0x00000000);
2993 /* Memory management */
2994 #if !defined(CONFIG_USER_ONLY)
2995 env->nb_tlb = 64;
2996 env->nb_ways = 1;
2997 env->id_tlbs = 0;
2998 #endif
2999 init_excp_BookE(env);
3000 env->dcache_line_size = 32;
3001 env->icache_line_size = 32;
3002 /* XXX: TODO: allocate internal IRQ controller */
3003 }
3004
3005 /* PowerPC 460 (guessed) */
3006 #define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | \
3007 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3008 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
3009 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3010 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3011 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3012 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3013 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3014 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3015 #define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3016 POWERPC_FLAG_DE)
3017
3018 __attribute__ (( unused ))
3019 static void init_proc_460 (CPUPPCState *env)
3020 {
3021 /* Time base */
3022 gen_tbl(env);
3023 gen_spr_BookE(env);
3024 gen_spr_440(env);
3025 /* XXX : not implemented */
3026 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3027 SPR_NOACCESS, SPR_NOACCESS,
3028 &spr_read_generic, &spr_write_generic,
3029 0x00000000);
3030 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3031 SPR_NOACCESS, SPR_NOACCESS,
3032 &spr_read_generic, &spr_write_generic,
3033 0x00000000);
3034 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3035 SPR_NOACCESS, SPR_NOACCESS,
3036 &spr_read_generic, &spr_write_generic,
3037 0x00000000);
3038 /* XXX : not implemented */
3039 spr_register(env, SPR_440_CCR1, "CCR1",
3040 SPR_NOACCESS, SPR_NOACCESS,
3041 &spr_read_generic, &spr_write_generic,
3042 0x00000000);
3043 /* XXX : not implemented */
3044 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3045 &spr_read_generic, &spr_write_generic,
3046 &spr_read_generic, &spr_write_generic,
3047 0x00000000);
3048 /* Memory management */
3049 #if !defined(CONFIG_USER_ONLY)
3050 env->nb_tlb = 64;
3051 env->nb_ways = 1;
3052 env->id_tlbs = 0;
3053 #endif
3054 init_excp_BookE(env);
3055 env->dcache_line_size = 32;
3056 env->icache_line_size = 32;
3057 /* XXX: TODO: allocate internal IRQ controller */
3058 }
3059
3060 /* PowerPC 460F (guessed) */
3061 #define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
3062 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3063 PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
3064 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
3065 PPC_FLOAT_STFIWX | \
3066 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
3067 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3068 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3069 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3070 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3071 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3072 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3073 #define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3074 POWERPC_FLAG_DE)
3075
3076 __attribute__ (( unused ))
3077 static void init_proc_460F (CPUPPCState *env)
3078 {
3079 /* Time base */
3080 gen_tbl(env);
3081 gen_spr_BookE(env);
3082 gen_spr_440(env);
3083 /* XXX : not implemented */
3084 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3085 SPR_NOACCESS, SPR_NOACCESS,
3086 &spr_read_generic, &spr_write_generic,
3087 0x00000000);
3088 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3089 SPR_NOACCESS, SPR_NOACCESS,
3090 &spr_read_generic, &spr_write_generic,
3091 0x00000000);
3092 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3093 SPR_NOACCESS, SPR_NOACCESS,
3094 &spr_read_generic, &spr_write_generic,
3095 0x00000000);
3096 /* XXX : not implemented */
3097 spr_register(env, SPR_440_CCR1, "CCR1",
3098 SPR_NOACCESS, SPR_NOACCESS,
3099 &spr_read_generic, &spr_write_generic,
3100 0x00000000);
3101 /* XXX : not implemented */
3102 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3103 &spr_read_generic, &spr_write_generic,
3104 &spr_read_generic, &spr_write_generic,
3105 0x00000000);
3106 /* Memory management */
3107 #if !defined(CONFIG_USER_ONLY)
3108 env->nb_tlb = 64;
3109 env->nb_ways = 1;
3110 env->id_tlbs = 0;
3111 #endif
3112 init_excp_BookE(env);
3113 env->dcache_line_size = 32;
3114 env->icache_line_size = 32;
3115 /* XXX: TODO: allocate internal IRQ controller */
3116 }
3117
3118 /* Generic BookE PowerPC */
3119 #define POWERPC_INSNS_BookE (POWERPC_INSNS_EMB | \
3120 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3121 PPC_CACHE_DCBA | \
3122 PPC_FLOAT | PPC_FLOAT_FSQRT | \
3123 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3124 PPC_FLOAT_FSEL | PPC_FLOAT_STFIW | \
3125 PPC_BOOKE)
3126 #define POWERPC_MSRM_BookE (0x000000000006D630ULL)
3127 #define POWERPC_MMU_BookE (POWERPC_MMU_BOOKE)
3128 #define POWERPC_EXCP_BookE (POWERPC_EXCP_BOOKE)
3129 #define POWERPC_INPUT_BookE (PPC_FLAGS_INPUT_BookE)
3130 #define POWERPC_BFDM_BookE (bfd_mach_ppc_403)
3131 #define POWERPC_FLAG_BookE (POWERPC_FLAG_NONE)
3132
3133 __attribute__ (( unused ))
3134 static void init_proc_BookE (CPUPPCState *env)
3135 {
3136 init_excp_BookE(env);
3137 env->dcache_line_size = 32;
3138 env->icache_line_size = 32;
3139 }
3140
3141 /* e200 core */
3142
3143 /* e300 core */
3144
3145 /* e500 core */
3146 #define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | \
3147 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3148 PPC_CACHE_DCBA | \
3149 PPC_BOOKE | PPC_E500_VECTOR)
3150 #define POWERPC_MMU_e500 (POWERPC_MMU_SOFT_4xx)
3151 #define POWERPC_EXCP_e500 (POWERPC_EXCP_40x)
3152 #define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
3153 #define POWERPC_BFDM_e500 (bfd_mach_ppc_403)
3154 #define POWERPC_FLAG_e500 (POWERPC_FLAG_SPE)
3155
3156 __attribute__ (( unused ))
3157 static void init_proc_e500 (CPUPPCState *env)
3158 {
3159 /* Time base */
3160 gen_tbl(env);
3161 gen_spr_BookE(env);
3162 /* Memory management */
3163 gen_spr_BookE_FSL(env);
3164 #if !defined(CONFIG_USER_ONLY)
3165 env->nb_tlb = 64;
3166 env->nb_ways = 1;
3167 env->id_tlbs = 0;
3168 #endif
3169 init_excp_BookE(env);
3170 env->dcache_line_size = 32;
3171 env->icache_line_size = 32;
3172 /* XXX: TODO: allocate internal IRQ controller */
3173 }
3174
3175 /* e600 core */
3176
3177 /* Non-embedded PowerPC */
3178 /* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
3179 #define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
3180 PPC_MEM_EIEIO | PPC_MEM_TLBIE)
3181 /* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
3182 #define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
3183 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3184 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3185 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB | \
3186 PPC_SEGMENT)
3187
3188 /* POWER : same as 601, without mfmsr, mfsr */
3189 #if defined(TODO)
3190 #define POWERPC_INSNS_POWER (XXX_TODO)
3191 /* POWER RSC (from RAD6000) */
3192 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
3193 #endif /* TODO */
3194
3195 /* PowerPC 601 */
3196 #define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ | \
3197 PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
3198 #define POWERPC_MSRM_601 (0x000000000000FD70ULL)
3199 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
3200 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
3201 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
3202 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
3203 #define POWERPC_FLAG_601 (POWERPC_FLAG_SE)
3204
3205 static void init_proc_601 (CPUPPCState *env)
3206 {
3207 gen_spr_ne_601(env);
3208 gen_spr_601(env);
3209 /* Hardware implementation registers */
3210 /* XXX : not implemented */
3211 spr_register(env, SPR_HID0, "HID0",
3212 SPR_NOACCESS, SPR_NOACCESS,
3213 &spr_read_generic, &spr_write_generic,
3214 0x00000000);
3215 /* XXX : not implemented */
3216 spr_register(env, SPR_HID1, "HID1",
3217 SPR_NOACCESS, SPR_NOACCESS,
3218 &spr_read_generic, &spr_write_generic,
3219 0x00000000);
3220 /* XXX : not implemented */
3221 spr_register(env, SPR_601_HID2, "HID2",
3222 SPR_NOACCESS, SPR_NOACCESS,
3223 &spr_read_generic, &spr_write_generic,
3224 0x00000000);
3225 /* XXX : not implemented */
3226 spr_register(env, SPR_601_HID5, "HID5",
3227 SPR_NOACCESS, SPR_NOACCESS,
3228 &spr_read_generic, &spr_write_generic,
3229 0x00000000);
3230 /* XXX : not implemented */
3231 spr_register(env, SPR_601_HID15, "HID15",
3232 SPR_NOACCESS, SPR_NOACCESS,
3233 &spr_read_generic, &spr_write_generic,
3234 0x00000000);
3235 /* Memory management */
3236 #if !defined(CONFIG_USER_ONLY)
3237 env->nb_tlb = 64;
3238 env->nb_ways = 2;
3239 env->id_tlbs = 0;
3240 #endif
3241 init_excp_601(env);
3242 env->dcache_line_size = 64;
3243 env->icache_line_size = 64;
3244 /* XXX: TODO: allocate internal IRQ controller */
3245 }
3246
3247 /* PowerPC 602 */
3248 #define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
3249 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3250 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3251 PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\
3252 PPC_SEGMENT | PPC_602_SPEC)
3253 #define POWERPC_MSRM_602 (0x000000000033FF73ULL)
3254 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
3255 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
3256 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
3257 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
3258 #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3259 POWERPC_FLAG_BE)
3260
3261 static void init_proc_602 (CPUPPCState *env)
3262 {
3263 gen_spr_ne_601(env);
3264 gen_spr_602(env);
3265 /* Time base */
3266 gen_tbl(env);
3267 /* hardware implementation registers */
3268 /* XXX : not implemented */
3269 spr_register(env, SPR_HID0, "HID0",
3270 SPR_NOACCESS, SPR_NOACCESS,
3271 &spr_read_generic, &spr_write_generic,
3272 0x00000000);
3273 /* XXX : not implemented */
3274 spr_register(env, SPR_HID1, "HID1",
3275 SPR_NOACCESS, SPR_NOACCESS,
3276 &spr_read_generic, &spr_write_generic,
3277 0x00000000);
3278 /* Memory management */
3279 gen_low_BATs(env);
3280 gen_6xx_7xx_soft_tlb(env, 64, 2);
3281 init_excp_602(env);
3282 env->dcache_line_size = 32;
3283 env->icache_line_size = 32;
3284 /* Allocate hardware IRQ controller */
3285 ppc6xx_irq_init(env);
3286 }
3287
3288 /* PowerPC 603 */
3289 #define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3290 #define POWERPC_MSRM_603 (0x000000000007FF73ULL)
3291 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
3292 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
3293 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
3294 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
3295 #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3296 POWERPC_FLAG_BE)
3297
3298 static void init_proc_603 (CPUPPCState *env)
3299 {
3300 gen_spr_ne_601(env);
3301 gen_spr_603(env);
3302 /* Time base */
3303 gen_tbl(env);
3304 /* hardware implementation registers */
3305 /* XXX : not implemented */
3306 spr_register(env, SPR_HID0, "HID0",
3307 SPR_NOACCESS, SPR_NOACCESS,
3308 &spr_read_generic, &spr_write_generic,
3309 0x00000000);
3310 /* XXX : not implemented */
3311 spr_register(env, SPR_HID1, "HID1",
3312 SPR_NOACCESS, SPR_NOACCESS,
3313 &spr_read_generic, &spr_write_generic,
3314 0x00000000);
3315 /* Memory management */
3316 gen_low_BATs(env);
3317 gen_6xx_7xx_soft_tlb(env, 64, 2);
3318 init_excp_603(env);
3319 env->dcache_line_size = 32;
3320 env->icache_line_size = 32;
3321 /* Allocate hardware IRQ controller */
3322 ppc6xx_irq_init(env);
3323 }
3324
3325 /* PowerPC 603e */
3326 #define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3327 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
3328 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
3329 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
3330 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
3331 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
3332 #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3333 POWERPC_FLAG_BE)
3334
3335 static void init_proc_603E (CPUPPCState *env)
3336 {
3337 gen_spr_ne_601(env);
3338 gen_spr_603(env);
3339 /* Time base */
3340 gen_tbl(env);
3341 /* hardware implementation registers */
3342 /* XXX : not implemented */
3343 spr_register(env, SPR_HID0, "HID0",
3344 SPR_NOACCESS, SPR_NOACCESS,
3345 &spr_read_generic, &spr_write_generic,
3346 0x00000000);
3347 /* XXX : not implemented */
3348 spr_register(env, SPR_HID1, "HID1",
3349 SPR_NOACCESS, SPR_NOACCESS,
3350 &spr_read_generic, &spr_write_generic,
3351 0x00000000);
3352 /* XXX : not implemented */
3353 spr_register(env, SPR_IABR, "IABR",
3354 SPR_NOACCESS, SPR_NOACCESS,
3355 &spr_read_generic, &spr_write_generic,
3356 0x00000000);
3357 /* Memory management */
3358 gen_low_BATs(env);
3359 gen_6xx_7xx_soft_tlb(env, 64, 2);
3360 init_excp_603(env);
3361 env->dcache_line_size = 32;
3362 env->icache_line_size = 32;
3363 /* Allocate hardware IRQ controller */
3364 ppc6xx_irq_init(env);
3365 }
3366
3367 /* PowerPC G2 */
3368 #define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3369 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3370 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3371 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3372 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3373 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3374 #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3375 POWERPC_FLAG_BE)
3376
3377 static void init_proc_G2 (CPUPPCState *env)
3378 {
3379 gen_spr_ne_601(env);
3380 gen_spr_G2_755(env);
3381 gen_spr_G2(env);
3382 /* Time base */
3383 gen_tbl(env);
3384 /* Hardware implementation register */
3385 /* XXX : not implemented */
3386 spr_register(env, SPR_HID0, "HID0",
3387 SPR_NOACCESS, SPR_NOACCESS,
3388 &spr_read_generic, &spr_write_generic,
3389 0x00000000);
3390 /* XXX : not implemented */
3391 spr_register(env, SPR_HID1, "HID1",
3392 SPR_NOACCESS, SPR_NOACCESS,
3393 &spr_read_generic, &spr_write_generic,
3394 0x00000000);
3395 /* XXX : not implemented */
3396 spr_register(env, SPR_HID2, "HID2",
3397 SPR_NOACCESS, SPR_NOACCESS,
3398 &spr_read_generic, &spr_write_generic,
3399 0x00000000);
3400 /* Memory management */
3401 gen_low_BATs(env);
3402 gen_high_BATs(env);
3403 gen_6xx_7xx_soft_tlb(env, 64, 2);
3404 init_excp_G2(env);
3405 env->dcache_line_size = 32;
3406 env->icache_line_size = 32;
3407 /* Allocate hardware IRQ controller */
3408 ppc6xx_irq_init(env);
3409 }
3410
3411 /* PowerPC G2LE */
3412 #define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3413 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3414 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3415 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3416 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
3417 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
3418 #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3419 POWERPC_FLAG_BE)
3420
3421 static void init_proc_G2LE (CPUPPCState *env)
3422 {
3423 gen_spr_ne_601(env);
3424 gen_spr_G2_755(env);
3425 gen_spr_G2(env);
3426 /* Time base */
3427 gen_tbl(env);
3428 /* Hardware implementation register */
3429 /* XXX : not implemented */
3430 spr_register(env, SPR_HID0, "HID0",
3431 SPR_NOACCESS, SPR_NOACCESS,
3432 &spr_read_generic, &spr_write_generic,
3433 0x00000000);
3434 /* XXX : not implemented */
3435 spr_register(env, SPR_HID1, "HID1",
3436 SPR_NOACCESS, SPR_NOACCESS,
3437 &spr_read_generic, &spr_write_generic,
3438 0x00000000);
3439 /* XXX : not implemented */
3440 spr_register(env, SPR_HID2, "HID2",
3441 SPR_NOACCESS, SPR_NOACCESS,
3442 &spr_read_generic, &spr_write_generic,
3443 0x00000000);
3444 /* Memory management */
3445 gen_low_BATs(env);
3446 gen_high_BATs(env);
3447 gen_6xx_7xx_soft_tlb(env, 64, 2);
3448 init_excp_G2(env);
3449 env->dcache_line_size = 32;
3450 env->icache_line_size = 32;
3451 /* Allocate hardware IRQ controller */
3452 ppc6xx_irq_init(env);
3453 }
3454
3455 /* PowerPC 604 */
3456 #define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3457 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
3458 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
3459 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
3460 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
3461 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
3462 #define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3463 POWERPC_FLAG_PMM)
3464
3465 static void init_proc_604 (CPUPPCState *env)
3466 {
3467 gen_spr_ne_601(env);
3468 gen_spr_604(env);
3469 /* Time base */
3470 gen_tbl(env);
3471 /* Hardware implementation registers */
3472 /* XXX : not implemented */
3473 spr_register(env, SPR_HID0, "HID0",
3474 SPR_NOACCESS, SPR_NOACCESS,
3475 &spr_read_generic, &spr_write_generic,
3476 0x00000000);
3477 /* XXX : not implemented */
3478 spr_register(env, SPR_HID1, "HID1",
3479 SPR_NOACCESS, SPR_NOACCESS,
3480 &spr_read_generic, &spr_write_generic,
3481 0x00000000);
3482 /* Memory management */
3483 gen_low_BATs(env);
3484 init_excp_604(env);
3485 env->dcache_line_size = 32;
3486 env->icache_line_size = 32;
3487 /* Allocate hardware IRQ controller */
3488 ppc6xx_irq_init(env);
3489 }
3490
3491 /* PowerPC 740/750 (aka G3) */
3492 #define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3493 #define POWERPC_MSRM_7x0 (0x000000000005FF77ULL)
3494 #define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
3495 //#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
3496 #define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
3497 #define POWERPC_BFDM_7x0 (bfd_mach_ppc_750)
3498 #define POWERPC_FLAG_7x0 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3499 POWERPC_FLAG_PMM)
3500
3501 static void init_proc_7x0 (CPUPPCState *env)
3502 {
3503 gen_spr_ne_601(env);
3504 gen_spr_7xx(env);
3505 /* Time base */
3506 gen_tbl(env);
3507 /* Thermal management */
3508 gen_spr_thrm(env);
3509 /* Hardware implementation registers */
3510 /* XXX : not implemented */
3511 spr_register(env, SPR_HID0, "HID0",
3512 SPR_NOACCESS, SPR_NOACCESS,
3513 &spr_read_generic, &spr_write_generic,
3514 0x00000000);
3515 /* XXX : not implemented */
3516 spr_register(env, SPR_HID1, "HID1",
3517 SPR_NOACCESS, SPR_NOACCESS,
3518 &spr_read_generic, &spr_write_generic,
3519 0x00000000);
3520 /* Memory management */
3521 gen_low_BATs(env);
3522 init_excp_7x0(env);
3523 env->dcache_line_size = 32;
3524 env->icache_line_size = 32;
3525 /* Allocate hardware IRQ controller */
3526 ppc6xx_irq_init(env);
3527 }
3528
3529 /* PowerPC 750FX/GX */
3530 #define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN)
3531 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
3532 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
3533 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
3534 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
3535 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
3536 #define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3537 POWERPC_FLAG_PMM)
3538
3539 static void init_proc_750fx (CPUPPCState *env)
3540 {
3541 gen_spr_ne_601(env);
3542 gen_spr_7xx(env);
3543 /* Time base */
3544 gen_tbl(env);
3545 /* Thermal management */
3546 gen_spr_thrm(env);
3547 /* Hardware implementation registers */
3548 /* XXX : not implemented */
3549 spr_register(env, SPR_HID0, "HID0",
3550 SPR_NOACCESS, SPR_NOACCESS,
3551 &spr_read_generic, &spr_write_generic,
3552 0x00000000);
3553 /* XXX : not implemented */
3554 spr_register(env, SPR_HID1, "HID1",
3555 SPR_NOACCESS, SPR_NOACCESS,
3556 &spr_read_generic, &spr_write_generic,
3557 0x00000000);
3558 /* XXX : not implemented */
3559 spr_register(env, SPR_750_HID2, "HID2",
3560 SPR_NOACCESS, SPR_NOACCESS,
3561 &spr_read_generic, &spr_write_generic,
3562 0x00000000);
3563 /* Memory management */
3564 gen_low_BATs(env);
3565 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3566 gen_high_BATs(env);
3567 init_excp_750FX(env);
3568 env->dcache_line_size = 32;
3569 env->icache_line_size = 32;
3570 /* Allocate hardware IRQ controller */
3571 ppc6xx_irq_init(env);
3572 }
3573
3574 /* PowerPC 745/755 */
3575 #define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
3576 #define POWERPC_MSRM_7x5 (0x000000000005FF77ULL)
3577 #define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
3578 //#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
3579 #define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
3580 #define POWERPC_BFDM_7x5 (bfd_mach_ppc_750)
3581 #define POWERPC_FLAG_7x5 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3582 POWERPC_FLAG_PMM)
3583
3584 static void init_proc_7x5 (CPUPPCState *env)
3585 {
3586 gen_spr_ne_601(env);
3587 gen_spr_G2_755(env);
3588 /* Time base */
3589 gen_tbl(env);
3590 /* L2 cache control */
3591 /* XXX : not implemented */
3592 spr_register(env, SPR_ICTC, "ICTC",
3593 SPR_NOACCESS, SPR_NOACCESS,
3594 &spr_read_generic, &spr_write_generic,
3595 0x00000000);
3596 /* XXX : not implemented */
3597 spr_register(env, SPR_L2PMCR, "L2PMCR",
3598 SPR_NOACCESS, SPR_NOACCESS,
3599 &spr_read_generic, &spr_write_generic,
3600 0x00000000);
3601 /* Hardware implementation registers */
3602 /* XXX : not implemented */
3603 spr_register(env, SPR_HID0, "HID0",
3604 SPR_NOACCESS, SPR_NOACCESS,
3605 &spr_read_generic, &spr_write_generic,
3606 0x00000000);
3607 /* XXX : not implemented */
3608 spr_register(env, SPR_HID1, "HID1",
3609 SPR_NOACCESS, SPR_NOACCESS,
3610 &spr_read_generic, &spr_write_generic,
3611 0x00000000);
3612 /* XXX : not implemented */
3613 spr_register(env, SPR_HID2, "HID2",
3614 SPR_NOACCESS, SPR_NOACCESS,
3615 &spr_read_generic, &spr_write_generic,
3616 0x00000000);
3617 /* Memory management */
3618 gen_low_BATs(env);
3619 gen_high_BATs(env);
3620 gen_6xx_7xx_soft_tlb(env, 64, 2);
3621 init_excp_7x5(env);
3622 env->dcache_line_size = 32;
3623 env->icache_line_size = 32;
3624 /* Allocate hardware IRQ controller */
3625 ppc6xx_irq_init(env);
3626 #if !defined(CONFIG_USER_ONLY)
3627 /* Hardware reset vector */
3628 env->hreset_vector = 0xFFFFFFFCUL;
3629 #endif
3630 }
3631
3632 /* PowerPC 7400 (aka G4) */
3633 #define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3634 PPC_EXTERN | PPC_MEM_TLBIA | \
3635 PPC_ALTIVEC)
3636 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
3637 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
3638 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
3639 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
3640 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
3641 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3642 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3643
3644 static void init_proc_7400 (CPUPPCState *env)
3645 {
3646 gen_spr_ne_601(env);
3647 gen_spr_7xx(env);
3648 /* Time base */
3649 gen_tbl(env);
3650 /* 74xx specific SPR */
3651 gen_spr_74xx(env);
3652 /* Thermal management */
3653 gen_spr_thrm(env);
3654 /* Memory management */
3655 gen_low_BATs(env);
3656 init_excp_7400(env);
3657 env->dcache_line_size = 32;
3658 env->icache_line_size = 32;
3659 /* Allocate hardware IRQ controller */
3660 ppc6xx_irq_init(env);
3661 }
3662
3663 /* PowerPC 7410 (aka G4) */
3664 #define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3665 PPC_EXTERN | PPC_MEM_TLBIA | \
3666 PPC_ALTIVEC)
3667 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
3668 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
3669 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
3670 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
3671 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
3672 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3673 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3674
3675 static void init_proc_7410 (CPUPPCState *env)
3676 {
3677 gen_spr_ne_601(env);
3678 gen_spr_7xx(env);
3679 /* Time base */
3680 gen_tbl(env);
3681 /* 74xx specific SPR */
3682 gen_spr_74xx(env);
3683 /* Thermal management */
3684 gen_spr_thrm(env);
3685 /* L2PMCR */
3686 /* XXX : not implemented */
3687 spr_register(env, SPR_L2PMCR, "L2PMCR",
3688 SPR_NOACCESS, SPR_NOACCESS,
3689 &spr_read_generic, &spr_write_generic,
3690 0x00000000);
3691 /* LDSTDB */
3692 /* XXX : not implemented */
3693 spr_register(env, SPR_LDSTDB, "LDSTDB",
3694 SPR_NOACCESS, SPR_NOACCESS,
3695 &spr_read_generic, &spr_write_generic,
3696 0x00000000);
3697 /* Memory management */
3698 gen_low_BATs(env);
3699 init_excp_7400(env);
3700 env->dcache_line_size = 32;
3701 env->icache_line_size = 32;
3702 /* Allocate hardware IRQ controller */
3703 ppc6xx_irq_init(env);
3704 }
3705
3706 /* PowerPC 7440 (aka G4) */
3707 #define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3708 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3709 PPC_ALTIVEC)
3710 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
3711 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
3712 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
3713 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
3714 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
3715 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3716 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3717
3718 __attribute__ (( unused ))
3719 static void init_proc_7440 (CPUPPCState *env)
3720 {
3721 gen_spr_ne_601(env);
3722 gen_spr_7xx(env);
3723 /* Time base */
3724 gen_tbl(env);
3725 /* 74xx specific SPR */
3726 gen_spr_74xx(env);
3727 /* LDSTCR */
3728 /* XXX : not implemented */
3729 spr_register(env, SPR_LDSTCR, "LDSTCR",
3730 SPR_NOACCESS, SPR_NOACCESS,
3731 &spr_read_generic, &spr_write_generic,
3732 0x00000000);
3733 /* ICTRL */
3734 /* XXX : not implemented */
3735 spr_register(env, SPR_ICTRL, "ICTRL",
3736 SPR_NOACCESS, SPR_NOACCESS,
3737 &spr_read_generic, &spr_write_generic,
3738 0x00000000);
3739 /* MSSSR0 */
3740 /* XXX : not implemented */
3741 spr_register(env, SPR_MSSSR0, "MSSSR0",
3742 SPR_NOACCESS, SPR_NOACCESS,
3743 &spr_read_generic, &spr_write_generic,
3744 0x00000000);
3745 /* PMC */
3746 /* XXX : not implemented */
3747 spr_register(env, SPR_PMC5, "PMC5",
3748 SPR_NOACCESS, SPR_NOACCESS,
3749 &spr_read_generic, &spr_write_generic,
3750 0x00000000);
3751 /* XXX : not implemented */
3752 spr_register(env, SPR_UPMC5, "UPMC5",
3753 &spr_read_ureg, SPR_NOACCESS,
3754 &spr_read_ureg, SPR_NOACCESS,
3755 0x00000000);
3756 /* XXX : not implemented */
3757 spr_register(env, SPR_PMC6, "PMC6",
3758 SPR_NOACCESS, SPR_NOACCESS,
3759 &spr_read_generic, &spr_write_generic,
3760 0x00000000);
3761 /* XXX : not implemented */
3762 spr_register(env, SPR_UPMC6, "UPMC6",
3763 &spr_read_ureg, SPR_NOACCESS,
3764 &spr_read_ureg, SPR_NOACCESS,
3765 0x00000000);
3766 /* Memory management */
3767 gen_low_BATs(env);
3768 gen_74xx_soft_tlb(env, 128, 2);
3769 init_excp_7450(env);
3770 env->dcache_line_size = 32;
3771 env->icache_line_size = 32;
3772 /* Allocate hardware IRQ controller */
3773 ppc6xx_irq_init(env);
3774 }
3775
3776 /* PowerPC 7450 (aka G4) */
3777 #define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3778 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3779 PPC_ALTIVEC)
3780 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
3781 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
3782 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
3783 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
3784 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
3785 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3786 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3787
3788 __attribute__ (( unused ))
3789 static void init_proc_7450 (CPUPPCState *env)
3790 {
3791 gen_spr_ne_601(env);
3792 gen_spr_7xx(env);
3793 /* Time base */
3794 gen_tbl(env);
3795 /* 74xx specific SPR */
3796 gen_spr_74xx(env);
3797 /* Level 3 cache control */
3798 gen_l3_ctrl(env);
3799 /* LDSTCR */
3800 /* XXX : not implemented */
3801 spr_register(env, SPR_LDSTCR, "LDSTCR",
3802 SPR_NOACCESS, SPR_NOACCESS,
3803 &spr_read_generic, &spr_write_generic,
3804 0x00000000);
3805 /* ICTRL */
3806 /* XXX : not implemented */
3807 spr_register(env, SPR_ICTRL, "ICTRL",
3808 SPR_NOACCESS, SPR_NOACCESS,
3809 &spr_read_generic, &spr_write_generic,
3810 0x00000000);
3811 /* MSSSR0 */
3812 /* XXX : not implemented */
3813 spr_register(env, SPR_MSSSR0, "MSSSR0",
3814 SPR_NOACCESS, SPR_NOACCESS,
3815 &spr_read_generic, &spr_write_generic,
3816 0x00000000);
3817 /* PMC */
3818 /* XXX : not implemented */
3819 spr_register(env, SPR_PMC5, "PMC5",
3820 SPR_NOACCESS, SPR_NOACCESS,
3821 &spr_read_generic, &spr_write_generic,
3822 0x00000000);
3823 /* XXX : not implemented */
3824 spr_register(env, SPR_UPMC5, "UPMC5",
3825 &spr_read_ureg, SPR_NOACCESS,
3826 &spr_read_ureg, SPR_NOACCESS,
3827 0x00000000);
3828 /* XXX : not implemented */
3829 spr_register(env, SPR_PMC6, "PMC6",
3830 SPR_NOACCESS, SPR_NOACCESS,
3831 &spr_read_generic, &spr_write_generic,
3832 0x00000000);
3833 /* XXX : not implemented */
3834 spr_register(env, SPR_UPMC6, "UPMC6",
3835 &spr_read_ureg, SPR_NOACCESS,
3836 &spr_read_ureg, SPR_NOACCESS,
3837 0x00000000);
3838 /* Memory management */
3839 gen_low_BATs(env);
3840 gen_74xx_soft_tlb(env, 128, 2);
3841 init_excp_7450(env);
3842 env->dcache_line_size = 32;
3843 env->icache_line_size = 32;
3844 /* Allocate hardware IRQ controller */
3845 ppc6xx_irq_init(env);
3846 }
3847
3848 /* PowerPC 7445 (aka G4) */
3849 #define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3850 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3851 PPC_ALTIVEC)
3852 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
3853 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
3854 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
3855 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
3856 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
3857 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3858 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3859
3860 __attribute__ (( unused ))
3861 static void init_proc_7445 (CPUPPCState *env)
3862 {
3863 gen_spr_ne_601(env);
3864 gen_spr_7xx(env);
3865 /* Time base */
3866 gen_tbl(env);
3867 /* 74xx specific SPR */
3868 gen_spr_74xx(env);
3869 /* LDSTCR */
3870 /* XXX : not implemented */
3871 spr_register(env, SPR_LDSTCR, "LDSTCR",
3872 SPR_NOACCESS, SPR_NOACCESS,
3873 &spr_read_generic, &spr_write_generic,
3874 0x00000000);
3875 /* ICTRL */
3876 /* XXX : not implemented */
3877 spr_register(env, SPR_ICTRL, "ICTRL",
3878 SPR_NOACCESS, SPR_NOACCESS,
3879 &spr_read_generic, &spr_write_generic,
3880 0x00000000);
3881 /* MSSSR0 */
3882 /* XXX : not implemented */
3883 spr_register(env, SPR_MSSSR0, "MSSSR0",
3884 SPR_NOACCESS, SPR_NOACCESS,
3885 &spr_read_generic, &spr_write_generic,
3886 0x00000000);
3887 /* PMC */
3888 /* XXX : not implemented */
3889 spr_register(env, SPR_PMC5, "PMC5",
3890 SPR_NOACCESS, SPR_NOACCESS,
3891 &spr_read_generic, &spr_write_generic,
3892 0x00000000);
3893 /* XXX : not implemented */
3894 spr_register(env, SPR_UPMC5, "UPMC5",
3895 &spr_read_ureg, SPR_NOACCESS,
3896 &spr_read_ureg, SPR_NOACCESS,
3897 0x00000000);
3898 /* XXX : not implemented */
3899 spr_register(env, SPR_PMC6, "PMC6",
3900 SPR_NOACCESS, SPR_NOACCESS,
3901 &spr_read_generic, &spr_write_generic,
3902 0x00000000);
3903 /* XXX : not implemented */
3904 spr_register(env, SPR_UPMC6, "UPMC6",
3905 &spr_read_ureg, SPR_NOACCESS,
3906 &spr_read_ureg, SPR_NOACCESS,
3907 0x00000000);
3908 /* SPRGs */
3909 spr_register(env, SPR_SPRG4, "SPRG4",
3910 SPR_NOACCESS, SPR_NOACCESS,
3911 &spr_read_generic, &spr_write_generic,
3912 0x00000000);
3913 spr_register(env, SPR_USPRG4, "USPRG4",
3914 &spr_read_ureg, SPR_NOACCESS,
3915 &spr_read_ureg, SPR_NOACCESS,
3916 0x00000000);
3917 spr_register(env, SPR_SPRG5, "SPRG5",
3918 SPR_NOACCESS, SPR_NOACCESS,
3919 &spr_read_generic, &spr_write_generic,
3920 0x00000000);
3921 spr_register(env, SPR_USPRG5, "USPRG5",
3922 &spr_read_ureg, SPR_NOACCESS,
3923 &spr_read_ureg, SPR_NOACCESS,
3924 0x00000000);
3925 spr_register(env, SPR_SPRG6, "SPRG6",
3926 SPR_NOACCESS, SPR_NOACCESS,
3927 &spr_read_generic, &spr_write_generic,
3928 0x00000000);
3929 spr_register(env, SPR_USPRG6, "USPRG6",
3930 &spr_read_ureg, SPR_NOACCESS,
3931 &spr_read_ureg, SPR_NOACCESS,
3932 0x00000000);
3933 spr_register(env, SPR_SPRG7, "SPRG7",
3934 SPR_NOACCESS, SPR_NOACCESS,
3935 &spr_read_generic, &spr_write_generic,
3936 0x00000000);
3937 spr_register(env, SPR_USPRG7, "USPRG7",
3938 &spr_read_ureg, SPR_NOACCESS,
3939 &spr_read_ureg, SPR_NOACCESS,
3940 0x00000000);
3941 /* Memory management */
3942 gen_low_BATs(env);
3943 gen_high_BATs(env);
3944 gen_74xx_soft_tlb(env, 128, 2);
3945 init_excp_7450(env);
3946 env->dcache_line_size = 32;
3947 env->icache_line_size = 32;
3948 /* Allocate hardware IRQ controller */
3949 ppc6xx_irq_init(env);
3950 }
3951
3952 /* PowerPC 7455 (aka G4) */
3953 #define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3954 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3955 PPC_ALTIVEC)
3956 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
3957 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
3958 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
3959 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
3960 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
3961 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3962 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3963
3964 __attribute__ (( unused ))
3965 static void init_proc_7455 (CPUPPCState *env)
3966 {
3967 gen_spr_ne_601(env);
3968 gen_spr_7xx(env);
3969 /* Time base */
3970 gen_tbl(env);
3971 /* 74xx specific SPR */
3972 gen_spr_74xx(env);
3973 /* Level 3 cache control */
3974 gen_l3_ctrl(env);
3975 /* LDSTCR */
3976 /* XXX : not implemented */
3977 spr_register(env, SPR_LDSTCR, "LDSTCR",
3978 SPR_NOACCESS, SPR_NOACCESS,
3979 &spr_read_generic, &spr_write_generic,
3980 0x00000000);
3981 /* ICTRL */
3982 /* XXX : not implemented */
3983 spr_register(env, SPR_ICTRL, "ICTRL",
3984 SPR_NOACCESS, SPR_NOACCESS,
3985 &spr_read_generic, &spr_write_generic,
3986 0x00000000);
3987 /* MSSSR0 */
3988 /* XXX : not implemented */
3989 spr_register(env, SPR_MSSSR0, "MSSSR0",
3990 SPR_NOACCESS, SPR_NOACCESS,
3991 &spr_read_generic, &spr_write_generic,
3992 0x00000000);
3993 /* PMC */
3994 /* XXX : not implemented */
3995 spr_register(env, SPR_PMC5, "PMC5",
3996 SPR_NOACCESS, SPR_NOACCESS,
3997 &spr_read_generic, &spr_write_generic,
3998 0x00000000);
3999 /* XXX : not implemented */
4000 spr_register(env, SPR_UPMC5, "UPMC5",
4001 &spr_read_ureg, SPR_NOACCESS,
4002 &spr_read_ureg, SPR_NOACCESS,
4003 0x00000000);
4004 /* XXX : not implemented */
4005 spr_register(env, SPR_PMC6, "PMC6",
4006 SPR_NOACCESS, SPR_NOACCESS,
4007 &spr_read_generic, &spr_write_generic,
4008 0x00000000);
4009 /* XXX : not implemented */
4010 spr_register(env, SPR_UPMC6, "UPMC6",
4011 &spr_read_ureg, SPR_NOACCESS,
4012 &spr_read_ureg, SPR_NOACCESS,
4013 0x00000000);
4014 /* SPRGs */
4015 spr_register(env, SPR_SPRG4, "SPRG4",
4016 SPR_NOACCESS, SPR_NOACCESS,
4017 &spr_read_generic, &spr_write_generic,
4018 0x00000000);
4019 spr_register(env, SPR_USPRG4, "USPRG4",
4020 &spr_read_ureg, SPR_NOACCESS,
4021 &spr_read_ureg, SPR_NOACCESS,
4022 0x00000000);
4023 spr_register(env, SPR_SPRG5, "SPRG5",
4024 SPR_NOACCESS, SPR_NOACCESS,
4025 &spr_read_generic, &spr_write_generic,
4026 0x00000000);
4027 spr_register(env, SPR_USPRG5, "USPRG5",
4028 &spr_read_ureg, SPR_NOACCESS,
4029 &spr_read_ureg, SPR_NOACCESS,
4030 0x00000000);
4031 spr_register(env, SPR_SPRG6, "SPRG6",
4032 SPR_NOACCESS, SPR_NOACCESS,
4033 &spr_read_generic, &spr_write_generic,
4034 0x00000000);
4035 spr_register(env, SPR_USPRG6, "USPRG6",
4036 &spr_read_ureg, SPR_NOACCESS,
4037 &spr_read_ureg, SPR_NOACCESS,
4038 0x00000000);
4039 spr_register(env, SPR_SPRG7, "SPRG7",
4040 SPR_NOACCESS, SPR_NOACCESS,
4041 &spr_read_generic, &spr_write_generic,
4042 0x00000000);
4043 spr_register(env, SPR_USPRG7, "USPRG7",
4044 &spr_read_ureg, SPR_NOACCESS,
4045 &spr_read_ureg, SPR_NOACCESS,
4046 0x00000000);
4047 /* Memory management */
4048 gen_low_BATs(env);
4049 gen_high_BATs(env);
4050 gen_74xx_soft_tlb(env, 128, 2);
4051 init_excp_7450(env);
4052 env->dcache_line_size = 32;
4053 env->icache_line_size = 32;
4054 /* Allocate hardware IRQ controller */
4055 ppc6xx_irq_init(env);
4056 }
4057
4058 #if defined (TARGET_PPC64)
4059 #define POWERPC_INSNS_WORK64 (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
4060 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
4061 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
4062 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)
4063 /* PowerPC 970 */
4064 #define POWERPC_INSNS_970 (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4065 PPC_64B | PPC_ALTIVEC | \
4066 PPC_SEGMENT_64B | PPC_SLBI)
4067 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
4068 #define POWERPC_MMU_970 (POWERPC_MMU_64B)
4069 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
4070 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
4071 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
4072 #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4073 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4074
4075 #if defined(CONFIG_USER_ONLY)
4076 #define POWERPC970_HID5_INIT 0x00000080
4077 #else
4078 #define POWERPC970_HID5_INIT 0x00000000
4079 #endif
4080
4081 static void init_proc_970 (CPUPPCState *env)
4082 {
4083 gen_spr_ne_601(env);
4084 gen_spr_7xx(env);
4085 /* Time base */
4086 gen_tbl(env);
4087 /* Hardware implementation registers */
4088 /* XXX : not implemented */
4089 spr_register(env, SPR_HID0, "HID0",
4090 SPR_NOACCESS, SPR_NOACCESS,
4091 &spr_read_generic, &spr_write_clear,
4092 0x60000000);
4093 /* XXX : not implemented */
4094 spr_register(env, SPR_HID1, "HID1",
4095 SPR_NOACCESS, SPR_NOACCESS,
4096 &spr_read_generic, &spr_write_generic,
4097 0x00000000);
4098 /* XXX : not implemented */
4099 spr_register(env, SPR_750_HID2, "HID2",
4100 SPR_NOACCESS, SPR_NOACCESS,
4101 &spr_read_generic, &spr_write_generic,
4102 0x00000000);
4103 /* XXX : not implemented */
4104 spr_register(env, SPR_970_HID5, "HID5",
4105 SPR_NOACCESS, SPR_NOACCESS,
4106 &spr_read_generic, &spr_write_generic,
4107 POWERPC970_HID5_INIT);
4108 /* Memory management */
4109 /* XXX: not correct */
4110 gen_low_BATs(env);
4111 /* XXX : not implemented */
4112 spr_register(env, SPR_MMUCFG, "MMUCFG",
4113 SPR_NOACCESS, SPR_NOACCESS,
4114 &spr_read_generic, SPR_NOACCESS,
4115 0x00000000); /* TOFIX */
4116 /* XXX : not implemented */
4117 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4118 SPR_NOACCESS, SPR_NOACCESS,
4119 &spr_read_generic, &spr_write_generic,
4120 0x00000000); /* TOFIX */
4121 spr_register(env, SPR_HIOR, "SPR_HIOR",
4122 SPR_NOACCESS, SPR_NOACCESS,
4123 &spr_read_generic, &spr_write_generic,
4124 0xFFF00000); /* XXX: This is a hack */
4125 #if !defined(CONFIG_USER_ONLY)
4126 env->excp_prefix = 0xFFF00000;
4127 #endif
4128 #if !defined(CONFIG_USER_ONLY)
4129 env->slb_nr = 32;
4130 #endif
4131 init_excp_970(env);
4132 env->dcache_line_size = 128;
4133 env->icache_line_size = 128;
4134 /* Allocate hardware IRQ controller */
4135 ppc970_irq_init(env);
4136 }
4137
4138 /* PowerPC 970FX (aka G5) */
4139 #define POWERPC_INSNS_970FX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4140 PPC_64B | PPC_ALTIVEC | \
4141 PPC_SEGMENT_64B | PPC_SLBI)
4142 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
4143 #define POWERPC_MMU_970FX (POWERPC_MMU_64B)
4144 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
4145 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
4146 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
4147 #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4148 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4149
4150 static void init_proc_970FX (CPUPPCState *env)
4151 {
4152 gen_spr_ne_601(env);
4153 gen_spr_7xx(env);
4154 /* Time base */
4155 gen_tbl(env);
4156 /* Hardware implementation registers */
4157 /* XXX : not implemented */
4158 spr_register(env, SPR_HID0, "HID0",
4159 SPR_NOACCESS, SPR_NOACCESS,
4160 &spr_read_generic, &spr_write_clear,
4161 0x60000000);
4162 /* XXX : not implemented */
4163 spr_register(env, SPR_HID1, "HID1",
4164 SPR_NOACCESS, SPR_NOACCESS,
4165 &spr_read_generic, &spr_write_generic,
4166 0x00000000);
4167 /* XXX : not implemented */
4168 spr_register(env, SPR_750_HID2, "HID2",
4169 SPR_NOACCESS, SPR_NOACCESS,
4170 &spr_read_generic, &spr_write_generic,
4171 0x00000000);
4172 /* XXX : not implemented */
4173 spr_register(env, SPR_970_HID5, "HID5",
4174 SPR_NOACCESS, SPR_NOACCESS,
4175 &spr_read_generic, &spr_write_generic,
4176 POWERPC970_HID5_INIT);
4177 /* Memory management */
4178 /* XXX: not correct */
4179 gen_low_BATs(env);
4180 /* XXX : not implemented */
4181 spr_register(env, SPR_MMUCFG, "MMUCFG",
4182 SPR_NOACCESS, SPR_NOACCESS,
4183 &spr_read_generic, SPR_NOACCESS,
4184 0x00000000); /* TOFIX */
4185 /* XXX : not implemented */
4186 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4187 SPR_NOACCESS, SPR_NOACCESS,
4188 &spr_read_generic, &spr_write_generic,
4189 0x00000000); /* TOFIX */
4190 spr_register(env, SPR_HIOR, "SPR_HIOR",
4191 SPR_NOACCESS, SPR_NOACCESS,
4192 &spr_read_generic, &spr_write_generic,
4193 0xFFF00000); /* XXX: This is a hack */
4194 #if !defined(CONFIG_USER_ONLY)
4195 env->excp_prefix = 0xFFF00000;
4196 #endif
4197 #if !defined(CONFIG_USER_ONLY)
4198 env->slb_nr = 32;
4199 #endif
4200 init_excp_970(env);
4201 env->dcache_line_size = 128;
4202 env->icache_line_size = 128;
4203 /* Allocate hardware IRQ controller */
4204 ppc970_irq_init(env);
4205 }
4206
4207 /* PowerPC 970 GX */
4208 #define POWERPC_INSNS_970GX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4209 PPC_64B | PPC_ALTIVEC | \
4210 PPC_SEGMENT_64B | PPC_SLBI)
4211 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
4212 #define POWERPC_MMU_970GX (POWERPC_MMU_64B)
4213 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
4214 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
4215 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
4216 #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4217 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4218
4219 static void init_proc_970GX (CPUPPCState *env)
4220 {
4221 gen_spr_ne_601(env);
4222 gen_spr_7xx(env);
4223 /* Time base */
4224 gen_tbl(env);
4225 /* Hardware implementation registers */
4226 /* XXX : not implemented */
4227 spr_register(env, SPR_HID0, "HID0",
4228 SPR_NOACCESS, SPR_NOACCESS,
4229 &spr_read_generic, &spr_write_clear,
4230 0x60000000);
4231 /* XXX : not implemented */
4232 spr_register(env, SPR_HID1, "HID1",
4233 SPR_NOACCESS, SPR_NOACCESS,
4234 &spr_read_generic, &spr_write_generic,
4235 0x00000000);
4236 /* XXX : not implemented */
4237 spr_register(env, SPR_750_HID2, "HID2",
4238 SPR_NOACCESS, SPR_NOACCESS,
4239 &spr_read_generic, &spr_write_generic,
4240 0x00000000);
4241 /* XXX : not implemented */
4242 spr_register(env, SPR_970_HID5, "HID5",
4243 SPR_NOACCESS, SPR_NOACCESS,
4244 &spr_read_generic, &spr_write_generic,
4245 POWERPC970_HID5_INIT);
4246 /* Memory management */
4247 /* XXX: not correct */
4248 gen_low_BATs(env);
4249 /* XXX : not implemented */
4250 spr_register(env, SPR_MMUCFG, "MMUCFG",
4251 SPR_NOACCESS, SPR_NOACCESS,
4252 &spr_read_generic, SPR_NOACCESS,
4253 0x00000000); /* TOFIX */
4254 /* XXX : not implemented */
4255 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4256 SPR_NOACCESS, SPR_NOACCESS,
4257 &spr_read_generic, &spr_write_generic,
4258 0x00000000); /* TOFIX */
4259 spr_register(env, SPR_HIOR, "SPR_HIOR",
4260 SPR_NOACCESS, SPR_NOACCESS,
4261 &spr_read_generic, &spr_write_generic,
4262 0xFFF00000); /* XXX: This is a hack */
4263 #if !defined(CONFIG_USER_ONLY)
4264 env->excp_prefix = 0xFFF00000;
4265 #endif
4266 #if !defined(CONFIG_USER_ONLY)
4267 env->slb_nr = 32;
4268 #endif
4269 init_excp_970(env);
4270 env->dcache_line_size = 128;
4271 env->icache_line_size = 128;
4272 /* Allocate hardware IRQ controller */
4273 ppc970_irq_init(env);
4274 }
4275
4276 /* PowerPC 620 */
4277 #define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
4278 PPC_64B | PPC_SLBI)
4279 #define POWERPC_MSRM_620 (0x800000000005FF73ULL)
4280 #define POWERPC_MMU_620 (POWERPC_MMU_64B)
4281 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
4282 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_970)
4283 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
4284 #define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE)
4285
4286 __attribute__ (( unused ))
4287 static void init_proc_620 (CPUPPCState *env)
4288 {
4289 gen_spr_ne_601(env);
4290 gen_spr_620(env);
4291 /* Time base */
4292 gen_tbl(env);
4293 /* Hardware implementation registers */
4294 /* XXX : not implemented */
4295 spr_register(env, SPR_HID0, "HID0",
4296 SPR_NOACCESS, SPR_NOACCESS,
4297 &spr_read_generic, &spr_write_generic,
4298 0x00000000);
4299 /* Memory management */
4300 gen_low_BATs(env);
4301 gen_high_BATs(env);
4302 init_excp_620(env);
4303 env->dcache_line_size = 64;
4304 env->icache_line_size = 64;
4305 /* XXX: TODO: initialize internal interrupt controller */
4306 }
4307 #endif /* defined (TARGET_PPC64) */
4308
4309 /* Default 32 bits PowerPC target will be 604 */
4310 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
4311 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
4312 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
4313 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
4314 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
4315 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
4316 #define init_proc_PPC32 init_proc_604
4317 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
4318 #define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
4319
4320 /* Default 64 bits PowerPC target will be 970 FX */
4321 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
4322 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
4323 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
4324 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
4325 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
4326 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
4327 #define init_proc_PPC64 init_proc_970FX
4328 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
4329 #define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
4330
4331 /* Default PowerPC target will be PowerPC 32 */
4332 #if defined (TARGET_PPC64) && 0 // XXX: TODO
4333 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
4334 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
4335 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
4336 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
4337 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
4338 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
4339 #define init_proc_DEFAULT init_proc_PPC64
4340 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
4341 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
4342 #else
4343 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
4344 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
4345 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
4346 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
4347 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
4348 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
4349 #define init_proc_DEFAULT init_proc_PPC32
4350 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
4351 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
4352 #endif
4353
4354 /*****************************************************************************/
4355 /* PVR definitions for most known PowerPC */
4356 enum {
4357 /* PowerPC 401 family */
4358 /* Generic PowerPC 401 */
4359 #define CPU_POWERPC_401 CPU_POWERPC_401G2
4360 /* PowerPC 401 cores */
4361 CPU_POWERPC_401A1 = 0x00210000,
4362 CPU_POWERPC_401B2 = 0x00220000,
4363 #if 0
4364 CPU_POWERPC_401B3 = xxx,
4365 #endif
4366 CPU_POWERPC_401C2 = 0x00230000,
4367 CPU_POWERPC_401D2 = 0x00240000,
4368 CPU_POWERPC_401E2 = 0x00250000,
4369 CPU_POWERPC_401F2 = 0x00260000,
4370 CPU_POWERPC_401G2 = 0x00270000,
4371 /* PowerPC 401 microcontrolers */
4372 #if 0
4373 CPU_POWERPC_401GF = xxx,
4374 #endif
4375 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
4376 /* IBM Processor for Network Resources */
4377 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
4378 #if 0
4379 CPU_POWERPC_XIPCHIP = xxx,
4380 #endif
4381 /* PowerPC 403 family */
4382 /* Generic PowerPC 403 */
4383 #define CPU_POWERPC_403 CPU_POWERPC_403GC
4384 /* PowerPC 403 microcontrollers */
4385 CPU_POWERPC_403GA = 0x00200011,
4386 CPU_POWERPC_403GB = 0x00200100,
4387 CPU_POWERPC_403GC = 0x00200200,
4388 CPU_POWERPC_403GCX = 0x00201400,
4389 #if 0
4390 CPU_POWERPC_403GP = xxx,
4391 #endif
4392 /* PowerPC 405 family */
4393 /* Generic PowerPC 405 */
4394 #define CPU_POWERPC_405 CPU_POWERPC_405D4
4395 /* PowerPC 405 cores */
4396 #if 0
4397 CPU_POWERPC_405A3 = xxx,
4398 #endif
4399 #if 0
4400 CPU_POWERPC_405A4 = xxx,
4401 #endif
4402 #if 0
4403 CPU_POWERPC_405B3 = xxx,
4404 #endif
4405 #if 0
4406 CPU_POWERPC_405B4 = xxx,
4407 #endif
4408 #if 0
4409 CPU_POWERPC_405C3 = xxx,
4410 #endif
4411 #if 0
4412 CPU_POWERPC_405C4 = xxx,
4413 #endif
4414 CPU_POWERPC_405D2 = 0x20010000,
4415 #if 0
4416 CPU_POWERPC_405D3 = xxx,
4417 #endif
4418 CPU_POWERPC_405D4 = 0x41810000,
4419 #if 0
4420 CPU_POWERPC_405D5 = xxx,
4421 #endif
4422 #if 0
4423 CPU_POWERPC_405E4 = xxx,
4424 #endif
4425 #if 0
4426 CPU_POWERPC_405F4 = xxx,
4427 #endif
4428 #if 0
4429 CPU_POWERPC_405F5 = xxx,
4430 #endif
4431 #if 0
4432 CPU_POWERPC_405F6 = xxx,
4433 #endif
4434 /* PowerPC 405 microcontrolers */
4435 /* XXX: missing 0x200108a0 */
4436 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
4437 CPU_POWERPC_405CRa = 0x40110041,
4438 CPU_POWERPC_405CRb = 0x401100C5,
4439 CPU_POWERPC_405CRc = 0x40110145,
4440 CPU_POWERPC_405EP = 0x51210950,
4441 #if 0
4442 CPU_POWERPC_405EXr = xxx,
4443 #endif
4444 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
4445 #if 0
4446 CPU_POWERPC_405FX = xxx,
4447 #endif
4448 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
4449 CPU_POWERPC_405GPa = 0x40110000,
4450 CPU_POWERPC_405GPb = 0x40110040,
4451 CPU_POWERPC_405GPc = 0x40110082,
4452 CPU_POWERPC_405GPd = 0x401100C4,
4453 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
4454 CPU_POWERPC_405GPR = 0x50910951,
4455 #if 0
4456 CPU_POWERPC_405H = xxx,
4457 #endif
4458 #if 0
4459 CPU_POWERPC_405L = xxx,
4460 #endif
4461 CPU_POWERPC_405LP = 0x41F10000,
4462 #if 0
4463 CPU_POWERPC_405PM = xxx,
4464 #endif
4465 #if 0
4466 CPU_POWERPC_405PS = xxx,
4467 #endif
4468 #if 0
4469 CPU_POWERPC_405S = xxx,
4470 #endif
4471 /* IBM network processors */
4472 CPU_POWERPC_NPE405H = 0x414100C0,
4473 CPU_POWERPC_NPE405H2 = 0x41410140,
4474 CPU_POWERPC_NPE405L = 0x416100C0,
4475 CPU_POWERPC_NPE4GS3 = 0x40B10000,
4476 #if 0
4477 CPU_POWERPC_NPCxx1 = xxx,
4478 #endif
4479 #if 0
4480 CPU_POWERPC_NPR161 = xxx,
4481 #endif
4482 #if 0
4483 CPU_POWERPC_LC77700 = xxx,
4484 #endif
4485 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
4486 #if 0
4487 CPU_POWERPC_STB01000 = xxx,
4488 #endif
4489 #if 0
4490 CPU_POWERPC_STB01010 = xxx,
4491 #endif
4492 #if 0
4493 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
4494 #endif
4495 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
4496 #if 0
4497 CPU_POWERPC_STB043 = xxx,
4498 #endif
4499 #if 0
4500 CPU_POWERPC_STB045 = xxx,
4501 #endif
4502 CPU_POWERPC_STB04 = 0x41810000,
4503 CPU_POWERPC_STB25 = 0x51510950,
4504 #if 0
4505 CPU_POWERPC_STB130 = xxx,
4506 #endif
4507 /* Xilinx cores */
4508 CPU_POWERPC_X2VP4 = 0x20010820,
4509 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
4510 CPU_POWERPC_X2VP20 = 0x20010860,
4511 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
4512 #if 0
4513 CPU_POWERPC_ZL10310 = xxx,
4514 #endif
4515 #if 0
4516 CPU_POWERPC_ZL10311 = xxx,
4517 #endif
4518 #if 0
4519 CPU_POWERPC_ZL10320 = xxx,
4520 #endif
4521 #if 0
4522 CPU_POWERPC_ZL10321 = xxx,
4523 #endif
4524 /* PowerPC 440 family */
4525 /* Generic PowerPC 440 */
4526 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
4527 /* PowerPC 440 cores */
4528 #if 0
4529 CPU_POWERPC_440A4 = xxx,
4530 #endif
4531 #if 0
4532 CPU_POWERPC_440A5 = xxx,
4533 #endif
4534 #if 0
4535 CPU_POWERPC_440B4 = xxx,
4536 #endif
4537 #if 0
4538 CPU_POWERPC_440F5 = xxx,
4539 #endif
4540 #if 0
4541 CPU_POWERPC_440G5 = xxx,
4542 #endif
4543 #if 0
4544 CPU_POWERPC_440H4 = xxx,
4545 #endif
4546 #if 0
4547 CPU_POWERPC_440H6 = xxx,
4548 #endif
4549 /* PowerPC 440 microcontrolers */
4550 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
4551 CPU_POWERPC_440EPa = 0x42221850,
4552 CPU_POWERPC_440EPb = 0x422218D3,
4553 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
4554 CPU_POWERPC_440GPb = 0x40120440,
4555 CPU_POWERPC_440GPc = 0x40120481,
4556 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
4557 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
4558 CPU_POWERPC_440GRX = 0x200008D0,
4559 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
4560 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
4561 CPU_POWERPC_440GXa = 0x51B21850,
4562 CPU_POWERPC_440GXb = 0x51B21851,
4563 CPU_POWERPC_440GXc = 0x51B21892,
4564 CPU_POWERPC_440GXf = 0x51B21894,
4565 #if 0
4566 CPU_POWERPC_440S = xxx,
4567 #endif
4568 CPU_POWERPC_440SP = 0x53221850,
4569 CPU_POWERPC_440SP2 = 0x53221891,
4570 CPU_POWERPC_440SPE = 0x53421890,
4571 /* PowerPC 460 family */
4572 #if 0
4573 /* Generic PowerPC 464 */
4574 #define CPU_POWERPC_464 CPU_POWERPC_464H90
4575 #endif
4576 /* PowerPC 464 microcontrolers */
4577 #if 0
4578 CPU_POWERPC_464H90 = xxx,
4579 #endif
4580 #if 0
4581 CPU_POWERPC_464H90FP = xxx,
4582 #endif
4583 /* Freescale embedded PowerPC cores */
4584 /* e200 family */
4585 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
4586 #if 0
4587 CPU_POWERPC_e200z0 = xxx,
4588 #endif
4589 #if 0
4590 CPU_POWERPC_e200z3 = xxx,
4591 #endif
4592 CPU_POWERPC_e200z5 = 0x81000000,
4593 CPU_POWERPC_e200z6 = 0x81120000,
4594 /* e300 family */
4595 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
4596 CPU_POWERPC_e300c1 = 0x00830000,
4597 CPU_POWERPC_e300c2 = 0x00840000,
4598 CPU_POWERPC_e300c3 = 0x00850000,
4599 /* e500 family */
4600 #define CPU_POWERPC_e500 CPU_POWERPC_e500_v22
4601 CPU_POWERPC_e500_v11 = 0x80200010,
4602 CPU_POWERPC_e500_v12 = 0x80200020,
4603 CPU_POWERPC_e500_v21 = 0x80210010,
4604 CPU_POWERPC_e500_v22 = 0x80210020,
4605 #if 0
4606 CPU_POWERPC_e500mc = xxx,
4607 #endif
4608 /* e600 family */
4609 CPU_POWERPC_e600 = 0x80040010,
4610 /* PowerPC MPC 5xx cores */
4611 CPU_POWERPC_5xx = 0x00020020,
4612 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
4613 CPU_POWERPC_8xx = 0x00500000,
4614 /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
4615 CPU_POWERPC_82xx_HIP3 = 0x00810101,
4616 CPU_POWERPC_82xx_HIP4 = 0x80811014,
4617 CPU_POWERPC_827x = 0x80822013,
4618 /* PowerPC 6xx cores */
4619 CPU_POWERPC_601 = 0x00010001,
4620 CPU_POWERPC_601a = 0x00010002,
4621 CPU_POWERPC_602 = 0x00050100,
4622 CPU_POWERPC_603 = 0x00030100,
4623 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
4624 CPU_POWERPC_603E_v11 = 0x00060101,
4625 CPU_POWERPC_603E_v12 = 0x00060102,
4626 CPU_POWERPC_603E_v13 = 0x00060103,
4627 CPU_POWERPC_603E_v14 = 0x00060104,
4628 CPU_POWERPC_603E_v22 = 0x00060202,
4629 CPU_POWERPC_603E_v3 = 0x00060300,
4630 CPU_POWERPC_603E_v4 = 0x00060400,
4631 CPU_POWERPC_603E_v41 = 0x00060401,
4632 CPU_POWERPC_603E7t = 0x00071201,
4633 CPU_POWERPC_603E7v = 0x00070100,
4634 CPU_POWERPC_603E7v1 = 0x00070101,
4635 CPU_POWERPC_603E7v2 = 0x00070201,
4636 CPU_POWERPC_603E7 = 0x00070200,
4637 CPU_POWERPC_603P = 0x00070000,
4638 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
4639 CPU_POWERPC_G2 = 0x00810011,
4640 #if 0 // Linux pretends the MSB is zero...
4641 CPU_POWERPC_G2H4 = 0x80811010,
4642 CPU_POWERPC_G2gp = 0x80821010,
4643 CPU_POWERPC_G2ls = 0x90810010,
4644 CPU_POWERPC_G2LE = 0x80820010,
4645 CPU_POWERPC_G2LEgp = 0x80822010,
4646 CPU_POWERPC_G2LEls = 0xA0822010,
4647 #else
4648 CPU_POWERPC_G2H4 = 0x00811010,
4649 CPU_POWERPC_G2gp = 0x00821010,
4650 CPU_POWERPC_G2ls = 0x10810010,
4651 CPU_POWERPC_G2LE = 0x00820010,
4652 CPU_POWERPC_G2LEgp = 0x00822010,
4653 CPU_POWERPC_G2LEls = 0x20822010,
4654 #endif
4655 CPU_POWERPC_604 = 0x00040103,
4656 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
4657 CPU_POWERPC_604E_v10 = 0x00090100, /* Also 2110 & 2120 */
4658 CPU_POWERPC_604E_v22 = 0x00090202,
4659 CPU_POWERPC_604E_v24 = 0x00090204,
4660 CPU_POWERPC_604R = 0x000a0101, /* Also 0x00093102 */
4661 #if 0
4662 CPU_POWERPC_604EV = xxx,
4663 #endif
4664 /* PowerPC 740/750 cores (aka G3) */
4665 /* XXX: missing 0x00084202 */
4666 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
4667 CPU_POWERPC_7x0_v20 = 0x00080200,
4668 CPU_POWERPC_7x0_v21 = 0x00080201,
4669 CPU_POWERPC_7x0_v22 = 0x00080202,
4670 CPU_POWERPC_7x0_v30 = 0x00080300,
4671 CPU_POWERPC_7x0_v31 = 0x00080301,
4672 CPU_POWERPC_740E = 0x00080100,
4673 CPU_POWERPC_7x0P = 0x10080000,
4674 /* XXX: missing 0x00087010 (CL ?) */
4675 CPU_POWERPC_750CL = 0x00087200,
4676 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
4677 CPU_POWERPC_750CX_v21 = 0x00082201,
4678 CPU_POWERPC_750CX_v22 = 0x00082202,
4679 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
4680 CPU_POWERPC_750CXE_v21 = 0x00082211,
4681 CPU_POWERPC_750CXE_v22 = 0x00082212,
4682 CPU_POWERPC_750CXE_v23 = 0x00082213,
4683 CPU_POWERPC_750CXE_v24 = 0x00082214,
4684 CPU_POWERPC_750CXE_v24b = 0x00083214,
4685 CPU_POWERPC_750CXE_v31 = 0x00083211,
4686 CPU_POWERPC_750CXE_v31b = 0x00083311,
4687 CPU_POWERPC_750CXR = 0x00083410,
4688 CPU_POWERPC_750E = 0x00080200,
4689 CPU_POWERPC_750FL = 0x700A0203,
4690 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
4691 CPU_POWERPC_750FX_v10 = 0x70000100,
4692 CPU_POWERPC_750FX_v20 = 0x70000200,
4693 CPU_POWERPC_750FX_v21 = 0x70000201,
4694 CPU_POWERPC_750FX_v22 = 0x70000202,
4695 CPU_POWERPC_750FX_v23 = 0x70000203,
4696 CPU_POWERPC_750GL = 0x70020102,
4697 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
4698 CPU_POWERPC_750GX_v10 = 0x70020100,
4699 CPU_POWERPC_750GX_v11 = 0x70020101,
4700 CPU_POWERPC_750GX_v12 = 0x70020102,
4701 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
4702 CPU_POWERPC_750L_v22 = 0x00088202,
4703 CPU_POWERPC_750L_v30 = 0x00088300,
4704 CPU_POWERPC_750L_v32 = 0x00088302,
4705 /* PowerPC 745/755 cores */
4706 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
4707 CPU_POWERPC_7x5_v10 = 0x00083100,
4708 CPU_POWERPC_7x5_v11 = 0x00083101,
4709 CPU_POWERPC_7x5_v20 = 0x00083200,
4710 CPU_POWERPC_7x5_v21 = 0x00083201,
4711 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
4712 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
4713 CPU_POWERPC_7x5_v24 = 0x00083204,
4714 CPU_POWERPC_7x5_v25 = 0x00083205,
4715 CPU_POWERPC_7x5_v26 = 0x00083206,
4716 CPU_POWERPC_7x5_v27 = 0x00083207,
4717 CPU_POWERPC_7x5_v28 = 0x00083208,
4718 #if 0
4719 CPU_POWERPC_7x5P = xxx,
4720 #endif
4721 /* PowerPC 74xx cores (aka G4) */
4722 /* XXX: missing 0x000C1101 */
4723 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
4724 CPU_POWERPC_7400_v10 = 0x000C0100,
4725 CPU_POWERPC_7400_v11 = 0x000C0101,
4726 CPU_POWERPC_7400_v20 = 0x000C0200,
4727 CPU_POWERPC_7400_v22 = 0x000C0202,
4728 CPU_POWERPC_7400_v26 = 0x000C0206,
4729 CPU_POWERPC_7400_v27 = 0x000C0207,
4730 CPU_POWERPC_7400_v28 = 0x000C0208,
4731 CPU_POWERPC_7400_v29 = 0x000C0209,
4732 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
4733 CPU_POWERPC_7410_v10 = 0x800C1100,
4734 CPU_POWERPC_7410_v11 = 0x800C1101,
4735 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
4736 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
4737 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
4738 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
4739 CPU_POWERPC_7448_v10 = 0x80040100,
4740 CPU_POWERPC_7448_v11 = 0x80040101,
4741 CPU_POWERPC_7448_v20 = 0x80040200,
4742 CPU_POWERPC_7448_v21 = 0x80040201,
4743 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
4744 CPU_POWERPC_7450_v10 = 0x80000100,
4745 CPU_POWERPC_7450_v11 = 0x80000101,
4746 CPU_POWERPC_7450_v12 = 0x80000102,
4747 CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
4748 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
4749 CPU_POWERPC_74x1 = 0x80000203,
4750 CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
4751 /* XXX: missing 0x80010200 */
4752 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
4753 CPU_POWERPC_74x5_v10 = 0x80010100,
4754 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
4755 CPU_POWERPC_74x5_v32 = 0x80010302,
4756 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
4757 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
4758 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
4759 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
4760 CPU_POWERPC_74x7_v11 = 0x80030101, /* aka B: 1.1 */
4761 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
4762 /* 64 bits PowerPC */
4763 #if defined(TARGET_PPC64)
4764 CPU_POWERPC_620 = 0x00140000,
4765 CPU_POWERPC_630 = 0x00400000,
4766 CPU_POWERPC_631 = 0x00410104,
4767 CPU_POWERPC_POWER4 = 0x00350000,
4768 CPU_POWERPC_POWER4P = 0x00380000,
4769 CPU_POWERPC_POWER5 = 0x003A0203,
4770 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
4771 CPU_POWERPC_POWER5P = 0x003B0000,
4772 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
4773 CPU_POWERPC_POWER6 = 0x003E0000,
4774 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 running POWER5 mode */
4775 CPU_POWERPC_POWER6A = 0x0F000002,
4776 CPU_POWERPC_970 = 0x00390202,
4777 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
4778 CPU_POWERPC_970FX_v10 = 0x00391100,
4779 CPU_POWERPC_970FX_v20 = 0x003C0200,
4780 CPU_POWERPC_970FX_v21 = 0x003C0201,
4781 CPU_POWERPC_970FX_v30 = 0x003C0300,
4782 CPU_POWERPC_970FX_v31 = 0x003C0301,
4783 CPU_POWERPC_970GX = 0x00450000,
4784 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
4785 CPU_POWERPC_970MP_v10 = 0x00440100,
4786 CPU_POWERPC_970MP_v11 = 0x00440101,
4787 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
4788 CPU_POWERPC_CELL_v10 = 0x00700100,
4789 CPU_POWERPC_CELL_v20 = 0x00700400,
4790 CPU_POWERPC_CELL_v30 = 0x00700500,
4791 CPU_POWERPC_CELL_v31 = 0x00700501,
4792 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
4793 CPU_POWERPC_RS64 = 0x00330000,
4794 CPU_POWERPC_RS64II = 0x00340000,
4795 CPU_POWERPC_RS64III = 0x00360000,
4796 CPU_POWERPC_RS64IV = 0x00370000,
4797 #endif /* defined(TARGET_PPC64) */
4798 /* Original POWER */
4799 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
4800 * POWER2 (RIOS2) & RSC2 (P2SC) here
4801 */
4802 #if 0
4803 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
4804 #endif
4805 #if 0
4806 CPU_POWER2 = xxx, /* 0x40000 ? */
4807 #endif
4808 /* PA Semi core */
4809 CPU_POWERPC_PA6T = 0x00900000,
4810 };
4811
4812 /* System version register (used on MPC 8xxx) */
4813 enum {
4814 PPC_SVR_8540 = 0x80300000,
4815 PPC_SVR_8541E = 0x807A0010,
4816 PPC_SVR_8543v10 = 0x80320010,
4817 PPC_SVR_8543v11 = 0x80320011,
4818 PPC_SVR_8543v20 = 0x80320020,
4819 PPC_SVR_8543Ev10 = 0x803A0010,
4820 PPC_SVR_8543Ev11 = 0x803A0011,
4821 PPC_SVR_8543Ev20 = 0x803A0020,
4822 PPC_SVR_8545 = 0x80310220,
4823 PPC_SVR_8545E = 0x80390220,
4824 PPC_SVR_8547E = 0x80390120,
4825 PPC_SCR_8548v10 = 0x80310010,
4826 PPC_SCR_8548v11 = 0x80310011,
4827 PPC_SCR_8548v20 = 0x80310020,
4828 PPC_SVR_8548Ev10 = 0x80390010,
4829 PPC_SVR_8548Ev11 = 0x80390011,
4830 PPC_SVR_8548Ev20 = 0x80390020,
4831 PPC_SVR_8555E = 0x80790010,
4832 PPC_SVR_8560v10 = 0x80700010,
4833 PPC_SVR_8560v20 = 0x80700020,
4834 };
4835
4836 /*****************************************************************************/
4837 /* PowerPC CPU definitions */
4838 #define POWERPC_DEF(_name, _pvr, _pvr_mask, _type) \
4839 { \
4840 .name = _name, \
4841 .pvr = _pvr, \
4842 .pvr_mask = _pvr_mask, \
4843 .insns_flags = glue(POWERPC_INSNS_,_type), \
4844 .msr_mask = glue(POWERPC_MSRM_,_type), \
4845 .mmu_model = glue(POWERPC_MMU_,_type), \
4846 .excp_model = glue(POWERPC_EXCP_,_type), \
4847 .bus_model = glue(POWERPC_INPUT_,_type), \
4848 .bfd_mach = glue(POWERPC_BFDM_,_type), \
4849 .flags = glue(POWERPC_FLAG_,_type), \
4850 .init_proc = &glue(init_proc_,_type), \
4851 }
4852
4853 static ppc_def_t ppc_defs[] = {
4854 /* Embedded PowerPC */
4855 /* PowerPC 401 family */
4856 /* Generic PowerPC 401 */
4857 POWERPC_DEF("401", CPU_POWERPC_401, 0xFFFF0000, 401),
4858 /* PowerPC 401 cores */
4859 /* PowerPC 401A1 */
4860 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 0xFFFFFFFF, 401),
4861 /* PowerPC 401B2 */
4862 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 0xFFFFFFFF, 401x2),
4863 #if defined (TODO)
4864 /* PowerPC 401B3 */
4865 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 0xFFFFFFFF, 401x3),
4866 #endif
4867 /* PowerPC 401C2 */
4868 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 0xFFFFFFFF, 401x2),
4869 /* PowerPC 401D2 */
4870 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 0xFFFFFFFF, 401x2),
4871 /* PowerPC 401E2 */
4872 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 0xFFFFFFFF, 401x2),
4873 /* PowerPC 401F2 */
4874 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 0xFFFFFFFF, 401x2),
4875 /* PowerPC 401G2 */
4876 /* XXX: to be checked */
4877 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 0xFFFFFFFF, 401x2),
4878 /* PowerPC 401 microcontrolers */
4879 #if defined (TODO)
4880 /* PowerPC 401GF */
4881 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 0xFFFFFFFF, 401),
4882 #endif
4883 /* IOP480 (401 microcontroler) */
4884 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, 0xFFFFFFFF, IOP480),
4885 /* IBM Processor for Network Resources */
4886 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 0xFFFFFFFF, 401),
4887 #if defined (TODO)
4888 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 0xFFFFFFFF, 401),
4889 #endif
4890 /* PowerPC 403 family */
4891 /* Generic PowerPC 403 */
4892 POWERPC_DEF("403", CPU_POWERPC_403, 0xFFFF0000, 403),
4893 /* PowerPC 403 microcontrolers */
4894 /* PowerPC 403 GA */
4895 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 0xFFFFFFFF, 403),
4896 /* PowerPC 403 GB */
4897 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 0xFFFFFFFF, 403),
4898 /* PowerPC 403 GC */
4899 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 0xFFFFFFFF, 403),
4900 /* PowerPC 403 GCX */
4901 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 0xFFFFFFFF, 403GCX),
4902 #if defined (TODO)
4903 /* PowerPC 403 GP */
4904 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 0xFFFFFFFF, 403),
4905 #endif
4906 /* PowerPC 405 family */
4907 /* Generic PowerPC 405 */
4908 POWERPC_DEF("405", CPU_POWERPC_405, 0xFFFF0000, 405),
4909 /* PowerPC 405 cores */
4910 #if defined (TODO)
4911 /* PowerPC 405 A3 */
4912 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 0xFFFFFFFF, 405),
4913 #endif
4914 #if defined (TODO)
4915 /* PowerPC 405 A4 */
4916 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 0xFFFFFFFF, 405),
4917 #endif
4918 #if defined (TODO)
4919 /* PowerPC 405 B3 */
4920 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 0xFFFFFFFF, 405),
4921 #endif
4922 #if defined (TODO)
4923 /* PowerPC 405 B4 */
4924 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 0xFFFFFFFF, 405),
4925 #endif
4926 #if defined (TODO)
4927 /* PowerPC 405 C3 */
4928 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 0xFFFFFFFF, 405),
4929 #endif
4930 #if defined (TODO)
4931 /* PowerPC 405 C4 */
4932 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 0xFFFFFFFF, 405),
4933 #endif
4934 /* PowerPC 405 D2 */
4935 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 0xFFFFFFFF, 405),
4936 #if defined (TODO)
4937 /* PowerPC 405 D3 */
4938 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 0xFFFFFFFF, 405),
4939 #endif
4940 /* PowerPC 405 D4 */
4941 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 0xFFFFFFFF, 405),
4942 #if defined (TODO)
4943 /* PowerPC 405 D5 */
4944 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 0xFFFFFFFF, 405),
4945 #endif
4946 #if defined (TODO)
4947 /* PowerPC 405 E4 */
4948 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 0xFFFFFFFF, 405),
4949 #endif
4950 #if defined (TODO)
4951 /* PowerPC 405 F4 */
4952 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 0xFFFFFFFF, 405),
4953 #endif
4954 #if defined (TODO)
4955 /* PowerPC 405 F5 */
4956 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 0xFFFFFFFF, 405),
4957 #endif
4958 #if defined (TODO)
4959 /* PowerPC 405 F6 */
4960 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 0xFFFFFFFF, 405),
4961 #endif
4962 /* PowerPC 405 microcontrolers */
4963 /* PowerPC 405 CR */
4964 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 0xFFFFFFFF, 405),
4965 /* PowerPC 405 CRa */
4966 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 0xFFFFFFFF, 405),
4967 /* PowerPC 405 CRb */
4968 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 0xFFFFFFFF, 405),
4969 /* PowerPC 405 CRc */
4970 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 0xFFFFFFFF, 405),
4971 /* PowerPC 405 EP */
4972 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 0xFFFFFFFF, 405),
4973 #if defined(TODO)
4974 /* PowerPC 405 EXr */
4975 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 0xFFFFFFFF, 405),
4976 #endif
4977 /* PowerPC 405 EZ */
4978 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 0xFFFFFFFF, 405),
4979 #if defined(TODO)
4980 /* PowerPC 405 FX */
4981 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 0xFFFFFFFF, 405),
4982 #endif
4983 /* PowerPC 405 GP */
4984 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 0xFFFFFFFF, 405),
4985 /* PowerPC 405 GPa */
4986 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 0xFFFFFFFF, 405),
4987 /* PowerPC 405 GPb */
4988 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 0xFFFFFFFF, 405),
4989 /* PowerPC 405 GPc */
4990 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 0xFFFFFFFF, 405),
4991 /* PowerPC 405 GPd */
4992 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 0xFFFFFFFF, 405),
4993 /* PowerPC 405 GPe */
4994 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 0xFFFFFFFF, 405),
4995 /* PowerPC 405 GPR */
4996 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 0xFFFFFFFF, 405),
4997 #if defined(TODO)
4998 /* PowerPC 405 H */
4999 POWERPC_DEF("405H", CPU_POWERPC_405H, 0xFFFFFFFF, 405),
5000 #endif
5001 #if defined(TODO)
5002 /* PowerPC 405 L */
5003 POWERPC_DEF("405L", CPU_POWERPC_405L, 0xFFFFFFFF, 405),
5004 #endif
5005 /* PowerPC 405 LP */
5006 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 0xFFFFFFFF, 405),
5007 #if defined(TODO)
5008 /* PowerPC 405 PM */
5009 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 0xFFFFFFFF, 405),
5010 #endif
5011 #if defined(TODO)
5012 /* PowerPC 405 PS */
5013 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 0xFFFFFFFF, 405),
5014 #endif
5015 #if defined(TODO)
5016 /* PowerPC 405 S */
5017 POWERPC_DEF("405S", CPU_POWERPC_405S, 0xFFFFFFFF, 405),
5018 #endif
5019 /* Npe405 H */
5020 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 0xFFFFFFFF, 405),
5021 /* Npe405 H2 */
5022 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 0xFFFFFFFF, 405),
5023 /* Npe405 L */
5024 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 0xFFFFFFFF, 405),
5025 /* Npe4GS3 */
5026 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 0xFFFFFFFF, 405),
5027 #if defined (TODO)
5028 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 0xFFFFFFFF, 405),
5029 #endif
5030 #if defined (TODO)
5031 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 0xFFFFFFFF, 405),
5032 #endif
5033 #if defined (TODO)
5034 /* PowerPC LC77700 (Sanyo) */
5035 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 0xFFFFFFFF, 405),
5036 #endif
5037 /* PowerPC 401/403/405 based set-top-box microcontrolers */
5038 #if defined (TODO)
5039 /* STB010000 */
5040 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 0xFFFFFFFF, 401x2),
5041 #endif
5042 #if defined (TODO)
5043 /* STB01010 */
5044 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 0xFFFFFFFF, 401x2),
5045 #endif
5046 #if defined (TODO)
5047 /* STB0210 */
5048 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 0xFFFFFFFF, 401x3),
5049 #endif
5050 /* STB03xx */
5051 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 0xFFFFFFFF, 405),
5052 #if defined (TODO)
5053 /* STB043x */
5054 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 0xFFFFFFFF, 405),
5055 #endif
5056 #if defined (TODO)
5057 /* STB045x */
5058 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 0xFFFFFFFF, 405),
5059 #endif
5060 /* STB04xx */
5061 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 0xFFFF0000, 405),
5062 /* STB25xx */
5063 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 0xFFFFFFFF, 405),
5064 #if defined (TODO)
5065 /* STB130 */
5066 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 0xFFFFFFFF, 405),
5067 #endif
5068 /* Xilinx PowerPC 405 cores */
5069 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 0xFFFFFFFF, 405),
5070 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 0xFFFFFFFF, 405),
5071 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 0xFFFFFFFF, 405),
5072 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 0xFFFFFFFF, 405),
5073 #if defined (TODO)
5074 /* Zarlink ZL10310 */
5075 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 0xFFFFFFFF, 405),
5076 #endif
5077 #if defined (TODO)
5078 /* Zarlink ZL10311 */
5079 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 0xFFFFFFFF, 405),
5080 #endif
5081 #if defined (TODO)
5082 /* Zarlink ZL10320 */
5083 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 0xFFFFFFFF, 405),
5084 #endif
5085 #if defined (TODO)
5086 /* Zarlink ZL10321 */
5087 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 0xFFFFFFFF, 405),
5088 #endif
5089 /* PowerPC 440 family */
5090 /* Generic PowerPC 440 */
5091 POWERPC_DEF("440", CPU_POWERPC_440, 0xFFFFFFFF, 440GP),
5092 /* PowerPC 440 cores */
5093 #if defined (TODO)
5094 /* PowerPC 440 A4 */
5095 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 0xFFFFFFFF, 440x4),
5096 #endif
5097 #if defined (TODO)
5098 /* PowerPC 440 A5 */
5099 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 0xFFFFFFFF, 440x5),
5100 #endif
5101 #if defined (TODO)
5102 /* PowerPC 440 B4 */
5103 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 0xFFFFFFFF, 440x4),
5104 #endif
5105 #if defined (TODO)
5106 /* PowerPC 440 G4 */
5107 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 0xFFFFFFFF, 440x4),
5108 #endif
5109 #if defined (TODO)
5110 /* PowerPC 440 F5 */
5111 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 0xFFFFFFFF, 440x5),
5112 #endif
5113 #if defined (TODO)
5114 /* PowerPC 440 G5 */
5115 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 0xFFFFFFFF, 440x5),
5116 #endif
5117 #if defined (TODO)
5118 /* PowerPC 440H4 */
5119 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 0xFFFFFFFF, 440x4),
5120 #endif
5121 #if defined (TODO)
5122 /* PowerPC 440H6 */
5123 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 0xFFFFFFFF, 440Gx5),
5124 #endif
5125 /* PowerPC 440 microcontrolers */
5126 /* PowerPC 440 EP */
5127 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 0xFFFFFFFF, 440EP),
5128 /* PowerPC 440 EPa */
5129 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 0xFFFFFFFF, 440EP),
5130 /* PowerPC 440 EPb */
5131 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 0xFFFFFFFF, 440EP),
5132 /* PowerPC 440 EPX */
5133 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 0xFFFFFFFF, 440EP),
5134 /* PowerPC 440 GP */
5135 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 0xFFFFFFFF, 440GP),
5136 /* PowerPC 440 GPb */
5137 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 0xFFFFFFFF, 440GP),
5138 /* PowerPC 440 GPc */
5139 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 0xFFFFFFFF, 440GP),
5140 /* PowerPC 440 GR */
5141 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 0xFFFFFFFF, 440x5),
5142 /* PowerPC 440 GRa */
5143 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 0xFFFFFFFF, 440x5),
5144 /* PowerPC 440 GRX */
5145 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 0xFFFFFFFF, 440x5),
5146 /* PowerPC 440 GX */
5147 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 0xFFFFFFFF, 440EP),
5148 /* PowerPC 440 GXa */
5149 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 0xFFFFFFFF, 440EP),
5150 /* PowerPC 440 GXb */
5151 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 0xFFFFFFFF, 440EP),
5152 /* PowerPC 440 GXc */
5153 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 0xFFFFFFFF, 440EP),
5154 /* PowerPC 440 GXf */
5155 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 0xFFFFFFFF, 440EP),
5156 #if defined(TODO)
5157 /* PowerPC 440 S */
5158 POWERPC_DEF("440S", CPU_POWERPC_440S, 0xFFFFFFFF, 440),
5159 #endif
5160 /* PowerPC 440 SP */
5161 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 0xFFFFFFFF, 440EP),
5162 /* PowerPC 440 SP2 */
5163 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 0xFFFFFFFF, 440EP),
5164 /* PowerPC 440 SPE */
5165 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 0xFFFFFFFF, 440EP),
5166 /* PowerPC 460 family */
5167 #if defined (TODO)
5168 /* Generic PowerPC 464 */
5169 POWERPC_DEF("464", CPU_POWERPC_464, 0xFFFFFFFF, 460),
5170 #endif
5171 /* PowerPC 464 microcontrolers */
5172 #if defined (TODO)
5173 /* PowerPC 464H90 */
5174 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 0xFFFFFFFF, 460),
5175 #endif
5176 #if defined (TODO)
5177 /* PowerPC 464H90F */
5178 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 0xFFFFFFFF, 460F),
5179 #endif
5180 /* Freescale embedded PowerPC cores */
5181 /* e200 family */
5182 #if defined (TODO)
5183 /* Generic PowerPC e200 core */
5184 POWERPC_DEF("e200", CPU_POWERPC_e200, 0xFFFFFFFF, e200),
5185 #endif
5186 #if defined (TODO)
5187 /* PowerPC e200z5 core */
5188 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, 0xFFFFFFFF, e200),
5189 #endif
5190 #if defined (TODO)
5191 /* PowerPC e200z6 core */
5192 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, 0xFFFFFFFF, e200),
5193 #endif
5194 /* e300 family */
5195 #if defined (TODO)
5196 /* Generic PowerPC e300 core */
5197 POWERPC_DEF("e300", CPU_POWERPC_e300, 0xFFFFFFFF, e300),
5198 #endif
5199 #if defined (TODO)
5200 /* PowerPC e300c1 core */
5201 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, 0xFFFFFFFF, e300),
5202 #endif
5203 #if defined (TODO)
5204 /* PowerPC e300c2 core */
5205 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, 0xFFFFFFFF, e300),
5206 #endif
5207 #if defined (TODO)
5208 /* PowerPC e300c3 core */
5209 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, 0xFFFFFFFF, e300),
5210 #endif
5211 /* e500 family */
5212 #if defined (TODO)
5213 /* PowerPC e500 core */
5214 POWERPC_DEF("e500", CPU_POWERPC_e500, 0xFFFFFFFF, e500),
5215 #endif
5216 #if defined (TODO)
5217 /* PowerPC e500 v1.1 core */
5218 POWERPC_DEF("e500v1.1", CPU_POWERPC_e500_v11, 0xFFFFFFFF, e500),
5219 #endif
5220 #if defined (TODO)
5221 /* PowerPC e500 v1.2 core */
5222 POWERPC_DEF("e500v1.2", CPU_POWERPC_e500_v12, 0xFFFFFFFF, e500),
5223 #endif
5224 #if defined (TODO)
5225 /* PowerPC e500 v2.1 core */
5226 POWERPC_DEF("e500v2.1", CPU_POWERPC_e500_v21, 0xFFFFFFFF, e500),
5227 #endif
5228 #if defined (TODO)
5229 /* PowerPC e500 v2.2 core */
5230 POWERPC_DEF("e500v2.2", CPU_POWERPC_e500_v22, 0xFFFFFFFF, e500),
5231 #endif
5232 /* e600 family */
5233 #if defined (TODO)
5234 /* PowerPC e600 core */
5235 POWERPC_DEF("e600", CPU_POWERPC_e600, 0xFFFFFFFF, e600),
5236 #endif
5237 /* PowerPC MPC 5xx cores */
5238 #if defined (TODO)
5239 /* PowerPC MPC 5xx */
5240 POWERPC_DEF("mpc5xx", CPU_POWERPC_5xx, 0xFFFFFFFF, 5xx),
5241 #endif
5242 /* PowerPC MPC 8xx cores */
5243 #if defined (TODO)
5244 /* PowerPC MPC 8xx */
5245 POWERPC_DEF("mpc8xx", CPU_POWERPC_8xx, 0xFFFFFFFF, 8xx),
5246 #endif
5247 /* PowerPC MPC 8xxx cores */
5248 #if defined (TODO)
5249 /* PowerPC MPC 82xx HIP3 */
5250 POWERPC_DEF("mpc82xxhip3", CPU_POWERPC_82xx_HIP3, 0xFFFFFFFF, 82xx),
5251 #endif
5252 #if defined (TODO)
5253 /* PowerPC MPC 82xx HIP4 */
5254 POWERPC_DEF("mpc82xxhip4", CPU_POWERPC_82xx_HIP4, 0xFFFFFFFF, 82xx),
5255 #endif
5256 #if defined (TODO)
5257 /* PowerPC MPC 827x */
5258 POWERPC_DEF("mpc827x", CPU_POWERPC_827x, 0xFFFFFFFF, 827x),
5259 #endif
5260
5261 /* 32 bits "classic" PowerPC */
5262 /* PowerPC 6xx family */
5263 /* PowerPC 601 */
5264 POWERPC_DEF("601", CPU_POWERPC_601, 0xFFFFFFFF, 601),
5265 /* PowerPC 601v2 */
5266 POWERPC_DEF("601a", CPU_POWERPC_601a, 0xFFFFFFFF, 601),
5267 /* PowerPC 602 */
5268 POWERPC_DEF("602", CPU_POWERPC_602, 0xFFFFFFFF, 602),
5269 /* PowerPC 603 */
5270 POWERPC_DEF("603", CPU_POWERPC_603, 0xFFFFFFFF, 603),
5271 /* Code name for PowerPC 603 */
5272 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 0xFFFFFFFF, 603),
5273 /* PowerPC 603e */
5274 POWERPC_DEF("603e", CPU_POWERPC_603E, 0xFFFFFFFF, 603E),
5275 /* Code name for PowerPC 603e */
5276 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 0xFFFFFFFF, 603E),
5277 /* PowerPC 603e v1.1 */
5278 POWERPC_DEF("603e1.1", CPU_POWERPC_603E_v11, 0xFFFFFFFF, 603E),
5279 /* PowerPC 603e v1.2 */
5280 POWERPC_DEF("603e1.2", CPU_POWERPC_603E_v12, 0xFFFFFFFF, 603E),
5281 /* PowerPC 603e v1.3 */
5282 POWERPC_DEF("603e1.3", CPU_POWERPC_603E_v13, 0xFFFFFFFF, 603E),
5283 /* PowerPC 603e v1.4 */
5284 POWERPC_DEF("603e1.4", CPU_POWERPC_603E_v14, 0xFFFFFFFF, 603E),
5285 /* PowerPC 603e v2.2 */
5286 POWERPC_DEF("603e2.2", CPU_POWERPC_603E_v22, 0xFFFFFFFF, 603E),
5287 /* PowerPC 603e v3 */
5288 POWERPC_DEF("603e3", CPU_POWERPC_603E_v3, 0xFFFFFFFF, 603E),
5289 /* PowerPC 603e v4 */
5290 POWERPC_DEF("603e4", CPU_POWERPC_603E_v4, 0xFFFFFFFF, 603E),
5291 /* PowerPC 603e v4.1 */
5292 POWERPC_DEF("603e4.1", CPU_POWERPC_603E_v41, 0xFFFFFFFF, 603E),
5293 /* PowerPC 603e */
5294 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 0xFFFFFFFF, 603E),
5295 /* PowerPC 603e7t */
5296 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 0xFFFFFFFF, 603E),
5297 /* PowerPC 603e7v */
5298 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E),
5299 /* Code name for PowerPC 603ev */
5300 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E),
5301 /* PowerPC 603e7v1 */
5302 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 0xFFFFFFFF, 603E),
5303 /* PowerPC 603e7v2 */
5304 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 0xFFFFFFFF, 603E),
5305 /* PowerPC 603p */
5306 /* to be checked */
5307 POWERPC_DEF("603p", CPU_POWERPC_603P, 0xFFFFFFFF, 603),
5308 /* PowerPC 603r */
5309 POWERPC_DEF("603r", CPU_POWERPC_603R, 0xFFFFFFFF, 603E),
5310 /* Code name for PowerPC 603r */
5311 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 0xFFFFFFFF, 603E),
5312 /* PowerPC G2 core */
5313 POWERPC_DEF("G2", CPU_POWERPC_G2, 0xFFFFFFFF, G2),
5314 /* PowerPC G2 H4 */
5315 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, 0xFFFFFFFF, G2),
5316 /* PowerPC G2 GP */
5317 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, 0xFFFFFFFF, G2),
5318 /* PowerPC G2 LS */
5319 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, 0xFFFFFFFF, G2),
5320 /* PowerPC G2LE */
5321 /* Same as G2, with little-endian mode support */
5322 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, 0xFFFFFFFF, G2LE),
5323 /* PowerPC G2LE GP */
5324 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, 0xFFFFFFFF, G2LE),
5325 /* PowerPC G2LE LS */
5326 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, 0xFFFFFFFF, G2LE),
5327 /* PowerPC 604 */
5328 POWERPC_DEF("604", CPU_POWERPC_604, 0xFFFFFFFF, 604),
5329 /* PowerPC 604e */
5330 POWERPC_DEF("604e", CPU_POWERPC_604E, 0xFFFFFFFF, 604),
5331 /* PowerPC 604e v1.0 */
5332 POWERPC_DEF("604e1.0", CPU_POWERPC_604E_v10, 0xFFFFFFFF, 604),
5333 /* PowerPC 604e v2.2 */
5334 POWERPC_DEF("604e2.2", CPU_POWERPC_604E_v22, 0xFFFFFFFF, 604),
5335 /* PowerPC 604e v2.4 */
5336 POWERPC_DEF("604e2.4", CPU_POWERPC_604E_v24, 0xFFFFFFFF, 604),
5337 /* PowerPC 604r */
5338 POWERPC_DEF("604r", CPU_POWERPC_604R, 0xFFFFFFFF, 604),
5339 #if defined(TODO)
5340 /* PowerPC 604ev */
5341 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 0xFFFFFFFF, 604),
5342 #endif
5343 /* PowerPC 7xx family */
5344 /* Generic PowerPC 740 (G3) */
5345 POWERPC_DEF("740", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5346 /* Generic PowerPC 750 (G3) */
5347 POWERPC_DEF("750", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5348 /* Code name for generic PowerPC 740/750 (G3) */
5349 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5350 /* PowerPC 740/750 is also known as G3 */
5351 POWERPC_DEF("G3", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5352 /* PowerPC 740 v2.0 (G3) */
5353 POWERPC_DEF("740v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0),
5354 /* PowerPC 750 v2.0 (G3) */
5355 POWERPC_DEF("750v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0),
5356 /* PowerPC 740 v2.1 (G3) */
5357 POWERPC_DEF("740v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0),
5358 /* PowerPC 750 v2.1 (G3) */
5359 POWERPC_DEF("750v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0),
5360 /* PowerPC 740 v2.2 (G3) */
5361 POWERPC_DEF("740v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0),
5362 /* PowerPC 750 v2.2 (G3) */
5363 POWERPC_DEF("750v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0),
5364 /* PowerPC 740 v3.0 (G3) */
5365 POWERPC_DEF("740v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0),
5366 /* PowerPC 750 v3.0 (G3) */
5367 POWERPC_DEF("750v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0),
5368 /* PowerPC 740 v3.1 (G3) */
5369 POWERPC_DEF("740v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0),
5370 /* PowerPC 750 v3.1 (G3) */
5371 POWERPC_DEF("750v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0),
5372 /* PowerPC 740E (G3) */
5373 POWERPC_DEF("740e", CPU_POWERPC_740E, 0xFFFFFFFF, 7x0),
5374 /* PowerPC 740P (G3) */
5375 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5376 /* PowerPC 750P (G3) */
5377 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5378 /* Code name for PowerPC 740P/750P (G3) */
5379 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5380 /* PowerPC 750CL (G3 embedded) */
5381 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 0xFFFFFFFF, 7x0),
5382 /* PowerPC 750CX (G3 embedded) */
5383 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 0xFFFFFFFF, 7x0),
5384 /* PowerPC 750CX v2.1 (G3 embedded) */
5385 POWERPC_DEF("750cx2.1", CPU_POWERPC_750CX_v21, 0xFFFFFFFF, 7x0),
5386 /* PowerPC 750CX v2.2 (G3 embedded) */
5387 POWERPC_DEF("750cx2.2", CPU_POWERPC_750CX_v22, 0xFFFFFFFF, 7x0),
5388 /* PowerPC 750CXe (G3 embedded) */
5389 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 0xFFFFFFFF, 7x0),
5390 /* PowerPC 750CXe v2.1 (G3 embedded) */
5391 POWERPC_DEF("750cxe21", CPU_POWERPC_750CXE_v21, 0xFFFFFFFF, 7x0),
5392 /* PowerPC 750CXe v2.2 (G3 embedded) */
5393 POWERPC_DEF("750cxe22", CPU_POWERPC_750CXE_v22, 0xFFFFFFFF, 7x0),
5394 /* PowerPC 750CXe v2.3 (G3 embedded) */
5395 POWERPC_DEF("750cxe23", CPU_POWERPC_750CXE_v23, 0xFFFFFFFF, 7x0),
5396 /* PowerPC 750CXe v2.4 (G3 embedded) */
5397 POWERPC_DEF("750cxe24", CPU_POWERPC_750CXE_v24, 0xFFFFFFFF, 7x0),
5398 /* PowerPC 750CXe v2.4b (G3 embedded) */
5399 POWERPC_DEF("750cxe24b", CPU_POWERPC_750CXE_v24b, 0xFFFFFFFF, 7x0),
5400 /* PowerPC 750CXe v3.1 (G3 embedded) */
5401 POWERPC_DEF("750cxe31", CPU_POWERPC_750CXE_v31, 0xFFFFFFFF, 7x0),
5402 /* PowerPC 750CXe v3.1b (G3 embedded) */
5403 POWERPC_DEF("750cxe3.1b", CPU_POWERPC_750CXE_v31b, 0xFFFFFFFF, 7x0),
5404 /* PowerPC 750CXr (G3 embedded) */
5405 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 0xFFFFFFFF, 7x0),
5406 /* PowerPC 750E (G3) */
5407 POWERPC_DEF("750e", CPU_POWERPC_750E, 0xFFFFFFFF, 7x0),
5408 /* PowerPC 750FL (G3 embedded) */
5409 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 0xFFFFFFFF, 750fx),
5410 /* PowerPC 750FX (G3 embedded) */
5411 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 0xFFFFFFFF, 750fx),
5412 /* PowerPC 750FX v1.0 (G3 embedded) */
5413 POWERPC_DEF("750fx1.0", CPU_POWERPC_750FX_v10, 0xFFFFFFFF, 750fx),
5414 /* PowerPC 750FX v2.0 (G3 embedded) */
5415 POWERPC_DEF("750fx2.0", CPU_POWERPC_750FX_v20, 0xFFFFFFFF, 750fx),
5416 /* PowerPC 750FX v2.1 (G3 embedded) */
5417 POWERPC_DEF("750fx2.1", CPU_POWERPC_750FX_v21, 0xFFFFFFFF, 750fx),
5418 /* PowerPC 750FX v2.2 (G3 embedded) */
5419 POWERPC_DEF("750fx2.2", CPU_POWERPC_750FX_v22, 0xFFFFFFFF, 750fx),
5420 /* PowerPC 750FX v2.3 (G3 embedded) */
5421 POWERPC_DEF("750fx2.3", CPU_POWERPC_750FX_v23, 0xFFFFFFFF, 750fx),
5422 /* PowerPC 750GL (G3 embedded) */
5423 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 0xFFFFFFFF, 750fx),
5424 /* PowerPC 750GX (G3 embedded) */
5425 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 0xFFFFFFFF, 750fx),
5426 /* PowerPC 750GX v1.0 (G3 embedded) */
5427 POWERPC_DEF("750gx1.0", CPU_POWERPC_750GX_v10, 0xFFFFFFFF, 750fx),
5428 /* PowerPC 750GX v1.1 (G3 embedded) */
5429 POWERPC_DEF("750gx1.1", CPU_POWERPC_750GX_v11, 0xFFFFFFFF, 750fx),
5430 /* PowerPC 750GX v1.2 (G3 embedded) */
5431 POWERPC_DEF("750gx1.2", CPU_POWERPC_750GX_v12, 0xFFFFFFFF, 750fx),
5432 /* PowerPC 750L (G3 embedded) */
5433 POWERPC_DEF("750l", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0),
5434 /* Code name for PowerPC 750L (G3 embedded) */
5435 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0),
5436 /* PowerPC 750L v2.2 (G3 embedded) */
5437 POWERPC_DEF("750l2.2", CPU_POWERPC_750L_v22, 0xFFFFFFFF, 7x0),
5438 /* PowerPC 750L v3.0 (G3 embedded) */
5439 POWERPC_DEF("750l3.0", CPU_POWERPC_750L_v30, 0xFFFFFFFF, 7x0),
5440 /* PowerPC 750L v3.2 (G3 embedded) */
5441 POWERPC_DEF("750l3.2", CPU_POWERPC_750L_v32, 0xFFFFFFFF, 7x0),
5442 /* Generic PowerPC 745 */
5443 POWERPC_DEF("745", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5444 /* Generic PowerPC 755 */
5445 POWERPC_DEF("755", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5446 /* Code name for PowerPC 745/755 */
5447 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5448 /* PowerPC 745 v1.0 */
5449 POWERPC_DEF("745v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5),
5450 /* PowerPC 755 v1.0 */
5451 POWERPC_DEF("755v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5),
5452 /* PowerPC 745 v1.1 */
5453 POWERPC_DEF("745v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5),
5454 /* PowerPC 755 v1.1 */
5455 POWERPC_DEF("755v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5),
5456 /* PowerPC 745 v2.0 */
5457 POWERPC_DEF("745v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5),
5458 /* PowerPC 755 v2.0 */
5459 POWERPC_DEF("755v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5),
5460 /* PowerPC 745 v2.1 */
5461 POWERPC_DEF("745v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5),
5462 /* PowerPC 755 v2.1 */
5463 POWERPC_DEF("755v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5),
5464 /* PowerPC 745 v2.2 */
5465 POWERPC_DEF("745v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5),
5466 /* PowerPC 755 v2.2 */
5467 POWERPC_DEF("755v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5),
5468 /* PowerPC 745 v2.3 */
5469 POWERPC_DEF("745v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5),
5470 /* PowerPC 755 v2.3 */
5471 POWERPC_DEF("755v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5),
5472 /* PowerPC 745 v2.4 */
5473 POWERPC_DEF("745v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5),
5474 /* PowerPC 755 v2.4 */
5475 POWERPC_DEF("755v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5),
5476 /* PowerPC 745 v2.5 */
5477 POWERPC_DEF("745v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5),
5478 /* PowerPC 755 v2.5 */
5479 POWERPC_DEF("755v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5),
5480 /* PowerPC 745 v2.6 */
5481 POWERPC_DEF("745v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5),
5482 /* PowerPC 755 v2.6 */
5483 POWERPC_DEF("755v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5),
5484 /* PowerPC 745 v2.7 */
5485 POWERPC_DEF("745v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5),
5486 /* PowerPC 755 v2.7 */
5487 POWERPC_DEF("755v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5),
5488 /* PowerPC 745 v2.8 */
5489 POWERPC_DEF("745v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5),
5490 /* PowerPC 755 v2.8 */
5491 POWERPC_DEF("755v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5),
5492 #if defined (TODO)
5493 /* PowerPC 745P (G3) */
5494 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5),
5495 /* PowerPC 755P (G3) */
5496 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5),
5497 #endif
5498 /* PowerPC 74xx family */
5499 /* PowerPC 7400 (G4) */
5500 POWERPC_DEF("7400", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5501 /* Code name for PowerPC 7400 */
5502 POWERPC_DEF("Max", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5503 /* PowerPC 74xx is also well known as G4 */
5504 POWERPC_DEF("G4", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5505 /* PowerPC 7400 v1.0 (G4) */
5506 POWERPC_DEF("7400v1.0", CPU_POWERPC_7400_v10, 0xFFFFFFFF, 7400),
5507 /* PowerPC 7400 v1.1 (G4) */
5508 POWERPC_DEF("7400v1.1", CPU_POWERPC_7400_v11, 0xFFFFFFFF, 7400),
5509 /* PowerPC 7400 v2.0 (G4) */
5510 POWERPC_DEF("7400v2.0", CPU_POWERPC_7400_v20, 0xFFFFFFFF, 7400),
5511 /* PowerPC 7400 v2.2 (G4) */
5512 POWERPC_DEF("7400v2.2", CPU_POWERPC_7400_v22, 0xFFFFFFFF, 7400),
5513 /* PowerPC 7400 v2.6 (G4) */
5514 POWERPC_DEF("7400v2.6", CPU_POWERPC_7400_v26, 0xFFFFFFFF, 7400),
5515 /* PowerPC 7400 v2.7 (G4) */
5516 POWERPC_DEF("7400v2.7", CPU_POWERPC_7400_v27, 0xFFFFFFFF, 7400),
5517 /* PowerPC 7400 v2.8 (G4) */
5518 POWERPC_DEF("7400v2.8", CPU_POWERPC_7400_v28, 0xFFFFFFFF, 7400),
5519 /* PowerPC 7400 v2.9 (G4) */
5520 POWERPC_DEF("7400v2.9", CPU_POWERPC_7400_v29, 0xFFFFFFFF, 7400),
5521 /* PowerPC 7410 (G4) */
5522 POWERPC_DEF("7410", CPU_POWERPC_7410, 0xFFFFFFFF, 7410),
5523 /* Code name for PowerPC 7410 */
5524 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 0xFFFFFFFF, 7410),
5525 /* PowerPC 7410 v1.0 (G4) */
5526 POWERPC_DEF("7410v1.0", CPU_POWERPC_7410_v10, 0xFFFFFFFF, 7410),
5527 /* PowerPC 7410 v1.1 (G4) */
5528 POWERPC_DEF("7410v1.1", CPU_POWERPC_7410_v11, 0xFFFFFFFF, 7410),
5529 /* PowerPC 7410 v1.2 (G4) */
5530 POWERPC_DEF("7410v1.2", CPU_POWERPC_7410_v12, 0xFFFFFFFF, 7410),
5531 /* PowerPC 7410 v1.3 (G4) */
5532 POWERPC_DEF("7410v1.3", CPU_POWERPC_7410_v13, 0xFFFFFFFF, 7410),
5533 /* PowerPC 7410 v1.4 (G4) */
5534 POWERPC_DEF("7410v1.4", CPU_POWERPC_7410_v14, 0xFFFFFFFF, 7410),
5535 /* PowerPC 7448 (G4) */
5536 POWERPC_DEF("7448", CPU_POWERPC_7448, 0xFFFFFFFF, 7400),
5537 /* PowerPC 7448 v1.0 (G4) */
5538 POWERPC_DEF("7448v1.0", CPU_POWERPC_7448_v10, 0xFFFFFFFF, 7400),
5539 /* PowerPC 7448 v1.1 (G4) */
5540 POWERPC_DEF("7448v1.1", CPU_POWERPC_7448_v11, 0xFFFFFFFF, 7400),
5541 /* PowerPC 7448 v2.0 (G4) */
5542 POWERPC_DEF("7448v2.0", CPU_POWERPC_7448_v20, 0xFFFFFFFF, 7400),
5543 /* PowerPC 7448 v2.1 (G4) */
5544 POWERPC_DEF("7448v2.1", CPU_POWERPC_7448_v21, 0xFFFFFFFF, 7400),
5545 #if defined (TODO)
5546 /* PowerPC 7450 (G4) */
5547 POWERPC_DEF("7450", CPU_POWERPC_7450, 0xFFFFFFFF, 7450),
5548 /* Code name for PowerPC 7450 */
5549 POWERPC_DEF("Vger", CPU_POWERPC_7450, 0xFFFFFFFF, 7450),
5550 #endif
5551 #if defined (TODO)
5552 /* PowerPC 7450 v1.0 (G4) */
5553 POWERPC_DEF("7450v1.0", CPU_POWERPC_7450_v10, 0xFFFFFFFF, 7450),
5554 #endif
5555 #if defined (TODO)
5556 /* PowerPC 7450 v1.1 (G4) */
5557 POWERPC_DEF("7450v1.1", CPU_POWERPC_7450_v11, 0xFFFFFFFF, 7450),
5558 #endif
5559 #if defined (TODO)
5560 /* PowerPC 7450 v1.2 (G4) */
5561 POWERPC_DEF("7450v1.2", CPU_POWERPC_7450_v12, 0xFFFFFFFF, 7450),
5562 #endif
5563 #if defined (TODO)
5564 /* PowerPC 7450 v2.0 (G4) */
5565 POWERPC_DEF("7450v2.0", CPU_POWERPC_7450_v20, 0xFFFFFFFF, 7450),
5566 #endif
5567 #if defined (TODO)
5568 /* PowerPC 7450 v2.1 (G4) */
5569 POWERPC_DEF("7450v2.1", CPU_POWERPC_7450_v21, 0xFFFFFFFF, 7450),
5570 #endif
5571 #if defined (TODO)
5572 /* PowerPC 7441 (G4) */
5573 POWERPC_DEF("7441", CPU_POWERPC_74x1, 0xFFFFFFFF, 7440),
5574 /* PowerPC 7451 (G4) */
5575 POWERPC_DEF("7451", CPU_POWERPC_74x1, 0xFFFFFFFF, 7450),
5576 #endif
5577 #if defined (TODO)
5578 /* PowerPC 7441g (G4) */
5579 POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7440),
5580 /* PowerPC 7451g (G4) */
5581 POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7450),
5582 #endif
5583 #if defined (TODO)
5584 /* PowerPC 7445 (G4) */
5585 POWERPC_DEF("7445", CPU_POWERPC_74x5, 0xFFFFFFFF, 7445),
5586 /* PowerPC 7455 (G4) */
5587 POWERPC_DEF("7455", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455),
5588 /* Code name for PowerPC 7445/7455 */
5589 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455),
5590 #endif
5591 #if defined (TODO)
5592 /* PowerPC 7445 v1.0 (G4) */
5593 POWERPC_DEF("7445v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7445),
5594 /* PowerPC 7455 v1.0 (G4) */
5595 POWERPC_DEF("7455v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7455),
5596 #endif
5597 #if defined (TODO)
5598 /* PowerPC 7445 v2.1 (G4) */
5599 POWERPC_DEF("7445v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7445),
5600 /* PowerPC 7455 v2.1 (G4) */
5601 POWERPC_DEF("7455v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7455),
5602 #endif
5603 #if defined (TODO)
5604 /* PowerPC 7445 v3.2 (G4) */
5605 POWERPC_DEF("7445v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7445),
5606 /* PowerPC 7455 v3.2 (G4) */
5607 POWERPC_DEF("7455v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7455),
5608 #endif
5609 #if defined (TODO)
5610 /* PowerPC 7445 v3.3 (G4) */
5611 POWERPC_DEF("7445v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7445),
5612 /* PowerPC 7455 v3.3 (G4) */
5613 POWERPC_DEF("7455v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7455),
5614 #endif
5615 #if defined (TODO)
5616 /* PowerPC 7445 v3.4 (G4) */
5617 POWERPC_DEF("7445v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7445),
5618 /* PowerPC 7455 v3.4 (G4) */
5619 POWERPC_DEF("7455v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7455),
5620 #endif
5621 #if defined (TODO)
5622 /* PowerPC 7447 (G4) */
5623 POWERPC_DEF("7447", CPU_POWERPC_74x7, 0xFFFFFFFF, 7445),
5624 /* PowerPC 7457 (G4) */
5625 POWERPC_DEF("7457", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455),
5626 /* Code name for PowerPC 7447/7457 */
5627 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455),
5628 #endif
5629 #if defined (TODO)
5630 /* PowerPC 7447 v1.0 (G4) */
5631 POWERPC_DEF("7447v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7445),
5632 /* PowerPC 7457 v1.0 (G4) */
5633 POWERPC_DEF("7457v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455),
5634 /* Code name for PowerPC 7447A/7457A */
5635 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455),
5636 #endif
5637 #if defined (TODO)
5638 /* PowerPC 7447 v1.1 (G4) */
5639 POWERPC_DEF("7447v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7445),
5640 /* PowerPC 7457 v1.1 (G4) */
5641 POWERPC_DEF("7457v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7455),
5642 #endif
5643 #if defined (TODO)
5644 /* PowerPC 7447 v1.2 (G4) */
5645 POWERPC_DEF("7447v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7445),
5646 /* PowerPC 7457 v1.2 (G4) */
5647 POWERPC_DEF("7457v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7455),
5648 #endif
5649 /* 64 bits PowerPC */
5650 #if defined (TARGET_PPC64)
5651 #if defined (TODO)
5652 /* PowerPC 620 */
5653 POWERPC_DEF("620", CPU_POWERPC_620, 0xFFFFFFFF, 620),
5654 #endif
5655 #if defined (TODO)
5656 /* PowerPC 630 (POWER3) */
5657 POWERPC_DEF("630", CPU_POWERPC_630, 0xFFFFFFFF, 630),
5658 POWERPC_DEF("POWER3", CPU_POWERPC_630, 0xFFFFFFFF, 630),
5659 #endif
5660 #if defined (TODO)
5661 /* PowerPC 631 (Power 3+) */
5662 POWERPC_DEF("631", CPU_POWERPC_631, 0xFFFFFFFF, 631),
5663 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 0xFFFFFFFF, 631),
5664 #endif
5665 #if defined (TODO)
5666 /* POWER4 */
5667 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, 0xFFFFFFFF, POWER4),
5668 #endif
5669 #if defined (TODO)
5670 /* POWER4p */
5671 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, 0xFFFFFFFF, POWER4P),
5672 #endif
5673 #if defined (TODO)
5674 /* POWER5 */
5675 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, 0xFFFFFFFF, POWER5),
5676 /* POWER5GR */
5677 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, 0xFFFFFFFF, POWER5),
5678 #endif
5679 #if defined (TODO)
5680 /* POWER5+ */
5681 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, 0xFFFFFFFF, POWER5P),
5682 /* POWER5GS */
5683 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, 0xFFFFFFFF, POWER5P),
5684 #endif
5685 #if defined (TODO)
5686 /* POWER6 */
5687 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, 0xFFFFFFFF, POWER6),
5688 /* POWER6 running in POWER5 mode */
5689 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, 0xFFFFFFFF, POWER5),
5690 /* POWER6A */
5691 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, 0xFFFFFFFF, POWER6),
5692 #endif
5693 /* PowerPC 970 */
5694 POWERPC_DEF("970", CPU_POWERPC_970, 0xFFFFFFFF, 970),
5695 /* PowerPC 970FX (G5) */
5696 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 0xFFFFFFFF, 970FX),
5697 /* PowerPC 970FX v1.0 (G5) */
5698 POWERPC_DEF("970fx1.0", CPU_POWERPC_970FX_v10, 0xFFFFFFFF, 970FX),
5699 /* PowerPC 970FX v2.0 (G5) */
5700 POWERPC_DEF("970fx2.0", CPU_POWERPC_970FX_v20, 0xFFFFFFFF, 970FX),
5701 /* PowerPC 970FX v2.1 (G5) */
5702 POWERPC_DEF("970fx2.1", CPU_POWERPC_970FX_v21, 0xFFFFFFFF, 970FX),
5703 /* PowerPC 970FX v3.0 (G5) */
5704 POWERPC_DEF("970fx3.0", CPU_POWERPC_970FX_v30, 0xFFFFFFFF, 970FX),
5705 /* PowerPC 970FX v3.1 (G5) */
5706 POWERPC_DEF("970fx3.1", CPU_POWERPC_970FX_v31, 0xFFFFFFFF, 970FX),
5707 /* PowerPC 970GX (G5) */
5708 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 0xFFFFFFFF, 970GX),
5709 /* PowerPC 970MP */
5710 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 0xFFFFFFFF, 970),
5711 /* PowerPC 970MP v1.0 */
5712 POWERPC_DEF("970mp1.0", CPU_POWERPC_970MP_v10, 0xFFFFFFFF, 970),
5713 /* PowerPC 970MP v1.1 */
5714 POWERPC_DEF("970mp1.1", CPU_POWERPC_970MP_v11, 0xFFFFFFFF, 970),
5715 #if defined (TODO)
5716 /* PowerPC Cell */
5717 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 0xFFFFFFFF, 970),
5718 #endif
5719 #if defined (TODO)
5720 /* PowerPC Cell v1.0 */
5721 POWERPC_DEF("Cell1.0", CPU_POWERPC_CELL_v10, 0xFFFFFFFF, 970),
5722 #endif
5723 #if defined (TODO)
5724 /* PowerPC Cell v2.0 */
5725 POWERPC_DEF("Cell2.0", CPU_POWERPC_CELL_v20, 0xFFFFFFFF, 970),
5726 #endif
5727 #if defined (TODO)
5728 /* PowerPC Cell v3.0 */
5729 POWERPC_DEF("Cell3.0", CPU_POWERPC_CELL_v30, 0xFFFFFFFF, 970),
5730 #endif
5731 #if defined (TODO)
5732 /* PowerPC Cell v3.1 */
5733 POWERPC_DEF("Cell3.1", CPU_POWERPC_CELL_v31, 0xFFFFFFFF, 970),
5734 #endif
5735 #if defined (TODO)
5736 /* PowerPC Cell v3.2 */
5737 POWERPC_DEF("Cell3.2", CPU_POWERPC_CELL_v32, 0xFFFFFFFF, 970),
5738 #endif
5739 #if defined (TODO)
5740 /* RS64 (Apache/A35) */
5741 /* This one seems to support the whole POWER2 instruction set
5742 * and the PowerPC 64 one.
5743 */
5744 /* What about A10 & A30 ? */
5745 POWERPC_DEF("RS64", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
5746 POWERPC_DEF("Apache", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
5747 POWERPC_DEF("A35", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
5748 #endif
5749 #if defined (TODO)
5750 /* RS64-II (NorthStar/A50) */
5751 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
5752 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
5753 POWERPC_DEF("A50", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
5754 #endif
5755 #if defined (TODO)
5756 /* RS64-III (Pulsar) */
5757 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64),
5758 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64),
5759 #endif
5760 #if defined (TODO)
5761 /* RS64-IV (IceStar/IStar/SStar) */
5762 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5763 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5764 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5765 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5766 #endif
5767 #endif /* defined (TARGET_PPC64) */
5768 /* POWER */
5769 #if defined (TODO)
5770 /* Original POWER */
5771 POWERPC_DEF("POWER", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5772 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5773 POWERPC_DEF("RSC", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5774 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5775 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5776 #endif
5777 #if defined (TODO)
5778 /* POWER2 */
5779 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5780 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5781 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5782 #endif
5783 /* PA semi cores */
5784 #if defined (TODO)
5785 /* PA PA6T */
5786 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, 0xFFFFFFFF, PA6T),
5787 #endif
5788 /* Generic PowerPCs */
5789 #if defined (TARGET_PPC64)
5790 #if defined (TODO)
5791 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, 0xFFFFFFFF, PPC64),
5792 #endif
5793 #endif
5794 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, 0xFFFFFFFF, PPC32),
5795 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, 0xFFFFFFFF, DEFAULT),
5796 /* Fallback */
5797 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, 0xFFFFFFFF, DEFAULT),
5798 };
5799
5800 /*****************************************************************************/
5801 /* Generic CPU instanciation routine */
5802 static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
5803 {
5804 #if !defined(CONFIG_USER_ONLY)
5805 int i;
5806
5807 env->irq_inputs = NULL;
5808 /* Set all exception vectors to an invalid address */
5809 for (i = 0; i < POWERPC_EXCP_NB; i++)
5810 env->excp_vectors[i] = (target_ulong)(-1ULL);
5811 env->excp_prefix = 0x00000000;
5812 env->ivor_mask = 0x00000000;
5813 env->ivpr_mask = 0x00000000;
5814 /* Default MMU definitions */
5815 env->nb_BATs = 0;
5816 env->nb_tlb = 0;
5817 env->nb_ways = 0;
5818 #endif
5819 /* Register SPR common to all PowerPC implementations */
5820 gen_spr_generic(env);
5821 spr_register(env, SPR_PVR, "PVR",
5822 SPR_NOACCESS, SPR_NOACCESS,
5823 &spr_read_generic, SPR_NOACCESS,
5824 def->pvr);
5825 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
5826 (*def->init_proc)(env);
5827 /* MSR bits & flags consistency checks */
5828 if (env->msr_mask & (1 << 25)) {
5829 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
5830 case POWERPC_FLAG_SPE:
5831 case POWERPC_FLAG_VRE:
5832 break;
5833 default:
5834 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5835 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
5836 exit(1);
5837 }
5838 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
5839 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5840 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
5841 exit(1);
5842 }
5843 if (env->msr_mask & (1 << 17)) {
5844 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
5845 case POWERPC_FLAG_TGPR:
5846 case POWERPC_FLAG_CE:
5847 break;
5848 default:
5849 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5850 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
5851 exit(1);
5852 }
5853 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
5854 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5855 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
5856 exit(1);
5857 }
5858 if (env->msr_mask & (1 << 10)) {
5859 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
5860 POWERPC_FLAG_UBLE)) {
5861 case POWERPC_FLAG_SE:
5862 case POWERPC_FLAG_DWE:
5863 case POWERPC_FLAG_UBLE:
5864 break;
5865 default:
5866 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5867 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
5868 "POWERPC_FLAG_UBLE\n");
5869 exit(1);
5870 }
5871 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
5872 POWERPC_FLAG_UBLE)) {
5873 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5874 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
5875 "POWERPC_FLAG_UBLE\n");
5876 exit(1);
5877 }
5878 if (env->msr_mask & (1 << 9)) {
5879 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
5880 case POWERPC_FLAG_BE:
5881 case POWERPC_FLAG_DE:
5882 break;
5883 default:
5884 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5885 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
5886 exit(1);
5887 }
5888 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
5889 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5890 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
5891 exit(1);
5892 }
5893 if (env->msr_mask & (1 << 2)) {
5894 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
5895 case POWERPC_FLAG_PX:
5896 case POWERPC_FLAG_PMM:
5897 break;
5898 default:
5899 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5900 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
5901 exit(1);
5902 }
5903 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
5904 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5905 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
5906 exit(1);
5907 }
5908 /* Allocate TLBs buffer when needed */
5909 #if !defined(CONFIG_USER_ONLY)
5910 if (env->nb_tlb != 0) {
5911 int nb_tlb = env->nb_tlb;
5912 if (env->id_tlbs != 0)
5913 nb_tlb *= 2;
5914 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
5915 /* Pre-compute some useful values */
5916 env->tlb_per_way = env->nb_tlb / env->nb_ways;
5917 }
5918 if (env->irq_inputs == NULL) {
5919 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
5920 " Attempt Qemu to crash very soon !\n");
5921 }
5922 #endif
5923 }
5924
5925 #if defined(PPC_DUMP_CPU)
5926 static void dump_ppc_sprs (CPUPPCState *env)
5927 {
5928 ppc_spr_t *spr;
5929 #if !defined(CONFIG_USER_ONLY)
5930 uint32_t sr, sw;
5931 #endif
5932 uint32_t ur, uw;
5933 int i, j, n;
5934
5935 printf("Special purpose registers:\n");
5936 for (i = 0; i < 32; i++) {
5937 for (j = 0; j < 32; j++) {
5938 n = (i << 5) | j;
5939 spr = &env->spr_cb[n];
5940 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
5941 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
5942 #if !defined(CONFIG_USER_ONLY)
5943 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
5944 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
5945 if (sw || sr || uw || ur) {
5946 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
5947 (i << 5) | j, (i << 5) | j, spr->name,
5948 sw ? 'w' : '-', sr ? 'r' : '-',
5949 uw ? 'w' : '-', ur ? 'r' : '-');
5950 }
5951 #else
5952 if (uw || ur) {
5953 printf("SPR: %4d (%03x) %-8s u%c%c\n",
5954 (i << 5) | j, (i << 5) | j, spr->name,
5955 uw ? 'w' : '-', ur ? 'r' : '-');
5956 }
5957 #endif
5958 }
5959 }
5960 fflush(stdout);
5961 fflush(stderr);
5962 }
5963 #endif
5964
5965 /*****************************************************************************/
5966 #include <stdlib.h>
5967 #include <string.h>
5968
5969 int fflush (FILE *stream);
5970
5971 /* Opcode types */
5972 enum {
5973 PPC_DIRECT = 0, /* Opcode routine */
5974 PPC_INDIRECT = 1, /* Indirect opcode table */
5975 };
5976
5977 static inline int is_indirect_opcode (void *handler)
5978 {
5979 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
5980 }
5981
5982 static inline opc_handler_t **ind_table(void *handler)
5983 {
5984 return (opc_handler_t **)((unsigned long)handler & ~3);
5985 }
5986
5987 /* Instruction table creation */
5988 /* Opcodes tables creation */
5989 static void fill_new_table (opc_handler_t **table, int len)
5990 {
5991 int i;
5992
5993 for (i = 0; i < len; i++)
5994 table[i] = &invalid_handler;
5995 }
5996
5997 static int create_new_table (opc_handler_t **table, unsigned char idx)
5998 {
5999 opc_handler_t **tmp;
6000
6001 tmp = malloc(0x20 * sizeof(opc_handler_t));
6002 if (tmp == NULL)
6003 return -1;
6004 fill_new_table(tmp, 0x20);
6005 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
6006
6007 return 0;
6008 }
6009
6010 static int insert_in_table (opc_handler_t **table, unsigned char idx,
6011 opc_handler_t *handler)
6012 {
6013 if (table[idx] != &invalid_handler)
6014 return -1;
6015 table[idx] = handler;
6016
6017 return 0;
6018 }
6019
6020 static int register_direct_insn (opc_handler_t **ppc_opcodes,
6021 unsigned char idx, opc_handler_t *handler)
6022 {
6023 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
6024 printf("*** ERROR: opcode %02x already assigned in main "
6025 "opcode table\n", idx);
6026 return -1;
6027 }
6028
6029 return 0;
6030 }
6031
6032 static int register_ind_in_table (opc_handler_t **table,
6033 unsigned char idx1, unsigned char idx2,
6034 opc_handler_t *handler)
6035 {
6036 if (table[idx1] == &invalid_handler) {
6037 if (create_new_table(table, idx1) < 0) {
6038 printf("*** ERROR: unable to create indirect table "
6039 "idx=%02x\n", idx1);
6040 return -1;
6041 }
6042 } else {
6043 if (!is_indirect_opcode(table[idx1])) {
6044 printf("*** ERROR: idx %02x already assigned to a direct "
6045 "opcode\n", idx1);
6046 return -1;
6047 }
6048 }
6049 if (handler != NULL &&
6050 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
6051 printf("*** ERROR: opcode %02x already assigned in "
6052 "opcode table %02x\n", idx2, idx1);
6053 return -1;
6054 }
6055
6056 return 0;
6057 }
6058
6059 static int register_ind_insn (opc_handler_t **ppc_opcodes,
6060 unsigned char idx1, unsigned char idx2,
6061 opc_handler_t *handler)
6062 {
6063 int ret;
6064
6065 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
6066
6067 return ret;
6068 }
6069
6070 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
6071 unsigned char idx1, unsigned char idx2,
6072 unsigned char idx3, opc_handler_t *handler)
6073 {
6074 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
6075 printf("*** ERROR: unable to join indirect table idx "
6076 "[%02x-%02x]\n", idx1, idx2);
6077 return -1;
6078 }
6079 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
6080 handler) < 0) {
6081 printf("*** ERROR: unable to insert opcode "
6082 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
6083 return -1;
6084 }
6085
6086 return 0;
6087 }
6088
6089 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
6090 {
6091 if (insn->opc2 != 0xFF) {
6092 if (insn->opc3 != 0xFF) {
6093 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
6094 insn->opc3, &insn->handler) < 0)
6095 return -1;
6096 } else {
6097 if (register_ind_insn(ppc_opcodes, insn->opc1,
6098 insn->opc2, &insn->handler) < 0)
6099 return -1;
6100 }
6101 } else {
6102 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
6103 return -1;
6104 }
6105
6106 return 0;
6107 }
6108
6109 static int test_opcode_table (opc_handler_t **table, int len)
6110 {
6111 int i, count, tmp;
6112
6113 for (i = 0, count = 0; i < len; i++) {
6114 /* Consistency fixup */
6115 if (table[i] == NULL)
6116 table[i] = &invalid_handler;
6117 if (table[i] != &invalid_handler) {
6118 if (is_indirect_opcode(table[i])) {
6119 tmp = test_opcode_table(ind_table(table[i]), 0x20);
6120 if (tmp == 0) {
6121 free(table[i]);
6122 table[i] = &invalid_handler;
6123 } else {
6124 count++;
6125 }
6126 } else {
6127 count++;
6128 }
6129 }
6130 }
6131
6132 return count;
6133 }
6134
6135 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
6136 {
6137 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
6138 printf("*** WARNING: no opcode defined !\n");
6139 }
6140
6141 /*****************************************************************************/
6142 static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def)
6143 {
6144 opcode_t *opc, *start, *end;
6145
6146 fill_new_table(env->opcodes, 0x40);
6147 if (&opc_start < &opc_end) {
6148 start = &opc_start;
6149 end = &opc_end;
6150 } else {
6151 start = &opc_end;
6152 end = &opc_start;
6153 }
6154 for (opc = start + 1; opc != end; opc++) {
6155 if ((opc->handler.type & def->insns_flags) != 0) {
6156 if (register_insn(env->opcodes, opc) < 0) {
6157 printf("*** ERROR initializing PowerPC instruction "
6158 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
6159 opc->opc3);
6160 return -1;
6161 }
6162 }
6163 }
6164 fix_opcode_tables(env->opcodes);
6165 fflush(stdout);
6166 fflush(stderr);
6167
6168 return 0;
6169 }
6170
6171 #if defined(PPC_DUMP_CPU)
6172 static void dump_ppc_insns (CPUPPCState *env)
6173 {
6174 opc_handler_t **table, *handler;
6175 uint8_t opc1, opc2, opc3;
6176
6177 printf("Instructions set:\n");
6178 /* opc1 is 6 bits long */
6179 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
6180 table = env->opcodes;
6181 handler = table[opc1];
6182 if (is_indirect_opcode(handler)) {
6183 /* opc2 is 5 bits long */
6184 for (opc2 = 0; opc2 < 0x20; opc2++) {
6185 table = env->opcodes;
6186 handler = env->opcodes[opc1];
6187 table = ind_table(handler);
6188 handler = table[opc2];
6189 if (is_indirect_opcode(handler)) {
6190 table = ind_table(handler);
6191 /* opc3 is 5 bits long */
6192 for (opc3 = 0; opc3 < 0x20; opc3++) {
6193 handler = table[opc3];
6194 if (handler->handler != &gen_invalid) {
6195 printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
6196 opc1, opc2, opc3, opc1, (opc3 << 5) | opc2,
6197 handler->oname);
6198 }
6199 }
6200 } else {
6201 if (handler->handler != &gen_invalid) {
6202 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
6203 opc1, opc2, opc1, opc2, handler->oname);
6204 }
6205 }
6206 }
6207 } else {
6208 if (handler->handler != &gen_invalid) {
6209 printf("INSN: %02x -- -- (%02d ----) : %s\n",
6210 opc1, opc1, handler->oname);
6211 }
6212 }
6213 }
6214 }
6215 #endif
6216
6217 int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
6218 {
6219 env->msr_mask = def->msr_mask;
6220 env->mmu_model = def->mmu_model;
6221 env->excp_model = def->excp_model;
6222 env->bus_model = def->bus_model;
6223 env->flags = def->flags;
6224 env->bfd_mach = def->bfd_mach;
6225 if (create_ppc_opcodes(env, def) < 0)
6226 return -1;
6227 init_ppc_proc(env, def);
6228 #if defined(PPC_DUMP_CPU)
6229 {
6230 const unsigned char *mmu_model, *excp_model, *bus_model;
6231 switch (env->mmu_model) {
6232 case POWERPC_MMU_32B:
6233 mmu_model = "PowerPC 32";
6234 break;
6235 case POWERPC_MMU_601:
6236 mmu_model = "PowerPC 601";
6237 break;
6238 case POWERPC_MMU_SOFT_6xx:
6239 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
6240 break;
6241 case POWERPC_MMU_SOFT_74xx:
6242 mmu_model = "PowerPC 74xx with software driven TLBs";
6243 break;
6244 case POWERPC_MMU_SOFT_4xx:
6245 mmu_model = "PowerPC 4xx with software driven TLBs";
6246 break;
6247 case POWERPC_MMU_SOFT_4xx_Z:
6248 mmu_model = "PowerPC 4xx with software driven TLBs "
6249 "and zones protections";
6250 break;
6251 case POWERPC_MMU_REAL_4xx:
6252 mmu_model = "PowerPC 4xx real mode only";
6253 break;
6254 case POWERPC_MMU_BOOKE:
6255 mmu_model = "PowerPC BookE";
6256 break;
6257 case POWERPC_MMU_BOOKE_FSL:
6258 mmu_model = "PowerPC BookE FSL";
6259 break;
6260 #if defined (TARGET_PPC64)
6261 case POWERPC_MMU_64B:
6262 mmu_model = "PowerPC 64";
6263 break;
6264 #endif
6265 default:
6266 mmu_model = "Unknown or invalid";
6267 break;
6268 }
6269 switch (env->excp_model) {
6270 case POWERPC_EXCP_STD:
6271 excp_model = "PowerPC";
6272 break;
6273 case POWERPC_EXCP_40x:
6274 excp_model = "PowerPC 40x";
6275 break;
6276 case POWERPC_EXCP_601:
6277 excp_model = "PowerPC 601";
6278 break;
6279 case POWERPC_EXCP_602:
6280 excp_model = "PowerPC 602";
6281 break;
6282 case POWERPC_EXCP_603:
6283 excp_model = "PowerPC 603";
6284 break;
6285 case POWERPC_EXCP_603E:
6286 excp_model = "PowerPC 603e";
6287 break;
6288 case POWERPC_EXCP_604:
6289 excp_model = "PowerPC 604";
6290 break;
6291 case POWERPC_EXCP_7x0:
6292 excp_model = "PowerPC 740/750";
6293 break;
6294 case POWERPC_EXCP_7x5:
6295 excp_model = "PowerPC 745/755";
6296 break;
6297 case POWERPC_EXCP_74xx:
6298 excp_model = "PowerPC 74xx";
6299 break;
6300 case POWERPC_EXCP_BOOKE:
6301 excp_model = "PowerPC BookE";
6302 break;
6303 #if defined (TARGET_PPC64)
6304 case POWERPC_EXCP_970:
6305 excp_model = "PowerPC 970";
6306 break;
6307 #endif
6308 default:
6309 excp_model = "Unknown or invalid";
6310 break;
6311 }
6312 switch (env->bus_model) {
6313 case PPC_FLAGS_INPUT_6xx:
6314 bus_model = "PowerPC 6xx";
6315 break;
6316 case PPC_FLAGS_INPUT_BookE:
6317 bus_model = "PowerPC BookE";
6318 break;
6319 case PPC_FLAGS_INPUT_405:
6320 bus_model = "PowerPC 405";
6321 break;
6322 case PPC_FLAGS_INPUT_401:
6323 bus_model = "PowerPC 401/403";
6324 break;
6325 #if defined (TARGET_PPC64)
6326 case PPC_FLAGS_INPUT_970:
6327 bus_model = "PowerPC 970";
6328 break;
6329 #endif
6330 default:
6331 bus_model = "Unknown or invalid";
6332 break;
6333 }
6334 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
6335 " MMU model : %s\n",
6336 def->name, def->pvr, def->msr_mask, mmu_model);
6337 #if !defined(CONFIG_USER_ONLY)
6338 if (env->tlb != NULL) {
6339 printf(" %d %s TLB in %d ways\n",
6340 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
6341 env->nb_ways);
6342 }
6343 #endif
6344 printf(" Exceptions model : %s\n"
6345 " Bus model : %s\n",
6346 excp_model, bus_model);
6347 printf(" MSR features :\n");
6348 if (env->flags & POWERPC_FLAG_SPE)
6349 printf(" signal processing engine enable"
6350 "\n");
6351 else if (env->flags & POWERPC_FLAG_VRE)
6352 printf(" vector processor enable\n");
6353 if (env->flags & POWERPC_FLAG_TGPR)
6354 printf(" temporary GPRs\n");
6355 else if (env->flags & POWERPC_FLAG_CE)
6356 printf(" critical input enable\n");
6357 if (env->flags & POWERPC_FLAG_SE)
6358 printf(" single-step trace mode\n");
6359 else if (env->flags & POWERPC_FLAG_DWE)
6360 printf(" debug wait enable\n");
6361 else if (env->flags & POWERPC_FLAG_UBLE)
6362 printf(" user BTB lock enable\n");
6363 if (env->flags & POWERPC_FLAG_BE)
6364 printf(" branch-step trace mode\n");
6365 else if (env->flags & POWERPC_FLAG_DE)
6366 printf(" debug interrupt enable\n");
6367 if (env->flags & POWERPC_FLAG_PX)
6368 printf(" inclusive protection\n");
6369 else if (env->flags & POWERPC_FLAG_PMM)
6370 printf(" performance monitor mark\n");
6371 if (env->flags == POWERPC_FLAG_NONE)
6372 printf(" none\n");
6373 }
6374 dump_ppc_insns(env);
6375 dump_ppc_sprs(env);
6376 fflush(stdout);
6377 #endif
6378
6379 return 0;
6380 }
6381
6382 int ppc_find_by_name (const unsigned char *name, ppc_def_t **def)
6383 {
6384 int i, max, ret;
6385
6386 ret = -1;
6387 *def = NULL;
6388 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6389 for (i = 0; i < max; i++) {
6390 if (strcasecmp(name, ppc_defs[i].name) == 0) {
6391 *def = &ppc_defs[i];
6392 ret = 0;
6393 break;
6394 }
6395 }
6396
6397 return ret;
6398 }
6399
6400 int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
6401 {
6402 int i, max, ret;
6403
6404 ret = -1;
6405 *def = NULL;
6406 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6407 for (i = 0; i < max; i++) {
6408 if ((pvr & ppc_defs[i].pvr_mask) ==
6409 (ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) {
6410 *def = &ppc_defs[i];
6411 ret = 0;
6412 break;
6413 }
6414 }
6415
6416 return ret;
6417 }
6418
6419 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
6420 {
6421 int i, max;
6422
6423 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6424 for (i = 0; i < max; i++) {
6425 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
6426 ppc_defs[i].name, ppc_defs[i].pvr);
6427 }
6428 }
Qemu copy for testing