2 * PowerPC CPU initialization for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 /* A lot of PowerPC definition have been included here.
21 * Most of them are not usable for now but have been kept
22 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
30 //#define PPC_DUMP_CPU
31 //#define PPC_DEBUG_SPR
32 //#define PPC_DUMP_SPR_ACCESSES
33 #if defined(CONFIG_USER_ONLY)
34 #define TODO_USER_ONLY 1
42 uint64_t insns_flags2
;
44 powerpc_mmu_t mmu_model
;
45 powerpc_excp_t excp_model
;
46 powerpc_input_t bus_model
;
49 void (*init_proc
)(CPUPPCState
*env
);
50 int (*check_pow
)(CPUPPCState
*env
);
53 /* For user-mode emulation, we don't emulate any IRQ controller */
54 #if defined(CONFIG_USER_ONLY)
55 #define PPC_IRQ_INIT_FN(name) \
56 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
60 #define PPC_IRQ_INIT_FN(name) \
61 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
67 PPC_IRQ_INIT_FN(POWER7
);
68 PPC_IRQ_INIT_FN(e500
);
71 * do nothing but store/retrieve spr value
73 static void spr_read_generic (void *opaque
, int gprn
, int sprn
)
75 gen_load_spr(cpu_gpr
[gprn
], sprn
);
76 #ifdef PPC_DUMP_SPR_ACCESSES
78 TCGv_i32 t0
= tcg_const_i32(sprn
);
79 gen_helper_load_dump_spr(t0
);
80 tcg_temp_free_i32(t0
);
85 static void spr_write_generic (void *opaque
, int sprn
, int gprn
)
87 gen_store_spr(sprn
, cpu_gpr
[gprn
]);
88 #ifdef PPC_DUMP_SPR_ACCESSES
90 TCGv_i32 t0
= tcg_const_i32(sprn
);
91 gen_helper_store_dump_spr(t0
);
92 tcg_temp_free_i32(t0
);
97 #if !defined(CONFIG_USER_ONLY)
98 static void spr_write_clear (void *opaque
, int sprn
, int gprn
)
100 TCGv t0
= tcg_temp_new();
101 TCGv t1
= tcg_temp_new();
102 gen_load_spr(t0
, sprn
);
103 tcg_gen_neg_tl(t1
, cpu_gpr
[gprn
]);
104 tcg_gen_and_tl(t0
, t0
, t1
);
105 gen_store_spr(sprn
, t0
);
111 /* SPR common to all PowerPC */
113 static void spr_read_xer (void *opaque
, int gprn
, int sprn
)
115 tcg_gen_mov_tl(cpu_gpr
[gprn
], cpu_xer
);
118 static void spr_write_xer (void *opaque
, int sprn
, int gprn
)
120 tcg_gen_mov_tl(cpu_xer
, cpu_gpr
[gprn
]);
124 static void spr_read_lr (void *opaque
, int gprn
, int sprn
)
126 tcg_gen_mov_tl(cpu_gpr
[gprn
], cpu_lr
);
129 static void spr_write_lr (void *opaque
, int sprn
, int gprn
)
131 tcg_gen_mov_tl(cpu_lr
, cpu_gpr
[gprn
]);
135 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
136 static void spr_read_cfar (void *opaque
, int gprn
, int sprn
)
138 tcg_gen_mov_tl(cpu_gpr
[gprn
], cpu_cfar
);
141 static void spr_write_cfar (void *opaque
, int sprn
, int gprn
)
143 tcg_gen_mov_tl(cpu_cfar
, cpu_gpr
[gprn
]);
145 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
148 static void spr_read_ctr (void *opaque
, int gprn
, int sprn
)
150 tcg_gen_mov_tl(cpu_gpr
[gprn
], cpu_ctr
);
153 static void spr_write_ctr (void *opaque
, int sprn
, int gprn
)
155 tcg_gen_mov_tl(cpu_ctr
, cpu_gpr
[gprn
]);
158 /* User read access to SPR */
164 static void spr_read_ureg (void *opaque
, int gprn
, int sprn
)
166 gen_load_spr(cpu_gpr
[gprn
], sprn
+ 0x10);
169 /* SPR common to all non-embedded PowerPC */
171 #if !defined(CONFIG_USER_ONLY)
172 static void spr_read_decr (void *opaque
, int gprn
, int sprn
)
177 gen_helper_load_decr(cpu_gpr
[gprn
]);
180 gen_stop_exception(opaque
);
184 static void spr_write_decr (void *opaque
, int sprn
, int gprn
)
189 gen_helper_store_decr(cpu_gpr
[gprn
]);
192 gen_stop_exception(opaque
);
197 /* SPR common to all non-embedded PowerPC, except 601 */
199 static void spr_read_tbl (void *opaque
, int gprn
, int sprn
)
204 gen_helper_load_tbl(cpu_gpr
[gprn
]);
207 gen_stop_exception(opaque
);
211 static void spr_read_tbu (void *opaque
, int gprn
, int sprn
)
216 gen_helper_load_tbu(cpu_gpr
[gprn
]);
219 gen_stop_exception(opaque
);
223 __attribute__ (( unused
))
224 static void spr_read_atbl (void *opaque
, int gprn
, int sprn
)
226 gen_helper_load_atbl(cpu_gpr
[gprn
]);
229 __attribute__ (( unused
))
230 static void spr_read_atbu (void *opaque
, int gprn
, int sprn
)
232 gen_helper_load_atbu(cpu_gpr
[gprn
]);
235 #if !defined(CONFIG_USER_ONLY)
236 static void spr_write_tbl (void *opaque
, int sprn
, int gprn
)
241 gen_helper_store_tbl(cpu_gpr
[gprn
]);
244 gen_stop_exception(opaque
);
248 static void spr_write_tbu (void *opaque
, int sprn
, int gprn
)
253 gen_helper_store_tbu(cpu_gpr
[gprn
]);
256 gen_stop_exception(opaque
);
260 __attribute__ (( unused
))
261 static void spr_write_atbl (void *opaque
, int sprn
, int gprn
)
263 gen_helper_store_atbl(cpu_gpr
[gprn
]);
266 __attribute__ (( unused
))
267 static void spr_write_atbu (void *opaque
, int sprn
, int gprn
)
269 gen_helper_store_atbu(cpu_gpr
[gprn
]);
272 #if defined(TARGET_PPC64)
273 __attribute__ (( unused
))
274 static void spr_read_purr (void *opaque
, int gprn
, int sprn
)
276 gen_helper_load_purr(cpu_gpr
[gprn
]);
281 #if !defined(CONFIG_USER_ONLY)
282 /* IBAT0U...IBAT0U */
283 /* IBAT0L...IBAT7L */
284 static void spr_read_ibat (void *opaque
, int gprn
, int sprn
)
286 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUState
, IBAT
[sprn
& 1][(sprn
- SPR_IBAT0U
) / 2]));
289 static void spr_read_ibat_h (void *opaque
, int gprn
, int sprn
)
291 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUState
, IBAT
[sprn
& 1][(sprn
- SPR_IBAT4U
) / 2]));
294 static void spr_write_ibatu (void *opaque
, int sprn
, int gprn
)
296 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_IBAT0U
) / 2);
297 gen_helper_store_ibatu(t0
, cpu_gpr
[gprn
]);
298 tcg_temp_free_i32(t0
);
301 static void spr_write_ibatu_h (void *opaque
, int sprn
, int gprn
)
303 TCGv_i32 t0
= tcg_const_i32(((sprn
- SPR_IBAT4U
) / 2) + 4);
304 gen_helper_store_ibatu(t0
, cpu_gpr
[gprn
]);
305 tcg_temp_free_i32(t0
);
308 static void spr_write_ibatl (void *opaque
, int sprn
, int gprn
)
310 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_IBAT0L
) / 2);
311 gen_helper_store_ibatl(t0
, cpu_gpr
[gprn
]);
312 tcg_temp_free_i32(t0
);
315 static void spr_write_ibatl_h (void *opaque
, int sprn
, int gprn
)
317 TCGv_i32 t0
= tcg_const_i32(((sprn
- SPR_IBAT4L
) / 2) + 4);
318 gen_helper_store_ibatl(t0
, cpu_gpr
[gprn
]);
319 tcg_temp_free_i32(t0
);
322 /* DBAT0U...DBAT7U */
323 /* DBAT0L...DBAT7L */
324 static void spr_read_dbat (void *opaque
, int gprn
, int sprn
)
326 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUState
, DBAT
[sprn
& 1][(sprn
- SPR_DBAT0U
) / 2]));
329 static void spr_read_dbat_h (void *opaque
, int gprn
, int sprn
)
331 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUState
, DBAT
[sprn
& 1][((sprn
- SPR_DBAT4U
) / 2) + 4]));
334 static void spr_write_dbatu (void *opaque
, int sprn
, int gprn
)
336 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_DBAT0U
) / 2);
337 gen_helper_store_dbatu(t0
, cpu_gpr
[gprn
]);
338 tcg_temp_free_i32(t0
);
341 static void spr_write_dbatu_h (void *opaque
, int sprn
, int gprn
)
343 TCGv_i32 t0
= tcg_const_i32(((sprn
- SPR_DBAT4U
) / 2) + 4);
344 gen_helper_store_dbatu(t0
, cpu_gpr
[gprn
]);
345 tcg_temp_free_i32(t0
);
348 static void spr_write_dbatl (void *opaque
, int sprn
, int gprn
)
350 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_DBAT0L
) / 2);
351 gen_helper_store_dbatl(t0
, cpu_gpr
[gprn
]);
352 tcg_temp_free_i32(t0
);
355 static void spr_write_dbatl_h (void *opaque
, int sprn
, int gprn
)
357 TCGv_i32 t0
= tcg_const_i32(((sprn
- SPR_DBAT4L
) / 2) + 4);
358 gen_helper_store_dbatl(t0
, cpu_gpr
[gprn
]);
359 tcg_temp_free_i32(t0
);
363 static void spr_write_sdr1 (void *opaque
, int sprn
, int gprn
)
365 gen_helper_store_sdr1(cpu_gpr
[gprn
]);
368 /* 64 bits PowerPC specific SPRs */
370 #if defined(TARGET_PPC64)
371 static void spr_read_hior (void *opaque
, int gprn
, int sprn
)
373 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUState
, excp_prefix
));
376 static void spr_write_hior (void *opaque
, int sprn
, int gprn
)
378 TCGv t0
= tcg_temp_new();
379 tcg_gen_andi_tl(t0
, cpu_gpr
[gprn
], 0x3FFFFF00000ULL
);
380 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, excp_prefix
));
384 static void spr_read_asr (void *opaque
, int gprn
, int sprn
)
386 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUState
, asr
));
389 static void spr_write_asr (void *opaque
, int sprn
, int gprn
)
391 gen_helper_store_asr(cpu_gpr
[gprn
]);
396 /* PowerPC 601 specific registers */
398 static void spr_read_601_rtcl (void *opaque
, int gprn
, int sprn
)
400 gen_helper_load_601_rtcl(cpu_gpr
[gprn
]);
403 static void spr_read_601_rtcu (void *opaque
, int gprn
, int sprn
)
405 gen_helper_load_601_rtcu(cpu_gpr
[gprn
]);
408 #if !defined(CONFIG_USER_ONLY)
409 static void spr_write_601_rtcu (void *opaque
, int sprn
, int gprn
)
411 gen_helper_store_601_rtcu(cpu_gpr
[gprn
]);
414 static void spr_write_601_rtcl (void *opaque
, int sprn
, int gprn
)
416 gen_helper_store_601_rtcl(cpu_gpr
[gprn
]);
419 static void spr_write_hid0_601 (void *opaque
, int sprn
, int gprn
)
421 DisasContext
*ctx
= opaque
;
423 gen_helper_store_hid0_601(cpu_gpr
[gprn
]);
424 /* Must stop the translation as endianness may have changed */
425 gen_stop_exception(ctx
);
430 #if !defined(CONFIG_USER_ONLY)
431 static void spr_read_601_ubat (void *opaque
, int gprn
, int sprn
)
433 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUState
, IBAT
[sprn
& 1][(sprn
- SPR_IBAT0U
) / 2]));
436 static void spr_write_601_ubatu (void *opaque
, int sprn
, int gprn
)
438 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_IBAT0U
) / 2);
439 gen_helper_store_601_batl(t0
, cpu_gpr
[gprn
]);
440 tcg_temp_free_i32(t0
);
443 static void spr_write_601_ubatl (void *opaque
, int sprn
, int gprn
)
445 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_IBAT0U
) / 2);
446 gen_helper_store_601_batu(t0
, cpu_gpr
[gprn
]);
447 tcg_temp_free_i32(t0
);
451 /* PowerPC 40x specific registers */
452 #if !defined(CONFIG_USER_ONLY)
453 static void spr_read_40x_pit (void *opaque
, int gprn
, int sprn
)
455 gen_helper_load_40x_pit(cpu_gpr
[gprn
]);
458 static void spr_write_40x_pit (void *opaque
, int sprn
, int gprn
)
460 gen_helper_store_40x_pit(cpu_gpr
[gprn
]);
463 static void spr_write_40x_dbcr0 (void *opaque
, int sprn
, int gprn
)
465 DisasContext
*ctx
= opaque
;
467 gen_helper_store_40x_dbcr0(cpu_gpr
[gprn
]);
468 /* We must stop translation as we may have rebooted */
469 gen_stop_exception(ctx
);
472 static void spr_write_40x_sler (void *opaque
, int sprn
, int gprn
)
474 gen_helper_store_40x_sler(cpu_gpr
[gprn
]);
477 static void spr_write_booke_tcr (void *opaque
, int sprn
, int gprn
)
479 gen_helper_store_booke_tcr(cpu_gpr
[gprn
]);
482 static void spr_write_booke_tsr (void *opaque
, int sprn
, int gprn
)
484 gen_helper_store_booke_tsr(cpu_gpr
[gprn
]);
488 /* PowerPC 403 specific registers */
489 /* PBL1 / PBU1 / PBL2 / PBU2 */
490 #if !defined(CONFIG_USER_ONLY)
491 static void spr_read_403_pbr (void *opaque
, int gprn
, int sprn
)
493 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUState
, pb
[sprn
- SPR_403_PBL1
]));
496 static void spr_write_403_pbr (void *opaque
, int sprn
, int gprn
)
498 TCGv_i32 t0
= tcg_const_i32(sprn
- SPR_403_PBL1
);
499 gen_helper_store_403_pbr(t0
, cpu_gpr
[gprn
]);
500 tcg_temp_free_i32(t0
);
503 static void spr_write_pir (void *opaque
, int sprn
, int gprn
)
505 TCGv t0
= tcg_temp_new();
506 tcg_gen_andi_tl(t0
, cpu_gpr
[gprn
], 0xF);
507 gen_store_spr(SPR_PIR
, t0
);
512 /* SPE specific registers */
513 static void spr_read_spefscr (void *opaque
, int gprn
, int sprn
)
515 TCGv_i32 t0
= tcg_temp_new_i32();
516 tcg_gen_ld_i32(t0
, cpu_env
, offsetof(CPUState
, spe_fscr
));
517 tcg_gen_extu_i32_tl(cpu_gpr
[gprn
], t0
);
518 tcg_temp_free_i32(t0
);
521 static void spr_write_spefscr (void *opaque
, int sprn
, int gprn
)
523 TCGv_i32 t0
= tcg_temp_new_i32();
524 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[gprn
]);
525 tcg_gen_st_i32(t0
, cpu_env
, offsetof(CPUState
, spe_fscr
));
526 tcg_temp_free_i32(t0
);
529 #if !defined(CONFIG_USER_ONLY)
530 /* Callback used to write the exception vector base */
531 static void spr_write_excp_prefix (void *opaque
, int sprn
, int gprn
)
533 TCGv t0
= tcg_temp_new();
534 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, ivpr_mask
));
535 tcg_gen_and_tl(t0
, t0
, cpu_gpr
[gprn
]);
536 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, excp_prefix
));
537 gen_store_spr(sprn
, t0
);
541 static void spr_write_excp_vector (void *opaque
, int sprn
, int gprn
)
543 DisasContext
*ctx
= opaque
;
545 if (sprn
>= SPR_BOOKE_IVOR0
&& sprn
<= SPR_BOOKE_IVOR15
) {
546 TCGv t0
= tcg_temp_new();
547 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, ivor_mask
));
548 tcg_gen_and_tl(t0
, t0
, cpu_gpr
[gprn
]);
549 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, excp_vectors
[sprn
- SPR_BOOKE_IVOR0
]));
550 gen_store_spr(sprn
, t0
);
552 } else if (sprn
>= SPR_BOOKE_IVOR32
&& sprn
<= SPR_BOOKE_IVOR37
) {
553 TCGv t0
= tcg_temp_new();
554 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, ivor_mask
));
555 tcg_gen_and_tl(t0
, t0
, cpu_gpr
[gprn
]);
556 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, excp_vectors
[sprn
- SPR_BOOKE_IVOR32
+ 32]));
557 gen_store_spr(sprn
, t0
);
560 printf("Trying to write an unknown exception vector %d %03x\n",
562 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
567 static inline void vscr_init (CPUPPCState
*env
, uint32_t val
)
570 /* Altivec always uses round-to-nearest */
571 set_float_rounding_mode(float_round_nearest_even
, &env
->vec_status
);
572 set_flush_to_zero(vscr_nj
, &env
->vec_status
);
575 #if defined(CONFIG_USER_ONLY)
576 #define spr_register(env, num, name, uea_read, uea_write, \
577 oea_read, oea_write, initial_value) \
579 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
581 static inline void _spr_register (CPUPPCState
*env
, int num
,
583 void (*uea_read
)(void *opaque
, int gprn
, int sprn
),
584 void (*uea_write
)(void *opaque
, int sprn
, int gprn
),
585 target_ulong initial_value
)
587 static inline void spr_register (CPUPPCState
*env
, int num
,
589 void (*uea_read
)(void *opaque
, int gprn
, int sprn
),
590 void (*uea_write
)(void *opaque
, int sprn
, int gprn
),
591 void (*oea_read
)(void *opaque
, int gprn
, int sprn
),
592 void (*oea_write
)(void *opaque
, int sprn
, int gprn
),
593 target_ulong initial_value
)
598 spr
= &env
->spr_cb
[num
];
599 if (spr
->name
!= NULL
||env
-> spr
[num
] != 0x00000000 ||
600 #if !defined(CONFIG_USER_ONLY)
601 spr
->oea_read
!= NULL
|| spr
->oea_write
!= NULL
||
603 spr
->uea_read
!= NULL
|| spr
->uea_write
!= NULL
) {
604 printf("Error: Trying to register SPR %d (%03x) twice !\n", num
, num
);
607 #if defined(PPC_DEBUG_SPR)
608 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx
"\n", num
, num
,
609 name
, initial_value
);
612 spr
->uea_read
= uea_read
;
613 spr
->uea_write
= uea_write
;
614 #if !defined(CONFIG_USER_ONLY)
615 spr
->oea_read
= oea_read
;
616 spr
->oea_write
= oea_write
;
618 env
->spr
[num
] = initial_value
;
621 /* Generic PowerPC SPRs */
622 static void gen_spr_generic (CPUPPCState
*env
)
624 /* Integer processing */
625 spr_register(env
, SPR_XER
, "XER",
626 &spr_read_xer
, &spr_write_xer
,
627 &spr_read_xer
, &spr_write_xer
,
630 spr_register(env
, SPR_LR
, "LR",
631 &spr_read_lr
, &spr_write_lr
,
632 &spr_read_lr
, &spr_write_lr
,
634 spr_register(env
, SPR_CTR
, "CTR",
635 &spr_read_ctr
, &spr_write_ctr
,
636 &spr_read_ctr
, &spr_write_ctr
,
638 /* Interrupt processing */
639 spr_register(env
, SPR_SRR0
, "SRR0",
640 SPR_NOACCESS
, SPR_NOACCESS
,
641 &spr_read_generic
, &spr_write_generic
,
643 spr_register(env
, SPR_SRR1
, "SRR1",
644 SPR_NOACCESS
, SPR_NOACCESS
,
645 &spr_read_generic
, &spr_write_generic
,
647 /* Processor control */
648 spr_register(env
, SPR_SPRG0
, "SPRG0",
649 SPR_NOACCESS
, SPR_NOACCESS
,
650 &spr_read_generic
, &spr_write_generic
,
652 spr_register(env
, SPR_SPRG1
, "SPRG1",
653 SPR_NOACCESS
, SPR_NOACCESS
,
654 &spr_read_generic
, &spr_write_generic
,
656 spr_register(env
, SPR_SPRG2
, "SPRG2",
657 SPR_NOACCESS
, SPR_NOACCESS
,
658 &spr_read_generic
, &spr_write_generic
,
660 spr_register(env
, SPR_SPRG3
, "SPRG3",
661 SPR_NOACCESS
, SPR_NOACCESS
,
662 &spr_read_generic
, &spr_write_generic
,
666 /* SPR common to all non-embedded PowerPC, including 601 */
667 static void gen_spr_ne_601 (CPUPPCState
*env
)
669 /* Exception processing */
670 spr_register(env
, SPR_DSISR
, "DSISR",
671 SPR_NOACCESS
, SPR_NOACCESS
,
672 &spr_read_generic
, &spr_write_generic
,
674 spr_register(env
, SPR_DAR
, "DAR",
675 SPR_NOACCESS
, SPR_NOACCESS
,
676 &spr_read_generic
, &spr_write_generic
,
679 spr_register(env
, SPR_DECR
, "DECR",
680 SPR_NOACCESS
, SPR_NOACCESS
,
681 &spr_read_decr
, &spr_write_decr
,
683 /* Memory management */
684 spr_register(env
, SPR_SDR1
, "SDR1",
685 SPR_NOACCESS
, SPR_NOACCESS
,
686 &spr_read_generic
, &spr_write_sdr1
,
691 static void gen_low_BATs (CPUPPCState
*env
)
693 #if !defined(CONFIG_USER_ONLY)
694 spr_register(env
, SPR_IBAT0U
, "IBAT0U",
695 SPR_NOACCESS
, SPR_NOACCESS
,
696 &spr_read_ibat
, &spr_write_ibatu
,
698 spr_register(env
, SPR_IBAT0L
, "IBAT0L",
699 SPR_NOACCESS
, SPR_NOACCESS
,
700 &spr_read_ibat
, &spr_write_ibatl
,
702 spr_register(env
, SPR_IBAT1U
, "IBAT1U",
703 SPR_NOACCESS
, SPR_NOACCESS
,
704 &spr_read_ibat
, &spr_write_ibatu
,
706 spr_register(env
, SPR_IBAT1L
, "IBAT1L",
707 SPR_NOACCESS
, SPR_NOACCESS
,
708 &spr_read_ibat
, &spr_write_ibatl
,
710 spr_register(env
, SPR_IBAT2U
, "IBAT2U",
711 SPR_NOACCESS
, SPR_NOACCESS
,
712 &spr_read_ibat
, &spr_write_ibatu
,
714 spr_register(env
, SPR_IBAT2L
, "IBAT2L",
715 SPR_NOACCESS
, SPR_NOACCESS
,
716 &spr_read_ibat
, &spr_write_ibatl
,
718 spr_register(env
, SPR_IBAT3U
, "IBAT3U",
719 SPR_NOACCESS
, SPR_NOACCESS
,
720 &spr_read_ibat
, &spr_write_ibatu
,
722 spr_register(env
, SPR_IBAT3L
, "IBAT3L",
723 SPR_NOACCESS
, SPR_NOACCESS
,
724 &spr_read_ibat
, &spr_write_ibatl
,
726 spr_register(env
, SPR_DBAT0U
, "DBAT0U",
727 SPR_NOACCESS
, SPR_NOACCESS
,
728 &spr_read_dbat
, &spr_write_dbatu
,
730 spr_register(env
, SPR_DBAT0L
, "DBAT0L",
731 SPR_NOACCESS
, SPR_NOACCESS
,
732 &spr_read_dbat
, &spr_write_dbatl
,
734 spr_register(env
, SPR_DBAT1U
, "DBAT1U",
735 SPR_NOACCESS
, SPR_NOACCESS
,
736 &spr_read_dbat
, &spr_write_dbatu
,
738 spr_register(env
, SPR_DBAT1L
, "DBAT1L",
739 SPR_NOACCESS
, SPR_NOACCESS
,
740 &spr_read_dbat
, &spr_write_dbatl
,
742 spr_register(env
, SPR_DBAT2U
, "DBAT2U",
743 SPR_NOACCESS
, SPR_NOACCESS
,
744 &spr_read_dbat
, &spr_write_dbatu
,
746 spr_register(env
, SPR_DBAT2L
, "DBAT2L",
747 SPR_NOACCESS
, SPR_NOACCESS
,
748 &spr_read_dbat
, &spr_write_dbatl
,
750 spr_register(env
, SPR_DBAT3U
, "DBAT3U",
751 SPR_NOACCESS
, SPR_NOACCESS
,
752 &spr_read_dbat
, &spr_write_dbatu
,
754 spr_register(env
, SPR_DBAT3L
, "DBAT3L",
755 SPR_NOACCESS
, SPR_NOACCESS
,
756 &spr_read_dbat
, &spr_write_dbatl
,
763 static void gen_high_BATs (CPUPPCState
*env
)
765 #if !defined(CONFIG_USER_ONLY)
766 spr_register(env
, SPR_IBAT4U
, "IBAT4U",
767 SPR_NOACCESS
, SPR_NOACCESS
,
768 &spr_read_ibat_h
, &spr_write_ibatu_h
,
770 spr_register(env
, SPR_IBAT4L
, "IBAT4L",
771 SPR_NOACCESS
, SPR_NOACCESS
,
772 &spr_read_ibat_h
, &spr_write_ibatl_h
,
774 spr_register(env
, SPR_IBAT5U
, "IBAT5U",
775 SPR_NOACCESS
, SPR_NOACCESS
,
776 &spr_read_ibat_h
, &spr_write_ibatu_h
,
778 spr_register(env
, SPR_IBAT5L
, "IBAT5L",
779 SPR_NOACCESS
, SPR_NOACCESS
,
780 &spr_read_ibat_h
, &spr_write_ibatl_h
,
782 spr_register(env
, SPR_IBAT6U
, "IBAT6U",
783 SPR_NOACCESS
, SPR_NOACCESS
,
784 &spr_read_ibat_h
, &spr_write_ibatu_h
,
786 spr_register(env
, SPR_IBAT6L
, "IBAT6L",
787 SPR_NOACCESS
, SPR_NOACCESS
,
788 &spr_read_ibat_h
, &spr_write_ibatl_h
,
790 spr_register(env
, SPR_IBAT7U
, "IBAT7U",
791 SPR_NOACCESS
, SPR_NOACCESS
,
792 &spr_read_ibat_h
, &spr_write_ibatu_h
,
794 spr_register(env
, SPR_IBAT7L
, "IBAT7L",
795 SPR_NOACCESS
, SPR_NOACCESS
,
796 &spr_read_ibat_h
, &spr_write_ibatl_h
,
798 spr_register(env
, SPR_DBAT4U
, "DBAT4U",
799 SPR_NOACCESS
, SPR_NOACCESS
,
800 &spr_read_dbat_h
, &spr_write_dbatu_h
,
802 spr_register(env
, SPR_DBAT4L
, "DBAT4L",
803 SPR_NOACCESS
, SPR_NOACCESS
,
804 &spr_read_dbat_h
, &spr_write_dbatl_h
,
806 spr_register(env
, SPR_DBAT5U
, "DBAT5U",
807 SPR_NOACCESS
, SPR_NOACCESS
,
808 &spr_read_dbat_h
, &spr_write_dbatu_h
,
810 spr_register(env
, SPR_DBAT5L
, "DBAT5L",
811 SPR_NOACCESS
, SPR_NOACCESS
,
812 &spr_read_dbat_h
, &spr_write_dbatl_h
,
814 spr_register(env
, SPR_DBAT6U
, "DBAT6U",
815 SPR_NOACCESS
, SPR_NOACCESS
,
816 &spr_read_dbat_h
, &spr_write_dbatu_h
,
818 spr_register(env
, SPR_DBAT6L
, "DBAT6L",
819 SPR_NOACCESS
, SPR_NOACCESS
,
820 &spr_read_dbat_h
, &spr_write_dbatl_h
,
822 spr_register(env
, SPR_DBAT7U
, "DBAT7U",
823 SPR_NOACCESS
, SPR_NOACCESS
,
824 &spr_read_dbat_h
, &spr_write_dbatu_h
,
826 spr_register(env
, SPR_DBAT7L
, "DBAT7L",
827 SPR_NOACCESS
, SPR_NOACCESS
,
828 &spr_read_dbat_h
, &spr_write_dbatl_h
,
834 /* Generic PowerPC time base */
835 static void gen_tbl (CPUPPCState
*env
)
837 spr_register(env
, SPR_VTBL
, "TBL",
838 &spr_read_tbl
, SPR_NOACCESS
,
839 &spr_read_tbl
, SPR_NOACCESS
,
841 spr_register(env
, SPR_TBL
, "TBL",
842 &spr_read_tbl
, SPR_NOACCESS
,
843 &spr_read_tbl
, &spr_write_tbl
,
845 spr_register(env
, SPR_VTBU
, "TBU",
846 &spr_read_tbu
, SPR_NOACCESS
,
847 &spr_read_tbu
, SPR_NOACCESS
,
849 spr_register(env
, SPR_TBU
, "TBU",
850 &spr_read_tbu
, SPR_NOACCESS
,
851 &spr_read_tbu
, &spr_write_tbu
,
855 /* Softare table search registers */
856 static void gen_6xx_7xx_soft_tlb (CPUPPCState
*env
, int nb_tlbs
, int nb_ways
)
858 #if !defined(CONFIG_USER_ONLY)
859 env
->nb_tlb
= nb_tlbs
;
860 env
->nb_ways
= nb_ways
;
862 env
->tlb_type
= TLB_6XX
;
863 spr_register(env
, SPR_DMISS
, "DMISS",
864 SPR_NOACCESS
, SPR_NOACCESS
,
865 &spr_read_generic
, SPR_NOACCESS
,
867 spr_register(env
, SPR_DCMP
, "DCMP",
868 SPR_NOACCESS
, SPR_NOACCESS
,
869 &spr_read_generic
, SPR_NOACCESS
,
871 spr_register(env
, SPR_HASH1
, "HASH1",
872 SPR_NOACCESS
, SPR_NOACCESS
,
873 &spr_read_generic
, SPR_NOACCESS
,
875 spr_register(env
, SPR_HASH2
, "HASH2",
876 SPR_NOACCESS
, SPR_NOACCESS
,
877 &spr_read_generic
, SPR_NOACCESS
,
879 spr_register(env
, SPR_IMISS
, "IMISS",
880 SPR_NOACCESS
, SPR_NOACCESS
,
881 &spr_read_generic
, SPR_NOACCESS
,
883 spr_register(env
, SPR_ICMP
, "ICMP",
884 SPR_NOACCESS
, SPR_NOACCESS
,
885 &spr_read_generic
, SPR_NOACCESS
,
887 spr_register(env
, SPR_RPA
, "RPA",
888 SPR_NOACCESS
, SPR_NOACCESS
,
889 &spr_read_generic
, &spr_write_generic
,
894 /* SPR common to MPC755 and G2 */
895 static void gen_spr_G2_755 (CPUPPCState
*env
)
898 spr_register(env
, SPR_SPRG4
, "SPRG4",
899 SPR_NOACCESS
, SPR_NOACCESS
,
900 &spr_read_generic
, &spr_write_generic
,
902 spr_register(env
, SPR_SPRG5
, "SPRG5",
903 SPR_NOACCESS
, SPR_NOACCESS
,
904 &spr_read_generic
, &spr_write_generic
,
906 spr_register(env
, SPR_SPRG6
, "SPRG6",
907 SPR_NOACCESS
, SPR_NOACCESS
,
908 &spr_read_generic
, &spr_write_generic
,
910 spr_register(env
, SPR_SPRG7
, "SPRG7",
911 SPR_NOACCESS
, SPR_NOACCESS
,
912 &spr_read_generic
, &spr_write_generic
,
916 /* SPR common to all 7xx PowerPC implementations */
917 static void gen_spr_7xx (CPUPPCState
*env
)
920 /* XXX : not implemented */
921 spr_register(env
, SPR_DABR
, "DABR",
922 SPR_NOACCESS
, SPR_NOACCESS
,
923 &spr_read_generic
, &spr_write_generic
,
925 /* XXX : not implemented */
926 spr_register(env
, SPR_IABR
, "IABR",
927 SPR_NOACCESS
, SPR_NOACCESS
,
928 &spr_read_generic
, &spr_write_generic
,
930 /* Cache management */
931 /* XXX : not implemented */
932 spr_register(env
, SPR_ICTC
, "ICTC",
933 SPR_NOACCESS
, SPR_NOACCESS
,
934 &spr_read_generic
, &spr_write_generic
,
936 /* Performance monitors */
937 /* XXX : not implemented */
938 spr_register(env
, SPR_MMCR0
, "MMCR0",
939 SPR_NOACCESS
, SPR_NOACCESS
,
940 &spr_read_generic
, &spr_write_generic
,
942 /* XXX : not implemented */
943 spr_register(env
, SPR_MMCR1
, "MMCR1",
944 SPR_NOACCESS
, SPR_NOACCESS
,
945 &spr_read_generic
, &spr_write_generic
,
947 /* XXX : not implemented */
948 spr_register(env
, SPR_PMC1
, "PMC1",
949 SPR_NOACCESS
, SPR_NOACCESS
,
950 &spr_read_generic
, &spr_write_generic
,
952 /* XXX : not implemented */
953 spr_register(env
, SPR_PMC2
, "PMC2",
954 SPR_NOACCESS
, SPR_NOACCESS
,
955 &spr_read_generic
, &spr_write_generic
,
957 /* XXX : not implemented */
958 spr_register(env
, SPR_PMC3
, "PMC3",
959 SPR_NOACCESS
, SPR_NOACCESS
,
960 &spr_read_generic
, &spr_write_generic
,
962 /* XXX : not implemented */
963 spr_register(env
, SPR_PMC4
, "PMC4",
964 SPR_NOACCESS
, SPR_NOACCESS
,
965 &spr_read_generic
, &spr_write_generic
,
967 /* XXX : not implemented */
968 spr_register(env
, SPR_SIAR
, "SIAR",
969 SPR_NOACCESS
, SPR_NOACCESS
,
970 &spr_read_generic
, SPR_NOACCESS
,
972 /* XXX : not implemented */
973 spr_register(env
, SPR_UMMCR0
, "UMMCR0",
974 &spr_read_ureg
, SPR_NOACCESS
,
975 &spr_read_ureg
, SPR_NOACCESS
,
977 /* XXX : not implemented */
978 spr_register(env
, SPR_UMMCR1
, "UMMCR1",
979 &spr_read_ureg
, SPR_NOACCESS
,
980 &spr_read_ureg
, SPR_NOACCESS
,
982 /* XXX : not implemented */
983 spr_register(env
, SPR_UPMC1
, "UPMC1",
984 &spr_read_ureg
, SPR_NOACCESS
,
985 &spr_read_ureg
, SPR_NOACCESS
,
987 /* XXX : not implemented */
988 spr_register(env
, SPR_UPMC2
, "UPMC2",
989 &spr_read_ureg
, SPR_NOACCESS
,
990 &spr_read_ureg
, SPR_NOACCESS
,
992 /* XXX : not implemented */
993 spr_register(env
, SPR_UPMC3
, "UPMC3",
994 &spr_read_ureg
, SPR_NOACCESS
,
995 &spr_read_ureg
, SPR_NOACCESS
,
997 /* XXX : not implemented */
998 spr_register(env
, SPR_UPMC4
, "UPMC4",
999 &spr_read_ureg
, SPR_NOACCESS
,
1000 &spr_read_ureg
, SPR_NOACCESS
,
1002 /* XXX : not implemented */
1003 spr_register(env
, SPR_USIAR
, "USIAR",
1004 &spr_read_ureg
, SPR_NOACCESS
,
1005 &spr_read_ureg
, SPR_NOACCESS
,
1007 /* External access control */
1008 /* XXX : not implemented */
1009 spr_register(env
, SPR_EAR
, "EAR",
1010 SPR_NOACCESS
, SPR_NOACCESS
,
1011 &spr_read_generic
, &spr_write_generic
,
1015 static void gen_spr_thrm (CPUPPCState
*env
)
1017 /* Thermal management */
1018 /* XXX : not implemented */
1019 spr_register(env
, SPR_THRM1
, "THRM1",
1020 SPR_NOACCESS
, SPR_NOACCESS
,
1021 &spr_read_generic
, &spr_write_generic
,
1023 /* XXX : not implemented */
1024 spr_register(env
, SPR_THRM2
, "THRM2",
1025 SPR_NOACCESS
, SPR_NOACCESS
,
1026 &spr_read_generic
, &spr_write_generic
,
1028 /* XXX : not implemented */
1029 spr_register(env
, SPR_THRM3
, "THRM3",
1030 SPR_NOACCESS
, SPR_NOACCESS
,
1031 &spr_read_generic
, &spr_write_generic
,
1035 /* SPR specific to PowerPC 604 implementation */
1036 static void gen_spr_604 (CPUPPCState
*env
)
1038 /* Processor identification */
1039 spr_register(env
, SPR_PIR
, "PIR",
1040 SPR_NOACCESS
, SPR_NOACCESS
,
1041 &spr_read_generic
, &spr_write_pir
,
1044 /* XXX : not implemented */
1045 spr_register(env
, SPR_IABR
, "IABR",
1046 SPR_NOACCESS
, SPR_NOACCESS
,
1047 &spr_read_generic
, &spr_write_generic
,
1049 /* XXX : not implemented */
1050 spr_register(env
, SPR_DABR
, "DABR",
1051 SPR_NOACCESS
, SPR_NOACCESS
,
1052 &spr_read_generic
, &spr_write_generic
,
1054 /* Performance counters */
1055 /* XXX : not implemented */
1056 spr_register(env
, SPR_MMCR0
, "MMCR0",
1057 SPR_NOACCESS
, SPR_NOACCESS
,
1058 &spr_read_generic
, &spr_write_generic
,
1060 /* XXX : not implemented */
1061 spr_register(env
, SPR_PMC1
, "PMC1",
1062 SPR_NOACCESS
, SPR_NOACCESS
,
1063 &spr_read_generic
, &spr_write_generic
,
1065 /* XXX : not implemented */
1066 spr_register(env
, SPR_PMC2
, "PMC2",
1067 SPR_NOACCESS
, SPR_NOACCESS
,
1068 &spr_read_generic
, &spr_write_generic
,
1070 /* XXX : not implemented */
1071 spr_register(env
, SPR_SIAR
, "SIAR",
1072 SPR_NOACCESS
, SPR_NOACCESS
,
1073 &spr_read_generic
, SPR_NOACCESS
,
1075 /* XXX : not implemented */
1076 spr_register(env
, SPR_SDA
, "SDA",
1077 SPR_NOACCESS
, SPR_NOACCESS
,
1078 &spr_read_generic
, SPR_NOACCESS
,
1080 /* External access control */
1081 /* XXX : not implemented */
1082 spr_register(env
, SPR_EAR
, "EAR",
1083 SPR_NOACCESS
, SPR_NOACCESS
,
1084 &spr_read_generic
, &spr_write_generic
,
1088 /* SPR specific to PowerPC 603 implementation */
1089 static void gen_spr_603 (CPUPPCState
*env
)
1091 /* External access control */
1092 /* XXX : not implemented */
1093 spr_register(env
, SPR_EAR
, "EAR",
1094 SPR_NOACCESS
, SPR_NOACCESS
,
1095 &spr_read_generic
, &spr_write_generic
,
1099 /* SPR specific to PowerPC G2 implementation */
1100 static void gen_spr_G2 (CPUPPCState
*env
)
1102 /* Memory base address */
1104 /* XXX : not implemented */
1105 spr_register(env
, SPR_MBAR
, "MBAR",
1106 SPR_NOACCESS
, SPR_NOACCESS
,
1107 &spr_read_generic
, &spr_write_generic
,
1109 /* Exception processing */
1110 spr_register(env
, SPR_BOOKE_CSRR0
, "CSRR0",
1111 SPR_NOACCESS
, SPR_NOACCESS
,
1112 &spr_read_generic
, &spr_write_generic
,
1114 spr_register(env
, SPR_BOOKE_CSRR1
, "CSRR1",
1115 SPR_NOACCESS
, SPR_NOACCESS
,
1116 &spr_read_generic
, &spr_write_generic
,
1119 /* XXX : not implemented */
1120 spr_register(env
, SPR_DABR
, "DABR",
1121 SPR_NOACCESS
, SPR_NOACCESS
,
1122 &spr_read_generic
, &spr_write_generic
,
1124 /* XXX : not implemented */
1125 spr_register(env
, SPR_DABR2
, "DABR2",
1126 SPR_NOACCESS
, SPR_NOACCESS
,
1127 &spr_read_generic
, &spr_write_generic
,
1129 /* XXX : not implemented */
1130 spr_register(env
, SPR_IABR
, "IABR",
1131 SPR_NOACCESS
, SPR_NOACCESS
,
1132 &spr_read_generic
, &spr_write_generic
,
1134 /* XXX : not implemented */
1135 spr_register(env
, SPR_IABR2
, "IABR2",
1136 SPR_NOACCESS
, SPR_NOACCESS
,
1137 &spr_read_generic
, &spr_write_generic
,
1139 /* XXX : not implemented */
1140 spr_register(env
, SPR_IBCR
, "IBCR",
1141 SPR_NOACCESS
, SPR_NOACCESS
,
1142 &spr_read_generic
, &spr_write_generic
,
1144 /* XXX : not implemented */
1145 spr_register(env
, SPR_DBCR
, "DBCR",
1146 SPR_NOACCESS
, SPR_NOACCESS
,
1147 &spr_read_generic
, &spr_write_generic
,
1151 /* SPR specific to PowerPC 602 implementation */
1152 static void gen_spr_602 (CPUPPCState
*env
)
1155 /* XXX : not implemented */
1156 spr_register(env
, SPR_SER
, "SER",
1157 SPR_NOACCESS
, SPR_NOACCESS
,
1158 &spr_read_generic
, &spr_write_generic
,
1160 /* XXX : not implemented */
1161 spr_register(env
, SPR_SEBR
, "SEBR",
1162 SPR_NOACCESS
, SPR_NOACCESS
,
1163 &spr_read_generic
, &spr_write_generic
,
1165 /* XXX : not implemented */
1166 spr_register(env
, SPR_ESASRR
, "ESASRR",
1167 SPR_NOACCESS
, SPR_NOACCESS
,
1168 &spr_read_generic
, &spr_write_generic
,
1170 /* Floating point status */
1171 /* XXX : not implemented */
1172 spr_register(env
, SPR_SP
, "SP",
1173 SPR_NOACCESS
, SPR_NOACCESS
,
1174 &spr_read_generic
, &spr_write_generic
,
1176 /* XXX : not implemented */
1177 spr_register(env
, SPR_LT
, "LT",
1178 SPR_NOACCESS
, SPR_NOACCESS
,
1179 &spr_read_generic
, &spr_write_generic
,
1181 /* Watchdog timer */
1182 /* XXX : not implemented */
1183 spr_register(env
, SPR_TCR
, "TCR",
1184 SPR_NOACCESS
, SPR_NOACCESS
,
1185 &spr_read_generic
, &spr_write_generic
,
1187 /* Interrupt base */
1188 spr_register(env
, SPR_IBR
, "IBR",
1189 SPR_NOACCESS
, SPR_NOACCESS
,
1190 &spr_read_generic
, &spr_write_generic
,
1192 /* XXX : not implemented */
1193 spr_register(env
, SPR_IABR
, "IABR",
1194 SPR_NOACCESS
, SPR_NOACCESS
,
1195 &spr_read_generic
, &spr_write_generic
,
1199 /* SPR specific to PowerPC 601 implementation */
1200 static void gen_spr_601 (CPUPPCState
*env
)
1202 /* Multiplication/division register */
1204 spr_register(env
, SPR_MQ
, "MQ",
1205 &spr_read_generic
, &spr_write_generic
,
1206 &spr_read_generic
, &spr_write_generic
,
1209 spr_register(env
, SPR_601_RTCU
, "RTCU",
1210 SPR_NOACCESS
, SPR_NOACCESS
,
1211 SPR_NOACCESS
, &spr_write_601_rtcu
,
1213 spr_register(env
, SPR_601_VRTCU
, "RTCU",
1214 &spr_read_601_rtcu
, SPR_NOACCESS
,
1215 &spr_read_601_rtcu
, SPR_NOACCESS
,
1217 spr_register(env
, SPR_601_RTCL
, "RTCL",
1218 SPR_NOACCESS
, SPR_NOACCESS
,
1219 SPR_NOACCESS
, &spr_write_601_rtcl
,
1221 spr_register(env
, SPR_601_VRTCL
, "RTCL",
1222 &spr_read_601_rtcl
, SPR_NOACCESS
,
1223 &spr_read_601_rtcl
, SPR_NOACCESS
,
1227 spr_register(env
, SPR_601_UDECR
, "UDECR",
1228 &spr_read_decr
, SPR_NOACCESS
,
1229 &spr_read_decr
, SPR_NOACCESS
,
1232 /* External access control */
1233 /* XXX : not implemented */
1234 spr_register(env
, SPR_EAR
, "EAR",
1235 SPR_NOACCESS
, SPR_NOACCESS
,
1236 &spr_read_generic
, &spr_write_generic
,
1238 /* Memory management */
1239 #if !defined(CONFIG_USER_ONLY)
1240 spr_register(env
, SPR_IBAT0U
, "IBAT0U",
1241 SPR_NOACCESS
, SPR_NOACCESS
,
1242 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1244 spr_register(env
, SPR_IBAT0L
, "IBAT0L",
1245 SPR_NOACCESS
, SPR_NOACCESS
,
1246 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1248 spr_register(env
, SPR_IBAT1U
, "IBAT1U",
1249 SPR_NOACCESS
, SPR_NOACCESS
,
1250 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1252 spr_register(env
, SPR_IBAT1L
, "IBAT1L",
1253 SPR_NOACCESS
, SPR_NOACCESS
,
1254 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1256 spr_register(env
, SPR_IBAT2U
, "IBAT2U",
1257 SPR_NOACCESS
, SPR_NOACCESS
,
1258 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1260 spr_register(env
, SPR_IBAT2L
, "IBAT2L",
1261 SPR_NOACCESS
, SPR_NOACCESS
,
1262 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1264 spr_register(env
, SPR_IBAT3U
, "IBAT3U",
1265 SPR_NOACCESS
, SPR_NOACCESS
,
1266 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1268 spr_register(env
, SPR_IBAT3L
, "IBAT3L",
1269 SPR_NOACCESS
, SPR_NOACCESS
,
1270 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1276 static void gen_spr_74xx (CPUPPCState
*env
)
1278 /* Processor identification */
1279 spr_register(env
, SPR_PIR
, "PIR",
1280 SPR_NOACCESS
, SPR_NOACCESS
,
1281 &spr_read_generic
, &spr_write_pir
,
1283 /* XXX : not implemented */
1284 spr_register(env
, SPR_MMCR2
, "MMCR2",
1285 SPR_NOACCESS
, SPR_NOACCESS
,
1286 &spr_read_generic
, &spr_write_generic
,
1288 /* XXX : not implemented */
1289 spr_register(env
, SPR_UMMCR2
, "UMMCR2",
1290 &spr_read_ureg
, SPR_NOACCESS
,
1291 &spr_read_ureg
, SPR_NOACCESS
,
1293 /* XXX: not implemented */
1294 spr_register(env
, SPR_BAMR
, "BAMR",
1295 SPR_NOACCESS
, SPR_NOACCESS
,
1296 &spr_read_generic
, &spr_write_generic
,
1298 /* XXX : not implemented */
1299 spr_register(env
, SPR_MSSCR0
, "MSSCR0",
1300 SPR_NOACCESS
, SPR_NOACCESS
,
1301 &spr_read_generic
, &spr_write_generic
,
1303 /* Hardware implementation registers */
1304 /* XXX : not implemented */
1305 spr_register(env
, SPR_HID0
, "HID0",
1306 SPR_NOACCESS
, SPR_NOACCESS
,
1307 &spr_read_generic
, &spr_write_generic
,
1309 /* XXX : not implemented */
1310 spr_register(env
, SPR_HID1
, "HID1",
1311 SPR_NOACCESS
, SPR_NOACCESS
,
1312 &spr_read_generic
, &spr_write_generic
,
1315 spr_register(env
, SPR_VRSAVE
, "VRSAVE",
1316 &spr_read_generic
, &spr_write_generic
,
1317 &spr_read_generic
, &spr_write_generic
,
1319 /* XXX : not implemented */
1320 spr_register(env
, SPR_L2CR
, "L2CR",
1321 SPR_NOACCESS
, SPR_NOACCESS
,
1322 &spr_read_generic
, &spr_write_generic
,
1324 /* Not strictly an SPR */
1325 vscr_init(env
, 0x00010000);
1328 static void gen_l3_ctrl (CPUPPCState
*env
)
1331 /* XXX : not implemented */
1332 spr_register(env
, SPR_L3CR
, "L3CR",
1333 SPR_NOACCESS
, SPR_NOACCESS
,
1334 &spr_read_generic
, &spr_write_generic
,
1337 /* XXX : not implemented */
1338 spr_register(env
, SPR_L3ITCR0
, "L3ITCR0",
1339 SPR_NOACCESS
, SPR_NOACCESS
,
1340 &spr_read_generic
, &spr_write_generic
,
1343 /* XXX : not implemented */
1344 spr_register(env
, SPR_L3PM
, "L3PM",
1345 SPR_NOACCESS
, SPR_NOACCESS
,
1346 &spr_read_generic
, &spr_write_generic
,
1350 static void gen_74xx_soft_tlb (CPUPPCState
*env
, int nb_tlbs
, int nb_ways
)
1352 #if !defined(CONFIG_USER_ONLY)
1353 env
->nb_tlb
= nb_tlbs
;
1354 env
->nb_ways
= nb_ways
;
1356 env
->tlb_type
= TLB_6XX
;
1357 /* XXX : not implemented */
1358 spr_register(env
, SPR_PTEHI
, "PTEHI",
1359 SPR_NOACCESS
, SPR_NOACCESS
,
1360 &spr_read_generic
, &spr_write_generic
,
1362 /* XXX : not implemented */
1363 spr_register(env
, SPR_PTELO
, "PTELO",
1364 SPR_NOACCESS
, SPR_NOACCESS
,
1365 &spr_read_generic
, &spr_write_generic
,
1367 /* XXX : not implemented */
1368 spr_register(env
, SPR_TLBMISS
, "TLBMISS",
1369 SPR_NOACCESS
, SPR_NOACCESS
,
1370 &spr_read_generic
, &spr_write_generic
,
1375 #if !defined(CONFIG_USER_ONLY)
1376 static void spr_write_e500_l1csr0 (void *opaque
, int sprn
, int gprn
)
1378 TCGv t0
= tcg_temp_new();
1380 tcg_gen_andi_tl(t0
, cpu_gpr
[gprn
], ~256);
1381 gen_store_spr(sprn
, t0
);
1385 static void spr_write_booke206_mmucsr0 (void *opaque
, int sprn
, int gprn
)
1387 TCGv_i32 t0
= tcg_const_i32(sprn
);
1388 gen_helper_booke206_tlbflush(t0
);
1389 tcg_temp_free_i32(t0
);
1392 static void spr_write_booke_pid (void *opaque
, int sprn
, int gprn
)
1394 TCGv_i32 t0
= tcg_const_i32(sprn
);
1395 gen_helper_booke_setpid(t0
, cpu_gpr
[gprn
]);
1396 tcg_temp_free_i32(t0
);
1400 static void gen_spr_usprgh (CPUPPCState
*env
)
1402 spr_register(env
, SPR_USPRG4
, "USPRG4",
1403 &spr_read_ureg
, SPR_NOACCESS
,
1404 &spr_read_ureg
, SPR_NOACCESS
,
1406 spr_register(env
, SPR_USPRG5
, "USPRG5",
1407 &spr_read_ureg
, SPR_NOACCESS
,
1408 &spr_read_ureg
, SPR_NOACCESS
,
1410 spr_register(env
, SPR_USPRG6
, "USPRG6",
1411 &spr_read_ureg
, SPR_NOACCESS
,
1412 &spr_read_ureg
, SPR_NOACCESS
,
1414 spr_register(env
, SPR_USPRG7
, "USPRG7",
1415 &spr_read_ureg
, SPR_NOACCESS
,
1416 &spr_read_ureg
, SPR_NOACCESS
,
1420 /* PowerPC BookE SPR */
1421 static void gen_spr_BookE (CPUPPCState
*env
, uint64_t ivor_mask
)
1423 const char *ivor_names
[64] = {
1424 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1425 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1426 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1427 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1428 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1429 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1430 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1431 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1432 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1433 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1434 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1435 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1436 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1437 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1438 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1439 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1441 #define SPR_BOOKE_IVORxx (-1)
1442 int ivor_sprn
[64] = {
1443 SPR_BOOKE_IVOR0
, SPR_BOOKE_IVOR1
, SPR_BOOKE_IVOR2
, SPR_BOOKE_IVOR3
,
1444 SPR_BOOKE_IVOR4
, SPR_BOOKE_IVOR5
, SPR_BOOKE_IVOR6
, SPR_BOOKE_IVOR7
,
1445 SPR_BOOKE_IVOR8
, SPR_BOOKE_IVOR9
, SPR_BOOKE_IVOR10
, SPR_BOOKE_IVOR11
,
1446 SPR_BOOKE_IVOR12
, SPR_BOOKE_IVOR13
, SPR_BOOKE_IVOR14
, SPR_BOOKE_IVOR15
,
1447 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1448 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1449 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1450 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1451 SPR_BOOKE_IVOR32
, SPR_BOOKE_IVOR33
, SPR_BOOKE_IVOR34
, SPR_BOOKE_IVOR35
,
1452 SPR_BOOKE_IVOR36
, SPR_BOOKE_IVOR37
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1453 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1454 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1455 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1456 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1457 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1458 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1462 /* Interrupt processing */
1463 spr_register(env
, SPR_BOOKE_CSRR0
, "CSRR0",
1464 SPR_NOACCESS
, SPR_NOACCESS
,
1465 &spr_read_generic
, &spr_write_generic
,
1467 spr_register(env
, SPR_BOOKE_CSRR1
, "CSRR1",
1468 SPR_NOACCESS
, SPR_NOACCESS
,
1469 &spr_read_generic
, &spr_write_generic
,
1472 /* XXX : not implemented */
1473 spr_register(env
, SPR_BOOKE_IAC1
, "IAC1",
1474 SPR_NOACCESS
, SPR_NOACCESS
,
1475 &spr_read_generic
, &spr_write_generic
,
1477 /* XXX : not implemented */
1478 spr_register(env
, SPR_BOOKE_IAC2
, "IAC2",
1479 SPR_NOACCESS
, SPR_NOACCESS
,
1480 &spr_read_generic
, &spr_write_generic
,
1482 /* XXX : not implemented */
1483 spr_register(env
, SPR_BOOKE_DAC1
, "DAC1",
1484 SPR_NOACCESS
, SPR_NOACCESS
,
1485 &spr_read_generic
, &spr_write_generic
,
1487 /* XXX : not implemented */
1488 spr_register(env
, SPR_BOOKE_DAC2
, "DAC2",
1489 SPR_NOACCESS
, SPR_NOACCESS
,
1490 &spr_read_generic
, &spr_write_generic
,
1492 /* XXX : not implemented */
1493 spr_register(env
, SPR_BOOKE_DBCR0
, "DBCR0",
1494 SPR_NOACCESS
, SPR_NOACCESS
,
1495 &spr_read_generic
, &spr_write_generic
,
1497 /* XXX : not implemented */
1498 spr_register(env
, SPR_BOOKE_DBCR1
, "DBCR1",
1499 SPR_NOACCESS
, SPR_NOACCESS
,
1500 &spr_read_generic
, &spr_write_generic
,
1502 /* XXX : not implemented */
1503 spr_register(env
, SPR_BOOKE_DBCR2
, "DBCR2",
1504 SPR_NOACCESS
, SPR_NOACCESS
,
1505 &spr_read_generic
, &spr_write_generic
,
1507 /* XXX : not implemented */
1508 spr_register(env
, SPR_BOOKE_DBSR
, "DBSR",
1509 SPR_NOACCESS
, SPR_NOACCESS
,
1510 &spr_read_generic
, &spr_write_clear
,
1512 spr_register(env
, SPR_BOOKE_DEAR
, "DEAR",
1513 SPR_NOACCESS
, SPR_NOACCESS
,
1514 &spr_read_generic
, &spr_write_generic
,
1516 spr_register(env
, SPR_BOOKE_ESR
, "ESR",
1517 SPR_NOACCESS
, SPR_NOACCESS
,
1518 &spr_read_generic
, &spr_write_generic
,
1520 spr_register(env
, SPR_BOOKE_IVPR
, "IVPR",
1521 SPR_NOACCESS
, SPR_NOACCESS
,
1522 &spr_read_generic
, &spr_write_excp_prefix
,
1524 /* Exception vectors */
1525 for (i
= 0; i
< 64; i
++) {
1526 if (ivor_mask
& (1ULL << i
)) {
1527 if (ivor_sprn
[i
] == SPR_BOOKE_IVORxx
) {
1528 fprintf(stderr
, "ERROR: IVOR %d SPR is not defined\n", i
);
1531 spr_register(env
, ivor_sprn
[i
], ivor_names
[i
],
1532 SPR_NOACCESS
, SPR_NOACCESS
,
1533 &spr_read_generic
, &spr_write_excp_vector
,
1537 spr_register(env
, SPR_BOOKE_PID
, "PID",
1538 SPR_NOACCESS
, SPR_NOACCESS
,
1539 &spr_read_generic
, &spr_write_booke_pid
,
1541 spr_register(env
, SPR_BOOKE_TCR
, "TCR",
1542 SPR_NOACCESS
, SPR_NOACCESS
,
1543 &spr_read_generic
, &spr_write_booke_tcr
,
1545 spr_register(env
, SPR_BOOKE_TSR
, "TSR",
1546 SPR_NOACCESS
, SPR_NOACCESS
,
1547 &spr_read_generic
, &spr_write_booke_tsr
,
1550 spr_register(env
, SPR_DECR
, "DECR",
1551 SPR_NOACCESS
, SPR_NOACCESS
,
1552 &spr_read_decr
, &spr_write_decr
,
1554 spr_register(env
, SPR_BOOKE_DECAR
, "DECAR",
1555 SPR_NOACCESS
, SPR_NOACCESS
,
1556 SPR_NOACCESS
, &spr_write_generic
,
1559 spr_register(env
, SPR_USPRG0
, "USPRG0",
1560 &spr_read_generic
, &spr_write_generic
,
1561 &spr_read_generic
, &spr_write_generic
,
1563 spr_register(env
, SPR_SPRG4
, "SPRG4",
1564 SPR_NOACCESS
, SPR_NOACCESS
,
1565 &spr_read_generic
, &spr_write_generic
,
1567 spr_register(env
, SPR_SPRG5
, "SPRG5",
1568 SPR_NOACCESS
, SPR_NOACCESS
,
1569 &spr_read_generic
, &spr_write_generic
,
1571 spr_register(env
, SPR_SPRG6
, "SPRG6",
1572 SPR_NOACCESS
, SPR_NOACCESS
,
1573 &spr_read_generic
, &spr_write_generic
,
1575 spr_register(env
, SPR_SPRG7
, "SPRG7",
1576 SPR_NOACCESS
, SPR_NOACCESS
,
1577 &spr_read_generic
, &spr_write_generic
,
1581 static inline uint32_t gen_tlbncfg(uint32_t assoc
, uint32_t minsize
,
1582 uint32_t maxsize
, uint32_t flags
,
1585 return (assoc
<< TLBnCFG_ASSOC_SHIFT
) |
1586 (minsize
<< TLBnCFG_MINSIZE_SHIFT
) |
1587 (maxsize
<< TLBnCFG_MAXSIZE_SHIFT
) |
1591 /* BookE 2.06 storage control registers */
1592 static void gen_spr_BookE206(CPUPPCState
*env
, uint32_t mas_mask
,
1595 #if !defined(CONFIG_USER_ONLY)
1596 const char *mas_names
[8] = {
1597 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1600 SPR_BOOKE_MAS0
, SPR_BOOKE_MAS1
, SPR_BOOKE_MAS2
, SPR_BOOKE_MAS3
,
1601 SPR_BOOKE_MAS4
, SPR_BOOKE_MAS5
, SPR_BOOKE_MAS6
, SPR_BOOKE_MAS7
,
1605 /* TLB assist registers */
1606 /* XXX : not implemented */
1607 for (i
= 0; i
< 8; i
++) {
1608 if (mas_mask
& (1 << i
)) {
1609 spr_register(env
, mas_sprn
[i
], mas_names
[i
],
1610 SPR_NOACCESS
, SPR_NOACCESS
,
1611 &spr_read_generic
, &spr_write_generic
,
1615 if (env
->nb_pids
> 1) {
1616 /* XXX : not implemented */
1617 spr_register(env
, SPR_BOOKE_PID1
, "PID1",
1618 SPR_NOACCESS
, SPR_NOACCESS
,
1619 &spr_read_generic
, &spr_write_booke_pid
,
1622 if (env
->nb_pids
> 2) {
1623 /* XXX : not implemented */
1624 spr_register(env
, SPR_BOOKE_PID2
, "PID2",
1625 SPR_NOACCESS
, SPR_NOACCESS
,
1626 &spr_read_generic
, &spr_write_booke_pid
,
1629 /* XXX : not implemented */
1630 spr_register(env
, SPR_MMUCFG
, "MMUCFG",
1631 SPR_NOACCESS
, SPR_NOACCESS
,
1632 &spr_read_generic
, SPR_NOACCESS
,
1633 0x00000000); /* TOFIX */
1634 switch (env
->nb_ways
) {
1636 spr_register(env
, SPR_BOOKE_TLB3CFG
, "TLB3CFG",
1637 SPR_NOACCESS
, SPR_NOACCESS
,
1638 &spr_read_generic
, SPR_NOACCESS
,
1642 spr_register(env
, SPR_BOOKE_TLB2CFG
, "TLB2CFG",
1643 SPR_NOACCESS
, SPR_NOACCESS
,
1644 &spr_read_generic
, SPR_NOACCESS
,
1648 spr_register(env
, SPR_BOOKE_TLB1CFG
, "TLB1CFG",
1649 SPR_NOACCESS
, SPR_NOACCESS
,
1650 &spr_read_generic
, SPR_NOACCESS
,
1654 spr_register(env
, SPR_BOOKE_TLB0CFG
, "TLB0CFG",
1655 SPR_NOACCESS
, SPR_NOACCESS
,
1656 &spr_read_generic
, SPR_NOACCESS
,
1665 gen_spr_usprgh(env
);
1668 /* SPR specific to PowerPC 440 implementation */
1669 static void gen_spr_440 (CPUPPCState
*env
)
1672 /* XXX : not implemented */
1673 spr_register(env
, SPR_440_DNV0
, "DNV0",
1674 SPR_NOACCESS
, SPR_NOACCESS
,
1675 &spr_read_generic
, &spr_write_generic
,
1677 /* XXX : not implemented */
1678 spr_register(env
, SPR_440_DNV1
, "DNV1",
1679 SPR_NOACCESS
, SPR_NOACCESS
,
1680 &spr_read_generic
, &spr_write_generic
,
1682 /* XXX : not implemented */
1683 spr_register(env
, SPR_440_DNV2
, "DNV2",
1684 SPR_NOACCESS
, SPR_NOACCESS
,
1685 &spr_read_generic
, &spr_write_generic
,
1687 /* XXX : not implemented */
1688 spr_register(env
, SPR_440_DNV3
, "DNV3",
1689 SPR_NOACCESS
, SPR_NOACCESS
,
1690 &spr_read_generic
, &spr_write_generic
,
1692 /* XXX : not implemented */
1693 spr_register(env
, SPR_440_DTV0
, "DTV0",
1694 SPR_NOACCESS
, SPR_NOACCESS
,
1695 &spr_read_generic
, &spr_write_generic
,
1697 /* XXX : not implemented */
1698 spr_register(env
, SPR_440_DTV1
, "DTV1",
1699 SPR_NOACCESS
, SPR_NOACCESS
,
1700 &spr_read_generic
, &spr_write_generic
,
1702 /* XXX : not implemented */
1703 spr_register(env
, SPR_440_DTV2
, "DTV2",
1704 SPR_NOACCESS
, SPR_NOACCESS
,
1705 &spr_read_generic
, &spr_write_generic
,
1707 /* XXX : not implemented */
1708 spr_register(env
, SPR_440_DTV3
, "DTV3",
1709 SPR_NOACCESS
, SPR_NOACCESS
,
1710 &spr_read_generic
, &spr_write_generic
,
1712 /* XXX : not implemented */
1713 spr_register(env
, SPR_440_DVLIM
, "DVLIM",
1714 SPR_NOACCESS
, SPR_NOACCESS
,
1715 &spr_read_generic
, &spr_write_generic
,
1717 /* XXX : not implemented */
1718 spr_register(env
, SPR_440_INV0
, "INV0",
1719 SPR_NOACCESS
, SPR_NOACCESS
,
1720 &spr_read_generic
, &spr_write_generic
,
1722 /* XXX : not implemented */
1723 spr_register(env
, SPR_440_INV1
, "INV1",
1724 SPR_NOACCESS
, SPR_NOACCESS
,
1725 &spr_read_generic
, &spr_write_generic
,
1727 /* XXX : not implemented */
1728 spr_register(env
, SPR_440_INV2
, "INV2",
1729 SPR_NOACCESS
, SPR_NOACCESS
,
1730 &spr_read_generic
, &spr_write_generic
,
1732 /* XXX : not implemented */
1733 spr_register(env
, SPR_440_INV3
, "INV3",
1734 SPR_NOACCESS
, SPR_NOACCESS
,
1735 &spr_read_generic
, &spr_write_generic
,
1737 /* XXX : not implemented */
1738 spr_register(env
, SPR_440_ITV0
, "ITV0",
1739 SPR_NOACCESS
, SPR_NOACCESS
,
1740 &spr_read_generic
, &spr_write_generic
,
1742 /* XXX : not implemented */
1743 spr_register(env
, SPR_440_ITV1
, "ITV1",
1744 SPR_NOACCESS
, SPR_NOACCESS
,
1745 &spr_read_generic
, &spr_write_generic
,
1747 /* XXX : not implemented */
1748 spr_register(env
, SPR_440_ITV2
, "ITV2",
1749 SPR_NOACCESS
, SPR_NOACCESS
,
1750 &spr_read_generic
, &spr_write_generic
,
1752 /* XXX : not implemented */
1753 spr_register(env
, SPR_440_ITV3
, "ITV3",
1754 SPR_NOACCESS
, SPR_NOACCESS
,
1755 &spr_read_generic
, &spr_write_generic
,
1757 /* XXX : not implemented */
1758 spr_register(env
, SPR_440_IVLIM
, "IVLIM",
1759 SPR_NOACCESS
, SPR_NOACCESS
,
1760 &spr_read_generic
, &spr_write_generic
,
1763 /* XXX : not implemented */
1764 spr_register(env
, SPR_BOOKE_DCDBTRH
, "DCDBTRH",
1765 SPR_NOACCESS
, SPR_NOACCESS
,
1766 &spr_read_generic
, SPR_NOACCESS
,
1768 /* XXX : not implemented */
1769 spr_register(env
, SPR_BOOKE_DCDBTRL
, "DCDBTRL",
1770 SPR_NOACCESS
, SPR_NOACCESS
,
1771 &spr_read_generic
, SPR_NOACCESS
,
1773 /* XXX : not implemented */
1774 spr_register(env
, SPR_BOOKE_ICDBDR
, "ICDBDR",
1775 SPR_NOACCESS
, SPR_NOACCESS
,
1776 &spr_read_generic
, SPR_NOACCESS
,
1778 /* XXX : not implemented */
1779 spr_register(env
, SPR_BOOKE_ICDBTRH
, "ICDBTRH",
1780 SPR_NOACCESS
, SPR_NOACCESS
,
1781 &spr_read_generic
, SPR_NOACCESS
,
1783 /* XXX : not implemented */
1784 spr_register(env
, SPR_BOOKE_ICDBTRL
, "ICDBTRL",
1785 SPR_NOACCESS
, SPR_NOACCESS
,
1786 &spr_read_generic
, SPR_NOACCESS
,
1788 /* XXX : not implemented */
1789 spr_register(env
, SPR_440_DBDR
, "DBDR",
1790 SPR_NOACCESS
, SPR_NOACCESS
,
1791 &spr_read_generic
, &spr_write_generic
,
1793 /* Processor control */
1794 spr_register(env
, SPR_4xx_CCR0
, "CCR0",
1795 SPR_NOACCESS
, SPR_NOACCESS
,
1796 &spr_read_generic
, &spr_write_generic
,
1798 spr_register(env
, SPR_440_RSTCFG
, "RSTCFG",
1799 SPR_NOACCESS
, SPR_NOACCESS
,
1800 &spr_read_generic
, SPR_NOACCESS
,
1802 /* Storage control */
1803 spr_register(env
, SPR_440_MMUCR
, "MMUCR",
1804 SPR_NOACCESS
, SPR_NOACCESS
,
1805 &spr_read_generic
, &spr_write_generic
,
1809 /* SPR shared between PowerPC 40x implementations */
1810 static void gen_spr_40x (CPUPPCState
*env
)
1813 /* not emulated, as Qemu do not emulate caches */
1814 spr_register(env
, SPR_40x_DCCR
, "DCCR",
1815 SPR_NOACCESS
, SPR_NOACCESS
,
1816 &spr_read_generic
, &spr_write_generic
,
1818 /* not emulated, as Qemu do not emulate caches */
1819 spr_register(env
, SPR_40x_ICCR
, "ICCR",
1820 SPR_NOACCESS
, SPR_NOACCESS
,
1821 &spr_read_generic
, &spr_write_generic
,
1823 /* not emulated, as Qemu do not emulate caches */
1824 spr_register(env
, SPR_BOOKE_ICDBDR
, "ICDBDR",
1825 SPR_NOACCESS
, SPR_NOACCESS
,
1826 &spr_read_generic
, SPR_NOACCESS
,
1829 spr_register(env
, SPR_40x_DEAR
, "DEAR",
1830 SPR_NOACCESS
, SPR_NOACCESS
,
1831 &spr_read_generic
, &spr_write_generic
,
1833 spr_register(env
, SPR_40x_ESR
, "ESR",
1834 SPR_NOACCESS
, SPR_NOACCESS
,
1835 &spr_read_generic
, &spr_write_generic
,
1837 spr_register(env
, SPR_40x_EVPR
, "EVPR",
1838 SPR_NOACCESS
, SPR_NOACCESS
,
1839 &spr_read_generic
, &spr_write_excp_prefix
,
1841 spr_register(env
, SPR_40x_SRR2
, "SRR2",
1842 &spr_read_generic
, &spr_write_generic
,
1843 &spr_read_generic
, &spr_write_generic
,
1845 spr_register(env
, SPR_40x_SRR3
, "SRR3",
1846 &spr_read_generic
, &spr_write_generic
,
1847 &spr_read_generic
, &spr_write_generic
,
1850 spr_register(env
, SPR_40x_PIT
, "PIT",
1851 SPR_NOACCESS
, SPR_NOACCESS
,
1852 &spr_read_40x_pit
, &spr_write_40x_pit
,
1854 spr_register(env
, SPR_40x_TCR
, "TCR",
1855 SPR_NOACCESS
, SPR_NOACCESS
,
1856 &spr_read_generic
, &spr_write_booke_tcr
,
1858 spr_register(env
, SPR_40x_TSR
, "TSR",
1859 SPR_NOACCESS
, SPR_NOACCESS
,
1860 &spr_read_generic
, &spr_write_booke_tsr
,
1864 /* SPR specific to PowerPC 405 implementation */
1865 static void gen_spr_405 (CPUPPCState
*env
)
1868 spr_register(env
, SPR_40x_PID
, "PID",
1869 SPR_NOACCESS
, SPR_NOACCESS
,
1870 &spr_read_generic
, &spr_write_generic
,
1872 spr_register(env
, SPR_4xx_CCR0
, "CCR0",
1873 SPR_NOACCESS
, SPR_NOACCESS
,
1874 &spr_read_generic
, &spr_write_generic
,
1876 /* Debug interface */
1877 /* XXX : not implemented */
1878 spr_register(env
, SPR_40x_DBCR0
, "DBCR0",
1879 SPR_NOACCESS
, SPR_NOACCESS
,
1880 &spr_read_generic
, &spr_write_40x_dbcr0
,
1882 /* XXX : not implemented */
1883 spr_register(env
, SPR_405_DBCR1
, "DBCR1",
1884 SPR_NOACCESS
, SPR_NOACCESS
,
1885 &spr_read_generic
, &spr_write_generic
,
1887 /* XXX : not implemented */
1888 spr_register(env
, SPR_40x_DBSR
, "DBSR",
1889 SPR_NOACCESS
, SPR_NOACCESS
,
1890 &spr_read_generic
, &spr_write_clear
,
1891 /* Last reset was system reset */
1893 /* XXX : not implemented */
1894 spr_register(env
, SPR_40x_DAC1
, "DAC1",
1895 SPR_NOACCESS
, SPR_NOACCESS
,
1896 &spr_read_generic
, &spr_write_generic
,
1898 spr_register(env
, SPR_40x_DAC2
, "DAC2",
1899 SPR_NOACCESS
, SPR_NOACCESS
,
1900 &spr_read_generic
, &spr_write_generic
,
1902 /* XXX : not implemented */
1903 spr_register(env
, SPR_405_DVC1
, "DVC1",
1904 SPR_NOACCESS
, SPR_NOACCESS
,
1905 &spr_read_generic
, &spr_write_generic
,
1907 /* XXX : not implemented */
1908 spr_register(env
, SPR_405_DVC2
, "DVC2",
1909 SPR_NOACCESS
, SPR_NOACCESS
,
1910 &spr_read_generic
, &spr_write_generic
,
1912 /* XXX : not implemented */
1913 spr_register(env
, SPR_40x_IAC1
, "IAC1",
1914 SPR_NOACCESS
, SPR_NOACCESS
,
1915 &spr_read_generic
, &spr_write_generic
,
1917 spr_register(env
, SPR_40x_IAC2
, "IAC2",
1918 SPR_NOACCESS
, SPR_NOACCESS
,
1919 &spr_read_generic
, &spr_write_generic
,
1921 /* XXX : not implemented */
1922 spr_register(env
, SPR_405_IAC3
, "IAC3",
1923 SPR_NOACCESS
, SPR_NOACCESS
,
1924 &spr_read_generic
, &spr_write_generic
,
1926 /* XXX : not implemented */
1927 spr_register(env
, SPR_405_IAC4
, "IAC4",
1928 SPR_NOACCESS
, SPR_NOACCESS
,
1929 &spr_read_generic
, &spr_write_generic
,
1931 /* Storage control */
1932 /* XXX: TODO: not implemented */
1933 spr_register(env
, SPR_405_SLER
, "SLER",
1934 SPR_NOACCESS
, SPR_NOACCESS
,
1935 &spr_read_generic
, &spr_write_40x_sler
,
1937 spr_register(env
, SPR_40x_ZPR
, "ZPR",
1938 SPR_NOACCESS
, SPR_NOACCESS
,
1939 &spr_read_generic
, &spr_write_generic
,
1941 /* XXX : not implemented */
1942 spr_register(env
, SPR_405_SU0R
, "SU0R",
1943 SPR_NOACCESS
, SPR_NOACCESS
,
1944 &spr_read_generic
, &spr_write_generic
,
1947 spr_register(env
, SPR_USPRG0
, "USPRG0",
1948 &spr_read_ureg
, SPR_NOACCESS
,
1949 &spr_read_ureg
, SPR_NOACCESS
,
1951 spr_register(env
, SPR_SPRG4
, "SPRG4",
1952 SPR_NOACCESS
, SPR_NOACCESS
,
1953 &spr_read_generic
, &spr_write_generic
,
1955 spr_register(env
, SPR_SPRG5
, "SPRG5",
1956 SPR_NOACCESS
, SPR_NOACCESS
,
1957 spr_read_generic
, &spr_write_generic
,
1959 spr_register(env
, SPR_SPRG6
, "SPRG6",
1960 SPR_NOACCESS
, SPR_NOACCESS
,
1961 spr_read_generic
, &spr_write_generic
,
1963 spr_register(env
, SPR_SPRG7
, "SPRG7",
1964 SPR_NOACCESS
, SPR_NOACCESS
,
1965 spr_read_generic
, &spr_write_generic
,
1967 gen_spr_usprgh(env
);
1970 /* SPR shared between PowerPC 401 & 403 implementations */
1971 static void gen_spr_401_403 (CPUPPCState
*env
)
1974 spr_register(env
, SPR_403_VTBL
, "TBL",
1975 &spr_read_tbl
, SPR_NOACCESS
,
1976 &spr_read_tbl
, SPR_NOACCESS
,
1978 spr_register(env
, SPR_403_TBL
, "TBL",
1979 SPR_NOACCESS
, SPR_NOACCESS
,
1980 SPR_NOACCESS
, &spr_write_tbl
,
1982 spr_register(env
, SPR_403_VTBU
, "TBU",
1983 &spr_read_tbu
, SPR_NOACCESS
,
1984 &spr_read_tbu
, SPR_NOACCESS
,
1986 spr_register(env
, SPR_403_TBU
, "TBU",
1987 SPR_NOACCESS
, SPR_NOACCESS
,
1988 SPR_NOACCESS
, &spr_write_tbu
,
1991 /* not emulated, as Qemu do not emulate caches */
1992 spr_register(env
, SPR_403_CDBCR
, "CDBCR",
1993 SPR_NOACCESS
, SPR_NOACCESS
,
1994 &spr_read_generic
, &spr_write_generic
,
1998 /* SPR specific to PowerPC 401 implementation */
1999 static void gen_spr_401 (CPUPPCState
*env
)
2001 /* Debug interface */
2002 /* XXX : not implemented */
2003 spr_register(env
, SPR_40x_DBCR0
, "DBCR",
2004 SPR_NOACCESS
, SPR_NOACCESS
,
2005 &spr_read_generic
, &spr_write_40x_dbcr0
,
2007 /* XXX : not implemented */
2008 spr_register(env
, SPR_40x_DBSR
, "DBSR",
2009 SPR_NOACCESS
, SPR_NOACCESS
,
2010 &spr_read_generic
, &spr_write_clear
,
2011 /* Last reset was system reset */
2013 /* XXX : not implemented */
2014 spr_register(env
, SPR_40x_DAC1
, "DAC",
2015 SPR_NOACCESS
, SPR_NOACCESS
,
2016 &spr_read_generic
, &spr_write_generic
,
2018 /* XXX : not implemented */
2019 spr_register(env
, SPR_40x_IAC1
, "IAC",
2020 SPR_NOACCESS
, SPR_NOACCESS
,
2021 &spr_read_generic
, &spr_write_generic
,
2023 /* Storage control */
2024 /* XXX: TODO: not implemented */
2025 spr_register(env
, SPR_405_SLER
, "SLER",
2026 SPR_NOACCESS
, SPR_NOACCESS
,
2027 &spr_read_generic
, &spr_write_40x_sler
,
2029 /* not emulated, as Qemu never does speculative access */
2030 spr_register(env
, SPR_40x_SGR
, "SGR",
2031 SPR_NOACCESS
, SPR_NOACCESS
,
2032 &spr_read_generic
, &spr_write_generic
,
2034 /* not emulated, as Qemu do not emulate caches */
2035 spr_register(env
, SPR_40x_DCWR
, "DCWR",
2036 SPR_NOACCESS
, SPR_NOACCESS
,
2037 &spr_read_generic
, &spr_write_generic
,
2041 static void gen_spr_401x2 (CPUPPCState
*env
)
2044 spr_register(env
, SPR_40x_PID
, "PID",
2045 SPR_NOACCESS
, SPR_NOACCESS
,
2046 &spr_read_generic
, &spr_write_generic
,
2048 spr_register(env
, SPR_40x_ZPR
, "ZPR",
2049 SPR_NOACCESS
, SPR_NOACCESS
,
2050 &spr_read_generic
, &spr_write_generic
,
2054 /* SPR specific to PowerPC 403 implementation */
2055 static void gen_spr_403 (CPUPPCState
*env
)
2057 /* Debug interface */
2058 /* XXX : not implemented */
2059 spr_register(env
, SPR_40x_DBCR0
, "DBCR0",
2060 SPR_NOACCESS
, SPR_NOACCESS
,
2061 &spr_read_generic
, &spr_write_40x_dbcr0
,
2063 /* XXX : not implemented */
2064 spr_register(env
, SPR_40x_DBSR
, "DBSR",
2065 SPR_NOACCESS
, SPR_NOACCESS
,
2066 &spr_read_generic
, &spr_write_clear
,
2067 /* Last reset was system reset */
2069 /* XXX : not implemented */
2070 spr_register(env
, SPR_40x_DAC1
, "DAC1",
2071 SPR_NOACCESS
, SPR_NOACCESS
,
2072 &spr_read_generic
, &spr_write_generic
,
2074 /* XXX : not implemented */
2075 spr_register(env
, SPR_40x_DAC2
, "DAC2",
2076 SPR_NOACCESS
, SPR_NOACCESS
,
2077 &spr_read_generic
, &spr_write_generic
,
2079 /* XXX : not implemented */
2080 spr_register(env
, SPR_40x_IAC1
, "IAC1",
2081 SPR_NOACCESS
, SPR_NOACCESS
,
2082 &spr_read_generic
, &spr_write_generic
,
2084 /* XXX : not implemented */
2085 spr_register(env
, SPR_40x_IAC2
, "IAC2",
2086 SPR_NOACCESS
, SPR_NOACCESS
,
2087 &spr_read_generic
, &spr_write_generic
,
2091 static void gen_spr_403_real (CPUPPCState
*env
)
2093 spr_register(env
, SPR_403_PBL1
, "PBL1",
2094 SPR_NOACCESS
, SPR_NOACCESS
,
2095 &spr_read_403_pbr
, &spr_write_403_pbr
,
2097 spr_register(env
, SPR_403_PBU1
, "PBU1",
2098 SPR_NOACCESS
, SPR_NOACCESS
,
2099 &spr_read_403_pbr
, &spr_write_403_pbr
,
2101 spr_register(env
, SPR_403_PBL2
, "PBL2",
2102 SPR_NOACCESS
, SPR_NOACCESS
,
2103 &spr_read_403_pbr
, &spr_write_403_pbr
,
2105 spr_register(env
, SPR_403_PBU2
, "PBU2",
2106 SPR_NOACCESS
, SPR_NOACCESS
,
2107 &spr_read_403_pbr
, &spr_write_403_pbr
,
2111 static void gen_spr_403_mmu (CPUPPCState
*env
)
2114 spr_register(env
, SPR_40x_PID
, "PID",
2115 SPR_NOACCESS
, SPR_NOACCESS
,
2116 &spr_read_generic
, &spr_write_generic
,
2118 spr_register(env
, SPR_40x_ZPR
, "ZPR",
2119 SPR_NOACCESS
, SPR_NOACCESS
,
2120 &spr_read_generic
, &spr_write_generic
,
2124 /* SPR specific to PowerPC compression coprocessor extension */
2125 static void gen_spr_compress (CPUPPCState
*env
)
2127 /* XXX : not implemented */
2128 spr_register(env
, SPR_401_SKR
, "SKR",
2129 SPR_NOACCESS
, SPR_NOACCESS
,
2130 &spr_read_generic
, &spr_write_generic
,
2134 #if defined (TARGET_PPC64)
2135 /* SPR specific to PowerPC 620 */
2136 static void gen_spr_620 (CPUPPCState
*env
)
2138 /* Processor identification */
2139 spr_register(env
, SPR_PIR
, "PIR",
2140 SPR_NOACCESS
, SPR_NOACCESS
,
2141 &spr_read_generic
, &spr_write_pir
,
2143 spr_register(env
, SPR_ASR
, "ASR",
2144 SPR_NOACCESS
, SPR_NOACCESS
,
2145 &spr_read_asr
, &spr_write_asr
,
2148 /* XXX : not implemented */
2149 spr_register(env
, SPR_IABR
, "IABR",
2150 SPR_NOACCESS
, SPR_NOACCESS
,
2151 &spr_read_generic
, &spr_write_generic
,
2153 /* XXX : not implemented */
2154 spr_register(env
, SPR_DABR
, "DABR",
2155 SPR_NOACCESS
, SPR_NOACCESS
,
2156 &spr_read_generic
, &spr_write_generic
,
2158 /* XXX : not implemented */
2159 spr_register(env
, SPR_SIAR
, "SIAR",
2160 SPR_NOACCESS
, SPR_NOACCESS
,
2161 &spr_read_generic
, SPR_NOACCESS
,
2163 /* XXX : not implemented */
2164 spr_register(env
, SPR_SDA
, "SDA",
2165 SPR_NOACCESS
, SPR_NOACCESS
,
2166 &spr_read_generic
, SPR_NOACCESS
,
2168 /* XXX : not implemented */
2169 spr_register(env
, SPR_620_PMC1R
, "PMC1",
2170 SPR_NOACCESS
, SPR_NOACCESS
,
2171 &spr_read_generic
, SPR_NOACCESS
,
2173 spr_register(env
, SPR_620_PMC1W
, "PMC1",
2174 SPR_NOACCESS
, SPR_NOACCESS
,
2175 SPR_NOACCESS
, &spr_write_generic
,
2177 /* XXX : not implemented */
2178 spr_register(env
, SPR_620_PMC2R
, "PMC2",
2179 SPR_NOACCESS
, SPR_NOACCESS
,
2180 &spr_read_generic
, SPR_NOACCESS
,
2182 spr_register(env
, SPR_620_PMC2W
, "PMC2",
2183 SPR_NOACCESS
, SPR_NOACCESS
,
2184 SPR_NOACCESS
, &spr_write_generic
,
2186 /* XXX : not implemented */
2187 spr_register(env
, SPR_620_MMCR0R
, "MMCR0",
2188 SPR_NOACCESS
, SPR_NOACCESS
,
2189 &spr_read_generic
, SPR_NOACCESS
,
2191 spr_register(env
, SPR_620_MMCR0W
, "MMCR0",
2192 SPR_NOACCESS
, SPR_NOACCESS
,
2193 SPR_NOACCESS
, &spr_write_generic
,
2195 /* External access control */
2196 /* XXX : not implemented */
2197 spr_register(env
, SPR_EAR
, "EAR",
2198 SPR_NOACCESS
, SPR_NOACCESS
,
2199 &spr_read_generic
, &spr_write_generic
,
2201 #if 0 // XXX: check this
2202 /* XXX : not implemented */
2203 spr_register(env
, SPR_620_PMR0
, "PMR0",
2204 SPR_NOACCESS
, SPR_NOACCESS
,
2205 &spr_read_generic
, &spr_write_generic
,
2207 /* XXX : not implemented */
2208 spr_register(env
, SPR_620_PMR1
, "PMR1",
2209 SPR_NOACCESS
, SPR_NOACCESS
,
2210 &spr_read_generic
, &spr_write_generic
,
2212 /* XXX : not implemented */
2213 spr_register(env
, SPR_620_PMR2
, "PMR2",
2214 SPR_NOACCESS
, SPR_NOACCESS
,
2215 &spr_read_generic
, &spr_write_generic
,
2217 /* XXX : not implemented */
2218 spr_register(env
, SPR_620_PMR3
, "PMR3",
2219 SPR_NOACCESS
, SPR_NOACCESS
,
2220 &spr_read_generic
, &spr_write_generic
,
2222 /* XXX : not implemented */
2223 spr_register(env
, SPR_620_PMR4
, "PMR4",
2224 SPR_NOACCESS
, SPR_NOACCESS
,
2225 &spr_read_generic
, &spr_write_generic
,
2227 /* XXX : not implemented */
2228 spr_register(env
, SPR_620_PMR5
, "PMR5",
2229 SPR_NOACCESS
, SPR_NOACCESS
,
2230 &spr_read_generic
, &spr_write_generic
,
2232 /* XXX : not implemented */
2233 spr_register(env
, SPR_620_PMR6
, "PMR6",
2234 SPR_NOACCESS
, SPR_NOACCESS
,
2235 &spr_read_generic
, &spr_write_generic
,
2237 /* XXX : not implemented */
2238 spr_register(env
, SPR_620_PMR7
, "PMR7",
2239 SPR_NOACCESS
, SPR_NOACCESS
,
2240 &spr_read_generic
, &spr_write_generic
,
2242 /* XXX : not implemented */
2243 spr_register(env
, SPR_620_PMR8
, "PMR8",
2244 SPR_NOACCESS
, SPR_NOACCESS
,
2245 &spr_read_generic
, &spr_write_generic
,
2247 /* XXX : not implemented */
2248 spr_register(env
, SPR_620_PMR9
, "PMR9",
2249 SPR_NOACCESS
, SPR_NOACCESS
,
2250 &spr_read_generic
, &spr_write_generic
,
2252 /* XXX : not implemented */
2253 spr_register(env
, SPR_620_PMRA
, "PMR10",
2254 SPR_NOACCESS
, SPR_NOACCESS
,
2255 &spr_read_generic
, &spr_write_generic
,
2257 /* XXX : not implemented */
2258 spr_register(env
, SPR_620_PMRB
, "PMR11",
2259 SPR_NOACCESS
, SPR_NOACCESS
,
2260 &spr_read_generic
, &spr_write_generic
,
2262 /* XXX : not implemented */
2263 spr_register(env
, SPR_620_PMRC
, "PMR12",
2264 SPR_NOACCESS
, SPR_NOACCESS
,
2265 &spr_read_generic
, &spr_write_generic
,
2267 /* XXX : not implemented */
2268 spr_register(env
, SPR_620_PMRD
, "PMR13",
2269 SPR_NOACCESS
, SPR_NOACCESS
,
2270 &spr_read_generic
, &spr_write_generic
,
2272 /* XXX : not implemented */
2273 spr_register(env
, SPR_620_PMRE
, "PMR14",
2274 SPR_NOACCESS
, SPR_NOACCESS
,
2275 &spr_read_generic
, &spr_write_generic
,
2277 /* XXX : not implemented */
2278 spr_register(env
, SPR_620_PMRF
, "PMR15",
2279 SPR_NOACCESS
, SPR_NOACCESS
,
2280 &spr_read_generic
, &spr_write_generic
,
2283 /* XXX : not implemented */
2284 spr_register(env
, SPR_620_BUSCSR
, "BUSCSR",
2285 SPR_NOACCESS
, SPR_NOACCESS
,
2286 &spr_read_generic
, &spr_write_generic
,
2288 /* XXX : not implemented */
2289 spr_register(env
, SPR_620_L2CR
, "L2CR",
2290 SPR_NOACCESS
, SPR_NOACCESS
,
2291 &spr_read_generic
, &spr_write_generic
,
2293 /* XXX : not implemented */
2294 spr_register(env
, SPR_620_L2SR
, "L2SR",
2295 SPR_NOACCESS
, SPR_NOACCESS
,
2296 &spr_read_generic
, &spr_write_generic
,
2299 #endif /* defined (TARGET_PPC64) */
2301 static void gen_spr_5xx_8xx (CPUPPCState
*env
)
2303 /* Exception processing */
2304 spr_register(env
, SPR_DSISR
, "DSISR",
2305 SPR_NOACCESS
, SPR_NOACCESS
,
2306 &spr_read_generic
, &spr_write_generic
,
2308 spr_register(env
, SPR_DAR
, "DAR",
2309 SPR_NOACCESS
, SPR_NOACCESS
,
2310 &spr_read_generic
, &spr_write_generic
,
2313 spr_register(env
, SPR_DECR
, "DECR",
2314 SPR_NOACCESS
, SPR_NOACCESS
,
2315 &spr_read_decr
, &spr_write_decr
,
2317 /* XXX : not implemented */
2318 spr_register(env
, SPR_MPC_EIE
, "EIE",
2319 SPR_NOACCESS
, SPR_NOACCESS
,
2320 &spr_read_generic
, &spr_write_generic
,
2322 /* XXX : not implemented */
2323 spr_register(env
, SPR_MPC_EID
, "EID",
2324 SPR_NOACCESS
, SPR_NOACCESS
,
2325 &spr_read_generic
, &spr_write_generic
,
2327 /* XXX : not implemented */
2328 spr_register(env
, SPR_MPC_NRI
, "NRI",
2329 SPR_NOACCESS
, SPR_NOACCESS
,
2330 &spr_read_generic
, &spr_write_generic
,
2332 /* XXX : not implemented */
2333 spr_register(env
, SPR_MPC_CMPA
, "CMPA",
2334 SPR_NOACCESS
, SPR_NOACCESS
,
2335 &spr_read_generic
, &spr_write_generic
,
2337 /* XXX : not implemented */
2338 spr_register(env
, SPR_MPC_CMPB
, "CMPB",
2339 SPR_NOACCESS
, SPR_NOACCESS
,
2340 &spr_read_generic
, &spr_write_generic
,
2342 /* XXX : not implemented */
2343 spr_register(env
, SPR_MPC_CMPC
, "CMPC",
2344 SPR_NOACCESS
, SPR_NOACCESS
,
2345 &spr_read_generic
, &spr_write_generic
,
2347 /* XXX : not implemented */
2348 spr_register(env
, SPR_MPC_CMPD
, "CMPD",
2349 SPR_NOACCESS
, SPR_NOACCESS
,
2350 &spr_read_generic
, &spr_write_generic
,
2352 /* XXX : not implemented */
2353 spr_register(env
, SPR_MPC_ECR
, "ECR",
2354 SPR_NOACCESS
, SPR_NOACCESS
,
2355 &spr_read_generic
, &spr_write_generic
,
2357 /* XXX : not implemented */
2358 spr_register(env
, SPR_MPC_DER
, "DER",
2359 SPR_NOACCESS
, SPR_NOACCESS
,
2360 &spr_read_generic
, &spr_write_generic
,
2362 /* XXX : not implemented */
2363 spr_register(env
, SPR_MPC_COUNTA
, "COUNTA",
2364 SPR_NOACCESS
, SPR_NOACCESS
,
2365 &spr_read_generic
, &spr_write_generic
,
2367 /* XXX : not implemented */
2368 spr_register(env
, SPR_MPC_COUNTB
, "COUNTB",
2369 SPR_NOACCESS
, SPR_NOACCESS
,
2370 &spr_read_generic
, &spr_write_generic
,
2372 /* XXX : not implemented */
2373 spr_register(env
, SPR_MPC_CMPE
, "CMPE",
2374 SPR_NOACCESS
, SPR_NOACCESS
,
2375 &spr_read_generic
, &spr_write_generic
,
2377 /* XXX : not implemented */
2378 spr_register(env
, SPR_MPC_CMPF
, "CMPF",
2379 SPR_NOACCESS
, SPR_NOACCESS
,
2380 &spr_read_generic
, &spr_write_generic
,
2382 /* XXX : not implemented */
2383 spr_register(env
, SPR_MPC_CMPG
, "CMPG",
2384 SPR_NOACCESS
, SPR_NOACCESS
,
2385 &spr_read_generic
, &spr_write_generic
,
2387 /* XXX : not implemented */
2388 spr_register(env
, SPR_MPC_CMPH
, "CMPH",
2389 SPR_NOACCESS
, SPR_NOACCESS
,
2390 &spr_read_generic
, &spr_write_generic
,
2392 /* XXX : not implemented */
2393 spr_register(env
, SPR_MPC_LCTRL1
, "LCTRL1",
2394 SPR_NOACCESS
, SPR_NOACCESS
,
2395 &spr_read_generic
, &spr_write_generic
,
2397 /* XXX : not implemented */
2398 spr_register(env
, SPR_MPC_LCTRL2
, "LCTRL2",
2399 SPR_NOACCESS
, SPR_NOACCESS
,
2400 &spr_read_generic
, &spr_write_generic
,
2402 /* XXX : not implemented */
2403 spr_register(env
, SPR_MPC_BAR
, "BAR",
2404 SPR_NOACCESS
, SPR_NOACCESS
,
2405 &spr_read_generic
, &spr_write_generic
,
2407 /* XXX : not implemented */
2408 spr_register(env
, SPR_MPC_DPDR
, "DPDR",
2409 SPR_NOACCESS
, SPR_NOACCESS
,
2410 &spr_read_generic
, &spr_write_generic
,
2412 /* XXX : not implemented */
2413 spr_register(env
, SPR_MPC_IMMR
, "IMMR",
2414 SPR_NOACCESS
, SPR_NOACCESS
,
2415 &spr_read_generic
, &spr_write_generic
,
2419 static void gen_spr_5xx (CPUPPCState
*env
)
2421 /* XXX : not implemented */
2422 spr_register(env
, SPR_RCPU_MI_GRA
, "MI_GRA",
2423 SPR_NOACCESS
, SPR_NOACCESS
,
2424 &spr_read_generic
, &spr_write_generic
,
2426 /* XXX : not implemented */
2427 spr_register(env
, SPR_RCPU_L2U_GRA
, "L2U_GRA",
2428 SPR_NOACCESS
, SPR_NOACCESS
,
2429 &spr_read_generic
, &spr_write_generic
,
2431 /* XXX : not implemented */
2432 spr_register(env
, SPR_RPCU_BBCMCR
, "L2U_BBCMCR",
2433 SPR_NOACCESS
, SPR_NOACCESS
,
2434 &spr_read_generic
, &spr_write_generic
,
2436 /* XXX : not implemented */
2437 spr_register(env
, SPR_RCPU_L2U_MCR
, "L2U_MCR",
2438 SPR_NOACCESS
, SPR_NOACCESS
,
2439 &spr_read_generic
, &spr_write_generic
,
2441 /* XXX : not implemented */
2442 spr_register(env
, SPR_RCPU_MI_RBA0
, "MI_RBA0",
2443 SPR_NOACCESS
, SPR_NOACCESS
,
2444 &spr_read_generic
, &spr_write_generic
,
2446 /* XXX : not implemented */
2447 spr_register(env
, SPR_RCPU_MI_RBA1
, "MI_RBA1",
2448 SPR_NOACCESS
, SPR_NOACCESS
,
2449 &spr_read_generic
, &spr_write_generic
,
2451 /* XXX : not implemented */
2452 spr_register(env
, SPR_RCPU_MI_RBA2
, "MI_RBA2",
2453 SPR_NOACCESS
, SPR_NOACCESS
,
2454 &spr_read_generic
, &spr_write_generic
,
2456 /* XXX : not implemented */
2457 spr_register(env
, SPR_RCPU_MI_RBA3
, "MI_RBA3",
2458 SPR_NOACCESS
, SPR_NOACCESS
,
2459 &spr_read_generic
, &spr_write_generic
,
2461 /* XXX : not implemented */
2462 spr_register(env
, SPR_RCPU_L2U_RBA0
, "L2U_RBA0",
2463 SPR_NOACCESS
, SPR_NOACCESS
,
2464 &spr_read_generic
, &spr_write_generic
,
2466 /* XXX : not implemented */
2467 spr_register(env
, SPR_RCPU_L2U_RBA1
, "L2U_RBA1",
2468 SPR_NOACCESS
, SPR_NOACCESS
,
2469 &spr_read_generic
, &spr_write_generic
,
2471 /* XXX : not implemented */
2472 spr_register(env
, SPR_RCPU_L2U_RBA2
, "L2U_RBA2",
2473 SPR_NOACCESS
, SPR_NOACCESS
,
2474 &spr_read_generic
, &spr_write_generic
,
2476 /* XXX : not implemented */
2477 spr_register(env
, SPR_RCPU_L2U_RBA3
, "L2U_RBA3",
2478 SPR_NOACCESS
, SPR_NOACCESS
,
2479 &spr_read_generic
, &spr_write_generic
,
2481 /* XXX : not implemented */
2482 spr_register(env
, SPR_RCPU_MI_RA0
, "MI_RA0",
2483 SPR_NOACCESS
, SPR_NOACCESS
,
2484 &spr_read_generic
, &spr_write_generic
,
2486 /* XXX : not implemented */
2487 spr_register(env
, SPR_RCPU_MI_RA1
, "MI_RA1",
2488 SPR_NOACCESS
, SPR_NOACCESS
,
2489 &spr_read_generic
, &spr_write_generic
,
2491 /* XXX : not implemented */
2492 spr_register(env
, SPR_RCPU_MI_RA2
, "MI_RA2",
2493 SPR_NOACCESS
, SPR_NOACCESS
,
2494 &spr_read_generic
, &spr_write_generic
,
2496 /* XXX : not implemented */
2497 spr_register(env
, SPR_RCPU_MI_RA3
, "MI_RA3",
2498 SPR_NOACCESS
, SPR_NOACCESS
,
2499 &spr_read_generic
, &spr_write_generic
,
2501 /* XXX : not implemented */
2502 spr_register(env
, SPR_RCPU_L2U_RA0
, "L2U_RA0",
2503 SPR_NOACCESS
, SPR_NOACCESS
,
2504 &spr_read_generic
, &spr_write_generic
,
2506 /* XXX : not implemented */
2507 spr_register(env
, SPR_RCPU_L2U_RA1
, "L2U_RA1",
2508 SPR_NOACCESS
, SPR_NOACCESS
,
2509 &spr_read_generic
, &spr_write_generic
,
2511 /* XXX : not implemented */
2512 spr_register(env
, SPR_RCPU_L2U_RA2
, "L2U_RA2",
2513 SPR_NOACCESS
, SPR_NOACCESS
,
2514 &spr_read_generic
, &spr_write_generic
,
2516 /* XXX : not implemented */
2517 spr_register(env
, SPR_RCPU_L2U_RA3
, "L2U_RA3",
2518 SPR_NOACCESS
, SPR_NOACCESS
,
2519 &spr_read_generic
, &spr_write_generic
,
2521 /* XXX : not implemented */
2522 spr_register(env
, SPR_RCPU_FPECR
, "FPECR",
2523 SPR_NOACCESS
, SPR_NOACCESS
,
2524 &spr_read_generic
, &spr_write_generic
,
2528 static void gen_spr_8xx (CPUPPCState
*env
)
2530 /* XXX : not implemented */
2531 spr_register(env
, SPR_MPC_IC_CST
, "IC_CST",
2532 SPR_NOACCESS
, SPR_NOACCESS
,
2533 &spr_read_generic
, &spr_write_generic
,
2535 /* XXX : not implemented */
2536 spr_register(env
, SPR_MPC_IC_ADR
, "IC_ADR",
2537 SPR_NOACCESS
, SPR_NOACCESS
,
2538 &spr_read_generic
, &spr_write_generic
,
2540 /* XXX : not implemented */
2541 spr_register(env
, SPR_MPC_IC_DAT
, "IC_DAT",
2542 SPR_NOACCESS
, SPR_NOACCESS
,
2543 &spr_read_generic
, &spr_write_generic
,
2545 /* XXX : not implemented */
2546 spr_register(env
, SPR_MPC_DC_CST
, "DC_CST",
2547 SPR_NOACCESS
, SPR_NOACCESS
,
2548 &spr_read_generic
, &spr_write_generic
,
2550 /* XXX : not implemented */
2551 spr_register(env
, SPR_MPC_DC_ADR
, "DC_ADR",
2552 SPR_NOACCESS
, SPR_NOACCESS
,
2553 &spr_read_generic
, &spr_write_generic
,
2555 /* XXX : not implemented */
2556 spr_register(env
, SPR_MPC_DC_DAT
, "DC_DAT",
2557 SPR_NOACCESS
, SPR_NOACCESS
,
2558 &spr_read_generic
, &spr_write_generic
,
2560 /* XXX : not implemented */
2561 spr_register(env
, SPR_MPC_MI_CTR
, "MI_CTR",
2562 SPR_NOACCESS
, SPR_NOACCESS
,
2563 &spr_read_generic
, &spr_write_generic
,
2565 /* XXX : not implemented */
2566 spr_register(env
, SPR_MPC_MI_AP
, "MI_AP",
2567 SPR_NOACCESS
, SPR_NOACCESS
,
2568 &spr_read_generic
, &spr_write_generic
,
2570 /* XXX : not implemented */
2571 spr_register(env
, SPR_MPC_MI_EPN
, "MI_EPN",
2572 SPR_NOACCESS
, SPR_NOACCESS
,
2573 &spr_read_generic
, &spr_write_generic
,
2575 /* XXX : not implemented */
2576 spr_register(env
, SPR_MPC_MI_TWC
, "MI_TWC",
2577 SPR_NOACCESS
, SPR_NOACCESS
,
2578 &spr_read_generic
, &spr_write_generic
,
2580 /* XXX : not implemented */
2581 spr_register(env
, SPR_MPC_MI_RPN
, "MI_RPN",
2582 SPR_NOACCESS
, SPR_NOACCESS
,
2583 &spr_read_generic
, &spr_write_generic
,
2585 /* XXX : not implemented */
2586 spr_register(env
, SPR_MPC_MI_DBCAM
, "MI_DBCAM",
2587 SPR_NOACCESS
, SPR_NOACCESS
,
2588 &spr_read_generic
, &spr_write_generic
,
2590 /* XXX : not implemented */
2591 spr_register(env
, SPR_MPC_MI_DBRAM0
, "MI_DBRAM0",
2592 SPR_NOACCESS
, SPR_NOACCESS
,
2593 &spr_read_generic
, &spr_write_generic
,
2595 /* XXX : not implemented */
2596 spr_register(env
, SPR_MPC_MI_DBRAM1
, "MI_DBRAM1",
2597 SPR_NOACCESS
, SPR_NOACCESS
,
2598 &spr_read_generic
, &spr_write_generic
,
2600 /* XXX : not implemented */
2601 spr_register(env
, SPR_MPC_MD_CTR
, "MD_CTR",
2602 SPR_NOACCESS
, SPR_NOACCESS
,
2603 &spr_read_generic
, &spr_write_generic
,
2605 /* XXX : not implemented */
2606 spr_register(env
, SPR_MPC_MD_CASID
, "MD_CASID",
2607 SPR_NOACCESS
, SPR_NOACCESS
,
2608 &spr_read_generic
, &spr_write_generic
,
2610 /* XXX : not implemented */
2611 spr_register(env
, SPR_MPC_MD_AP
, "MD_AP",
2612 SPR_NOACCESS
, SPR_NOACCESS
,
2613 &spr_read_generic
, &spr_write_generic
,
2615 /* XXX : not implemented */
2616 spr_register(env
, SPR_MPC_MD_EPN
, "MD_EPN",
2617 SPR_NOACCESS
, SPR_NOACCESS
,
2618 &spr_read_generic
, &spr_write_generic
,
2620 /* XXX : not implemented */
2621 spr_register(env
, SPR_MPC_MD_TWB
, "MD_TWB",
2622 SPR_NOACCESS
, SPR_NOACCESS
,
2623 &spr_read_generic
, &spr_write_generic
,
2625 /* XXX : not implemented */
2626 spr_register(env
, SPR_MPC_MD_TWC
, "MD_TWC",
2627 SPR_NOACCESS
, SPR_NOACCESS
,
2628 &spr_read_generic
, &spr_write_generic
,
2630 /* XXX : not implemented */
2631 spr_register(env
, SPR_MPC_MD_RPN
, "MD_RPN",
2632 SPR_NOACCESS
, SPR_NOACCESS
,
2633 &spr_read_generic
, &spr_write_generic
,
2635 /* XXX : not implemented */
2636 spr_register(env
, SPR_MPC_MD_TW
, "MD_TW",
2637 SPR_NOACCESS
, SPR_NOACCESS
,
2638 &spr_read_generic
, &spr_write_generic
,
2640 /* XXX : not implemented */
2641 spr_register(env
, SPR_MPC_MD_DBCAM
, "MD_DBCAM",
2642 SPR_NOACCESS
, SPR_NOACCESS
,
2643 &spr_read_generic
, &spr_write_generic
,
2645 /* XXX : not implemented */
2646 spr_register(env
, SPR_MPC_MD_DBRAM0
, "MD_DBRAM0",
2647 SPR_NOACCESS
, SPR_NOACCESS
,
2648 &spr_read_generic
, &spr_write_generic
,
2650 /* XXX : not implemented */
2651 spr_register(env
, SPR_MPC_MD_DBRAM1
, "MD_DBRAM1",
2652 SPR_NOACCESS
, SPR_NOACCESS
,
2653 &spr_read_generic
, &spr_write_generic
,
2659 * AMR => SPR 29 (Power 2.04)
2660 * CTRL => SPR 136 (Power 2.04)
2661 * CTRL => SPR 152 (Power 2.04)
2662 * SCOMC => SPR 276 (64 bits ?)
2663 * SCOMD => SPR 277 (64 bits ?)
2664 * TBU40 => SPR 286 (Power 2.04 hypv)
2665 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2666 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2667 * HDSISR => SPR 306 (Power 2.04 hypv)
2668 * HDAR => SPR 307 (Power 2.04 hypv)
2669 * PURR => SPR 309 (Power 2.04 hypv)
2670 * HDEC => SPR 310 (Power 2.04 hypv)
2671 * HIOR => SPR 311 (hypv)
2672 * RMOR => SPR 312 (970)
2673 * HRMOR => SPR 313 (Power 2.04 hypv)
2674 * HSRR0 => SPR 314 (Power 2.04 hypv)
2675 * HSRR1 => SPR 315 (Power 2.04 hypv)
2676 * LPCR => SPR 316 (970)
2677 * LPIDR => SPR 317 (970)
2678 * EPR => SPR 702 (Power 2.04 emb)
2679 * perf => 768-783 (Power 2.04)
2680 * perf => 784-799 (Power 2.04)
2681 * PPR => SPR 896 (Power 2.04)
2682 * EPLC => SPR 947 (Power 2.04 emb)
2683 * EPSC => SPR 948 (Power 2.04 emb)
2684 * DABRX => 1015 (Power 2.04 hypv)
2685 * FPECR => SPR 1022 (?)
2686 * ... and more (thermal management, performance counters, ...)
2689 /*****************************************************************************/
2690 /* Exception vectors models */
2691 static void init_excp_4xx_real (CPUPPCState
*env
)
2693 #if !defined(CONFIG_USER_ONLY)
2694 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000100;
2695 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2696 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2697 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2698 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2699 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2700 env
->excp_vectors
[POWERPC_EXCP_PIT
] = 0x00001000;
2701 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00001010;
2702 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00001020;
2703 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00002000;
2704 env
->hreset_excp_prefix
= 0x00000000UL
;
2705 env
->ivor_mask
= 0x0000FFF0UL
;
2706 env
->ivpr_mask
= 0xFFFF0000UL
;
2707 /* Hardware reset vector */
2708 env
->hreset_vector
= 0xFFFFFFFCUL
;
2712 static void init_excp_4xx_softmmu (CPUPPCState
*env
)
2714 #if !defined(CONFIG_USER_ONLY)
2715 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000100;
2716 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2717 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2718 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2719 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2720 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2721 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2722 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2723 env
->excp_vectors
[POWERPC_EXCP_PIT
] = 0x00001000;
2724 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00001010;
2725 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00001020;
2726 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00001100;
2727 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00001200;
2728 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00002000;
2729 env
->hreset_excp_prefix
= 0x00000000UL
;
2730 env
->ivor_mask
= 0x0000FFF0UL
;
2731 env
->ivpr_mask
= 0xFFFF0000UL
;
2732 /* Hardware reset vector */
2733 env
->hreset_vector
= 0xFFFFFFFCUL
;
2737 static void init_excp_MPC5xx (CPUPPCState
*env
)
2739 #if !defined(CONFIG_USER_ONLY)
2740 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2741 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2742 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2743 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2744 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2745 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000900;
2746 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2747 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2748 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2749 env
->excp_vectors
[POWERPC_EXCP_FPA
] = 0x00000E00;
2750 env
->excp_vectors
[POWERPC_EXCP_EMUL
] = 0x00001000;
2751 env
->excp_vectors
[POWERPC_EXCP_DABR
] = 0x00001C00;
2752 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001C00;
2753 env
->excp_vectors
[POWERPC_EXCP_MEXTBR
] = 0x00001E00;
2754 env
->excp_vectors
[POWERPC_EXCP_NMEXTBR
] = 0x00001F00;
2755 env
->hreset_excp_prefix
= 0x00000000UL
;
2756 env
->ivor_mask
= 0x0000FFF0UL
;
2757 env
->ivpr_mask
= 0xFFFF0000UL
;
2758 /* Hardware reset vector */
2759 env
->hreset_vector
= 0xFFFFFFFCUL
;
2763 static void init_excp_MPC8xx (CPUPPCState
*env
)
2765 #if !defined(CONFIG_USER_ONLY)
2766 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2767 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2768 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2769 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2770 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2771 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2772 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2773 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000900;
2774 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2775 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2776 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2777 env
->excp_vectors
[POWERPC_EXCP_FPA
] = 0x00000E00;
2778 env
->excp_vectors
[POWERPC_EXCP_EMUL
] = 0x00001000;
2779 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00001100;
2780 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00001200;
2781 env
->excp_vectors
[POWERPC_EXCP_ITLBE
] = 0x00001300;
2782 env
->excp_vectors
[POWERPC_EXCP_DTLBE
] = 0x00001400;
2783 env
->excp_vectors
[POWERPC_EXCP_DABR
] = 0x00001C00;
2784 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001C00;
2785 env
->excp_vectors
[POWERPC_EXCP_MEXTBR
] = 0x00001E00;
2786 env
->excp_vectors
[POWERPC_EXCP_NMEXTBR
] = 0x00001F00;
2787 env
->hreset_excp_prefix
= 0x00000000UL
;
2788 env
->ivor_mask
= 0x0000FFF0UL
;
2789 env
->ivpr_mask
= 0xFFFF0000UL
;
2790 /* Hardware reset vector */
2791 env
->hreset_vector
= 0xFFFFFFFCUL
;
2795 static void init_excp_G2 (CPUPPCState
*env
)
2797 #if !defined(CONFIG_USER_ONLY)
2798 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2799 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2800 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2801 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2802 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2803 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2804 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2805 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2806 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2807 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000A00;
2808 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2809 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2810 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2811 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2812 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2813 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2814 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2815 env
->hreset_excp_prefix
= 0x00000000UL
;
2816 /* Hardware reset vector */
2817 env
->hreset_vector
= 0xFFFFFFFCUL
;
2821 static void init_excp_e200 (CPUPPCState
*env
)
2823 #if !defined(CONFIG_USER_ONLY)
2824 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000FFC;
2825 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000000;
2826 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000000;
2827 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000000;
2828 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000000;
2829 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000000;
2830 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000000;
2831 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000000;
2832 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000000;
2833 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000000;
2834 env
->excp_vectors
[POWERPC_EXCP_APU
] = 0x00000000;
2835 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000000;
2836 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00000000;
2837 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00000000;
2838 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00000000;
2839 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00000000;
2840 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00000000;
2841 env
->excp_vectors
[POWERPC_EXCP_SPEU
] = 0x00000000;
2842 env
->excp_vectors
[POWERPC_EXCP_EFPDI
] = 0x00000000;
2843 env
->excp_vectors
[POWERPC_EXCP_EFPRI
] = 0x00000000;
2844 env
->hreset_excp_prefix
= 0x00000000UL
;
2845 env
->ivor_mask
= 0x0000FFF7UL
;
2846 env
->ivpr_mask
= 0xFFFF0000UL
;
2847 /* Hardware reset vector */
2848 env
->hreset_vector
= 0xFFFFFFFCUL
;
2852 static void init_excp_BookE (CPUPPCState
*env
)
2854 #if !defined(CONFIG_USER_ONLY)
2855 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000000;
2856 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000000;
2857 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000000;
2858 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000000;
2859 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000000;
2860 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000000;
2861 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000000;
2862 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000000;
2863 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000000;
2864 env
->excp_vectors
[POWERPC_EXCP_APU
] = 0x00000000;
2865 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000000;
2866 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00000000;
2867 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00000000;
2868 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00000000;
2869 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00000000;
2870 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00000000;
2871 env
->hreset_excp_prefix
= 0x00000000UL
;
2872 env
->ivor_mask
= 0x0000FFE0UL
;
2873 env
->ivpr_mask
= 0xFFFF0000UL
;
2874 /* Hardware reset vector */
2875 env
->hreset_vector
= 0xFFFFFFFCUL
;
2879 static void init_excp_601 (CPUPPCState
*env
)
2881 #if !defined(CONFIG_USER_ONLY)
2882 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2883 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2884 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2885 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2886 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2887 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2888 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2889 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2890 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2891 env
->excp_vectors
[POWERPC_EXCP_IO
] = 0x00000A00;
2892 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2893 env
->excp_vectors
[POWERPC_EXCP_RUNM
] = 0x00002000;
2894 env
->hreset_excp_prefix
= 0xFFF00000UL
;
2895 /* Hardware reset vector */
2896 env
->hreset_vector
= 0x00000100UL
;
2900 static void init_excp_602 (CPUPPCState
*env
)
2902 #if !defined(CONFIG_USER_ONLY)
2903 /* XXX: exception prefix has a special behavior on 602 */
2904 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2905 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2906 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2907 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2908 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2909 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2910 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2911 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2912 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2913 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2914 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2915 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2916 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2917 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2918 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2919 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2920 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00001500;
2921 env
->excp_vectors
[POWERPC_EXCP_EMUL
] = 0x00001600;
2922 env
->hreset_excp_prefix
= 0xFFF00000UL
;
2923 /* Hardware reset vector */
2924 env
->hreset_vector
= 0xFFFFFFFCUL
;
2928 static void init_excp_603 (CPUPPCState
*env
)
2930 #if !defined(CONFIG_USER_ONLY)
2931 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2932 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2933 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2934 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2935 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2936 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2937 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2938 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2939 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2940 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2941 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2942 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2943 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2944 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2945 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2946 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2947 env
->hreset_excp_prefix
= 0x00000000UL
;
2948 /* Hardware reset vector */
2949 env
->hreset_vector
= 0xFFFFFFFCUL
;
2953 static void init_excp_604 (CPUPPCState
*env
)
2955 #if !defined(CONFIG_USER_ONLY)
2956 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2957 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2958 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2959 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2960 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2961 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2962 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2963 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2964 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2965 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2966 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2967 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2968 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2969 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2970 env
->hreset_excp_prefix
= 0xFFF00000UL
;
2971 /* Hardware reset vector */
2972 env
->hreset_vector
= 0x00000100UL
;
2976 #if defined(TARGET_PPC64)
2977 static void init_excp_620 (CPUPPCState
*env
)
2979 #if !defined(CONFIG_USER_ONLY)
2980 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2981 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2982 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2983 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2984 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2985 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2986 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2987 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2988 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2989 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2990 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2991 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2992 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2993 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2994 env
->hreset_excp_prefix
= 0xFFF00000UL
;
2995 /* Hardware reset vector */
2996 env
->hreset_vector
= 0x0000000000000100ULL
;
2999 #endif /* defined(TARGET_PPC64) */
3001 static void init_excp_7x0 (CPUPPCState
*env
)
3003 #if !defined(CONFIG_USER_ONLY)
3004 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
3005 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
3006 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
3007 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
3008 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
3009 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
3010 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
3011 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
3012 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
3013 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
3014 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
3015 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
3016 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
3017 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
3018 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
3019 env
->hreset_excp_prefix
= 0x00000000UL
;
3020 /* Hardware reset vector */
3021 env
->hreset_vector
= 0xFFFFFFFCUL
;
3025 static void init_excp_750cl (CPUPPCState
*env
)
3027 #if !defined(CONFIG_USER_ONLY)
3028 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
3029 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
3030 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
3031 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
3032 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
3033 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
3034 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
3035 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
3036 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
3037 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
3038 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
3039 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
3040 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
3041 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
3042 env
->hreset_excp_prefix
= 0x00000000UL
;
3043 /* Hardware reset vector */
3044 env
->hreset_vector
= 0xFFFFFFFCUL
;
3048 static void init_excp_750cx (CPUPPCState
*env
)
3050 #if !defined(CONFIG_USER_ONLY)
3051 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
3052 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
3053 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
3054 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
3055 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
3056 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
3057 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
3058 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
3059 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
3060 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
3061 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
3062 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
3063 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
3064 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
3065 env
->hreset_excp_prefix
= 0x00000000UL
;
3066 /* Hardware reset vector */
3067 env
->hreset_vector
= 0xFFFFFFFCUL
;
3071 /* XXX: Check if this is correct */
3072 static void init_excp_7x5 (CPUPPCState
*env
)
3074 #if !defined(CONFIG_USER_ONLY)
3075 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
3076 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
3077 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
3078 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
3079 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
3080 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
3081 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
3082 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
3083 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
3084 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
3085 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
3086 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
3087 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
3088 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
3089 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
3090 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
3091 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
3092 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
3093 env
->hreset_excp_prefix
= 0x00000000UL
;
3094 /* Hardware reset vector */
3095 env
->hreset_vector
= 0xFFFFFFFCUL
;
3099 static void init_excp_7400 (CPUPPCState
*env
)
3101 #if !defined(CONFIG_USER_ONLY)
3102 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
3103 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
3104 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
3105 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
3106 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
3107 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
3108 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
3109 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
3110 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
3111 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
3112 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
3113 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
3114 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
3115 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
3116 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
3117 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001600;
3118 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
3119 env
->hreset_excp_prefix
= 0x00000000UL
;
3120 /* Hardware reset vector */
3121 env
->hreset_vector
= 0xFFFFFFFCUL
;
3125 static void init_excp_7450 (CPUPPCState
*env
)
3127 #if !defined(CONFIG_USER_ONLY)
3128 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
3129 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
3130 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
3131 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
3132 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
3133 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
3134 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
3135 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
3136 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
3137 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
3138 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
3139 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
3140 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
3141 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
3142 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
3143 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
3144 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
3145 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
3146 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001600;
3147 env
->hreset_excp_prefix
= 0x00000000UL
;
3148 /* Hardware reset vector */
3149 env
->hreset_vector
= 0xFFFFFFFCUL
;
3153 #if defined (TARGET_PPC64)
3154 static void init_excp_970 (CPUPPCState
*env
)
3156 #if !defined(CONFIG_USER_ONLY)
3157 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
3158 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
3159 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
3160 env
->excp_vectors
[POWERPC_EXCP_DSEG
] = 0x00000380;
3161 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
3162 env
->excp_vectors
[POWERPC_EXCP_ISEG
] = 0x00000480;
3163 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
3164 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
3165 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
3166 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
3167 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
3168 env
->excp_vectors
[POWERPC_EXCP_HDECR
] = 0x00000980;
3169 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
3170 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
3171 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
3172 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
3173 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
3174 env
->excp_vectors
[POWERPC_EXCP_MAINT
] = 0x00001600;
3175 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001700;
3176 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001800;
3177 env
->hreset_excp_prefix
= 0x00000000FFF00000ULL
;
3178 /* Hardware reset vector */
3179 env
->hreset_vector
= 0x0000000000000100ULL
;
3183 static void init_excp_POWER7 (CPUPPCState
*env
)
3185 #if !defined(CONFIG_USER_ONLY)
3186 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
3187 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
3188 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
3189 env
->excp_vectors
[POWERPC_EXCP_DSEG
] = 0x00000380;
3190 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
3191 env
->excp_vectors
[POWERPC_EXCP_ISEG
] = 0x00000480;
3192 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
3193 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
3194 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
3195 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
3196 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
3197 env
->excp_vectors
[POWERPC_EXCP_HDECR
] = 0x00000980;
3198 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
3199 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
3200 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
3201 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
3202 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
3203 env
->excp_vectors
[POWERPC_EXCP_MAINT
] = 0x00001600;
3204 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001700;
3205 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001800;
3206 env
->hreset_excp_prefix
= 0;
3207 /* Hardware reset vector */
3208 env
->hreset_vector
= 0x0000000000000100ULL
;
3213 /*****************************************************************************/
3214 /* Power management enable checks */
3215 static int check_pow_none (CPUPPCState
*env
)
3220 static int check_pow_nocheck (CPUPPCState
*env
)
3225 static int check_pow_hid0 (CPUPPCState
*env
)
3227 if (env
->spr
[SPR_HID0
] & 0x00E00000)
3233 static int check_pow_hid0_74xx (CPUPPCState
*env
)
3235 if (env
->spr
[SPR_HID0
] & 0x00600000)
3241 /*****************************************************************************/
3242 /* PowerPC implementations definitions */
3245 #define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3246 PPC_WRTEE | PPC_DCR | \
3247 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3249 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3250 PPC_4xx_COMMON | PPC_40x_EXCP)
3251 #define POWERPC_INSNS2_401 (PPC_NONE)
3252 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
3253 #define POWERPC_MMU_401 (POWERPC_MMU_REAL)
3254 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3255 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
3256 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
3257 #define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3258 POWERPC_FLAG_BUS_CLK)
3259 #define check_pow_401 check_pow_nocheck
3261 static void init_proc_401 (CPUPPCState
*env
)
3264 gen_spr_401_403(env
);
3266 init_excp_4xx_real(env
);
3267 env
->dcache_line_size
= 32;
3268 env
->icache_line_size
= 32;
3269 /* Allocate hardware IRQ controller */
3270 ppc40x_irq_init(env
);
3272 SET_FIT_PERIOD(12, 16, 20, 24);
3273 SET_WDT_PERIOD(16, 20, 24, 28);
3277 #define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3278 PPC_DCR | PPC_WRTEE | \
3279 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3280 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3281 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3282 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3283 PPC_4xx_COMMON | PPC_40x_EXCP)
3284 #define POWERPC_INSNS2_401x2 (PPC_NONE)
3285 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3286 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3287 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3288 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
3289 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
3290 #define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3291 POWERPC_FLAG_BUS_CLK)
3292 #define check_pow_401x2 check_pow_nocheck
3294 static void init_proc_401x2 (CPUPPCState
*env
)
3297 gen_spr_401_403(env
);
3299 gen_spr_compress(env
);
3300 /* Memory management */
3301 #if !defined(CONFIG_USER_ONLY)
3305 env
->tlb_type
= TLB_EMB
;
3307 init_excp_4xx_softmmu(env
);
3308 env
->dcache_line_size
= 32;
3309 env
->icache_line_size
= 32;
3310 /* Allocate hardware IRQ controller */
3311 ppc40x_irq_init(env
);
3313 SET_FIT_PERIOD(12, 16, 20, 24);
3314 SET_WDT_PERIOD(16, 20, 24, 28);
3318 #define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3319 PPC_DCR | PPC_WRTEE | \
3320 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3321 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3322 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3323 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3324 PPC_4xx_COMMON | PPC_40x_EXCP)
3325 #define POWERPC_INSNS2_401x3 (PPC_NONE)
3326 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3327 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3328 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3329 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
3330 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
3331 #define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3332 POWERPC_FLAG_BUS_CLK)
3333 #define check_pow_401x3 check_pow_nocheck
3335 __attribute__ (( unused
))
3336 static void init_proc_401x3 (CPUPPCState
*env
)
3339 gen_spr_401_403(env
);
3342 gen_spr_compress(env
);
3343 init_excp_4xx_softmmu(env
);
3344 env
->dcache_line_size
= 32;
3345 env
->icache_line_size
= 32;
3346 /* Allocate hardware IRQ controller */
3347 ppc40x_irq_init(env
);
3349 SET_FIT_PERIOD(12, 16, 20, 24);
3350 SET_WDT_PERIOD(16, 20, 24, 28);
3354 #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3355 PPC_DCR | PPC_WRTEE | \
3356 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3357 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3358 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3359 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3360 PPC_4xx_COMMON | PPC_40x_EXCP)
3361 #define POWERPC_INSNS2_IOP480 (PPC_NONE)
3362 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3363 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3364 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3365 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3366 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
3367 #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3368 POWERPC_FLAG_BUS_CLK)
3369 #define check_pow_IOP480 check_pow_nocheck
3371 static void init_proc_IOP480 (CPUPPCState
*env
)
3374 gen_spr_401_403(env
);
3376 gen_spr_compress(env
);
3377 /* Memory management */
3378 #if !defined(CONFIG_USER_ONLY)
3382 env
->tlb_type
= TLB_EMB
;
3384 init_excp_4xx_softmmu(env
);
3385 env
->dcache_line_size
= 32;
3386 env
->icache_line_size
= 32;
3387 /* Allocate hardware IRQ controller */
3388 ppc40x_irq_init(env
);
3390 SET_FIT_PERIOD(8, 12, 16, 20);
3391 SET_WDT_PERIOD(16, 20, 24, 28);
3395 #define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3396 PPC_DCR | PPC_WRTEE | \
3397 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3399 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3400 PPC_4xx_COMMON | PPC_40x_EXCP)
3401 #define POWERPC_INSNS2_403 (PPC_NONE)
3402 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
3403 #define POWERPC_MMU_403 (POWERPC_MMU_REAL)
3404 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3405 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
3406 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
3407 #define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3408 POWERPC_FLAG_BUS_CLK)
3409 #define check_pow_403 check_pow_nocheck
3411 static void init_proc_403 (CPUPPCState
*env
)
3414 gen_spr_401_403(env
);
3416 gen_spr_403_real(env
);
3417 init_excp_4xx_real(env
);
3418 env
->dcache_line_size
= 32;
3419 env
->icache_line_size
= 32;
3420 /* Allocate hardware IRQ controller */
3421 ppc40x_irq_init(env
);
3423 SET_FIT_PERIOD(8, 12, 16, 20);
3424 SET_WDT_PERIOD(16, 20, 24, 28);
3427 /* PowerPC 403 GCX */
3428 #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3429 PPC_DCR | PPC_WRTEE | \
3430 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3432 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3433 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3434 PPC_4xx_COMMON | PPC_40x_EXCP)
3435 #define POWERPC_INSNS2_403GCX (PPC_NONE)
3436 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3437 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3438 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3439 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3440 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
3441 #define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3442 POWERPC_FLAG_BUS_CLK)
3443 #define check_pow_403GCX check_pow_nocheck
3445 static void init_proc_403GCX (CPUPPCState
*env
)
3448 gen_spr_401_403(env
);
3450 gen_spr_403_real(env
);
3451 gen_spr_403_mmu(env
);
3452 /* Bus access control */
3453 /* not emulated, as Qemu never does speculative access */
3454 spr_register(env
, SPR_40x_SGR
, "SGR",
3455 SPR_NOACCESS
, SPR_NOACCESS
,
3456 &spr_read_generic
, &spr_write_generic
,
3458 /* not emulated, as Qemu do not emulate caches */
3459 spr_register(env
, SPR_40x_DCWR
, "DCWR",
3460 SPR_NOACCESS
, SPR_NOACCESS
,
3461 &spr_read_generic
, &spr_write_generic
,
3463 /* Memory management */
3464 #if !defined(CONFIG_USER_ONLY)
3468 env
->tlb_type
= TLB_EMB
;
3470 init_excp_4xx_softmmu(env
);
3471 env
->dcache_line_size
= 32;
3472 env
->icache_line_size
= 32;
3473 /* Allocate hardware IRQ controller */
3474 ppc40x_irq_init(env
);
3476 SET_FIT_PERIOD(8, 12, 16, 20);
3477 SET_WDT_PERIOD(16, 20, 24, 28);
3481 #define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3482 PPC_DCR | PPC_WRTEE | \
3483 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3484 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3485 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3486 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3487 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3488 #define POWERPC_INSNS2_405 (PPC_NONE)
3489 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
3490 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3491 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3492 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3493 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3494 #define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3495 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3496 #define check_pow_405 check_pow_nocheck
3498 static void init_proc_405 (CPUPPCState
*env
)
3504 /* Bus access control */
3505 /* not emulated, as Qemu never does speculative access */
3506 spr_register(env
, SPR_40x_SGR
, "SGR",
3507 SPR_NOACCESS
, SPR_NOACCESS
,
3508 &spr_read_generic
, &spr_write_generic
,
3510 /* not emulated, as Qemu do not emulate caches */
3511 spr_register(env
, SPR_40x_DCWR
, "DCWR",
3512 SPR_NOACCESS
, SPR_NOACCESS
,
3513 &spr_read_generic
, &spr_write_generic
,
3515 /* Memory management */
3516 #if !defined(CONFIG_USER_ONLY)
3520 env
->tlb_type
= TLB_EMB
;
3522 init_excp_4xx_softmmu(env
);
3523 env
->dcache_line_size
= 32;
3524 env
->icache_line_size
= 32;
3525 /* Allocate hardware IRQ controller */
3526 ppc40x_irq_init(env
);
3528 SET_FIT_PERIOD(8, 12, 16, 20);
3529 SET_WDT_PERIOD(16, 20, 24, 28);
3532 /* PowerPC 440 EP */
3533 #define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3534 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3535 PPC_CACHE | PPC_CACHE_ICBI | \
3536 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3537 PPC_MEM_TLBSYNC | PPC_MFTB | \
3538 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3540 #define POWERPC_INSNS2_440EP (PPC_NONE)
3541 #define POWERPC_MSRM_440EP (0x000000000006D630ULL)
3542 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3543 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3544 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3545 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3546 #define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3547 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3548 #define check_pow_440EP check_pow_nocheck
3550 __attribute__ (( unused
))
3551 static void init_proc_440EP (CPUPPCState
*env
)
3555 gen_spr_BookE(env
, 0x000000000000FFFFULL
);
3557 gen_spr_usprgh(env
);
3558 /* Processor identification */
3559 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
3560 SPR_NOACCESS
, SPR_NOACCESS
,
3561 &spr_read_generic
, &spr_write_pir
,
3563 /* XXX : not implemented */
3564 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
3565 SPR_NOACCESS
, SPR_NOACCESS
,
3566 &spr_read_generic
, &spr_write_generic
,
3568 /* XXX : not implemented */
3569 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
3570 SPR_NOACCESS
, SPR_NOACCESS
,
3571 &spr_read_generic
, &spr_write_generic
,
3573 /* XXX : not implemented */
3574 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
3575 SPR_NOACCESS
, SPR_NOACCESS
,
3576 &spr_read_generic
, &spr_write_generic
,
3578 /* XXX : not implemented */
3579 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
3580 SPR_NOACCESS
, SPR_NOACCESS
,
3581 &spr_read_generic
, &spr_write_generic
,
3583 /* XXX : not implemented */
3584 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
3585 SPR_NOACCESS
, SPR_NOACCESS
,
3586 &spr_read_generic
, &spr_write_generic
,
3588 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
3589 SPR_NOACCESS
, SPR_NOACCESS
,
3590 &spr_read_generic
, &spr_write_generic
,
3592 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
3593 SPR_NOACCESS
, SPR_NOACCESS
,
3594 &spr_read_generic
, &spr_write_generic
,
3596 /* XXX : not implemented */
3597 spr_register(env
, SPR_440_CCR1
, "CCR1",
3598 SPR_NOACCESS
, SPR_NOACCESS
,
3599 &spr_read_generic
, &spr_write_generic
,
3601 /* Memory management */
3602 #if !defined(CONFIG_USER_ONLY)
3606 env
->tlb_type
= TLB_EMB
;
3608 init_excp_BookE(env
);
3609 env
->dcache_line_size
= 32;
3610 env
->icache_line_size
= 32;
3611 /* XXX: TODO: allocate internal IRQ controller */
3613 SET_FIT_PERIOD(12, 16, 20, 24);
3614 SET_WDT_PERIOD(20, 24, 28, 32);
3617 /* PowerPC 440 GP */
3618 #define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3619 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3620 PPC_CACHE | PPC_CACHE_ICBI | \
3621 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3622 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \
3623 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3625 #define POWERPC_INSNS2_440GP (PPC_NONE)
3626 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3627 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3628 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3629 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3630 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3631 #define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3632 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3633 #define check_pow_440GP check_pow_nocheck
3635 __attribute__ (( unused
))
3636 static void init_proc_440GP (CPUPPCState
*env
)
3640 gen_spr_BookE(env
, 0x000000000000FFFFULL
);
3642 gen_spr_usprgh(env
);
3643 /* Processor identification */
3644 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
3645 SPR_NOACCESS
, SPR_NOACCESS
,
3646 &spr_read_generic
, &spr_write_pir
,
3648 /* XXX : not implemented */
3649 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
3650 SPR_NOACCESS
, SPR_NOACCESS
,
3651 &spr_read_generic
, &spr_write_generic
,
3653 /* XXX : not implemented */
3654 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
3655 SPR_NOACCESS
, SPR_NOACCESS
,
3656 &spr_read_generic
, &spr_write_generic
,
3658 /* XXX : not implemented */
3659 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
3660 SPR_NOACCESS
, SPR_NOACCESS
,
3661 &spr_read_generic
, &spr_write_generic
,
3663 /* XXX : not implemented */
3664 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
3665 SPR_NOACCESS
, SPR_NOACCESS
,
3666 &spr_read_generic
, &spr_write_generic
,
3668 /* Memory management */
3669 #if !defined(CONFIG_USER_ONLY)
3673 env
->tlb_type
= TLB_EMB
;
3675 init_excp_BookE(env
);
3676 env
->dcache_line_size
= 32;
3677 env
->icache_line_size
= 32;
3678 /* XXX: TODO: allocate internal IRQ controller */
3680 SET_FIT_PERIOD(12, 16, 20, 24);
3681 SET_WDT_PERIOD(20, 24, 28, 32);
3685 #define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3686 PPC_DCR | PPC_WRTEE | \
3687 PPC_CACHE | PPC_CACHE_ICBI | \
3688 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3689 PPC_MEM_TLBSYNC | PPC_MFTB | \
3690 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3692 #define POWERPC_INSNS2_440x4 (PPC_NONE)
3693 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3694 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3695 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3696 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3697 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3698 #define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3699 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3700 #define check_pow_440x4 check_pow_nocheck
3702 __attribute__ (( unused
))
3703 static void init_proc_440x4 (CPUPPCState
*env
)
3707 gen_spr_BookE(env
, 0x000000000000FFFFULL
);
3709 gen_spr_usprgh(env
);
3710 /* Processor identification */
3711 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
3712 SPR_NOACCESS
, SPR_NOACCESS
,
3713 &spr_read_generic
, &spr_write_pir
,
3715 /* XXX : not implemented */
3716 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
3717 SPR_NOACCESS
, SPR_NOACCESS
,
3718 &spr_read_generic
, &spr_write_generic
,
3720 /* XXX : not implemented */
3721 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
3722 SPR_NOACCESS
, SPR_NOACCESS
,
3723 &spr_read_generic
, &spr_write_generic
,
3725 /* XXX : not implemented */
3726 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
3727 SPR_NOACCESS
, SPR_NOACCESS
,
3728 &spr_read_generic
, &spr_write_generic
,
3730 /* XXX : not implemented */
3731 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
3732 SPR_NOACCESS
, SPR_NOACCESS
,
3733 &spr_read_generic
, &spr_write_generic
,
3735 /* Memory management */
3736 #if !defined(CONFIG_USER_ONLY)
3740 env
->tlb_type
= TLB_EMB
;
3742 init_excp_BookE(env
);
3743 env
->dcache_line_size
= 32;
3744 env
->icache_line_size
= 32;
3745 /* XXX: TODO: allocate internal IRQ controller */
3747 SET_FIT_PERIOD(12, 16, 20, 24);
3748 SET_WDT_PERIOD(20, 24, 28, 32);
3752 #define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3753 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3754 PPC_CACHE | PPC_CACHE_ICBI | \
3755 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3756 PPC_MEM_TLBSYNC | PPC_MFTB | \
3757 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3759 #define POWERPC_INSNS2_440x5 (PPC_NONE)
3760 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3761 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3762 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3763 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3764 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3765 #define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3766 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3767 #define check_pow_440x5 check_pow_nocheck
3769 static void init_proc_440x5 (CPUPPCState
*env
)
3773 gen_spr_BookE(env
, 0x000000000000FFFFULL
);
3775 gen_spr_usprgh(env
);
3776 /* Processor identification */
3777 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
3778 SPR_NOACCESS
, SPR_NOACCESS
,
3779 &spr_read_generic
, &spr_write_pir
,
3781 /* XXX : not implemented */
3782 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
3783 SPR_NOACCESS
, SPR_NOACCESS
,
3784 &spr_read_generic
, &spr_write_generic
,
3786 /* XXX : not implemented */
3787 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
3788 SPR_NOACCESS
, SPR_NOACCESS
,
3789 &spr_read_generic
, &spr_write_generic
,
3791 /* XXX : not implemented */
3792 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
3793 SPR_NOACCESS
, SPR_NOACCESS
,
3794 &spr_read_generic
, &spr_write_generic
,
3796 /* XXX : not implemented */
3797 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
3798 SPR_NOACCESS
, SPR_NOACCESS
,
3799 &spr_read_generic
, &spr_write_generic
,
3801 /* XXX : not implemented */
3802 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
3803 SPR_NOACCESS
, SPR_NOACCESS
,
3804 &spr_read_generic
, &spr_write_generic
,
3806 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
3807 SPR_NOACCESS
, SPR_NOACCESS
,
3808 &spr_read_generic
, &spr_write_generic
,
3810 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
3811 SPR_NOACCESS
, SPR_NOACCESS
,
3812 &spr_read_generic
, &spr_write_generic
,
3814 /* XXX : not implemented */
3815 spr_register(env
, SPR_440_CCR1
, "CCR1",
3816 SPR_NOACCESS
, SPR_NOACCESS
,
3817 &spr_read_generic
, &spr_write_generic
,
3819 /* Memory management */
3820 #if !defined(CONFIG_USER_ONLY)
3824 env
->tlb_type
= TLB_EMB
;
3826 init_excp_BookE(env
);
3827 env
->dcache_line_size
= 32;
3828 env
->icache_line_size
= 32;
3829 ppc40x_irq_init(env
);
3831 SET_FIT_PERIOD(12, 16, 20, 24);
3832 SET_WDT_PERIOD(20, 24, 28, 32);
3835 /* PowerPC 460 (guessed) */
3836 #define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
3837 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3838 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \
3839 PPC_CACHE | PPC_CACHE_ICBI | \
3840 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3841 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3842 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3844 #define POWERPC_INSNS2_460 (PPC_NONE)
3845 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3846 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3847 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3848 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3849 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3850 #define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3851 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3852 #define check_pow_460 check_pow_nocheck
3854 __attribute__ (( unused
))
3855 static void init_proc_460 (CPUPPCState
*env
)
3859 gen_spr_BookE(env
, 0x000000000000FFFFULL
);
3861 gen_spr_usprgh(env
);
3862 /* Processor identification */
3863 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
3864 SPR_NOACCESS
, SPR_NOACCESS
,
3865 &spr_read_generic
, &spr_write_pir
,
3867 /* XXX : not implemented */
3868 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
3869 SPR_NOACCESS
, SPR_NOACCESS
,
3870 &spr_read_generic
, &spr_write_generic
,
3872 /* XXX : not implemented */
3873 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
3874 SPR_NOACCESS
, SPR_NOACCESS
,
3875 &spr_read_generic
, &spr_write_generic
,
3877 /* XXX : not implemented */
3878 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
3879 SPR_NOACCESS
, SPR_NOACCESS
,
3880 &spr_read_generic
, &spr_write_generic
,
3882 /* XXX : not implemented */
3883 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
3884 SPR_NOACCESS
, SPR_NOACCESS
,
3885 &spr_read_generic
, &spr_write_generic
,
3887 /* XXX : not implemented */
3888 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
3889 SPR_NOACCESS
, SPR_NOACCESS
,
3890 &spr_read_generic
, &spr_write_generic
,
3892 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
3893 SPR_NOACCESS
, SPR_NOACCESS
,
3894 &spr_read_generic
, &spr_write_generic
,
3896 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
3897 SPR_NOACCESS
, SPR_NOACCESS
,
3898 &spr_read_generic
, &spr_write_generic
,
3900 /* XXX : not implemented */
3901 spr_register(env
, SPR_440_CCR1
, "CCR1",
3902 SPR_NOACCESS
, SPR_NOACCESS
,
3903 &spr_read_generic
, &spr_write_generic
,
3905 /* XXX : not implemented */
3906 spr_register(env
, SPR_DCRIPR
, "SPR_DCRIPR",
3907 &spr_read_generic
, &spr_write_generic
,
3908 &spr_read_generic
, &spr_write_generic
,
3910 /* Memory management */
3911 #if !defined(CONFIG_USER_ONLY)
3915 env
->tlb_type
= TLB_EMB
;
3917 init_excp_BookE(env
);
3918 env
->dcache_line_size
= 32;
3919 env
->icache_line_size
= 32;
3920 /* XXX: TODO: allocate internal IRQ controller */
3922 SET_FIT_PERIOD(12, 16, 20, 24);
3923 SET_WDT_PERIOD(20, 24, 28, 32);
3926 /* PowerPC 460F (guessed) */
3927 #define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3928 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3929 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3930 PPC_FLOAT_STFIWX | PPC_MFTB | \
3931 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3932 PPC_WRTEE | PPC_MFAPIDI | \
3933 PPC_CACHE | PPC_CACHE_ICBI | \
3934 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3935 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3936 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3938 #define POWERPC_INSNS2_460F (PPC_NONE)
3939 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3940 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3941 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3942 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3943 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3944 #define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3945 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3946 #define check_pow_460F check_pow_nocheck
3948 __attribute__ (( unused
))
3949 static void init_proc_460F (CPUPPCState
*env
)
3953 gen_spr_BookE(env
, 0x000000000000FFFFULL
);
3955 gen_spr_usprgh(env
);
3956 /* Processor identification */
3957 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
3958 SPR_NOACCESS
, SPR_NOACCESS
,
3959 &spr_read_generic
, &spr_write_pir
,
3961 /* XXX : not implemented */
3962 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
3963 SPR_NOACCESS
, SPR_NOACCESS
,
3964 &spr_read_generic
, &spr_write_generic
,
3966 /* XXX : not implemented */
3967 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
3968 SPR_NOACCESS
, SPR_NOACCESS
,
3969 &spr_read_generic
, &spr_write_generic
,
3971 /* XXX : not implemented */
3972 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
3973 SPR_NOACCESS
, SPR_NOACCESS
,
3974 &spr_read_generic
, &spr_write_generic
,
3976 /* XXX : not implemented */
3977 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
3978 SPR_NOACCESS
, SPR_NOACCESS
,
3979 &spr_read_generic
, &spr_write_generic
,
3981 /* XXX : not implemented */
3982 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
3983 SPR_NOACCESS
, SPR_NOACCESS
,
3984 &spr_read_generic
, &spr_write_generic
,
3986 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
3987 SPR_NOACCESS
, SPR_NOACCESS
,
3988 &spr_read_generic
, &spr_write_generic
,
3990 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
3991 SPR_NOACCESS
, SPR_NOACCESS
,
3992 &spr_read_generic
, &spr_write_generic
,
3994 /* XXX : not implemented */
3995 spr_register(env
, SPR_440_CCR1
, "CCR1",
3996 SPR_NOACCESS
, SPR_NOACCESS
,
3997 &spr_read_generic
, &spr_write_generic
,
3999 /* XXX : not implemented */
4000 spr_register(env
, SPR_DCRIPR
, "SPR_DCRIPR",
4001 &spr_read_generic
, &spr_write_generic
,
4002 &spr_read_generic
, &spr_write_generic
,
4004 /* Memory management */
4005 #if !defined(CONFIG_USER_ONLY)
4009 env
->tlb_type
= TLB_EMB
;
4011 init_excp_BookE(env
);
4012 env
->dcache_line_size
= 32;
4013 env
->icache_line_size
= 32;
4014 /* XXX: TODO: allocate internal IRQ controller */
4016 SET_FIT_PERIOD(12, 16, 20, 24);
4017 SET_WDT_PERIOD(20, 24, 28, 32);
4020 /* Freescale 5xx cores (aka RCPU) */
4021 #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
4022 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4023 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
4025 #define POWERPC_INSNS2_MPC5xx (PPC_NONE)
4026 #define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
4027 #define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
4028 #define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
4029 #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
4030 #define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4031 #define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4032 POWERPC_FLAG_BUS_CLK)
4033 #define check_pow_MPC5xx check_pow_none
4035 __attribute__ (( unused
))
4036 static void init_proc_MPC5xx (CPUPPCState
*env
)
4040 gen_spr_5xx_8xx(env
);
4042 init_excp_MPC5xx(env
);
4043 env
->dcache_line_size
= 32;
4044 env
->icache_line_size
= 32;
4045 /* XXX: TODO: allocate internal IRQ controller */
4048 /* Freescale 8xx cores (aka PowerQUICC) */
4049 #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
4050 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4051 PPC_CACHE_ICBI | PPC_MFTB)
4052 #define POWERPC_INSNS2_MPC8xx (PPC_NONE)
4053 #define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
4054 #define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
4055 #define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
4056 #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
4057 #define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4058 #define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4059 POWERPC_FLAG_BUS_CLK)
4060 #define check_pow_MPC8xx check_pow_none
4062 __attribute__ (( unused
))
4063 static void init_proc_MPC8xx (CPUPPCState
*env
)
4067 gen_spr_5xx_8xx(env
);
4069 init_excp_MPC8xx(env
);
4070 env
->dcache_line_size
= 32;
4071 env
->icache_line_size
= 32;
4072 /* XXX: TODO: allocate internal IRQ controller */
4075 /* Freescale 82xx cores (aka PowerQUICC-II) */
4077 #define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4078 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4079 PPC_FLOAT_STFIWX | \
4080 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4081 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4082 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4083 PPC_SEGMENT | PPC_EXTERN)
4084 #define POWERPC_INSNS2_G2 (PPC_NONE)
4085 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
4086 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
4087 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
4088 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
4089 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
4090 #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4091 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4092 #define check_pow_G2 check_pow_hid0
4094 static void init_proc_G2 (CPUPPCState
*env
)
4096 gen_spr_ne_601(env
);
4097 gen_spr_G2_755(env
);
4101 /* External access control */
4102 /* XXX : not implemented */
4103 spr_register(env
, SPR_EAR
, "EAR",
4104 SPR_NOACCESS
, SPR_NOACCESS
,
4105 &spr_read_generic
, &spr_write_generic
,
4107 /* Hardware implementation register */
4108 /* XXX : not implemented */
4109 spr_register(env
, SPR_HID0
, "HID0",
4110 SPR_NOACCESS
, SPR_NOACCESS
,
4111 &spr_read_generic
, &spr_write_generic
,
4113 /* XXX : not implemented */
4114 spr_register(env
, SPR_HID1
, "HID1",
4115 SPR_NOACCESS
, SPR_NOACCESS
,
4116 &spr_read_generic
, &spr_write_generic
,
4118 /* XXX : not implemented */
4119 spr_register(env
, SPR_HID2
, "HID2",
4120 SPR_NOACCESS
, SPR_NOACCESS
,
4121 &spr_read_generic
, &spr_write_generic
,
4123 /* Memory management */
4126 gen_6xx_7xx_soft_tlb(env
, 64, 2);
4128 env
->dcache_line_size
= 32;
4129 env
->icache_line_size
= 32;
4130 /* Allocate hardware IRQ controller */
4131 ppc6xx_irq_init(env
);
4135 #define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4136 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4137 PPC_FLOAT_STFIWX | \
4138 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4139 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4140 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4141 PPC_SEGMENT | PPC_EXTERN)
4142 #define POWERPC_INSNS2_G2LE (PPC_NONE)
4143 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
4144 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
4145 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
4146 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
4147 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
4148 #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4149 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4150 #define check_pow_G2LE check_pow_hid0
4152 static void init_proc_G2LE (CPUPPCState
*env
)
4154 gen_spr_ne_601(env
);
4155 gen_spr_G2_755(env
);
4159 /* External access control */
4160 /* XXX : not implemented */
4161 spr_register(env
, SPR_EAR
, "EAR",
4162 SPR_NOACCESS
, SPR_NOACCESS
,
4163 &spr_read_generic
, &spr_write_generic
,
4165 /* Hardware implementation register */
4166 /* XXX : not implemented */
4167 spr_register(env
, SPR_HID0
, "HID0",
4168 SPR_NOACCESS
, SPR_NOACCESS
,
4169 &spr_read_generic
, &spr_write_generic
,
4171 /* XXX : not implemented */
4172 spr_register(env
, SPR_HID1
, "HID1",
4173 SPR_NOACCESS
, SPR_NOACCESS
,
4174 &spr_read_generic
, &spr_write_generic
,
4176 /* XXX : not implemented */
4177 spr_register(env
, SPR_HID2
, "HID2",
4178 SPR_NOACCESS
, SPR_NOACCESS
,
4179 &spr_read_generic
, &spr_write_generic
,
4181 /* Memory management */
4184 gen_6xx_7xx_soft_tlb(env
, 64, 2);
4186 env
->dcache_line_size
= 32;
4187 env
->icache_line_size
= 32;
4188 /* Allocate hardware IRQ controller */
4189 ppc6xx_irq_init(env
);
4193 /* XXX: unimplemented instructions:
4200 * all SPE multiply-accumulate instructions
4202 #define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
4203 PPC_SPE | PPC_SPE_SINGLE | \
4204 PPC_WRTEE | PPC_RFDI | \
4205 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4206 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4207 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4209 #define POWERPC_INSNS2_e200 (PPC_NONE)
4210 #define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
4211 #define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
4212 #define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
4213 #define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
4214 #define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
4215 #define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4216 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4217 POWERPC_FLAG_BUS_CLK)
4218 #define check_pow_e200 check_pow_hid0
4220 __attribute__ (( unused
))
4221 static void init_proc_e200 (CPUPPCState
*env
)
4225 gen_spr_BookE(env
, 0x000000070000FFFFULL
);
4226 /* XXX : not implemented */
4227 spr_register(env
, SPR_BOOKE_SPEFSCR
, "SPEFSCR",
4228 &spr_read_spefscr
, &spr_write_spefscr
,
4229 &spr_read_spefscr
, &spr_write_spefscr
,
4231 /* Memory management */
4232 gen_spr_BookE206(env
, 0x0000005D, NULL
);
4233 /* XXX : not implemented */
4234 spr_register(env
, SPR_HID0
, "HID0",
4235 SPR_NOACCESS
, SPR_NOACCESS
,
4236 &spr_read_generic
, &spr_write_generic
,
4238 /* XXX : not implemented */
4239 spr_register(env
, SPR_HID1
, "HID1",
4240 SPR_NOACCESS
, SPR_NOACCESS
,
4241 &spr_read_generic
, &spr_write_generic
,
4243 /* XXX : not implemented */
4244 spr_register(env
, SPR_Exxx_ALTCTXCR
, "ALTCTXCR",
4245 SPR_NOACCESS
, SPR_NOACCESS
,
4246 &spr_read_generic
, &spr_write_generic
,
4248 /* XXX : not implemented */
4249 spr_register(env
, SPR_Exxx_BUCSR
, "BUCSR",
4250 SPR_NOACCESS
, SPR_NOACCESS
,
4251 &spr_read_generic
, &spr_write_generic
,
4253 /* XXX : not implemented */
4254 spr_register(env
, SPR_Exxx_CTXCR
, "CTXCR",
4255 SPR_NOACCESS
, SPR_NOACCESS
,
4256 &spr_read_generic
, &spr_write_generic
,
4258 /* XXX : not implemented */
4259 spr_register(env
, SPR_Exxx_DBCNT
, "DBCNT",
4260 SPR_NOACCESS
, SPR_NOACCESS
,
4261 &spr_read_generic
, &spr_write_generic
,
4263 /* XXX : not implemented */
4264 spr_register(env
, SPR_Exxx_DBCR3
, "DBCR3",
4265 SPR_NOACCESS
, SPR_NOACCESS
,
4266 &spr_read_generic
, &spr_write_generic
,
4268 /* XXX : not implemented */
4269 spr_register(env
, SPR_Exxx_L1CFG0
, "L1CFG0",
4270 SPR_NOACCESS
, SPR_NOACCESS
,
4271 &spr_read_generic
, &spr_write_generic
,
4273 /* XXX : not implemented */
4274 spr_register(env
, SPR_Exxx_L1CSR0
, "L1CSR0",
4275 SPR_NOACCESS
, SPR_NOACCESS
,
4276 &spr_read_generic
, &spr_write_generic
,
4278 /* XXX : not implemented */
4279 spr_register(env
, SPR_Exxx_L1FINV0
, "L1FINV0",
4280 SPR_NOACCESS
, SPR_NOACCESS
,
4281 &spr_read_generic
, &spr_write_generic
,
4283 /* XXX : not implemented */
4284 spr_register(env
, SPR_BOOKE_TLB0CFG
, "TLB0CFG",
4285 SPR_NOACCESS
, SPR_NOACCESS
,
4286 &spr_read_generic
, &spr_write_generic
,
4288 /* XXX : not implemented */
4289 spr_register(env
, SPR_BOOKE_TLB1CFG
, "TLB1CFG",
4290 SPR_NOACCESS
, SPR_NOACCESS
,
4291 &spr_read_generic
, &spr_write_generic
,
4293 /* XXX : not implemented */
4294 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
4295 SPR_NOACCESS
, SPR_NOACCESS
,
4296 &spr_read_generic
, &spr_write_generic
,
4298 /* XXX : not implemented */
4299 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
4300 SPR_NOACCESS
, SPR_NOACCESS
,
4301 &spr_read_generic
, &spr_write_generic
,
4303 /* XXX : not implemented */
4304 spr_register(env
, SPR_MMUCSR0
, "MMUCSR0",
4305 SPR_NOACCESS
, SPR_NOACCESS
,
4306 &spr_read_generic
, &spr_write_generic
,
4307 0x00000000); /* TOFIX */
4308 spr_register(env
, SPR_BOOKE_DSRR0
, "DSRR0",
4309 SPR_NOACCESS
, SPR_NOACCESS
,
4310 &spr_read_generic
, &spr_write_generic
,
4312 spr_register(env
, SPR_BOOKE_DSRR1
, "DSRR1",
4313 SPR_NOACCESS
, SPR_NOACCESS
,
4314 &spr_read_generic
, &spr_write_generic
,
4316 #if !defined(CONFIG_USER_ONLY)
4320 env
->tlb_type
= TLB_EMB
;
4322 init_excp_e200(env
);
4323 env
->dcache_line_size
= 32;
4324 env
->icache_line_size
= 32;
4325 /* XXX: TODO: allocate internal IRQ controller */
4329 #define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4330 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4331 PPC_FLOAT_STFIWX | \
4332 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4333 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4334 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4335 PPC_SEGMENT | PPC_EXTERN)
4336 #define POWERPC_INSNS2_e300 (PPC_NONE)
4337 #define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4338 #define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4339 #define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4340 #define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4341 #define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4342 #define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4343 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4344 #define check_pow_e300 check_pow_hid0
4346 __attribute__ (( unused
))
4347 static void init_proc_e300 (CPUPPCState
*env
)
4349 gen_spr_ne_601(env
);
4353 /* hardware implementation registers */
4354 /* XXX : not implemented */
4355 spr_register(env
, SPR_HID0
, "HID0",
4356 SPR_NOACCESS
, SPR_NOACCESS
,
4357 &spr_read_generic
, &spr_write_generic
,
4359 /* XXX : not implemented */
4360 spr_register(env
, SPR_HID1
, "HID1",
4361 SPR_NOACCESS
, SPR_NOACCESS
,
4362 &spr_read_generic
, &spr_write_generic
,
4364 /* XXX : not implemented */
4365 spr_register(env
, SPR_HID2
, "HID2",
4366 SPR_NOACCESS
, SPR_NOACCESS
,
4367 &spr_read_generic
, &spr_write_generic
,
4369 /* Memory management */
4372 gen_6xx_7xx_soft_tlb(env
, 64, 2);
4374 env
->dcache_line_size
= 32;
4375 env
->icache_line_size
= 32;
4376 /* Allocate hardware IRQ controller */
4377 ppc6xx_irq_init(env
);
4381 #define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4382 PPC_SPE | PPC_SPE_SINGLE | \
4383 PPC_WRTEE | PPC_RFDI | \
4384 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4385 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4386 PPC_MEM_TLBSYNC | PPC_TLBIVAX)
4387 #define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206)
4388 #define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
4389 #define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
4390 #define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4391 #define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4392 #define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4393 #define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4394 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4395 POWERPC_FLAG_BUS_CLK)
4396 #define check_pow_e500v1 check_pow_hid0
4397 #define init_proc_e500v1 init_proc_e500v1
4400 #define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4401 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4402 PPC_WRTEE | PPC_RFDI | \
4403 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4404 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4405 PPC_MEM_TLBSYNC | PPC_TLBIVAX)
4406 #define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206)
4407 #define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
4408 #define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
4409 #define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4410 #define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4411 #define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4412 #define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4413 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4414 POWERPC_FLAG_BUS_CLK)
4415 #define check_pow_e500v2 check_pow_hid0
4416 #define init_proc_e500v2 init_proc_e500v2
4418 static void init_proc_e500 (CPUPPCState
*env
, int version
)
4420 uint32_t tlbncfg
[2];
4421 #if !defined(CONFIG_USER_ONLY)
4428 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4429 * complain when accessing them.
4430 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4432 gen_spr_BookE(env
, 0x0000000F0000FFFFULL
);
4433 /* Processor identification */
4434 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
4435 SPR_NOACCESS
, SPR_NOACCESS
,
4436 &spr_read_generic
, &spr_write_pir
,
4438 /* XXX : not implemented */
4439 spr_register(env
, SPR_BOOKE_SPEFSCR
, "SPEFSCR",
4440 &spr_read_spefscr
, &spr_write_spefscr
,
4441 &spr_read_spefscr
, &spr_write_spefscr
,
4443 /* Memory management */
4444 #if !defined(CONFIG_USER_ONLY)
4451 tlbncfg
[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4452 tlbncfg
[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL
| TLBnCFG_IPROT
, 16);
4456 tlbncfg
[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4457 tlbncfg
[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL
| TLBnCFG_IPROT
, 16);
4460 cpu_abort(env
, "Unknown CPU: " TARGET_FMT_lx
"\n", env
->spr
[SPR_PVR
]);
4463 gen_spr_BookE206(env
, 0x000000DF, tlbncfg
);
4464 /* XXX : not implemented */
4465 spr_register(env
, SPR_HID0
, "HID0",
4466 SPR_NOACCESS
, SPR_NOACCESS
,
4467 &spr_read_generic
, &spr_write_generic
,
4469 /* XXX : not implemented */
4470 spr_register(env
, SPR_HID1
, "HID1",
4471 SPR_NOACCESS
, SPR_NOACCESS
,
4472 &spr_read_generic
, &spr_write_generic
,
4474 /* XXX : not implemented */
4475 spr_register(env
, SPR_Exxx_BBEAR
, "BBEAR",
4476 SPR_NOACCESS
, SPR_NOACCESS
,
4477 &spr_read_generic
, &spr_write_generic
,
4479 /* XXX : not implemented */
4480 spr_register(env
, SPR_Exxx_BBTAR
, "BBTAR",
4481 SPR_NOACCESS
, SPR_NOACCESS
,
4482 &spr_read_generic
, &spr_write_generic
,
4484 /* XXX : not implemented */
4485 spr_register(env
, SPR_Exxx_MCAR
, "MCAR",
4486 SPR_NOACCESS
, SPR_NOACCESS
,
4487 &spr_read_generic
, &spr_write_generic
,
4489 /* XXX : not implemented */
4490 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
4491 SPR_NOACCESS
, SPR_NOACCESS
,
4492 &spr_read_generic
, &spr_write_generic
,
4494 /* XXX : not implemented */
4495 spr_register(env
, SPR_Exxx_NPIDR
, "NPIDR",
4496 SPR_NOACCESS
, SPR_NOACCESS
,
4497 &spr_read_generic
, &spr_write_generic
,
4499 /* XXX : not implemented */
4500 spr_register(env
, SPR_Exxx_BUCSR
, "BUCSR",
4501 SPR_NOACCESS
, SPR_NOACCESS
,
4502 &spr_read_generic
, &spr_write_generic
,
4504 /* XXX : not implemented */
4505 spr_register(env
, SPR_Exxx_L1CFG0
, "L1CFG0",
4506 SPR_NOACCESS
, SPR_NOACCESS
,
4507 &spr_read_generic
, &spr_write_generic
,
4509 /* XXX : not implemented */
4510 spr_register(env
, SPR_Exxx_L1CSR0
, "L1CSR0",
4511 SPR_NOACCESS
, SPR_NOACCESS
,
4512 &spr_read_generic
, &spr_write_e500_l1csr0
,
4514 /* XXX : not implemented */
4515 spr_register(env
, SPR_Exxx_L1CSR1
, "L1CSR1",
4516 SPR_NOACCESS
, SPR_NOACCESS
,
4517 &spr_read_generic
, &spr_write_generic
,
4519 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
4520 SPR_NOACCESS
, SPR_NOACCESS
,
4521 &spr_read_generic
, &spr_write_generic
,
4523 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
4524 SPR_NOACCESS
, SPR_NOACCESS
,
4525 &spr_read_generic
, &spr_write_generic
,
4527 spr_register(env
, SPR_MMUCSR0
, "MMUCSR0",
4528 SPR_NOACCESS
, SPR_NOACCESS
,
4529 &spr_read_generic
, &spr_write_booke206_mmucsr0
,
4532 #if !defined(CONFIG_USER_ONLY)
4534 env
->tlb_type
= TLB_MAS
;
4535 for (i
= 0; i
< BOOKE206_MAX_TLBN
; i
++) {
4536 env
->nb_tlb
+= booke206_tlb_size(env
, i
);
4540 init_excp_e200(env
);
4541 env
->dcache_line_size
= 32;
4542 env
->icache_line_size
= 32;
4543 /* Allocate hardware IRQ controller */
4544 ppce500_irq_init(env
);
4547 static void init_proc_e500v1(CPUPPCState
*env
)
4549 init_proc_e500(env
, 1);
4552 static void init_proc_e500v2(CPUPPCState
*env
)
4554 init_proc_e500(env
, 2);
4557 /* Non-embedded PowerPC */
4559 /* POWER : same as 601, without mfmsr, mfsr */
4561 #define POWERPC_INSNS_POWER (XXX_TODO)
4562 /* POWER RSC (from RAD6000) */
4563 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4567 #define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4569 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4570 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4571 PPC_SEGMENT | PPC_EXTERN)
4572 #define POWERPC_INSNS2_601 (PPC_NONE)
4573 #define POWERPC_MSRM_601 (0x000000000000FD70ULL)
4574 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4575 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
4576 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4577 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
4578 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4579 #define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4580 #define check_pow_601 check_pow_none
4582 static void init_proc_601 (CPUPPCState
*env
)
4584 gen_spr_ne_601(env
);
4586 /* Hardware implementation registers */
4587 /* XXX : not implemented */
4588 spr_register(env
, SPR_HID0
, "HID0",
4589 SPR_NOACCESS
, SPR_NOACCESS
,
4590 &spr_read_generic
, &spr_write_hid0_601
,
4592 /* XXX : not implemented */
4593 spr_register(env
, SPR_HID1
, "HID1",
4594 SPR_NOACCESS
, SPR_NOACCESS
,
4595 &spr_read_generic
, &spr_write_generic
,
4597 /* XXX : not implemented */
4598 spr_register(env
, SPR_601_HID2
, "HID2",
4599 SPR_NOACCESS
, SPR_NOACCESS
,
4600 &spr_read_generic
, &spr_write_generic
,
4602 /* XXX : not implemented */
4603 spr_register(env
, SPR_601_HID5
, "HID5",
4604 SPR_NOACCESS
, SPR_NOACCESS
,
4605 &spr_read_generic
, &spr_write_generic
,
4607 /* Memory management */
4609 /* XXX: beware that dcache line size is 64
4610 * but dcbz uses 32 bytes "sectors"
4611 * XXX: this breaks clcs instruction !
4613 env
->dcache_line_size
= 32;
4614 env
->icache_line_size
= 64;
4615 /* Allocate hardware IRQ controller */
4616 ppc6xx_irq_init(env
);
4620 #define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4622 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4623 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4624 PPC_SEGMENT | PPC_EXTERN)
4625 #define POWERPC_INSNS2_601v (PPC_NONE)
4626 #define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4627 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4628 #define POWERPC_MMU_601v (POWERPC_MMU_601)
4629 #define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4630 #define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4631 #define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4632 #define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4633 #define check_pow_601v check_pow_none
4635 static void init_proc_601v (CPUPPCState
*env
)
4638 /* XXX : not implemented */
4639 spr_register(env
, SPR_601_HID15
, "HID15",
4640 SPR_NOACCESS
, SPR_NOACCESS
,
4641 &spr_read_generic
, &spr_write_generic
,
4646 #define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4647 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4648 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4649 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4650 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4651 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4652 PPC_SEGMENT | PPC_602_SPEC)
4653 #define POWERPC_INSNS2_602 (PPC_NONE)
4654 #define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4655 /* XXX: 602 MMU is quite specific. Should add a special case */
4656 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4657 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4658 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
4659 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
4660 #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4661 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4662 #define check_pow_602 check_pow_hid0
4664 static void init_proc_602 (CPUPPCState
*env
)
4666 gen_spr_ne_601(env
);
4670 /* hardware implementation registers */
4671 /* XXX : not implemented */
4672 spr_register(env
, SPR_HID0
, "HID0",
4673 SPR_NOACCESS
, SPR_NOACCESS
,
4674 &spr_read_generic
, &spr_write_generic
,
4676 /* XXX : not implemented */
4677 spr_register(env
, SPR_HID1
, "HID1",
4678 SPR_NOACCESS
, SPR_NOACCESS
,
4679 &spr_read_generic
, &spr_write_generic
,
4681 /* Memory management */
4683 gen_6xx_7xx_soft_tlb(env
, 64, 2);
4685 env
->dcache_line_size
= 32;
4686 env
->icache_line_size
= 32;
4687 /* Allocate hardware IRQ controller */
4688 ppc6xx_irq_init(env
);
4692 #define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4693 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4694 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4695 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4696 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4697 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4698 PPC_SEGMENT | PPC_EXTERN)
4699 #define POWERPC_INSNS2_603 (PPC_NONE)
4700 #define POWERPC_MSRM_603 (0x000000000007FF73ULL)
4701 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4702 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4703 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
4704 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
4705 #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4706 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4707 #define check_pow_603 check_pow_hid0
4709 static void init_proc_603 (CPUPPCState
*env
)
4711 gen_spr_ne_601(env
);
4715 /* hardware implementation registers */
4716 /* XXX : not implemented */
4717 spr_register(env
, SPR_HID0
, "HID0",
4718 SPR_NOACCESS
, SPR_NOACCESS
,
4719 &spr_read_generic
, &spr_write_generic
,
4721 /* XXX : not implemented */
4722 spr_register(env
, SPR_HID1
, "HID1",
4723 SPR_NOACCESS
, SPR_NOACCESS
,
4724 &spr_read_generic
, &spr_write_generic
,
4726 /* Memory management */
4728 gen_6xx_7xx_soft_tlb(env
, 64, 2);
4730 env
->dcache_line_size
= 32;
4731 env
->icache_line_size
= 32;
4732 /* Allocate hardware IRQ controller */
4733 ppc6xx_irq_init(env
);
4737 #define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4738 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4739 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4740 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4741 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4742 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4743 PPC_SEGMENT | PPC_EXTERN)
4744 #define POWERPC_INSNS2_603E (PPC_NONE)
4745 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4746 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4747 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4748 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
4749 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
4750 #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4751 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4752 #define check_pow_603E check_pow_hid0
4754 static void init_proc_603E (CPUPPCState
*env
)
4756 gen_spr_ne_601(env
);
4760 /* hardware implementation registers */
4761 /* XXX : not implemented */
4762 spr_register(env
, SPR_HID0
, "HID0",
4763 SPR_NOACCESS
, SPR_NOACCESS
,
4764 &spr_read_generic
, &spr_write_generic
,
4766 /* XXX : not implemented */
4767 spr_register(env
, SPR_HID1
, "HID1",
4768 SPR_NOACCESS
, SPR_NOACCESS
,
4769 &spr_read_generic
, &spr_write_generic
,
4771 /* XXX : not implemented */
4772 spr_register(env
, SPR_IABR
, "IABR",
4773 SPR_NOACCESS
, SPR_NOACCESS
,
4774 &spr_read_generic
, &spr_write_generic
,
4776 /* Memory management */
4778 gen_6xx_7xx_soft_tlb(env
, 64, 2);
4780 env
->dcache_line_size
= 32;
4781 env
->icache_line_size
= 32;
4782 /* Allocate hardware IRQ controller */
4783 ppc6xx_irq_init(env
);
4787 #define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4788 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4789 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4790 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4791 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4792 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4793 PPC_SEGMENT | PPC_EXTERN)
4794 #define POWERPC_INSNS2_604 (PPC_NONE)
4795 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4796 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
4797 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4798 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
4799 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
4800 #define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4801 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4802 #define check_pow_604 check_pow_nocheck
4804 static void init_proc_604 (CPUPPCState
*env
)
4806 gen_spr_ne_601(env
);
4810 /* Hardware implementation registers */
4811 /* XXX : not implemented */
4812 spr_register(env
, SPR_HID0
, "HID0",
4813 SPR_NOACCESS
, SPR_NOACCESS
,
4814 &spr_read_generic
, &spr_write_generic
,
4816 /* Memory management */
4819 env
->dcache_line_size
= 32;
4820 env
->icache_line_size
= 32;
4821 /* Allocate hardware IRQ controller */
4822 ppc6xx_irq_init(env
);
4826 #define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4827 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4828 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4829 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4830 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4831 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4832 PPC_SEGMENT | PPC_EXTERN)
4833 #define POWERPC_INSNS2_604E (PPC_NONE)
4834 #define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4835 #define POWERPC_MMU_604E (POWERPC_MMU_32B)
4836 #define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4837 #define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4838 #define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4839 #define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4840 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4841 #define check_pow_604E check_pow_nocheck
4843 static void init_proc_604E (CPUPPCState
*env
)
4845 gen_spr_ne_601(env
);
4847 /* XXX : not implemented */
4848 spr_register(env
, SPR_MMCR1
, "MMCR1",
4849 SPR_NOACCESS
, SPR_NOACCESS
,
4850 &spr_read_generic
, &spr_write_generic
,
4852 /* XXX : not implemented */
4853 spr_register(env
, SPR_PMC3
, "PMC3",
4854 SPR_NOACCESS
, SPR_NOACCESS
,
4855 &spr_read_generic
, &spr_write_generic
,
4857 /* XXX : not implemented */
4858 spr_register(env
, SPR_PMC4
, "PMC4",
4859 SPR_NOACCESS
, SPR_NOACCESS
,
4860 &spr_read_generic
, &spr_write_generic
,
4864 /* Hardware implementation registers */
4865 /* XXX : not implemented */
4866 spr_register(env
, SPR_HID0
, "HID0",
4867 SPR_NOACCESS
, SPR_NOACCESS
,
4868 &spr_read_generic
, &spr_write_generic
,
4870 /* XXX : not implemented */
4871 spr_register(env
, SPR_HID1
, "HID1",
4872 SPR_NOACCESS
, SPR_NOACCESS
,
4873 &spr_read_generic
, &spr_write_generic
,
4875 /* Memory management */
4878 env
->dcache_line_size
= 32;
4879 env
->icache_line_size
= 32;
4880 /* Allocate hardware IRQ controller */
4881 ppc6xx_irq_init(env
);
4885 #define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4886 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4887 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4888 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4889 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4890 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4891 PPC_SEGMENT | PPC_EXTERN)
4892 #define POWERPC_INSNS2_740 (PPC_NONE)
4893 #define POWERPC_MSRM_740 (0x000000000005FF77ULL)
4894 #define POWERPC_MMU_740 (POWERPC_MMU_32B)
4895 #define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
4896 #define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
4897 #define POWERPC_BFDM_740 (bfd_mach_ppc_750)
4898 #define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4899 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4900 #define check_pow_740 check_pow_hid0
4902 static void init_proc_740 (CPUPPCState
*env
)
4904 gen_spr_ne_601(env
);
4908 /* Thermal management */
4910 /* Hardware implementation registers */
4911 /* XXX : not implemented */
4912 spr_register(env
, SPR_HID0
, "HID0",
4913 SPR_NOACCESS
, SPR_NOACCESS
,
4914 &spr_read_generic
, &spr_write_generic
,
4916 /* XXX : not implemented */
4917 spr_register(env
, SPR_HID1
, "HID1",
4918 SPR_NOACCESS
, SPR_NOACCESS
,
4919 &spr_read_generic
, &spr_write_generic
,
4921 /* Memory management */
4924 env
->dcache_line_size
= 32;
4925 env
->icache_line_size
= 32;
4926 /* Allocate hardware IRQ controller */
4927 ppc6xx_irq_init(env
);
4931 #define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4932 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4933 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4934 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4935 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4936 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4937 PPC_SEGMENT | PPC_EXTERN)
4938 #define POWERPC_INSNS2_750 (PPC_NONE)
4939 #define POWERPC_MSRM_750 (0x000000000005FF77ULL)
4940 #define POWERPC_MMU_750 (POWERPC_MMU_32B)
4941 #define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
4942 #define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
4943 #define POWERPC_BFDM_750 (bfd_mach_ppc_750)
4944 #define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4945 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4946 #define check_pow_750 check_pow_hid0
4948 static void init_proc_750 (CPUPPCState
*env
)
4950 gen_spr_ne_601(env
);
4952 /* XXX : not implemented */
4953 spr_register(env
, SPR_L2CR
, "L2CR",
4954 SPR_NOACCESS
, SPR_NOACCESS
,
4955 &spr_read_generic
, &spr_write_generic
,
4959 /* Thermal management */
4961 /* Hardware implementation registers */
4962 /* XXX : not implemented */
4963 spr_register(env
, SPR_HID0
, "HID0",
4964 SPR_NOACCESS
, SPR_NOACCESS
,
4965 &spr_read_generic
, &spr_write_generic
,
4967 /* XXX : not implemented */
4968 spr_register(env
, SPR_HID1
, "HID1",
4969 SPR_NOACCESS
, SPR_NOACCESS
,
4970 &spr_read_generic
, &spr_write_generic
,
4972 /* Memory management */
4974 /* XXX: high BATs are also present but are known to be bugged on
4978 env
->dcache_line_size
= 32;
4979 env
->icache_line_size
= 32;
4980 /* Allocate hardware IRQ controller */
4981 ppc6xx_irq_init(env
);
4984 /* PowerPC 750 CL */
4985 /* XXX: not implemented:
4986 * cache lock instructions:
4988 * floating point paired instructions
5023 #define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5024 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5025 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5026 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5027 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5028 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5029 PPC_SEGMENT | PPC_EXTERN)
5030 #define POWERPC_INSNS2_750cl (PPC_NONE)
5031 #define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
5032 #define POWERPC_MMU_750cl (POWERPC_MMU_32B)
5033 #define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
5034 #define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
5035 #define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
5036 #define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5037 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5038 #define check_pow_750cl check_pow_hid0
5040 static void init_proc_750cl (CPUPPCState
*env
)
5042 gen_spr_ne_601(env
);
5044 /* XXX : not implemented */
5045 spr_register(env
, SPR_L2CR
, "L2CR",
5046 SPR_NOACCESS
, SPR_NOACCESS
,
5047 &spr_read_generic
, &spr_write_generic
,
5051 /* Thermal management */
5052 /* Those registers are fake on 750CL */
5053 spr_register(env
, SPR_THRM1
, "THRM1",
5054 SPR_NOACCESS
, SPR_NOACCESS
,
5055 &spr_read_generic
, &spr_write_generic
,
5057 spr_register(env
, SPR_THRM2
, "THRM2",
5058 SPR_NOACCESS
, SPR_NOACCESS
,
5059 &spr_read_generic
, &spr_write_generic
,
5061 spr_register(env
, SPR_THRM3
, "THRM3",
5062 SPR_NOACCESS
, SPR_NOACCESS
,
5063 &spr_read_generic
, &spr_write_generic
,
5065 /* XXX: not implemented */
5066 spr_register(env
, SPR_750_TDCL
, "TDCL",
5067 SPR_NOACCESS
, SPR_NOACCESS
,
5068 &spr_read_generic
, &spr_write_generic
,
5070 spr_register(env
, SPR_750_TDCH
, "TDCH",
5071 SPR_NOACCESS
, SPR_NOACCESS
,
5072 &spr_read_generic
, &spr_write_generic
,
5075 /* XXX : not implemented */
5076 spr_register(env
, SPR_750_WPAR
, "WPAR",
5077 SPR_NOACCESS
, SPR_NOACCESS
,
5078 &spr_read_generic
, &spr_write_generic
,
5080 spr_register(env
, SPR_750_DMAL
, "DMAL",
5081 SPR_NOACCESS
, SPR_NOACCESS
,
5082 &spr_read_generic
, &spr_write_generic
,
5084 spr_register(env
, SPR_750_DMAU
, "DMAU",
5085 SPR_NOACCESS
, SPR_NOACCESS
,
5086 &spr_read_generic
, &spr_write_generic
,
5088 /* Hardware implementation registers */
5089 /* XXX : not implemented */
5090 spr_register(env
, SPR_HID0
, "HID0",
5091 SPR_NOACCESS
, SPR_NOACCESS
,
5092 &spr_read_generic
, &spr_write_generic
,
5094 /* XXX : not implemented */
5095 spr_register(env
, SPR_HID1
, "HID1",
5096 SPR_NOACCESS
, SPR_NOACCESS
,
5097 &spr_read_generic
, &spr_write_generic
,
5099 /* XXX : not implemented */
5100 spr_register(env
, SPR_750CL_HID2
, "HID2",
5101 SPR_NOACCESS
, SPR_NOACCESS
,
5102 &spr_read_generic
, &spr_write_generic
,
5104 /* XXX : not implemented */
5105 spr_register(env
, SPR_750CL_HID4
, "HID4",
5106 SPR_NOACCESS
, SPR_NOACCESS
,
5107 &spr_read_generic
, &spr_write_generic
,
5109 /* Quantization registers */
5110 /* XXX : not implemented */
5111 spr_register(env
, SPR_750_GQR0
, "GQR0",
5112 SPR_NOACCESS
, SPR_NOACCESS
,
5113 &spr_read_generic
, &spr_write_generic
,
5115 /* XXX : not implemented */
5116 spr_register(env
, SPR_750_GQR1
, "GQR1",
5117 SPR_NOACCESS
, SPR_NOACCESS
,
5118 &spr_read_generic
, &spr_write_generic
,
5120 /* XXX : not implemented */
5121 spr_register(env
, SPR_750_GQR2
, "GQR2",
5122 SPR_NOACCESS
, SPR_NOACCESS
,
5123 &spr_read_generic
, &spr_write_generic
,
5125 /* XXX : not implemented */
5126 spr_register(env
, SPR_750_GQR3
, "GQR3",
5127 SPR_NOACCESS
, SPR_NOACCESS
,
5128 &spr_read_generic
, &spr_write_generic
,
5130 /* XXX : not implemented */
5131 spr_register(env
, SPR_750_GQR4
, "GQR4",
5132 SPR_NOACCESS
, SPR_NOACCESS
,
5133 &spr_read_generic
, &spr_write_generic
,
5135 /* XXX : not implemented */
5136 spr_register(env
, SPR_750_GQR5
, "GQR5",
5137 SPR_NOACCESS
, SPR_NOACCESS
,
5138 &spr_read_generic
, &spr_write_generic
,
5140 /* XXX : not implemented */
5141 spr_register(env
, SPR_750_GQR6
, "GQR6",
5142 SPR_NOACCESS
, SPR_NOACCESS
,
5143 &spr_read_generic
, &spr_write_generic
,
5145 /* XXX : not implemented */
5146 spr_register(env
, SPR_750_GQR7
, "GQR7",
5147 SPR_NOACCESS
, SPR_NOACCESS
,
5148 &spr_read_generic
, &spr_write_generic
,
5150 /* Memory management */
5152 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5154 init_excp_750cl(env
);
5155 env
->dcache_line_size
= 32;
5156 env
->icache_line_size
= 32;
5157 /* Allocate hardware IRQ controller */
5158 ppc6xx_irq_init(env
);
5162 #define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5163 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5164 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5165 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5166 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5167 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5168 PPC_SEGMENT | PPC_EXTERN)
5169 #define POWERPC_INSNS2_750cx (PPC_NONE)
5170 #define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
5171 #define POWERPC_MMU_750cx (POWERPC_MMU_32B)
5172 #define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
5173 #define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
5174 #define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
5175 #define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5176 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5177 #define check_pow_750cx check_pow_hid0
5179 static void init_proc_750cx (CPUPPCState
*env
)
5181 gen_spr_ne_601(env
);
5183 /* XXX : not implemented */
5184 spr_register(env
, SPR_L2CR
, "L2CR",
5185 SPR_NOACCESS
, SPR_NOACCESS
,
5186 &spr_read_generic
, &spr_write_generic
,
5190 /* Thermal management */
5192 /* This register is not implemented but is present for compatibility */
5193 spr_register(env
, SPR_SDA
, "SDA",
5194 SPR_NOACCESS
, SPR_NOACCESS
,
5195 &spr_read_generic
, &spr_write_generic
,
5197 /* Hardware implementation registers */
5198 /* XXX : not implemented */
5199 spr_register(env
, SPR_HID0
, "HID0",
5200 SPR_NOACCESS
, SPR_NOACCESS
,
5201 &spr_read_generic
, &spr_write_generic
,
5203 /* XXX : not implemented */
5204 spr_register(env
, SPR_HID1
, "HID1",
5205 SPR_NOACCESS
, SPR_NOACCESS
,
5206 &spr_read_generic
, &spr_write_generic
,
5208 /* Memory management */
5210 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5212 init_excp_750cx(env
);
5213 env
->dcache_line_size
= 32;
5214 env
->icache_line_size
= 32;
5215 /* Allocate hardware IRQ controller */
5216 ppc6xx_irq_init(env
);
5220 #define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5221 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5222 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5223 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5224 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5225 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5226 PPC_SEGMENT | PPC_EXTERN)
5227 #define POWERPC_INSNS2_750fx (PPC_NONE)
5228 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
5229 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
5230 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
5231 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
5232 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
5233 #define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5234 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5235 #define check_pow_750fx check_pow_hid0
5237 static void init_proc_750fx (CPUPPCState
*env
)
5239 gen_spr_ne_601(env
);
5241 /* XXX : not implemented */
5242 spr_register(env
, SPR_L2CR
, "L2CR",
5243 SPR_NOACCESS
, SPR_NOACCESS
,
5244 &spr_read_generic
, &spr_write_generic
,
5248 /* Thermal management */
5250 /* XXX : not implemented */
5251 spr_register(env
, SPR_750_THRM4
, "THRM4",
5252 SPR_NOACCESS
, SPR_NOACCESS
,
5253 &spr_read_generic
, &spr_write_generic
,
5255 /* Hardware implementation registers */
5256 /* XXX : not implemented */
5257 spr_register(env
, SPR_HID0
, "HID0",
5258 SPR_NOACCESS
, SPR_NOACCESS
,
5259 &spr_read_generic
, &spr_write_generic
,
5261 /* XXX : not implemented */
5262 spr_register(env
, SPR_HID1
, "HID1",
5263 SPR_NOACCESS
, SPR_NOACCESS
,
5264 &spr_read_generic
, &spr_write_generic
,
5266 /* XXX : not implemented */
5267 spr_register(env
, SPR_750FX_HID2
, "HID2",
5268 SPR_NOACCESS
, SPR_NOACCESS
,
5269 &spr_read_generic
, &spr_write_generic
,
5271 /* Memory management */
5273 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5276 env
->dcache_line_size
= 32;
5277 env
->icache_line_size
= 32;
5278 /* Allocate hardware IRQ controller */
5279 ppc6xx_irq_init(env
);
5283 #define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5284 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5285 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5286 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5287 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5288 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5289 PPC_SEGMENT | PPC_EXTERN)
5290 #define POWERPC_INSNS2_750gx (PPC_NONE)
5291 #define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5292 #define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5293 #define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5294 #define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5295 #define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5296 #define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5297 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5298 #define check_pow_750gx check_pow_hid0
5300 static void init_proc_750gx (CPUPPCState
*env
)
5302 gen_spr_ne_601(env
);
5304 /* XXX : not implemented (XXX: different from 750fx) */
5305 spr_register(env
, SPR_L2CR
, "L2CR",
5306 SPR_NOACCESS
, SPR_NOACCESS
,
5307 &spr_read_generic
, &spr_write_generic
,
5311 /* Thermal management */
5313 /* XXX : not implemented */
5314 spr_register(env
, SPR_750_THRM4
, "THRM4",
5315 SPR_NOACCESS
, SPR_NOACCESS
,
5316 &spr_read_generic
, &spr_write_generic
,
5318 /* Hardware implementation registers */
5319 /* XXX : not implemented (XXX: different from 750fx) */
5320 spr_register(env
, SPR_HID0
, "HID0",
5321 SPR_NOACCESS
, SPR_NOACCESS
,
5322 &spr_read_generic
, &spr_write_generic
,
5324 /* XXX : not implemented */
5325 spr_register(env
, SPR_HID1
, "HID1",
5326 SPR_NOACCESS
, SPR_NOACCESS
,
5327 &spr_read_generic
, &spr_write_generic
,
5329 /* XXX : not implemented (XXX: different from 750fx) */
5330 spr_register(env
, SPR_750FX_HID2
, "HID2",
5331 SPR_NOACCESS
, SPR_NOACCESS
,
5332 &spr_read_generic
, &spr_write_generic
,
5334 /* Memory management */
5336 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5339 env
->dcache_line_size
= 32;
5340 env
->icache_line_size
= 32;
5341 /* Allocate hardware IRQ controller */
5342 ppc6xx_irq_init(env
);
5346 #define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5347 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5348 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5349 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5350 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5351 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5352 PPC_SEGMENT | PPC_EXTERN)
5353 #define POWERPC_INSNS2_745 (PPC_NONE)
5354 #define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5355 #define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5356 #define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5357 #define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5358 #define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5359 #define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5360 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5361 #define check_pow_745 check_pow_hid0
5363 static void init_proc_745 (CPUPPCState
*env
)
5365 gen_spr_ne_601(env
);
5367 gen_spr_G2_755(env
);
5370 /* Thermal management */
5372 /* Hardware implementation registers */
5373 /* XXX : not implemented */
5374 spr_register(env
, SPR_HID0
, "HID0",
5375 SPR_NOACCESS
, SPR_NOACCESS
,
5376 &spr_read_generic
, &spr_write_generic
,
5378 /* XXX : not implemented */
5379 spr_register(env
, SPR_HID1
, "HID1",
5380 SPR_NOACCESS
, SPR_NOACCESS
,
5381 &spr_read_generic
, &spr_write_generic
,
5383 /* XXX : not implemented */
5384 spr_register(env
, SPR_HID2
, "HID2",
5385 SPR_NOACCESS
, SPR_NOACCESS
,
5386 &spr_read_generic
, &spr_write_generic
,
5388 /* Memory management */
5391 gen_6xx_7xx_soft_tlb(env
, 64, 2);
5393 env
->dcache_line_size
= 32;
5394 env
->icache_line_size
= 32;
5395 /* Allocate hardware IRQ controller */
5396 ppc6xx_irq_init(env
);
5400 #define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5401 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5402 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5403 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5404 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5405 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5406 PPC_SEGMENT | PPC_EXTERN)
5407 #define POWERPC_INSNS2_755 (PPC_NONE)
5408 #define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5409 #define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5410 #define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5411 #define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5412 #define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5413 #define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5414 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5415 #define check_pow_755 check_pow_hid0
5417 static void init_proc_755 (CPUPPCState
*env
)
5419 gen_spr_ne_601(env
);
5421 gen_spr_G2_755(env
);
5424 /* L2 cache control */
5425 /* XXX : not implemented */
5426 spr_register(env
, SPR_L2CR
, "L2CR",
5427 SPR_NOACCESS
, SPR_NOACCESS
,
5428 &spr_read_generic
, &spr_write_generic
,
5430 /* XXX : not implemented */
5431 spr_register(env
, SPR_L2PMCR
, "L2PMCR",
5432 SPR_NOACCESS
, SPR_NOACCESS
,
5433 &spr_read_generic
, &spr_write_generic
,
5435 /* Thermal management */
5437 /* Hardware implementation registers */
5438 /* XXX : not implemented */
5439 spr_register(env
, SPR_HID0
, "HID0",
5440 SPR_NOACCESS
, SPR_NOACCESS
,
5441 &spr_read_generic
, &spr_write_generic
,
5443 /* XXX : not implemented */
5444 spr_register(env
, SPR_HID1
, "HID1",
5445 SPR_NOACCESS
, SPR_NOACCESS
,
5446 &spr_read_generic
, &spr_write_generic
,
5448 /* XXX : not implemented */
5449 spr_register(env
, SPR_HID2
, "HID2",
5450 SPR_NOACCESS
, SPR_NOACCESS
,
5451 &spr_read_generic
, &spr_write_generic
,
5453 /* Memory management */
5456 gen_6xx_7xx_soft_tlb(env
, 64, 2);
5458 env
->dcache_line_size
= 32;
5459 env
->icache_line_size
= 32;
5460 /* Allocate hardware IRQ controller */
5461 ppc6xx_irq_init(env
);
5464 /* PowerPC 7400 (aka G4) */
5465 #define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5466 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5467 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5468 PPC_FLOAT_STFIWX | \
5469 PPC_CACHE | PPC_CACHE_ICBI | \
5470 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5471 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5472 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5474 PPC_SEGMENT | PPC_EXTERN | \
5476 #define POWERPC_INSNS2_7400 (PPC_NONE)
5477 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5478 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5479 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5480 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
5481 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
5482 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5483 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5484 POWERPC_FLAG_BUS_CLK)
5485 #define check_pow_7400 check_pow_hid0
5487 static void init_proc_7400 (CPUPPCState
*env
)
5489 gen_spr_ne_601(env
);
5493 /* 74xx specific SPR */
5495 /* XXX : not implemented */
5496 spr_register(env
, SPR_UBAMR
, "UBAMR",
5497 &spr_read_ureg
, SPR_NOACCESS
,
5498 &spr_read_ureg
, SPR_NOACCESS
,
5500 /* XXX: this seems not implemented on all revisions. */
5501 /* XXX : not implemented */
5502 spr_register(env
, SPR_MSSCR1
, "MSSCR1",
5503 SPR_NOACCESS
, SPR_NOACCESS
,
5504 &spr_read_generic
, &spr_write_generic
,
5506 /* Thermal management */
5508 /* Memory management */
5510 init_excp_7400(env
);
5511 env
->dcache_line_size
= 32;
5512 env
->icache_line_size
= 32;
5513 /* Allocate hardware IRQ controller */
5514 ppc6xx_irq_init(env
);
5517 /* PowerPC 7410 (aka G4) */
5518 #define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5519 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5520 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5521 PPC_FLOAT_STFIWX | \
5522 PPC_CACHE | PPC_CACHE_ICBI | \
5523 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5524 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5525 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5527 PPC_SEGMENT | PPC_EXTERN | \
5529 #define POWERPC_INSNS2_7410 (PPC_NONE)
5530 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5531 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5532 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5533 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
5534 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
5535 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5536 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5537 POWERPC_FLAG_BUS_CLK)
5538 #define check_pow_7410 check_pow_hid0
5540 static void init_proc_7410 (CPUPPCState
*env
)
5542 gen_spr_ne_601(env
);
5546 /* 74xx specific SPR */
5548 /* XXX : not implemented */
5549 spr_register(env
, SPR_UBAMR
, "UBAMR",
5550 &spr_read_ureg
, SPR_NOACCESS
,
5551 &spr_read_ureg
, SPR_NOACCESS
,
5553 /* Thermal management */
5556 /* XXX : not implemented */
5557 spr_register(env
, SPR_L2PMCR
, "L2PMCR",
5558 SPR_NOACCESS
, SPR_NOACCESS
,
5559 &spr_read_generic
, &spr_write_generic
,
5562 /* XXX : not implemented */
5563 spr_register(env
, SPR_LDSTDB
, "LDSTDB",
5564 SPR_NOACCESS
, SPR_NOACCESS
,
5565 &spr_read_generic
, &spr_write_generic
,
5567 /* Memory management */
5569 init_excp_7400(env
);
5570 env
->dcache_line_size
= 32;
5571 env
->icache_line_size
= 32;
5572 /* Allocate hardware IRQ controller */
5573 ppc6xx_irq_init(env
);
5576 /* PowerPC 7440 (aka G4) */
5577 #define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5578 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5579 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5580 PPC_FLOAT_STFIWX | \
5581 PPC_CACHE | PPC_CACHE_ICBI | \
5582 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5583 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5584 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5585 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5586 PPC_SEGMENT | PPC_EXTERN | \
5588 #define POWERPC_INSNS2_7440 (PPC_NONE)
5589 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5590 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5591 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5592 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
5593 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
5594 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5595 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5596 POWERPC_FLAG_BUS_CLK)
5597 #define check_pow_7440 check_pow_hid0_74xx
5599 __attribute__ (( unused
))
5600 static void init_proc_7440 (CPUPPCState
*env
)
5602 gen_spr_ne_601(env
);
5606 /* 74xx specific SPR */
5608 /* XXX : not implemented */
5609 spr_register(env
, SPR_UBAMR
, "UBAMR",
5610 &spr_read_ureg
, SPR_NOACCESS
,
5611 &spr_read_ureg
, SPR_NOACCESS
,
5614 /* XXX : not implemented */
5615 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
5616 SPR_NOACCESS
, SPR_NOACCESS
,
5617 &spr_read_generic
, &spr_write_generic
,
5620 /* XXX : not implemented */
5621 spr_register(env
, SPR_ICTRL
, "ICTRL",
5622 SPR_NOACCESS
, SPR_NOACCESS
,
5623 &spr_read_generic
, &spr_write_generic
,
5626 /* XXX : not implemented */
5627 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
5628 SPR_NOACCESS
, SPR_NOACCESS
,
5629 &spr_read_generic
, &spr_write_generic
,
5632 /* XXX : not implemented */
5633 spr_register(env
, SPR_PMC5
, "PMC5",
5634 SPR_NOACCESS
, SPR_NOACCESS
,
5635 &spr_read_generic
, &spr_write_generic
,
5637 /* XXX : not implemented */
5638 spr_register(env
, SPR_UPMC5
, "UPMC5",
5639 &spr_read_ureg
, SPR_NOACCESS
,
5640 &spr_read_ureg
, SPR_NOACCESS
,
5642 /* XXX : not implemented */
5643 spr_register(env
, SPR_PMC6
, "PMC6",
5644 SPR_NOACCESS
, SPR_NOACCESS
,
5645 &spr_read_generic
, &spr_write_generic
,
5647 /* XXX : not implemented */
5648 spr_register(env
, SPR_UPMC6
, "UPMC6",
5649 &spr_read_ureg
, SPR_NOACCESS
,
5650 &spr_read_ureg
, SPR_NOACCESS
,
5652 /* Memory management */
5654 gen_74xx_soft_tlb(env
, 128, 2);
5655 init_excp_7450(env
);
5656 env
->dcache_line_size
= 32;
5657 env
->icache_line_size
= 32;
5658 /* Allocate hardware IRQ controller */
5659 ppc6xx_irq_init(env
);
5662 /* PowerPC 7450 (aka G4) */
5663 #define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5664 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5665 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5666 PPC_FLOAT_STFIWX | \
5667 PPC_CACHE | PPC_CACHE_ICBI | \
5668 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5669 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5670 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5671 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5672 PPC_SEGMENT | PPC_EXTERN | \
5674 #define POWERPC_INSNS2_7450 (PPC_NONE)
5675 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5676 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5677 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5678 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
5679 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
5680 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5681 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5682 POWERPC_FLAG_BUS_CLK)
5683 #define check_pow_7450 check_pow_hid0_74xx
5685 __attribute__ (( unused
))
5686 static void init_proc_7450 (CPUPPCState
*env
)
5688 gen_spr_ne_601(env
);
5692 /* 74xx specific SPR */
5694 /* Level 3 cache control */
5697 /* XXX : not implemented */
5698 spr_register(env
, SPR_L3ITCR1
, "L3ITCR1",
5699 SPR_NOACCESS
, SPR_NOACCESS
,
5700 &spr_read_generic
, &spr_write_generic
,
5703 /* XXX : not implemented */
5704 spr_register(env
, SPR_L3ITCR2
, "L3ITCR2",
5705 SPR_NOACCESS
, SPR_NOACCESS
,
5706 &spr_read_generic
, &spr_write_generic
,
5709 /* XXX : not implemented */
5710 spr_register(env
, SPR_L3ITCR3
, "L3ITCR3",
5711 SPR_NOACCESS
, SPR_NOACCESS
,
5712 &spr_read_generic
, &spr_write_generic
,
5715 /* XXX : not implemented */
5716 spr_register(env
, SPR_L3OHCR
, "L3OHCR",
5717 SPR_NOACCESS
, SPR_NOACCESS
,
5718 &spr_read_generic
, &spr_write_generic
,
5720 /* XXX : not implemented */
5721 spr_register(env
, SPR_UBAMR
, "UBAMR",
5722 &spr_read_ureg
, SPR_NOACCESS
,
5723 &spr_read_ureg
, SPR_NOACCESS
,
5726 /* XXX : not implemented */
5727 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
5728 SPR_NOACCESS
, SPR_NOACCESS
,
5729 &spr_read_generic
, &spr_write_generic
,
5732 /* XXX : not implemented */
5733 spr_register(env
, SPR_ICTRL
, "ICTRL",
5734 SPR_NOACCESS
, SPR_NOACCESS
,
5735 &spr_read_generic
, &spr_write_generic
,
5738 /* XXX : not implemented */
5739 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
5740 SPR_NOACCESS
, SPR_NOACCESS
,
5741 &spr_read_generic
, &spr_write_generic
,
5744 /* XXX : not implemented */
5745 spr_register(env
, SPR_PMC5
, "PMC5",
5746 SPR_NOACCESS
, SPR_NOACCESS
,
5747 &spr_read_generic
, &spr_write_generic
,
5749 /* XXX : not implemented */
5750 spr_register(env
, SPR_UPMC5
, "UPMC5",
5751 &spr_read_ureg
, SPR_NOACCESS
,
5752 &spr_read_ureg
, SPR_NOACCESS
,
5754 /* XXX : not implemented */
5755 spr_register(env
, SPR_PMC6
, "PMC6",
5756 SPR_NOACCESS
, SPR_NOACCESS
,
5757 &spr_read_generic
, &spr_write_generic
,
5759 /* XXX : not implemented */
5760 spr_register(env
, SPR_UPMC6
, "UPMC6",
5761 &spr_read_ureg
, SPR_NOACCESS
,
5762 &spr_read_ureg
, SPR_NOACCESS
,
5764 /* Memory management */
5766 gen_74xx_soft_tlb(env
, 128, 2);
5767 init_excp_7450(env
);
5768 env
->dcache_line_size
= 32;
5769 env
->icache_line_size
= 32;
5770 /* Allocate hardware IRQ controller */
5771 ppc6xx_irq_init(env
);
5774 /* PowerPC 7445 (aka G4) */
5775 #define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5776 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5777 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5778 PPC_FLOAT_STFIWX | \
5779 PPC_CACHE | PPC_CACHE_ICBI | \
5780 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5781 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5782 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5783 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5784 PPC_SEGMENT | PPC_EXTERN | \
5786 #define POWERPC_INSNS2_7445 (PPC_NONE)
5787 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5788 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5789 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5790 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
5791 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
5792 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5793 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5794 POWERPC_FLAG_BUS_CLK)
5795 #define check_pow_7445 check_pow_hid0_74xx
5797 __attribute__ (( unused
))
5798 static void init_proc_7445 (CPUPPCState
*env
)
5800 gen_spr_ne_601(env
);
5804 /* 74xx specific SPR */
5807 /* XXX : not implemented */
5808 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
5809 SPR_NOACCESS
, SPR_NOACCESS
,
5810 &spr_read_generic
, &spr_write_generic
,
5813 /* XXX : not implemented */
5814 spr_register(env
, SPR_ICTRL
, "ICTRL",
5815 SPR_NOACCESS
, SPR_NOACCESS
,
5816 &spr_read_generic
, &spr_write_generic
,
5819 /* XXX : not implemented */
5820 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
5821 SPR_NOACCESS
, SPR_NOACCESS
,
5822 &spr_read_generic
, &spr_write_generic
,
5825 /* XXX : not implemented */
5826 spr_register(env
, SPR_PMC5
, "PMC5",
5827 SPR_NOACCESS
, SPR_NOACCESS
,
5828 &spr_read_generic
, &spr_write_generic
,
5830 /* XXX : not implemented */
5831 spr_register(env
, SPR_UPMC5
, "UPMC5",
5832 &spr_read_ureg
, SPR_NOACCESS
,
5833 &spr_read_ureg
, SPR_NOACCESS
,
5835 /* XXX : not implemented */
5836 spr_register(env
, SPR_PMC6
, "PMC6",
5837 SPR_NOACCESS
, SPR_NOACCESS
,
5838 &spr_read_generic
, &spr_write_generic
,
5840 /* XXX : not implemented */
5841 spr_register(env
, SPR_UPMC6
, "UPMC6",
5842 &spr_read_ureg
, SPR_NOACCESS
,
5843 &spr_read_ureg
, SPR_NOACCESS
,
5846 spr_register(env
, SPR_SPRG4
, "SPRG4",
5847 SPR_NOACCESS
, SPR_NOACCESS
,
5848 &spr_read_generic
, &spr_write_generic
,
5850 spr_register(env
, SPR_USPRG4
, "USPRG4",
5851 &spr_read_ureg
, SPR_NOACCESS
,
5852 &spr_read_ureg
, SPR_NOACCESS
,
5854 spr_register(env
, SPR_SPRG5
, "SPRG5",
5855 SPR_NOACCESS
, SPR_NOACCESS
,
5856 &spr_read_generic
, &spr_write_generic
,
5858 spr_register(env
, SPR_USPRG5
, "USPRG5",
5859 &spr_read_ureg
, SPR_NOACCESS
,
5860 &spr_read_ureg
, SPR_NOACCESS
,
5862 spr_register(env
, SPR_SPRG6
, "SPRG6",
5863 SPR_NOACCESS
, SPR_NOACCESS
,
5864 &spr_read_generic
, &spr_write_generic
,
5866 spr_register(env
, SPR_USPRG6
, "USPRG6",
5867 &spr_read_ureg
, SPR_NOACCESS
,
5868 &spr_read_ureg
, SPR_NOACCESS
,
5870 spr_register(env
, SPR_SPRG7
, "SPRG7",
5871 SPR_NOACCESS
, SPR_NOACCESS
,
5872 &spr_read_generic
, &spr_write_generic
,
5874 spr_register(env
, SPR_USPRG7
, "USPRG7",
5875 &spr_read_ureg
, SPR_NOACCESS
,
5876 &spr_read_ureg
, SPR_NOACCESS
,
5878 /* Memory management */
5881 gen_74xx_soft_tlb(env
, 128, 2);
5882 init_excp_7450(env
);
5883 env
->dcache_line_size
= 32;
5884 env
->icache_line_size
= 32;
5885 /* Allocate hardware IRQ controller */
5886 ppc6xx_irq_init(env
);
5889 /* PowerPC 7455 (aka G4) */
5890 #define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5891 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5892 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5893 PPC_FLOAT_STFIWX | \
5894 PPC_CACHE | PPC_CACHE_ICBI | \
5895 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5896 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5897 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5898 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5899 PPC_SEGMENT | PPC_EXTERN | \
5901 #define POWERPC_INSNS2_7455 (PPC_NONE)
5902 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
5903 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
5904 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
5905 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
5906 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
5907 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5908 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5909 POWERPC_FLAG_BUS_CLK)
5910 #define check_pow_7455 check_pow_hid0_74xx
5912 __attribute__ (( unused
))
5913 static void init_proc_7455 (CPUPPCState
*env
)
5915 gen_spr_ne_601(env
);
5919 /* 74xx specific SPR */
5921 /* Level 3 cache control */
5924 /* XXX : not implemented */
5925 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
5926 SPR_NOACCESS
, SPR_NOACCESS
,
5927 &spr_read_generic
, &spr_write_generic
,
5930 /* XXX : not implemented */
5931 spr_register(env
, SPR_ICTRL
, "ICTRL",
5932 SPR_NOACCESS
, SPR_NOACCESS
,
5933 &spr_read_generic
, &spr_write_generic
,
5936 /* XXX : not implemented */
5937 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
5938 SPR_NOACCESS
, SPR_NOACCESS
,
5939 &spr_read_generic
, &spr_write_generic
,
5942 /* XXX : not implemented */
5943 spr_register(env
, SPR_PMC5
, "PMC5",
5944 SPR_NOACCESS
, SPR_NOACCESS
,
5945 &spr_read_generic
, &spr_write_generic
,
5947 /* XXX : not implemented */
5948 spr_register(env
, SPR_UPMC5
, "UPMC5",
5949 &spr_read_ureg
, SPR_NOACCESS
,
5950 &spr_read_ureg
, SPR_NOACCESS
,
5952 /* XXX : not implemented */
5953 spr_register(env
, SPR_PMC6
, "PMC6",
5954 SPR_NOACCESS
, SPR_NOACCESS
,
5955 &spr_read_generic
, &spr_write_generic
,
5957 /* XXX : not implemented */
5958 spr_register(env
, SPR_UPMC6
, "UPMC6",
5959 &spr_read_ureg
, SPR_NOACCESS
,
5960 &spr_read_ureg
, SPR_NOACCESS
,
5963 spr_register(env
, SPR_SPRG4
, "SPRG4",
5964 SPR_NOACCESS
, SPR_NOACCESS
,
5965 &spr_read_generic
, &spr_write_generic
,
5967 spr_register(env
, SPR_USPRG4
, "USPRG4",
5968 &spr_read_ureg
, SPR_NOACCESS
,
5969 &spr_read_ureg
, SPR_NOACCESS
,
5971 spr_register(env
, SPR_SPRG5
, "SPRG5",
5972 SPR_NOACCESS
, SPR_NOACCESS
,
5973 &spr_read_generic
, &spr_write_generic
,
5975 spr_register(env
, SPR_USPRG5
, "USPRG5",
5976 &spr_read_ureg
, SPR_NOACCESS
,
5977 &spr_read_ureg
, SPR_NOACCESS
,
5979 spr_register(env
, SPR_SPRG6
, "SPRG6",
5980 SPR_NOACCESS
, SPR_NOACCESS
,
5981 &spr_read_generic
, &spr_write_generic
,
5983 spr_register(env
, SPR_USPRG6
, "USPRG6",
5984 &spr_read_ureg
, SPR_NOACCESS
,
5985 &spr_read_ureg
, SPR_NOACCESS
,
5987 spr_register(env
, SPR_SPRG7
, "SPRG7",
5988 SPR_NOACCESS
, SPR_NOACCESS
,
5989 &spr_read_generic
, &spr_write_generic
,
5991 spr_register(env
, SPR_USPRG7
, "USPRG7",
5992 &spr_read_ureg
, SPR_NOACCESS
,
5993 &spr_read_ureg
, SPR_NOACCESS
,
5995 /* Memory management */
5998 gen_74xx_soft_tlb(env
, 128, 2);
5999 init_excp_7450(env
);
6000 env
->dcache_line_size
= 32;
6001 env
->icache_line_size
= 32;
6002 /* Allocate hardware IRQ controller */
6003 ppc6xx_irq_init(env
);
6006 /* PowerPC 7457 (aka G4) */
6007 #define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6008 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6009 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6010 PPC_FLOAT_STFIWX | \
6011 PPC_CACHE | PPC_CACHE_ICBI | \
6012 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
6013 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6014 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6015 PPC_MEM_TLBIA | PPC_74xx_TLB | \
6016 PPC_SEGMENT | PPC_EXTERN | \
6018 #define POWERPC_INSNS2_7457 (PPC_NONE)
6019 #define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
6020 #define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
6021 #define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
6022 #define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
6023 #define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
6024 #define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6025 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6026 POWERPC_FLAG_BUS_CLK)
6027 #define check_pow_7457 check_pow_hid0_74xx
6029 __attribute__ (( unused
))
6030 static void init_proc_7457 (CPUPPCState
*env
)
6032 gen_spr_ne_601(env
);
6036 /* 74xx specific SPR */
6038 /* Level 3 cache control */
6041 /* XXX : not implemented */
6042 spr_register(env
, SPR_L3ITCR1
, "L3ITCR1",
6043 SPR_NOACCESS
, SPR_NOACCESS
,
6044 &spr_read_generic
, &spr_write_generic
,
6047 /* XXX : not implemented */
6048 spr_register(env
, SPR_L3ITCR2
, "L3ITCR2",
6049 SPR_NOACCESS
, SPR_NOACCESS
,
6050 &spr_read_generic
, &spr_write_generic
,
6053 /* XXX : not implemented */
6054 spr_register(env
, SPR_L3ITCR3
, "L3ITCR3",
6055 SPR_NOACCESS
, SPR_NOACCESS
,
6056 &spr_read_generic
, &spr_write_generic
,
6059 /* XXX : not implemented */
6060 spr_register(env
, SPR_L3OHCR
, "L3OHCR",
6061 SPR_NOACCESS
, SPR_NOACCESS
,
6062 &spr_read_generic
, &spr_write_generic
,
6065 /* XXX : not implemented */
6066 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
6067 SPR_NOACCESS
, SPR_NOACCESS
,
6068 &spr_read_generic
, &spr_write_generic
,
6071 /* XXX : not implemented */
6072 spr_register(env
, SPR_ICTRL
, "ICTRL",
6073 SPR_NOACCESS
, SPR_NOACCESS
,
6074 &spr_read_generic
, &spr_write_generic
,
6077 /* XXX : not implemented */
6078 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
6079 SPR_NOACCESS
, SPR_NOACCESS
,
6080 &spr_read_generic
, &spr_write_generic
,
6083 /* XXX : not implemented */
6084 spr_register(env
, SPR_PMC5
, "PMC5",
6085 SPR_NOACCESS
, SPR_NOACCESS
,
6086 &spr_read_generic
, &spr_write_generic
,
6088 /* XXX : not implemented */
6089 spr_register(env
, SPR_UPMC5
, "UPMC5",
6090 &spr_read_ureg
, SPR_NOACCESS
,
6091 &spr_read_ureg
, SPR_NOACCESS
,
6093 /* XXX : not implemented */
6094 spr_register(env
, SPR_PMC6
, "PMC6",
6095 SPR_NOACCESS
, SPR_NOACCESS
,
6096 &spr_read_generic
, &spr_write_generic
,
6098 /* XXX : not implemented */
6099 spr_register(env
, SPR_UPMC6
, "UPMC6",
6100 &spr_read_ureg
, SPR_NOACCESS
,
6101 &spr_read_ureg
, SPR_NOACCESS
,
6104 spr_register(env
, SPR_SPRG4
, "SPRG4",
6105 SPR_NOACCESS
, SPR_NOACCESS
,
6106 &spr_read_generic
, &spr_write_generic
,
6108 spr_register(env
, SPR_USPRG4
, "USPRG4",
6109 &spr_read_ureg
, SPR_NOACCESS
,
6110 &spr_read_ureg
, SPR_NOACCESS
,
6112 spr_register(env
, SPR_SPRG5
, "SPRG5",
6113 SPR_NOACCESS
, SPR_NOACCESS
,
6114 &spr_read_generic
, &spr_write_generic
,
6116 spr_register(env
, SPR_USPRG5
, "USPRG5",
6117 &spr_read_ureg
, SPR_NOACCESS
,
6118 &spr_read_ureg
, SPR_NOACCESS
,
6120 spr_register(env
, SPR_SPRG6
, "SPRG6",
6121 SPR_NOACCESS
, SPR_NOACCESS
,
6122 &spr_read_generic
, &spr_write_generic
,
6124 spr_register(env
, SPR_USPRG6
, "USPRG6",
6125 &spr_read_ureg
, SPR_NOACCESS
,
6126 &spr_read_ureg
, SPR_NOACCESS
,
6128 spr_register(env
, SPR_SPRG7
, "SPRG7",
6129 SPR_NOACCESS
, SPR_NOACCESS
,
6130 &spr_read_generic
, &spr_write_generic
,
6132 spr_register(env
, SPR_USPRG7
, "USPRG7",
6133 &spr_read_ureg
, SPR_NOACCESS
,
6134 &spr_read_ureg
, SPR_NOACCESS
,
6136 /* Memory management */
6139 gen_74xx_soft_tlb(env
, 128, 2);
6140 init_excp_7450(env
);
6141 env
->dcache_line_size
= 32;
6142 env
->icache_line_size
= 32;
6143 /* Allocate hardware IRQ controller */
6144 ppc6xx_irq_init(env
);
6147 #if defined (TARGET_PPC64)
6149 #define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6150 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6151 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6152 PPC_FLOAT_STFIWX | \
6153 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6154 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6155 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6156 PPC_64B | PPC_ALTIVEC | \
6157 PPC_SEGMENT_64B | PPC_SLBI)
6158 #define POWERPC_INSNS2_970 (PPC_NONE)
6159 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
6160 #define POWERPC_MMU_970 (POWERPC_MMU_64B)
6161 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
6162 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
6163 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
6164 #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6165 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6166 POWERPC_FLAG_BUS_CLK)
6168 #if defined(CONFIG_USER_ONLY)
6169 #define POWERPC970_HID5_INIT 0x00000080
6171 #define POWERPC970_HID5_INIT 0x00000000
6174 static int check_pow_970 (CPUPPCState
*env
)
6176 if (env
->spr
[SPR_HID0
] & 0x00600000)
6182 static void init_proc_970 (CPUPPCState
*env
)
6184 gen_spr_ne_601(env
);
6188 /* Hardware implementation registers */
6189 /* XXX : not implemented */
6190 spr_register(env
, SPR_HID0
, "HID0",
6191 SPR_NOACCESS
, SPR_NOACCESS
,
6192 &spr_read_generic
, &spr_write_clear
,
6194 /* XXX : not implemented */
6195 spr_register(env
, SPR_HID1
, "HID1",
6196 SPR_NOACCESS
, SPR_NOACCESS
,
6197 &spr_read_generic
, &spr_write_generic
,
6199 /* XXX : not implemented */
6200 spr_register(env
, SPR_750FX_HID2
, "HID2",
6201 SPR_NOACCESS
, SPR_NOACCESS
,
6202 &spr_read_generic
, &spr_write_generic
,
6204 /* XXX : not implemented */
6205 spr_register(env
, SPR_970_HID5
, "HID5",
6206 SPR_NOACCESS
, SPR_NOACCESS
,
6207 &spr_read_generic
, &spr_write_generic
,
6208 POWERPC970_HID5_INIT
);
6209 /* XXX : not implemented */
6210 spr_register(env
, SPR_L2CR
, "L2CR",
6211 SPR_NOACCESS
, SPR_NOACCESS
,
6212 &spr_read_generic
, &spr_write_generic
,
6214 /* Memory management */
6215 /* XXX: not correct */
6217 /* XXX : not implemented */
6218 spr_register(env
, SPR_MMUCFG
, "MMUCFG",
6219 SPR_NOACCESS
, SPR_NOACCESS
,
6220 &spr_read_generic
, SPR_NOACCESS
,
6221 0x00000000); /* TOFIX */
6222 /* XXX : not implemented */
6223 spr_register(env
, SPR_MMUCSR0
, "MMUCSR0",
6224 SPR_NOACCESS
, SPR_NOACCESS
,
6225 &spr_read_generic
, &spr_write_generic
,
6226 0x00000000); /* TOFIX */
6227 spr_register(env
, SPR_HIOR
, "SPR_HIOR",
6228 SPR_NOACCESS
, SPR_NOACCESS
,
6229 &spr_read_hior
, &spr_write_hior
,
6231 #if !defined(CONFIG_USER_ONLY)
6235 env
->dcache_line_size
= 128;
6236 env
->icache_line_size
= 128;
6237 /* Allocate hardware IRQ controller */
6238 ppc970_irq_init(env
);
6239 /* Can't find information on what this should be on reset. This
6240 * value is the one used by 74xx processors. */
6241 vscr_init(env
, 0x00010000);
6244 /* PowerPC 970FX (aka G5) */
6245 #define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6246 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6247 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6248 PPC_FLOAT_STFIWX | \
6249 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6250 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6251 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6252 PPC_64B | PPC_ALTIVEC | \
6253 PPC_SEGMENT_64B | PPC_SLBI)
6254 #define POWERPC_INSNS2_970FX (PPC_NONE)
6255 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
6256 #define POWERPC_MMU_970FX (POWERPC_MMU_64B)
6257 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
6258 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
6259 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
6260 #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6261 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6262 POWERPC_FLAG_BUS_CLK)
6264 static int check_pow_970FX (CPUPPCState
*env
)
6266 if (env
->spr
[SPR_HID0
] & 0x00600000)
6272 static void init_proc_970FX (CPUPPCState
*env
)
6274 gen_spr_ne_601(env
);
6278 /* Hardware implementation registers */
6279 /* XXX : not implemented */
6280 spr_register(env
, SPR_HID0
, "HID0",
6281 SPR_NOACCESS
, SPR_NOACCESS
,
6282 &spr_read_generic
, &spr_write_clear
,
6284 /* XXX : not implemented */
6285 spr_register(env
, SPR_HID1
, "HID1",
6286 SPR_NOACCESS
, SPR_NOACCESS
,
6287 &spr_read_generic
, &spr_write_generic
,
6289 /* XXX : not implemented */
6290 spr_register(env
, SPR_750FX_HID2
, "HID2",
6291 SPR_NOACCESS
, SPR_NOACCESS
,
6292 &spr_read_generic
, &spr_write_generic
,
6294 /* XXX : not implemented */
6295 spr_register(env
, SPR_970_HID5
, "HID5",
6296 SPR_NOACCESS
, SPR_NOACCESS
,
6297 &spr_read_generic
, &spr_write_generic
,
6298 POWERPC970_HID5_INIT
);
6299 /* XXX : not implemented */
6300 spr_register(env
, SPR_L2CR
, "L2CR",
6301 SPR_NOACCESS
, SPR_NOACCESS
,
6302 &spr_read_generic
, &spr_write_generic
,
6304 /* Memory management */
6305 /* XXX: not correct */
6307 /* XXX : not implemented */
6308 spr_register(env
, SPR_MMUCFG
, "MMUCFG",
6309 SPR_NOACCESS
, SPR_NOACCESS
,
6310 &spr_read_generic
, SPR_NOACCESS
,
6311 0x00000000); /* TOFIX */
6312 /* XXX : not implemented */
6313 spr_register(env
, SPR_MMUCSR0
, "MMUCSR0",
6314 SPR_NOACCESS
, SPR_NOACCESS
,
6315 &spr_read_generic
, &spr_write_generic
,
6316 0x00000000); /* TOFIX */
6317 spr_register(env
, SPR_HIOR
, "SPR_HIOR",
6318 SPR_NOACCESS
, SPR_NOACCESS
,
6319 &spr_read_hior
, &spr_write_hior
,
6321 spr_register(env
, SPR_CTRL
, "SPR_CTRL",
6322 SPR_NOACCESS
, SPR_NOACCESS
,
6323 &spr_read_generic
, &spr_write_generic
,
6325 spr_register(env
, SPR_UCTRL
, "SPR_UCTRL",
6326 SPR_NOACCESS
, SPR_NOACCESS
,
6327 &spr_read_generic
, &spr_write_generic
,
6329 spr_register(env
, SPR_VRSAVE
, "SPR_VRSAVE",
6330 &spr_read_generic
, &spr_write_generic
,
6331 &spr_read_generic
, &spr_write_generic
,
6333 #if !defined(CONFIG_USER_ONLY)
6337 env
->dcache_line_size
= 128;
6338 env
->icache_line_size
= 128;
6339 /* Allocate hardware IRQ controller */
6340 ppc970_irq_init(env
);
6341 /* Can't find information on what this should be on reset. This
6342 * value is the one used by 74xx processors. */
6343 vscr_init(env
, 0x00010000);
6346 /* PowerPC 970 GX */
6347 #define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6348 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6349 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6350 PPC_FLOAT_STFIWX | \
6351 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6352 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6353 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6354 PPC_64B | PPC_ALTIVEC | \
6355 PPC_SEGMENT_64B | PPC_SLBI)
6356 #define POWERPC_INSNS2_970GX (PPC_NONE)
6357 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
6358 #define POWERPC_MMU_970GX (POWERPC_MMU_64B)
6359 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6360 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
6361 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
6362 #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6363 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6364 POWERPC_FLAG_BUS_CLK)
6366 static int check_pow_970GX (CPUPPCState
*env
)
6368 if (env
->spr
[SPR_HID0
] & 0x00600000)
6374 static void init_proc_970GX (CPUPPCState
*env
)
6376 gen_spr_ne_601(env
);
6380 /* Hardware implementation registers */
6381 /* XXX : not implemented */
6382 spr_register(env
, SPR_HID0
, "HID0",
6383 SPR_NOACCESS
, SPR_NOACCESS
,
6384 &spr_read_generic
, &spr_write_clear
,
6386 /* XXX : not implemented */
6387 spr_register(env
, SPR_HID1
, "HID1",
6388 SPR_NOACCESS
, SPR_NOACCESS
,
6389 &spr_read_generic
, &spr_write_generic
,
6391 /* XXX : not implemented */
6392 spr_register(env
, SPR_750FX_HID2
, "HID2",
6393 SPR_NOACCESS
, SPR_NOACCESS
,
6394 &spr_read_generic
, &spr_write_generic
,
6396 /* XXX : not implemented */
6397 spr_register(env
, SPR_970_HID5
, "HID5",
6398 SPR_NOACCESS
, SPR_NOACCESS
,
6399 &spr_read_generic
, &spr_write_generic
,
6400 POWERPC970_HID5_INIT
);
6401 /* XXX : not implemented */
6402 spr_register(env
, SPR_L2CR
, "L2CR",
6403 SPR_NOACCESS
, SPR_NOACCESS
,
6404 &spr_read_generic
, &spr_write_generic
,
6406 /* Memory management */
6407 /* XXX: not correct */
6409 /* XXX : not implemented */
6410 spr_register(env
, SPR_MMUCFG
, "MMUCFG",
6411 SPR_NOACCESS
, SPR_NOACCESS
,
6412 &spr_read_generic
, SPR_NOACCESS
,
6413 0x00000000); /* TOFIX */
6414 /* XXX : not implemented */
6415 spr_register(env
, SPR_MMUCSR0
, "MMUCSR0",
6416 SPR_NOACCESS
, SPR_NOACCESS
,
6417 &spr_read_generic
, &spr_write_generic
,
6418 0x00000000); /* TOFIX */
6419 spr_register(env
, SPR_HIOR
, "SPR_HIOR",
6420 SPR_NOACCESS
, SPR_NOACCESS
,
6421 &spr_read_hior
, &spr_write_hior
,
6423 #if !defined(CONFIG_USER_ONLY)
6427 env
->dcache_line_size
= 128;
6428 env
->icache_line_size
= 128;
6429 /* Allocate hardware IRQ controller */
6430 ppc970_irq_init(env
);
6431 /* Can't find information on what this should be on reset. This
6432 * value is the one used by 74xx processors. */
6433 vscr_init(env
, 0x00010000);
6436 /* PowerPC 970 MP */
6437 #define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6438 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6439 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6440 PPC_FLOAT_STFIWX | \
6441 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6442 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6443 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6444 PPC_64B | PPC_ALTIVEC | \
6445 PPC_SEGMENT_64B | PPC_SLBI)
6446 #define POWERPC_INSNS2_970MP (PPC_NONE)
6447 #define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6448 #define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6449 #define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6450 #define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6451 #define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6452 #define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6453 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6454 POWERPC_FLAG_BUS_CLK)
6456 static int check_pow_970MP (CPUPPCState
*env
)
6458 if (env
->spr
[SPR_HID0
] & 0x01C00000)
6464 static void init_proc_970MP (CPUPPCState
*env
)
6466 gen_spr_ne_601(env
);
6470 /* Hardware implementation registers */
6471 /* XXX : not implemented */
6472 spr_register(env
, SPR_HID0
, "HID0",
6473 SPR_NOACCESS
, SPR_NOACCESS
,
6474 &spr_read_generic
, &spr_write_clear
,
6476 /* XXX : not implemented */
6477 spr_register(env
, SPR_HID1
, "HID1",
6478 SPR_NOACCESS
, SPR_NOACCESS
,
6479 &spr_read_generic
, &spr_write_generic
,
6481 /* XXX : not implemented */
6482 spr_register(env
, SPR_750FX_HID2
, "HID2",
6483 SPR_NOACCESS
, SPR_NOACCESS
,
6484 &spr_read_generic
, &spr_write_generic
,
6486 /* XXX : not implemented */
6487 spr_register(env
, SPR_970_HID5
, "HID5",
6488 SPR_NOACCESS
, SPR_NOACCESS
,
6489 &spr_read_generic
, &spr_write_generic
,
6490 POWERPC970_HID5_INIT
);
6491 /* XXX : not implemented */
6492 spr_register(env
, SPR_L2CR
, "L2CR",
6493 SPR_NOACCESS
, SPR_NOACCESS
,
6494 &spr_read_generic
, &spr_write_generic
,
6496 /* Memory management */
6497 /* XXX: not correct */
6499 /* XXX : not implemented */
6500 spr_register(env
, SPR_MMUCFG
, "MMUCFG",
6501 SPR_NOACCESS
, SPR_NOACCESS
,
6502 &spr_read_generic
, SPR_NOACCESS
,
6503 0x00000000); /* TOFIX */
6504 /* XXX : not implemented */
6505 spr_register(env
, SPR_MMUCSR0
, "MMUCSR0",
6506 SPR_NOACCESS
, SPR_NOACCESS
,
6507 &spr_read_generic
, &spr_write_generic
,
6508 0x00000000); /* TOFIX */
6509 spr_register(env
, SPR_HIOR
, "SPR_HIOR",
6510 SPR_NOACCESS
, SPR_NOACCESS
,
6511 &spr_read_hior
, &spr_write_hior
,
6513 #if !defined(CONFIG_USER_ONLY)
6517 env
->dcache_line_size
= 128;
6518 env
->icache_line_size
= 128;
6519 /* Allocate hardware IRQ controller */
6520 ppc970_irq_init(env
);
6521 /* Can't find information on what this should be on reset. This
6522 * value is the one used by 74xx processors. */
6523 vscr_init(env
, 0x00010000);
6526 #if defined(TARGET_PPC64)
6528 #define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6529 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6530 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6531 PPC_FLOAT_STFIWX | \
6532 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6533 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6534 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6535 PPC_64B | PPC_ALTIVEC | \
6536 PPC_SEGMENT_64B | PPC_SLBI | \
6537 PPC_POPCNTB | PPC_POPCNTWD)
6538 #define POWERPC_INSNS2_POWER7 (PPC_NONE)
6539 #define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
6540 #define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
6541 #define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
6542 #define POWERPC_INPUT_POWER7 (PPC_FLAGS_INPUT_POWER7)
6543 #define POWERPC_BFDM_POWER7 (bfd_mach_ppc64)
6544 #define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6545 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6546 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR)
6547 #define check_pow_POWER7 check_pow_nocheck
6549 static void init_proc_POWER7 (CPUPPCState
*env
)
6551 gen_spr_ne_601(env
);
6555 #if !defined(CONFIG_USER_ONLY)
6556 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6557 spr_register(env
, SPR_PURR
, "PURR",
6558 &spr_read_purr
, SPR_NOACCESS
,
6559 &spr_read_purr
, SPR_NOACCESS
,
6561 spr_register(env
, SPR_SPURR
, "SPURR",
6562 &spr_read_purr
, SPR_NOACCESS
,
6563 &spr_read_purr
, SPR_NOACCESS
,
6565 spr_register(env
, SPR_CFAR
, "SPR_CFAR",
6566 SPR_NOACCESS
, SPR_NOACCESS
,
6567 &spr_read_cfar
, &spr_write_cfar
,
6569 spr_register(env
, SPR_DSCR
, "SPR_DSCR",
6570 SPR_NOACCESS
, SPR_NOACCESS
,
6571 &spr_read_generic
, &spr_write_generic
,
6573 #endif /* !CONFIG_USER_ONLY */
6574 /* Memory management */
6575 /* XXX : not implemented */
6576 spr_register(env
, SPR_MMUCFG
, "MMUCFG",
6577 SPR_NOACCESS
, SPR_NOACCESS
,
6578 &spr_read_generic
, SPR_NOACCESS
,
6579 0x00000000); /* TOFIX */
6580 /* XXX : not implemented */
6581 spr_register(env
, SPR_CTRL
, "SPR_CTRLT",
6582 SPR_NOACCESS
, SPR_NOACCESS
,
6583 &spr_read_generic
, &spr_write_generic
,
6585 spr_register(env
, SPR_UCTRL
, "SPR_CTRLF",
6586 SPR_NOACCESS
, SPR_NOACCESS
,
6587 &spr_read_generic
, &spr_write_generic
,
6589 spr_register(env
, SPR_VRSAVE
, "SPR_VRSAVE",
6590 &spr_read_generic
, &spr_write_generic
,
6591 &spr_read_generic
, &spr_write_generic
,
6593 #if !defined(CONFIG_USER_ONLY)
6596 init_excp_POWER7(env
);
6597 env
->dcache_line_size
= 128;
6598 env
->icache_line_size
= 128;
6599 /* Allocate hardware IRQ controller */
6600 ppcPOWER7_irq_init(env
);
6601 /* Can't find information on what this should be on reset. This
6602 * value is the one used by 74xx processors. */
6603 vscr_init(env
, 0x00010000);
6605 #endif /* TARGET_PPC64 */
6608 #define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6609 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6610 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6611 PPC_FLOAT_STFIWX | \
6612 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6613 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6614 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6615 PPC_SEGMENT | PPC_EXTERN | \
6617 #define POWERPC_INSNS2_620 (PPC_NONE)
6618 #define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6619 //#define POWERPC_MMU_620 (POWERPC_MMU_620)
6620 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
6621 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
6622 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
6623 #define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
6624 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
6625 #define check_pow_620 check_pow_nocheck /* Check this */
6627 __attribute__ (( unused
))
6628 static void init_proc_620 (CPUPPCState
*env
)
6630 gen_spr_ne_601(env
);
6634 /* Hardware implementation registers */
6635 /* XXX : not implemented */
6636 spr_register(env
, SPR_HID0
, "HID0",
6637 SPR_NOACCESS
, SPR_NOACCESS
,
6638 &spr_read_generic
, &spr_write_generic
,
6640 /* Memory management */
6643 env
->dcache_line_size
= 64;
6644 env
->icache_line_size
= 64;
6645 /* Allocate hardware IRQ controller */
6646 ppc6xx_irq_init(env
);
6648 #endif /* defined (TARGET_PPC64) */
6650 /* Default 32 bits PowerPC target will be 604 */
6651 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
6652 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
6653 #define POWERPC_INSNS2_PPC32 POWERPC_INSNS2_604
6654 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6655 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
6656 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6657 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
6658 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
6659 #define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
6660 #define check_pow_PPC32 check_pow_604
6661 #define init_proc_PPC32 init_proc_604
6663 /* Default 64 bits PowerPC target will be 970 FX */
6664 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6665 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
6666 #define POWERPC_INSNS2_PPC64 POWERPC_INSNS2_970FX
6667 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6668 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6669 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6670 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
6671 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
6672 #define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
6673 #define check_pow_PPC64 check_pow_970FX
6674 #define init_proc_PPC64 init_proc_970FX
6676 /* Default PowerPC target will be PowerPC 32 */
6677 #if defined (TARGET_PPC64) && 0 // XXX: TODO
6678 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6679 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6680 #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC64
6681 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6682 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6683 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6684 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6685 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
6686 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
6687 #define check_pow_DEFAULT check_pow_PPC64
6688 #define init_proc_DEFAULT init_proc_PPC64
6690 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6691 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6692 #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC32
6693 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6694 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6695 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6696 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6697 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
6698 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
6699 #define check_pow_DEFAULT check_pow_PPC32
6700 #define init_proc_DEFAULT init_proc_PPC32
6703 /*****************************************************************************/
6704 /* PVR definitions for most known PowerPC */
6706 /* PowerPC 401 family */
6707 /* Generic PowerPC 401 */
6708 #define CPU_POWERPC_401 CPU_POWERPC_401G2
6709 /* PowerPC 401 cores */
6710 CPU_POWERPC_401A1
= 0x00210000,
6711 CPU_POWERPC_401B2
= 0x00220000,
6713 CPU_POWERPC_401B3
= xxx
,
6715 CPU_POWERPC_401C2
= 0x00230000,
6716 CPU_POWERPC_401D2
= 0x00240000,
6717 CPU_POWERPC_401E2
= 0x00250000,
6718 CPU_POWERPC_401F2
= 0x00260000,
6719 CPU_POWERPC_401G2
= 0x00270000,
6720 /* PowerPC 401 microcontrolers */
6722 CPU_POWERPC_401GF
= xxx
,
6724 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
6725 /* IBM Processor for Network Resources */
6726 CPU_POWERPC_COBRA
= 0x10100000, /* XXX: 405 ? */
6728 CPU_POWERPC_XIPCHIP
= xxx
,
6730 /* PowerPC 403 family */
6731 /* Generic PowerPC 403 */
6732 #define CPU_POWERPC_403 CPU_POWERPC_403GC
6733 /* PowerPC 403 microcontrollers */
6734 CPU_POWERPC_403GA
= 0x00200011,
6735 CPU_POWERPC_403GB
= 0x00200100,
6736 CPU_POWERPC_403GC
= 0x00200200,
6737 CPU_POWERPC_403GCX
= 0x00201400,
6739 CPU_POWERPC_403GP
= xxx
,
6741 /* PowerPC 405 family */
6742 /* Generic PowerPC 405 */
6743 #define CPU_POWERPC_405 CPU_POWERPC_405D4
6744 /* PowerPC 405 cores */
6746 CPU_POWERPC_405A3
= xxx
,
6749 CPU_POWERPC_405A4
= xxx
,
6752 CPU_POWERPC_405B3
= xxx
,
6755 CPU_POWERPC_405B4
= xxx
,
6758 CPU_POWERPC_405C3
= xxx
,
6761 CPU_POWERPC_405C4
= xxx
,
6763 CPU_POWERPC_405D2
= 0x20010000,
6765 CPU_POWERPC_405D3
= xxx
,
6767 CPU_POWERPC_405D4
= 0x41810000,
6769 CPU_POWERPC_405D5
= xxx
,
6772 CPU_POWERPC_405E4
= xxx
,
6775 CPU_POWERPC_405F4
= xxx
,
6778 CPU_POWERPC_405F5
= xxx
,
6781 CPU_POWERPC_405F6
= xxx
,
6783 /* PowerPC 405 microcontrolers */
6784 /* XXX: missing 0x200108a0 */
6785 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6786 CPU_POWERPC_405CRa
= 0x40110041,
6787 CPU_POWERPC_405CRb
= 0x401100C5,
6788 CPU_POWERPC_405CRc
= 0x40110145,
6789 CPU_POWERPC_405EP
= 0x51210950,
6791 CPU_POWERPC_405EXr
= xxx
,
6793 CPU_POWERPC_405EZ
= 0x41511460, /* 0x51210950 ? */
6795 CPU_POWERPC_405FX
= xxx
,
6797 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6798 CPU_POWERPC_405GPa
= 0x40110000,
6799 CPU_POWERPC_405GPb
= 0x40110040,
6800 CPU_POWERPC_405GPc
= 0x40110082,
6801 CPU_POWERPC_405GPd
= 0x401100C4,
6802 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6803 CPU_POWERPC_405GPR
= 0x50910951,
6805 CPU_POWERPC_405H
= xxx
,
6808 CPU_POWERPC_405L
= xxx
,
6810 CPU_POWERPC_405LP
= 0x41F10000,
6812 CPU_POWERPC_405PM
= xxx
,
6815 CPU_POWERPC_405PS
= xxx
,
6818 CPU_POWERPC_405S
= xxx
,
6820 /* IBM network processors */
6821 CPU_POWERPC_NPE405H
= 0x414100C0,
6822 CPU_POWERPC_NPE405H2
= 0x41410140,
6823 CPU_POWERPC_NPE405L
= 0x416100C0,
6824 CPU_POWERPC_NPE4GS3
= 0x40B10000,
6826 CPU_POWERPC_NPCxx1
= xxx
,
6829 CPU_POWERPC_NPR161
= xxx
,
6832 CPU_POWERPC_LC77700
= xxx
,
6834 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6836 CPU_POWERPC_STB01000
= xxx
,
6839 CPU_POWERPC_STB01010
= xxx
,
6842 CPU_POWERPC_STB0210
= xxx
, /* 401B3 */
6844 CPU_POWERPC_STB03
= 0x40310000, /* 0x40130000 ? */
6846 CPU_POWERPC_STB043
= xxx
,
6849 CPU_POWERPC_STB045
= xxx
,
6851 CPU_POWERPC_STB04
= 0x41810000,
6852 CPU_POWERPC_STB25
= 0x51510950,
6854 CPU_POWERPC_STB130
= xxx
,
6857 CPU_POWERPC_X2VP4
= 0x20010820,
6858 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
6859 CPU_POWERPC_X2VP20
= 0x20010860,
6860 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
6862 CPU_POWERPC_ZL10310
= xxx
,
6865 CPU_POWERPC_ZL10311
= xxx
,
6868 CPU_POWERPC_ZL10320
= xxx
,
6871 CPU_POWERPC_ZL10321
= xxx
,
6873 /* PowerPC 440 family */
6874 /* Generic PowerPC 440 */
6875 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
6876 /* PowerPC 440 cores */
6878 CPU_POWERPC_440A4
= xxx
,
6880 CPU_POWERPC_440_XILINX
= 0x7ff21910,
6882 CPU_POWERPC_440A5
= xxx
,
6885 CPU_POWERPC_440B4
= xxx
,
6888 CPU_POWERPC_440F5
= xxx
,
6891 CPU_POWERPC_440G5
= xxx
,
6894 CPU_POWERPC_440H4
= xxx
,
6897 CPU_POWERPC_440H6
= xxx
,
6899 /* PowerPC 440 microcontrolers */
6900 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
6901 CPU_POWERPC_440EPa
= 0x42221850,
6902 CPU_POWERPC_440EPb
= 0x422218D3,
6903 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
6904 CPU_POWERPC_440GPb
= 0x40120440,
6905 CPU_POWERPC_440GPc
= 0x40120481,
6906 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
6907 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
6908 CPU_POWERPC_440GRX
= 0x200008D0,
6909 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
6910 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
6911 CPU_POWERPC_440GXa
= 0x51B21850,
6912 CPU_POWERPC_440GXb
= 0x51B21851,
6913 CPU_POWERPC_440GXc
= 0x51B21892,
6914 CPU_POWERPC_440GXf
= 0x51B21894,
6916 CPU_POWERPC_440S
= xxx
,
6918 CPU_POWERPC_440SP
= 0x53221850,
6919 CPU_POWERPC_440SP2
= 0x53221891,
6920 CPU_POWERPC_440SPE
= 0x53421890,
6921 /* PowerPC 460 family */
6923 /* Generic PowerPC 464 */
6924 #define CPU_POWERPC_464 CPU_POWERPC_464H90
6926 /* PowerPC 464 microcontrolers */
6928 CPU_POWERPC_464H90
= xxx
,
6931 CPU_POWERPC_464H90FP
= xxx
,
6933 /* Freescale embedded PowerPC cores */
6934 /* PowerPC MPC 5xx cores (aka RCPU) */
6935 CPU_POWERPC_MPC5xx
= 0x00020020,
6936 #define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
6937 #define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
6938 #define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
6939 #define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
6940 #define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
6941 #define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
6942 #define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
6943 #define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
6944 #define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
6945 #define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
6946 #define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
6947 #define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
6948 #define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
6949 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
6950 CPU_POWERPC_MPC8xx
= 0x00500000,
6951 #define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
6952 #define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
6953 #define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
6954 #define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
6955 #define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
6956 #define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
6957 #define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
6958 #define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
6959 #define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
6960 #define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
6961 #define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
6962 #define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
6963 #define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
6964 #define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
6965 #define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
6966 /* G2 cores (aka PowerQUICC-II) */
6967 CPU_POWERPC_G2
= 0x00810011,
6968 CPU_POWERPC_G2H4
= 0x80811010,
6969 CPU_POWERPC_G2gp
= 0x80821010,
6970 CPU_POWERPC_G2ls
= 0x90810010,
6971 CPU_POWERPC_MPC603
= 0x00810100,
6972 CPU_POWERPC_G2_HIP3
= 0x00810101,
6973 CPU_POWERPC_G2_HIP4
= 0x80811014,
6974 /* G2_LE core (aka PowerQUICC-II) */
6975 CPU_POWERPC_G2LE
= 0x80820010,
6976 CPU_POWERPC_G2LEgp
= 0x80822010,
6977 CPU_POWERPC_G2LEls
= 0xA0822010,
6978 CPU_POWERPC_G2LEgp1
= 0x80822011,
6979 CPU_POWERPC_G2LEgp3
= 0x80822013,
6980 /* MPC52xx microcontrollers */
6981 /* XXX: MPC 5121 ? */
6982 #define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
6983 #define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
6984 #define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
6985 #define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
6986 #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
6987 #define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
6988 #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
6989 #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
6990 /* MPC82xx microcontrollers */
6991 #define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
6992 #define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
6993 #define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
6994 #define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
6995 #define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
6996 #define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
6997 #define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
6998 #define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
6999 #define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
7000 #define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
7001 #define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
7002 #define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
7003 #define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
7004 #define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
7005 #define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
7006 #define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
7007 #define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
7008 #define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
7009 #define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
7010 #define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
7011 #define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
7012 #define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
7013 #define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
7014 #define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
7015 #define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
7016 #define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
7017 #define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
7018 #define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
7019 #define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
7022 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
7024 CPU_POWERPC_e200z0
= xxx
,
7027 CPU_POWERPC_e200z1
= xxx
,
7030 CPU_POWERPC_e200z3
= 0x81120000,
7032 CPU_POWERPC_e200z5
= 0x81000000,
7033 CPU_POWERPC_e200z6
= 0x81120000,
7034 /* MPC55xx microcontrollers */
7035 #define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
7037 #define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
7038 #define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
7039 #define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
7040 #define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
7041 #define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
7042 #define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
7043 #define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
7044 #define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
7045 #define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
7046 #define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
7047 #define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
7048 #define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
7049 #define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
7050 #define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
7053 #define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
7054 #define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
7056 #define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
7057 #define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
7058 #define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
7059 #define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
7060 #define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
7061 #define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
7064 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
7065 CPU_POWERPC_e300c1
= 0x00830010,
7066 CPU_POWERPC_e300c2
= 0x00840010,
7067 CPU_POWERPC_e300c3
= 0x00850010,
7068 CPU_POWERPC_e300c4
= 0x00860010,
7069 /* MPC83xx microcontrollers */
7070 #define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
7071 #define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
7072 #define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
7073 #define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
7074 #define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
7075 #define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
7078 #define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
7079 #define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
7080 #define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
7081 CPU_POWERPC_e500v1_v10
= 0x80200010,
7082 CPU_POWERPC_e500v1_v20
= 0x80200020,
7083 CPU_POWERPC_e500v2_v10
= 0x80210010,
7084 CPU_POWERPC_e500v2_v11
= 0x80210011,
7085 CPU_POWERPC_e500v2_v20
= 0x80210020,
7086 CPU_POWERPC_e500v2_v21
= 0x80210021,
7087 CPU_POWERPC_e500v2_v22
= 0x80210022,
7088 CPU_POWERPC_e500v2_v30
= 0x80210030,
7089 /* MPC85xx microcontrollers */
7090 #define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
7091 #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
7092 #define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
7093 #define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
7094 #define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
7095 #define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
7096 #define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
7097 #define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
7098 #define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
7099 #define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
7100 #define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
7101 #define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
7102 #define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
7103 #define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
7104 #define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
7105 #define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
7106 #define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
7107 #define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
7108 #define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
7109 #define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
7110 #define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
7111 #define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
7112 #define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
7113 #define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
7114 #define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
7115 #define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
7116 #define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
7117 #define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
7118 #define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
7119 #define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
7120 #define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
7121 #define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
7122 #define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
7123 #define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
7124 #define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
7125 #define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
7126 #define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
7127 #define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
7128 #define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
7129 #define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
7130 #define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
7131 #define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
7132 #define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
7133 #define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
7134 #define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
7135 #define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
7136 #define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
7137 #define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
7138 #define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
7139 #define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
7140 #define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
7141 #define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
7142 #define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
7143 #define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
7144 #define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
7145 #define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
7146 #define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
7147 #define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
7148 #define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
7149 #define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
7150 #define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
7151 #define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
7152 #define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
7153 #define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
7154 #define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
7155 #define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
7156 #define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
7157 #define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
7158 #define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
7159 #define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
7162 CPU_POWERPC_e600
= 0x80040010,
7163 /* MPC86xx microcontrollers */
7164 #define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
7165 #define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
7166 #define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
7167 /* PowerPC 6xx cores */
7168 #define CPU_POWERPC_601 CPU_POWERPC_601_v2
7169 CPU_POWERPC_601_v0
= 0x00010001,
7170 CPU_POWERPC_601_v1
= 0x00010001,
7171 #define CPU_POWERPC_601v CPU_POWERPC_601_v2
7172 CPU_POWERPC_601_v2
= 0x00010002,
7173 CPU_POWERPC_602
= 0x00050100,
7174 CPU_POWERPC_603
= 0x00030100,
7175 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
7176 CPU_POWERPC_603E_v11
= 0x00060101,
7177 CPU_POWERPC_603E_v12
= 0x00060102,
7178 CPU_POWERPC_603E_v13
= 0x00060103,
7179 CPU_POWERPC_603E_v14
= 0x00060104,
7180 CPU_POWERPC_603E_v22
= 0x00060202,
7181 CPU_POWERPC_603E_v3
= 0x00060300,
7182 CPU_POWERPC_603E_v4
= 0x00060400,
7183 CPU_POWERPC_603E_v41
= 0x00060401,
7184 CPU_POWERPC_603E7t
= 0x00071201,
7185 CPU_POWERPC_603E7v
= 0x00070100,
7186 CPU_POWERPC_603E7v1
= 0x00070101,
7187 CPU_POWERPC_603E7v2
= 0x00070201,
7188 CPU_POWERPC_603E7
= 0x00070200,
7189 CPU_POWERPC_603P
= 0x00070000,
7190 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
7191 /* XXX: missing 0x00040303 (604) */
7192 CPU_POWERPC_604
= 0x00040103,
7193 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
7194 /* XXX: missing 0x00091203 */
7195 /* XXX: missing 0x00092110 */
7196 /* XXX: missing 0x00092120 */
7197 CPU_POWERPC_604E_v10
= 0x00090100,
7198 CPU_POWERPC_604E_v22
= 0x00090202,
7199 CPU_POWERPC_604E_v24
= 0x00090204,
7200 /* XXX: missing 0x000a0100 */
7201 /* XXX: missing 0x00093102 */
7202 CPU_POWERPC_604R
= 0x000a0101,
7204 CPU_POWERPC_604EV
= xxx
, /* XXX: same as 604R ? */
7206 /* PowerPC 740/750 cores (aka G3) */
7207 /* XXX: missing 0x00084202 */
7208 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
7209 CPU_POWERPC_7x0_v10
= 0x00080100,
7210 CPU_POWERPC_7x0_v20
= 0x00080200,
7211 CPU_POWERPC_7x0_v21
= 0x00080201,
7212 CPU_POWERPC_7x0_v22
= 0x00080202,
7213 CPU_POWERPC_7x0_v30
= 0x00080300,
7214 CPU_POWERPC_7x0_v31
= 0x00080301,
7215 CPU_POWERPC_740E
= 0x00080100,
7216 CPU_POWERPC_750E
= 0x00080200,
7217 CPU_POWERPC_7x0P
= 0x10080000,
7218 /* XXX: missing 0x00087010 (CL ?) */
7219 #define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
7220 CPU_POWERPC_750CL_v10
= 0x00087200,
7221 CPU_POWERPC_750CL_v20
= 0x00087210, /* aka rev E */
7222 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
7223 CPU_POWERPC_750CX_v10
= 0x00082100,
7224 CPU_POWERPC_750CX_v20
= 0x00082200,
7225 CPU_POWERPC_750CX_v21
= 0x00082201,
7226 CPU_POWERPC_750CX_v22
= 0x00082202,
7227 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
7228 CPU_POWERPC_750CXE_v21
= 0x00082211,
7229 CPU_POWERPC_750CXE_v22
= 0x00082212,
7230 CPU_POWERPC_750CXE_v23
= 0x00082213,
7231 CPU_POWERPC_750CXE_v24
= 0x00082214,
7232 CPU_POWERPC_750CXE_v24b
= 0x00083214,
7233 CPU_POWERPC_750CXE_v30
= 0x00082310,
7234 CPU_POWERPC_750CXE_v31
= 0x00082311,
7235 CPU_POWERPC_750CXE_v31b
= 0x00083311,
7236 CPU_POWERPC_750CXR
= 0x00083410,
7237 CPU_POWERPC_750FL
= 0x70000203,
7238 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
7239 CPU_POWERPC_750FX_v10
= 0x70000100,
7240 CPU_POWERPC_750FX_v20
= 0x70000200,
7241 CPU_POWERPC_750FX_v21
= 0x70000201,
7242 CPU_POWERPC_750FX_v22
= 0x70000202,
7243 CPU_POWERPC_750FX_v23
= 0x70000203,
7244 CPU_POWERPC_750GL
= 0x70020102,
7245 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
7246 CPU_POWERPC_750GX_v10
= 0x70020100,
7247 CPU_POWERPC_750GX_v11
= 0x70020101,
7248 CPU_POWERPC_750GX_v12
= 0x70020102,
7249 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
7250 CPU_POWERPC_750L_v20
= 0x00088200,
7251 CPU_POWERPC_750L_v21
= 0x00088201,
7252 CPU_POWERPC_750L_v22
= 0x00088202,
7253 CPU_POWERPC_750L_v30
= 0x00088300,
7254 CPU_POWERPC_750L_v32
= 0x00088302,
7255 /* PowerPC 745/755 cores */
7256 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
7257 CPU_POWERPC_7x5_v10
= 0x00083100,
7258 CPU_POWERPC_7x5_v11
= 0x00083101,
7259 CPU_POWERPC_7x5_v20
= 0x00083200,
7260 CPU_POWERPC_7x5_v21
= 0x00083201,
7261 CPU_POWERPC_7x5_v22
= 0x00083202, /* aka D */
7262 CPU_POWERPC_7x5_v23
= 0x00083203, /* aka E */
7263 CPU_POWERPC_7x5_v24
= 0x00083204,
7264 CPU_POWERPC_7x5_v25
= 0x00083205,
7265 CPU_POWERPC_7x5_v26
= 0x00083206,
7266 CPU_POWERPC_7x5_v27
= 0x00083207,
7267 CPU_POWERPC_7x5_v28
= 0x00083208,
7269 CPU_POWERPC_7x5P
= xxx
,
7271 /* PowerPC 74xx cores (aka G4) */
7272 /* XXX: missing 0x000C1101 */
7273 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
7274 CPU_POWERPC_7400_v10
= 0x000C0100,
7275 CPU_POWERPC_7400_v11
= 0x000C0101,
7276 CPU_POWERPC_7400_v20
= 0x000C0200,
7277 CPU_POWERPC_7400_v21
= 0x000C0201,
7278 CPU_POWERPC_7400_v22
= 0x000C0202,
7279 CPU_POWERPC_7400_v26
= 0x000C0206,
7280 CPU_POWERPC_7400_v27
= 0x000C0207,
7281 CPU_POWERPC_7400_v28
= 0x000C0208,
7282 CPU_POWERPC_7400_v29
= 0x000C0209,
7283 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
7284 CPU_POWERPC_7410_v10
= 0x800C1100,
7285 CPU_POWERPC_7410_v11
= 0x800C1101,
7286 CPU_POWERPC_7410_v12
= 0x800C1102, /* aka C */
7287 CPU_POWERPC_7410_v13
= 0x800C1103, /* aka D */
7288 CPU_POWERPC_7410_v14
= 0x800C1104, /* aka E */
7289 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
7290 CPU_POWERPC_7448_v10
= 0x80040100,
7291 CPU_POWERPC_7448_v11
= 0x80040101,
7292 CPU_POWERPC_7448_v20
= 0x80040200,
7293 CPU_POWERPC_7448_v21
= 0x80040201,
7294 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
7295 CPU_POWERPC_7450_v10
= 0x80000100,
7296 CPU_POWERPC_7450_v11
= 0x80000101,
7297 CPU_POWERPC_7450_v12
= 0x80000102,
7298 CPU_POWERPC_7450_v20
= 0x80000200, /* aka A, B, C, D: 2.04 */
7299 CPU_POWERPC_7450_v21
= 0x80000201, /* aka E */
7300 #define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
7301 CPU_POWERPC_74x1_v23
= 0x80000203, /* aka G: 2.3 */
7302 /* XXX: this entry might be a bug in some documentation */
7303 CPU_POWERPC_74x1_v210
= 0x80000210, /* aka G: 2.3 ? */
7304 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
7305 CPU_POWERPC_74x5_v10
= 0x80010100,
7306 /* XXX: missing 0x80010200 */
7307 CPU_POWERPC_74x5_v21
= 0x80010201, /* aka C: 2.1 */
7308 CPU_POWERPC_74x5_v32
= 0x80010302,
7309 CPU_POWERPC_74x5_v33
= 0x80010303, /* aka F: 3.3 */
7310 CPU_POWERPC_74x5_v34
= 0x80010304, /* aka G: 3.4 */
7311 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
7312 CPU_POWERPC_74x7_v10
= 0x80020100, /* aka A: 1.0 */
7313 CPU_POWERPC_74x7_v11
= 0x80020101, /* aka B: 1.1 */
7314 CPU_POWERPC_74x7_v12
= 0x80020102, /* aka C: 1.2 */
7315 #define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
7316 CPU_POWERPC_74x7A_v10
= 0x80030100, /* aka A: 1.0 */
7317 CPU_POWERPC_74x7A_v11
= 0x80030101, /* aka B: 1.1 */
7318 CPU_POWERPC_74x7A_v12
= 0x80030102, /* aka C: 1.2 */
7319 /* 64 bits PowerPC */
7320 #if defined(TARGET_PPC64)
7321 CPU_POWERPC_620
= 0x00140000,
7322 CPU_POWERPC_630
= 0x00400000,
7323 CPU_POWERPC_631
= 0x00410104,
7324 CPU_POWERPC_POWER4
= 0x00350000,
7325 CPU_POWERPC_POWER4P
= 0x00380000,
7326 /* XXX: missing 0x003A0201 */
7327 CPU_POWERPC_POWER5
= 0x003A0203,
7328 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
7329 CPU_POWERPC_POWER5P
= 0x003B0000,
7330 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
7331 CPU_POWERPC_POWER6
= 0x003E0000,
7332 CPU_POWERPC_POWER6_5
= 0x0F000001, /* POWER6 in POWER5 mode */
7333 CPU_POWERPC_POWER6A
= 0x0F000002,
7334 #define CPU_POWERPC_POWER7 CPU_POWERPC_POWER7_v20
7335 CPU_POWERPC_POWER7_v20
= 0x003F0200,
7336 CPU_POWERPC_POWER7_v21
= 0x003F0201,
7337 CPU_POWERPC_POWER7_v23
= 0x003F0203,
7338 CPU_POWERPC_970
= 0x00390202,
7339 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
7340 CPU_POWERPC_970FX_v10
= 0x00391100,
7341 CPU_POWERPC_970FX_v20
= 0x003C0200,
7342 CPU_POWERPC_970FX_v21
= 0x003C0201,
7343 CPU_POWERPC_970FX_v30
= 0x003C0300,
7344 CPU_POWERPC_970FX_v31
= 0x003C0301,
7345 CPU_POWERPC_970GX
= 0x00450000,
7346 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
7347 CPU_POWERPC_970MP_v10
= 0x00440100,
7348 CPU_POWERPC_970MP_v11
= 0x00440101,
7349 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
7350 CPU_POWERPC_CELL_v10
= 0x00700100,
7351 CPU_POWERPC_CELL_v20
= 0x00700400,
7352 CPU_POWERPC_CELL_v30
= 0x00700500,
7353 CPU_POWERPC_CELL_v31
= 0x00700501,
7354 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
7355 CPU_POWERPC_RS64
= 0x00330000,
7356 CPU_POWERPC_RS64II
= 0x00340000,
7357 CPU_POWERPC_RS64III
= 0x00360000,
7358 CPU_POWERPC_RS64IV
= 0x00370000,
7359 #endif /* defined(TARGET_PPC64) */
7360 /* Original POWER */
7361 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7362 * POWER2 (RIOS2) & RSC2 (P2SC) here
7365 CPU_POWER
= xxx
, /* 0x20000 ? 0x30000 for RSC ? */
7368 CPU_POWER2
= xxx
, /* 0x40000 ? */
7371 CPU_POWERPC_PA6T
= 0x00900000,
7374 /* System version register (used on MPC 8xxx) */
7376 POWERPC_SVR_NONE
= 0x00000000,
7377 #define POWERPC_SVR_52xx POWERPC_SVR_5200
7378 #define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7379 POWERPC_SVR_5200_v10
= 0x80110010,
7380 POWERPC_SVR_5200_v11
= 0x80110011,
7381 POWERPC_SVR_5200_v12
= 0x80110012,
7382 #define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7383 POWERPC_SVR_5200B_v20
= 0x80110020,
7384 POWERPC_SVR_5200B_v21
= 0x80110021,
7385 #define POWERPC_SVR_55xx POWERPC_SVR_5567
7387 POWERPC_SVR_5533
= xxx
,
7390 POWERPC_SVR_5534
= xxx
,
7393 POWERPC_SVR_5553
= xxx
,
7396 POWERPC_SVR_5554
= xxx
,
7399 POWERPC_SVR_5561
= xxx
,
7402 POWERPC_SVR_5565
= xxx
,
7405 POWERPC_SVR_5566
= xxx
,
7408 POWERPC_SVR_5567
= xxx
,
7411 POWERPC_SVR_8313
= xxx
,
7414 POWERPC_SVR_8313E
= xxx
,
7417 POWERPC_SVR_8314
= xxx
,
7420 POWERPC_SVR_8314E
= xxx
,
7423 POWERPC_SVR_8315
= xxx
,
7426 POWERPC_SVR_8315E
= xxx
,
7429 POWERPC_SVR_8321
= xxx
,
7432 POWERPC_SVR_8321E
= xxx
,
7435 POWERPC_SVR_8323
= xxx
,
7438 POWERPC_SVR_8323E
= xxx
,
7440 POWERPC_SVR_8343
= 0x80570010,
7441 POWERPC_SVR_8343A
= 0x80570030,
7442 POWERPC_SVR_8343E
= 0x80560010,
7443 POWERPC_SVR_8343EA
= 0x80560030,
7444 #define POWERPC_SVR_8347 POWERPC_SVR_8347T
7445 POWERPC_SVR_8347P
= 0x80550010, /* PBGA package */
7446 POWERPC_SVR_8347T
= 0x80530010, /* TBGA package */
7447 #define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7448 POWERPC_SVR_8347AP
= 0x80550030, /* PBGA package */
7449 POWERPC_SVR_8347AT
= 0x80530030, /* TBGA package */
7450 #define POWERPC_SVR_8347E POWERPC_SVR_8347ET
7451 POWERPC_SVR_8347EP
= 0x80540010, /* PBGA package */
7452 POWERPC_SVR_8347ET
= 0x80520010, /* TBGA package */
7453 #define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7454 POWERPC_SVR_8347EAP
= 0x80540030, /* PBGA package */
7455 POWERPC_SVR_8347EAT
= 0x80520030, /* TBGA package */
7456 POWERPC_SVR_8349
= 0x80510010,
7457 POWERPC_SVR_8349A
= 0x80510030,
7458 POWERPC_SVR_8349E
= 0x80500010,
7459 POWERPC_SVR_8349EA
= 0x80500030,
7461 POWERPC_SVR_8358E
= xxx
,
7464 POWERPC_SVR_8360E
= xxx
,
7466 #define POWERPC_SVR_E500 0x40000000
7467 POWERPC_SVR_8377
= 0x80C70010 | POWERPC_SVR_E500
,
7468 POWERPC_SVR_8377E
= 0x80C60010 | POWERPC_SVR_E500
,
7469 POWERPC_SVR_8378
= 0x80C50010 | POWERPC_SVR_E500
,
7470 POWERPC_SVR_8378E
= 0x80C40010 | POWERPC_SVR_E500
,
7471 POWERPC_SVR_8379
= 0x80C30010 | POWERPC_SVR_E500
,
7472 POWERPC_SVR_8379E
= 0x80C00010 | POWERPC_SVR_E500
,
7473 #define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7474 POWERPC_SVR_8533_v10
= 0x80340010 | POWERPC_SVR_E500
,
7475 POWERPC_SVR_8533_v11
= 0x80340011 | POWERPC_SVR_E500
,
7476 #define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7477 POWERPC_SVR_8533E_v10
= 0x803C0010 | POWERPC_SVR_E500
,
7478 POWERPC_SVR_8533E_v11
= 0x803C0011 | POWERPC_SVR_E500
,
7479 #define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7480 POWERPC_SVR_8540_v10
= 0x80300010 | POWERPC_SVR_E500
,
7481 POWERPC_SVR_8540_v20
= 0x80300020 | POWERPC_SVR_E500
,
7482 POWERPC_SVR_8540_v21
= 0x80300021 | POWERPC_SVR_E500
,
7483 #define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7484 POWERPC_SVR_8541_v10
= 0x80720010 | POWERPC_SVR_E500
,
7485 POWERPC_SVR_8541_v11
= 0x80720011 | POWERPC_SVR_E500
,
7486 #define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7487 POWERPC_SVR_8541E_v10
= 0x807A0010 | POWERPC_SVR_E500
,
7488 POWERPC_SVR_8541E_v11
= 0x807A0011 | POWERPC_SVR_E500
,
7489 #define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7490 POWERPC_SVR_8543_v10
= 0x80320010 | POWERPC_SVR_E500
,
7491 POWERPC_SVR_8543_v11
= 0x80320011 | POWERPC_SVR_E500
,
7492 POWERPC_SVR_8543_v20
= 0x80320020 | POWERPC_SVR_E500
,
7493 POWERPC_SVR_8543_v21
= 0x80320021 | POWERPC_SVR_E500
,
7494 #define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7495 POWERPC_SVR_8543E_v10
= 0x803A0010 | POWERPC_SVR_E500
,
7496 POWERPC_SVR_8543E_v11
= 0x803A0011 | POWERPC_SVR_E500
,
7497 POWERPC_SVR_8543E_v20
= 0x803A0020 | POWERPC_SVR_E500
,
7498 POWERPC_SVR_8543E_v21
= 0x803A0021 | POWERPC_SVR_E500
,
7499 #define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7500 POWERPC_SVR_8544_v10
= 0x80340110 | POWERPC_SVR_E500
,
7501 POWERPC_SVR_8544_v11
= 0x80340111 | POWERPC_SVR_E500
,
7502 #define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7503 POWERPC_SVR_8544E_v10
= 0x803C0110 | POWERPC_SVR_E500
,
7504 POWERPC_SVR_8544E_v11
= 0x803C0111 | POWERPC_SVR_E500
,
7505 #define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7506 POWERPC_SVR_8545_v20
= 0x80310220 | POWERPC_SVR_E500
,
7507 POWERPC_SVR_8545_v21
= 0x80310221 | POWERPC_SVR_E500
,
7508 #define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7509 POWERPC_SVR_8545E_v20
= 0x80390220 | POWERPC_SVR_E500
,
7510 POWERPC_SVR_8545E_v21
= 0x80390221 | POWERPC_SVR_E500
,
7511 #define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7512 POWERPC_SVR_8547E_v20
= 0x80390120 | POWERPC_SVR_E500
,
7513 POWERPC_SVR_8547E_v21
= 0x80390121 | POWERPC_SVR_E500
,
7514 #define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7515 POWERPC_SVR_8548_v10
= 0x80310010 | POWERPC_SVR_E500
,
7516 POWERPC_SVR_8548_v11
= 0x80310011 | POWERPC_SVR_E500
,
7517 POWERPC_SVR_8548_v20
= 0x80310020 | POWERPC_SVR_E500
,
7518 POWERPC_SVR_8548_v21
= 0x80310021 | POWERPC_SVR_E500
,
7519 #define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7520 POWERPC_SVR_8548E_v10
= 0x80390010 | POWERPC_SVR_E500
,
7521 POWERPC_SVR_8548E_v11
= 0x80390011 | POWERPC_SVR_E500
,
7522 POWERPC_SVR_8548E_v20
= 0x80390020 | POWERPC_SVR_E500
,
7523 POWERPC_SVR_8548E_v21
= 0x80390021 | POWERPC_SVR_E500
,
7524 #define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7525 POWERPC_SVR_8555_v10
= 0x80710010 | POWERPC_SVR_E500
,
7526 POWERPC_SVR_8555_v11
= 0x80710011 | POWERPC_SVR_E500
,
7527 #define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7528 POWERPC_SVR_8555E_v10
= 0x80790010 | POWERPC_SVR_E500
,
7529 POWERPC_SVR_8555E_v11
= 0x80790011 | POWERPC_SVR_E500
,
7530 #define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7531 POWERPC_SVR_8560_v10
= 0x80700010 | POWERPC_SVR_E500
,
7532 POWERPC_SVR_8560_v20
= 0x80700020 | POWERPC_SVR_E500
,
7533 POWERPC_SVR_8560_v21
= 0x80700021 | POWERPC_SVR_E500
,
7534 POWERPC_SVR_8567
= 0x80750111 | POWERPC_SVR_E500
,
7535 POWERPC_SVR_8567E
= 0x807D0111 | POWERPC_SVR_E500
,
7536 POWERPC_SVR_8568
= 0x80750011 | POWERPC_SVR_E500
,
7537 POWERPC_SVR_8568E
= 0x807D0011 | POWERPC_SVR_E500
,
7538 POWERPC_SVR_8572
= 0x80E00010 | POWERPC_SVR_E500
,
7539 POWERPC_SVR_8572E
= 0x80E80010 | POWERPC_SVR_E500
,
7541 POWERPC_SVR_8610
= xxx
,
7543 POWERPC_SVR_8641
= 0x80900021,
7544 POWERPC_SVR_8641D
= 0x80900121,
7547 /*****************************************************************************/
7548 /* PowerPC CPU definitions */
7549 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
7554 .insns_flags = glue(POWERPC_INSNS_,_type), \
7555 .insns_flags2 = glue(POWERPC_INSNS2_,_type), \
7556 .msr_mask = glue(POWERPC_MSRM_,_type), \
7557 .mmu_model = glue(POWERPC_MMU_,_type), \
7558 .excp_model = glue(POWERPC_EXCP_,_type), \
7559 .bus_model = glue(POWERPC_INPUT_,_type), \
7560 .bfd_mach = glue(POWERPC_BFDM_,_type), \
7561 .flags = glue(POWERPC_FLAG_,_type), \
7562 .init_proc = &glue(init_proc_,_type), \
7563 .check_pow = &glue(check_pow_,_type), \
7565 #define POWERPC_DEF(_name, _pvr, _type) \
7566 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
7568 static const ppc_def_t ppc_defs
[] = {
7569 /* Embedded PowerPC */
7570 /* PowerPC 401 family */
7571 /* Generic PowerPC 401 */
7572 POWERPC_DEF("401", CPU_POWERPC_401
, 401),
7573 /* PowerPC 401 cores */
7575 POWERPC_DEF("401A1", CPU_POWERPC_401A1
, 401),
7577 POWERPC_DEF("401B2", CPU_POWERPC_401B2
, 401x2
),
7580 POWERPC_DEF("401B3", CPU_POWERPC_401B3
, 401x3
),
7583 POWERPC_DEF("401C2", CPU_POWERPC_401C2
, 401x2
),
7585 POWERPC_DEF("401D2", CPU_POWERPC_401D2
, 401x2
),
7587 POWERPC_DEF("401E2", CPU_POWERPC_401E2
, 401x2
),
7589 POWERPC_DEF("401F2", CPU_POWERPC_401F2
, 401x2
),
7591 /* XXX: to be checked */
7592 POWERPC_DEF("401G2", CPU_POWERPC_401G2
, 401x2
),
7593 /* PowerPC 401 microcontrolers */
7596 POWERPC_DEF("401GF", CPU_POWERPC_401GF
, 401),
7598 /* IOP480 (401 microcontroler) */
7599 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480
, IOP480
),
7600 /* IBM Processor for Network Resources */
7601 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA
, 401),
7603 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP
, 401),
7605 /* PowerPC 403 family */
7606 /* Generic PowerPC 403 */
7607 POWERPC_DEF("403", CPU_POWERPC_403
, 403),
7608 /* PowerPC 403 microcontrolers */
7609 /* PowerPC 403 GA */
7610 POWERPC_DEF("403GA", CPU_POWERPC_403GA
, 403),
7611 /* PowerPC 403 GB */
7612 POWERPC_DEF("403GB", CPU_POWERPC_403GB
, 403),
7613 /* PowerPC 403 GC */
7614 POWERPC_DEF("403GC", CPU_POWERPC_403GC
, 403),
7615 /* PowerPC 403 GCX */
7616 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX
, 403GCX
),
7618 /* PowerPC 403 GP */
7619 POWERPC_DEF("403GP", CPU_POWERPC_403GP
, 403),
7621 /* PowerPC 405 family */
7622 /* Generic PowerPC 405 */
7623 POWERPC_DEF("405", CPU_POWERPC_405
, 405),
7624 /* PowerPC 405 cores */
7626 /* PowerPC 405 A3 */
7627 POWERPC_DEF("405A3", CPU_POWERPC_405A3
, 405),
7630 /* PowerPC 405 A4 */
7631 POWERPC_DEF("405A4", CPU_POWERPC_405A4
, 405),
7634 /* PowerPC 405 B3 */
7635 POWERPC_DEF("405B3", CPU_POWERPC_405B3
, 405),
7638 /* PowerPC 405 B4 */
7639 POWERPC_DEF("405B4", CPU_POWERPC_405B4
, 405),
7642 /* PowerPC 405 C3 */
7643 POWERPC_DEF("405C3", CPU_POWERPC_405C3
, 405),
7646 /* PowerPC 405 C4 */
7647 POWERPC_DEF("405C4", CPU_POWERPC_405C4
, 405),
7649 /* PowerPC 405 D2 */
7650 POWERPC_DEF("405D2", CPU_POWERPC_405D2
, 405),
7652 /* PowerPC 405 D3 */
7653 POWERPC_DEF("405D3", CPU_POWERPC_405D3
, 405),
7655 /* PowerPC 405 D4 */
7656 POWERPC_DEF("405D4", CPU_POWERPC_405D4
, 405),
7658 /* PowerPC 405 D5 */
7659 POWERPC_DEF("405D5", CPU_POWERPC_405D5
, 405),
7662 /* PowerPC 405 E4 */
7663 POWERPC_DEF("405E4", CPU_POWERPC_405E4
, 405),
7666 /* PowerPC 405 F4 */
7667 POWERPC_DEF("405F4", CPU_POWERPC_405F4
, 405),
7670 /* PowerPC 405 F5 */
7671 POWERPC_DEF("405F5", CPU_POWERPC_405F5
, 405),
7674 /* PowerPC 405 F6 */
7675 POWERPC_DEF("405F6", CPU_POWERPC_405F6
, 405),
7677 /* PowerPC 405 microcontrolers */
7678 /* PowerPC 405 CR */
7679 POWERPC_DEF("405CR", CPU_POWERPC_405CR
, 405),
7680 /* PowerPC 405 CRa */
7681 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa
, 405),
7682 /* PowerPC 405 CRb */
7683 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb
, 405),
7684 /* PowerPC 405 CRc */
7685 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc
, 405),
7686 /* PowerPC 405 EP */
7687 POWERPC_DEF("405EP", CPU_POWERPC_405EP
, 405),
7689 /* PowerPC 405 EXr */
7690 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr
, 405),
7692 /* PowerPC 405 EZ */
7693 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ
, 405),
7695 /* PowerPC 405 FX */
7696 POWERPC_DEF("405FX", CPU_POWERPC_405FX
, 405),
7698 /* PowerPC 405 GP */
7699 POWERPC_DEF("405GP", CPU_POWERPC_405GP
, 405),
7700 /* PowerPC 405 GPa */
7701 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa
, 405),
7702 /* PowerPC 405 GPb */
7703 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb
, 405),
7704 /* PowerPC 405 GPc */
7705 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc
, 405),
7706 /* PowerPC 405 GPd */
7707 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd
, 405),
7708 /* PowerPC 405 GPe */
7709 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe
, 405),
7710 /* PowerPC 405 GPR */
7711 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR
, 405),
7714 POWERPC_DEF("405H", CPU_POWERPC_405H
, 405),
7718 POWERPC_DEF("405L", CPU_POWERPC_405L
, 405),
7720 /* PowerPC 405 LP */
7721 POWERPC_DEF("405LP", CPU_POWERPC_405LP
, 405),
7723 /* PowerPC 405 PM */
7724 POWERPC_DEF("405PM", CPU_POWERPC_405PM
, 405),
7727 /* PowerPC 405 PS */
7728 POWERPC_DEF("405PS", CPU_POWERPC_405PS
, 405),
7732 POWERPC_DEF("405S", CPU_POWERPC_405S
, 405),
7735 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H
, 405),
7737 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2
, 405),
7739 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L
, 405),
7741 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3
, 405),
7743 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1
, 405),
7746 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161
, 405),
7749 /* PowerPC LC77700 (Sanyo) */
7750 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700
, 405),
7752 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7755 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000
, 401x2
),
7759 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010
, 401x2
),
7763 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210
, 401x3
),
7766 POWERPC_DEF("STB03", CPU_POWERPC_STB03
, 405),
7769 POWERPC_DEF("STB043", CPU_POWERPC_STB043
, 405),
7773 POWERPC_DEF("STB045", CPU_POWERPC_STB045
, 405),
7776 POWERPC_DEF("STB04", CPU_POWERPC_STB04
, 405),
7778 POWERPC_DEF("STB25", CPU_POWERPC_STB25
, 405),
7781 POWERPC_DEF("STB130", CPU_POWERPC_STB130
, 405),
7783 /* Xilinx PowerPC 405 cores */
7784 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4
, 405),
7785 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7
, 405),
7786 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20
, 405),
7787 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50
, 405),
7789 /* Zarlink ZL10310 */
7790 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310
, 405),
7793 /* Zarlink ZL10311 */
7794 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311
, 405),
7797 /* Zarlink ZL10320 */
7798 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320
, 405),
7801 /* Zarlink ZL10321 */
7802 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321
, 405),
7804 /* PowerPC 440 family */
7805 #if defined(TODO_USER_ONLY)
7806 /* Generic PowerPC 440 */
7807 POWERPC_DEF("440", CPU_POWERPC_440
, 440GP
),
7809 /* PowerPC 440 cores */
7811 /* PowerPC 440 A4 */
7812 POWERPC_DEF("440A4", CPU_POWERPC_440A4
, 440x4
),
7814 /* PowerPC 440 Xilinx 5 */
7815 POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX
, 440x5
),
7817 /* PowerPC 440 A5 */
7818 POWERPC_DEF("440A5", CPU_POWERPC_440A5
, 440x5
),
7821 /* PowerPC 440 B4 */
7822 POWERPC_DEF("440B4", CPU_POWERPC_440B4
, 440x4
),
7825 /* PowerPC 440 G4 */
7826 POWERPC_DEF("440G4", CPU_POWERPC_440G4
, 440x4
),
7829 /* PowerPC 440 F5 */
7830 POWERPC_DEF("440F5", CPU_POWERPC_440F5
, 440x5
),
7833 /* PowerPC 440 G5 */
7834 POWERPC_DEF("440G5", CPU_POWERPC_440G5
, 440x5
),
7838 POWERPC_DEF("440H4", CPU_POWERPC_440H4
, 440x4
),
7842 POWERPC_DEF("440H6", CPU_POWERPC_440H6
, 440Gx5
),
7844 /* PowerPC 440 microcontrolers */
7845 #if defined(TODO_USER_ONLY)
7846 /* PowerPC 440 EP */
7847 POWERPC_DEF("440EP", CPU_POWERPC_440EP
, 440EP
),
7849 #if defined(TODO_USER_ONLY)
7850 /* PowerPC 440 EPa */
7851 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa
, 440EP
),
7853 #if defined(TODO_USER_ONLY)
7854 /* PowerPC 440 EPb */
7855 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb
, 440EP
),
7857 #if defined(TODO_USER_ONLY)
7858 /* PowerPC 440 EPX */
7859 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX
, 440EP
),
7861 #if defined(TODO_USER_ONLY)
7862 /* PowerPC 440 GP */
7863 POWERPC_DEF("440GP", CPU_POWERPC_440GP
, 440GP
),
7865 #if defined(TODO_USER_ONLY)
7866 /* PowerPC 440 GPb */
7867 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb
, 440GP
),
7869 #if defined(TODO_USER_ONLY)
7870 /* PowerPC 440 GPc */
7871 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc
, 440GP
),
7873 #if defined(TODO_USER_ONLY)
7874 /* PowerPC 440 GR */
7875 POWERPC_DEF("440GR", CPU_POWERPC_440GR
, 440x5
),
7877 #if defined(TODO_USER_ONLY)
7878 /* PowerPC 440 GRa */
7879 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa
, 440x5
),
7881 #if defined(TODO_USER_ONLY)
7882 /* PowerPC 440 GRX */
7883 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX
, 440x5
),
7885 #if defined(TODO_USER_ONLY)
7886 /* PowerPC 440 GX */
7887 POWERPC_DEF("440GX", CPU_POWERPC_440GX
, 440EP
),
7889 #if defined(TODO_USER_ONLY)
7890 /* PowerPC 440 GXa */
7891 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa
, 440EP
),
7893 #if defined(TODO_USER_ONLY)
7894 /* PowerPC 440 GXb */
7895 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb
, 440EP
),
7897 #if defined(TODO_USER_ONLY)
7898 /* PowerPC 440 GXc */
7899 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc
, 440EP
),
7901 #if defined(TODO_USER_ONLY)
7902 /* PowerPC 440 GXf */
7903 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf
, 440EP
),
7907 POWERPC_DEF("440S", CPU_POWERPC_440S
, 440),
7909 #if defined(TODO_USER_ONLY)
7910 /* PowerPC 440 SP */
7911 POWERPC_DEF("440SP", CPU_POWERPC_440SP
, 440EP
),
7913 #if defined(TODO_USER_ONLY)
7914 /* PowerPC 440 SP2 */
7915 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2
, 440EP
),
7917 #if defined(TODO_USER_ONLY)
7918 /* PowerPC 440 SPE */
7919 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE
, 440EP
),
7921 /* PowerPC 460 family */
7923 /* Generic PowerPC 464 */
7924 POWERPC_DEF("464", CPU_POWERPC_464
, 460),
7926 /* PowerPC 464 microcontrolers */
7928 /* PowerPC 464H90 */
7929 POWERPC_DEF("464H90", CPU_POWERPC_464H90
, 460),
7932 /* PowerPC 464H90F */
7933 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F
, 460F
),
7935 /* Freescale embedded PowerPC cores */
7936 /* MPC5xx family (aka RCPU) */
7937 #if defined(TODO_USER_ONLY)
7938 /* Generic MPC5xx core */
7939 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx
, MPC5xx
),
7941 #if defined(TODO_USER_ONLY)
7942 /* Codename for MPC5xx core */
7943 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx
, MPC5xx
),
7945 /* MPC5xx microcontrollers */
7946 #if defined(TODO_USER_ONLY)
7948 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560
, MPC5xx
),
7950 #if defined(TODO_USER_ONLY)
7952 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509
, MPC5xx
),
7954 #if defined(TODO_USER_ONLY)
7956 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533
, MPC5xx
),
7958 #if defined(TODO_USER_ONLY)
7960 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534
, MPC5xx
),
7962 #if defined(TODO_USER_ONLY)
7964 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555
, MPC5xx
),
7966 #if defined(TODO_USER_ONLY)
7968 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556
, MPC5xx
),
7970 #if defined(TODO_USER_ONLY)
7972 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560
, MPC5xx
),
7974 #if defined(TODO_USER_ONLY)
7976 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561
, MPC5xx
),
7978 #if defined(TODO_USER_ONLY)
7980 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562
, MPC5xx
),
7982 #if defined(TODO_USER_ONLY)
7984 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563
, MPC5xx
),
7986 #if defined(TODO_USER_ONLY)
7988 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564
, MPC5xx
),
7990 #if defined(TODO_USER_ONLY)
7992 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565
, MPC5xx
),
7994 #if defined(TODO_USER_ONLY)
7996 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566
, MPC5xx
),
7998 /* MPC8xx family (aka PowerQUICC) */
7999 #if defined(TODO_USER_ONLY)
8000 /* Generic MPC8xx core */
8001 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx
, MPC8xx
),
8003 #if defined(TODO_USER_ONLY)
8004 /* Codename for MPC8xx core */
8005 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx
, MPC8xx
),
8007 /* MPC8xx microcontrollers */
8008 #if defined(TODO_USER_ONLY)
8010 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823
, MPC8xx
),
8012 #if defined(TODO_USER_ONLY)
8014 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821
, MPC8xx
),
8016 #if defined(TODO_USER_ONLY)
8018 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823
, MPC8xx
),
8020 #if defined(TODO_USER_ONLY)
8022 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850
, MPC8xx
),
8024 #if defined(TODO_USER_ONLY)
8026 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T
, MPC8xx
),
8028 #if defined(TODO_USER_ONLY)
8030 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T
, MPC8xx
),
8032 #if defined(TODO_USER_ONLY)
8034 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857
, MPC8xx
),
8036 #if defined(TODO_USER_ONLY)
8038 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859
, MPC8xx
),
8040 #if defined(TODO_USER_ONLY)
8042 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860
, MPC8xx
),
8044 #if defined(TODO_USER_ONLY)
8046 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862
, MPC8xx
),
8048 #if defined(TODO_USER_ONLY)
8050 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866
, MPC8xx
),
8052 #if defined(TODO_USER_ONLY)
8054 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870
, MPC8xx
),
8056 #if defined(TODO_USER_ONLY)
8058 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875
, MPC8xx
),
8060 #if defined(TODO_USER_ONLY)
8062 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880
, MPC8xx
),
8064 #if defined(TODO_USER_ONLY)
8066 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885
, MPC8xx
),
8068 /* MPC82xx family (aka PowerQUICC-II) */
8069 /* Generic MPC52xx core */
8070 POWERPC_DEF_SVR("MPC52xx",
8071 CPU_POWERPC_MPC52xx
, POWERPC_SVR_52xx
, G2LE
),
8072 /* Generic MPC82xx core */
8073 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx
, G2
),
8074 /* Codename for MPC82xx */
8075 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx
, G2
),
8076 /* PowerPC G2 core */
8077 POWERPC_DEF("G2", CPU_POWERPC_G2
, G2
),
8078 /* PowerPC G2 H4 core */
8079 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4
, G2
),
8080 /* PowerPC G2 GP core */
8081 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp
, G2
),
8082 /* PowerPC G2 LS core */
8083 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls
, G2
),
8084 /* PowerPC G2 HiP3 core */
8085 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3
, G2
),
8086 /* PowerPC G2 HiP4 core */
8087 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4
, G2
),
8088 /* PowerPC MPC603 core */
8089 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603
, 603E
),
8090 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
8091 POWERPC_DEF("G2le", CPU_POWERPC_G2LE
, G2LE
),
8092 /* PowerPC G2LE GP core */
8093 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp
, G2LE
),
8094 /* PowerPC G2LE LS core */
8095 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls
, G2LE
),
8096 /* PowerPC G2LE GP1 core */
8097 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1
, G2LE
),
8098 /* PowerPC G2LE GP3 core */
8099 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1
, G2LE
),
8100 /* PowerPC MPC603 microcontrollers */
8102 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240
, 603E
),
8103 /* PowerPC G2 microcontrollers */
8106 POWERPC_DEF_SVR("MPC5121",
8107 CPU_POWERPC_MPC5121
, POWERPC_SVR_5121
, G2LE
),
8110 POWERPC_DEF_SVR("MPC5200",
8111 CPU_POWERPC_MPC5200
, POWERPC_SVR_5200
, G2LE
),
8113 POWERPC_DEF_SVR("MPC5200_v10",
8114 CPU_POWERPC_MPC5200_v10
, POWERPC_SVR_5200_v10
, G2LE
),
8116 POWERPC_DEF_SVR("MPC5200_v11",
8117 CPU_POWERPC_MPC5200_v11
, POWERPC_SVR_5200_v11
, G2LE
),
8119 POWERPC_DEF_SVR("MPC5200_v12",
8120 CPU_POWERPC_MPC5200_v12
, POWERPC_SVR_5200_v12
, G2LE
),
8122 POWERPC_DEF_SVR("MPC5200B",
8123 CPU_POWERPC_MPC5200B
, POWERPC_SVR_5200B
, G2LE
),
8125 POWERPC_DEF_SVR("MPC5200B_v20",
8126 CPU_POWERPC_MPC5200B_v20
, POWERPC_SVR_5200B_v20
, G2LE
),
8128 POWERPC_DEF_SVR("MPC5200B_v21",
8129 CPU_POWERPC_MPC5200B_v21
, POWERPC_SVR_5200B_v21
, G2LE
),
8131 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241
, G2
),
8133 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245
, G2
),
8135 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247
, G2LE
),
8137 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248
, G2LE
),
8139 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250
, G2
),
8141 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3
, G2
),
8143 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4
, G2
),
8145 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255
, G2
),
8147 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3
, G2
),
8149 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4
, G2
),
8151 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260
, G2
),
8153 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3
, G2
),
8155 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4
, G2
),
8157 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264
, G2
),
8159 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3
, G2
),
8161 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4
, G2
),
8163 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265
, G2
),
8165 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3
, G2
),
8167 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4
, G2
),
8169 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266
, G2
),
8171 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3
, G2
),
8173 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4
, G2
),
8175 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270
, G2LE
),
8177 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271
, G2LE
),
8179 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272
, G2LE
),
8181 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275
, G2LE
),
8183 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280
, G2LE
),
8185 /* Generic PowerPC e200 core */
8186 POWERPC_DEF("e200", CPU_POWERPC_e200
, e200
),
8187 /* Generic MPC55xx core */
8189 POWERPC_DEF_SVR("MPC55xx",
8190 CPU_POWERPC_MPC55xx
, POWERPC_SVR_55xx
, e200
),
8193 /* PowerPC e200z0 core */
8194 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0
, e200
),
8197 /* PowerPC e200z1 core */
8198 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1
, e200
),
8201 /* PowerPC e200z3 core */
8202 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3
, e200
),
8204 /* PowerPC e200z5 core */
8205 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5
, e200
),
8206 /* PowerPC e200z6 core */
8207 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6
, e200
),
8208 /* PowerPC e200 microcontrollers */
8211 POWERPC_DEF_SVR("MPC5514E",
8212 CPU_POWERPC_MPC5514E
, POWERPC_SVR_5514E
, e200
),
8216 POWERPC_DEF_SVR("MPC5514E_v0",
8217 CPU_POWERPC_MPC5514E_v0
, POWERPC_SVR_5514E_v0
, e200
),
8221 POWERPC_DEF_SVR("MPC5514E_v1",
8222 CPU_POWERPC_MPC5514E_v1
, POWERPC_SVR_5514E_v1
, e200
),
8226 POWERPC_DEF_SVR("MPC5514G",
8227 CPU_POWERPC_MPC5514G
, POWERPC_SVR_5514G
, e200
),
8231 POWERPC_DEF_SVR("MPC5514G_v0",
8232 CPU_POWERPC_MPC5514G_v0
, POWERPC_SVR_5514G_v0
, e200
),
8236 POWERPC_DEF_SVR("MPC5514G_v1",
8237 CPU_POWERPC_MPC5514G_v1
, POWERPC_SVR_5514G_v1
, e200
),
8241 POWERPC_DEF_SVR("MPC5515S",
8242 CPU_POWERPC_MPC5515S
, POWERPC_SVR_5515S
, e200
),
8246 POWERPC_DEF_SVR("MPC5516E",
8247 CPU_POWERPC_MPC5516E
, POWERPC_SVR_5516E
, e200
),
8251 POWERPC_DEF_SVR("MPC5516E_v0",
8252 CPU_POWERPC_MPC5516E_v0
, POWERPC_SVR_5516E_v0
, e200
),
8256 POWERPC_DEF_SVR("MPC5516E_v1",
8257 CPU_POWERPC_MPC5516E_v1
, POWERPC_SVR_5516E_v1
, e200
),
8261 POWERPC_DEF_SVR("MPC5516G",
8262 CPU_POWERPC_MPC5516G
, POWERPC_SVR_5516G
, e200
),
8266 POWERPC_DEF_SVR("MPC5516G_v0",
8267 CPU_POWERPC_MPC5516G_v0
, POWERPC_SVR_5516G_v0
, e200
),
8271 POWERPC_DEF_SVR("MPC5516G_v1",
8272 CPU_POWERPC_MPC5516G_v1
, POWERPC_SVR_5516G_v1
, e200
),
8276 POWERPC_DEF_SVR("MPC5516S",
8277 CPU_POWERPC_MPC5516S
, POWERPC_SVR_5516S
, e200
),
8281 POWERPC_DEF_SVR("MPC5533",
8282 CPU_POWERPC_MPC5533
, POWERPC_SVR_5533
, e200
),
8286 POWERPC_DEF_SVR("MPC5534",
8287 CPU_POWERPC_MPC5534
, POWERPC_SVR_5534
, e200
),
8291 POWERPC_DEF_SVR("MPC5553",
8292 CPU_POWERPC_MPC5553
, POWERPC_SVR_5553
, e200
),
8296 POWERPC_DEF_SVR("MPC5554",
8297 CPU_POWERPC_MPC5554
, POWERPC_SVR_5554
, e200
),
8301 POWERPC_DEF_SVR("MPC5561",
8302 CPU_POWERPC_MPC5561
, POWERPC_SVR_5561
, e200
),
8306 POWERPC_DEF_SVR("MPC5565",
8307 CPU_POWERPC_MPC5565
, POWERPC_SVR_5565
, e200
),
8311 POWERPC_DEF_SVR("MPC5566",
8312 CPU_POWERPC_MPC5566
, POWERPC_SVR_5566
, e200
),
8316 POWERPC_DEF_SVR("MPC5567",
8317 CPU_POWERPC_MPC5567
, POWERPC_SVR_5567
, e200
),
8320 /* Generic PowerPC e300 core */
8321 POWERPC_DEF("e300", CPU_POWERPC_e300
, e300
),
8322 /* PowerPC e300c1 core */
8323 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1
, e300
),
8324 /* PowerPC e300c2 core */
8325 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2
, e300
),
8326 /* PowerPC e300c3 core */
8327 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3
, e300
),
8328 /* PowerPC e300c4 core */
8329 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4
, e300
),
8330 /* PowerPC e300 microcontrollers */
8333 POWERPC_DEF_SVR("MPC8313",
8334 CPU_POWERPC_MPC831x
, POWERPC_SVR_8313
, e300
),
8338 POWERPC_DEF_SVR("MPC8313E",
8339 CPU_POWERPC_MPC831x
, POWERPC_SVR_8313E
, e300
),
8343 POWERPC_DEF_SVR("MPC8314",
8344 CPU_POWERPC_MPC831x
, POWERPC_SVR_8314
, e300
),
8348 POWERPC_DEF_SVR("MPC8314E",
8349 CPU_POWERPC_MPC831x
, POWERPC_SVR_8314E
, e300
),
8353 POWERPC_DEF_SVR("MPC8315",
8354 CPU_POWERPC_MPC831x
, POWERPC_SVR_8315
, e300
),
8358 POWERPC_DEF_SVR("MPC8315E",
8359 CPU_POWERPC_MPC831x
, POWERPC_SVR_8315E
, e300
),
8363 POWERPC_DEF_SVR("MPC8321",
8364 CPU_POWERPC_MPC832x
, POWERPC_SVR_8321
, e300
),
8368 POWERPC_DEF_SVR("MPC8321E",
8369 CPU_POWERPC_MPC832x
, POWERPC_SVR_8321E
, e300
),
8373 POWERPC_DEF_SVR("MPC8323",
8374 CPU_POWERPC_MPC832x
, POWERPC_SVR_8323
, e300
),
8378 POWERPC_DEF_SVR("MPC8323E",
8379 CPU_POWERPC_MPC832x
, POWERPC_SVR_8323E
, e300
),
8382 POWERPC_DEF_SVR("MPC8343",
8383 CPU_POWERPC_MPC834x
, POWERPC_SVR_8343
, e300
),
8385 POWERPC_DEF_SVR("MPC8343A",
8386 CPU_POWERPC_MPC834x
, POWERPC_SVR_8343A
, e300
),
8388 POWERPC_DEF_SVR("MPC8343E",
8389 CPU_POWERPC_MPC834x
, POWERPC_SVR_8343E
, e300
),
8391 POWERPC_DEF_SVR("MPC8343EA",
8392 CPU_POWERPC_MPC834x
, POWERPC_SVR_8343EA
, e300
),
8394 POWERPC_DEF_SVR("MPC8347",
8395 CPU_POWERPC_MPC834x
, POWERPC_SVR_8347
, e300
),
8397 POWERPC_DEF_SVR("MPC8347T",
8398 CPU_POWERPC_MPC834x
, POWERPC_SVR_8347T
, e300
),
8400 POWERPC_DEF_SVR("MPC8347P",
8401 CPU_POWERPC_MPC834x
, POWERPC_SVR_8347P
, e300
),
8403 POWERPC_DEF_SVR("MPC8347A",
8404 CPU_POWERPC_MPC834x
, POWERPC_SVR_8347A
, e300
),
8406 POWERPC_DEF_SVR("MPC8347AT",
8407 CPU_POWERPC_MPC834x
, POWERPC_SVR_8347AT
, e300
),
8409 POWERPC_DEF_SVR("MPC8347AP",
8410 CPU_POWERPC_MPC834x
, POWERPC_SVR_8347AP
, e300
),
8412 POWERPC_DEF_SVR("MPC8347E",
8413 CPU_POWERPC_MPC834x
, POWERPC_SVR_8347E
, e300
),
8415 POWERPC_DEF_SVR("MPC8347ET",
8416 CPU_POWERPC_MPC834x
, POWERPC_SVR_8347ET
, e300
),
8418 POWERPC_DEF_SVR("MPC8347EP",
8419 CPU_POWERPC_MPC834x
, POWERPC_SVR_8347EP
, e300
),
8421 POWERPC_DEF_SVR("MPC8347EA",
8422 CPU_POWERPC_MPC834x
, POWERPC_SVR_8347EA
, e300
),
8424 POWERPC_DEF_SVR("MPC8347EAT",
8425 CPU_POWERPC_MPC834x
, POWERPC_SVR_8347EAT
, e300
),
8427 POWERPC_DEF_SVR("MPC8347EAP",
8428 CPU_POWERPC_MPC834x
, POWERPC_SVR_8347EAP
, e300
),
8430 POWERPC_DEF_SVR("MPC8349",
8431 CPU_POWERPC_MPC834x
, POWERPC_SVR_8349
, e300
),
8433 POWERPC_DEF_SVR("MPC8349A",
8434 CPU_POWERPC_MPC834x
, POWERPC_SVR_8349A
, e300
),
8436 POWERPC_DEF_SVR("MPC8349E",
8437 CPU_POWERPC_MPC834x
, POWERPC_SVR_8349E
, e300
),
8439 POWERPC_DEF_SVR("MPC8349EA",
8440 CPU_POWERPC_MPC834x
, POWERPC_SVR_8349EA
, e300
),
8443 POWERPC_DEF_SVR("MPC8358E",
8444 CPU_POWERPC_MPC835x
, POWERPC_SVR_8358E
, e300
),
8448 POWERPC_DEF_SVR("MPC8360E",
8449 CPU_POWERPC_MPC836x
, POWERPC_SVR_8360E
, e300
),
8452 POWERPC_DEF_SVR("MPC8377",
8453 CPU_POWERPC_MPC837x
, POWERPC_SVR_8377
, e300
),
8455 POWERPC_DEF_SVR("MPC8377E",
8456 CPU_POWERPC_MPC837x
, POWERPC_SVR_8377E
, e300
),
8458 POWERPC_DEF_SVR("MPC8378",
8459 CPU_POWERPC_MPC837x
, POWERPC_SVR_8378
, e300
),
8461 POWERPC_DEF_SVR("MPC8378E",
8462 CPU_POWERPC_MPC837x
, POWERPC_SVR_8378E
, e300
),
8464 POWERPC_DEF_SVR("MPC8379",
8465 CPU_POWERPC_MPC837x
, POWERPC_SVR_8379
, e300
),
8467 POWERPC_DEF_SVR("MPC8379E",
8468 CPU_POWERPC_MPC837x
, POWERPC_SVR_8379E
, e300
),
8470 /* PowerPC e500 core */
8471 POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22
, e500v2
),
8472 /* PowerPC e500v1 core */
8473 POWERPC_DEF("e500v1", CPU_POWERPC_e500v1
, e500v1
),
8474 /* PowerPC e500 v1.0 core */
8475 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10
, e500v1
),
8476 /* PowerPC e500 v2.0 core */
8477 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20
, e500v1
),
8478 /* PowerPC e500v2 core */
8479 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2
, e500v2
),
8480 /* PowerPC e500v2 v1.0 core */
8481 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10
, e500v2
),
8482 /* PowerPC e500v2 v2.0 core */
8483 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20
, e500v2
),
8484 /* PowerPC e500v2 v2.1 core */
8485 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21
, e500v2
),
8486 /* PowerPC e500v2 v2.2 core */
8487 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22
, e500v2
),
8488 /* PowerPC e500v2 v3.0 core */
8489 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30
, e500v2
),
8490 /* PowerPC e500 microcontrollers */
8492 POWERPC_DEF_SVR("MPC8533",
8493 CPU_POWERPC_MPC8533
, POWERPC_SVR_8533
, e500v2
),
8495 POWERPC_DEF_SVR("MPC8533_v10",
8496 CPU_POWERPC_MPC8533_v10
, POWERPC_SVR_8533_v10
, e500v2
),
8498 POWERPC_DEF_SVR("MPC8533_v11",
8499 CPU_POWERPC_MPC8533_v11
, POWERPC_SVR_8533_v11
, e500v2
),
8501 POWERPC_DEF_SVR("MPC8533E",
8502 CPU_POWERPC_MPC8533E
, POWERPC_SVR_8533E
, e500v2
),
8504 POWERPC_DEF_SVR("MPC8533E_v10",
8505 CPU_POWERPC_MPC8533E_v10
, POWERPC_SVR_8533E_v10
, e500v2
),
8506 POWERPC_DEF_SVR("MPC8533E_v11",
8507 CPU_POWERPC_MPC8533E_v11
, POWERPC_SVR_8533E_v11
, e500v2
),
8509 POWERPC_DEF_SVR("MPC8540",
8510 CPU_POWERPC_MPC8540
, POWERPC_SVR_8540
, e500v1
),
8512 POWERPC_DEF_SVR("MPC8540_v10",
8513 CPU_POWERPC_MPC8540_v10
, POWERPC_SVR_8540_v10
, e500v1
),
8515 POWERPC_DEF_SVR("MPC8540_v20",
8516 CPU_POWERPC_MPC8540_v20
, POWERPC_SVR_8540_v20
, e500v1
),
8518 POWERPC_DEF_SVR("MPC8540_v21",
8519 CPU_POWERPC_MPC8540_v21
, POWERPC_SVR_8540_v21
, e500v1
),
8521 POWERPC_DEF_SVR("MPC8541",
8522 CPU_POWERPC_MPC8541
, POWERPC_SVR_8541
, e500v1
),
8524 POWERPC_DEF_SVR("MPC8541_v10",
8525 CPU_POWERPC_MPC8541_v10
, POWERPC_SVR_8541_v10
, e500v1
),
8527 POWERPC_DEF_SVR("MPC8541_v11",
8528 CPU_POWERPC_MPC8541_v11
, POWERPC_SVR_8541_v11
, e500v1
),
8530 POWERPC_DEF_SVR("MPC8541E",
8531 CPU_POWERPC_MPC8541E
, POWERPC_SVR_8541E
, e500v1
),
8533 POWERPC_DEF_SVR("MPC8541E_v10",
8534 CPU_POWERPC_MPC8541E_v10
, POWERPC_SVR_8541E_v10
, e500v1
),
8536 POWERPC_DEF_SVR("MPC8541E_v11",
8537 CPU_POWERPC_MPC8541E_v11
, POWERPC_SVR_8541E_v11
, e500v1
),
8539 POWERPC_DEF_SVR("MPC8543",
8540 CPU_POWERPC_MPC8543
, POWERPC_SVR_8543
, e500v2
),
8542 POWERPC_DEF_SVR("MPC8543_v10",
8543 CPU_POWERPC_MPC8543_v10
, POWERPC_SVR_8543_v10
, e500v2
),
8545 POWERPC_DEF_SVR("MPC8543_v11",
8546 CPU_POWERPC_MPC8543_v11
, POWERPC_SVR_8543_v11
, e500v2
),
8548 POWERPC_DEF_SVR("MPC8543_v20",
8549 CPU_POWERPC_MPC8543_v20
, POWERPC_SVR_8543_v20
, e500v2
),
8551 POWERPC_DEF_SVR("MPC8543_v21",
8552 CPU_POWERPC_MPC8543_v21
, POWERPC_SVR_8543_v21
, e500v2
),
8554 POWERPC_DEF_SVR("MPC8543E",
8555 CPU_POWERPC_MPC8543E
, POWERPC_SVR_8543E
, e500v2
),
8557 POWERPC_DEF_SVR("MPC8543E_v10",
8558 CPU_POWERPC_MPC8543E_v10
, POWERPC_SVR_8543E_v10
, e500v2
),
8560 POWERPC_DEF_SVR("MPC8543E_v11",
8561 CPU_POWERPC_MPC8543E_v11
, POWERPC_SVR_8543E_v11
, e500v2
),
8563 POWERPC_DEF_SVR("MPC8543E_v20",
8564 CPU_POWERPC_MPC8543E_v20
, POWERPC_SVR_8543E_v20
, e500v2
),
8566 POWERPC_DEF_SVR("MPC8543E_v21",
8567 CPU_POWERPC_MPC8543E_v21
, POWERPC_SVR_8543E_v21
, e500v2
),
8569 POWERPC_DEF_SVR("MPC8544",
8570 CPU_POWERPC_MPC8544
, POWERPC_SVR_8544
, e500v2
),
8572 POWERPC_DEF_SVR("MPC8544_v10",
8573 CPU_POWERPC_MPC8544_v10
, POWERPC_SVR_8544_v10
, e500v2
),
8575 POWERPC_DEF_SVR("MPC8544_v11",
8576 CPU_POWERPC_MPC8544_v11
, POWERPC_SVR_8544_v11
, e500v2
),
8578 POWERPC_DEF_SVR("MPC8544E",
8579 CPU_POWERPC_MPC8544E
, POWERPC_SVR_8544E
, e500v2
),
8581 POWERPC_DEF_SVR("MPC8544E_v10",
8582 CPU_POWERPC_MPC8544E_v10
, POWERPC_SVR_8544E_v10
, e500v2
),
8584 POWERPC_DEF_SVR("MPC8544E_v11",
8585 CPU_POWERPC_MPC8544E_v11
, POWERPC_SVR_8544E_v11
, e500v2
),
8587 POWERPC_DEF_SVR("MPC8545",
8588 CPU_POWERPC_MPC8545
, POWERPC_SVR_8545
, e500v2
),
8590 POWERPC_DEF_SVR("MPC8545_v20",
8591 CPU_POWERPC_MPC8545_v20
, POWERPC_SVR_8545_v20
, e500v2
),
8593 POWERPC_DEF_SVR("MPC8545_v21",
8594 CPU_POWERPC_MPC8545_v21
, POWERPC_SVR_8545_v21
, e500v2
),
8596 POWERPC_DEF_SVR("MPC8545E",
8597 CPU_POWERPC_MPC8545E
, POWERPC_SVR_8545E
, e500v2
),
8599 POWERPC_DEF_SVR("MPC8545E_v20",
8600 CPU_POWERPC_MPC8545E_v20
, POWERPC_SVR_8545E_v20
, e500v2
),
8602 POWERPC_DEF_SVR("MPC8545E_v21",
8603 CPU_POWERPC_MPC8545E_v21
, POWERPC_SVR_8545E_v21
, e500v2
),
8605 POWERPC_DEF_SVR("MPC8547E",
8606 CPU_POWERPC_MPC8547E
, POWERPC_SVR_8547E
, e500v2
),
8608 POWERPC_DEF_SVR("MPC8547E_v20",
8609 CPU_POWERPC_MPC8547E_v20
, POWERPC_SVR_8547E_v20
, e500v2
),
8611 POWERPC_DEF_SVR("MPC8547E_v21",
8612 CPU_POWERPC_MPC8547E_v21
, POWERPC_SVR_8547E_v21
, e500v2
),
8614 POWERPC_DEF_SVR("MPC8548",
8615 CPU_POWERPC_MPC8548
, POWERPC_SVR_8548
, e500v2
),
8617 POWERPC_DEF_SVR("MPC8548_v10",
8618 CPU_POWERPC_MPC8548_v10
, POWERPC_SVR_8548_v10
, e500v2
),
8620 POWERPC_DEF_SVR("MPC8548_v11",
8621 CPU_POWERPC_MPC8548_v11
, POWERPC_SVR_8548_v11
, e500v2
),
8623 POWERPC_DEF_SVR("MPC8548_v20",
8624 CPU_POWERPC_MPC8548_v20
, POWERPC_SVR_8548_v20
, e500v2
),
8626 POWERPC_DEF_SVR("MPC8548_v21",
8627 CPU_POWERPC_MPC8548_v21
, POWERPC_SVR_8548_v21
, e500v2
),
8629 POWERPC_DEF_SVR("MPC8548E",
8630 CPU_POWERPC_MPC8548E
, POWERPC_SVR_8548E
, e500v2
),
8632 POWERPC_DEF_SVR("MPC8548E_v10",
8633 CPU_POWERPC_MPC8548E_v10
, POWERPC_SVR_8548E_v10
, e500v2
),
8635 POWERPC_DEF_SVR("MPC8548E_v11",
8636 CPU_POWERPC_MPC8548E_v11
, POWERPC_SVR_8548E_v11
, e500v2
),
8638 POWERPC_DEF_SVR("MPC8548E_v20",
8639 CPU_POWERPC_MPC8548E_v20
, POWERPC_SVR_8548E_v20
, e500v2
),
8641 POWERPC_DEF_SVR("MPC8548E_v21",
8642 CPU_POWERPC_MPC8548E_v21
, POWERPC_SVR_8548E_v21
, e500v2
),
8644 POWERPC_DEF_SVR("MPC8555",
8645 CPU_POWERPC_MPC8555
, POWERPC_SVR_8555
, e500v2
),
8647 POWERPC_DEF_SVR("MPC8555_v10",
8648 CPU_POWERPC_MPC8555_v10
, POWERPC_SVR_8555_v10
, e500v2
),
8650 POWERPC_DEF_SVR("MPC8555_v11",
8651 CPU_POWERPC_MPC8555_v11
, POWERPC_SVR_8555_v11
, e500v2
),
8653 POWERPC_DEF_SVR("MPC8555E",
8654 CPU_POWERPC_MPC8555E
, POWERPC_SVR_8555E
, e500v2
),
8656 POWERPC_DEF_SVR("MPC8555E_v10",
8657 CPU_POWERPC_MPC8555E_v10
, POWERPC_SVR_8555E_v10
, e500v2
),
8659 POWERPC_DEF_SVR("MPC8555E_v11",
8660 CPU_POWERPC_MPC8555E_v11
, POWERPC_SVR_8555E_v11
, e500v2
),
8662 POWERPC_DEF_SVR("MPC8560",
8663 CPU_POWERPC_MPC8560
, POWERPC_SVR_8560
, e500v2
),
8665 POWERPC_DEF_SVR("MPC8560_v10",
8666 CPU_POWERPC_MPC8560_v10
, POWERPC_SVR_8560_v10
, e500v2
),
8668 POWERPC_DEF_SVR("MPC8560_v20",
8669 CPU_POWERPC_MPC8560_v20
, POWERPC_SVR_8560_v20
, e500v2
),
8671 POWERPC_DEF_SVR("MPC8560_v21",
8672 CPU_POWERPC_MPC8560_v21
, POWERPC_SVR_8560_v21
, e500v2
),
8674 POWERPC_DEF_SVR("MPC8567",
8675 CPU_POWERPC_MPC8567
, POWERPC_SVR_8567
, e500v2
),
8677 POWERPC_DEF_SVR("MPC8567E",
8678 CPU_POWERPC_MPC8567E
, POWERPC_SVR_8567E
, e500v2
),
8680 POWERPC_DEF_SVR("MPC8568",
8681 CPU_POWERPC_MPC8568
, POWERPC_SVR_8568
, e500v2
),
8683 POWERPC_DEF_SVR("MPC8568E",
8684 CPU_POWERPC_MPC8568E
, POWERPC_SVR_8568E
, e500v2
),
8686 POWERPC_DEF_SVR("MPC8572",
8687 CPU_POWERPC_MPC8572
, POWERPC_SVR_8572
, e500v2
),
8689 POWERPC_DEF_SVR("MPC8572E",
8690 CPU_POWERPC_MPC8572E
, POWERPC_SVR_8572E
, e500v2
),
8692 /* PowerPC e600 core */
8693 POWERPC_DEF("e600", CPU_POWERPC_e600
, 7400),
8694 /* PowerPC e600 microcontrollers */
8697 POWERPC_DEF_SVR("MPC8610",
8698 CPU_POWERPC_MPC8610
, POWERPC_SVR_8610
, 7400),
8701 POWERPC_DEF_SVR("MPC8641",
8702 CPU_POWERPC_MPC8641
, POWERPC_SVR_8641
, 7400),
8704 POWERPC_DEF_SVR("MPC8641D",
8705 CPU_POWERPC_MPC8641D
, POWERPC_SVR_8641D
, 7400),
8706 /* 32 bits "classic" PowerPC */
8707 /* PowerPC 6xx family */
8709 POWERPC_DEF("601", CPU_POWERPC_601
, 601v
),
8711 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0
, 601),
8713 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1
, 601),
8715 POWERPC_DEF("601v", CPU_POWERPC_601v
, 601v
),
8717 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2
, 601v
),
8719 POWERPC_DEF("602", CPU_POWERPC_602
, 602),
8721 POWERPC_DEF("603", CPU_POWERPC_603
, 603),
8722 /* Code name for PowerPC 603 */
8723 POWERPC_DEF("Vanilla", CPU_POWERPC_603
, 603),
8724 /* PowerPC 603e (aka PID6) */
8725 POWERPC_DEF("603e", CPU_POWERPC_603E
, 603E
),
8726 /* Code name for PowerPC 603e */
8727 POWERPC_DEF("Stretch", CPU_POWERPC_603E
, 603E
),
8728 /* PowerPC 603e v1.1 */
8729 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11
, 603E
),
8730 /* PowerPC 603e v1.2 */
8731 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12
, 603E
),
8732 /* PowerPC 603e v1.3 */
8733 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13
, 603E
),
8734 /* PowerPC 603e v1.4 */
8735 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14
, 603E
),
8736 /* PowerPC 603e v2.2 */
8737 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22
, 603E
),
8738 /* PowerPC 603e v3 */
8739 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3
, 603E
),
8740 /* PowerPC 603e v4 */
8741 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4
, 603E
),
8742 /* PowerPC 603e v4.1 */
8743 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41
, 603E
),
8744 /* PowerPC 603e (aka PID7) */
8745 POWERPC_DEF("603e7", CPU_POWERPC_603E7
, 603E
),
8746 /* PowerPC 603e7t */
8747 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t
, 603E
),
8748 /* PowerPC 603e7v */
8749 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v
, 603E
),
8750 /* Code name for PowerPC 603ev */
8751 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v
, 603E
),
8752 /* PowerPC 603e7v1 */
8753 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1
, 603E
),
8754 /* PowerPC 603e7v2 */
8755 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2
, 603E
),
8756 /* PowerPC 603p (aka PID7v) */
8757 POWERPC_DEF("603p", CPU_POWERPC_603P
, 603E
),
8758 /* PowerPC 603r (aka PID7t) */
8759 POWERPC_DEF("603r", CPU_POWERPC_603R
, 603E
),
8760 /* Code name for PowerPC 603r */
8761 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R
, 603E
),
8763 POWERPC_DEF("604", CPU_POWERPC_604
, 604),
8764 /* PowerPC 604e (aka PID9) */
8765 POWERPC_DEF("604e", CPU_POWERPC_604E
, 604E
),
8766 /* Code name for PowerPC 604e */
8767 POWERPC_DEF("Sirocco", CPU_POWERPC_604E
, 604E
),
8768 /* PowerPC 604e v1.0 */
8769 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10
, 604E
),
8770 /* PowerPC 604e v2.2 */
8771 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22
, 604E
),
8772 /* PowerPC 604e v2.4 */
8773 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24
, 604E
),
8774 /* PowerPC 604r (aka PIDA) */
8775 POWERPC_DEF("604r", CPU_POWERPC_604R
, 604E
),
8776 /* Code name for PowerPC 604r */
8777 POWERPC_DEF("Mach5", CPU_POWERPC_604R
, 604E
),
8780 POWERPC_DEF("604ev", CPU_POWERPC_604EV
, 604E
),
8782 /* PowerPC 7xx family */
8783 /* Generic PowerPC 740 (G3) */
8784 POWERPC_DEF("740", CPU_POWERPC_7x0
, 740),
8785 /* Code name for PowerPC 740 */
8786 POWERPC_DEF("Arthur", CPU_POWERPC_7x0
, 740),
8787 /* Generic PowerPC 750 (G3) */
8788 POWERPC_DEF("750", CPU_POWERPC_7x0
, 750),
8789 /* Code name for PowerPC 750 */
8790 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0
, 750),
8791 /* PowerPC 740/750 is also known as G3 */
8792 POWERPC_DEF("G3", CPU_POWERPC_7x0
, 750),
8793 /* PowerPC 740 v1.0 (G3) */
8794 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10
, 740),
8795 /* PowerPC 750 v1.0 (G3) */
8796 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10
, 750),
8797 /* PowerPC 740 v2.0 (G3) */
8798 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20
, 740),
8799 /* PowerPC 750 v2.0 (G3) */
8800 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20
, 750),
8801 /* PowerPC 740 v2.1 (G3) */
8802 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21
, 740),
8803 /* PowerPC 750 v2.1 (G3) */
8804 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21
, 750),
8805 /* PowerPC 740 v2.2 (G3) */
8806 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22
, 740),
8807 /* PowerPC 750 v2.2 (G3) */
8808 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22
, 750),
8809 /* PowerPC 740 v3.0 (G3) */
8810 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30
, 740),
8811 /* PowerPC 750 v3.0 (G3) */
8812 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30
, 750),
8813 /* PowerPC 740 v3.1 (G3) */
8814 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31
, 740),
8815 /* PowerPC 750 v3.1 (G3) */
8816 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31
, 750),
8817 /* PowerPC 740E (G3) */
8818 POWERPC_DEF("740e", CPU_POWERPC_740E
, 740),
8819 /* PowerPC 750E (G3) */
8820 POWERPC_DEF("750e", CPU_POWERPC_750E
, 750),
8821 /* PowerPC 740P (G3) */
8822 POWERPC_DEF("740p", CPU_POWERPC_7x0P
, 740),
8823 /* PowerPC 750P (G3) */
8824 POWERPC_DEF("750p", CPU_POWERPC_7x0P
, 750),
8825 /* Code name for PowerPC 740P/750P (G3) */
8826 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P
, 750),
8827 /* PowerPC 750CL (G3 embedded) */
8828 POWERPC_DEF("750cl", CPU_POWERPC_750CL
, 750cl
),
8829 /* PowerPC 750CL v1.0 */
8830 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10
, 750cl
),
8831 /* PowerPC 750CL v2.0 */
8832 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20
, 750cl
),
8833 /* PowerPC 750CX (G3 embedded) */
8834 POWERPC_DEF("750cx", CPU_POWERPC_750CX
, 750cx
),
8835 /* PowerPC 750CX v1.0 (G3 embedded) */
8836 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10
, 750cx
),
8837 /* PowerPC 750CX v2.1 (G3 embedded) */
8838 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20
, 750cx
),
8839 /* PowerPC 750CX v2.1 (G3 embedded) */
8840 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21
, 750cx
),
8841 /* PowerPC 750CX v2.2 (G3 embedded) */
8842 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22
, 750cx
),
8843 /* PowerPC 750CXe (G3 embedded) */
8844 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE
, 750cx
),
8845 /* PowerPC 750CXe v2.1 (G3 embedded) */
8846 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21
, 750cx
),
8847 /* PowerPC 750CXe v2.2 (G3 embedded) */
8848 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22
, 750cx
),
8849 /* PowerPC 750CXe v2.3 (G3 embedded) */
8850 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23
, 750cx
),
8851 /* PowerPC 750CXe v2.4 (G3 embedded) */
8852 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24
, 750cx
),
8853 /* PowerPC 750CXe v2.4b (G3 embedded) */
8854 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b
, 750cx
),
8855 /* PowerPC 750CXe v3.0 (G3 embedded) */
8856 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30
, 750cx
),
8857 /* PowerPC 750CXe v3.1 (G3 embedded) */
8858 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31
, 750cx
),
8859 /* PowerPC 750CXe v3.1b (G3 embedded) */
8860 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b
, 750cx
),
8861 /* PowerPC 750CXr (G3 embedded) */
8862 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR
, 750cx
),
8863 /* PowerPC 750FL (G3 embedded) */
8864 POWERPC_DEF("750fl", CPU_POWERPC_750FL
, 750fx
),
8865 /* PowerPC 750FX (G3 embedded) */
8866 POWERPC_DEF("750fx", CPU_POWERPC_750FX
, 750fx
),
8867 /* PowerPC 750FX v1.0 (G3 embedded) */
8868 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10
, 750fx
),
8869 /* PowerPC 750FX v2.0 (G3 embedded) */
8870 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20
, 750fx
),
8871 /* PowerPC 750FX v2.1 (G3 embedded) */
8872 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21
, 750fx
),
8873 /* PowerPC 750FX v2.2 (G3 embedded) */
8874 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22
, 750fx
),
8875 /* PowerPC 750FX v2.3 (G3 embedded) */
8876 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23
, 750fx
),
8877 /* PowerPC 750GL (G3 embedded) */
8878 POWERPC_DEF("750gl", CPU_POWERPC_750GL
, 750gx
),
8879 /* PowerPC 750GX (G3 embedded) */
8880 POWERPC_DEF("750gx", CPU_POWERPC_750GX
, 750gx
),
8881 /* PowerPC 750GX v1.0 (G3 embedded) */
8882 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10
, 750gx
),
8883 /* PowerPC 750GX v1.1 (G3 embedded) */
8884 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11
, 750gx
),
8885 /* PowerPC 750GX v1.2 (G3 embedded) */
8886 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12
, 750gx
),
8887 /* PowerPC 750L (G3 embedded) */
8888 POWERPC_DEF("750l", CPU_POWERPC_750L
, 750),
8889 /* Code name for PowerPC 750L (G3 embedded) */
8890 POWERPC_DEF("LoneStar", CPU_POWERPC_750L
, 750),
8891 /* PowerPC 750L v2.0 (G3 embedded) */
8892 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20
, 750),
8893 /* PowerPC 750L v2.1 (G3 embedded) */
8894 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21
, 750),
8895 /* PowerPC 750L v2.2 (G3 embedded) */
8896 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22
, 750),
8897 /* PowerPC 750L v3.0 (G3 embedded) */
8898 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30
, 750),
8899 /* PowerPC 750L v3.2 (G3 embedded) */
8900 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32
, 750),
8901 /* Generic PowerPC 745 */
8902 POWERPC_DEF("745", CPU_POWERPC_7x5
, 745),
8903 /* Generic PowerPC 755 */
8904 POWERPC_DEF("755", CPU_POWERPC_7x5
, 755),
8905 /* Code name for PowerPC 745/755 */
8906 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5
, 755),
8907 /* PowerPC 745 v1.0 */
8908 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10
, 745),
8909 /* PowerPC 755 v1.0 */
8910 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10
, 755),
8911 /* PowerPC 745 v1.1 */
8912 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11
, 745),
8913 /* PowerPC 755 v1.1 */
8914 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11
, 755),
8915 /* PowerPC 745 v2.0 */
8916 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20
, 745),
8917 /* PowerPC 755 v2.0 */
8918 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20
, 755),
8919 /* PowerPC 745 v2.1 */
8920 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21
, 745),
8921 /* PowerPC 755 v2.1 */
8922 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21
, 755),
8923 /* PowerPC 745 v2.2 */
8924 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22
, 745),
8925 /* PowerPC 755 v2.2 */
8926 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22
, 755),
8927 /* PowerPC 745 v2.3 */
8928 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23
, 745),
8929 /* PowerPC 755 v2.3 */
8930 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23
, 755),
8931 /* PowerPC 745 v2.4 */
8932 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24
, 745),
8933 /* PowerPC 755 v2.4 */
8934 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24
, 755),
8935 /* PowerPC 745 v2.5 */
8936 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25
, 745),
8937 /* PowerPC 755 v2.5 */
8938 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25
, 755),
8939 /* PowerPC 745 v2.6 */
8940 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26
, 745),
8941 /* PowerPC 755 v2.6 */
8942 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26
, 755),
8943 /* PowerPC 745 v2.7 */
8944 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27
, 745),
8945 /* PowerPC 755 v2.7 */
8946 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27
, 755),
8947 /* PowerPC 745 v2.8 */
8948 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28
, 745),
8949 /* PowerPC 755 v2.8 */
8950 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28
, 755),
8952 /* PowerPC 745P (G3) */
8953 POWERPC_DEF("745p", CPU_POWERPC_7x5P
, 745),
8954 /* PowerPC 755P (G3) */
8955 POWERPC_DEF("755p", CPU_POWERPC_7x5P
, 755),
8957 /* PowerPC 74xx family */
8958 /* PowerPC 7400 (G4) */
8959 POWERPC_DEF("7400", CPU_POWERPC_7400
, 7400),
8960 /* Code name for PowerPC 7400 */
8961 POWERPC_DEF("Max", CPU_POWERPC_7400
, 7400),
8962 /* PowerPC 74xx is also well known as G4 */
8963 POWERPC_DEF("G4", CPU_POWERPC_7400
, 7400),
8964 /* PowerPC 7400 v1.0 (G4) */
8965 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10
, 7400),
8966 /* PowerPC 7400 v1.1 (G4) */
8967 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11
, 7400),
8968 /* PowerPC 7400 v2.0 (G4) */
8969 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20
, 7400),
8970 /* PowerPC 7400 v2.1 (G4) */
8971 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21
, 7400),
8972 /* PowerPC 7400 v2.2 (G4) */
8973 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22
, 7400),
8974 /* PowerPC 7400 v2.6 (G4) */
8975 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26
, 7400),
8976 /* PowerPC 7400 v2.7 (G4) */
8977 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27
, 7400),
8978 /* PowerPC 7400 v2.8 (G4) */
8979 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28
, 7400),
8980 /* PowerPC 7400 v2.9 (G4) */
8981 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29
, 7400),
8982 /* PowerPC 7410 (G4) */
8983 POWERPC_DEF("7410", CPU_POWERPC_7410
, 7410),
8984 /* Code name for PowerPC 7410 */
8985 POWERPC_DEF("Nitro", CPU_POWERPC_7410
, 7410),
8986 /* PowerPC 7410 v1.0 (G4) */
8987 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10
, 7410),
8988 /* PowerPC 7410 v1.1 (G4) */
8989 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11
, 7410),
8990 /* PowerPC 7410 v1.2 (G4) */
8991 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12
, 7410),
8992 /* PowerPC 7410 v1.3 (G4) */
8993 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13
, 7410),
8994 /* PowerPC 7410 v1.4 (G4) */
8995 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14
, 7410),
8996 /* PowerPC 7448 (G4) */
8997 POWERPC_DEF("7448", CPU_POWERPC_7448
, 7400),
8998 /* PowerPC 7448 v1.0 (G4) */
8999 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10
, 7400),
9000 /* PowerPC 7448 v1.1 (G4) */
9001 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11
, 7400),
9002 /* PowerPC 7448 v2.0 (G4) */
9003 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20
, 7400),
9004 /* PowerPC 7448 v2.1 (G4) */
9005 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21
, 7400),
9006 /* PowerPC 7450 (G4) */
9007 POWERPC_DEF("7450", CPU_POWERPC_7450
, 7450),
9008 /* Code name for PowerPC 7450 */
9009 POWERPC_DEF("Vger", CPU_POWERPC_7450
, 7450),
9010 /* PowerPC 7450 v1.0 (G4) */
9011 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10
, 7450),
9012 /* PowerPC 7450 v1.1 (G4) */
9013 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11
, 7450),
9014 /* PowerPC 7450 v1.2 (G4) */
9015 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12
, 7450),
9016 /* PowerPC 7450 v2.0 (G4) */
9017 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20
, 7450),
9018 /* PowerPC 7450 v2.1 (G4) */
9019 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21
, 7450),
9020 /* PowerPC 7441 (G4) */
9021 POWERPC_DEF("7441", CPU_POWERPC_74x1
, 7440),
9022 /* PowerPC 7451 (G4) */
9023 POWERPC_DEF("7451", CPU_POWERPC_74x1
, 7450),
9024 /* PowerPC 7441 v2.1 (G4) */
9025 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21
, 7440),
9026 /* PowerPC 7441 v2.3 (G4) */
9027 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23
, 7440),
9028 /* PowerPC 7451 v2.3 (G4) */
9029 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23
, 7450),
9030 /* PowerPC 7441 v2.10 (G4) */
9031 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210
, 7440),
9032 /* PowerPC 7451 v2.10 (G4) */
9033 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210
, 7450),
9034 /* PowerPC 7445 (G4) */
9035 POWERPC_DEF("7445", CPU_POWERPC_74x5
, 7445),
9036 /* PowerPC 7455 (G4) */
9037 POWERPC_DEF("7455", CPU_POWERPC_74x5
, 7455),
9038 /* Code name for PowerPC 7445/7455 */
9039 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5
, 7455),
9040 /* PowerPC 7445 v1.0 (G4) */
9041 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10
, 7445),
9042 /* PowerPC 7455 v1.0 (G4) */
9043 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10
, 7455),
9044 /* PowerPC 7445 v2.1 (G4) */
9045 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21
, 7445),
9046 /* PowerPC 7455 v2.1 (G4) */
9047 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21
, 7455),
9048 /* PowerPC 7445 v3.2 (G4) */
9049 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32
, 7445),
9050 /* PowerPC 7455 v3.2 (G4) */
9051 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32
, 7455),
9052 /* PowerPC 7445 v3.3 (G4) */
9053 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33
, 7445),
9054 /* PowerPC 7455 v3.3 (G4) */
9055 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33
, 7455),
9056 /* PowerPC 7445 v3.4 (G4) */
9057 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34
, 7445),
9058 /* PowerPC 7455 v3.4 (G4) */
9059 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34
, 7455),
9060 /* PowerPC 7447 (G4) */
9061 POWERPC_DEF("7447", CPU_POWERPC_74x7
, 7445),
9062 /* PowerPC 7457 (G4) */
9063 POWERPC_DEF("7457", CPU_POWERPC_74x7
, 7455),
9064 /* Code name for PowerPC 7447/7457 */
9065 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7
, 7455),
9066 /* PowerPC 7447 v1.0 (G4) */
9067 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10
, 7445),
9068 /* PowerPC 7457 v1.0 (G4) */
9069 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10
, 7455),
9070 /* PowerPC 7447 v1.1 (G4) */
9071 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11
, 7445),
9072 /* PowerPC 7457 v1.1 (G4) */
9073 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11
, 7455),
9074 /* PowerPC 7457 v1.2 (G4) */
9075 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12
, 7455),
9076 /* PowerPC 7447A (G4) */
9077 POWERPC_DEF("7447A", CPU_POWERPC_74x7A
, 7445),
9078 /* PowerPC 7457A (G4) */
9079 POWERPC_DEF("7457A", CPU_POWERPC_74x7A
, 7455),
9080 /* PowerPC 7447A v1.0 (G4) */
9081 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10
, 7445),
9082 /* PowerPC 7457A v1.0 (G4) */
9083 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10
, 7455),
9084 /* Code name for PowerPC 7447A/7457A */
9085 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10
, 7455),
9086 /* PowerPC 7447A v1.1 (G4) */
9087 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11
, 7445),
9088 /* PowerPC 7457A v1.1 (G4) */
9089 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11
, 7455),
9090 /* PowerPC 7447A v1.2 (G4) */
9091 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12
, 7445),
9092 /* PowerPC 7457A v1.2 (G4) */
9093 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12
, 7455),
9094 /* 64 bits PowerPC */
9095 #if defined (TARGET_PPC64)
9097 POWERPC_DEF("620", CPU_POWERPC_620
, 620),
9098 /* Code name for PowerPC 620 */
9099 POWERPC_DEF("Trident", CPU_POWERPC_620
, 620),
9101 /* PowerPC 630 (POWER3) */
9102 POWERPC_DEF("630", CPU_POWERPC_630
, 630),
9103 POWERPC_DEF("POWER3", CPU_POWERPC_630
, 630),
9104 /* Code names for POWER3 */
9105 POWERPC_DEF("Boxer", CPU_POWERPC_630
, 630),
9106 POWERPC_DEF("Dino", CPU_POWERPC_630
, 630),
9109 /* PowerPC 631 (Power 3+) */
9110 POWERPC_DEF("631", CPU_POWERPC_631
, 631),
9111 POWERPC_DEF("POWER3+", CPU_POWERPC_631
, 631),
9115 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4
, POWER4
),
9119 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P
, POWER4P
),
9123 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5
, POWER5
),
9125 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR
, POWER5
),
9129 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P
, POWER5P
),
9131 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS
, POWER5P
),
9135 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6
, POWER6
),
9136 /* POWER6 running in POWER5 mode */
9137 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5
, POWER5
),
9139 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A
, POWER6
),
9142 POWERPC_DEF("POWER7", CPU_POWERPC_POWER7
, POWER7
),
9143 POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20
, POWER7
),
9144 POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21
, POWER7
),
9145 POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23
, POWER7
),
9147 POWERPC_DEF("970", CPU_POWERPC_970
, 970),
9148 /* PowerPC 970FX (G5) */
9149 POWERPC_DEF("970fx", CPU_POWERPC_970FX
, 970FX
),
9150 /* PowerPC 970FX v1.0 (G5) */
9151 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10
, 970FX
),
9152 /* PowerPC 970FX v2.0 (G5) */
9153 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20
, 970FX
),
9154 /* PowerPC 970FX v2.1 (G5) */
9155 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21
, 970FX
),
9156 /* PowerPC 970FX v3.0 (G5) */
9157 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30
, 970FX
),
9158 /* PowerPC 970FX v3.1 (G5) */
9159 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31
, 970FX
),
9160 /* PowerPC 970GX (G5) */
9161 POWERPC_DEF("970gx", CPU_POWERPC_970GX
, 970GX
),
9163 POWERPC_DEF("970mp", CPU_POWERPC_970MP
, 970MP
),
9164 /* PowerPC 970MP v1.0 */
9165 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10
, 970MP
),
9166 /* PowerPC 970MP v1.1 */
9167 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11
, 970MP
),
9170 POWERPC_DEF("Cell", CPU_POWERPC_CELL
, 970),
9173 /* PowerPC Cell v1.0 */
9174 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10
, 970),
9177 /* PowerPC Cell v2.0 */
9178 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20
, 970),
9181 /* PowerPC Cell v3.0 */
9182 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30
, 970),
9185 /* PowerPC Cell v3.1 */
9186 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31
, 970),
9189 /* PowerPC Cell v3.2 */
9190 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32
, 970),
9193 /* RS64 (Apache/A35) */
9194 /* This one seems to support the whole POWER2 instruction set
9195 * and the PowerPC 64 one.
9197 /* What about A10 & A30 ? */
9198 POWERPC_DEF("RS64", CPU_POWERPC_RS64
, RS64
),
9199 POWERPC_DEF("Apache", CPU_POWERPC_RS64
, RS64
),
9200 POWERPC_DEF("A35", CPU_POWERPC_RS64
, RS64
),
9203 /* RS64-II (NorthStar/A50) */
9204 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II
, RS64
),
9205 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II
, RS64
),
9206 POWERPC_DEF("A50", CPU_POWERPC_RS64II
, RS64
),
9209 /* RS64-III (Pulsar) */
9210 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III
, RS64
),
9211 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III
, RS64
),
9214 /* RS64-IV (IceStar/IStar/SStar) */
9215 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV
, RS64
),
9216 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV
, RS64
),
9217 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV
, RS64
),
9218 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV
, RS64
),
9220 #endif /* defined (TARGET_PPC64) */
9223 /* Original POWER */
9224 POWERPC_DEF("POWER", CPU_POWERPC_POWER
, POWER
),
9225 POWERPC_DEF("RIOS", CPU_POWERPC_POWER
, POWER
),
9226 POWERPC_DEF("RSC", CPU_POWERPC_POWER
, POWER
),
9227 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER
, POWER
),
9228 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER
, POWER
),
9232 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2
, POWER
),
9233 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2
, POWER
),
9234 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2
, POWER
),
9239 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T
, PA6T
),
9241 /* Generic PowerPCs */
9242 #if defined (TARGET_PPC64)
9243 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64
, PPC64
),
9245 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32
, PPC32
),
9246 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT
, DEFAULT
),
9248 POWERPC_DEF("default", CPU_POWERPC_DEFAULT
, DEFAULT
),
9251 /*****************************************************************************/
9252 /* Generic CPU instantiation routine */
9253 static void init_ppc_proc (CPUPPCState
*env
, const ppc_def_t
*def
)
9255 #if !defined(CONFIG_USER_ONLY)
9258 env
->irq_inputs
= NULL
;
9259 /* Set all exception vectors to an invalid address */
9260 for (i
= 0; i
< POWERPC_EXCP_NB
; i
++)
9261 env
->excp_vectors
[i
] = (target_ulong
)(-1ULL);
9262 env
->hreset_excp_prefix
= 0x00000000;
9263 env
->ivor_mask
= 0x00000000;
9264 env
->ivpr_mask
= 0x00000000;
9265 /* Default MMU definitions */
9269 env
->tlb_type
= TLB_NONE
;
9271 /* Register SPR common to all PowerPC implementations */
9272 gen_spr_generic(env
);
9273 spr_register(env
, SPR_PVR
, "PVR",
9274 /* Linux permits userspace to read PVR */
9275 #if defined(CONFIG_LINUX_USER)
9281 &spr_read_generic
, SPR_NOACCESS
,
9283 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9284 if (def
->svr
!= POWERPC_SVR_NONE
) {
9285 if (def
->svr
& POWERPC_SVR_E500
) {
9286 spr_register(env
, SPR_E500_SVR
, "SVR",
9287 SPR_NOACCESS
, SPR_NOACCESS
,
9288 &spr_read_generic
, SPR_NOACCESS
,
9289 def
->svr
& ~POWERPC_SVR_E500
);
9291 spr_register(env
, SPR_SVR
, "SVR",
9292 SPR_NOACCESS
, SPR_NOACCESS
,
9293 &spr_read_generic
, SPR_NOACCESS
,
9297 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9298 (*def
->init_proc
)(env
);
9299 #if !defined(CONFIG_USER_ONLY)
9300 env
->excp_prefix
= env
->hreset_excp_prefix
;
9302 /* MSR bits & flags consistency checks */
9303 if (env
->msr_mask
& (1 << 25)) {
9304 switch (env
->flags
& (POWERPC_FLAG_SPE
| POWERPC_FLAG_VRE
)) {
9305 case POWERPC_FLAG_SPE
:
9306 case POWERPC_FLAG_VRE
:
9309 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
9310 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9313 } else if (env
->flags
& (POWERPC_FLAG_SPE
| POWERPC_FLAG_VRE
)) {
9314 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
9315 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9318 if (env
->msr_mask
& (1 << 17)) {
9319 switch (env
->flags
& (POWERPC_FLAG_TGPR
| POWERPC_FLAG_CE
)) {
9320 case POWERPC_FLAG_TGPR
:
9321 case POWERPC_FLAG_CE
:
9324 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
9325 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9328 } else if (env
->flags
& (POWERPC_FLAG_TGPR
| POWERPC_FLAG_CE
)) {
9329 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
9330 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9333 if (env
->msr_mask
& (1 << 10)) {
9334 switch (env
->flags
& (POWERPC_FLAG_SE
| POWERPC_FLAG_DWE
|
9335 POWERPC_FLAG_UBLE
)) {
9336 case POWERPC_FLAG_SE
:
9337 case POWERPC_FLAG_DWE
:
9338 case POWERPC_FLAG_UBLE
:
9341 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
9342 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9343 "POWERPC_FLAG_UBLE\n");
9346 } else if (env
->flags
& (POWERPC_FLAG_SE
| POWERPC_FLAG_DWE
|
9347 POWERPC_FLAG_UBLE
)) {
9348 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
9349 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9350 "POWERPC_FLAG_UBLE\n");
9353 if (env
->msr_mask
& (1 << 9)) {
9354 switch (env
->flags
& (POWERPC_FLAG_BE
| POWERPC_FLAG_DE
)) {
9355 case POWERPC_FLAG_BE
:
9356 case POWERPC_FLAG_DE
:
9359 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
9360 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9363 } else if (env
->flags
& (POWERPC_FLAG_BE
| POWERPC_FLAG_DE
)) {
9364 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
9365 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9368 if (env
->msr_mask
& (1 << 2)) {
9369 switch (env
->flags
& (POWERPC_FLAG_PX
| POWERPC_FLAG_PMM
)) {
9370 case POWERPC_FLAG_PX
:
9371 case POWERPC_FLAG_PMM
:
9374 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
9375 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9378 } else if (env
->flags
& (POWERPC_FLAG_PX
| POWERPC_FLAG_PMM
)) {
9379 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
9380 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9383 if ((env
->flags
& (POWERPC_FLAG_RTC_CLK
| POWERPC_FLAG_BUS_CLK
)) == 0) {
9384 fprintf(stderr
, "PowerPC flags inconsistency\n"
9385 "Should define the time-base and decrementer clock source\n");
9388 /* Allocate TLBs buffer when needed */
9389 #if !defined(CONFIG_USER_ONLY)
9390 if (env
->nb_tlb
!= 0) {
9391 int nb_tlb
= env
->nb_tlb
;
9392 if (env
->id_tlbs
!= 0)
9394 switch (env
->tlb_type
) {
9396 env
->tlb
.tlb6
= g_malloc0(nb_tlb
* sizeof(ppc6xx_tlb_t
));
9399 env
->tlb
.tlbe
= g_malloc0(nb_tlb
* sizeof(ppcemb_tlb_t
));
9402 env
->tlb
.tlbm
= g_malloc0(nb_tlb
* sizeof(ppcmas_tlb_t
));
9405 /* Pre-compute some useful values */
9406 env
->tlb_per_way
= env
->nb_tlb
/ env
->nb_ways
;
9408 if (env
->irq_inputs
== NULL
) {
9409 fprintf(stderr
, "WARNING: no internal IRQ controller registered.\n"
9410 " Attempt Qemu to crash very soon !\n");
9413 if (env
->check_pow
== NULL
) {
9414 fprintf(stderr
, "WARNING: no power management check handler "
9416 " Attempt Qemu to crash very soon !\n");
9420 #if defined(PPC_DUMP_CPU)
9421 static void dump_ppc_sprs (CPUPPCState
*env
)
9424 #if !defined(CONFIG_USER_ONLY)
9430 printf("Special purpose registers:\n");
9431 for (i
= 0; i
< 32; i
++) {
9432 for (j
= 0; j
< 32; j
++) {
9434 spr
= &env
->spr_cb
[n
];
9435 uw
= spr
->uea_write
!= NULL
&& spr
->uea_write
!= SPR_NOACCESS
;
9436 ur
= spr
->uea_read
!= NULL
&& spr
->uea_read
!= SPR_NOACCESS
;
9437 #if !defined(CONFIG_USER_ONLY)
9438 sw
= spr
->oea_write
!= NULL
&& spr
->oea_write
!= SPR_NOACCESS
;
9439 sr
= spr
->oea_read
!= NULL
&& spr
->oea_read
!= SPR_NOACCESS
;
9440 if (sw
|| sr
|| uw
|| ur
) {
9441 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9442 (i
<< 5) | j
, (i
<< 5) | j
, spr
->name
,
9443 sw
? 'w' : '-', sr
? 'r' : '-',
9444 uw
? 'w' : '-', ur
? 'r' : '-');
9448 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9449 (i
<< 5) | j
, (i
<< 5) | j
, spr
->name
,
9450 uw
? 'w' : '-', ur
? 'r' : '-');
9460 /*****************************************************************************/
9466 PPC_DIRECT
= 0, /* Opcode routine */
9467 PPC_INDIRECT
= 1, /* Indirect opcode table */
9470 static inline int is_indirect_opcode (void *handler
)
9472 return ((unsigned long)handler
& 0x03) == PPC_INDIRECT
;
9475 static inline opc_handler_t
**ind_table(void *handler
)
9477 return (opc_handler_t
**)((unsigned long)handler
& ~3);
9480 /* Instruction table creation */
9481 /* Opcodes tables creation */
9482 static void fill_new_table (opc_handler_t
**table
, int len
)
9486 for (i
= 0; i
< len
; i
++)
9487 table
[i
] = &invalid_handler
;
9490 static int create_new_table (opc_handler_t
**table
, unsigned char idx
)
9492 opc_handler_t
**tmp
;
9494 tmp
= malloc(0x20 * sizeof(opc_handler_t
));
9495 fill_new_table(tmp
, 0x20);
9496 table
[idx
] = (opc_handler_t
*)((unsigned long)tmp
| PPC_INDIRECT
);
9501 static int insert_in_table (opc_handler_t
**table
, unsigned char idx
,
9502 opc_handler_t
*handler
)
9504 if (table
[idx
] != &invalid_handler
)
9506 table
[idx
] = handler
;
9511 static int register_direct_insn (opc_handler_t
**ppc_opcodes
,
9512 unsigned char idx
, opc_handler_t
*handler
)
9514 if (insert_in_table(ppc_opcodes
, idx
, handler
) < 0) {
9515 printf("*** ERROR: opcode %02x already assigned in main "
9516 "opcode table\n", idx
);
9517 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9518 printf(" Registered handler '%s' - new handler '%s'\n",
9519 ppc_opcodes
[idx
]->oname
, handler
->oname
);
9527 static int register_ind_in_table (opc_handler_t
**table
,
9528 unsigned char idx1
, unsigned char idx2
,
9529 opc_handler_t
*handler
)
9531 if (table
[idx1
] == &invalid_handler
) {
9532 if (create_new_table(table
, idx1
) < 0) {
9533 printf("*** ERROR: unable to create indirect table "
9534 "idx=%02x\n", idx1
);
9538 if (!is_indirect_opcode(table
[idx1
])) {
9539 printf("*** ERROR: idx %02x already assigned to a direct "
9541 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9542 printf(" Registered handler '%s' - new handler '%s'\n",
9543 ind_table(table
[idx1
])[idx2
]->oname
, handler
->oname
);
9548 if (handler
!= NULL
&&
9549 insert_in_table(ind_table(table
[idx1
]), idx2
, handler
) < 0) {
9550 printf("*** ERROR: opcode %02x already assigned in "
9551 "opcode table %02x\n", idx2
, idx1
);
9552 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9553 printf(" Registered handler '%s' - new handler '%s'\n",
9554 ind_table(table
[idx1
])[idx2
]->oname
, handler
->oname
);
9562 static int register_ind_insn (opc_handler_t
**ppc_opcodes
,
9563 unsigned char idx1
, unsigned char idx2
,
9564 opc_handler_t
*handler
)
9568 ret
= register_ind_in_table(ppc_opcodes
, idx1
, idx2
, handler
);
9573 static int register_dblind_insn (opc_handler_t
**ppc_opcodes
,
9574 unsigned char idx1
, unsigned char idx2
,
9575 unsigned char idx3
, opc_handler_t
*handler
)
9577 if (register_ind_in_table(ppc_opcodes
, idx1
, idx2
, NULL
) < 0) {
9578 printf("*** ERROR: unable to join indirect table idx "
9579 "[%02x-%02x]\n", idx1
, idx2
);
9582 if (register_ind_in_table(ind_table(ppc_opcodes
[idx1
]), idx2
, idx3
,
9584 printf("*** ERROR: unable to insert opcode "
9585 "[%02x-%02x-%02x]\n", idx1
, idx2
, idx3
);
9592 static int register_insn (opc_handler_t
**ppc_opcodes
, opcode_t
*insn
)
9594 if (insn
->opc2
!= 0xFF) {
9595 if (insn
->opc3
!= 0xFF) {
9596 if (register_dblind_insn(ppc_opcodes
, insn
->opc1
, insn
->opc2
,
9597 insn
->opc3
, &insn
->handler
) < 0)
9600 if (register_ind_insn(ppc_opcodes
, insn
->opc1
,
9601 insn
->opc2
, &insn
->handler
) < 0)
9605 if (register_direct_insn(ppc_opcodes
, insn
->opc1
, &insn
->handler
) < 0)
9612 static int test_opcode_table (opc_handler_t
**table
, int len
)
9616 for (i
= 0, count
= 0; i
< len
; i
++) {
9617 /* Consistency fixup */
9618 if (table
[i
] == NULL
)
9619 table
[i
] = &invalid_handler
;
9620 if (table
[i
] != &invalid_handler
) {
9621 if (is_indirect_opcode(table
[i
])) {
9622 tmp
= test_opcode_table(ind_table(table
[i
]), 0x20);
9625 table
[i
] = &invalid_handler
;
9638 static void fix_opcode_tables (opc_handler_t
**ppc_opcodes
)
9640 if (test_opcode_table(ppc_opcodes
, 0x40) == 0)
9641 printf("*** WARNING: no opcode defined !\n");
9644 /*****************************************************************************/
9645 static int create_ppc_opcodes (CPUPPCState
*env
, const ppc_def_t
*def
)
9649 fill_new_table(env
->opcodes
, 0x40);
9650 for (opc
= opcodes
; opc
< &opcodes
[ARRAY_SIZE(opcodes
)]; opc
++) {
9651 if (((opc
->handler
.type
& def
->insns_flags
) != 0) ||
9652 ((opc
->handler
.type2
& def
->insns_flags2
) != 0)) {
9653 if (register_insn(env
->opcodes
, opc
) < 0) {
9654 printf("*** ERROR initializing PowerPC instruction "
9655 "0x%02x 0x%02x 0x%02x\n", opc
->opc1
, opc
->opc2
,
9661 fix_opcode_tables(env
->opcodes
);
9668 #if defined(PPC_DUMP_CPU)
9669 static void dump_ppc_insns (CPUPPCState
*env
)
9671 opc_handler_t
**table
, *handler
;
9673 uint8_t opc1
, opc2
, opc3
;
9675 printf("Instructions set:\n");
9676 /* opc1 is 6 bits long */
9677 for (opc1
= 0x00; opc1
< 0x40; opc1
++) {
9678 table
= env
->opcodes
;
9679 handler
= table
[opc1
];
9680 if (is_indirect_opcode(handler
)) {
9681 /* opc2 is 5 bits long */
9682 for (opc2
= 0; opc2
< 0x20; opc2
++) {
9683 table
= env
->opcodes
;
9684 handler
= env
->opcodes
[opc1
];
9685 table
= ind_table(handler
);
9686 handler
= table
[opc2
];
9687 if (is_indirect_opcode(handler
)) {
9688 table
= ind_table(handler
);
9689 /* opc3 is 5 bits long */
9690 for (opc3
= 0; opc3
< 0x20; opc3
++) {
9691 handler
= table
[opc3
];
9692 if (handler
->handler
!= &gen_invalid
) {
9693 /* Special hack to properly dump SPE insns */
9694 p
= strchr(handler
->oname
, '_');
9696 printf("INSN: %02x %02x %02x (%02d %04d) : "
9698 opc1
, opc2
, opc3
, opc1
,
9703 if ((p
- handler
->oname
) != strlen(q
) ||
9704 memcmp(handler
->oname
, q
, strlen(q
)) != 0) {
9705 /* First instruction */
9706 printf("INSN: %02x %02x %02x (%02d %04d) : "
9708 opc1
, opc2
<< 1, opc3
, opc1
,
9709 (opc3
<< 6) | (opc2
<< 1),
9710 (int)(p
- handler
->oname
),
9713 if (strcmp(p
+ 1, q
) != 0) {
9714 /* Second instruction */
9715 printf("INSN: %02x %02x %02x (%02d %04d) : "
9717 opc1
, (opc2
<< 1) | 1, opc3
, opc1
,
9718 (opc3
<< 6) | (opc2
<< 1) | 1,
9725 if (handler
->handler
!= &gen_invalid
) {
9726 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9727 opc1
, opc2
, opc1
, opc2
, handler
->oname
);
9732 if (handler
->handler
!= &gen_invalid
) {
9733 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9734 opc1
, opc1
, handler
->oname
);
9741 static int gdb_get_float_reg(CPUState
*env
, uint8_t *mem_buf
, int n
)
9744 stfq_p(mem_buf
, env
->fpr
[n
]);
9748 stl_p(mem_buf
, env
->fpscr
);
9754 static int gdb_set_float_reg(CPUState
*env
, uint8_t *mem_buf
, int n
)
9757 env
->fpr
[n
] = ldfq_p(mem_buf
);
9761 /* FPSCR not implemented */
9767 static int gdb_get_avr_reg(CPUState
*env
, uint8_t *mem_buf
, int n
)
9770 #ifdef HOST_WORDS_BIGENDIAN
9771 stq_p(mem_buf
, env
->avr
[n
].u64
[0]);
9772 stq_p(mem_buf
+8, env
->avr
[n
].u64
[1]);
9774 stq_p(mem_buf
, env
->avr
[n
].u64
[1]);
9775 stq_p(mem_buf
+8, env
->avr
[n
].u64
[0]);
9780 stl_p(mem_buf
, env
->vscr
);
9784 stl_p(mem_buf
, (uint32_t)env
->spr
[SPR_VRSAVE
]);
9790 static int gdb_set_avr_reg(CPUState
*env
, uint8_t *mem_buf
, int n
)
9793 #ifdef HOST_WORDS_BIGENDIAN
9794 env
->avr
[n
].u64
[0] = ldq_p(mem_buf
);
9795 env
->avr
[n
].u64
[1] = ldq_p(mem_buf
+8);
9797 env
->avr
[n
].u64
[1] = ldq_p(mem_buf
);
9798 env
->avr
[n
].u64
[0] = ldq_p(mem_buf
+8);
9803 env
->vscr
= ldl_p(mem_buf
);
9807 env
->spr
[SPR_VRSAVE
] = (target_ulong
)ldl_p(mem_buf
);
9813 static int gdb_get_spe_reg(CPUState
*env
, uint8_t *mem_buf
, int n
)
9816 #if defined(TARGET_PPC64)
9817 stl_p(mem_buf
, env
->gpr
[n
] >> 32);
9819 stl_p(mem_buf
, env
->gprh
[n
]);
9824 stq_p(mem_buf
, env
->spe_acc
);
9828 stl_p(mem_buf
, env
->spe_fscr
);
9834 static int gdb_set_spe_reg(CPUState
*env
, uint8_t *mem_buf
, int n
)
9837 #if defined(TARGET_PPC64)
9838 target_ulong lo
= (uint32_t)env
->gpr
[n
];
9839 target_ulong hi
= (target_ulong
)ldl_p(mem_buf
) << 32;
9840 env
->gpr
[n
] = lo
| hi
;
9842 env
->gprh
[n
] = ldl_p(mem_buf
);
9847 env
->spe_acc
= ldq_p(mem_buf
);
9851 env
->spe_fscr
= ldl_p(mem_buf
);
9857 int cpu_ppc_register_internal (CPUPPCState
*env
, const ppc_def_t
*def
)
9859 env
->msr_mask
= def
->msr_mask
;
9860 env
->mmu_model
= def
->mmu_model
;
9861 env
->excp_model
= def
->excp_model
;
9862 env
->bus_model
= def
->bus_model
;
9863 env
->insns_flags
= def
->insns_flags
;
9864 env
->insns_flags2
= def
->insns_flags2
;
9865 env
->flags
= def
->flags
;
9866 env
->bfd_mach
= def
->bfd_mach
;
9867 env
->check_pow
= def
->check_pow
;
9868 if (create_ppc_opcodes(env
, def
) < 0)
9870 init_ppc_proc(env
, def
);
9872 if (def
->insns_flags
& PPC_FLOAT
) {
9873 gdb_register_coprocessor(env
, gdb_get_float_reg
, gdb_set_float_reg
,
9874 33, "power-fpu.xml", 0);
9876 if (def
->insns_flags
& PPC_ALTIVEC
) {
9877 gdb_register_coprocessor(env
, gdb_get_avr_reg
, gdb_set_avr_reg
,
9878 34, "power-altivec.xml", 0);
9880 if (def
->insns_flags
& PPC_SPE
) {
9881 gdb_register_coprocessor(env
, gdb_get_spe_reg
, gdb_set_spe_reg
,
9882 34, "power-spe.xml", 0);
9885 #if defined(PPC_DUMP_CPU)
9887 const char *mmu_model
, *excp_model
, *bus_model
;
9888 switch (env
->mmu_model
) {
9889 case POWERPC_MMU_32B
:
9890 mmu_model
= "PowerPC 32";
9892 case POWERPC_MMU_SOFT_6xx
:
9893 mmu_model
= "PowerPC 6xx/7xx with software driven TLBs";
9895 case POWERPC_MMU_SOFT_74xx
:
9896 mmu_model
= "PowerPC 74xx with software driven TLBs";
9898 case POWERPC_MMU_SOFT_4xx
:
9899 mmu_model
= "PowerPC 4xx with software driven TLBs";
9901 case POWERPC_MMU_SOFT_4xx_Z
:
9902 mmu_model
= "PowerPC 4xx with software driven TLBs "
9903 "and zones protections";
9905 case POWERPC_MMU_REAL
:
9906 mmu_model
= "PowerPC real mode only";
9908 case POWERPC_MMU_MPC8xx
:
9909 mmu_model
= "PowerPC MPC8xx";
9911 case POWERPC_MMU_BOOKE
:
9912 mmu_model
= "PowerPC BookE";
9914 case POWERPC_MMU_BOOKE206
:
9915 mmu_model
= "PowerPC BookE 2.06";
9917 case POWERPC_MMU_601
:
9918 mmu_model
= "PowerPC 601";
9920 #if defined (TARGET_PPC64)
9921 case POWERPC_MMU_64B
:
9922 mmu_model
= "PowerPC 64";
9924 case POWERPC_MMU_620
:
9925 mmu_model
= "PowerPC 620";
9929 mmu_model
= "Unknown or invalid";
9932 switch (env
->excp_model
) {
9933 case POWERPC_EXCP_STD
:
9934 excp_model
= "PowerPC";
9936 case POWERPC_EXCP_40x
:
9937 excp_model
= "PowerPC 40x";
9939 case POWERPC_EXCP_601
:
9940 excp_model
= "PowerPC 601";
9942 case POWERPC_EXCP_602
:
9943 excp_model
= "PowerPC 602";
9945 case POWERPC_EXCP_603
:
9946 excp_model
= "PowerPC 603";
9948 case POWERPC_EXCP_603E
:
9949 excp_model
= "PowerPC 603e";
9951 case POWERPC_EXCP_604
:
9952 excp_model
= "PowerPC 604";
9954 case POWERPC_EXCP_7x0
:
9955 excp_model
= "PowerPC 740/750";
9957 case POWERPC_EXCP_7x5
:
9958 excp_model
= "PowerPC 745/755";
9960 case POWERPC_EXCP_74xx
:
9961 excp_model
= "PowerPC 74xx";
9963 case POWERPC_EXCP_BOOKE
:
9964 excp_model
= "PowerPC BookE";
9966 #if defined (TARGET_PPC64)
9967 case POWERPC_EXCP_970
:
9968 excp_model
= "PowerPC 970";
9972 excp_model
= "Unknown or invalid";
9975 switch (env
->bus_model
) {
9976 case PPC_FLAGS_INPUT_6xx
:
9977 bus_model
= "PowerPC 6xx";
9979 case PPC_FLAGS_INPUT_BookE
:
9980 bus_model
= "PowerPC BookE";
9982 case PPC_FLAGS_INPUT_405
:
9983 bus_model
= "PowerPC 405";
9985 case PPC_FLAGS_INPUT_401
:
9986 bus_model
= "PowerPC 401/403";
9988 case PPC_FLAGS_INPUT_RCPU
:
9989 bus_model
= "RCPU / MPC8xx";
9991 #if defined (TARGET_PPC64)
9992 case PPC_FLAGS_INPUT_970
:
9993 bus_model
= "PowerPC 970";
9997 bus_model
= "Unknown or invalid";
10000 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64
"\n"
10001 " MMU model : %s\n",
10002 def
->name
, def
->pvr
, def
->msr_mask
, mmu_model
);
10003 #if !defined(CONFIG_USER_ONLY)
10004 if (env
->tlb
!= NULL
) {
10005 printf(" %d %s TLB in %d ways\n",
10006 env
->nb_tlb
, env
->id_tlbs
? "splitted" : "merged",
10010 printf(" Exceptions model : %s\n"
10011 " Bus model : %s\n",
10012 excp_model
, bus_model
);
10013 printf(" MSR features :\n");
10014 if (env
->flags
& POWERPC_FLAG_SPE
)
10015 printf(" signal processing engine enable"
10017 else if (env
->flags
& POWERPC_FLAG_VRE
)
10018 printf(" vector processor enable\n");
10019 if (env
->flags
& POWERPC_FLAG_TGPR
)
10020 printf(" temporary GPRs\n");
10021 else if (env
->flags
& POWERPC_FLAG_CE
)
10022 printf(" critical input enable\n");
10023 if (env
->flags
& POWERPC_FLAG_SE
)
10024 printf(" single-step trace mode\n");
10025 else if (env
->flags
& POWERPC_FLAG_DWE
)
10026 printf(" debug wait enable\n");
10027 else if (env
->flags
& POWERPC_FLAG_UBLE
)
10028 printf(" user BTB lock enable\n");
10029 if (env
->flags
& POWERPC_FLAG_BE
)
10030 printf(" branch-step trace mode\n");
10031 else if (env
->flags
& POWERPC_FLAG_DE
)
10032 printf(" debug interrupt enable\n");
10033 if (env
->flags
& POWERPC_FLAG_PX
)
10034 printf(" inclusive protection\n");
10035 else if (env
->flags
& POWERPC_FLAG_PMM
)
10036 printf(" performance monitor mark\n");
10037 if (env
->flags
== POWERPC_FLAG_NONE
)
10039 printf(" Time-base/decrementer clock source: %s\n",
10040 env
->flags
& POWERPC_FLAG_RTC_CLK
? "RTC clock" : "bus clock");
10042 dump_ppc_insns(env
);
10043 dump_ppc_sprs(env
);
10050 const ppc_def_t
*ppc_find_by_pvr(uint32_t pvr
)
10054 for (i
= 0; i
< ARRAY_SIZE(ppc_defs
); i
++) {
10055 /* If we have an exact match, we're done */
10056 if (pvr
== ppc_defs
[i
].pvr
) {
10057 return &ppc_defs
[i
];
10066 const ppc_def_t
*cpu_ppc_find_by_name (const char *name
)
10068 const ppc_def_t
*ret
;
10072 if (kvm_enabled() && (strcasecmp(name
, "host") == 0)) {
10073 return kvmppc_host_cpu_def();
10076 /* Check if the given name is a PVR */
10077 len
= strlen(name
);
10078 if (len
== 10 && name
[0] == '0' && name
[1] == 'x') {
10081 } else if (len
== 8) {
10084 for (i
= 0; i
< 8; i
++) {
10085 if (!qemu_isxdigit(*p
++))
10089 return ppc_find_by_pvr(strtoul(name
, NULL
, 16));
10092 max
= ARRAY_SIZE(ppc_defs
);
10093 for (i
= 0; i
< max
; i
++) {
10094 if (strcasecmp(name
, ppc_defs
[i
].name
) == 0) {
10095 ret
= &ppc_defs
[i
];
10103 void ppc_cpu_list (FILE *f
, fprintf_function cpu_fprintf
)
10107 max
= ARRAY_SIZE(ppc_defs
);
10108 for (i
= 0; i
< max
; i
++) {
10109 (*cpu_fprintf
)(f
, "PowerPC %-16s PVR %08x\n",
10110 ppc_defs
[i
].name
, ppc_defs
[i
].pvr
);