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Gdbstub: handle read of fpscr
[qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 /* A lot of PowerPC definition have been included here.
21 * Most of them are not usable for now but have been kept
22 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
23 */
24
25 #include "dis-asm.h"
26 #include "gdbstub.h"
27
28 //#define PPC_DUMP_CPU
29 //#define PPC_DEBUG_SPR
30 //#define PPC_DUMP_SPR_ACCESSES
31 #if defined(CONFIG_USER_ONLY)
32 #define TODO_USER_ONLY 1
33 #endif
34
35 struct ppc_def_t {
36 const char *name;
37 uint32_t pvr;
38 uint32_t svr;
39 uint64_t insns_flags;
40 uint64_t insns_flags2;
41 uint64_t msr_mask;
42 powerpc_mmu_t mmu_model;
43 powerpc_excp_t excp_model;
44 powerpc_input_t bus_model;
45 uint32_t flags;
46 int bfd_mach;
47 void (*init_proc)(CPUPPCState *env);
48 int (*check_pow)(CPUPPCState *env);
49 };
50
51 /* For user-mode emulation, we don't emulate any IRQ controller */
52 #if defined(CONFIG_USER_ONLY)
53 #define PPC_IRQ_INIT_FN(name) \
54 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
55 { \
56 }
57 #else
58 #define PPC_IRQ_INIT_FN(name) \
59 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
60 #endif
61
62 PPC_IRQ_INIT_FN(40x);
63 PPC_IRQ_INIT_FN(6xx);
64 PPC_IRQ_INIT_FN(970);
65 PPC_IRQ_INIT_FN(POWER7);
66 PPC_IRQ_INIT_FN(e500);
67
68 /* Generic callbacks:
69 * do nothing but store/retrieve spr value
70 */
71 static void spr_read_generic (void *opaque, int gprn, int sprn)
72 {
73 gen_load_spr(cpu_gpr[gprn], sprn);
74 #ifdef PPC_DUMP_SPR_ACCESSES
75 {
76 TCGv_i32 t0 = tcg_const_i32(sprn);
77 gen_helper_load_dump_spr(t0);
78 tcg_temp_free_i32(t0);
79 }
80 #endif
81 }
82
83 static void spr_write_generic (void *opaque, int sprn, int gprn)
84 {
85 gen_store_spr(sprn, cpu_gpr[gprn]);
86 #ifdef PPC_DUMP_SPR_ACCESSES
87 {
88 TCGv_i32 t0 = tcg_const_i32(sprn);
89 gen_helper_store_dump_spr(t0);
90 tcg_temp_free_i32(t0);
91 }
92 #endif
93 }
94
95 #if !defined(CONFIG_USER_ONLY)
96 static void spr_write_clear (void *opaque, int sprn, int gprn)
97 {
98 TCGv t0 = tcg_temp_new();
99 TCGv t1 = tcg_temp_new();
100 gen_load_spr(t0, sprn);
101 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
102 tcg_gen_and_tl(t0, t0, t1);
103 gen_store_spr(sprn, t0);
104 tcg_temp_free(t0);
105 tcg_temp_free(t1);
106 }
107 #endif
108
109 /* SPR common to all PowerPC */
110 /* XER */
111 static void spr_read_xer (void *opaque, int gprn, int sprn)
112 {
113 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
114 }
115
116 static void spr_write_xer (void *opaque, int sprn, int gprn)
117 {
118 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
119 }
120
121 /* LR */
122 static void spr_read_lr (void *opaque, int gprn, int sprn)
123 {
124 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
125 }
126
127 static void spr_write_lr (void *opaque, int sprn, int gprn)
128 {
129 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
130 }
131
132 /* CFAR */
133 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
134 static void spr_read_cfar (void *opaque, int gprn, int sprn)
135 {
136 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
137 }
138
139 static void spr_write_cfar (void *opaque, int sprn, int gprn)
140 {
141 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
142 }
143 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
144
145 /* CTR */
146 static void spr_read_ctr (void *opaque, int gprn, int sprn)
147 {
148 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
149 }
150
151 static void spr_write_ctr (void *opaque, int sprn, int gprn)
152 {
153 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
154 }
155
156 /* User read access to SPR */
157 /* USPRx */
158 /* UMMCRx */
159 /* UPMCx */
160 /* USIA */
161 /* UDECR */
162 static void spr_read_ureg (void *opaque, int gprn, int sprn)
163 {
164 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
165 }
166
167 /* SPR common to all non-embedded PowerPC */
168 /* DECR */
169 #if !defined(CONFIG_USER_ONLY)
170 static void spr_read_decr (void *opaque, int gprn, int sprn)
171 {
172 if (use_icount) {
173 gen_io_start();
174 }
175 gen_helper_load_decr(cpu_gpr[gprn]);
176 if (use_icount) {
177 gen_io_end();
178 gen_stop_exception(opaque);
179 }
180 }
181
182 static void spr_write_decr (void *opaque, int sprn, int gprn)
183 {
184 if (use_icount) {
185 gen_io_start();
186 }
187 gen_helper_store_decr(cpu_gpr[gprn]);
188 if (use_icount) {
189 gen_io_end();
190 gen_stop_exception(opaque);
191 }
192 }
193 #endif
194
195 /* SPR common to all non-embedded PowerPC, except 601 */
196 /* Time base */
197 static void spr_read_tbl (void *opaque, int gprn, int sprn)
198 {
199 if (use_icount) {
200 gen_io_start();
201 }
202 gen_helper_load_tbl(cpu_gpr[gprn]);
203 if (use_icount) {
204 gen_io_end();
205 gen_stop_exception(opaque);
206 }
207 }
208
209 static void spr_read_tbu (void *opaque, int gprn, int sprn)
210 {
211 if (use_icount) {
212 gen_io_start();
213 }
214 gen_helper_load_tbu(cpu_gpr[gprn]);
215 if (use_icount) {
216 gen_io_end();
217 gen_stop_exception(opaque);
218 }
219 }
220
221 __attribute__ (( unused ))
222 static void spr_read_atbl (void *opaque, int gprn, int sprn)
223 {
224 gen_helper_load_atbl(cpu_gpr[gprn]);
225 }
226
227 __attribute__ (( unused ))
228 static void spr_read_atbu (void *opaque, int gprn, int sprn)
229 {
230 gen_helper_load_atbu(cpu_gpr[gprn]);
231 }
232
233 #if !defined(CONFIG_USER_ONLY)
234 static void spr_write_tbl (void *opaque, int sprn, int gprn)
235 {
236 if (use_icount) {
237 gen_io_start();
238 }
239 gen_helper_store_tbl(cpu_gpr[gprn]);
240 if (use_icount) {
241 gen_io_end();
242 gen_stop_exception(opaque);
243 }
244 }
245
246 static void spr_write_tbu (void *opaque, int sprn, int gprn)
247 {
248 if (use_icount) {
249 gen_io_start();
250 }
251 gen_helper_store_tbu(cpu_gpr[gprn]);
252 if (use_icount) {
253 gen_io_end();
254 gen_stop_exception(opaque);
255 }
256 }
257
258 __attribute__ (( unused ))
259 static void spr_write_atbl (void *opaque, int sprn, int gprn)
260 {
261 gen_helper_store_atbl(cpu_gpr[gprn]);
262 }
263
264 __attribute__ (( unused ))
265 static void spr_write_atbu (void *opaque, int sprn, int gprn)
266 {
267 gen_helper_store_atbu(cpu_gpr[gprn]);
268 }
269
270 #if defined(TARGET_PPC64)
271 __attribute__ (( unused ))
272 static void spr_read_purr (void *opaque, int gprn, int sprn)
273 {
274 gen_helper_load_purr(cpu_gpr[gprn]);
275 }
276 #endif
277 #endif
278
279 #if !defined(CONFIG_USER_ONLY)
280 /* IBAT0U...IBAT0U */
281 /* IBAT0L...IBAT7L */
282 static void spr_read_ibat (void *opaque, int gprn, int sprn)
283 {
284 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
285 }
286
287 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
288 {
289 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
290 }
291
292 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
293 {
294 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
295 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
296 tcg_temp_free_i32(t0);
297 }
298
299 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
300 {
301 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
302 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
303 tcg_temp_free_i32(t0);
304 }
305
306 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
307 {
308 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
309 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
310 tcg_temp_free_i32(t0);
311 }
312
313 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
314 {
315 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
316 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
317 tcg_temp_free_i32(t0);
318 }
319
320 /* DBAT0U...DBAT7U */
321 /* DBAT0L...DBAT7L */
322 static void spr_read_dbat (void *opaque, int gprn, int sprn)
323 {
324 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
325 }
326
327 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
328 {
329 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
330 }
331
332 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
333 {
334 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
335 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
336 tcg_temp_free_i32(t0);
337 }
338
339 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
340 {
341 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
342 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
343 tcg_temp_free_i32(t0);
344 }
345
346 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
347 {
348 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
349 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
350 tcg_temp_free_i32(t0);
351 }
352
353 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
354 {
355 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
356 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
357 tcg_temp_free_i32(t0);
358 }
359
360 /* SDR1 */
361 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
362 {
363 gen_helper_store_sdr1(cpu_gpr[gprn]);
364 }
365
366 /* 64 bits PowerPC specific SPRs */
367 /* ASR */
368 #if defined(TARGET_PPC64)
369 static void spr_read_hior (void *opaque, int gprn, int sprn)
370 {
371 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
372 }
373
374 static void spr_write_hior (void *opaque, int sprn, int gprn)
375 {
376 TCGv t0 = tcg_temp_new();
377 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
378 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
379 tcg_temp_free(t0);
380 }
381
382 static void spr_read_asr (void *opaque, int gprn, int sprn)
383 {
384 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
385 }
386
387 static void spr_write_asr (void *opaque, int sprn, int gprn)
388 {
389 gen_helper_store_asr(cpu_gpr[gprn]);
390 }
391 #endif
392 #endif
393
394 /* PowerPC 601 specific registers */
395 /* RTC */
396 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
397 {
398 gen_helper_load_601_rtcl(cpu_gpr[gprn]);
399 }
400
401 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
402 {
403 gen_helper_load_601_rtcu(cpu_gpr[gprn]);
404 }
405
406 #if !defined(CONFIG_USER_ONLY)
407 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
408 {
409 gen_helper_store_601_rtcu(cpu_gpr[gprn]);
410 }
411
412 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
413 {
414 gen_helper_store_601_rtcl(cpu_gpr[gprn]);
415 }
416
417 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
418 {
419 DisasContext *ctx = opaque;
420
421 gen_helper_store_hid0_601(cpu_gpr[gprn]);
422 /* Must stop the translation as endianness may have changed */
423 gen_stop_exception(ctx);
424 }
425 #endif
426
427 /* Unified bats */
428 #if !defined(CONFIG_USER_ONLY)
429 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
430 {
431 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
432 }
433
434 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
435 {
436 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
437 gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
438 tcg_temp_free_i32(t0);
439 }
440
441 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
442 {
443 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
444 gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
445 tcg_temp_free_i32(t0);
446 }
447 #endif
448
449 /* PowerPC 40x specific registers */
450 #if !defined(CONFIG_USER_ONLY)
451 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
452 {
453 gen_helper_load_40x_pit(cpu_gpr[gprn]);
454 }
455
456 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
457 {
458 gen_helper_store_40x_pit(cpu_gpr[gprn]);
459 }
460
461 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
462 {
463 DisasContext *ctx = opaque;
464
465 gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
466 /* We must stop translation as we may have rebooted */
467 gen_stop_exception(ctx);
468 }
469
470 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
471 {
472 gen_helper_store_40x_sler(cpu_gpr[gprn]);
473 }
474
475 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
476 {
477 gen_helper_store_booke_tcr(cpu_gpr[gprn]);
478 }
479
480 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
481 {
482 gen_helper_store_booke_tsr(cpu_gpr[gprn]);
483 }
484 #endif
485
486 /* PowerPC 403 specific registers */
487 /* PBL1 / PBU1 / PBL2 / PBU2 */
488 #if !defined(CONFIG_USER_ONLY)
489 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
490 {
491 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
492 }
493
494 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
495 {
496 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
497 gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
498 tcg_temp_free_i32(t0);
499 }
500
501 static void spr_write_pir (void *opaque, int sprn, int gprn)
502 {
503 TCGv t0 = tcg_temp_new();
504 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
505 gen_store_spr(SPR_PIR, t0);
506 tcg_temp_free(t0);
507 }
508 #endif
509
510 /* SPE specific registers */
511 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
512 {
513 TCGv_i32 t0 = tcg_temp_new_i32();
514 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
515 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
516 tcg_temp_free_i32(t0);
517 }
518
519 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
520 {
521 TCGv_i32 t0 = tcg_temp_new_i32();
522 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
523 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
524 tcg_temp_free_i32(t0);
525 }
526
527 #if !defined(CONFIG_USER_ONLY)
528 /* Callback used to write the exception vector base */
529 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
530 {
531 TCGv t0 = tcg_temp_new();
532 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
533 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
534 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
535 gen_store_spr(sprn, t0);
536 tcg_temp_free(t0);
537 }
538
539 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
540 {
541 DisasContext *ctx = opaque;
542
543 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
544 TCGv t0 = tcg_temp_new();
545 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
546 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
547 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
548 gen_store_spr(sprn, t0);
549 tcg_temp_free(t0);
550 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
551 TCGv t0 = tcg_temp_new();
552 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
553 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
554 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
555 gen_store_spr(sprn, t0);
556 tcg_temp_free(t0);
557 } else {
558 printf("Trying to write an unknown exception vector %d %03x\n",
559 sprn, sprn);
560 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
561 }
562 }
563 #endif
564
565 static inline void vscr_init (CPUPPCState *env, uint32_t val)
566 {
567 env->vscr = val;
568 /* Altivec always uses round-to-nearest */
569 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
570 set_flush_to_zero(vscr_nj, &env->vec_status);
571 }
572
573 #if defined(CONFIG_USER_ONLY)
574 #define spr_register(env, num, name, uea_read, uea_write, \
575 oea_read, oea_write, initial_value) \
576 do { \
577 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
578 } while (0)
579 static inline void _spr_register (CPUPPCState *env, int num,
580 const char *name,
581 void (*uea_read)(void *opaque, int gprn, int sprn),
582 void (*uea_write)(void *opaque, int sprn, int gprn),
583 target_ulong initial_value)
584 #else
585 static inline void spr_register (CPUPPCState *env, int num,
586 const char *name,
587 void (*uea_read)(void *opaque, int gprn, int sprn),
588 void (*uea_write)(void *opaque, int sprn, int gprn),
589 void (*oea_read)(void *opaque, int gprn, int sprn),
590 void (*oea_write)(void *opaque, int sprn, int gprn),
591 target_ulong initial_value)
592 #endif
593 {
594 ppc_spr_t *spr;
595
596 spr = &env->spr_cb[num];
597 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
598 #if !defined(CONFIG_USER_ONLY)
599 spr->oea_read != NULL || spr->oea_write != NULL ||
600 #endif
601 spr->uea_read != NULL || spr->uea_write != NULL) {
602 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
603 exit(1);
604 }
605 #if defined(PPC_DEBUG_SPR)
606 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
607 name, initial_value);
608 #endif
609 spr->name = name;
610 spr->uea_read = uea_read;
611 spr->uea_write = uea_write;
612 #if !defined(CONFIG_USER_ONLY)
613 spr->oea_read = oea_read;
614 spr->oea_write = oea_write;
615 #endif
616 env->spr[num] = initial_value;
617 }
618
619 /* Generic PowerPC SPRs */
620 static void gen_spr_generic (CPUPPCState *env)
621 {
622 /* Integer processing */
623 spr_register(env, SPR_XER, "XER",
624 &spr_read_xer, &spr_write_xer,
625 &spr_read_xer, &spr_write_xer,
626 0x00000000);
627 /* Branch contol */
628 spr_register(env, SPR_LR, "LR",
629 &spr_read_lr, &spr_write_lr,
630 &spr_read_lr, &spr_write_lr,
631 0x00000000);
632 spr_register(env, SPR_CTR, "CTR",
633 &spr_read_ctr, &spr_write_ctr,
634 &spr_read_ctr, &spr_write_ctr,
635 0x00000000);
636 /* Interrupt processing */
637 spr_register(env, SPR_SRR0, "SRR0",
638 SPR_NOACCESS, SPR_NOACCESS,
639 &spr_read_generic, &spr_write_generic,
640 0x00000000);
641 spr_register(env, SPR_SRR1, "SRR1",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_generic, &spr_write_generic,
644 0x00000000);
645 /* Processor control */
646 spr_register(env, SPR_SPRG0, "SPRG0",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_generic, &spr_write_generic,
649 0x00000000);
650 spr_register(env, SPR_SPRG1, "SPRG1",
651 SPR_NOACCESS, SPR_NOACCESS,
652 &spr_read_generic, &spr_write_generic,
653 0x00000000);
654 spr_register(env, SPR_SPRG2, "SPRG2",
655 SPR_NOACCESS, SPR_NOACCESS,
656 &spr_read_generic, &spr_write_generic,
657 0x00000000);
658 spr_register(env, SPR_SPRG3, "SPRG3",
659 SPR_NOACCESS, SPR_NOACCESS,
660 &spr_read_generic, &spr_write_generic,
661 0x00000000);
662 }
663
664 /* SPR common to all non-embedded PowerPC, including 601 */
665 static void gen_spr_ne_601 (CPUPPCState *env)
666 {
667 /* Exception processing */
668 spr_register(env, SPR_DSISR, "DSISR",
669 SPR_NOACCESS, SPR_NOACCESS,
670 &spr_read_generic, &spr_write_generic,
671 0x00000000);
672 spr_register(env, SPR_DAR, "DAR",
673 SPR_NOACCESS, SPR_NOACCESS,
674 &spr_read_generic, &spr_write_generic,
675 0x00000000);
676 /* Timer */
677 spr_register(env, SPR_DECR, "DECR",
678 SPR_NOACCESS, SPR_NOACCESS,
679 &spr_read_decr, &spr_write_decr,
680 0x00000000);
681 /* Memory management */
682 spr_register(env, SPR_SDR1, "SDR1",
683 SPR_NOACCESS, SPR_NOACCESS,
684 &spr_read_generic, &spr_write_sdr1,
685 0x00000000);
686 }
687
688 /* BATs 0-3 */
689 static void gen_low_BATs (CPUPPCState *env)
690 {
691 #if !defined(CONFIG_USER_ONLY)
692 spr_register(env, SPR_IBAT0U, "IBAT0U",
693 SPR_NOACCESS, SPR_NOACCESS,
694 &spr_read_ibat, &spr_write_ibatu,
695 0x00000000);
696 spr_register(env, SPR_IBAT0L, "IBAT0L",
697 SPR_NOACCESS, SPR_NOACCESS,
698 &spr_read_ibat, &spr_write_ibatl,
699 0x00000000);
700 spr_register(env, SPR_IBAT1U, "IBAT1U",
701 SPR_NOACCESS, SPR_NOACCESS,
702 &spr_read_ibat, &spr_write_ibatu,
703 0x00000000);
704 spr_register(env, SPR_IBAT1L, "IBAT1L",
705 SPR_NOACCESS, SPR_NOACCESS,
706 &spr_read_ibat, &spr_write_ibatl,
707 0x00000000);
708 spr_register(env, SPR_IBAT2U, "IBAT2U",
709 SPR_NOACCESS, SPR_NOACCESS,
710 &spr_read_ibat, &spr_write_ibatu,
711 0x00000000);
712 spr_register(env, SPR_IBAT2L, "IBAT2L",
713 SPR_NOACCESS, SPR_NOACCESS,
714 &spr_read_ibat, &spr_write_ibatl,
715 0x00000000);
716 spr_register(env, SPR_IBAT3U, "IBAT3U",
717 SPR_NOACCESS, SPR_NOACCESS,
718 &spr_read_ibat, &spr_write_ibatu,
719 0x00000000);
720 spr_register(env, SPR_IBAT3L, "IBAT3L",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_ibat, &spr_write_ibatl,
723 0x00000000);
724 spr_register(env, SPR_DBAT0U, "DBAT0U",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_dbat, &spr_write_dbatu,
727 0x00000000);
728 spr_register(env, SPR_DBAT0L, "DBAT0L",
729 SPR_NOACCESS, SPR_NOACCESS,
730 &spr_read_dbat, &spr_write_dbatl,
731 0x00000000);
732 spr_register(env, SPR_DBAT1U, "DBAT1U",
733 SPR_NOACCESS, SPR_NOACCESS,
734 &spr_read_dbat, &spr_write_dbatu,
735 0x00000000);
736 spr_register(env, SPR_DBAT1L, "DBAT1L",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_dbat, &spr_write_dbatl,
739 0x00000000);
740 spr_register(env, SPR_DBAT2U, "DBAT2U",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_dbat, &spr_write_dbatu,
743 0x00000000);
744 spr_register(env, SPR_DBAT2L, "DBAT2L",
745 SPR_NOACCESS, SPR_NOACCESS,
746 &spr_read_dbat, &spr_write_dbatl,
747 0x00000000);
748 spr_register(env, SPR_DBAT3U, "DBAT3U",
749 SPR_NOACCESS, SPR_NOACCESS,
750 &spr_read_dbat, &spr_write_dbatu,
751 0x00000000);
752 spr_register(env, SPR_DBAT3L, "DBAT3L",
753 SPR_NOACCESS, SPR_NOACCESS,
754 &spr_read_dbat, &spr_write_dbatl,
755 0x00000000);
756 env->nb_BATs += 4;
757 #endif
758 }
759
760 /* BATs 4-7 */
761 static void gen_high_BATs (CPUPPCState *env)
762 {
763 #if !defined(CONFIG_USER_ONLY)
764 spr_register(env, SPR_IBAT4U, "IBAT4U",
765 SPR_NOACCESS, SPR_NOACCESS,
766 &spr_read_ibat_h, &spr_write_ibatu_h,
767 0x00000000);
768 spr_register(env, SPR_IBAT4L, "IBAT4L",
769 SPR_NOACCESS, SPR_NOACCESS,
770 &spr_read_ibat_h, &spr_write_ibatl_h,
771 0x00000000);
772 spr_register(env, SPR_IBAT5U, "IBAT5U",
773 SPR_NOACCESS, SPR_NOACCESS,
774 &spr_read_ibat_h, &spr_write_ibatu_h,
775 0x00000000);
776 spr_register(env, SPR_IBAT5L, "IBAT5L",
777 SPR_NOACCESS, SPR_NOACCESS,
778 &spr_read_ibat_h, &spr_write_ibatl_h,
779 0x00000000);
780 spr_register(env, SPR_IBAT6U, "IBAT6U",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_ibat_h, &spr_write_ibatu_h,
783 0x00000000);
784 spr_register(env, SPR_IBAT6L, "IBAT6L",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_ibat_h, &spr_write_ibatl_h,
787 0x00000000);
788 spr_register(env, SPR_IBAT7U, "IBAT7U",
789 SPR_NOACCESS, SPR_NOACCESS,
790 &spr_read_ibat_h, &spr_write_ibatu_h,
791 0x00000000);
792 spr_register(env, SPR_IBAT7L, "IBAT7L",
793 SPR_NOACCESS, SPR_NOACCESS,
794 &spr_read_ibat_h, &spr_write_ibatl_h,
795 0x00000000);
796 spr_register(env, SPR_DBAT4U, "DBAT4U",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_dbat_h, &spr_write_dbatu_h,
799 0x00000000);
800 spr_register(env, SPR_DBAT4L, "DBAT4L",
801 SPR_NOACCESS, SPR_NOACCESS,
802 &spr_read_dbat_h, &spr_write_dbatl_h,
803 0x00000000);
804 spr_register(env, SPR_DBAT5U, "DBAT5U",
805 SPR_NOACCESS, SPR_NOACCESS,
806 &spr_read_dbat_h, &spr_write_dbatu_h,
807 0x00000000);
808 spr_register(env, SPR_DBAT5L, "DBAT5L",
809 SPR_NOACCESS, SPR_NOACCESS,
810 &spr_read_dbat_h, &spr_write_dbatl_h,
811 0x00000000);
812 spr_register(env, SPR_DBAT6U, "DBAT6U",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_dbat_h, &spr_write_dbatu_h,
815 0x00000000);
816 spr_register(env, SPR_DBAT6L, "DBAT6L",
817 SPR_NOACCESS, SPR_NOACCESS,
818 &spr_read_dbat_h, &spr_write_dbatl_h,
819 0x00000000);
820 spr_register(env, SPR_DBAT7U, "DBAT7U",
821 SPR_NOACCESS, SPR_NOACCESS,
822 &spr_read_dbat_h, &spr_write_dbatu_h,
823 0x00000000);
824 spr_register(env, SPR_DBAT7L, "DBAT7L",
825 SPR_NOACCESS, SPR_NOACCESS,
826 &spr_read_dbat_h, &spr_write_dbatl_h,
827 0x00000000);
828 env->nb_BATs += 4;
829 #endif
830 }
831
832 /* Generic PowerPC time base */
833 static void gen_tbl (CPUPPCState *env)
834 {
835 spr_register(env, SPR_VTBL, "TBL",
836 &spr_read_tbl, SPR_NOACCESS,
837 &spr_read_tbl, SPR_NOACCESS,
838 0x00000000);
839 spr_register(env, SPR_TBL, "TBL",
840 &spr_read_tbl, SPR_NOACCESS,
841 &spr_read_tbl, &spr_write_tbl,
842 0x00000000);
843 spr_register(env, SPR_VTBU, "TBU",
844 &spr_read_tbu, SPR_NOACCESS,
845 &spr_read_tbu, SPR_NOACCESS,
846 0x00000000);
847 spr_register(env, SPR_TBU, "TBU",
848 &spr_read_tbu, SPR_NOACCESS,
849 &spr_read_tbu, &spr_write_tbu,
850 0x00000000);
851 }
852
853 /* Softare table search registers */
854 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
855 {
856 #if !defined(CONFIG_USER_ONLY)
857 env->nb_tlb = nb_tlbs;
858 env->nb_ways = nb_ways;
859 env->id_tlbs = 1;
860 env->tlb_type = TLB_6XX;
861 spr_register(env, SPR_DMISS, "DMISS",
862 SPR_NOACCESS, SPR_NOACCESS,
863 &spr_read_generic, SPR_NOACCESS,
864 0x00000000);
865 spr_register(env, SPR_DCMP, "DCMP",
866 SPR_NOACCESS, SPR_NOACCESS,
867 &spr_read_generic, SPR_NOACCESS,
868 0x00000000);
869 spr_register(env, SPR_HASH1, "HASH1",
870 SPR_NOACCESS, SPR_NOACCESS,
871 &spr_read_generic, SPR_NOACCESS,
872 0x00000000);
873 spr_register(env, SPR_HASH2, "HASH2",
874 SPR_NOACCESS, SPR_NOACCESS,
875 &spr_read_generic, SPR_NOACCESS,
876 0x00000000);
877 spr_register(env, SPR_IMISS, "IMISS",
878 SPR_NOACCESS, SPR_NOACCESS,
879 &spr_read_generic, SPR_NOACCESS,
880 0x00000000);
881 spr_register(env, SPR_ICMP, "ICMP",
882 SPR_NOACCESS, SPR_NOACCESS,
883 &spr_read_generic, SPR_NOACCESS,
884 0x00000000);
885 spr_register(env, SPR_RPA, "RPA",
886 SPR_NOACCESS, SPR_NOACCESS,
887 &spr_read_generic, &spr_write_generic,
888 0x00000000);
889 #endif
890 }
891
892 /* SPR common to MPC755 and G2 */
893 static void gen_spr_G2_755 (CPUPPCState *env)
894 {
895 /* SGPRs */
896 spr_register(env, SPR_SPRG4, "SPRG4",
897 SPR_NOACCESS, SPR_NOACCESS,
898 &spr_read_generic, &spr_write_generic,
899 0x00000000);
900 spr_register(env, SPR_SPRG5, "SPRG5",
901 SPR_NOACCESS, SPR_NOACCESS,
902 &spr_read_generic, &spr_write_generic,
903 0x00000000);
904 spr_register(env, SPR_SPRG6, "SPRG6",
905 SPR_NOACCESS, SPR_NOACCESS,
906 &spr_read_generic, &spr_write_generic,
907 0x00000000);
908 spr_register(env, SPR_SPRG7, "SPRG7",
909 SPR_NOACCESS, SPR_NOACCESS,
910 &spr_read_generic, &spr_write_generic,
911 0x00000000);
912 }
913
914 /* SPR common to all 7xx PowerPC implementations */
915 static void gen_spr_7xx (CPUPPCState *env)
916 {
917 /* Breakpoints */
918 /* XXX : not implemented */
919 spr_register(env, SPR_DABR, "DABR",
920 SPR_NOACCESS, SPR_NOACCESS,
921 &spr_read_generic, &spr_write_generic,
922 0x00000000);
923 /* XXX : not implemented */
924 spr_register(env, SPR_IABR, "IABR",
925 SPR_NOACCESS, SPR_NOACCESS,
926 &spr_read_generic, &spr_write_generic,
927 0x00000000);
928 /* Cache management */
929 /* XXX : not implemented */
930 spr_register(env, SPR_ICTC, "ICTC",
931 SPR_NOACCESS, SPR_NOACCESS,
932 &spr_read_generic, &spr_write_generic,
933 0x00000000);
934 /* Performance monitors */
935 /* XXX : not implemented */
936 spr_register(env, SPR_MMCR0, "MMCR0",
937 SPR_NOACCESS, SPR_NOACCESS,
938 &spr_read_generic, &spr_write_generic,
939 0x00000000);
940 /* XXX : not implemented */
941 spr_register(env, SPR_MMCR1, "MMCR1",
942 SPR_NOACCESS, SPR_NOACCESS,
943 &spr_read_generic, &spr_write_generic,
944 0x00000000);
945 /* XXX : not implemented */
946 spr_register(env, SPR_PMC1, "PMC1",
947 SPR_NOACCESS, SPR_NOACCESS,
948 &spr_read_generic, &spr_write_generic,
949 0x00000000);
950 /* XXX : not implemented */
951 spr_register(env, SPR_PMC2, "PMC2",
952 SPR_NOACCESS, SPR_NOACCESS,
953 &spr_read_generic, &spr_write_generic,
954 0x00000000);
955 /* XXX : not implemented */
956 spr_register(env, SPR_PMC3, "PMC3",
957 SPR_NOACCESS, SPR_NOACCESS,
958 &spr_read_generic, &spr_write_generic,
959 0x00000000);
960 /* XXX : not implemented */
961 spr_register(env, SPR_PMC4, "PMC4",
962 SPR_NOACCESS, SPR_NOACCESS,
963 &spr_read_generic, &spr_write_generic,
964 0x00000000);
965 /* XXX : not implemented */
966 spr_register(env, SPR_SIAR, "SIAR",
967 SPR_NOACCESS, SPR_NOACCESS,
968 &spr_read_generic, SPR_NOACCESS,
969 0x00000000);
970 /* XXX : not implemented */
971 spr_register(env, SPR_UMMCR0, "UMMCR0",
972 &spr_read_ureg, SPR_NOACCESS,
973 &spr_read_ureg, SPR_NOACCESS,
974 0x00000000);
975 /* XXX : not implemented */
976 spr_register(env, SPR_UMMCR1, "UMMCR1",
977 &spr_read_ureg, SPR_NOACCESS,
978 &spr_read_ureg, SPR_NOACCESS,
979 0x00000000);
980 /* XXX : not implemented */
981 spr_register(env, SPR_UPMC1, "UPMC1",
982 &spr_read_ureg, SPR_NOACCESS,
983 &spr_read_ureg, SPR_NOACCESS,
984 0x00000000);
985 /* XXX : not implemented */
986 spr_register(env, SPR_UPMC2, "UPMC2",
987 &spr_read_ureg, SPR_NOACCESS,
988 &spr_read_ureg, SPR_NOACCESS,
989 0x00000000);
990 /* XXX : not implemented */
991 spr_register(env, SPR_UPMC3, "UPMC3",
992 &spr_read_ureg, SPR_NOACCESS,
993 &spr_read_ureg, SPR_NOACCESS,
994 0x00000000);
995 /* XXX : not implemented */
996 spr_register(env, SPR_UPMC4, "UPMC4",
997 &spr_read_ureg, SPR_NOACCESS,
998 &spr_read_ureg, SPR_NOACCESS,
999 0x00000000);
1000 /* XXX : not implemented */
1001 spr_register(env, SPR_USIAR, "USIAR",
1002 &spr_read_ureg, SPR_NOACCESS,
1003 &spr_read_ureg, SPR_NOACCESS,
1004 0x00000000);
1005 /* External access control */
1006 /* XXX : not implemented */
1007 spr_register(env, SPR_EAR, "EAR",
1008 SPR_NOACCESS, SPR_NOACCESS,
1009 &spr_read_generic, &spr_write_generic,
1010 0x00000000);
1011 }
1012
1013 static void gen_spr_thrm (CPUPPCState *env)
1014 {
1015 /* Thermal management */
1016 /* XXX : not implemented */
1017 spr_register(env, SPR_THRM1, "THRM1",
1018 SPR_NOACCESS, SPR_NOACCESS,
1019 &spr_read_generic, &spr_write_generic,
1020 0x00000000);
1021 /* XXX : not implemented */
1022 spr_register(env, SPR_THRM2, "THRM2",
1023 SPR_NOACCESS, SPR_NOACCESS,
1024 &spr_read_generic, &spr_write_generic,
1025 0x00000000);
1026 /* XXX : not implemented */
1027 spr_register(env, SPR_THRM3, "THRM3",
1028 SPR_NOACCESS, SPR_NOACCESS,
1029 &spr_read_generic, &spr_write_generic,
1030 0x00000000);
1031 }
1032
1033 /* SPR specific to PowerPC 604 implementation */
1034 static void gen_spr_604 (CPUPPCState *env)
1035 {
1036 /* Processor identification */
1037 spr_register(env, SPR_PIR, "PIR",
1038 SPR_NOACCESS, SPR_NOACCESS,
1039 &spr_read_generic, &spr_write_pir,
1040 0x00000000);
1041 /* Breakpoints */
1042 /* XXX : not implemented */
1043 spr_register(env, SPR_IABR, "IABR",
1044 SPR_NOACCESS, SPR_NOACCESS,
1045 &spr_read_generic, &spr_write_generic,
1046 0x00000000);
1047 /* XXX : not implemented */
1048 spr_register(env, SPR_DABR, "DABR",
1049 SPR_NOACCESS, SPR_NOACCESS,
1050 &spr_read_generic, &spr_write_generic,
1051 0x00000000);
1052 /* Performance counters */
1053 /* XXX : not implemented */
1054 spr_register(env, SPR_MMCR0, "MMCR0",
1055 SPR_NOACCESS, SPR_NOACCESS,
1056 &spr_read_generic, &spr_write_generic,
1057 0x00000000);
1058 /* XXX : not implemented */
1059 spr_register(env, SPR_PMC1, "PMC1",
1060 SPR_NOACCESS, SPR_NOACCESS,
1061 &spr_read_generic, &spr_write_generic,
1062 0x00000000);
1063 /* XXX : not implemented */
1064 spr_register(env, SPR_PMC2, "PMC2",
1065 SPR_NOACCESS, SPR_NOACCESS,
1066 &spr_read_generic, &spr_write_generic,
1067 0x00000000);
1068 /* XXX : not implemented */
1069 spr_register(env, SPR_SIAR, "SIAR",
1070 SPR_NOACCESS, SPR_NOACCESS,
1071 &spr_read_generic, SPR_NOACCESS,
1072 0x00000000);
1073 /* XXX : not implemented */
1074 spr_register(env, SPR_SDA, "SDA",
1075 SPR_NOACCESS, SPR_NOACCESS,
1076 &spr_read_generic, SPR_NOACCESS,
1077 0x00000000);
1078 /* External access control */
1079 /* XXX : not implemented */
1080 spr_register(env, SPR_EAR, "EAR",
1081 SPR_NOACCESS, SPR_NOACCESS,
1082 &spr_read_generic, &spr_write_generic,
1083 0x00000000);
1084 }
1085
1086 /* SPR specific to PowerPC 603 implementation */
1087 static void gen_spr_603 (CPUPPCState *env)
1088 {
1089 /* External access control */
1090 /* XXX : not implemented */
1091 spr_register(env, SPR_EAR, "EAR",
1092 SPR_NOACCESS, SPR_NOACCESS,
1093 &spr_read_generic, &spr_write_generic,
1094 0x00000000);
1095 }
1096
1097 /* SPR specific to PowerPC G2 implementation */
1098 static void gen_spr_G2 (CPUPPCState *env)
1099 {
1100 /* Memory base address */
1101 /* MBAR */
1102 /* XXX : not implemented */
1103 spr_register(env, SPR_MBAR, "MBAR",
1104 SPR_NOACCESS, SPR_NOACCESS,
1105 &spr_read_generic, &spr_write_generic,
1106 0x00000000);
1107 /* Exception processing */
1108 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1109 SPR_NOACCESS, SPR_NOACCESS,
1110 &spr_read_generic, &spr_write_generic,
1111 0x00000000);
1112 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1113 SPR_NOACCESS, SPR_NOACCESS,
1114 &spr_read_generic, &spr_write_generic,
1115 0x00000000);
1116 /* Breakpoints */
1117 /* XXX : not implemented */
1118 spr_register(env, SPR_DABR, "DABR",
1119 SPR_NOACCESS, SPR_NOACCESS,
1120 &spr_read_generic, &spr_write_generic,
1121 0x00000000);
1122 /* XXX : not implemented */
1123 spr_register(env, SPR_DABR2, "DABR2",
1124 SPR_NOACCESS, SPR_NOACCESS,
1125 &spr_read_generic, &spr_write_generic,
1126 0x00000000);
1127 /* XXX : not implemented */
1128 spr_register(env, SPR_IABR, "IABR",
1129 SPR_NOACCESS, SPR_NOACCESS,
1130 &spr_read_generic, &spr_write_generic,
1131 0x00000000);
1132 /* XXX : not implemented */
1133 spr_register(env, SPR_IABR2, "IABR2",
1134 SPR_NOACCESS, SPR_NOACCESS,
1135 &spr_read_generic, &spr_write_generic,
1136 0x00000000);
1137 /* XXX : not implemented */
1138 spr_register(env, SPR_IBCR, "IBCR",
1139 SPR_NOACCESS, SPR_NOACCESS,
1140 &spr_read_generic, &spr_write_generic,
1141 0x00000000);
1142 /* XXX : not implemented */
1143 spr_register(env, SPR_DBCR, "DBCR",
1144 SPR_NOACCESS, SPR_NOACCESS,
1145 &spr_read_generic, &spr_write_generic,
1146 0x00000000);
1147 }
1148
1149 /* SPR specific to PowerPC 602 implementation */
1150 static void gen_spr_602 (CPUPPCState *env)
1151 {
1152 /* ESA registers */
1153 /* XXX : not implemented */
1154 spr_register(env, SPR_SER, "SER",
1155 SPR_NOACCESS, SPR_NOACCESS,
1156 &spr_read_generic, &spr_write_generic,
1157 0x00000000);
1158 /* XXX : not implemented */
1159 spr_register(env, SPR_SEBR, "SEBR",
1160 SPR_NOACCESS, SPR_NOACCESS,
1161 &spr_read_generic, &spr_write_generic,
1162 0x00000000);
1163 /* XXX : not implemented */
1164 spr_register(env, SPR_ESASRR, "ESASRR",
1165 SPR_NOACCESS, SPR_NOACCESS,
1166 &spr_read_generic, &spr_write_generic,
1167 0x00000000);
1168 /* Floating point status */
1169 /* XXX : not implemented */
1170 spr_register(env, SPR_SP, "SP",
1171 SPR_NOACCESS, SPR_NOACCESS,
1172 &spr_read_generic, &spr_write_generic,
1173 0x00000000);
1174 /* XXX : not implemented */
1175 spr_register(env, SPR_LT, "LT",
1176 SPR_NOACCESS, SPR_NOACCESS,
1177 &spr_read_generic, &spr_write_generic,
1178 0x00000000);
1179 /* Watchdog timer */
1180 /* XXX : not implemented */
1181 spr_register(env, SPR_TCR, "TCR",
1182 SPR_NOACCESS, SPR_NOACCESS,
1183 &spr_read_generic, &spr_write_generic,
1184 0x00000000);
1185 /* Interrupt base */
1186 spr_register(env, SPR_IBR, "IBR",
1187 SPR_NOACCESS, SPR_NOACCESS,
1188 &spr_read_generic, &spr_write_generic,
1189 0x00000000);
1190 /* XXX : not implemented */
1191 spr_register(env, SPR_IABR, "IABR",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
1195 }
1196
1197 /* SPR specific to PowerPC 601 implementation */
1198 static void gen_spr_601 (CPUPPCState *env)
1199 {
1200 /* Multiplication/division register */
1201 /* MQ */
1202 spr_register(env, SPR_MQ, "MQ",
1203 &spr_read_generic, &spr_write_generic,
1204 &spr_read_generic, &spr_write_generic,
1205 0x00000000);
1206 /* RTC registers */
1207 spr_register(env, SPR_601_RTCU, "RTCU",
1208 SPR_NOACCESS, SPR_NOACCESS,
1209 SPR_NOACCESS, &spr_write_601_rtcu,
1210 0x00000000);
1211 spr_register(env, SPR_601_VRTCU, "RTCU",
1212 &spr_read_601_rtcu, SPR_NOACCESS,
1213 &spr_read_601_rtcu, SPR_NOACCESS,
1214 0x00000000);
1215 spr_register(env, SPR_601_RTCL, "RTCL",
1216 SPR_NOACCESS, SPR_NOACCESS,
1217 SPR_NOACCESS, &spr_write_601_rtcl,
1218 0x00000000);
1219 spr_register(env, SPR_601_VRTCL, "RTCL",
1220 &spr_read_601_rtcl, SPR_NOACCESS,
1221 &spr_read_601_rtcl, SPR_NOACCESS,
1222 0x00000000);
1223 /* Timer */
1224 #if 0 /* ? */
1225 spr_register(env, SPR_601_UDECR, "UDECR",
1226 &spr_read_decr, SPR_NOACCESS,
1227 &spr_read_decr, SPR_NOACCESS,
1228 0x00000000);
1229 #endif
1230 /* External access control */
1231 /* XXX : not implemented */
1232 spr_register(env, SPR_EAR, "EAR",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_generic, &spr_write_generic,
1235 0x00000000);
1236 /* Memory management */
1237 #if !defined(CONFIG_USER_ONLY)
1238 spr_register(env, SPR_IBAT0U, "IBAT0U",
1239 SPR_NOACCESS, SPR_NOACCESS,
1240 &spr_read_601_ubat, &spr_write_601_ubatu,
1241 0x00000000);
1242 spr_register(env, SPR_IBAT0L, "IBAT0L",
1243 SPR_NOACCESS, SPR_NOACCESS,
1244 &spr_read_601_ubat, &spr_write_601_ubatl,
1245 0x00000000);
1246 spr_register(env, SPR_IBAT1U, "IBAT1U",
1247 SPR_NOACCESS, SPR_NOACCESS,
1248 &spr_read_601_ubat, &spr_write_601_ubatu,
1249 0x00000000);
1250 spr_register(env, SPR_IBAT1L, "IBAT1L",
1251 SPR_NOACCESS, SPR_NOACCESS,
1252 &spr_read_601_ubat, &spr_write_601_ubatl,
1253 0x00000000);
1254 spr_register(env, SPR_IBAT2U, "IBAT2U",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_601_ubat, &spr_write_601_ubatu,
1257 0x00000000);
1258 spr_register(env, SPR_IBAT2L, "IBAT2L",
1259 SPR_NOACCESS, SPR_NOACCESS,
1260 &spr_read_601_ubat, &spr_write_601_ubatl,
1261 0x00000000);
1262 spr_register(env, SPR_IBAT3U, "IBAT3U",
1263 SPR_NOACCESS, SPR_NOACCESS,
1264 &spr_read_601_ubat, &spr_write_601_ubatu,
1265 0x00000000);
1266 spr_register(env, SPR_IBAT3L, "IBAT3L",
1267 SPR_NOACCESS, SPR_NOACCESS,
1268 &spr_read_601_ubat, &spr_write_601_ubatl,
1269 0x00000000);
1270 env->nb_BATs = 4;
1271 #endif
1272 }
1273
1274 static void gen_spr_74xx (CPUPPCState *env)
1275 {
1276 /* Processor identification */
1277 spr_register(env, SPR_PIR, "PIR",
1278 SPR_NOACCESS, SPR_NOACCESS,
1279 &spr_read_generic, &spr_write_pir,
1280 0x00000000);
1281 /* XXX : not implemented */
1282 spr_register(env, SPR_MMCR2, "MMCR2",
1283 SPR_NOACCESS, SPR_NOACCESS,
1284 &spr_read_generic, &spr_write_generic,
1285 0x00000000);
1286 /* XXX : not implemented */
1287 spr_register(env, SPR_UMMCR2, "UMMCR2",
1288 &spr_read_ureg, SPR_NOACCESS,
1289 &spr_read_ureg, SPR_NOACCESS,
1290 0x00000000);
1291 /* XXX: not implemented */
1292 spr_register(env, SPR_BAMR, "BAMR",
1293 SPR_NOACCESS, SPR_NOACCESS,
1294 &spr_read_generic, &spr_write_generic,
1295 0x00000000);
1296 /* XXX : not implemented */
1297 spr_register(env, SPR_MSSCR0, "MSSCR0",
1298 SPR_NOACCESS, SPR_NOACCESS,
1299 &spr_read_generic, &spr_write_generic,
1300 0x00000000);
1301 /* Hardware implementation registers */
1302 /* XXX : not implemented */
1303 spr_register(env, SPR_HID0, "HID0",
1304 SPR_NOACCESS, SPR_NOACCESS,
1305 &spr_read_generic, &spr_write_generic,
1306 0x00000000);
1307 /* XXX : not implemented */
1308 spr_register(env, SPR_HID1, "HID1",
1309 SPR_NOACCESS, SPR_NOACCESS,
1310 &spr_read_generic, &spr_write_generic,
1311 0x00000000);
1312 /* Altivec */
1313 spr_register(env, SPR_VRSAVE, "VRSAVE",
1314 &spr_read_generic, &spr_write_generic,
1315 &spr_read_generic, &spr_write_generic,
1316 0x00000000);
1317 /* XXX : not implemented */
1318 spr_register(env, SPR_L2CR, "L2CR",
1319 SPR_NOACCESS, SPR_NOACCESS,
1320 &spr_read_generic, &spr_write_generic,
1321 0x00000000);
1322 /* Not strictly an SPR */
1323 vscr_init(env, 0x00010000);
1324 }
1325
1326 static void gen_l3_ctrl (CPUPPCState *env)
1327 {
1328 /* L3CR */
1329 /* XXX : not implemented */
1330 spr_register(env, SPR_L3CR, "L3CR",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1333 0x00000000);
1334 /* L3ITCR0 */
1335 /* XXX : not implemented */
1336 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1337 SPR_NOACCESS, SPR_NOACCESS,
1338 &spr_read_generic, &spr_write_generic,
1339 0x00000000);
1340 /* L3PM */
1341 /* XXX : not implemented */
1342 spr_register(env, SPR_L3PM, "L3PM",
1343 SPR_NOACCESS, SPR_NOACCESS,
1344 &spr_read_generic, &spr_write_generic,
1345 0x00000000);
1346 }
1347
1348 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1349 {
1350 #if !defined(CONFIG_USER_ONLY)
1351 env->nb_tlb = nb_tlbs;
1352 env->nb_ways = nb_ways;
1353 env->id_tlbs = 1;
1354 env->tlb_type = TLB_6XX;
1355 /* XXX : not implemented */
1356 spr_register(env, SPR_PTEHI, "PTEHI",
1357 SPR_NOACCESS, SPR_NOACCESS,
1358 &spr_read_generic, &spr_write_generic,
1359 0x00000000);
1360 /* XXX : not implemented */
1361 spr_register(env, SPR_PTELO, "PTELO",
1362 SPR_NOACCESS, SPR_NOACCESS,
1363 &spr_read_generic, &spr_write_generic,
1364 0x00000000);
1365 /* XXX : not implemented */
1366 spr_register(env, SPR_TLBMISS, "TLBMISS",
1367 SPR_NOACCESS, SPR_NOACCESS,
1368 &spr_read_generic, &spr_write_generic,
1369 0x00000000);
1370 #endif
1371 }
1372
1373 #if !defined(CONFIG_USER_ONLY)
1374 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1375 {
1376 TCGv t0 = tcg_temp_new();
1377
1378 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1379 gen_store_spr(sprn, t0);
1380 tcg_temp_free(t0);
1381 }
1382
1383 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1384 {
1385 TCGv_i32 t0 = tcg_const_i32(sprn);
1386 gen_helper_booke206_tlbflush(t0);
1387 tcg_temp_free_i32(t0);
1388 }
1389
1390 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1391 {
1392 TCGv_i32 t0 = tcg_const_i32(sprn);
1393 gen_helper_booke_setpid(t0, cpu_gpr[gprn]);
1394 tcg_temp_free_i32(t0);
1395 }
1396 #endif
1397
1398 static void gen_spr_usprgh (CPUPPCState *env)
1399 {
1400 spr_register(env, SPR_USPRG4, "USPRG4",
1401 &spr_read_ureg, SPR_NOACCESS,
1402 &spr_read_ureg, SPR_NOACCESS,
1403 0x00000000);
1404 spr_register(env, SPR_USPRG5, "USPRG5",
1405 &spr_read_ureg, SPR_NOACCESS,
1406 &spr_read_ureg, SPR_NOACCESS,
1407 0x00000000);
1408 spr_register(env, SPR_USPRG6, "USPRG6",
1409 &spr_read_ureg, SPR_NOACCESS,
1410 &spr_read_ureg, SPR_NOACCESS,
1411 0x00000000);
1412 spr_register(env, SPR_USPRG7, "USPRG7",
1413 &spr_read_ureg, SPR_NOACCESS,
1414 &spr_read_ureg, SPR_NOACCESS,
1415 0x00000000);
1416 }
1417
1418 /* PowerPC BookE SPR */
1419 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1420 {
1421 const char *ivor_names[64] = {
1422 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1423 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1424 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1425 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1426 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1427 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1428 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1429 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1430 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1431 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1432 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1433 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1434 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1435 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1436 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1437 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1438 };
1439 #define SPR_BOOKE_IVORxx (-1)
1440 int ivor_sprn[64] = {
1441 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1442 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1443 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1444 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1445 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1446 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1447 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1448 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1449 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1450 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1451 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1452 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1453 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1454 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1455 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1456 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1457 };
1458 int i;
1459
1460 /* Interrupt processing */
1461 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1462 SPR_NOACCESS, SPR_NOACCESS,
1463 &spr_read_generic, &spr_write_generic,
1464 0x00000000);
1465 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1466 SPR_NOACCESS, SPR_NOACCESS,
1467 &spr_read_generic, &spr_write_generic,
1468 0x00000000);
1469 /* Debug */
1470 /* XXX : not implemented */
1471 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1472 SPR_NOACCESS, SPR_NOACCESS,
1473 &spr_read_generic, &spr_write_generic,
1474 0x00000000);
1475 /* XXX : not implemented */
1476 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1477 SPR_NOACCESS, SPR_NOACCESS,
1478 &spr_read_generic, &spr_write_generic,
1479 0x00000000);
1480 /* XXX : not implemented */
1481 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1482 SPR_NOACCESS, SPR_NOACCESS,
1483 &spr_read_generic, &spr_write_generic,
1484 0x00000000);
1485 /* XXX : not implemented */
1486 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1487 SPR_NOACCESS, SPR_NOACCESS,
1488 &spr_read_generic, &spr_write_generic,
1489 0x00000000);
1490 /* XXX : not implemented */
1491 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1492 SPR_NOACCESS, SPR_NOACCESS,
1493 &spr_read_generic, &spr_write_generic,
1494 0x00000000);
1495 /* XXX : not implemented */
1496 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1497 SPR_NOACCESS, SPR_NOACCESS,
1498 &spr_read_generic, &spr_write_generic,
1499 0x00000000);
1500 /* XXX : not implemented */
1501 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1502 SPR_NOACCESS, SPR_NOACCESS,
1503 &spr_read_generic, &spr_write_generic,
1504 0x00000000);
1505 /* XXX : not implemented */
1506 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1507 SPR_NOACCESS, SPR_NOACCESS,
1508 &spr_read_generic, &spr_write_clear,
1509 0x00000000);
1510 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1511 SPR_NOACCESS, SPR_NOACCESS,
1512 &spr_read_generic, &spr_write_generic,
1513 0x00000000);
1514 spr_register(env, SPR_BOOKE_ESR, "ESR",
1515 SPR_NOACCESS, SPR_NOACCESS,
1516 &spr_read_generic, &spr_write_generic,
1517 0x00000000);
1518 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1519 SPR_NOACCESS, SPR_NOACCESS,
1520 &spr_read_generic, &spr_write_excp_prefix,
1521 0x00000000);
1522 /* Exception vectors */
1523 for (i = 0; i < 64; i++) {
1524 if (ivor_mask & (1ULL << i)) {
1525 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1526 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1527 exit(1);
1528 }
1529 spr_register(env, ivor_sprn[i], ivor_names[i],
1530 SPR_NOACCESS, SPR_NOACCESS,
1531 &spr_read_generic, &spr_write_excp_vector,
1532 0x00000000);
1533 }
1534 }
1535 spr_register(env, SPR_BOOKE_PID, "PID",
1536 SPR_NOACCESS, SPR_NOACCESS,
1537 &spr_read_generic, &spr_write_booke_pid,
1538 0x00000000);
1539 spr_register(env, SPR_BOOKE_TCR, "TCR",
1540 SPR_NOACCESS, SPR_NOACCESS,
1541 &spr_read_generic, &spr_write_booke_tcr,
1542 0x00000000);
1543 spr_register(env, SPR_BOOKE_TSR, "TSR",
1544 SPR_NOACCESS, SPR_NOACCESS,
1545 &spr_read_generic, &spr_write_booke_tsr,
1546 0x00000000);
1547 /* Timer */
1548 spr_register(env, SPR_DECR, "DECR",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_decr, &spr_write_decr,
1551 0x00000000);
1552 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1553 SPR_NOACCESS, SPR_NOACCESS,
1554 SPR_NOACCESS, &spr_write_generic,
1555 0x00000000);
1556 /* SPRGs */
1557 spr_register(env, SPR_USPRG0, "USPRG0",
1558 &spr_read_generic, &spr_write_generic,
1559 &spr_read_generic, &spr_write_generic,
1560 0x00000000);
1561 spr_register(env, SPR_SPRG4, "SPRG4",
1562 SPR_NOACCESS, SPR_NOACCESS,
1563 &spr_read_generic, &spr_write_generic,
1564 0x00000000);
1565 spr_register(env, SPR_SPRG5, "SPRG5",
1566 SPR_NOACCESS, SPR_NOACCESS,
1567 &spr_read_generic, &spr_write_generic,
1568 0x00000000);
1569 spr_register(env, SPR_SPRG6, "SPRG6",
1570 SPR_NOACCESS, SPR_NOACCESS,
1571 &spr_read_generic, &spr_write_generic,
1572 0x00000000);
1573 spr_register(env, SPR_SPRG7, "SPRG7",
1574 SPR_NOACCESS, SPR_NOACCESS,
1575 &spr_read_generic, &spr_write_generic,
1576 0x00000000);
1577 }
1578
1579 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1580 uint32_t maxsize, uint32_t flags,
1581 uint32_t nentries)
1582 {
1583 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1584 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1585 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1586 flags | nentries;
1587 }
1588
1589 /* BookE 2.06 storage control registers */
1590 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1591 uint32_t *tlbncfg)
1592 {
1593 #if !defined(CONFIG_USER_ONLY)
1594 const char *mas_names[8] = {
1595 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1596 };
1597 int mas_sprn[8] = {
1598 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1599 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1600 };
1601 int i;
1602
1603 /* TLB assist registers */
1604 /* XXX : not implemented */
1605 for (i = 0; i < 8; i++) {
1606 if (mas_mask & (1 << i)) {
1607 spr_register(env, mas_sprn[i], mas_names[i],
1608 SPR_NOACCESS, SPR_NOACCESS,
1609 &spr_read_generic, &spr_write_generic,
1610 0x00000000);
1611 }
1612 }
1613 if (env->nb_pids > 1) {
1614 /* XXX : not implemented */
1615 spr_register(env, SPR_BOOKE_PID1, "PID1",
1616 SPR_NOACCESS, SPR_NOACCESS,
1617 &spr_read_generic, &spr_write_booke_pid,
1618 0x00000000);
1619 }
1620 if (env->nb_pids > 2) {
1621 /* XXX : not implemented */
1622 spr_register(env, SPR_BOOKE_PID2, "PID2",
1623 SPR_NOACCESS, SPR_NOACCESS,
1624 &spr_read_generic, &spr_write_booke_pid,
1625 0x00000000);
1626 }
1627 /* XXX : not implemented */
1628 spr_register(env, SPR_MMUCFG, "MMUCFG",
1629 SPR_NOACCESS, SPR_NOACCESS,
1630 &spr_read_generic, SPR_NOACCESS,
1631 0x00000000); /* TOFIX */
1632 switch (env->nb_ways) {
1633 case 4:
1634 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_generic, SPR_NOACCESS,
1637 tlbncfg[3]);
1638 /* Fallthru */
1639 case 3:
1640 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1641 SPR_NOACCESS, SPR_NOACCESS,
1642 &spr_read_generic, SPR_NOACCESS,
1643 tlbncfg[2]);
1644 /* Fallthru */
1645 case 2:
1646 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1647 SPR_NOACCESS, SPR_NOACCESS,
1648 &spr_read_generic, SPR_NOACCESS,
1649 tlbncfg[1]);
1650 /* Fallthru */
1651 case 1:
1652 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1653 SPR_NOACCESS, SPR_NOACCESS,
1654 &spr_read_generic, SPR_NOACCESS,
1655 tlbncfg[0]);
1656 /* Fallthru */
1657 case 0:
1658 default:
1659 break;
1660 }
1661 #endif
1662
1663 gen_spr_usprgh(env);
1664 }
1665
1666 /* SPR specific to PowerPC 440 implementation */
1667 static void gen_spr_440 (CPUPPCState *env)
1668 {
1669 /* Cache control */
1670 /* XXX : not implemented */
1671 spr_register(env, SPR_440_DNV0, "DNV0",
1672 SPR_NOACCESS, SPR_NOACCESS,
1673 &spr_read_generic, &spr_write_generic,
1674 0x00000000);
1675 /* XXX : not implemented */
1676 spr_register(env, SPR_440_DNV1, "DNV1",
1677 SPR_NOACCESS, SPR_NOACCESS,
1678 &spr_read_generic, &spr_write_generic,
1679 0x00000000);
1680 /* XXX : not implemented */
1681 spr_register(env, SPR_440_DNV2, "DNV2",
1682 SPR_NOACCESS, SPR_NOACCESS,
1683 &spr_read_generic, &spr_write_generic,
1684 0x00000000);
1685 /* XXX : not implemented */
1686 spr_register(env, SPR_440_DNV3, "DNV3",
1687 SPR_NOACCESS, SPR_NOACCESS,
1688 &spr_read_generic, &spr_write_generic,
1689 0x00000000);
1690 /* XXX : not implemented */
1691 spr_register(env, SPR_440_DTV0, "DTV0",
1692 SPR_NOACCESS, SPR_NOACCESS,
1693 &spr_read_generic, &spr_write_generic,
1694 0x00000000);
1695 /* XXX : not implemented */
1696 spr_register(env, SPR_440_DTV1, "DTV1",
1697 SPR_NOACCESS, SPR_NOACCESS,
1698 &spr_read_generic, &spr_write_generic,
1699 0x00000000);
1700 /* XXX : not implemented */
1701 spr_register(env, SPR_440_DTV2, "DTV2",
1702 SPR_NOACCESS, SPR_NOACCESS,
1703 &spr_read_generic, &spr_write_generic,
1704 0x00000000);
1705 /* XXX : not implemented */
1706 spr_register(env, SPR_440_DTV3, "DTV3",
1707 SPR_NOACCESS, SPR_NOACCESS,
1708 &spr_read_generic, &spr_write_generic,
1709 0x00000000);
1710 /* XXX : not implemented */
1711 spr_register(env, SPR_440_DVLIM, "DVLIM",
1712 SPR_NOACCESS, SPR_NOACCESS,
1713 &spr_read_generic, &spr_write_generic,
1714 0x00000000);
1715 /* XXX : not implemented */
1716 spr_register(env, SPR_440_INV0, "INV0",
1717 SPR_NOACCESS, SPR_NOACCESS,
1718 &spr_read_generic, &spr_write_generic,
1719 0x00000000);
1720 /* XXX : not implemented */
1721 spr_register(env, SPR_440_INV1, "INV1",
1722 SPR_NOACCESS, SPR_NOACCESS,
1723 &spr_read_generic, &spr_write_generic,
1724 0x00000000);
1725 /* XXX : not implemented */
1726 spr_register(env, SPR_440_INV2, "INV2",
1727 SPR_NOACCESS, SPR_NOACCESS,
1728 &spr_read_generic, &spr_write_generic,
1729 0x00000000);
1730 /* XXX : not implemented */
1731 spr_register(env, SPR_440_INV3, "INV3",
1732 SPR_NOACCESS, SPR_NOACCESS,
1733 &spr_read_generic, &spr_write_generic,
1734 0x00000000);
1735 /* XXX : not implemented */
1736 spr_register(env, SPR_440_ITV0, "ITV0",
1737 SPR_NOACCESS, SPR_NOACCESS,
1738 &spr_read_generic, &spr_write_generic,
1739 0x00000000);
1740 /* XXX : not implemented */
1741 spr_register(env, SPR_440_ITV1, "ITV1",
1742 SPR_NOACCESS, SPR_NOACCESS,
1743 &spr_read_generic, &spr_write_generic,
1744 0x00000000);
1745 /* XXX : not implemented */
1746 spr_register(env, SPR_440_ITV2, "ITV2",
1747 SPR_NOACCESS, SPR_NOACCESS,
1748 &spr_read_generic, &spr_write_generic,
1749 0x00000000);
1750 /* XXX : not implemented */
1751 spr_register(env, SPR_440_ITV3, "ITV3",
1752 SPR_NOACCESS, SPR_NOACCESS,
1753 &spr_read_generic, &spr_write_generic,
1754 0x00000000);
1755 /* XXX : not implemented */
1756 spr_register(env, SPR_440_IVLIM, "IVLIM",
1757 SPR_NOACCESS, SPR_NOACCESS,
1758 &spr_read_generic, &spr_write_generic,
1759 0x00000000);
1760 /* Cache debug */
1761 /* XXX : not implemented */
1762 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1763 SPR_NOACCESS, SPR_NOACCESS,
1764 &spr_read_generic, SPR_NOACCESS,
1765 0x00000000);
1766 /* XXX : not implemented */
1767 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1768 SPR_NOACCESS, SPR_NOACCESS,
1769 &spr_read_generic, SPR_NOACCESS,
1770 0x00000000);
1771 /* XXX : not implemented */
1772 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1773 SPR_NOACCESS, SPR_NOACCESS,
1774 &spr_read_generic, SPR_NOACCESS,
1775 0x00000000);
1776 /* XXX : not implemented */
1777 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1778 SPR_NOACCESS, SPR_NOACCESS,
1779 &spr_read_generic, SPR_NOACCESS,
1780 0x00000000);
1781 /* XXX : not implemented */
1782 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1783 SPR_NOACCESS, SPR_NOACCESS,
1784 &spr_read_generic, SPR_NOACCESS,
1785 0x00000000);
1786 /* XXX : not implemented */
1787 spr_register(env, SPR_440_DBDR, "DBDR",
1788 SPR_NOACCESS, SPR_NOACCESS,
1789 &spr_read_generic, &spr_write_generic,
1790 0x00000000);
1791 /* Processor control */
1792 spr_register(env, SPR_4xx_CCR0, "CCR0",
1793 SPR_NOACCESS, SPR_NOACCESS,
1794 &spr_read_generic, &spr_write_generic,
1795 0x00000000);
1796 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1797 SPR_NOACCESS, SPR_NOACCESS,
1798 &spr_read_generic, SPR_NOACCESS,
1799 0x00000000);
1800 /* Storage control */
1801 spr_register(env, SPR_440_MMUCR, "MMUCR",
1802 SPR_NOACCESS, SPR_NOACCESS,
1803 &spr_read_generic, &spr_write_generic,
1804 0x00000000);
1805 }
1806
1807 /* SPR shared between PowerPC 40x implementations */
1808 static void gen_spr_40x (CPUPPCState *env)
1809 {
1810 /* Cache */
1811 /* not emulated, as Qemu do not emulate caches */
1812 spr_register(env, SPR_40x_DCCR, "DCCR",
1813 SPR_NOACCESS, SPR_NOACCESS,
1814 &spr_read_generic, &spr_write_generic,
1815 0x00000000);
1816 /* not emulated, as Qemu do not emulate caches */
1817 spr_register(env, SPR_40x_ICCR, "ICCR",
1818 SPR_NOACCESS, SPR_NOACCESS,
1819 &spr_read_generic, &spr_write_generic,
1820 0x00000000);
1821 /* not emulated, as Qemu do not emulate caches */
1822 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1823 SPR_NOACCESS, SPR_NOACCESS,
1824 &spr_read_generic, SPR_NOACCESS,
1825 0x00000000);
1826 /* Exception */
1827 spr_register(env, SPR_40x_DEAR, "DEAR",
1828 SPR_NOACCESS, SPR_NOACCESS,
1829 &spr_read_generic, &spr_write_generic,
1830 0x00000000);
1831 spr_register(env, SPR_40x_ESR, "ESR",
1832 SPR_NOACCESS, SPR_NOACCESS,
1833 &spr_read_generic, &spr_write_generic,
1834 0x00000000);
1835 spr_register(env, SPR_40x_EVPR, "EVPR",
1836 SPR_NOACCESS, SPR_NOACCESS,
1837 &spr_read_generic, &spr_write_excp_prefix,
1838 0x00000000);
1839 spr_register(env, SPR_40x_SRR2, "SRR2",
1840 &spr_read_generic, &spr_write_generic,
1841 &spr_read_generic, &spr_write_generic,
1842 0x00000000);
1843 spr_register(env, SPR_40x_SRR3, "SRR3",
1844 &spr_read_generic, &spr_write_generic,
1845 &spr_read_generic, &spr_write_generic,
1846 0x00000000);
1847 /* Timers */
1848 spr_register(env, SPR_40x_PIT, "PIT",
1849 SPR_NOACCESS, SPR_NOACCESS,
1850 &spr_read_40x_pit, &spr_write_40x_pit,
1851 0x00000000);
1852 spr_register(env, SPR_40x_TCR, "TCR",
1853 SPR_NOACCESS, SPR_NOACCESS,
1854 &spr_read_generic, &spr_write_booke_tcr,
1855 0x00000000);
1856 spr_register(env, SPR_40x_TSR, "TSR",
1857 SPR_NOACCESS, SPR_NOACCESS,
1858 &spr_read_generic, &spr_write_booke_tsr,
1859 0x00000000);
1860 }
1861
1862 /* SPR specific to PowerPC 405 implementation */
1863 static void gen_spr_405 (CPUPPCState *env)
1864 {
1865 /* MMU */
1866 spr_register(env, SPR_40x_PID, "PID",
1867 SPR_NOACCESS, SPR_NOACCESS,
1868 &spr_read_generic, &spr_write_generic,
1869 0x00000000);
1870 spr_register(env, SPR_4xx_CCR0, "CCR0",
1871 SPR_NOACCESS, SPR_NOACCESS,
1872 &spr_read_generic, &spr_write_generic,
1873 0x00700000);
1874 /* Debug interface */
1875 /* XXX : not implemented */
1876 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1877 SPR_NOACCESS, SPR_NOACCESS,
1878 &spr_read_generic, &spr_write_40x_dbcr0,
1879 0x00000000);
1880 /* XXX : not implemented */
1881 spr_register(env, SPR_405_DBCR1, "DBCR1",
1882 SPR_NOACCESS, SPR_NOACCESS,
1883 &spr_read_generic, &spr_write_generic,
1884 0x00000000);
1885 /* XXX : not implemented */
1886 spr_register(env, SPR_40x_DBSR, "DBSR",
1887 SPR_NOACCESS, SPR_NOACCESS,
1888 &spr_read_generic, &spr_write_clear,
1889 /* Last reset was system reset */
1890 0x00000300);
1891 /* XXX : not implemented */
1892 spr_register(env, SPR_40x_DAC1, "DAC1",
1893 SPR_NOACCESS, SPR_NOACCESS,
1894 &spr_read_generic, &spr_write_generic,
1895 0x00000000);
1896 spr_register(env, SPR_40x_DAC2, "DAC2",
1897 SPR_NOACCESS, SPR_NOACCESS,
1898 &spr_read_generic, &spr_write_generic,
1899 0x00000000);
1900 /* XXX : not implemented */
1901 spr_register(env, SPR_405_DVC1, "DVC1",
1902 SPR_NOACCESS, SPR_NOACCESS,
1903 &spr_read_generic, &spr_write_generic,
1904 0x00000000);
1905 /* XXX : not implemented */
1906 spr_register(env, SPR_405_DVC2, "DVC2",
1907 SPR_NOACCESS, SPR_NOACCESS,
1908 &spr_read_generic, &spr_write_generic,
1909 0x00000000);
1910 /* XXX : not implemented */
1911 spr_register(env, SPR_40x_IAC1, "IAC1",
1912 SPR_NOACCESS, SPR_NOACCESS,
1913 &spr_read_generic, &spr_write_generic,
1914 0x00000000);
1915 spr_register(env, SPR_40x_IAC2, "IAC2",
1916 SPR_NOACCESS, SPR_NOACCESS,
1917 &spr_read_generic, &spr_write_generic,
1918 0x00000000);
1919 /* XXX : not implemented */
1920 spr_register(env, SPR_405_IAC3, "IAC3",
1921 SPR_NOACCESS, SPR_NOACCESS,
1922 &spr_read_generic, &spr_write_generic,
1923 0x00000000);
1924 /* XXX : not implemented */
1925 spr_register(env, SPR_405_IAC4, "IAC4",
1926 SPR_NOACCESS, SPR_NOACCESS,
1927 &spr_read_generic, &spr_write_generic,
1928 0x00000000);
1929 /* Storage control */
1930 /* XXX: TODO: not implemented */
1931 spr_register(env, SPR_405_SLER, "SLER",
1932 SPR_NOACCESS, SPR_NOACCESS,
1933 &spr_read_generic, &spr_write_40x_sler,
1934 0x00000000);
1935 spr_register(env, SPR_40x_ZPR, "ZPR",
1936 SPR_NOACCESS, SPR_NOACCESS,
1937 &spr_read_generic, &spr_write_generic,
1938 0x00000000);
1939 /* XXX : not implemented */
1940 spr_register(env, SPR_405_SU0R, "SU0R",
1941 SPR_NOACCESS, SPR_NOACCESS,
1942 &spr_read_generic, &spr_write_generic,
1943 0x00000000);
1944 /* SPRG */
1945 spr_register(env, SPR_USPRG0, "USPRG0",
1946 &spr_read_ureg, SPR_NOACCESS,
1947 &spr_read_ureg, SPR_NOACCESS,
1948 0x00000000);
1949 spr_register(env, SPR_SPRG4, "SPRG4",
1950 SPR_NOACCESS, SPR_NOACCESS,
1951 &spr_read_generic, &spr_write_generic,
1952 0x00000000);
1953 spr_register(env, SPR_SPRG5, "SPRG5",
1954 SPR_NOACCESS, SPR_NOACCESS,
1955 spr_read_generic, &spr_write_generic,
1956 0x00000000);
1957 spr_register(env, SPR_SPRG6, "SPRG6",
1958 SPR_NOACCESS, SPR_NOACCESS,
1959 spr_read_generic, &spr_write_generic,
1960 0x00000000);
1961 spr_register(env, SPR_SPRG7, "SPRG7",
1962 SPR_NOACCESS, SPR_NOACCESS,
1963 spr_read_generic, &spr_write_generic,
1964 0x00000000);
1965 gen_spr_usprgh(env);
1966 }
1967
1968 /* SPR shared between PowerPC 401 & 403 implementations */
1969 static void gen_spr_401_403 (CPUPPCState *env)
1970 {
1971 /* Time base */
1972 spr_register(env, SPR_403_VTBL, "TBL",
1973 &spr_read_tbl, SPR_NOACCESS,
1974 &spr_read_tbl, SPR_NOACCESS,
1975 0x00000000);
1976 spr_register(env, SPR_403_TBL, "TBL",
1977 SPR_NOACCESS, SPR_NOACCESS,
1978 SPR_NOACCESS, &spr_write_tbl,
1979 0x00000000);
1980 spr_register(env, SPR_403_VTBU, "TBU",
1981 &spr_read_tbu, SPR_NOACCESS,
1982 &spr_read_tbu, SPR_NOACCESS,
1983 0x00000000);
1984 spr_register(env, SPR_403_TBU, "TBU",
1985 SPR_NOACCESS, SPR_NOACCESS,
1986 SPR_NOACCESS, &spr_write_tbu,
1987 0x00000000);
1988 /* Debug */
1989 /* not emulated, as Qemu do not emulate caches */
1990 spr_register(env, SPR_403_CDBCR, "CDBCR",
1991 SPR_NOACCESS, SPR_NOACCESS,
1992 &spr_read_generic, &spr_write_generic,
1993 0x00000000);
1994 }
1995
1996 /* SPR specific to PowerPC 401 implementation */
1997 static void gen_spr_401 (CPUPPCState *env)
1998 {
1999 /* Debug interface */
2000 /* XXX : not implemented */
2001 spr_register(env, SPR_40x_DBCR0, "DBCR",
2002 SPR_NOACCESS, SPR_NOACCESS,
2003 &spr_read_generic, &spr_write_40x_dbcr0,
2004 0x00000000);
2005 /* XXX : not implemented */
2006 spr_register(env, SPR_40x_DBSR, "DBSR",
2007 SPR_NOACCESS, SPR_NOACCESS,
2008 &spr_read_generic, &spr_write_clear,
2009 /* Last reset was system reset */
2010 0x00000300);
2011 /* XXX : not implemented */
2012 spr_register(env, SPR_40x_DAC1, "DAC",
2013 SPR_NOACCESS, SPR_NOACCESS,
2014 &spr_read_generic, &spr_write_generic,
2015 0x00000000);
2016 /* XXX : not implemented */
2017 spr_register(env, SPR_40x_IAC1, "IAC",
2018 SPR_NOACCESS, SPR_NOACCESS,
2019 &spr_read_generic, &spr_write_generic,
2020 0x00000000);
2021 /* Storage control */
2022 /* XXX: TODO: not implemented */
2023 spr_register(env, SPR_405_SLER, "SLER",
2024 SPR_NOACCESS, SPR_NOACCESS,
2025 &spr_read_generic, &spr_write_40x_sler,
2026 0x00000000);
2027 /* not emulated, as Qemu never does speculative access */
2028 spr_register(env, SPR_40x_SGR, "SGR",
2029 SPR_NOACCESS, SPR_NOACCESS,
2030 &spr_read_generic, &spr_write_generic,
2031 0xFFFFFFFF);
2032 /* not emulated, as Qemu do not emulate caches */
2033 spr_register(env, SPR_40x_DCWR, "DCWR",
2034 SPR_NOACCESS, SPR_NOACCESS,
2035 &spr_read_generic, &spr_write_generic,
2036 0x00000000);
2037 }
2038
2039 static void gen_spr_401x2 (CPUPPCState *env)
2040 {
2041 gen_spr_401(env);
2042 spr_register(env, SPR_40x_PID, "PID",
2043 SPR_NOACCESS, SPR_NOACCESS,
2044 &spr_read_generic, &spr_write_generic,
2045 0x00000000);
2046 spr_register(env, SPR_40x_ZPR, "ZPR",
2047 SPR_NOACCESS, SPR_NOACCESS,
2048 &spr_read_generic, &spr_write_generic,
2049 0x00000000);
2050 }
2051
2052 /* SPR specific to PowerPC 403 implementation */
2053 static void gen_spr_403 (CPUPPCState *env)
2054 {
2055 /* Debug interface */
2056 /* XXX : not implemented */
2057 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2058 SPR_NOACCESS, SPR_NOACCESS,
2059 &spr_read_generic, &spr_write_40x_dbcr0,
2060 0x00000000);
2061 /* XXX : not implemented */
2062 spr_register(env, SPR_40x_DBSR, "DBSR",
2063 SPR_NOACCESS, SPR_NOACCESS,
2064 &spr_read_generic, &spr_write_clear,
2065 /* Last reset was system reset */
2066 0x00000300);
2067 /* XXX : not implemented */
2068 spr_register(env, SPR_40x_DAC1, "DAC1",
2069 SPR_NOACCESS, SPR_NOACCESS,
2070 &spr_read_generic, &spr_write_generic,
2071 0x00000000);
2072 /* XXX : not implemented */
2073 spr_register(env, SPR_40x_DAC2, "DAC2",
2074 SPR_NOACCESS, SPR_NOACCESS,
2075 &spr_read_generic, &spr_write_generic,
2076 0x00000000);
2077 /* XXX : not implemented */
2078 spr_register(env, SPR_40x_IAC1, "IAC1",
2079 SPR_NOACCESS, SPR_NOACCESS,
2080 &spr_read_generic, &spr_write_generic,
2081 0x00000000);
2082 /* XXX : not implemented */
2083 spr_register(env, SPR_40x_IAC2, "IAC2",
2084 SPR_NOACCESS, SPR_NOACCESS,
2085 &spr_read_generic, &spr_write_generic,
2086 0x00000000);
2087 }
2088
2089 static void gen_spr_403_real (CPUPPCState *env)
2090 {
2091 spr_register(env, SPR_403_PBL1, "PBL1",
2092 SPR_NOACCESS, SPR_NOACCESS,
2093 &spr_read_403_pbr, &spr_write_403_pbr,
2094 0x00000000);
2095 spr_register(env, SPR_403_PBU1, "PBU1",
2096 SPR_NOACCESS, SPR_NOACCESS,
2097 &spr_read_403_pbr, &spr_write_403_pbr,
2098 0x00000000);
2099 spr_register(env, SPR_403_PBL2, "PBL2",
2100 SPR_NOACCESS, SPR_NOACCESS,
2101 &spr_read_403_pbr, &spr_write_403_pbr,
2102 0x00000000);
2103 spr_register(env, SPR_403_PBU2, "PBU2",
2104 SPR_NOACCESS, SPR_NOACCESS,
2105 &spr_read_403_pbr, &spr_write_403_pbr,
2106 0x00000000);
2107 }
2108
2109 static void gen_spr_403_mmu (CPUPPCState *env)
2110 {
2111 /* MMU */
2112 spr_register(env, SPR_40x_PID, "PID",
2113 SPR_NOACCESS, SPR_NOACCESS,
2114 &spr_read_generic, &spr_write_generic,
2115 0x00000000);
2116 spr_register(env, SPR_40x_ZPR, "ZPR",
2117 SPR_NOACCESS, SPR_NOACCESS,
2118 &spr_read_generic, &spr_write_generic,
2119 0x00000000);
2120 }
2121
2122 /* SPR specific to PowerPC compression coprocessor extension */
2123 static void gen_spr_compress (CPUPPCState *env)
2124 {
2125 /* XXX : not implemented */
2126 spr_register(env, SPR_401_SKR, "SKR",
2127 SPR_NOACCESS, SPR_NOACCESS,
2128 &spr_read_generic, &spr_write_generic,
2129 0x00000000);
2130 }
2131
2132 #if defined (TARGET_PPC64)
2133 /* SPR specific to PowerPC 620 */
2134 static void gen_spr_620 (CPUPPCState *env)
2135 {
2136 /* Processor identification */
2137 spr_register(env, SPR_PIR, "PIR",
2138 SPR_NOACCESS, SPR_NOACCESS,
2139 &spr_read_generic, &spr_write_pir,
2140 0x00000000);
2141 spr_register(env, SPR_ASR, "ASR",
2142 SPR_NOACCESS, SPR_NOACCESS,
2143 &spr_read_asr, &spr_write_asr,
2144 0x00000000);
2145 /* Breakpoints */
2146 /* XXX : not implemented */
2147 spr_register(env, SPR_IABR, "IABR",
2148 SPR_NOACCESS, SPR_NOACCESS,
2149 &spr_read_generic, &spr_write_generic,
2150 0x00000000);
2151 /* XXX : not implemented */
2152 spr_register(env, SPR_DABR, "DABR",
2153 SPR_NOACCESS, SPR_NOACCESS,
2154 &spr_read_generic, &spr_write_generic,
2155 0x00000000);
2156 /* XXX : not implemented */
2157 spr_register(env, SPR_SIAR, "SIAR",
2158 SPR_NOACCESS, SPR_NOACCESS,
2159 &spr_read_generic, SPR_NOACCESS,
2160 0x00000000);
2161 /* XXX : not implemented */
2162 spr_register(env, SPR_SDA, "SDA",
2163 SPR_NOACCESS, SPR_NOACCESS,
2164 &spr_read_generic, SPR_NOACCESS,
2165 0x00000000);
2166 /* XXX : not implemented */
2167 spr_register(env, SPR_620_PMC1R, "PMC1",
2168 SPR_NOACCESS, SPR_NOACCESS,
2169 &spr_read_generic, SPR_NOACCESS,
2170 0x00000000);
2171 spr_register(env, SPR_620_PMC1W, "PMC1",
2172 SPR_NOACCESS, SPR_NOACCESS,
2173 SPR_NOACCESS, &spr_write_generic,
2174 0x00000000);
2175 /* XXX : not implemented */
2176 spr_register(env, SPR_620_PMC2R, "PMC2",
2177 SPR_NOACCESS, SPR_NOACCESS,
2178 &spr_read_generic, SPR_NOACCESS,
2179 0x00000000);
2180 spr_register(env, SPR_620_PMC2W, "PMC2",
2181 SPR_NOACCESS, SPR_NOACCESS,
2182 SPR_NOACCESS, &spr_write_generic,
2183 0x00000000);
2184 /* XXX : not implemented */
2185 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2186 SPR_NOACCESS, SPR_NOACCESS,
2187 &spr_read_generic, SPR_NOACCESS,
2188 0x00000000);
2189 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 SPR_NOACCESS, &spr_write_generic,
2192 0x00000000);
2193 /* External access control */
2194 /* XXX : not implemented */
2195 spr_register(env, SPR_EAR, "EAR",
2196 SPR_NOACCESS, SPR_NOACCESS,
2197 &spr_read_generic, &spr_write_generic,
2198 0x00000000);
2199 #if 0 // XXX: check this
2200 /* XXX : not implemented */
2201 spr_register(env, SPR_620_PMR0, "PMR0",
2202 SPR_NOACCESS, SPR_NOACCESS,
2203 &spr_read_generic, &spr_write_generic,
2204 0x00000000);
2205 /* XXX : not implemented */
2206 spr_register(env, SPR_620_PMR1, "PMR1",
2207 SPR_NOACCESS, SPR_NOACCESS,
2208 &spr_read_generic, &spr_write_generic,
2209 0x00000000);
2210 /* XXX : not implemented */
2211 spr_register(env, SPR_620_PMR2, "PMR2",
2212 SPR_NOACCESS, SPR_NOACCESS,
2213 &spr_read_generic, &spr_write_generic,
2214 0x00000000);
2215 /* XXX : not implemented */
2216 spr_register(env, SPR_620_PMR3, "PMR3",
2217 SPR_NOACCESS, SPR_NOACCESS,
2218 &spr_read_generic, &spr_write_generic,
2219 0x00000000);
2220 /* XXX : not implemented */
2221 spr_register(env, SPR_620_PMR4, "PMR4",
2222 SPR_NOACCESS, SPR_NOACCESS,
2223 &spr_read_generic, &spr_write_generic,
2224 0x00000000);
2225 /* XXX : not implemented */
2226 spr_register(env, SPR_620_PMR5, "PMR5",
2227 SPR_NOACCESS, SPR_NOACCESS,
2228 &spr_read_generic, &spr_write_generic,
2229 0x00000000);
2230 /* XXX : not implemented */
2231 spr_register(env, SPR_620_PMR6, "PMR6",
2232 SPR_NOACCESS, SPR_NOACCESS,
2233 &spr_read_generic, &spr_write_generic,
2234 0x00000000);
2235 /* XXX : not implemented */
2236 spr_register(env, SPR_620_PMR7, "PMR7",
2237 SPR_NOACCESS, SPR_NOACCESS,
2238 &spr_read_generic, &spr_write_generic,
2239 0x00000000);
2240 /* XXX : not implemented */
2241 spr_register(env, SPR_620_PMR8, "PMR8",
2242 SPR_NOACCESS, SPR_NOACCESS,
2243 &spr_read_generic, &spr_write_generic,
2244 0x00000000);
2245 /* XXX : not implemented */
2246 spr_register(env, SPR_620_PMR9, "PMR9",
2247 SPR_NOACCESS, SPR_NOACCESS,
2248 &spr_read_generic, &spr_write_generic,
2249 0x00000000);
2250 /* XXX : not implemented */
2251 spr_register(env, SPR_620_PMRA, "PMR10",
2252 SPR_NOACCESS, SPR_NOACCESS,
2253 &spr_read_generic, &spr_write_generic,
2254 0x00000000);
2255 /* XXX : not implemented */
2256 spr_register(env, SPR_620_PMRB, "PMR11",
2257 SPR_NOACCESS, SPR_NOACCESS,
2258 &spr_read_generic, &spr_write_generic,
2259 0x00000000);
2260 /* XXX : not implemented */
2261 spr_register(env, SPR_620_PMRC, "PMR12",
2262 SPR_NOACCESS, SPR_NOACCESS,
2263 &spr_read_generic, &spr_write_generic,
2264 0x00000000);
2265 /* XXX : not implemented */
2266 spr_register(env, SPR_620_PMRD, "PMR13",
2267 SPR_NOACCESS, SPR_NOACCESS,
2268 &spr_read_generic, &spr_write_generic,
2269 0x00000000);
2270 /* XXX : not implemented */
2271 spr_register(env, SPR_620_PMRE, "PMR14",
2272 SPR_NOACCESS, SPR_NOACCESS,
2273 &spr_read_generic, &spr_write_generic,
2274 0x00000000);
2275 /* XXX : not implemented */
2276 spr_register(env, SPR_620_PMRF, "PMR15",
2277 SPR_NOACCESS, SPR_NOACCESS,
2278 &spr_read_generic, &spr_write_generic,
2279 0x00000000);
2280 #endif
2281 /* XXX : not implemented */
2282 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2283 SPR_NOACCESS, SPR_NOACCESS,
2284 &spr_read_generic, &spr_write_generic,
2285 0x00000000);
2286 /* XXX : not implemented */
2287 spr_register(env, SPR_620_L2CR, "L2CR",
2288 SPR_NOACCESS, SPR_NOACCESS,
2289 &spr_read_generic, &spr_write_generic,
2290 0x00000000);
2291 /* XXX : not implemented */
2292 spr_register(env, SPR_620_L2SR, "L2SR",
2293 SPR_NOACCESS, SPR_NOACCESS,
2294 &spr_read_generic, &spr_write_generic,
2295 0x00000000);
2296 }
2297 #endif /* defined (TARGET_PPC64) */
2298
2299 static void gen_spr_5xx_8xx (CPUPPCState *env)
2300 {
2301 /* Exception processing */
2302 spr_register(env, SPR_DSISR, "DSISR",
2303 SPR_NOACCESS, SPR_NOACCESS,
2304 &spr_read_generic, &spr_write_generic,
2305 0x00000000);
2306 spr_register(env, SPR_DAR, "DAR",
2307 SPR_NOACCESS, SPR_NOACCESS,
2308 &spr_read_generic, &spr_write_generic,
2309 0x00000000);
2310 /* Timer */
2311 spr_register(env, SPR_DECR, "DECR",
2312 SPR_NOACCESS, SPR_NOACCESS,
2313 &spr_read_decr, &spr_write_decr,
2314 0x00000000);
2315 /* XXX : not implemented */
2316 spr_register(env, SPR_MPC_EIE, "EIE",
2317 SPR_NOACCESS, SPR_NOACCESS,
2318 &spr_read_generic, &spr_write_generic,
2319 0x00000000);
2320 /* XXX : not implemented */
2321 spr_register(env, SPR_MPC_EID, "EID",
2322 SPR_NOACCESS, SPR_NOACCESS,
2323 &spr_read_generic, &spr_write_generic,
2324 0x00000000);
2325 /* XXX : not implemented */
2326 spr_register(env, SPR_MPC_NRI, "NRI",
2327 SPR_NOACCESS, SPR_NOACCESS,
2328 &spr_read_generic, &spr_write_generic,
2329 0x00000000);
2330 /* XXX : not implemented */
2331 spr_register(env, SPR_MPC_CMPA, "CMPA",
2332 SPR_NOACCESS, SPR_NOACCESS,
2333 &spr_read_generic, &spr_write_generic,
2334 0x00000000);
2335 /* XXX : not implemented */
2336 spr_register(env, SPR_MPC_CMPB, "CMPB",
2337 SPR_NOACCESS, SPR_NOACCESS,
2338 &spr_read_generic, &spr_write_generic,
2339 0x00000000);
2340 /* XXX : not implemented */
2341 spr_register(env, SPR_MPC_CMPC, "CMPC",
2342 SPR_NOACCESS, SPR_NOACCESS,
2343 &spr_read_generic, &spr_write_generic,
2344 0x00000000);
2345 /* XXX : not implemented */
2346 spr_register(env, SPR_MPC_CMPD, "CMPD",
2347 SPR_NOACCESS, SPR_NOACCESS,
2348 &spr_read_generic, &spr_write_generic,
2349 0x00000000);
2350 /* XXX : not implemented */
2351 spr_register(env, SPR_MPC_ECR, "ECR",
2352 SPR_NOACCESS, SPR_NOACCESS,
2353 &spr_read_generic, &spr_write_generic,
2354 0x00000000);
2355 /* XXX : not implemented */
2356 spr_register(env, SPR_MPC_DER, "DER",
2357 SPR_NOACCESS, SPR_NOACCESS,
2358 &spr_read_generic, &spr_write_generic,
2359 0x00000000);
2360 /* XXX : not implemented */
2361 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2362 SPR_NOACCESS, SPR_NOACCESS,
2363 &spr_read_generic, &spr_write_generic,
2364 0x00000000);
2365 /* XXX : not implemented */
2366 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2367 SPR_NOACCESS, SPR_NOACCESS,
2368 &spr_read_generic, &spr_write_generic,
2369 0x00000000);
2370 /* XXX : not implemented */
2371 spr_register(env, SPR_MPC_CMPE, "CMPE",
2372 SPR_NOACCESS, SPR_NOACCESS,
2373 &spr_read_generic, &spr_write_generic,
2374 0x00000000);
2375 /* XXX : not implemented */
2376 spr_register(env, SPR_MPC_CMPF, "CMPF",
2377 SPR_NOACCESS, SPR_NOACCESS,
2378 &spr_read_generic, &spr_write_generic,
2379 0x00000000);
2380 /* XXX : not implemented */
2381 spr_register(env, SPR_MPC_CMPG, "CMPG",
2382 SPR_NOACCESS, SPR_NOACCESS,
2383 &spr_read_generic, &spr_write_generic,
2384 0x00000000);
2385 /* XXX : not implemented */
2386 spr_register(env, SPR_MPC_CMPH, "CMPH",
2387 SPR_NOACCESS, SPR_NOACCESS,
2388 &spr_read_generic, &spr_write_generic,
2389 0x00000000);
2390 /* XXX : not implemented */
2391 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2392 SPR_NOACCESS, SPR_NOACCESS,
2393 &spr_read_generic, &spr_write_generic,
2394 0x00000000);
2395 /* XXX : not implemented */
2396 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2397 SPR_NOACCESS, SPR_NOACCESS,
2398 &spr_read_generic, &spr_write_generic,
2399 0x00000000);
2400 /* XXX : not implemented */
2401 spr_register(env, SPR_MPC_BAR, "BAR",
2402 SPR_NOACCESS, SPR_NOACCESS,
2403 &spr_read_generic, &spr_write_generic,
2404 0x00000000);
2405 /* XXX : not implemented */
2406 spr_register(env, SPR_MPC_DPDR, "DPDR",
2407 SPR_NOACCESS, SPR_NOACCESS,
2408 &spr_read_generic, &spr_write_generic,
2409 0x00000000);
2410 /* XXX : not implemented */
2411 spr_register(env, SPR_MPC_IMMR, "IMMR",
2412 SPR_NOACCESS, SPR_NOACCESS,
2413 &spr_read_generic, &spr_write_generic,
2414 0x00000000);
2415 }
2416
2417 static void gen_spr_5xx (CPUPPCState *env)
2418 {
2419 /* XXX : not implemented */
2420 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2421 SPR_NOACCESS, SPR_NOACCESS,
2422 &spr_read_generic, &spr_write_generic,
2423 0x00000000);
2424 /* XXX : not implemented */
2425 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2426 SPR_NOACCESS, SPR_NOACCESS,
2427 &spr_read_generic, &spr_write_generic,
2428 0x00000000);
2429 /* XXX : not implemented */
2430 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2431 SPR_NOACCESS, SPR_NOACCESS,
2432 &spr_read_generic, &spr_write_generic,
2433 0x00000000);
2434 /* XXX : not implemented */
2435 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2436 SPR_NOACCESS, SPR_NOACCESS,
2437 &spr_read_generic, &spr_write_generic,
2438 0x00000000);
2439 /* XXX : not implemented */
2440 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2441 SPR_NOACCESS, SPR_NOACCESS,
2442 &spr_read_generic, &spr_write_generic,
2443 0x00000000);
2444 /* XXX : not implemented */
2445 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2446 SPR_NOACCESS, SPR_NOACCESS,
2447 &spr_read_generic, &spr_write_generic,
2448 0x00000000);
2449 /* XXX : not implemented */
2450 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2451 SPR_NOACCESS, SPR_NOACCESS,
2452 &spr_read_generic, &spr_write_generic,
2453 0x00000000);
2454 /* XXX : not implemented */
2455 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2456 SPR_NOACCESS, SPR_NOACCESS,
2457 &spr_read_generic, &spr_write_generic,
2458 0x00000000);
2459 /* XXX : not implemented */
2460 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2461 SPR_NOACCESS, SPR_NOACCESS,
2462 &spr_read_generic, &spr_write_generic,
2463 0x00000000);
2464 /* XXX : not implemented */
2465 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2466 SPR_NOACCESS, SPR_NOACCESS,
2467 &spr_read_generic, &spr_write_generic,
2468 0x00000000);
2469 /* XXX : not implemented */
2470 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2471 SPR_NOACCESS, SPR_NOACCESS,
2472 &spr_read_generic, &spr_write_generic,
2473 0x00000000);
2474 /* XXX : not implemented */
2475 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2476 SPR_NOACCESS, SPR_NOACCESS,
2477 &spr_read_generic, &spr_write_generic,
2478 0x00000000);
2479 /* XXX : not implemented */
2480 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2481 SPR_NOACCESS, SPR_NOACCESS,
2482 &spr_read_generic, &spr_write_generic,
2483 0x00000000);
2484 /* XXX : not implemented */
2485 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2486 SPR_NOACCESS, SPR_NOACCESS,
2487 &spr_read_generic, &spr_write_generic,
2488 0x00000000);
2489 /* XXX : not implemented */
2490 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2491 SPR_NOACCESS, SPR_NOACCESS,
2492 &spr_read_generic, &spr_write_generic,
2493 0x00000000);
2494 /* XXX : not implemented */
2495 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2496 SPR_NOACCESS, SPR_NOACCESS,
2497 &spr_read_generic, &spr_write_generic,
2498 0x00000000);
2499 /* XXX : not implemented */
2500 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2501 SPR_NOACCESS, SPR_NOACCESS,
2502 &spr_read_generic, &spr_write_generic,
2503 0x00000000);
2504 /* XXX : not implemented */
2505 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2506 SPR_NOACCESS, SPR_NOACCESS,
2507 &spr_read_generic, &spr_write_generic,
2508 0x00000000);
2509 /* XXX : not implemented */
2510 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2511 SPR_NOACCESS, SPR_NOACCESS,
2512 &spr_read_generic, &spr_write_generic,
2513 0x00000000);
2514 /* XXX : not implemented */
2515 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2516 SPR_NOACCESS, SPR_NOACCESS,
2517 &spr_read_generic, &spr_write_generic,
2518 0x00000000);
2519 /* XXX : not implemented */
2520 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2521 SPR_NOACCESS, SPR_NOACCESS,
2522 &spr_read_generic, &spr_write_generic,
2523 0x00000000);
2524 }
2525
2526 static void gen_spr_8xx (CPUPPCState *env)
2527 {
2528 /* XXX : not implemented */
2529 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2530 SPR_NOACCESS, SPR_NOACCESS,
2531 &spr_read_generic, &spr_write_generic,
2532 0x00000000);
2533 /* XXX : not implemented */
2534 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2535 SPR_NOACCESS, SPR_NOACCESS,
2536 &spr_read_generic, &spr_write_generic,
2537 0x00000000);
2538 /* XXX : not implemented */
2539 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2540 SPR_NOACCESS, SPR_NOACCESS,
2541 &spr_read_generic, &spr_write_generic,
2542 0x00000000);
2543 /* XXX : not implemented */
2544 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2545 SPR_NOACCESS, SPR_NOACCESS,
2546 &spr_read_generic, &spr_write_generic,
2547 0x00000000);
2548 /* XXX : not implemented */
2549 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2550 SPR_NOACCESS, SPR_NOACCESS,
2551 &spr_read_generic, &spr_write_generic,
2552 0x00000000);
2553 /* XXX : not implemented */
2554 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2555 SPR_NOACCESS, SPR_NOACCESS,
2556 &spr_read_generic, &spr_write_generic,
2557 0x00000000);
2558 /* XXX : not implemented */
2559 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2560 SPR_NOACCESS, SPR_NOACCESS,
2561 &spr_read_generic, &spr_write_generic,
2562 0x00000000);
2563 /* XXX : not implemented */
2564 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2565 SPR_NOACCESS, SPR_NOACCESS,
2566 &spr_read_generic, &spr_write_generic,
2567 0x00000000);
2568 /* XXX : not implemented */
2569 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2570 SPR_NOACCESS, SPR_NOACCESS,
2571 &spr_read_generic, &spr_write_generic,
2572 0x00000000);
2573 /* XXX : not implemented */
2574 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2575 SPR_NOACCESS, SPR_NOACCESS,
2576 &spr_read_generic, &spr_write_generic,
2577 0x00000000);
2578 /* XXX : not implemented */
2579 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2580 SPR_NOACCESS, SPR_NOACCESS,
2581 &spr_read_generic, &spr_write_generic,
2582 0x00000000);
2583 /* XXX : not implemented */
2584 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2585 SPR_NOACCESS, SPR_NOACCESS,
2586 &spr_read_generic, &spr_write_generic,
2587 0x00000000);
2588 /* XXX : not implemented */
2589 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2590 SPR_NOACCESS, SPR_NOACCESS,
2591 &spr_read_generic, &spr_write_generic,
2592 0x00000000);
2593 /* XXX : not implemented */
2594 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2595 SPR_NOACCESS, SPR_NOACCESS,
2596 &spr_read_generic, &spr_write_generic,
2597 0x00000000);
2598 /* XXX : not implemented */
2599 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2600 SPR_NOACCESS, SPR_NOACCESS,
2601 &spr_read_generic, &spr_write_generic,
2602 0x00000000);
2603 /* XXX : not implemented */
2604 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2605 SPR_NOACCESS, SPR_NOACCESS,
2606 &spr_read_generic, &spr_write_generic,
2607 0x00000000);
2608 /* XXX : not implemented */
2609 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2610 SPR_NOACCESS, SPR_NOACCESS,
2611 &spr_read_generic, &spr_write_generic,
2612 0x00000000);
2613 /* XXX : not implemented */
2614 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2615 SPR_NOACCESS, SPR_NOACCESS,
2616 &spr_read_generic, &spr_write_generic,
2617 0x00000000);
2618 /* XXX : not implemented */
2619 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2620 SPR_NOACCESS, SPR_NOACCESS,
2621 &spr_read_generic, &spr_write_generic,
2622 0x00000000);
2623 /* XXX : not implemented */
2624 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2625 SPR_NOACCESS, SPR_NOACCESS,
2626 &spr_read_generic, &spr_write_generic,
2627 0x00000000);
2628 /* XXX : not implemented */
2629 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2630 SPR_NOACCESS, SPR_NOACCESS,
2631 &spr_read_generic, &spr_write_generic,
2632 0x00000000);
2633 /* XXX : not implemented */
2634 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2635 SPR_NOACCESS, SPR_NOACCESS,
2636 &spr_read_generic, &spr_write_generic,
2637 0x00000000);
2638 /* XXX : not implemented */
2639 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2640 SPR_NOACCESS, SPR_NOACCESS,
2641 &spr_read_generic, &spr_write_generic,
2642 0x00000000);
2643 /* XXX : not implemented */
2644 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2645 SPR_NOACCESS, SPR_NOACCESS,
2646 &spr_read_generic, &spr_write_generic,
2647 0x00000000);
2648 /* XXX : not implemented */
2649 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2650 SPR_NOACCESS, SPR_NOACCESS,
2651 &spr_read_generic, &spr_write_generic,
2652 0x00000000);
2653 }
2654
2655 // XXX: TODO
2656 /*
2657 * AMR => SPR 29 (Power 2.04)
2658 * CTRL => SPR 136 (Power 2.04)
2659 * CTRL => SPR 152 (Power 2.04)
2660 * SCOMC => SPR 276 (64 bits ?)
2661 * SCOMD => SPR 277 (64 bits ?)
2662 * TBU40 => SPR 286 (Power 2.04 hypv)
2663 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2664 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2665 * HDSISR => SPR 306 (Power 2.04 hypv)
2666 * HDAR => SPR 307 (Power 2.04 hypv)
2667 * PURR => SPR 309 (Power 2.04 hypv)
2668 * HDEC => SPR 310 (Power 2.04 hypv)
2669 * HIOR => SPR 311 (hypv)
2670 * RMOR => SPR 312 (970)
2671 * HRMOR => SPR 313 (Power 2.04 hypv)
2672 * HSRR0 => SPR 314 (Power 2.04 hypv)
2673 * HSRR1 => SPR 315 (Power 2.04 hypv)
2674 * LPCR => SPR 316 (970)
2675 * LPIDR => SPR 317 (970)
2676 * EPR => SPR 702 (Power 2.04 emb)
2677 * perf => 768-783 (Power 2.04)
2678 * perf => 784-799 (Power 2.04)
2679 * PPR => SPR 896 (Power 2.04)
2680 * EPLC => SPR 947 (Power 2.04 emb)
2681 * EPSC => SPR 948 (Power 2.04 emb)
2682 * DABRX => 1015 (Power 2.04 hypv)
2683 * FPECR => SPR 1022 (?)
2684 * ... and more (thermal management, performance counters, ...)
2685 */
2686
2687 /*****************************************************************************/
2688 /* Exception vectors models */
2689 static void init_excp_4xx_real (CPUPPCState *env)
2690 {
2691 #if !defined(CONFIG_USER_ONLY)
2692 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2693 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2694 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2695 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2696 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2697 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2698 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2699 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2700 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2701 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2702 env->hreset_excp_prefix = 0x00000000UL;
2703 env->ivor_mask = 0x0000FFF0UL;
2704 env->ivpr_mask = 0xFFFF0000UL;
2705 /* Hardware reset vector */
2706 env->hreset_vector = 0xFFFFFFFCUL;
2707 #endif
2708 }
2709
2710 static void init_excp_4xx_softmmu (CPUPPCState *env)
2711 {
2712 #if !defined(CONFIG_USER_ONLY)
2713 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2714 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2715 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2716 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2717 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2718 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2719 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2720 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2721 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2722 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2723 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2724 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2725 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2726 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2727 env->hreset_excp_prefix = 0x00000000UL;
2728 env->ivor_mask = 0x0000FFF0UL;
2729 env->ivpr_mask = 0xFFFF0000UL;
2730 /* Hardware reset vector */
2731 env->hreset_vector = 0xFFFFFFFCUL;
2732 #endif
2733 }
2734
2735 static void init_excp_MPC5xx (CPUPPCState *env)
2736 {
2737 #if !defined(CONFIG_USER_ONLY)
2738 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2739 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2740 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2741 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2742 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2743 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2744 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2745 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2746 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2747 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2748 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2749 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2750 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2751 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2752 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2753 env->hreset_excp_prefix = 0x00000000UL;
2754 env->ivor_mask = 0x0000FFF0UL;
2755 env->ivpr_mask = 0xFFFF0000UL;
2756 /* Hardware reset vector */
2757 env->hreset_vector = 0xFFFFFFFCUL;
2758 #endif
2759 }
2760
2761 static void init_excp_MPC8xx (CPUPPCState *env)
2762 {
2763 #if !defined(CONFIG_USER_ONLY)
2764 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2765 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2766 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2767 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2768 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2769 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2770 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2771 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2772 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2773 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2774 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2775 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2776 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2777 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2778 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2779 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2780 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2781 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2782 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2783 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2784 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2785 env->hreset_excp_prefix = 0x00000000UL;
2786 env->ivor_mask = 0x0000FFF0UL;
2787 env->ivpr_mask = 0xFFFF0000UL;
2788 /* Hardware reset vector */
2789 env->hreset_vector = 0xFFFFFFFCUL;
2790 #endif
2791 }
2792
2793 static void init_excp_G2 (CPUPPCState *env)
2794 {
2795 #if !defined(CONFIG_USER_ONLY)
2796 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2797 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2798 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2799 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2800 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2801 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2802 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2803 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2804 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2805 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2806 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2807 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2808 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2809 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2810 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2811 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2812 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2813 env->hreset_excp_prefix = 0x00000000UL;
2814 /* Hardware reset vector */
2815 env->hreset_vector = 0xFFFFFFFCUL;
2816 #endif
2817 }
2818
2819 static void init_excp_e200 (CPUPPCState *env)
2820 {
2821 #if !defined(CONFIG_USER_ONLY)
2822 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2823 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2824 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2825 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2826 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2827 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2828 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2829 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2830 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2831 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2832 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2833 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2834 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2835 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2836 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2837 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2838 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2839 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2840 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2841 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2842 env->hreset_excp_prefix = 0x00000000UL;
2843 env->ivor_mask = 0x0000FFF7UL;
2844 env->ivpr_mask = 0xFFFF0000UL;
2845 /* Hardware reset vector */
2846 env->hreset_vector = 0xFFFFFFFCUL;
2847 #endif
2848 }
2849
2850 static void init_excp_BookE (CPUPPCState *env)
2851 {
2852 #if !defined(CONFIG_USER_ONLY)
2853 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2854 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2855 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2856 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2857 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2858 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2859 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2860 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2861 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2862 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2863 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2864 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2865 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2866 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2867 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2868 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2869 env->hreset_excp_prefix = 0x00000000UL;
2870 env->ivor_mask = 0x0000FFE0UL;
2871 env->ivpr_mask = 0xFFFF0000UL;
2872 /* Hardware reset vector */
2873 env->hreset_vector = 0xFFFFFFFCUL;
2874 #endif
2875 }
2876
2877 static void init_excp_601 (CPUPPCState *env)
2878 {
2879 #if !defined(CONFIG_USER_ONLY)
2880 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2881 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2882 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2883 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2884 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2885 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2886 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2887 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2888 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2889 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2890 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2891 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2892 env->hreset_excp_prefix = 0xFFF00000UL;
2893 /* Hardware reset vector */
2894 env->hreset_vector = 0x00000100UL;
2895 #endif
2896 }
2897
2898 static void init_excp_602 (CPUPPCState *env)
2899 {
2900 #if !defined(CONFIG_USER_ONLY)
2901 /* XXX: exception prefix has a special behavior on 602 */
2902 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2903 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2904 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2905 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2906 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2907 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2908 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2909 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2910 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2911 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2912 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2913 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2914 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2915 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2916 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2917 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2918 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2919 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2920 env->hreset_excp_prefix = 0xFFF00000UL;
2921 /* Hardware reset vector */
2922 env->hreset_vector = 0xFFFFFFFCUL;
2923 #endif
2924 }
2925
2926 static void init_excp_603 (CPUPPCState *env)
2927 {
2928 #if !defined(CONFIG_USER_ONLY)
2929 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2930 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2931 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2932 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2933 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2934 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2935 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2936 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2937 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2938 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2939 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2940 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2941 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2942 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2943 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2944 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2945 env->hreset_excp_prefix = 0x00000000UL;
2946 /* Hardware reset vector */
2947 env->hreset_vector = 0xFFFFFFFCUL;
2948 #endif
2949 }
2950
2951 static void init_excp_604 (CPUPPCState *env)
2952 {
2953 #if !defined(CONFIG_USER_ONLY)
2954 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2955 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2956 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2957 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2958 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2959 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2960 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2961 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2962 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2963 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2964 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2965 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2966 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2967 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2968 env->hreset_excp_prefix = 0xFFF00000UL;
2969 /* Hardware reset vector */
2970 env->hreset_vector = 0x00000100UL;
2971 #endif
2972 }
2973
2974 #if defined(TARGET_PPC64)
2975 static void init_excp_620 (CPUPPCState *env)
2976 {
2977 #if !defined(CONFIG_USER_ONLY)
2978 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2979 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2980 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2981 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2982 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2983 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2984 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2985 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2986 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2987 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2988 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2989 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2990 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2991 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2992 env->hreset_excp_prefix = 0xFFF00000UL;
2993 /* Hardware reset vector */
2994 env->hreset_vector = 0x0000000000000100ULL;
2995 #endif
2996 }
2997 #endif /* defined(TARGET_PPC64) */
2998
2999 static void init_excp_7x0 (CPUPPCState *env)
3000 {
3001 #if !defined(CONFIG_USER_ONLY)
3002 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3003 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3004 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3005 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3006 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3007 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3008 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3009 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3010 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3011 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3012 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3013 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3014 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3015 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3016 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3017 env->hreset_excp_prefix = 0x00000000UL;
3018 /* Hardware reset vector */
3019 env->hreset_vector = 0xFFFFFFFCUL;
3020 #endif
3021 }
3022
3023 static void init_excp_750cl (CPUPPCState *env)
3024 {
3025 #if !defined(CONFIG_USER_ONLY)
3026 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3027 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3028 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3029 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3030 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3031 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3032 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3033 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3034 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3035 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3036 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3037 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3038 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3039 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3040 env->hreset_excp_prefix = 0x00000000UL;
3041 /* Hardware reset vector */
3042 env->hreset_vector = 0xFFFFFFFCUL;
3043 #endif
3044 }
3045
3046 static void init_excp_750cx (CPUPPCState *env)
3047 {
3048 #if !defined(CONFIG_USER_ONLY)
3049 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3050 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3051 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3052 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3053 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3054 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3055 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3056 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3057 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3058 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3059 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3060 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3061 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3062 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3063 env->hreset_excp_prefix = 0x00000000UL;
3064 /* Hardware reset vector */
3065 env->hreset_vector = 0xFFFFFFFCUL;
3066 #endif
3067 }
3068
3069 /* XXX: Check if this is correct */
3070 static void init_excp_7x5 (CPUPPCState *env)
3071 {
3072 #if !defined(CONFIG_USER_ONLY)
3073 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3074 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3075 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3076 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3077 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3078 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3079 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3080 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3081 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3082 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3083 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3084 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3085 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3086 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3087 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3088 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3089 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3090 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3091 env->hreset_excp_prefix = 0x00000000UL;
3092 /* Hardware reset vector */
3093 env->hreset_vector = 0xFFFFFFFCUL;
3094 #endif
3095 }
3096
3097 static void init_excp_7400 (CPUPPCState *env)
3098 {
3099 #if !defined(CONFIG_USER_ONLY)
3100 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3101 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3102 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3103 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3104 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3105 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3106 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3107 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3108 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3109 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3110 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3111 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3112 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3113 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3114 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3115 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3116 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3117 env->hreset_excp_prefix = 0x00000000UL;
3118 /* Hardware reset vector */
3119 env->hreset_vector = 0xFFFFFFFCUL;
3120 #endif
3121 }
3122
3123 static void init_excp_7450 (CPUPPCState *env)
3124 {
3125 #if !defined(CONFIG_USER_ONLY)
3126 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3127 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3128 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3129 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3130 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3131 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3132 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3133 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3134 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3135 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3136 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3137 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3138 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3139 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3140 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3141 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3142 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3143 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3144 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3145 env->hreset_excp_prefix = 0x00000000UL;
3146 /* Hardware reset vector */
3147 env->hreset_vector = 0xFFFFFFFCUL;
3148 #endif
3149 }
3150
3151 #if defined (TARGET_PPC64)
3152 static void init_excp_970 (CPUPPCState *env)
3153 {
3154 #if !defined(CONFIG_USER_ONLY)
3155 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3156 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3157 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3158 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3159 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3160 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3161 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3162 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3163 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3164 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3165 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3166 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3167 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3168 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3169 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3170 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3171 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3172 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3173 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3174 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3175 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
3176 /* Hardware reset vector */
3177 env->hreset_vector = 0x0000000000000100ULL;
3178 #endif
3179 }
3180
3181 static void init_excp_POWER7 (CPUPPCState *env)
3182 {
3183 #if !defined(CONFIG_USER_ONLY)
3184 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3185 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3186 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3187 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3188 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3189 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3190 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3191 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3192 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3193 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3194 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3195 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3196 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3197 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3198 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3199 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3200 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3201 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3202 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3203 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3204 env->hreset_excp_prefix = 0;
3205 /* Hardware reset vector */
3206 env->hreset_vector = 0x0000000000000100ULL;
3207 #endif
3208 }
3209 #endif
3210
3211 /*****************************************************************************/
3212 /* Power management enable checks */
3213 static int check_pow_none (CPUPPCState *env)
3214 {
3215 return 0;
3216 }
3217
3218 static int check_pow_nocheck (CPUPPCState *env)
3219 {
3220 return 1;
3221 }
3222
3223 static int check_pow_hid0 (CPUPPCState *env)
3224 {
3225 if (env->spr[SPR_HID0] & 0x00E00000)
3226 return 1;
3227
3228 return 0;
3229 }
3230
3231 static int check_pow_hid0_74xx (CPUPPCState *env)
3232 {
3233 if (env->spr[SPR_HID0] & 0x00600000)
3234 return 1;
3235
3236 return 0;
3237 }
3238
3239 /*****************************************************************************/
3240 /* PowerPC implementations definitions */
3241
3242 /* PowerPC 401 */
3243 #define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3244 PPC_WRTEE | PPC_DCR | \
3245 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3246 PPC_CACHE_DCBZ | \
3247 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3248 PPC_4xx_COMMON | PPC_40x_EXCP)
3249 #define POWERPC_INSNS2_401 (PPC_NONE)
3250 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
3251 #define POWERPC_MMU_401 (POWERPC_MMU_REAL)
3252 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3253 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
3254 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
3255 #define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3256 POWERPC_FLAG_BUS_CLK)
3257 #define check_pow_401 check_pow_nocheck
3258
3259 static void init_proc_401 (CPUPPCState *env)
3260 {
3261 gen_spr_40x(env);
3262 gen_spr_401_403(env);
3263 gen_spr_401(env);
3264 init_excp_4xx_real(env);
3265 env->dcache_line_size = 32;
3266 env->icache_line_size = 32;
3267 /* Allocate hardware IRQ controller */
3268 ppc40x_irq_init(env);
3269 }
3270
3271 /* PowerPC 401x2 */
3272 #define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3273 PPC_DCR | PPC_WRTEE | \
3274 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3275 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3276 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3277 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3278 PPC_4xx_COMMON | PPC_40x_EXCP)
3279 #define POWERPC_INSNS2_401x2 (PPC_NONE)
3280 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3281 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3282 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3283 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
3284 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
3285 #define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3286 POWERPC_FLAG_BUS_CLK)
3287 #define check_pow_401x2 check_pow_nocheck
3288
3289 static void init_proc_401x2 (CPUPPCState *env)
3290 {
3291 gen_spr_40x(env);
3292 gen_spr_401_403(env);
3293 gen_spr_401x2(env);
3294 gen_spr_compress(env);
3295 /* Memory management */
3296 #if !defined(CONFIG_USER_ONLY)
3297 env->nb_tlb = 64;
3298 env->nb_ways = 1;
3299 env->id_tlbs = 0;
3300 env->tlb_type = TLB_EMB;
3301 #endif
3302 init_excp_4xx_softmmu(env);
3303 env->dcache_line_size = 32;
3304 env->icache_line_size = 32;
3305 /* Allocate hardware IRQ controller */
3306 ppc40x_irq_init(env);
3307 }
3308
3309 /* PowerPC 401x3 */
3310 #define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3311 PPC_DCR | PPC_WRTEE | \
3312 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3313 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3314 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3315 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3316 PPC_4xx_COMMON | PPC_40x_EXCP)
3317 #define POWERPC_INSNS2_401x3 (PPC_NONE)
3318 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3319 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3320 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3321 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
3322 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
3323 #define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3324 POWERPC_FLAG_BUS_CLK)
3325 #define check_pow_401x3 check_pow_nocheck
3326
3327 __attribute__ (( unused ))
3328 static void init_proc_401x3 (CPUPPCState *env)
3329 {
3330 gen_spr_40x(env);
3331 gen_spr_401_403(env);
3332 gen_spr_401(env);
3333 gen_spr_401x2(env);
3334 gen_spr_compress(env);
3335 init_excp_4xx_softmmu(env);
3336 env->dcache_line_size = 32;
3337 env->icache_line_size = 32;
3338 /* Allocate hardware IRQ controller */
3339 ppc40x_irq_init(env);
3340 }
3341
3342 /* IOP480 */
3343 #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3344 PPC_DCR | PPC_WRTEE | \
3345 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3346 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3347 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3348 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3349 PPC_4xx_COMMON | PPC_40x_EXCP)
3350 #define POWERPC_INSNS2_IOP480 (PPC_NONE)
3351 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3352 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3353 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3354 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3355 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
3356 #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3357 POWERPC_FLAG_BUS_CLK)
3358 #define check_pow_IOP480 check_pow_nocheck
3359
3360 static void init_proc_IOP480 (CPUPPCState *env)
3361 {
3362 gen_spr_40x(env);
3363 gen_spr_401_403(env);
3364 gen_spr_401x2(env);
3365 gen_spr_compress(env);
3366 /* Memory management */
3367 #if !defined(CONFIG_USER_ONLY)
3368 env->nb_tlb = 64;
3369 env->nb_ways = 1;
3370 env->id_tlbs = 0;
3371 env->tlb_type = TLB_EMB;
3372 #endif
3373 init_excp_4xx_softmmu(env);
3374 env->dcache_line_size = 32;
3375 env->icache_line_size = 32;
3376 /* Allocate hardware IRQ controller */
3377 ppc40x_irq_init(env);
3378 }
3379
3380 /* PowerPC 403 */
3381 #define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3382 PPC_DCR | PPC_WRTEE | \
3383 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3384 PPC_CACHE_DCBZ | \
3385 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3386 PPC_4xx_COMMON | PPC_40x_EXCP)
3387 #define POWERPC_INSNS2_403 (PPC_NONE)
3388 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
3389 #define POWERPC_MMU_403 (POWERPC_MMU_REAL)
3390 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3391 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
3392 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
3393 #define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3394 POWERPC_FLAG_BUS_CLK)
3395 #define check_pow_403 check_pow_nocheck
3396
3397 static void init_proc_403 (CPUPPCState *env)
3398 {
3399 gen_spr_40x(env);
3400 gen_spr_401_403(env);
3401 gen_spr_403(env);
3402 gen_spr_403_real(env);
3403 init_excp_4xx_real(env);
3404 env->dcache_line_size = 32;
3405 env->icache_line_size = 32;
3406 /* Allocate hardware IRQ controller */
3407 ppc40x_irq_init(env);
3408 }
3409
3410 /* PowerPC 403 GCX */
3411 #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3412 PPC_DCR | PPC_WRTEE | \
3413 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3414 PPC_CACHE_DCBZ | \
3415 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3416 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3417 PPC_4xx_COMMON | PPC_40x_EXCP)
3418 #define POWERPC_INSNS2_403GCX (PPC_NONE)
3419 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3420 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3421 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3422 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3423 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
3424 #define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3425 POWERPC_FLAG_BUS_CLK)
3426 #define check_pow_403GCX check_pow_nocheck
3427
3428 static void init_proc_403GCX (CPUPPCState *env)
3429 {
3430 gen_spr_40x(env);
3431 gen_spr_401_403(env);
3432 gen_spr_403(env);
3433 gen_spr_403_real(env);
3434 gen_spr_403_mmu(env);
3435 /* Bus access control */
3436 /* not emulated, as Qemu never does speculative access */
3437 spr_register(env, SPR_40x_SGR, "SGR",
3438 SPR_NOACCESS, SPR_NOACCESS,
3439 &spr_read_generic, &spr_write_generic,
3440 0xFFFFFFFF);
3441 /* not emulated, as Qemu do not emulate caches */
3442 spr_register(env, SPR_40x_DCWR, "DCWR",
3443 SPR_NOACCESS, SPR_NOACCESS,
3444 &spr_read_generic, &spr_write_generic,
3445 0x00000000);
3446 /* Memory management */
3447 #if !defined(CONFIG_USER_ONLY)
3448 env->nb_tlb = 64;
3449 env->nb_ways = 1;
3450 env->id_tlbs = 0;
3451 env->tlb_type = TLB_EMB;
3452 #endif
3453 init_excp_4xx_softmmu(env);
3454 env->dcache_line_size = 32;
3455 env->icache_line_size = 32;
3456 /* Allocate hardware IRQ controller */
3457 ppc40x_irq_init(env);
3458 }
3459
3460 /* PowerPC 405 */
3461 #define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3462 PPC_DCR | PPC_WRTEE | \
3463 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3464 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3465 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3466 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3467 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3468 #define POWERPC_INSNS2_405 (PPC_NONE)
3469 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
3470 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3471 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3472 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3473 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3474 #define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3475 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3476 #define check_pow_405 check_pow_nocheck
3477
3478 static void init_proc_405 (CPUPPCState *env)
3479 {
3480 /* Time base */
3481 gen_tbl(env);
3482 gen_spr_40x(env);
3483 gen_spr_405(env);
3484 /* Bus access control */
3485 /* not emulated, as Qemu never does speculative access */
3486 spr_register(env, SPR_40x_SGR, "SGR",
3487 SPR_NOACCESS, SPR_NOACCESS,
3488 &spr_read_generic, &spr_write_generic,
3489 0xFFFFFFFF);
3490 /* not emulated, as Qemu do not emulate caches */
3491 spr_register(env, SPR_40x_DCWR, "DCWR",
3492 SPR_NOACCESS, SPR_NOACCESS,
3493 &spr_read_generic, &spr_write_generic,
3494 0x00000000);
3495 /* Memory management */
3496 #if !defined(CONFIG_USER_ONLY)
3497 env->nb_tlb = 64;
3498 env->nb_ways = 1;
3499 env->id_tlbs = 0;
3500 env->tlb_type = TLB_EMB;
3501 #endif
3502 init_excp_4xx_softmmu(env);
3503 env->dcache_line_size = 32;
3504 env->icache_line_size = 32;
3505 /* Allocate hardware IRQ controller */
3506 ppc40x_irq_init(env);
3507 }
3508
3509 /* PowerPC 440 EP */
3510 #define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3511 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3512 PPC_CACHE | PPC_CACHE_ICBI | \
3513 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3514 PPC_MEM_TLBSYNC | PPC_MFTB | \
3515 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3516 PPC_440_SPEC)
3517 #define POWERPC_INSNS2_440EP (PPC_NONE)
3518 #define POWERPC_MSRM_440EP (0x000000000006D630ULL)
3519 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3520 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3521 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3522 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3523 #define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3524 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3525 #define check_pow_440EP check_pow_nocheck
3526
3527 __attribute__ (( unused ))
3528 static void init_proc_440EP (CPUPPCState *env)
3529 {
3530 /* Time base */
3531 gen_tbl(env);
3532 gen_spr_BookE(env, 0x000000000000FFFFULL);
3533 gen_spr_440(env);
3534 gen_spr_usprgh(env);
3535 /* Processor identification */
3536 spr_register(env, SPR_BOOKE_PIR, "PIR",
3537 SPR_NOACCESS, SPR_NOACCESS,
3538 &spr_read_generic, &spr_write_pir,
3539 0x00000000);
3540 /* XXX : not implemented */
3541 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3542 SPR_NOACCESS, SPR_NOACCESS,
3543 &spr_read_generic, &spr_write_generic,
3544 0x00000000);
3545 /* XXX : not implemented */
3546 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3547 SPR_NOACCESS, SPR_NOACCESS,
3548 &spr_read_generic, &spr_write_generic,
3549 0x00000000);
3550 /* XXX : not implemented */
3551 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3552 SPR_NOACCESS, SPR_NOACCESS,
3553 &spr_read_generic, &spr_write_generic,
3554 0x00000000);
3555 /* XXX : not implemented */
3556 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3557 SPR_NOACCESS, SPR_NOACCESS,
3558 &spr_read_generic, &spr_write_generic,
3559 0x00000000);
3560 /* XXX : not implemented */
3561 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3562 SPR_NOACCESS, SPR_NOACCESS,
3563 &spr_read_generic, &spr_write_generic,
3564 0x00000000);
3565 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3566 SPR_NOACCESS, SPR_NOACCESS,
3567 &spr_read_generic, &spr_write_generic,
3568 0x00000000);
3569 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3570 SPR_NOACCESS, SPR_NOACCESS,
3571 &spr_read_generic, &spr_write_generic,
3572 0x00000000);
3573 /* XXX : not implemented */
3574 spr_register(env, SPR_440_CCR1, "CCR1",
3575 SPR_NOACCESS, SPR_NOACCESS,
3576 &spr_read_generic, &spr_write_generic,
3577 0x00000000);
3578 /* Memory management */
3579 #if !defined(CONFIG_USER_ONLY)
3580 env->nb_tlb = 64;
3581 env->nb_ways = 1;
3582 env->id_tlbs = 0;
3583 env->tlb_type = TLB_EMB;
3584 #endif
3585 init_excp_BookE(env);
3586 env->dcache_line_size = 32;
3587 env->icache_line_size = 32;
3588 /* XXX: TODO: allocate internal IRQ controller */
3589 }
3590
3591 /* PowerPC 440 GP */
3592 #define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3593 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3594 PPC_CACHE | PPC_CACHE_ICBI | \
3595 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3596 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \
3597 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3598 PPC_440_SPEC)
3599 #define POWERPC_INSNS2_440GP (PPC_NONE)
3600 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3601 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3602 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3603 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3604 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3605 #define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3606 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3607 #define check_pow_440GP check_pow_nocheck
3608
3609 __attribute__ (( unused ))
3610 static void init_proc_440GP (CPUPPCState *env)
3611 {
3612 /* Time base */
3613 gen_tbl(env);
3614 gen_spr_BookE(env, 0x000000000000FFFFULL);
3615 gen_spr_440(env);
3616 gen_spr_usprgh(env);
3617 /* Processor identification */
3618 spr_register(env, SPR_BOOKE_PIR, "PIR",
3619 SPR_NOACCESS, SPR_NOACCESS,
3620 &spr_read_generic, &spr_write_pir,
3621 0x00000000);
3622 /* XXX : not implemented */
3623 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3624 SPR_NOACCESS, SPR_NOACCESS,
3625 &spr_read_generic, &spr_write_generic,
3626 0x00000000);
3627 /* XXX : not implemented */
3628 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3629 SPR_NOACCESS, SPR_NOACCESS,
3630 &spr_read_generic, &spr_write_generic,
3631 0x00000000);
3632 /* XXX : not implemented */
3633 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3634 SPR_NOACCESS, SPR_NOACCESS,
3635 &spr_read_generic, &spr_write_generic,
3636 0x00000000);
3637 /* XXX : not implemented */
3638 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3639 SPR_NOACCESS, SPR_NOACCESS,
3640 &spr_read_generic, &spr_write_generic,
3641 0x00000000);
3642 /* Memory management */
3643 #if !defined(CONFIG_USER_ONLY)
3644 env->nb_tlb = 64;
3645 env->nb_ways = 1;
3646 env->id_tlbs = 0;
3647 env->tlb_type = TLB_EMB;
3648 #endif
3649 init_excp_BookE(env);
3650 env->dcache_line_size = 32;
3651 env->icache_line_size = 32;
3652 /* XXX: TODO: allocate internal IRQ controller */
3653 }
3654
3655 /* PowerPC 440x4 */
3656 #define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3657 PPC_DCR | PPC_WRTEE | \
3658 PPC_CACHE | PPC_CACHE_ICBI | \
3659 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3660 PPC_MEM_TLBSYNC | PPC_MFTB | \
3661 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3662 PPC_440_SPEC)
3663 #define POWERPC_INSNS2_440x4 (PPC_NONE)
3664 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3665 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3666 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3667 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3668 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3669 #define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3670 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3671 #define check_pow_440x4 check_pow_nocheck
3672
3673 __attribute__ (( unused ))
3674 static void init_proc_440x4 (CPUPPCState *env)
3675 {
3676 /* Time base */
3677 gen_tbl(env);
3678 gen_spr_BookE(env, 0x000000000000FFFFULL);
3679 gen_spr_440(env);
3680 gen_spr_usprgh(env);
3681 /* Processor identification */
3682 spr_register(env, SPR_BOOKE_PIR, "PIR",
3683 SPR_NOACCESS, SPR_NOACCESS,
3684 &spr_read_generic, &spr_write_pir,
3685 0x00000000);
3686 /* XXX : not implemented */
3687 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3688 SPR_NOACCESS, SPR_NOACCESS,
3689 &spr_read_generic, &spr_write_generic,
3690 0x00000000);
3691 /* XXX : not implemented */
3692 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3693 SPR_NOACCESS, SPR_NOACCESS,
3694 &spr_read_generic, &spr_write_generic,
3695 0x00000000);
3696 /* XXX : not implemented */
3697 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3698 SPR_NOACCESS, SPR_NOACCESS,
3699 &spr_read_generic, &spr_write_generic,
3700 0x00000000);
3701 /* XXX : not implemented */
3702 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3703 SPR_NOACCESS, SPR_NOACCESS,
3704 &spr_read_generic, &spr_write_generic,
3705 0x00000000);
3706 /* Memory management */
3707 #if !defined(CONFIG_USER_ONLY)
3708 env->nb_tlb = 64;
3709 env->nb_ways = 1;
3710 env->id_tlbs = 0;
3711 env->tlb_type = TLB_EMB;
3712 #endif
3713 init_excp_BookE(env);
3714 env->dcache_line_size = 32;
3715 env->icache_line_size = 32;
3716 /* XXX: TODO: allocate internal IRQ controller */
3717 }
3718
3719 /* PowerPC 440x5 */
3720 #define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3721 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3722 PPC_CACHE | PPC_CACHE_ICBI | \
3723 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3724 PPC_MEM_TLBSYNC | PPC_MFTB | \
3725 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3726 PPC_440_SPEC)
3727 #define POWERPC_INSNS2_440x5 (PPC_NONE)
3728 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3729 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3730 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3731 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3732 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3733 #define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3734 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3735 #define check_pow_440x5 check_pow_nocheck
3736
3737 static void init_proc_440x5 (CPUPPCState *env)
3738 {
3739 /* Time base */
3740 gen_tbl(env);
3741 gen_spr_BookE(env, 0x000000000000FFFFULL);
3742 gen_spr_440(env);
3743 gen_spr_usprgh(env);
3744 /* Processor identification */
3745 spr_register(env, SPR_BOOKE_PIR, "PIR",
3746 SPR_NOACCESS, SPR_NOACCESS,
3747 &spr_read_generic, &spr_write_pir,
3748 0x00000000);
3749 /* XXX : not implemented */
3750 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3751 SPR_NOACCESS, SPR_NOACCESS,
3752 &spr_read_generic, &spr_write_generic,
3753 0x00000000);
3754 /* XXX : not implemented */
3755 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3756 SPR_NOACCESS, SPR_NOACCESS,
3757 &spr_read_generic, &spr_write_generic,
3758 0x00000000);
3759 /* XXX : not implemented */
3760 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3761 SPR_NOACCESS, SPR_NOACCESS,
3762 &spr_read_generic, &spr_write_generic,
3763 0x00000000);
3764 /* XXX : not implemented */
3765 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3766 SPR_NOACCESS, SPR_NOACCESS,
3767 &spr_read_generic, &spr_write_generic,
3768 0x00000000);
3769 /* XXX : not implemented */
3770 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3771 SPR_NOACCESS, SPR_NOACCESS,
3772 &spr_read_generic, &spr_write_generic,
3773 0x00000000);
3774 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3775 SPR_NOACCESS, SPR_NOACCESS,
3776 &spr_read_generic, &spr_write_generic,
3777 0x00000000);
3778 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3779 SPR_NOACCESS, SPR_NOACCESS,
3780 &spr_read_generic, &spr_write_generic,
3781 0x00000000);
3782 /* XXX : not implemented */
3783 spr_register(env, SPR_440_CCR1, "CCR1",
3784 SPR_NOACCESS, SPR_NOACCESS,
3785 &spr_read_generic, &spr_write_generic,
3786 0x00000000);
3787 /* Memory management */
3788 #if !defined(CONFIG_USER_ONLY)
3789 env->nb_tlb = 64;
3790 env->nb_ways = 1;
3791 env->id_tlbs = 0;
3792 env->tlb_type = TLB_EMB;
3793 #endif
3794 init_excp_BookE(env);
3795 env->dcache_line_size = 32;
3796 env->icache_line_size = 32;
3797 ppc40x_irq_init(env);
3798 }
3799
3800 /* PowerPC 460 (guessed) */
3801 #define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
3802 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3803 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \
3804 PPC_CACHE | PPC_CACHE_ICBI | \
3805 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3806 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3807 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3808 PPC_440_SPEC)
3809 #define POWERPC_INSNS2_460 (PPC_NONE)
3810 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3811 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3812 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3813 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3814 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3815 #define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3816 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3817 #define check_pow_460 check_pow_nocheck
3818
3819 __attribute__ (( unused ))
3820 static void init_proc_460 (CPUPPCState *env)
3821 {
3822 /* Time base */
3823 gen_tbl(env);
3824 gen_spr_BookE(env, 0x000000000000FFFFULL);
3825 gen_spr_440(env);
3826 gen_spr_usprgh(env);
3827 /* Processor identification */
3828 spr_register(env, SPR_BOOKE_PIR, "PIR",
3829 SPR_NOACCESS, SPR_NOACCESS,
3830 &spr_read_generic, &spr_write_pir,
3831 0x00000000);
3832 /* XXX : not implemented */
3833 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3834 SPR_NOACCESS, SPR_NOACCESS,
3835 &spr_read_generic, &spr_write_generic,
3836 0x00000000);
3837 /* XXX : not implemented */
3838 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3839 SPR_NOACCESS, SPR_NOACCESS,
3840 &spr_read_generic, &spr_write_generic,
3841 0x00000000);
3842 /* XXX : not implemented */
3843 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3844 SPR_NOACCESS, SPR_NOACCESS,
3845 &spr_read_generic, &spr_write_generic,
3846 0x00000000);
3847 /* XXX : not implemented */
3848 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3849 SPR_NOACCESS, SPR_NOACCESS,
3850 &spr_read_generic, &spr_write_generic,
3851 0x00000000);
3852 /* XXX : not implemented */
3853 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3854 SPR_NOACCESS, SPR_NOACCESS,
3855 &spr_read_generic, &spr_write_generic,
3856 0x00000000);
3857 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3858 SPR_NOACCESS, SPR_NOACCESS,
3859 &spr_read_generic, &spr_write_generic,
3860 0x00000000);
3861 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3862 SPR_NOACCESS, SPR_NOACCESS,
3863 &spr_read_generic, &spr_write_generic,
3864 0x00000000);
3865 /* XXX : not implemented */
3866 spr_register(env, SPR_440_CCR1, "CCR1",
3867 SPR_NOACCESS, SPR_NOACCESS,
3868 &spr_read_generic, &spr_write_generic,
3869 0x00000000);
3870 /* XXX : not implemented */
3871 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3872 &spr_read_generic, &spr_write_generic,
3873 &spr_read_generic, &spr_write_generic,
3874 0x00000000);
3875 /* Memory management */
3876 #if !defined(CONFIG_USER_ONLY)
3877 env->nb_tlb = 64;
3878 env->nb_ways = 1;
3879 env->id_tlbs = 0;
3880 env->tlb_type = TLB_EMB;
3881 #endif
3882 init_excp_BookE(env);
3883 env->dcache_line_size = 32;
3884 env->icache_line_size = 32;
3885 /* XXX: TODO: allocate internal IRQ controller */
3886 }
3887
3888 /* PowerPC 460F (guessed) */
3889 #define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3890 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3891 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3892 PPC_FLOAT_STFIWX | PPC_MFTB | \
3893 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3894 PPC_WRTEE | PPC_MFAPIDI | \
3895 PPC_CACHE | PPC_CACHE_ICBI | \
3896 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3897 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3898 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3899 PPC_440_SPEC)
3900 #define POWERPC_INSNS2_460F (PPC_NONE)
3901 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3902 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3903 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3904 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3905 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3906 #define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3907 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3908 #define check_pow_460F check_pow_nocheck
3909
3910 __attribute__ (( unused ))
3911 static void init_proc_460F (CPUPPCState *env)
3912 {
3913 /* Time base */
3914 gen_tbl(env);
3915 gen_spr_BookE(env, 0x000000000000FFFFULL);
3916 gen_spr_440(env);
3917 gen_spr_usprgh(env);
3918 /* Processor identification */
3919 spr_register(env, SPR_BOOKE_PIR, "PIR",
3920 SPR_NOACCESS, SPR_NOACCESS,
3921 &spr_read_generic, &spr_write_pir,
3922 0x00000000);
3923 /* XXX : not implemented */
3924 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3925 SPR_NOACCESS, SPR_NOACCESS,
3926 &spr_read_generic, &spr_write_generic,
3927 0x00000000);
3928 /* XXX : not implemented */
3929 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3930 SPR_NOACCESS, SPR_NOACCESS,
3931 &spr_read_generic, &spr_write_generic,
3932 0x00000000);
3933 /* XXX : not implemented */
3934 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3935 SPR_NOACCESS, SPR_NOACCESS,
3936 &spr_read_generic, &spr_write_generic,
3937 0x00000000);
3938 /* XXX : not implemented */
3939 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3940 SPR_NOACCESS, SPR_NOACCESS,
3941 &spr_read_generic, &spr_write_generic,
3942 0x00000000);
3943 /* XXX : not implemented */
3944 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3945 SPR_NOACCESS, SPR_NOACCESS,
3946 &spr_read_generic, &spr_write_generic,
3947 0x00000000);
3948 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3949 SPR_NOACCESS, SPR_NOACCESS,
3950 &spr_read_generic, &spr_write_generic,
3951 0x00000000);
3952 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3953 SPR_NOACCESS, SPR_NOACCESS,
3954 &spr_read_generic, &spr_write_generic,
3955 0x00000000);
3956 /* XXX : not implemented */
3957 spr_register(env, SPR_440_CCR1, "CCR1",
3958 SPR_NOACCESS, SPR_NOACCESS,
3959 &spr_read_generic, &spr_write_generic,
3960 0x00000000);
3961 /* XXX : not implemented */
3962 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3963 &spr_read_generic, &spr_write_generic,
3964 &spr_read_generic, &spr_write_generic,
3965 0x00000000);
3966 /* Memory management */
3967 #if !defined(CONFIG_USER_ONLY)
3968 env->nb_tlb = 64;
3969 env->nb_ways = 1;
3970 env->id_tlbs = 0;
3971 env->tlb_type = TLB_EMB;
3972 #endif
3973 init_excp_BookE(env);
3974 env->dcache_line_size = 32;
3975 env->icache_line_size = 32;
3976 /* XXX: TODO: allocate internal IRQ controller */
3977 }
3978
3979 /* Freescale 5xx cores (aka RCPU) */
3980 #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
3981 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3982 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3983 PPC_MFTB)
3984 #define POWERPC_INSNS2_MPC5xx (PPC_NONE)
3985 #define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
3986 #define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
3987 #define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
3988 #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3989 #define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
3990 #define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3991 POWERPC_FLAG_BUS_CLK)
3992 #define check_pow_MPC5xx check_pow_none
3993
3994 __attribute__ (( unused ))
3995 static void init_proc_MPC5xx (CPUPPCState *env)
3996 {
3997 /* Time base */
3998 gen_tbl(env);
3999 gen_spr_5xx_8xx(env);
4000 gen_spr_5xx(env);
4001 init_excp_MPC5xx(env);
4002 env->dcache_line_size = 32;
4003 env->icache_line_size = 32;
4004 /* XXX: TODO: allocate internal IRQ controller */
4005 }
4006
4007 /* Freescale 8xx cores (aka PowerQUICC) */
4008 #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
4009 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4010 PPC_CACHE_ICBI | PPC_MFTB)
4011 #define POWERPC_INSNS2_MPC8xx (PPC_NONE)
4012 #define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
4013 #define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
4014 #define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
4015 #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
4016 #define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4017 #define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018 POWERPC_FLAG_BUS_CLK)
4019 #define check_pow_MPC8xx check_pow_none
4020
4021 __attribute__ (( unused ))
4022 static void init_proc_MPC8xx (CPUPPCState *env)
4023 {
4024 /* Time base */
4025 gen_tbl(env);
4026 gen_spr_5xx_8xx(env);
4027 gen_spr_8xx(env);
4028 init_excp_MPC8xx(env);
4029 env->dcache_line_size = 32;
4030 env->icache_line_size = 32;
4031 /* XXX: TODO: allocate internal IRQ controller */
4032 }
4033
4034 /* Freescale 82xx cores (aka PowerQUICC-II) */
4035 /* PowerPC G2 */
4036 #define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4037 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4038 PPC_FLOAT_STFIWX | \
4039 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4040 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4041 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4042 PPC_SEGMENT | PPC_EXTERN)
4043 #define POWERPC_INSNS2_G2 (PPC_NONE)
4044 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
4045 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
4046 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
4047 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
4048 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
4049 #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4050 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4051 #define check_pow_G2 check_pow_hid0
4052
4053 static void init_proc_G2 (CPUPPCState *env)
4054 {
4055 gen_spr_ne_601(env);
4056 gen_spr_G2_755(env);
4057 gen_spr_G2(env);
4058 /* Time base */
4059 gen_tbl(env);
4060 /* External access control */
4061 /* XXX : not implemented */
4062 spr_register(env, SPR_EAR, "EAR",
4063 SPR_NOACCESS, SPR_NOACCESS,
4064 &spr_read_generic, &spr_write_generic,
4065 0x00000000);
4066 /* Hardware implementation register */
4067 /* XXX : not implemented */
4068 spr_register(env, SPR_HID0, "HID0",
4069 SPR_NOACCESS, SPR_NOACCESS,
4070 &spr_read_generic, &spr_write_generic,
4071 0x00000000);
4072 /* XXX : not implemented */
4073 spr_register(env, SPR_HID1, "HID1",
4074 SPR_NOACCESS, SPR_NOACCESS,
4075 &spr_read_generic, &spr_write_generic,
4076 0x00000000);
4077 /* XXX : not implemented */
4078 spr_register(env, SPR_HID2, "HID2",
4079 SPR_NOACCESS, SPR_NOACCESS,
4080 &spr_read_generic, &spr_write_generic,
4081 0x00000000);
4082 /* Memory management */
4083 gen_low_BATs(env);
4084 gen_high_BATs(env);
4085 gen_6xx_7xx_soft_tlb(env, 64, 2);
4086 init_excp_G2(env);
4087 env->dcache_line_size = 32;
4088 env->icache_line_size = 32;
4089 /* Allocate hardware IRQ controller */
4090 ppc6xx_irq_init(env);
4091 }
4092
4093 /* PowerPC G2LE */
4094 #define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4095 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4096 PPC_FLOAT_STFIWX | \
4097 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4098 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4099 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4100 PPC_SEGMENT | PPC_EXTERN)
4101 #define POWERPC_INSNS2_G2LE (PPC_NONE)
4102 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
4103 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
4104 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
4105 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
4106 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
4107 #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4108 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4109 #define check_pow_G2LE check_pow_hid0
4110
4111 static void init_proc_G2LE (CPUPPCState *env)
4112 {
4113 gen_spr_ne_601(env);
4114 gen_spr_G2_755(env);
4115 gen_spr_G2(env);
4116 /* Time base */
4117 gen_tbl(env);
4118 /* External access control */
4119 /* XXX : not implemented */
4120 spr_register(env, SPR_EAR, "EAR",
4121 SPR_NOACCESS, SPR_NOACCESS,
4122 &spr_read_generic, &spr_write_generic,
4123 0x00000000);
4124 /* Hardware implementation register */
4125 /* XXX : not implemented */
4126 spr_register(env, SPR_HID0, "HID0",
4127 SPR_NOACCESS, SPR_NOACCESS,
4128 &spr_read_generic, &spr_write_generic,
4129 0x00000000);
4130 /* XXX : not implemented */
4131 spr_register(env, SPR_HID1, "HID1",
4132 SPR_NOACCESS, SPR_NOACCESS,
4133 &spr_read_generic, &spr_write_generic,
4134 0x00000000);
4135 /* XXX : not implemented */
4136 spr_register(env, SPR_HID2, "HID2",
4137 SPR_NOACCESS, SPR_NOACCESS,
4138 &spr_read_generic, &spr_write_generic,
4139 0x00000000);
4140 /* Memory management */
4141 gen_low_BATs(env);
4142 gen_high_BATs(env);
4143 gen_6xx_7xx_soft_tlb(env, 64, 2);
4144 init_excp_G2(env);
4145 env->dcache_line_size = 32;
4146 env->icache_line_size = 32;
4147 /* Allocate hardware IRQ controller */
4148 ppc6xx_irq_init(env);
4149 }
4150
4151 /* e200 core */
4152 /* XXX: unimplemented instructions:
4153 * dcblc
4154 * dcbtlst
4155 * dcbtstls
4156 * icblc
4157 * icbtls
4158 * tlbivax
4159 * all SPE multiply-accumulate instructions
4160 */
4161 #define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
4162 PPC_SPE | PPC_SPE_SINGLE | \
4163 PPC_WRTEE | PPC_RFDI | \
4164 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4165 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4166 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4167 PPC_BOOKE)
4168 #define POWERPC_INSNS2_e200 (PPC_NONE)
4169 #define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
4170 #define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
4171 #define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
4172 #define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
4173 #define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
4174 #define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4175 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4176 POWERPC_FLAG_BUS_CLK)
4177 #define check_pow_e200 check_pow_hid0
4178
4179 __attribute__ (( unused ))
4180 static void init_proc_e200 (CPUPPCState *env)
4181 {
4182 /* Time base */
4183 gen_tbl(env);
4184 gen_spr_BookE(env, 0x000000070000FFFFULL);
4185 /* XXX : not implemented */
4186 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4187 &spr_read_spefscr, &spr_write_spefscr,
4188 &spr_read_spefscr, &spr_write_spefscr,
4189 0x00000000);
4190 /* Memory management */
4191 gen_spr_BookE206(env, 0x0000005D, NULL);
4192 /* XXX : not implemented */
4193 spr_register(env, SPR_HID0, "HID0",
4194 SPR_NOACCESS, SPR_NOACCESS,
4195 &spr_read_generic, &spr_write_generic,
4196 0x00000000);
4197 /* XXX : not implemented */
4198 spr_register(env, SPR_HID1, "HID1",
4199 SPR_NOACCESS, SPR_NOACCESS,
4200 &spr_read_generic, &spr_write_generic,
4201 0x00000000);
4202 /* XXX : not implemented */
4203 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4204 SPR_NOACCESS, SPR_NOACCESS,
4205 &spr_read_generic, &spr_write_generic,
4206 0x00000000);
4207 /* XXX : not implemented */
4208 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4209 SPR_NOACCESS, SPR_NOACCESS,
4210 &spr_read_generic, &spr_write_generic,
4211 0x00000000);
4212 /* XXX : not implemented */
4213 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4214 SPR_NOACCESS, SPR_NOACCESS,
4215 &spr_read_generic, &spr_write_generic,
4216 0x00000000);
4217 /* XXX : not implemented */
4218 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4219 SPR_NOACCESS, SPR_NOACCESS,
4220 &spr_read_generic, &spr_write_generic,
4221 0x00000000);
4222 /* XXX : not implemented */
4223 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4224 SPR_NOACCESS, SPR_NOACCESS,
4225 &spr_read_generic, &spr_write_generic,
4226 0x00000000);
4227 /* XXX : not implemented */
4228 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4229 SPR_NOACCESS, SPR_NOACCESS,
4230 &spr_read_generic, &spr_write_generic,
4231 0x00000000);
4232 /* XXX : not implemented */
4233 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4234 SPR_NOACCESS, SPR_NOACCESS,
4235 &spr_read_generic, &spr_write_generic,
4236 0x00000000);
4237 /* XXX : not implemented */
4238 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4239 SPR_NOACCESS, SPR_NOACCESS,
4240 &spr_read_generic, &spr_write_generic,
4241 0x00000000);
4242 /* XXX : not implemented */
4243 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4244 SPR_NOACCESS, SPR_NOACCESS,
4245 &spr_read_generic, &spr_write_generic,
4246 0x00000000);
4247 /* XXX : not implemented */
4248 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4249 SPR_NOACCESS, SPR_NOACCESS,
4250 &spr_read_generic, &spr_write_generic,
4251 0x00000000);
4252 /* XXX : not implemented */
4253 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4254 SPR_NOACCESS, SPR_NOACCESS,
4255 &spr_read_generic, &spr_write_generic,
4256 0x00000000);
4257 /* XXX : not implemented */
4258 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4259 SPR_NOACCESS, SPR_NOACCESS,
4260 &spr_read_generic, &spr_write_generic,
4261 0x00000000);
4262 /* XXX : not implemented */
4263 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4264 SPR_NOACCESS, SPR_NOACCESS,
4265 &spr_read_generic, &spr_write_generic,
4266 0x00000000); /* TOFIX */
4267 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4268 SPR_NOACCESS, SPR_NOACCESS,
4269 &spr_read_generic, &spr_write_generic,
4270 0x00000000);
4271 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4272 SPR_NOACCESS, SPR_NOACCESS,
4273 &spr_read_generic, &spr_write_generic,
4274 0x00000000);
4275 #if !defined(CONFIG_USER_ONLY)
4276 env->nb_tlb = 64;
4277 env->nb_ways = 1;
4278 env->id_tlbs = 0;
4279 env->tlb_type = TLB_EMB;
4280 #endif
4281 init_excp_e200(env);
4282 env->dcache_line_size = 32;
4283 env->icache_line_size = 32;
4284 /* XXX: TODO: allocate internal IRQ controller */
4285 }
4286
4287 /* e300 core */
4288 #define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4289 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4290 PPC_FLOAT_STFIWX | \
4291 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4292 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4293 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4294 PPC_SEGMENT | PPC_EXTERN)
4295 #define POWERPC_INSNS2_e300 (PPC_NONE)
4296 #define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4297 #define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4298 #define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4299 #define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4300 #define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4301 #define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4302 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4303 #define check_pow_e300 check_pow_hid0
4304
4305 __attribute__ (( unused ))
4306 static void init_proc_e300 (CPUPPCState *env)
4307 {
4308 gen_spr_ne_601(env);
4309 gen_spr_603(env);
4310 /* Time base */
4311 gen_tbl(env);
4312 /* hardware implementation registers */
4313 /* XXX : not implemented */
4314 spr_register(env, SPR_HID0, "HID0",
4315 SPR_NOACCESS, SPR_NOACCESS,
4316 &spr_read_generic, &spr_write_generic,
4317 0x00000000);
4318 /* XXX : not implemented */
4319 spr_register(env, SPR_HID1, "HID1",
4320 SPR_NOACCESS, SPR_NOACCESS,
4321 &spr_read_generic, &spr_write_generic,
4322 0x00000000);
4323 /* XXX : not implemented */
4324 spr_register(env, SPR_HID2, "HID2",
4325 SPR_NOACCESS, SPR_NOACCESS,
4326 &spr_read_generic, &spr_write_generic,
4327 0x00000000);
4328 /* Memory management */
4329 gen_low_BATs(env);
4330 gen_high_BATs(env);
4331 gen_6xx_7xx_soft_tlb(env, 64, 2);
4332 init_excp_603(env);
4333 env->dcache_line_size = 32;
4334 env->icache_line_size = 32;
4335 /* Allocate hardware IRQ controller */
4336 ppc6xx_irq_init(env);
4337 }
4338
4339 /* e500v1 core */
4340 #define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4341 PPC_SPE | PPC_SPE_SINGLE | \
4342 PPC_WRTEE | PPC_RFDI | \
4343 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4344 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4345 PPC_MEM_TLBSYNC | PPC_TLBIVAX)
4346 #define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206)
4347 #define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
4348 #define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
4349 #define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4350 #define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4351 #define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4352 #define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4353 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4354 POWERPC_FLAG_BUS_CLK)
4355 #define check_pow_e500v1 check_pow_hid0
4356 #define init_proc_e500v1 init_proc_e500v1
4357
4358 /* e500v2 core */
4359 #define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4360 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4361 PPC_WRTEE | PPC_RFDI | \
4362 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4363 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4364 PPC_MEM_TLBSYNC | PPC_TLBIVAX)
4365 #define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206)
4366 #define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
4367 #define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
4368 #define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4369 #define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4370 #define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4371 #define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4372 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4373 POWERPC_FLAG_BUS_CLK)
4374 #define check_pow_e500v2 check_pow_hid0
4375 #define init_proc_e500v2 init_proc_e500v2
4376
4377 static void init_proc_e500 (CPUPPCState *env, int version)
4378 {
4379 uint32_t tlbncfg[2];
4380 #if !defined(CONFIG_USER_ONLY)
4381 int i;
4382 #endif
4383
4384 /* Time base */
4385 gen_tbl(env);
4386 /*
4387 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4388 * complain when accessing them.
4389 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4390 */
4391 gen_spr_BookE(env, 0x0000000F0000FFFFULL);
4392 /* Processor identification */
4393 spr_register(env, SPR_BOOKE_PIR, "PIR",
4394 SPR_NOACCESS, SPR_NOACCESS,
4395 &spr_read_generic, &spr_write_pir,
4396 0x00000000);
4397 /* XXX : not implemented */
4398 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4399 &spr_read_spefscr, &spr_write_spefscr,
4400 &spr_read_spefscr, &spr_write_spefscr,
4401 0x00000000);
4402 /* Memory management */
4403 #if !defined(CONFIG_USER_ONLY)
4404 env->nb_pids = 3;
4405 env->nb_ways = 2;
4406 env->id_tlbs = 0;
4407 switch (version) {
4408 case 1:
4409 /* e500v1 */
4410 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4411 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4412 break;
4413 case 2:
4414 /* e500v2 */
4415 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4416 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4417 break;
4418 default:
4419 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4420 }
4421 #endif
4422 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4423 /* XXX : not implemented */
4424 spr_register(env, SPR_HID0, "HID0",
4425 SPR_NOACCESS, SPR_NOACCESS,
4426 &spr_read_generic, &spr_write_generic,
4427 0x00000000);
4428 /* XXX : not implemented */
4429 spr_register(env, SPR_HID1, "HID1",
4430 SPR_NOACCESS, SPR_NOACCESS,
4431 &spr_read_generic, &spr_write_generic,
4432 0x00000000);
4433 /* XXX : not implemented */
4434 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4435 SPR_NOACCESS, SPR_NOACCESS,
4436 &spr_read_generic, &spr_write_generic,
4437 0x00000000);
4438 /* XXX : not implemented */
4439 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4440 SPR_NOACCESS, SPR_NOACCESS,
4441 &spr_read_generic, &spr_write_generic,
4442 0x00000000);
4443 /* XXX : not implemented */
4444 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4445 SPR_NOACCESS, SPR_NOACCESS,
4446 &spr_read_generic, &spr_write_generic,
4447 0x00000000);
4448 /* XXX : not implemented */
4449 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4450 SPR_NOACCESS, SPR_NOACCESS,
4451 &spr_read_generic, &spr_write_generic,
4452 0x00000000);
4453 /* XXX : not implemented */
4454 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4455 SPR_NOACCESS, SPR_NOACCESS,
4456 &spr_read_generic, &spr_write_generic,
4457 0x00000000);
4458 /* XXX : not implemented */
4459 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4460 SPR_NOACCESS, SPR_NOACCESS,
4461 &spr_read_generic, &spr_write_generic,
4462 0x00000000);
4463 /* XXX : not implemented */
4464 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4465 SPR_NOACCESS, SPR_NOACCESS,
4466 &spr_read_generic, &spr_write_generic,
4467 0x00000000);
4468 /* XXX : not implemented */
4469 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4470 SPR_NOACCESS, SPR_NOACCESS,
4471 &spr_read_generic, &spr_write_e500_l1csr0,
4472 0x00000000);
4473 /* XXX : not implemented */
4474 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4475 SPR_NOACCESS, SPR_NOACCESS,
4476 &spr_read_generic, &spr_write_generic,
4477 0x00000000);
4478 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4479 SPR_NOACCESS, SPR_NOACCESS,
4480 &spr_read_generic, &spr_write_generic,
4481 0x00000000);
4482 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4483 SPR_NOACCESS, SPR_NOACCESS,
4484 &spr_read_generic, &spr_write_generic,
4485 0x00000000);
4486 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4487 SPR_NOACCESS, SPR_NOACCESS,
4488 &spr_read_generic, &spr_write_booke206_mmucsr0,
4489 0x00000000);
4490
4491 #if !defined(CONFIG_USER_ONLY)
4492 env->nb_tlb = 0;
4493 env->tlb_type = TLB_MAS;
4494 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4495 env->nb_tlb += booke206_tlb_size(env, i);
4496 }
4497 #endif
4498
4499 init_excp_e200(env);
4500 env->dcache_line_size = 32;
4501 env->icache_line_size = 32;
4502 /* Allocate hardware IRQ controller */
4503 ppce500_irq_init(env);
4504 }
4505
4506 static void init_proc_e500v1(CPUPPCState *env)
4507 {
4508 init_proc_e500(env, 1);
4509 }
4510
4511 static void init_proc_e500v2(CPUPPCState *env)
4512 {
4513 init_proc_e500(env, 2);
4514 }
4515
4516 /* Non-embedded PowerPC */
4517
4518 /* POWER : same as 601, without mfmsr, mfsr */
4519 #if defined(TODO)
4520 #define POWERPC_INSNS_POWER (XXX_TODO)
4521 /* POWER RSC (from RAD6000) */
4522 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4523 #endif /* TODO */
4524
4525 /* PowerPC 601 */
4526 #define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4527 PPC_FLOAT | \
4528 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4529 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4530 PPC_SEGMENT | PPC_EXTERN)
4531 #define POWERPC_INSNS2_601 (PPC_NONE)
4532 #define POWERPC_MSRM_601 (0x000000000000FD70ULL)
4533 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4534 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
4535 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4536 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
4537 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4538 #define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4539 #define check_pow_601 check_pow_none
4540
4541 static void init_proc_601 (CPUPPCState *env)
4542 {
4543 gen_spr_ne_601(env);
4544 gen_spr_601(env);
4545 /* Hardware implementation registers */
4546 /* XXX : not implemented */
4547 spr_register(env, SPR_HID0, "HID0",
4548 SPR_NOACCESS, SPR_NOACCESS,
4549 &spr_read_generic, &spr_write_hid0_601,
4550 0x80010080);
4551 /* XXX : not implemented */
4552 spr_register(env, SPR_HID1, "HID1",
4553 SPR_NOACCESS, SPR_NOACCESS,
4554 &spr_read_generic, &spr_write_generic,
4555 0x00000000);
4556 /* XXX : not implemented */
4557 spr_register(env, SPR_601_HID2, "HID2",
4558 SPR_NOACCESS, SPR_NOACCESS,
4559 &spr_read_generic, &spr_write_generic,
4560 0x00000000);
4561 /* XXX : not implemented */
4562 spr_register(env, SPR_601_HID5, "HID5",
4563 SPR_NOACCESS, SPR_NOACCESS,
4564 &spr_read_generic, &spr_write_generic,
4565 0x00000000);
4566 /* Memory management */
4567 init_excp_601(env);
4568 /* XXX: beware that dcache line size is 64
4569 * but dcbz uses 32 bytes "sectors"
4570 * XXX: this breaks clcs instruction !
4571 */
4572 env->dcache_line_size = 32;
4573 env->icache_line_size = 64;
4574 /* Allocate hardware IRQ controller */
4575 ppc6xx_irq_init(env);
4576 }
4577
4578 /* PowerPC 601v */
4579 #define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4580 PPC_FLOAT | \
4581 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4582 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4583 PPC_SEGMENT | PPC_EXTERN)
4584 #define POWERPC_INSNS2_601v (PPC_NONE)
4585 #define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4586 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4587 #define POWERPC_MMU_601v (POWERPC_MMU_601)
4588 #define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4589 #define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4590 #define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4591 #define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4592 #define check_pow_601v check_pow_none
4593
4594 static void init_proc_601v (CPUPPCState *env)
4595 {
4596 init_proc_601(env);
4597 /* XXX : not implemented */
4598 spr_register(env, SPR_601_HID15, "HID15",
4599 SPR_NOACCESS, SPR_NOACCESS,
4600 &spr_read_generic, &spr_write_generic,
4601 0x00000000);
4602 }
4603
4604 /* PowerPC 602 */
4605 #define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4606 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4607 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4608 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4609 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4610 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4611 PPC_SEGMENT | PPC_602_SPEC)
4612 #define POWERPC_INSNS2_602 (PPC_NONE)
4613 #define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4614 /* XXX: 602 MMU is quite specific. Should add a special case */
4615 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4616 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4617 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
4618 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
4619 #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4620 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4621 #define check_pow_602 check_pow_hid0
4622
4623 static void init_proc_602 (CPUPPCState *env)
4624 {
4625 gen_spr_ne_601(env);
4626 gen_spr_602(env);
4627 /* Time base */
4628 gen_tbl(env);
4629 /* hardware implementation registers */
4630 /* XXX : not implemented */
4631 spr_register(env, SPR_HID0, "HID0",
4632 SPR_NOACCESS, SPR_NOACCESS,
4633 &spr_read_generic, &spr_write_generic,
4634 0x00000000);
4635 /* XXX : not implemented */
4636 spr_register(env, SPR_HID1, "HID1",
4637 SPR_NOACCESS, SPR_NOACCESS,
4638 &spr_read_generic, &spr_write_generic,
4639 0x00000000);
4640 /* Memory management */
4641 gen_low_BATs(env);
4642 gen_6xx_7xx_soft_tlb(env, 64, 2);
4643 init_excp_602(env);
4644 env->dcache_line_size = 32;
4645 env->icache_line_size = 32;
4646 /* Allocate hardware IRQ controller */
4647 ppc6xx_irq_init(env);
4648 }
4649
4650 /* PowerPC 603 */
4651 #define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4652 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4653 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4654 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4655 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4656 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4657 PPC_SEGMENT | PPC_EXTERN)
4658 #define POWERPC_INSNS2_603 (PPC_NONE)
4659 #define POWERPC_MSRM_603 (0x000000000007FF73ULL)
4660 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4661 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4662 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
4663 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
4664 #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4665 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4666 #define check_pow_603 check_pow_hid0
4667
4668 static void init_proc_603 (CPUPPCState *env)
4669 {
4670 gen_spr_ne_601(env);
4671 gen_spr_603(env);
4672 /* Time base */
4673 gen_tbl(env);
4674 /* hardware implementation registers */
4675 /* XXX : not implemented */
4676 spr_register(env, SPR_HID0, "HID0",
4677 SPR_NOACCESS, SPR_NOACCESS,
4678 &spr_read_generic, &spr_write_generic,
4679 0x00000000);
4680 /* XXX : not implemented */
4681 spr_register(env, SPR_HID1, "HID1",
4682 SPR_NOACCESS, SPR_NOACCESS,
4683 &spr_read_generic, &spr_write_generic,
4684 0x00000000);
4685 /* Memory management */
4686 gen_low_BATs(env);
4687 gen_6xx_7xx_soft_tlb(env, 64, 2);
4688 init_excp_603(env);
4689 env->dcache_line_size = 32;
4690 env->icache_line_size = 32;
4691 /* Allocate hardware IRQ controller */
4692 ppc6xx_irq_init(env);
4693 }
4694
4695 /* PowerPC 603e */
4696 #define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4697 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4698 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4699 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4700 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4701 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4702 PPC_SEGMENT | PPC_EXTERN)
4703 #define POWERPC_INSNS2_603E (PPC_NONE)
4704 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4705 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4706 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4707 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
4708 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
4709 #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4710 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4711 #define check_pow_603E check_pow_hid0
4712
4713 static void init_proc_603E (CPUPPCState *env)
4714 {
4715 gen_spr_ne_601(env);
4716 gen_spr_603(env);
4717 /* Time base */
4718 gen_tbl(env);
4719 /* hardware implementation registers */
4720 /* XXX : not implemented */
4721 spr_register(env, SPR_HID0, "HID0",
4722 SPR_NOACCESS, SPR_NOACCESS,
4723 &spr_read_generic, &spr_write_generic,
4724 0x00000000);
4725 /* XXX : not implemented */
4726 spr_register(env, SPR_HID1, "HID1",
4727 SPR_NOACCESS, SPR_NOACCESS,
4728 &spr_read_generic, &spr_write_generic,
4729 0x00000000);
4730 /* XXX : not implemented */
4731 spr_register(env, SPR_IABR, "IABR",
4732 SPR_NOACCESS, SPR_NOACCESS,
4733 &spr_read_generic, &spr_write_generic,
4734 0x00000000);
4735 /* Memory management */
4736 gen_low_BATs(env);
4737 gen_6xx_7xx_soft_tlb(env, 64, 2);
4738 init_excp_603(env);
4739 env->dcache_line_size = 32;
4740 env->icache_line_size = 32;
4741 /* Allocate hardware IRQ controller */
4742 ppc6xx_irq_init(env);
4743 }
4744
4745 /* PowerPC 604 */
4746 #define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4747 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4748 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4749 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4750 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4751 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4752 PPC_SEGMENT | PPC_EXTERN)
4753 #define POWERPC_INSNS2_604 (PPC_NONE)
4754 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4755 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
4756 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4757 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
4758 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
4759 #define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4760 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4761 #define check_pow_604 check_pow_nocheck
4762
4763 static void init_proc_604 (CPUPPCState *env)
4764 {
4765 gen_spr_ne_601(env);
4766 gen_spr_604(env);
4767 /* Time base */
4768 gen_tbl(env);
4769 /* Hardware implementation registers */
4770 /* XXX : not implemented */
4771 spr_register(env, SPR_HID0, "HID0",
4772 SPR_NOACCESS, SPR_NOACCESS,
4773 &spr_read_generic, &spr_write_generic,
4774 0x00000000);
4775 /* Memory management */
4776 gen_low_BATs(env);
4777 init_excp_604(env);
4778 env->dcache_line_size = 32;
4779 env->icache_line_size = 32;
4780 /* Allocate hardware IRQ controller */
4781 ppc6xx_irq_init(env);
4782 }
4783
4784 /* PowerPC 604E */
4785 #define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4786 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4787 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4788 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4789 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4790 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4791 PPC_SEGMENT | PPC_EXTERN)
4792 #define POWERPC_INSNS2_604E (PPC_NONE)
4793 #define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4794 #define POWERPC_MMU_604E (POWERPC_MMU_32B)
4795 #define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4796 #define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4797 #define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4798 #define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4799 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4800 #define check_pow_604E check_pow_nocheck
4801
4802 static void init_proc_604E (CPUPPCState *env)
4803 {
4804 gen_spr_ne_601(env);
4805 gen_spr_604(env);
4806 /* XXX : not implemented */
4807 spr_register(env, SPR_MMCR1, "MMCR1",
4808 SPR_NOACCESS, SPR_NOACCESS,
4809 &spr_read_generic, &spr_write_generic,
4810 0x00000000);
4811 /* XXX : not implemented */
4812 spr_register(env, SPR_PMC3, "PMC3",
4813 SPR_NOACCESS, SPR_NOACCESS,
4814 &spr_read_generic, &spr_write_generic,
4815 0x00000000);
4816 /* XXX : not implemented */
4817 spr_register(env, SPR_PMC4, "PMC4",
4818 SPR_NOACCESS, SPR_NOACCESS,
4819 &spr_read_generic, &spr_write_generic,
4820 0x00000000);
4821 /* Time base */
4822 gen_tbl(env);
4823 /* Hardware implementation registers */
4824 /* XXX : not implemented */
4825 spr_register(env, SPR_HID0, "HID0",
4826 SPR_NOACCESS, SPR_NOACCESS,
4827 &spr_read_generic, &spr_write_generic,
4828 0x00000000);
4829 /* XXX : not implemented */
4830 spr_register(env, SPR_HID1, "HID1",
4831 SPR_NOACCESS, SPR_NOACCESS,
4832 &spr_read_generic, &spr_write_generic,
4833 0x00000000);
4834 /* Memory management */
4835 gen_low_BATs(env);
4836 init_excp_604(env);
4837 env->dcache_line_size = 32;
4838 env->icache_line_size = 32;
4839 /* Allocate hardware IRQ controller */
4840 ppc6xx_irq_init(env);
4841 }
4842
4843 /* PowerPC 740 */
4844 #define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4845 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4846 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4847 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4848 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4849 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4850 PPC_SEGMENT | PPC_EXTERN)
4851 #define POWERPC_INSNS2_740 (PPC_NONE)
4852 #define POWERPC_MSRM_740 (0x000000000005FF77ULL)
4853 #define POWERPC_MMU_740 (POWERPC_MMU_32B)
4854 #define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
4855 #define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
4856 #define POWERPC_BFDM_740 (bfd_mach_ppc_750)
4857 #define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4858 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4859 #define check_pow_740 check_pow_hid0
4860
4861 static void init_proc_740 (CPUPPCState *env)
4862 {
4863 gen_spr_ne_601(env);
4864 gen_spr_7xx(env);
4865 /* Time base */
4866 gen_tbl(env);
4867 /* Thermal management */
4868 gen_spr_thrm(env);
4869 /* Hardware implementation registers */
4870 /* XXX : not implemented */
4871 spr_register(env, SPR_HID0, "HID0",
4872 SPR_NOACCESS, SPR_NOACCESS,
4873 &spr_read_generic, &spr_write_generic,
4874 0x00000000);
4875 /* XXX : not implemented */
4876 spr_register(env, SPR_HID1, "HID1",
4877 SPR_NOACCESS, SPR_NOACCESS,
4878 &spr_read_generic, &spr_write_generic,
4879 0x00000000);
4880 /* Memory management */
4881 gen_low_BATs(env);
4882 init_excp_7x0(env);
4883 env->dcache_line_size = 32;
4884 env->icache_line_size = 32;
4885 /* Allocate hardware IRQ controller */
4886 ppc6xx_irq_init(env);
4887 }
4888
4889 /* PowerPC 750 */
4890 #define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4891 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4892 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4893 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4894 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4895 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4896 PPC_SEGMENT | PPC_EXTERN)
4897 #define POWERPC_INSNS2_750 (PPC_NONE)
4898 #define POWERPC_MSRM_750 (0x000000000005FF77ULL)
4899 #define POWERPC_MMU_750 (POWERPC_MMU_32B)
4900 #define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
4901 #define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
4902 #define POWERPC_BFDM_750 (bfd_mach_ppc_750)
4903 #define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4904 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4905 #define check_pow_750 check_pow_hid0
4906
4907 static void init_proc_750 (CPUPPCState *env)
4908 {
4909 gen_spr_ne_601(env);
4910 gen_spr_7xx(env);
4911 /* XXX : not implemented */
4912 spr_register(env, SPR_L2CR, "L2CR",
4913 SPR_NOACCESS, SPR_NOACCESS,
4914 &spr_read_generic, &spr_write_generic,
4915 0x00000000);
4916 /* Time base */
4917 gen_tbl(env);
4918 /* Thermal management */
4919 gen_spr_thrm(env);
4920 /* Hardware implementation registers */
4921 /* XXX : not implemented */
4922 spr_register(env, SPR_HID0, "HID0",
4923 SPR_NOACCESS, SPR_NOACCESS,
4924 &spr_read_generic, &spr_write_generic,
4925 0x00000000);
4926 /* XXX : not implemented */
4927 spr_register(env, SPR_HID1, "HID1",
4928 SPR_NOACCESS, SPR_NOACCESS,
4929 &spr_read_generic, &spr_write_generic,
4930 0x00000000);
4931 /* Memory management */
4932 gen_low_BATs(env);
4933 /* XXX: high BATs are also present but are known to be bugged on
4934 * die version 1.x
4935 */
4936 init_excp_7x0(env);
4937 env->dcache_line_size = 32;
4938 env->icache_line_size = 32;
4939 /* Allocate hardware IRQ controller */
4940 ppc6xx_irq_init(env);
4941 }
4942
4943 /* PowerPC 750 CL */
4944 /* XXX: not implemented:
4945 * cache lock instructions:
4946 * dcbz_l
4947 * floating point paired instructions
4948 * psq_lux
4949 * psq_lx
4950 * psq_stux
4951 * psq_stx
4952 * ps_abs
4953 * ps_add
4954 * ps_cmpo0
4955 * ps_cmpo1
4956 * ps_cmpu0
4957 * ps_cmpu1
4958 * ps_div
4959 * ps_madd
4960 * ps_madds0
4961 * ps_madds1
4962 * ps_merge00
4963 * ps_merge01
4964 * ps_merge10
4965 * ps_merge11
4966 * ps_mr
4967 * ps_msub
4968 * ps_mul
4969 * ps_muls0
4970 * ps_muls1
4971 * ps_nabs
4972 * ps_neg
4973 * ps_nmadd
4974 * ps_nmsub
4975 * ps_res
4976 * ps_rsqrte
4977 * ps_sel
4978 * ps_sub
4979 * ps_sum0
4980 * ps_sum1
4981 */
4982 #define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4983 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4984 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4985 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4986 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4987 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4988 PPC_SEGMENT | PPC_EXTERN)
4989 #define POWERPC_INSNS2_750cl (PPC_NONE)
4990 #define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
4991 #define POWERPC_MMU_750cl (POWERPC_MMU_32B)
4992 #define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
4993 #define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
4994 #define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
4995 #define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4996 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4997 #define check_pow_750cl check_pow_hid0
4998
4999 static void init_proc_750cl (CPUPPCState *env)
5000 {
5001 gen_spr_ne_601(env);
5002 gen_spr_7xx(env);
5003 /* XXX : not implemented */
5004 spr_register(env, SPR_L2CR, "L2CR",
5005 SPR_NOACCESS, SPR_NOACCESS,
5006 &spr_read_generic, &spr_write_generic,
5007 0x00000000);
5008 /* Time base */
5009 gen_tbl(env);
5010 /* Thermal management */
5011 /* Those registers are fake on 750CL */
5012 spr_register(env, SPR_THRM1, "THRM1",
5013 SPR_NOACCESS, SPR_NOACCESS,
5014 &spr_read_generic, &spr_write_generic,
5015 0x00000000);
5016 spr_register(env, SPR_THRM2, "THRM2",
5017 SPR_NOACCESS, SPR_NOACCESS,
5018 &spr_read_generic, &spr_write_generic,
5019 0x00000000);
5020 spr_register(env, SPR_THRM3, "THRM3",
5021 SPR_NOACCESS, SPR_NOACCESS,
5022 &spr_read_generic, &spr_write_generic,
5023 0x00000000);
5024 /* XXX: not implemented */
5025 spr_register(env, SPR_750_TDCL, "TDCL",
5026 SPR_NOACCESS, SPR_NOACCESS,
5027 &spr_read_generic, &spr_write_generic,
5028 0x00000000);
5029 spr_register(env, SPR_750_TDCH, "TDCH",
5030 SPR_NOACCESS, SPR_NOACCESS,
5031 &spr_read_generic, &spr_write_generic,
5032 0x00000000);
5033 /* DMA */
5034 /* XXX : not implemented */
5035 spr_register(env, SPR_750_WPAR, "WPAR",
5036 SPR_NOACCESS, SPR_NOACCESS,
5037 &spr_read_generic, &spr_write_generic,
5038 0x00000000);
5039 spr_register(env, SPR_750_DMAL, "DMAL",
5040 SPR_NOACCESS, SPR_NOACCESS,
5041 &spr_read_generic, &spr_write_generic,
5042 0x00000000);
5043 spr_register(env, SPR_750_DMAU, "DMAU",
5044 SPR_NOACCESS, SPR_NOACCESS,
5045 &spr_read_generic, &spr_write_generic,
5046 0x00000000);
5047 /* Hardware implementation registers */
5048 /* XXX : not implemented */
5049 spr_register(env, SPR_HID0, "HID0",
5050 SPR_NOACCESS, SPR_NOACCESS,
5051 &spr_read_generic, &spr_write_generic,
5052 0x00000000);
5053 /* XXX : not implemented */
5054 spr_register(env, SPR_HID1, "HID1",
5055 SPR_NOACCESS, SPR_NOACCESS,
5056 &spr_read_generic, &spr_write_generic,
5057 0x00000000);
5058 /* XXX : not implemented */
5059 spr_register(env, SPR_750CL_HID2, "HID2",
5060 SPR_NOACCESS, SPR_NOACCESS,
5061 &spr_read_generic, &spr_write_generic,
5062 0x00000000);
5063 /* XXX : not implemented */
5064 spr_register(env, SPR_750CL_HID4, "HID4",
5065 SPR_NOACCESS, SPR_NOACCESS,
5066 &spr_read_generic, &spr_write_generic,
5067 0x00000000);
5068 /* Quantization registers */
5069 /* XXX : not implemented */
5070 spr_register(env, SPR_750_GQR0, "GQR0",
5071 SPR_NOACCESS, SPR_NOACCESS,
5072 &spr_read_generic, &spr_write_generic,
5073 0x00000000);
5074 /* XXX : not implemented */
5075 spr_register(env, SPR_750_GQR1, "GQR1",
5076 SPR_NOACCESS, SPR_NOACCESS,
5077 &spr_read_generic, &spr_write_generic,
5078 0x00000000);
5079 /* XXX : not implemented */
5080 spr_register(env, SPR_750_GQR2, "GQR2",
5081 SPR_NOACCESS, SPR_NOACCESS,
5082 &spr_read_generic, &spr_write_generic,
5083 0x00000000);
5084 /* XXX : not implemented */
5085 spr_register(env, SPR_750_GQR3, "GQR3",
5086 SPR_NOACCESS, SPR_NOACCESS,
5087 &spr_read_generic, &spr_write_generic,
5088 0x00000000);
5089 /* XXX : not implemented */
5090 spr_register(env, SPR_750_GQR4, "GQR4",
5091 SPR_NOACCESS, SPR_NOACCESS,
5092 &spr_read_generic, &spr_write_generic,
5093 0x00000000);
5094 /* XXX : not implemented */
5095 spr_register(env, SPR_750_GQR5, "GQR5",
5096 SPR_NOACCESS, SPR_NOACCESS,
5097 &spr_read_generic, &spr_write_generic,
5098 0x00000000);
5099 /* XXX : not implemented */
5100 spr_register(env, SPR_750_GQR6, "GQR6",
5101 SPR_NOACCESS, SPR_NOACCESS,
5102 &spr_read_generic, &spr_write_generic,
5103 0x00000000);
5104 /* XXX : not implemented */
5105 spr_register(env, SPR_750_GQR7, "GQR7",
5106 SPR_NOACCESS, SPR_NOACCESS,
5107 &spr_read_generic, &spr_write_generic,
5108 0x00000000);
5109 /* Memory management */
5110 gen_low_BATs(env);
5111 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5112 gen_high_BATs(env);
5113 init_excp_750cl(env);
5114 env->dcache_line_size = 32;
5115 env->icache_line_size = 32;
5116 /* Allocate hardware IRQ controller */
5117 ppc6xx_irq_init(env);
5118 }
5119
5120 /* PowerPC 750CX */
5121 #define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5122 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5123 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5124 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5125 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5126 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5127 PPC_SEGMENT | PPC_EXTERN)
5128 #define POWERPC_INSNS2_750cx (PPC_NONE)
5129 #define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
5130 #define POWERPC_MMU_750cx (POWERPC_MMU_32B)
5131 #define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
5132 #define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
5133 #define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
5134 #define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5135 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5136 #define check_pow_750cx check_pow_hid0
5137
5138 static void init_proc_750cx (CPUPPCState *env)
5139 {
5140 gen_spr_ne_601(env);
5141 gen_spr_7xx(env);
5142 /* XXX : not implemented */
5143 spr_register(env, SPR_L2CR, "L2CR",
5144 SPR_NOACCESS, SPR_NOACCESS,
5145 &spr_read_generic, &spr_write_generic,
5146 0x00000000);
5147 /* Time base */
5148 gen_tbl(env);
5149 /* Thermal management */
5150 gen_spr_thrm(env);
5151 /* This register is not implemented but is present for compatibility */
5152 spr_register(env, SPR_SDA, "SDA",
5153 SPR_NOACCESS, SPR_NOACCESS,
5154 &spr_read_generic, &spr_write_generic,
5155 0x00000000);
5156 /* Hardware implementation registers */
5157 /* XXX : not implemented */
5158 spr_register(env, SPR_HID0, "HID0",
5159 SPR_NOACCESS, SPR_NOACCESS,
5160 &spr_read_generic, &spr_write_generic,
5161 0x00000000);
5162 /* XXX : not implemented */
5163 spr_register(env, SPR_HID1, "HID1",
5164 SPR_NOACCESS, SPR_NOACCESS,
5165 &spr_read_generic, &spr_write_generic,
5166 0x00000000);
5167 /* Memory management */
5168 gen_low_BATs(env);
5169 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5170 gen_high_BATs(env);
5171 init_excp_750cx(env);
5172 env->dcache_line_size = 32;
5173 env->icache_line_size = 32;
5174 /* Allocate hardware IRQ controller */
5175 ppc6xx_irq_init(env);
5176 }
5177
5178 /* PowerPC 750FX */
5179 #define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5180 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5181 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5182 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5183 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5184 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5185 PPC_SEGMENT | PPC_EXTERN)
5186 #define POWERPC_INSNS2_750fx (PPC_NONE)
5187 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
5188 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
5189 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
5190 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
5191 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
5192 #define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5193 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5194 #define check_pow_750fx check_pow_hid0
5195
5196 static void init_proc_750fx (CPUPPCState *env)
5197 {
5198 gen_spr_ne_601(env);
5199 gen_spr_7xx(env);
5200 /* XXX : not implemented */
5201 spr_register(env, SPR_L2CR, "L2CR",
5202 SPR_NOACCESS, SPR_NOACCESS,
5203 &spr_read_generic, &spr_write_generic,
5204 0x00000000);
5205 /* Time base */
5206 gen_tbl(env);
5207 /* Thermal management */
5208 gen_spr_thrm(env);
5209 /* XXX : not implemented */
5210 spr_register(env, SPR_750_THRM4, "THRM4",
5211 SPR_NOACCESS, SPR_NOACCESS,
5212 &spr_read_generic, &spr_write_generic,
5213 0x00000000);
5214 /* Hardware implementation registers */
5215 /* XXX : not implemented */
5216 spr_register(env, SPR_HID0, "HID0",
5217 SPR_NOACCESS, SPR_NOACCESS,
5218 &spr_read_generic, &spr_write_generic,
5219 0x00000000);
5220 /* XXX : not implemented */
5221 spr_register(env, SPR_HID1, "HID1",
5222 SPR_NOACCESS, SPR_NOACCESS,
5223 &spr_read_generic, &spr_write_generic,
5224 0x00000000);
5225 /* XXX : not implemented */
5226 spr_register(env, SPR_750FX_HID2, "HID2",
5227 SPR_NOACCESS, SPR_NOACCESS,
5228 &spr_read_generic, &spr_write_generic,
5229 0x00000000);
5230 /* Memory management */
5231 gen_low_BATs(env);
5232 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5233 gen_high_BATs(env);
5234 init_excp_7x0(env);
5235 env->dcache_line_size = 32;
5236 env->icache_line_size = 32;
5237 /* Allocate hardware IRQ controller */
5238 ppc6xx_irq_init(env);
5239 }
5240
5241 /* PowerPC 750GX */
5242 #define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5243 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5244 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5245 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5246 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5247 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5248 PPC_SEGMENT | PPC_EXTERN)
5249 #define POWERPC_INSNS2_750gx (PPC_NONE)
5250 #define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5251 #define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5252 #define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5253 #define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5254 #define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5255 #define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5256 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5257 #define check_pow_750gx check_pow_hid0
5258
5259 static void init_proc_750gx (CPUPPCState *env)
5260 {
5261 gen_spr_ne_601(env);
5262 gen_spr_7xx(env);
5263 /* XXX : not implemented (XXX: different from 750fx) */
5264 spr_register(env, SPR_L2CR, "L2CR",
5265 SPR_NOACCESS, SPR_NOACCESS,
5266 &spr_read_generic, &spr_write_generic,
5267 0x00000000);
5268 /* Time base */
5269 gen_tbl(env);
5270 /* Thermal management */
5271 gen_spr_thrm(env);
5272 /* XXX : not implemented */
5273 spr_register(env, SPR_750_THRM4, "THRM4",
5274 SPR_NOACCESS, SPR_NOACCESS,
5275 &spr_read_generic, &spr_write_generic,
5276 0x00000000);
5277 /* Hardware implementation registers */
5278 /* XXX : not implemented (XXX: different from 750fx) */
5279 spr_register(env, SPR_HID0, "HID0",
5280 SPR_NOACCESS, SPR_NOACCESS,
5281 &spr_read_generic, &spr_write_generic,
5282 0x00000000);
5283 /* XXX : not implemented */
5284 spr_register(env, SPR_HID1, "HID1",
5285 SPR_NOACCESS, SPR_NOACCESS,
5286 &spr_read_generic, &spr_write_generic,
5287 0x00000000);
5288 /* XXX : not implemented (XXX: different from 750fx) */
5289 spr_register(env, SPR_750FX_HID2, "HID2",
5290 SPR_NOACCESS, SPR_NOACCESS,
5291 &spr_read_generic, &spr_write_generic,
5292 0x00000000);
5293 /* Memory management */
5294 gen_low_BATs(env);
5295 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5296 gen_high_BATs(env);
5297 init_excp_7x0(env);
5298 env->dcache_line_size = 32;
5299 env->icache_line_size = 32;
5300 /* Allocate hardware IRQ controller */
5301 ppc6xx_irq_init(env);
5302 }
5303
5304 /* PowerPC 745 */
5305 #define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5306 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5307 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5308 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5309 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5310 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5311 PPC_SEGMENT | PPC_EXTERN)
5312 #define POWERPC_INSNS2_745 (PPC_NONE)
5313 #define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5314 #define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5315 #define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5316 #define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5317 #define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5318 #define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5319 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5320 #define check_pow_745 check_pow_hid0
5321
5322 static void init_proc_745 (CPUPPCState *env)
5323 {
5324 gen_spr_ne_601(env);
5325 gen_spr_7xx(env);
5326 gen_spr_G2_755(env);
5327 /* Time base */
5328 gen_tbl(env);
5329 /* Thermal management */
5330 gen_spr_thrm(env);
5331 /* Hardware implementation registers */
5332 /* XXX : not implemented */
5333 spr_register(env, SPR_HID0, "HID0",
5334 SPR_NOACCESS, SPR_NOACCESS,
5335 &spr_read_generic, &spr_write_generic,
5336 0x00000000);
5337 /* XXX : not implemented */
5338 spr_register(env, SPR_HID1, "HID1",
5339 SPR_NOACCESS, SPR_NOACCESS,
5340 &spr_read_generic, &spr_write_generic,
5341 0x00000000);
5342 /* XXX : not implemented */
5343 spr_register(env, SPR_HID2, "HID2",
5344 SPR_NOACCESS, SPR_NOACCESS,
5345 &spr_read_generic, &spr_write_generic,
5346 0x00000000);
5347 /* Memory management */
5348 gen_low_BATs(env);
5349 gen_high_BATs(env);
5350 gen_6xx_7xx_soft_tlb(env, 64, 2);
5351 init_excp_7x5(env);
5352 env->dcache_line_size = 32;
5353 env->icache_line_size = 32;
5354 /* Allocate hardware IRQ controller */
5355 ppc6xx_irq_init(env);
5356 }
5357
5358 /* PowerPC 755 */
5359 #define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5360 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5361 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5362 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5363 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5364 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5365 PPC_SEGMENT | PPC_EXTERN)
5366 #define POWERPC_INSNS2_755 (PPC_NONE)
5367 #define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5368 #define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5369 #define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5370 #define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5371 #define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5372 #define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5373 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5374 #define check_pow_755 check_pow_hid0
5375
5376 static void init_proc_755 (CPUPPCState *env)
5377 {
5378 gen_spr_ne_601(env);
5379 gen_spr_7xx(env);
5380 gen_spr_G2_755(env);
5381 /* Time base */
5382 gen_tbl(env);
5383 /* L2 cache control */
5384 /* XXX : not implemented */
5385 spr_register(env, SPR_L2CR, "L2CR",
5386 SPR_NOACCESS, SPR_NOACCESS,
5387 &spr_read_generic, &spr_write_generic,
5388 0x00000000);
5389 /* XXX : not implemented */
5390 spr_register(env, SPR_L2PMCR, "L2PMCR",
5391 SPR_NOACCESS, SPR_NOACCESS,
5392 &spr_read_generic, &spr_write_generic,
5393 0x00000000);
5394 /* Thermal management */
5395 gen_spr_thrm(env);
5396 /* Hardware implementation registers */
5397 /* XXX : not implemented */
5398 spr_register(env, SPR_HID0, "HID0",
5399 SPR_NOACCESS, SPR_NOACCESS,
5400 &spr_read_generic, &spr_write_generic,
5401 0x00000000);
5402 /* XXX : not implemented */
5403 spr_register(env, SPR_HID1, "HID1",
5404 SPR_NOACCESS, SPR_NOACCESS,
5405 &spr_read_generic, &spr_write_generic,
5406 0x00000000);
5407 /* XXX : not implemented */
5408 spr_register(env, SPR_HID2, "HID2",
5409 SPR_NOACCESS, SPR_NOACCESS,
5410 &spr_read_generic, &spr_write_generic,
5411 0x00000000);
5412 /* Memory management */
5413 gen_low_BATs(env);
5414 gen_high_BATs(env);
5415 gen_6xx_7xx_soft_tlb(env, 64, 2);
5416 init_excp_7x5(env);
5417 env->dcache_line_size = 32;
5418 env->icache_line_size = 32;
5419 /* Allocate hardware IRQ controller */
5420 ppc6xx_irq_init(env);
5421 }
5422
5423 /* PowerPC 7400 (aka G4) */
5424 #define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5425 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5426 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5427 PPC_FLOAT_STFIWX | \
5428 PPC_CACHE | PPC_CACHE_ICBI | \
5429 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5430 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5431 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5432 PPC_MEM_TLBIA | \
5433 PPC_SEGMENT | PPC_EXTERN | \
5434 PPC_ALTIVEC)
5435 #define POWERPC_INSNS2_7400 (PPC_NONE)
5436 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5437 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5438 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5439 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
5440 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
5441 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5442 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5443 POWERPC_FLAG_BUS_CLK)
5444 #define check_pow_7400 check_pow_hid0
5445
5446 static void init_proc_7400 (CPUPPCState *env)
5447 {
5448 gen_spr_ne_601(env);
5449 gen_spr_7xx(env);
5450 /* Time base */
5451 gen_tbl(env);
5452 /* 74xx specific SPR */
5453 gen_spr_74xx(env);
5454 /* XXX : not implemented */
5455 spr_register(env, SPR_UBAMR, "UBAMR",
5456 &spr_read_ureg, SPR_NOACCESS,
5457 &spr_read_ureg, SPR_NOACCESS,
5458 0x00000000);
5459 /* XXX: this seems not implemented on all revisions. */
5460 /* XXX : not implemented */
5461 spr_register(env, SPR_MSSCR1, "MSSCR1",
5462 SPR_NOACCESS, SPR_NOACCESS,
5463 &spr_read_generic, &spr_write_generic,
5464 0x00000000);
5465 /* Thermal management */
5466 gen_spr_thrm(env);
5467 /* Memory management */
5468 gen_low_BATs(env);
5469 init_excp_7400(env);
5470 env->dcache_line_size = 32;
5471 env->icache_line_size = 32;
5472 /* Allocate hardware IRQ controller */
5473 ppc6xx_irq_init(env);
5474 }
5475
5476 /* PowerPC 7410 (aka G4) */
5477 #define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5478 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5479 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5480 PPC_FLOAT_STFIWX | \
5481 PPC_CACHE | PPC_CACHE_ICBI | \
5482 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5483 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5484 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5485 PPC_MEM_TLBIA | \
5486 PPC_SEGMENT | PPC_EXTERN | \
5487 PPC_ALTIVEC)
5488 #define POWERPC_INSNS2_7410 (PPC_NONE)
5489 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5490 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5491 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5492 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
5493 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
5494 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5495 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5496 POWERPC_FLAG_BUS_CLK)
5497 #define check_pow_7410 check_pow_hid0
5498
5499 static void init_proc_7410 (CPUPPCState *env)
5500 {
5501 gen_spr_ne_601(env);
5502 gen_spr_7xx(env);
5503 /* Time base */
5504 gen_tbl(env);
5505 /* 74xx specific SPR */
5506 gen_spr_74xx(env);
5507 /* XXX : not implemented */
5508 spr_register(env, SPR_UBAMR, "UBAMR",
5509 &spr_read_ureg, SPR_NOACCESS,
5510 &spr_read_ureg, SPR_NOACCESS,
5511 0x00000000);
5512 /* Thermal management */
5513 gen_spr_thrm(env);
5514 /* L2PMCR */
5515 /* XXX : not implemented */
5516 spr_register(env, SPR_L2PMCR, "L2PMCR",
5517 SPR_NOACCESS, SPR_NOACCESS,
5518 &spr_read_generic, &spr_write_generic,
5519 0x00000000);
5520 /* LDSTDB */
5521 /* XXX : not implemented */
5522 spr_register(env, SPR_LDSTDB, "LDSTDB",
5523 SPR_NOACCESS, SPR_NOACCESS,
5524 &spr_read_generic, &spr_write_generic,
5525 0x00000000);
5526 /* Memory management */
5527 gen_low_BATs(env);
5528 init_excp_7400(env);
5529 env->dcache_line_size = 32;
5530 env->icache_line_size = 32;
5531 /* Allocate hardware IRQ controller */
5532 ppc6xx_irq_init(env);
5533 }
5534
5535 /* PowerPC 7440 (aka G4) */
5536 #define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5537 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5538 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5539 PPC_FLOAT_STFIWX | \
5540 PPC_CACHE | PPC_CACHE_ICBI | \
5541 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5542 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5543 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5544 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5545 PPC_SEGMENT | PPC_EXTERN | \
5546 PPC_ALTIVEC)
5547 #define POWERPC_INSNS2_7440 (PPC_NONE)
5548 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5549 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5550 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5551 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
5552 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
5553 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5554 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5555 POWERPC_FLAG_BUS_CLK)
5556 #define check_pow_7440 check_pow_hid0_74xx
5557
5558 __attribute__ (( unused ))
5559 static void init_proc_7440 (CPUPPCState *env)
5560 {
5561 gen_spr_ne_601(env);
5562 gen_spr_7xx(env);
5563 /* Time base */
5564 gen_tbl(env);
5565 /* 74xx specific SPR */
5566 gen_spr_74xx(env);
5567 /* XXX : not implemented */
5568 spr_register(env, SPR_UBAMR, "UBAMR",
5569 &spr_read_ureg, SPR_NOACCESS,
5570 &spr_read_ureg, SPR_NOACCESS,
5571 0x00000000);
5572 /* LDSTCR */
5573 /* XXX : not implemented */
5574 spr_register(env, SPR_LDSTCR, "LDSTCR",
5575 SPR_NOACCESS, SPR_NOACCESS,
5576 &spr_read_generic, &spr_write_generic,
5577 0x00000000);
5578 /* ICTRL */
5579 /* XXX : not implemented */
5580 spr_register(env, SPR_ICTRL, "ICTRL",
5581 SPR_NOACCESS, SPR_NOACCESS,
5582 &spr_read_generic, &spr_write_generic,
5583 0x00000000);
5584 /* MSSSR0 */
5585 /* XXX : not implemented */
5586 spr_register(env, SPR_MSSSR0, "MSSSR0",
5587 SPR_NOACCESS, SPR_NOACCESS,
5588 &spr_read_generic, &spr_write_generic,
5589 0x00000000);
5590 /* PMC */
5591 /* XXX : not implemented */
5592 spr_register(env, SPR_PMC5, "PMC5",
5593 SPR_NOACCESS, SPR_NOACCESS,
5594 &spr_read_generic, &spr_write_generic,
5595 0x00000000);
5596 /* XXX : not implemented */
5597 spr_register(env, SPR_UPMC5, "UPMC5",
5598 &spr_read_ureg, SPR_NOACCESS,
5599 &spr_read_ureg, SPR_NOACCESS,
5600 0x00000000);
5601 /* XXX : not implemented */
5602 spr_register(env, SPR_PMC6, "PMC6",
5603 SPR_NOACCESS, SPR_NOACCESS,
5604 &spr_read_generic, &spr_write_generic,
5605 0x00000000);
5606 /* XXX : not implemented */
5607 spr_register(env, SPR_UPMC6, "UPMC6",
5608 &spr_read_ureg, SPR_NOACCESS,
5609 &spr_read_ureg, SPR_NOACCESS,
5610 0x00000000);
5611 /* Memory management */
5612 gen_low_BATs(env);
5613 gen_74xx_soft_tlb(env, 128, 2);
5614 init_excp_7450(env);
5615 env->dcache_line_size = 32;
5616 env->icache_line_size = 32;
5617 /* Allocate hardware IRQ controller */
5618 ppc6xx_irq_init(env);
5619 }
5620
5621 /* PowerPC 7450 (aka G4) */
5622 #define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5623 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5624 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5625 PPC_FLOAT_STFIWX | \
5626 PPC_CACHE | PPC_CACHE_ICBI | \
5627 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5628 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5629 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5630 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5631 PPC_SEGMENT | PPC_EXTERN | \
5632 PPC_ALTIVEC)
5633 #define POWERPC_INSNS2_7450 (PPC_NONE)
5634 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5635 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5636 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5637 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
5638 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
5639 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5640 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5641 POWERPC_FLAG_BUS_CLK)
5642 #define check_pow_7450 check_pow_hid0_74xx
5643
5644 __attribute__ (( unused ))
5645 static void init_proc_7450 (CPUPPCState *env)
5646 {
5647 gen_spr_ne_601(env);
5648 gen_spr_7xx(env);
5649 /* Time base */
5650 gen_tbl(env);
5651 /* 74xx specific SPR */
5652 gen_spr_74xx(env);
5653 /* Level 3 cache control */
5654 gen_l3_ctrl(env);
5655 /* L3ITCR1 */
5656 /* XXX : not implemented */
5657 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5658 SPR_NOACCESS, SPR_NOACCESS,
5659 &spr_read_generic, &spr_write_generic,
5660 0x00000000);
5661 /* L3ITCR2 */
5662 /* XXX : not implemented */
5663 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5664 SPR_NOACCESS, SPR_NOACCESS,
5665 &spr_read_generic, &spr_write_generic,
5666 0x00000000);
5667 /* L3ITCR3 */
5668 /* XXX : not implemented */
5669 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5670 SPR_NOACCESS, SPR_NOACCESS,
5671 &spr_read_generic, &spr_write_generic,
5672 0x00000000);
5673 /* L3OHCR */
5674 /* XXX : not implemented */
5675 spr_register(env, SPR_L3OHCR, "L3OHCR",
5676 SPR_NOACCESS, SPR_NOACCESS,
5677 &spr_read_generic, &spr_write_generic,
5678 0x00000000);
5679 /* XXX : not implemented */
5680 spr_register(env, SPR_UBAMR, "UBAMR",
5681 &spr_read_ureg, SPR_NOACCESS,
5682 &spr_read_ureg, SPR_NOACCESS,
5683 0x00000000);
5684 /* LDSTCR */
5685 /* XXX : not implemented */
5686 spr_register(env, SPR_LDSTCR, "LDSTCR",
5687 SPR_NOACCESS, SPR_NOACCESS,
5688 &spr_read_generic, &spr_write_generic,
5689 0x00000000);
5690 /* ICTRL */
5691 /* XXX : not implemented */
5692 spr_register(env, SPR_ICTRL, "ICTRL",
5693 SPR_NOACCESS, SPR_NOACCESS,
5694 &spr_read_generic, &spr_write_generic,
5695 0x00000000);
5696 /* MSSSR0 */
5697 /* XXX : not implemented */
5698 spr_register(env, SPR_MSSSR0, "MSSSR0",
5699 SPR_NOACCESS, SPR_NOACCESS,
5700 &spr_read_generic, &spr_write_generic,
5701 0x00000000);
5702 /* PMC */
5703 /* XXX : not implemented */
5704 spr_register(env, SPR_PMC5, "PMC5",
5705 SPR_NOACCESS, SPR_NOACCESS,
5706 &spr_read_generic, &spr_write_generic,
5707 0x00000000);
5708 /* XXX : not implemented */
5709 spr_register(env, SPR_UPMC5, "UPMC5",
5710 &spr_read_ureg, SPR_NOACCESS,
5711 &spr_read_ureg, SPR_NOACCESS,
5712 0x00000000);
5713 /* XXX : not implemented */
5714 spr_register(env, SPR_PMC6, "PMC6",
5715 SPR_NOACCESS, SPR_NOACCESS,
5716 &spr_read_generic, &spr_write_generic,
5717 0x00000000);
5718 /* XXX : not implemented */
5719 spr_register(env, SPR_UPMC6, "UPMC6",
5720 &spr_read_ureg, SPR_NOACCESS,
5721 &spr_read_ureg, SPR_NOACCESS,
5722 0x00000000);
5723 /* Memory management */
5724 gen_low_BATs(env);
5725 gen_74xx_soft_tlb(env, 128, 2);
5726 init_excp_7450(env);
5727 env->dcache_line_size = 32;
5728 env->icache_line_size = 32;
5729 /* Allocate hardware IRQ controller */
5730 ppc6xx_irq_init(env);
5731 }
5732
5733 /* PowerPC 7445 (aka G4) */
5734 #define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5735 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5736 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5737 PPC_FLOAT_STFIWX | \
5738 PPC_CACHE | PPC_CACHE_ICBI | \
5739 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5740 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5741 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5742 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5743 PPC_SEGMENT | PPC_EXTERN | \
5744 PPC_ALTIVEC)
5745 #define POWERPC_INSNS2_7445 (PPC_NONE)
5746 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5747 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5748 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5749 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
5750 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
5751 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5752 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5753 POWERPC_FLAG_BUS_CLK)
5754 #define check_pow_7445 check_pow_hid0_74xx
5755
5756 __attribute__ (( unused ))
5757 static void init_proc_7445 (CPUPPCState *env)
5758 {
5759 gen_spr_ne_601(env);
5760 gen_spr_7xx(env);
5761 /* Time base */
5762 gen_tbl(env);
5763 /* 74xx specific SPR */
5764 gen_spr_74xx(env);
5765 /* LDSTCR */
5766 /* XXX : not implemented */
5767 spr_register(env, SPR_LDSTCR, "LDSTCR",
5768 SPR_NOACCESS, SPR_NOACCESS,
5769 &spr_read_generic, &spr_write_generic,
5770 0x00000000);
5771 /* ICTRL */
5772 /* XXX : not implemented */
5773 spr_register(env, SPR_ICTRL, "ICTRL",
5774 SPR_NOACCESS, SPR_NOACCESS,
5775 &spr_read_generic, &spr_write_generic,
5776 0x00000000);
5777 /* MSSSR0 */
5778 /* XXX : not implemented */
5779 spr_register(env, SPR_MSSSR0, "MSSSR0",
5780 SPR_NOACCESS, SPR_NOACCESS,
5781 &spr_read_generic, &spr_write_generic,
5782 0x00000000);
5783 /* PMC */
5784 /* XXX : not implemented */
5785 spr_register(env, SPR_PMC5, "PMC5",
5786 SPR_NOACCESS, SPR_NOACCESS,
5787 &spr_read_generic, &spr_write_generic,
5788 0x00000000);
5789 /* XXX : not implemented */
5790 spr_register(env, SPR_UPMC5, "UPMC5",
5791 &spr_read_ureg, SPR_NOACCESS,
5792 &spr_read_ureg, SPR_NOACCESS,
5793 0x00000000);
5794 /* XXX : not implemented */
5795 spr_register(env, SPR_PMC6, "PMC6",
5796 SPR_NOACCESS, SPR_NOACCESS,
5797 &spr_read_generic, &spr_write_generic,
5798 0x00000000);
5799 /* XXX : not implemented */
5800 spr_register(env, SPR_UPMC6, "UPMC6",
5801 &spr_read_ureg, SPR_NOACCESS,
5802 &spr_read_ureg, SPR_NOACCESS,
5803 0x00000000);
5804 /* SPRGs */
5805 spr_register(env, SPR_SPRG4, "SPRG4",
5806 SPR_NOACCESS, SPR_NOACCESS,
5807 &spr_read_generic, &spr_write_generic,
5808 0x00000000);
5809 spr_register(env, SPR_USPRG4, "USPRG4",
5810 &spr_read_ureg, SPR_NOACCESS,
5811 &spr_read_ureg, SPR_NOACCESS,
5812 0x00000000);
5813 spr_register(env, SPR_SPRG5, "SPRG5",
5814 SPR_NOACCESS, SPR_NOACCESS,
5815 &spr_read_generic, &spr_write_generic,
5816 0x00000000);
5817 spr_register(env, SPR_USPRG5, "USPRG5",
5818 &spr_read_ureg, SPR_NOACCESS,
5819 &spr_read_ureg, SPR_NOACCESS,
5820 0x00000000);
5821 spr_register(env, SPR_SPRG6, "SPRG6",
5822 SPR_NOACCESS, SPR_NOACCESS,
5823 &spr_read_generic, &spr_write_generic,
5824 0x00000000);
5825 spr_register(env, SPR_USPRG6, "USPRG6",
5826 &spr_read_ureg, SPR_NOACCESS,
5827 &spr_read_ureg, SPR_NOACCESS,
5828 0x00000000);
5829 spr_register(env, SPR_SPRG7, "SPRG7",
5830 SPR_NOACCESS, SPR_NOACCESS,
5831 &spr_read_generic, &spr_write_generic,
5832 0x00000000);
5833 spr_register(env, SPR_USPRG7, "USPRG7",
5834 &spr_read_ureg, SPR_NOACCESS,
5835 &spr_read_ureg, SPR_NOACCESS,
5836 0x00000000);
5837 /* Memory management */
5838 gen_low_BATs(env);
5839 gen_high_BATs(env);
5840 gen_74xx_soft_tlb(env, 128, 2);
5841 init_excp_7450(env);
5842 env->dcache_line_size = 32;
5843 env->icache_line_size = 32;
5844 /* Allocate hardware IRQ controller */
5845 ppc6xx_irq_init(env);
5846 }
5847
5848 /* PowerPC 7455 (aka G4) */
5849 #define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5850 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5851 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5852 PPC_FLOAT_STFIWX | \
5853 PPC_CACHE | PPC_CACHE_ICBI | \
5854 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5855 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5856 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5857 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5858 PPC_SEGMENT | PPC_EXTERN | \
5859 PPC_ALTIVEC)
5860 #define POWERPC_INSNS2_7455 (PPC_NONE)
5861 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
5862 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
5863 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
5864 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
5865 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
5866 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5867 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5868 POWERPC_FLAG_BUS_CLK)
5869 #define check_pow_7455 check_pow_hid0_74xx
5870
5871 __attribute__ (( unused ))
5872 static void init_proc_7455 (CPUPPCState *env)
5873 {
5874 gen_spr_ne_601(env);
5875 gen_spr_7xx(env);
5876 /* Time base */
5877 gen_tbl(env);
5878 /* 74xx specific SPR */
5879 gen_spr_74xx(env);
5880 /* Level 3 cache control */
5881 gen_l3_ctrl(env);
5882 /* LDSTCR */
5883 /* XXX : not implemented */
5884 spr_register(env, SPR_LDSTCR, "LDSTCR",
5885 SPR_NOACCESS, SPR_NOACCESS,
5886 &spr_read_generic, &spr_write_generic,
5887 0x00000000);
5888 /* ICTRL */
5889 /* XXX : not implemented */
5890 spr_register(env, SPR_ICTRL, "ICTRL",
5891 SPR_NOACCESS, SPR_NOACCESS,
5892 &spr_read_generic, &spr_write_generic,
5893 0x00000000);
5894 /* MSSSR0 */
5895 /* XXX : not implemented */
5896 spr_register(env, SPR_MSSSR0, "MSSSR0",
5897 SPR_NOACCESS, SPR_NOACCESS,
5898 &spr_read_generic, &spr_write_generic,
5899 0x00000000);
5900 /* PMC */
5901 /* XXX : not implemented */
5902 spr_register(env, SPR_PMC5, "PMC5",
5903 SPR_NOACCESS, SPR_NOACCESS,
5904 &spr_read_generic, &spr_write_generic,
5905 0x00000000);
5906 /* XXX : not implemented */
5907 spr_register(env, SPR_UPMC5, "UPMC5",
5908 &spr_read_ureg, SPR_NOACCESS,
5909 &spr_read_ureg, SPR_NOACCESS,
5910 0x00000000);
5911 /* XXX : not implemented */
5912 spr_register(env, SPR_PMC6, "PMC6",
5913 SPR_NOACCESS, SPR_NOACCESS,
5914 &spr_read_generic, &spr_write_generic,
5915 0x00000000);
5916 /* XXX : not implemented */
5917 spr_register(env, SPR_UPMC6, "UPMC6",
5918 &spr_read_ureg, SPR_NOACCESS,
5919 &spr_read_ureg, SPR_NOACCESS,
5920 0x00000000);
5921 /* SPRGs */
5922 spr_register(env, SPR_SPRG4, "SPRG4",
5923 SPR_NOACCESS, SPR_NOACCESS,
5924 &spr_read_generic, &spr_write_generic,
5925 0x00000000);
5926 spr_register(env, SPR_USPRG4, "USPRG4",
5927 &spr_read_ureg, SPR_NOACCESS,
5928 &spr_read_ureg, SPR_NOACCESS,
5929 0x00000000);
5930 spr_register(env, SPR_SPRG5, "SPRG5",
5931 SPR_NOACCESS, SPR_NOACCESS,
5932 &spr_read_generic, &spr_write_generic,
5933 0x00000000);
5934 spr_register(env, SPR_USPRG5, "USPRG5",
5935 &spr_read_ureg, SPR_NOACCESS,
5936 &spr_read_ureg, SPR_NOACCESS,
5937 0x00000000);
5938 spr_register(env, SPR_SPRG6, "SPRG6",
5939 SPR_NOACCESS, SPR_NOACCESS,
5940 &spr_read_generic, &spr_write_generic,
5941 0x00000000);
5942 spr_register(env, SPR_USPRG6, "USPRG6",
5943 &spr_read_ureg, SPR_NOACCESS,
5944 &spr_read_ureg, SPR_NOACCESS,
5945 0x00000000);
5946 spr_register(env, SPR_SPRG7, "SPRG7",
5947 SPR_NOACCESS, SPR_NOACCESS,
5948 &spr_read_generic, &spr_write_generic,
5949 0x00000000);
5950 spr_register(env, SPR_USPRG7, "USPRG7",
5951 &spr_read_ureg, SPR_NOACCESS,
5952 &spr_read_ureg, SPR_NOACCESS,
5953 0x00000000);
5954 /* Memory management */
5955 gen_low_BATs(env);
5956 gen_high_BATs(env);
5957 gen_74xx_soft_tlb(env, 128, 2);
5958 init_excp_7450(env);
5959 env->dcache_line_size = 32;
5960 env->icache_line_size = 32;
5961 /* Allocate hardware IRQ controller */
5962 ppc6xx_irq_init(env);
5963 }
5964
5965 /* PowerPC 7457 (aka G4) */
5966 #define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5967 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5968 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5969 PPC_FLOAT_STFIWX | \
5970 PPC_CACHE | PPC_CACHE_ICBI | \
5971 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5972 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5973 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5974 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5975 PPC_SEGMENT | PPC_EXTERN | \
5976 PPC_ALTIVEC)
5977 #define POWERPC_INSNS2_7457 (PPC_NONE)
5978 #define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
5979 #define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
5980 #define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
5981 #define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
5982 #define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
5983 #define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5984 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5985 POWERPC_FLAG_BUS_CLK)
5986 #define check_pow_7457 check_pow_hid0_74xx
5987
5988 __attribute__ (( unused ))
5989 static void init_proc_7457 (CPUPPCState *env)
5990 {
5991 gen_spr_ne_601(env);
5992 gen_spr_7xx(env);
5993 /* Time base */
5994 gen_tbl(env);
5995 /* 74xx specific SPR */
5996 gen_spr_74xx(env);
5997 /* Level 3 cache control */
5998 gen_l3_ctrl(env);
5999 /* L3ITCR1 */
6000 /* XXX : not implemented */
6001 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6002 SPR_NOACCESS, SPR_NOACCESS,
6003 &spr_read_generic, &spr_write_generic,
6004 0x00000000);
6005 /* L3ITCR2 */
6006 /* XXX : not implemented */
6007 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6008 SPR_NOACCESS, SPR_NOACCESS,
6009 &spr_read_generic, &spr_write_generic,
6010 0x00000000);
6011 /* L3ITCR3 */
6012 /* XXX : not implemented */
6013 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6014 SPR_NOACCESS, SPR_NOACCESS,
6015 &spr_read_generic, &spr_write_generic,
6016 0x00000000);
6017 /* L3OHCR */
6018 /* XXX : not implemented */
6019 spr_register(env, SPR_L3OHCR, "L3OHCR",
6020 SPR_NOACCESS, SPR_NOACCESS,
6021 &spr_read_generic, &spr_write_generic,
6022 0x00000000);
6023 /* LDSTCR */
6024 /* XXX : not implemented */
6025 spr_register(env, SPR_LDSTCR, "LDSTCR",
6026 SPR_NOACCESS, SPR_NOACCESS,
6027 &spr_read_generic, &spr_write_generic,
6028 0x00000000);
6029 /* ICTRL */
6030 /* XXX : not implemented */
6031 spr_register(env, SPR_ICTRL, "ICTRL",
6032 SPR_NOACCESS, SPR_NOACCESS,
6033 &spr_read_generic, &spr_write_generic,
6034 0x00000000);
6035 /* MSSSR0 */
6036 /* XXX : not implemented */
6037 spr_register(env, SPR_MSSSR0, "MSSSR0",
6038 SPR_NOACCESS, SPR_NOACCESS,
6039 &spr_read_generic, &spr_write_generic,
6040 0x00000000);
6041 /* PMC */
6042 /* XXX : not implemented */
6043 spr_register(env, SPR_PMC5, "PMC5",
6044 SPR_NOACCESS, SPR_NOACCESS,
6045 &spr_read_generic, &spr_write_generic,
6046 0x00000000);
6047 /* XXX : not implemented */
6048 spr_register(env, SPR_UPMC5, "UPMC5",
6049 &spr_read_ureg, SPR_NOACCESS,
6050 &spr_read_ureg, SPR_NOACCESS,
6051 0x00000000);
6052 /* XXX : not implemented */
6053 spr_register(env, SPR_PMC6, "PMC6",
6054 SPR_NOACCESS, SPR_NOACCESS,
6055 &spr_read_generic, &spr_write_generic,
6056 0x00000000);
6057 /* XXX : not implemented */
6058 spr_register(env, SPR_UPMC6, "UPMC6",
6059 &spr_read_ureg, SPR_NOACCESS,
6060 &spr_read_ureg, SPR_NOACCESS,
6061 0x00000000);
6062 /* SPRGs */
6063 spr_register(env, SPR_SPRG4, "SPRG4",
6064 SPR_NOACCESS, SPR_NOACCESS,
6065 &spr_read_generic, &spr_write_generic,
6066 0x00000000);
6067 spr_register(env, SPR_USPRG4, "USPRG4",
6068 &spr_read_ureg, SPR_NOACCESS,
6069 &spr_read_ureg, SPR_NOACCESS,
6070 0x00000000);
6071 spr_register(env, SPR_SPRG5, "SPRG5",
6072 SPR_NOACCESS, SPR_NOACCESS,
6073 &spr_read_generic, &spr_write_generic,
6074 0x00000000);
6075 spr_register(env, SPR_USPRG5, "USPRG5",
6076 &spr_read_ureg, SPR_NOACCESS,
6077 &spr_read_ureg, SPR_NOACCESS,
6078 0x00000000);
6079 spr_register(env, SPR_SPRG6, "SPRG6",
6080 SPR_NOACCESS, SPR_NOACCESS,
6081 &spr_read_generic, &spr_write_generic,
6082 0x00000000);
6083 spr_register(env, SPR_USPRG6, "USPRG6",
6084 &spr_read_ureg, SPR_NOACCESS,
6085 &spr_read_ureg, SPR_NOACCESS,
6086 0x00000000);
6087 spr_register(env, SPR_SPRG7, "SPRG7",
6088 SPR_NOACCESS, SPR_NOACCESS,
6089 &spr_read_generic, &spr_write_generic,
6090 0x00000000);
6091 spr_register(env, SPR_USPRG7, "USPRG7",
6092 &spr_read_ureg, SPR_NOACCESS,
6093 &spr_read_ureg, SPR_NOACCESS,
6094 0x00000000);
6095 /* Memory management */
6096 gen_low_BATs(env);
6097 gen_high_BATs(env);
6098 gen_74xx_soft_tlb(env, 128, 2);
6099 init_excp_7450(env);
6100 env->dcache_line_size = 32;
6101 env->icache_line_size = 32;
6102 /* Allocate hardware IRQ controller */
6103 ppc6xx_irq_init(env);
6104 }
6105
6106 #if defined (TARGET_PPC64)
6107 /* PowerPC 970 */
6108 #define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6109 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6110 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6111 PPC_FLOAT_STFIWX | \
6112 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6113 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6114 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6115 PPC_64B | PPC_ALTIVEC | \
6116 PPC_SEGMENT_64B | PPC_SLBI)
6117 #define POWERPC_INSNS2_970 (PPC_NONE)
6118 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
6119 #define POWERPC_MMU_970 (POWERPC_MMU_64B)
6120 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
6121 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
6122 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
6123 #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6124 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6125 POWERPC_FLAG_BUS_CLK)
6126
6127 #if defined(CONFIG_USER_ONLY)
6128 #define POWERPC970_HID5_INIT 0x00000080
6129 #else
6130 #define POWERPC970_HID5_INIT 0x00000000
6131 #endif
6132
6133 static int check_pow_970 (CPUPPCState *env)
6134 {
6135 if (env->spr[SPR_HID0] & 0x00600000)
6136 return 1;
6137
6138 return 0;
6139 }
6140
6141 static void init_proc_970 (CPUPPCState *env)
6142 {
6143 gen_spr_ne_601(env);
6144 gen_spr_7xx(env);
6145 /* Time base */
6146 gen_tbl(env);
6147 /* Hardware implementation registers */
6148 /* XXX : not implemented */
6149 spr_register(env, SPR_HID0, "HID0",
6150 SPR_NOACCESS, SPR_NOACCESS,
6151 &spr_read_generic, &spr_write_clear,
6152 0x60000000);
6153 /* XXX : not implemented */
6154 spr_register(env, SPR_HID1, "HID1",
6155 SPR_NOACCESS, SPR_NOACCESS,
6156 &spr_read_generic, &spr_write_generic,
6157 0x00000000);
6158 /* XXX : not implemented */
6159 spr_register(env, SPR_750FX_HID2, "HID2",
6160 SPR_NOACCESS, SPR_NOACCESS,
6161 &spr_read_generic, &spr_write_generic,
6162 0x00000000);
6163 /* XXX : not implemented */
6164 spr_register(env, SPR_970_HID5, "HID5",
6165 SPR_NOACCESS, SPR_NOACCESS,
6166 &spr_read_generic, &spr_write_generic,
6167 POWERPC970_HID5_INIT);
6168 /* XXX : not implemented */
6169 spr_register(env, SPR_L2CR, "L2CR",
6170 SPR_NOACCESS, SPR_NOACCESS,
6171 &spr_read_generic, &spr_write_generic,
6172 0x00000000);
6173 /* Memory management */
6174 /* XXX: not correct */
6175 gen_low_BATs(env);
6176 /* XXX : not implemented */
6177 spr_register(env, SPR_MMUCFG, "MMUCFG",
6178 SPR_NOACCESS, SPR_NOACCESS,
6179 &spr_read_generic, SPR_NOACCESS,
6180 0x00000000); /* TOFIX */
6181 /* XXX : not implemented */
6182 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6183 SPR_NOACCESS, SPR_NOACCESS,
6184 &spr_read_generic, &spr_write_generic,
6185 0x00000000); /* TOFIX */
6186 spr_register(env, SPR_HIOR, "SPR_HIOR",
6187 SPR_NOACCESS, SPR_NOACCESS,
6188 &spr_read_hior, &spr_write_hior,
6189 0x00000000);
6190 #if !defined(CONFIG_USER_ONLY)
6191 env->slb_nr = 32;
6192 #endif
6193 init_excp_970(env);
6194 env->dcache_line_size = 128;
6195 env->icache_line_size = 128;
6196 /* Allocate hardware IRQ controller */
6197 ppc970_irq_init(env);
6198 /* Can't find information on what this should be on reset. This
6199 * value is the one used by 74xx processors. */
6200 vscr_init(env, 0x00010000);
6201 }
6202
6203 /* PowerPC 970FX (aka G5) */
6204 #define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6205 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6206 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6207 PPC_FLOAT_STFIWX | \
6208 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6209 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6210 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6211 PPC_64B | PPC_ALTIVEC | \
6212 PPC_SEGMENT_64B | PPC_SLBI)
6213 #define POWERPC_INSNS2_970FX (PPC_NONE)
6214 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
6215 #define POWERPC_MMU_970FX (POWERPC_MMU_64B)
6216 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
6217 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
6218 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
6219 #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6220 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6221 POWERPC_FLAG_BUS_CLK)
6222
6223 static int check_pow_970FX (CPUPPCState *env)
6224 {
6225 if (env->spr[SPR_HID0] & 0x00600000)
6226 return 1;
6227
6228 return 0;
6229 }
6230
6231 static void init_proc_970FX (CPUPPCState *env)
6232 {
6233 gen_spr_ne_601(env);
6234 gen_spr_7xx(env);
6235 /* Time base */
6236 gen_tbl(env);
6237 /* Hardware implementation registers */
6238 /* XXX : not implemented */
6239 spr_register(env, SPR_HID0, "HID0",
6240 SPR_NOACCESS, SPR_NOACCESS,
6241 &spr_read_generic, &spr_write_clear,
6242 0x60000000);
6243 /* XXX : not implemented */
6244 spr_register(env, SPR_HID1, "HID1",
6245 SPR_NOACCESS, SPR_NOACCESS,
6246 &spr_read_generic, &spr_write_generic,
6247 0x00000000);
6248 /* XXX : not implemented */
6249 spr_register(env, SPR_750FX_HID2, "HID2",
6250 SPR_NOACCESS, SPR_NOACCESS,
6251 &spr_read_generic, &spr_write_generic,
6252 0x00000000);
6253 /* XXX : not implemented */
6254 spr_register(env, SPR_970_HID5, "HID5",
6255 SPR_NOACCESS, SPR_NOACCESS,
6256 &spr_read_generic, &spr_write_generic,
6257 POWERPC970_HID5_INIT);
6258 /* XXX : not implemented */
6259 spr_register(env, SPR_L2CR, "L2CR",
6260 SPR_NOACCESS, SPR_NOACCESS,
6261 &spr_read_generic, &spr_write_generic,
6262 0x00000000);
6263 /* Memory management */
6264 /* XXX: not correct */
6265 gen_low_BATs(env);
6266 /* XXX : not implemented */
6267 spr_register(env, SPR_MMUCFG, "MMUCFG",
6268 SPR_NOACCESS, SPR_NOACCESS,
6269 &spr_read_generic, SPR_NOACCESS,
6270 0x00000000); /* TOFIX */
6271 /* XXX : not implemented */
6272 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6273 SPR_NOACCESS, SPR_NOACCESS,
6274 &spr_read_generic, &spr_write_generic,
6275 0x00000000); /* TOFIX */
6276 spr_register(env, SPR_HIOR, "SPR_HIOR",
6277 SPR_NOACCESS, SPR_NOACCESS,
6278 &spr_read_hior, &spr_write_hior,
6279 0x00000000);
6280 spr_register(env, SPR_CTRL, "SPR_CTRL",
6281 SPR_NOACCESS, SPR_NOACCESS,
6282 &spr_read_generic, &spr_write_generic,
6283 0x00000000);
6284 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6285 SPR_NOACCESS, SPR_NOACCESS,
6286 &spr_read_generic, &spr_write_generic,
6287 0x00000000);
6288 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6289 &spr_read_generic, &spr_write_generic,
6290 &spr_read_generic, &spr_write_generic,
6291 0x00000000);
6292 #if !defined(CONFIG_USER_ONLY)
6293 env->slb_nr = 64;
6294 #endif
6295 init_excp_970(env);
6296 env->dcache_line_size = 128;
6297 env->icache_line_size = 128;
6298 /* Allocate hardware IRQ controller */
6299 ppc970_irq_init(env);
6300 /* Can't find information on what this should be on reset. This
6301 * value is the one used by 74xx processors. */
6302 vscr_init(env, 0x00010000);
6303 }
6304
6305 /* PowerPC 970 GX */
6306 #define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6307 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6308 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6309 PPC_FLOAT_STFIWX | \
6310 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6311 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6312 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6313 PPC_64B | PPC_ALTIVEC | \
6314 PPC_SEGMENT_64B | PPC_SLBI)
6315 #define POWERPC_INSNS2_970GX (PPC_NONE)
6316 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
6317 #define POWERPC_MMU_970GX (POWERPC_MMU_64B)
6318 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6319 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
6320 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
6321 #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6322 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6323 POWERPC_FLAG_BUS_CLK)
6324
6325 static int check_pow_970GX (CPUPPCState *env)
6326 {
6327 if (env->spr[SPR_HID0] & 0x00600000)
6328 return 1;
6329
6330 return 0;
6331 }
6332
6333 static void init_proc_970GX (CPUPPCState *env)
6334 {
6335 gen_spr_ne_601(env);
6336 gen_spr_7xx(env);
6337 /* Time base */
6338 gen_tbl(env);
6339 /* Hardware implementation registers */
6340 /* XXX : not implemented */
6341 spr_register(env, SPR_HID0, "HID0",
6342 SPR_NOACCESS, SPR_NOACCESS,
6343 &spr_read_generic, &spr_write_clear,
6344 0x60000000);
6345 /* XXX : not implemented */
6346 spr_register(env, SPR_HID1, "HID1",
6347 SPR_NOACCESS, SPR_NOACCESS,
6348 &spr_read_generic, &spr_write_generic,
6349 0x00000000);
6350 /* XXX : not implemented */
6351 spr_register(env, SPR_750FX_HID2, "HID2",
6352 SPR_NOACCESS, SPR_NOACCESS,
6353 &spr_read_generic, &spr_write_generic,
6354 0x00000000);
6355 /* XXX : not implemented */
6356 spr_register(env, SPR_970_HID5, "HID5",
6357 SPR_NOACCESS, SPR_NOACCESS,
6358 &spr_read_generic, &spr_write_generic,
6359 POWERPC970_HID5_INIT);
6360 /* XXX : not implemented */
6361 spr_register(env, SPR_L2CR, "L2CR",
6362 SPR_NOACCESS, SPR_NOACCESS,
6363 &spr_read_generic, &spr_write_generic,
6364 0x00000000);
6365 /* Memory management */
6366 /* XXX: not correct */
6367 gen_low_BATs(env);
6368 /* XXX : not implemented */
6369 spr_register(env, SPR_MMUCFG, "MMUCFG",
6370 SPR_NOACCESS, SPR_NOACCESS,
6371 &spr_read_generic, SPR_NOACCESS,
6372 0x00000000); /* TOFIX */
6373 /* XXX : not implemented */
6374 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6375 SPR_NOACCESS, SPR_NOACCESS,
6376 &spr_read_generic, &spr_write_generic,
6377 0x00000000); /* TOFIX */
6378 spr_register(env, SPR_HIOR, "SPR_HIOR",
6379 SPR_NOACCESS, SPR_NOACCESS,
6380 &spr_read_hior, &spr_write_hior,
6381 0x00000000);
6382 #if !defined(CONFIG_USER_ONLY)
6383 env->slb_nr = 32;
6384 #endif
6385 init_excp_970(env);
6386 env->dcache_line_size = 128;
6387 env->icache_line_size = 128;
6388 /* Allocate hardware IRQ controller */
6389 ppc970_irq_init(env);
6390 /* Can't find information on what this should be on reset. This
6391 * value is the one used by 74xx processors. */
6392 vscr_init(env, 0x00010000);
6393 }
6394
6395 /* PowerPC 970 MP */
6396 #define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6397 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6398 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6399 PPC_FLOAT_STFIWX | \
6400 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6401 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6402 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6403 PPC_64B | PPC_ALTIVEC | \
6404 PPC_SEGMENT_64B | PPC_SLBI)
6405 #define POWERPC_INSNS2_970MP (PPC_NONE)
6406 #define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6407 #define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6408 #define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6409 #define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6410 #define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6411 #define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6412 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6413 POWERPC_FLAG_BUS_CLK)
6414
6415 static int check_pow_970MP (CPUPPCState *env)
6416 {
6417 if (env->spr[SPR_HID0] & 0x01C00000)
6418 return 1;
6419
6420 return 0;
6421 }
6422
6423 static void init_proc_970MP (CPUPPCState *env)
6424 {
6425 gen_spr_ne_601(env);
6426 gen_spr_7xx(env);
6427 /* Time base */
6428 gen_tbl(env);
6429 /* Hardware implementation registers */
6430 /* XXX : not implemented */
6431 spr_register(env, SPR_HID0, "HID0",
6432 SPR_NOACCESS, SPR_NOACCESS,
6433 &spr_read_generic, &spr_write_clear,
6434 0x60000000);
6435 /* XXX : not implemented */
6436 spr_register(env, SPR_HID1, "HID1",
6437 SPR_NOACCESS, SPR_NOACCESS,
6438 &spr_read_generic, &spr_write_generic,
6439 0x00000000);
6440 /* XXX : not implemented */
6441 spr_register(env, SPR_750FX_HID2, "HID2",
6442 SPR_NOACCESS, SPR_NOACCESS,
6443 &spr_read_generic, &spr_write_generic,
6444 0x00000000);
6445 /* XXX : not implemented */
6446 spr_register(env, SPR_970_HID5, "HID5",
6447 SPR_NOACCESS, SPR_NOACCESS,
6448 &spr_read_generic, &spr_write_generic,
6449 POWERPC970_HID5_INIT);
6450 /* XXX : not implemented */
6451 spr_register(env, SPR_L2CR, "L2CR",
6452 SPR_NOACCESS, SPR_NOACCESS,
6453 &spr_read_generic, &spr_write_generic,
6454 0x00000000);
6455 /* Memory management */
6456 /* XXX: not correct */
6457 gen_low_BATs(env);
6458 /* XXX : not implemented */
6459 spr_register(env, SPR_MMUCFG, "MMUCFG",
6460 SPR_NOACCESS, SPR_NOACCESS,
6461 &spr_read_generic, SPR_NOACCESS,
6462 0x00000000); /* TOFIX */
6463 /* XXX : not implemented */
6464 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6465 SPR_NOACCESS, SPR_NOACCESS,
6466 &spr_read_generic, &spr_write_generic,
6467 0x00000000); /* TOFIX */
6468 spr_register(env, SPR_HIOR, "SPR_HIOR",
6469 SPR_NOACCESS, SPR_NOACCESS,
6470 &spr_read_hior, &spr_write_hior,
6471 0x00000000);
6472 #if !defined(CONFIG_USER_ONLY)
6473 env->slb_nr = 32;
6474 #endif
6475 init_excp_970(env);
6476 env->dcache_line_size = 128;
6477 env->icache_line_size = 128;
6478 /* Allocate hardware IRQ controller */
6479 ppc970_irq_init(env);
6480 /* Can't find information on what this should be on reset. This
6481 * value is the one used by 74xx processors. */
6482 vscr_init(env, 0x00010000);
6483 }
6484
6485 #if defined(TARGET_PPC64)
6486 /* POWER7 */
6487 #define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6488 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6489 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6490 PPC_FLOAT_STFIWX | \
6491 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6492 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6493 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6494 PPC_64B | PPC_ALTIVEC | \
6495 PPC_SEGMENT_64B | PPC_SLBI | \
6496 PPC_POPCNTB | PPC_POPCNTWD)
6497 #define POWERPC_INSNS2_POWER7 (PPC_NONE)
6498 #define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
6499 #define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
6500 #define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
6501 #define POWERPC_INPUT_POWER7 (PPC_FLAGS_INPUT_POWER7)
6502 #define POWERPC_BFDM_POWER7 (bfd_mach_ppc64)
6503 #define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6504 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6505 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR)
6506 #define check_pow_POWER7 check_pow_nocheck
6507
6508 static void init_proc_POWER7 (CPUPPCState *env)
6509 {
6510 gen_spr_ne_601(env);
6511 gen_spr_7xx(env);
6512 /* Time base */
6513 gen_tbl(env);
6514 #if !defined(CONFIG_USER_ONLY)
6515 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6516 spr_register(env, SPR_PURR, "PURR",
6517 &spr_read_purr, SPR_NOACCESS,
6518 &spr_read_purr, SPR_NOACCESS,
6519 0x00000000);
6520 spr_register(env, SPR_SPURR, "SPURR",
6521 &spr_read_purr, SPR_NOACCESS,
6522 &spr_read_purr, SPR_NOACCESS,
6523 0x00000000);
6524 spr_register(env, SPR_CFAR, "SPR_CFAR",
6525 SPR_NOACCESS, SPR_NOACCESS,
6526 &spr_read_cfar, &spr_write_cfar,
6527 0x00000000);
6528 spr_register(env, SPR_DSCR, "SPR_DSCR",
6529 SPR_NOACCESS, SPR_NOACCESS,
6530 &spr_read_generic, &spr_write_generic,
6531 0x00000000);
6532 #endif /* !CONFIG_USER_ONLY */
6533 /* Memory management */
6534 /* XXX : not implemented */
6535 spr_register(env, SPR_MMUCFG, "MMUCFG",
6536 SPR_NOACCESS, SPR_NOACCESS,
6537 &spr_read_generic, SPR_NOACCESS,
6538 0x00000000); /* TOFIX */
6539 /* XXX : not implemented */
6540 spr_register(env, SPR_CTRL, "SPR_CTRLT",
6541 SPR_NOACCESS, SPR_NOACCESS,
6542 &spr_read_generic, &spr_write_generic,
6543 0x80800000);
6544 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
6545 SPR_NOACCESS, SPR_NOACCESS,
6546 &spr_read_generic, &spr_write_generic,
6547 0x80800000);
6548 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6549 &spr_read_generic, &spr_write_generic,
6550 &spr_read_generic, &spr_write_generic,
6551 0x00000000);
6552 #if !defined(CONFIG_USER_ONLY)
6553 env->slb_nr = 32;
6554 #endif
6555 init_excp_POWER7(env);
6556 env->dcache_line_size = 128;
6557 env->icache_line_size = 128;
6558 /* Allocate hardware IRQ controller */
6559 ppcPOWER7_irq_init(env);
6560 /* Can't find information on what this should be on reset. This
6561 * value is the one used by 74xx processors. */
6562 vscr_init(env, 0x00010000);
6563 }
6564 #endif /* TARGET_PPC64 */
6565
6566 /* PowerPC 620 */
6567 #define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6568 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6569 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6570 PPC_FLOAT_STFIWX | \
6571 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6572 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6573 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6574 PPC_SEGMENT | PPC_EXTERN | \
6575 PPC_64B | PPC_SLBI)
6576 #define POWERPC_INSNS2_620 (PPC_NONE)
6577 #define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6578 //#define POWERPC_MMU_620 (POWERPC_MMU_620)
6579 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
6580 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
6581 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
6582 #define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
6583 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
6584 #define check_pow_620 check_pow_nocheck /* Check this */
6585
6586 __attribute__ (( unused ))
6587 static void init_proc_620 (CPUPPCState *env)
6588 {
6589 gen_spr_ne_601(env);
6590 gen_spr_620(env);
6591 /* Time base */
6592 gen_tbl(env);
6593 /* Hardware implementation registers */
6594 /* XXX : not implemented */
6595 spr_register(env, SPR_HID0, "HID0",
6596 SPR_NOACCESS, SPR_NOACCESS,
6597 &spr_read_generic, &spr_write_generic,
6598 0x00000000);
6599 /* Memory management */
6600 gen_low_BATs(env);
6601 init_excp_620(env);
6602 env->dcache_line_size = 64;
6603 env->icache_line_size = 64;
6604 /* Allocate hardware IRQ controller */
6605 ppc6xx_irq_init(env);
6606 }
6607 #endif /* defined (TARGET_PPC64) */
6608
6609 /* Default 32 bits PowerPC target will be 604 */
6610 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
6611 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
6612 #define POWERPC_INSNS2_PPC32 POWERPC_INSNS2_604
6613 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6614 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
6615 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6616 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
6617 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
6618 #define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
6619 #define check_pow_PPC32 check_pow_604
6620 #define init_proc_PPC32 init_proc_604
6621
6622 /* Default 64 bits PowerPC target will be 970 FX */
6623 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6624 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
6625 #define POWERPC_INSNS2_PPC64 POWERPC_INSNS2_970FX
6626 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6627 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6628 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6629 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
6630 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
6631 #define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
6632 #define check_pow_PPC64 check_pow_970FX
6633 #define init_proc_PPC64 init_proc_970FX
6634
6635 /* Default PowerPC target will be PowerPC 32 */
6636 #if defined (TARGET_PPC64) && 0 // XXX: TODO
6637 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6638 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6639 #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC64
6640 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6641 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6642 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6643 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6644 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
6645 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
6646 #define check_pow_DEFAULT check_pow_PPC64
6647 #define init_proc_DEFAULT init_proc_PPC64
6648 #else
6649 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6650 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6651 #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC32
6652 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6653 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6654 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6655 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6656 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
6657 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
6658 #define check_pow_DEFAULT check_pow_PPC32
6659 #define init_proc_DEFAULT init_proc_PPC32
6660 #endif
6661
6662 /*****************************************************************************/
6663 /* PVR definitions for most known PowerPC */
6664 enum {
6665 /* PowerPC 401 family */
6666 /* Generic PowerPC 401 */
6667 #define CPU_POWERPC_401 CPU_POWERPC_401G2
6668 /* PowerPC 401 cores */
6669 CPU_POWERPC_401A1 = 0x00210000,
6670 CPU_POWERPC_401B2 = 0x00220000,
6671 #if 0
6672 CPU_POWERPC_401B3 = xxx,
6673 #endif
6674 CPU_POWERPC_401C2 = 0x00230000,
6675 CPU_POWERPC_401D2 = 0x00240000,
6676 CPU_POWERPC_401E2 = 0x00250000,
6677 CPU_POWERPC_401F2 = 0x00260000,
6678 CPU_POWERPC_401G2 = 0x00270000,
6679 /* PowerPC 401 microcontrolers */
6680 #if 0
6681 CPU_POWERPC_401GF = xxx,
6682 #endif
6683 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
6684 /* IBM Processor for Network Resources */
6685 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
6686 #if 0
6687 CPU_POWERPC_XIPCHIP = xxx,
6688 #endif
6689 /* PowerPC 403 family */
6690 /* Generic PowerPC 403 */
6691 #define CPU_POWERPC_403 CPU_POWERPC_403GC
6692 /* PowerPC 403 microcontrollers */
6693 CPU_POWERPC_403GA = 0x00200011,
6694 CPU_POWERPC_403GB = 0x00200100,
6695 CPU_POWERPC_403GC = 0x00200200,
6696 CPU_POWERPC_403GCX = 0x00201400,
6697 #if 0
6698 CPU_POWERPC_403GP = xxx,
6699 #endif
6700 /* PowerPC 405 family */
6701 /* Generic PowerPC 405 */
6702 #define CPU_POWERPC_405 CPU_POWERPC_405D4
6703 /* PowerPC 405 cores */
6704 #if 0
6705 CPU_POWERPC_405A3 = xxx,
6706 #endif
6707 #if 0
6708 CPU_POWERPC_405A4 = xxx,
6709 #endif
6710 #if 0
6711 CPU_POWERPC_405B3 = xxx,
6712 #endif
6713 #if 0
6714 CPU_POWERPC_405B4 = xxx,
6715 #endif
6716 #if 0
6717 CPU_POWERPC_405C3 = xxx,
6718 #endif
6719 #if 0
6720 CPU_POWERPC_405C4 = xxx,
6721 #endif
6722 CPU_POWERPC_405D2 = 0x20010000,
6723 #if 0
6724 CPU_POWERPC_405D3 = xxx,
6725 #endif
6726 CPU_POWERPC_405D4 = 0x41810000,
6727 #if 0
6728 CPU_POWERPC_405D5 = xxx,
6729 #endif
6730 #if 0
6731 CPU_POWERPC_405E4 = xxx,
6732 #endif
6733 #if 0
6734 CPU_POWERPC_405F4 = xxx,
6735 #endif
6736 #if 0
6737 CPU_POWERPC_405F5 = xxx,
6738 #endif
6739 #if 0
6740 CPU_POWERPC_405F6 = xxx,
6741 #endif
6742 /* PowerPC 405 microcontrolers */
6743 /* XXX: missing 0x200108a0 */
6744 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6745 CPU_POWERPC_405CRa = 0x40110041,
6746 CPU_POWERPC_405CRb = 0x401100C5,
6747 CPU_POWERPC_405CRc = 0x40110145,
6748 CPU_POWERPC_405EP = 0x51210950,
6749 #if 0
6750 CPU_POWERPC_405EXr = xxx,
6751 #endif
6752 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
6753 #if 0
6754 CPU_POWERPC_405FX = xxx,
6755 #endif
6756 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6757 CPU_POWERPC_405GPa = 0x40110000,
6758 CPU_POWERPC_405GPb = 0x40110040,
6759 CPU_POWERPC_405GPc = 0x40110082,
6760 CPU_POWERPC_405GPd = 0x401100C4,
6761 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6762 CPU_POWERPC_405GPR = 0x50910951,
6763 #if 0
6764 CPU_POWERPC_405H = xxx,
6765 #endif
6766 #if 0
6767 CPU_POWERPC_405L = xxx,
6768 #endif
6769 CPU_POWERPC_405LP = 0x41F10000,
6770 #if 0
6771 CPU_POWERPC_405PM = xxx,
6772 #endif
6773 #if 0
6774 CPU_POWERPC_405PS = xxx,
6775 #endif
6776 #if 0
6777 CPU_POWERPC_405S = xxx,
6778 #endif
6779 /* IBM network processors */
6780 CPU_POWERPC_NPE405H = 0x414100C0,
6781 CPU_POWERPC_NPE405H2 = 0x41410140,
6782 CPU_POWERPC_NPE405L = 0x416100C0,
6783 CPU_POWERPC_NPE4GS3 = 0x40B10000,
6784 #if 0
6785 CPU_POWERPC_NPCxx1 = xxx,
6786 #endif
6787 #if 0
6788 CPU_POWERPC_NPR161 = xxx,
6789 #endif
6790 #if 0
6791 CPU_POWERPC_LC77700 = xxx,
6792 #endif
6793 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6794 #if 0
6795 CPU_POWERPC_STB01000 = xxx,
6796 #endif
6797 #if 0
6798 CPU_POWERPC_STB01010 = xxx,
6799 #endif
6800 #if 0
6801 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
6802 #endif
6803 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
6804 #if 0
6805 CPU_POWERPC_STB043 = xxx,
6806 #endif
6807 #if 0
6808 CPU_POWERPC_STB045 = xxx,
6809 #endif
6810 CPU_POWERPC_STB04 = 0x41810000,
6811 CPU_POWERPC_STB25 = 0x51510950,
6812 #if 0
6813 CPU_POWERPC_STB130 = xxx,
6814 #endif
6815 /* Xilinx cores */
6816 CPU_POWERPC_X2VP4 = 0x20010820,
6817 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
6818 CPU_POWERPC_X2VP20 = 0x20010860,
6819 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
6820 #if 0
6821 CPU_POWERPC_ZL10310 = xxx,
6822 #endif
6823 #if 0
6824 CPU_POWERPC_ZL10311 = xxx,
6825 #endif
6826 #if 0
6827 CPU_POWERPC_ZL10320 = xxx,
6828 #endif
6829 #if 0
6830 CPU_POWERPC_ZL10321 = xxx,
6831 #endif
6832 /* PowerPC 440 family */
6833 /* Generic PowerPC 440 */
6834 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
6835 /* PowerPC 440 cores */
6836 #if 0
6837 CPU_POWERPC_440A4 = xxx,
6838 #endif
6839 CPU_POWERPC_440_XILINX = 0x7ff21910,
6840 #if 0
6841 CPU_POWERPC_440A5 = xxx,
6842 #endif
6843 #if 0
6844 CPU_POWERPC_440B4 = xxx,
6845 #endif
6846 #if 0
6847 CPU_POWERPC_440F5 = xxx,
6848 #endif
6849 #if 0
6850 CPU_POWERPC_440G5 = xxx,
6851 #endif
6852 #if 0
6853 CPU_POWERPC_440H4 = xxx,
6854 #endif
6855 #if 0
6856 CPU_POWERPC_440H6 = xxx,
6857 #endif
6858 /* PowerPC 440 microcontrolers */
6859 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
6860 CPU_POWERPC_440EPa = 0x42221850,
6861 CPU_POWERPC_440EPb = 0x422218D3,
6862 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
6863 CPU_POWERPC_440GPb = 0x40120440,
6864 CPU_POWERPC_440GPc = 0x40120481,
6865 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
6866 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
6867 CPU_POWERPC_440GRX = 0x200008D0,
6868 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
6869 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
6870 CPU_POWERPC_440GXa = 0x51B21850,
6871 CPU_POWERPC_440GXb = 0x51B21851,
6872 CPU_POWERPC_440GXc = 0x51B21892,
6873 CPU_POWERPC_440GXf = 0x51B21894,
6874 #if 0
6875 CPU_POWERPC_440S = xxx,
6876 #endif
6877 CPU_POWERPC_440SP = 0x53221850,
6878 CPU_POWERPC_440SP2 = 0x53221891,
6879 CPU_POWERPC_440SPE = 0x53421890,
6880 /* PowerPC 460 family */
6881 #if 0
6882 /* Generic PowerPC 464 */
6883 #define CPU_POWERPC_464 CPU_POWERPC_464H90
6884 #endif
6885 /* PowerPC 464 microcontrolers */
6886 #if 0
6887 CPU_POWERPC_464H90 = xxx,
6888 #endif
6889 #if 0
6890 CPU_POWERPC_464H90FP = xxx,
6891 #endif
6892 /* Freescale embedded PowerPC cores */
6893 /* PowerPC MPC 5xx cores (aka RCPU) */
6894 CPU_POWERPC_MPC5xx = 0x00020020,
6895 #define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
6896 #define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
6897 #define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
6898 #define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
6899 #define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
6900 #define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
6901 #define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
6902 #define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
6903 #define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
6904 #define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
6905 #define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
6906 #define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
6907 #define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
6908 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
6909 CPU_POWERPC_MPC8xx = 0x00500000,
6910 #define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
6911 #define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
6912 #define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
6913 #define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
6914 #define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
6915 #define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
6916 #define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
6917 #define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
6918 #define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
6919 #define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
6920 #define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
6921 #define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
6922 #define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
6923 #define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
6924 #define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
6925 /* G2 cores (aka PowerQUICC-II) */
6926 CPU_POWERPC_G2 = 0x00810011,
6927 CPU_POWERPC_G2H4 = 0x80811010,
6928 CPU_POWERPC_G2gp = 0x80821010,
6929 CPU_POWERPC_G2ls = 0x90810010,
6930 CPU_POWERPC_MPC603 = 0x00810100,
6931 CPU_POWERPC_G2_HIP3 = 0x00810101,
6932 CPU_POWERPC_G2_HIP4 = 0x80811014,
6933 /* G2_LE core (aka PowerQUICC-II) */
6934 CPU_POWERPC_G2LE = 0x80820010,
6935 CPU_POWERPC_G2LEgp = 0x80822010,
6936 CPU_POWERPC_G2LEls = 0xA0822010,
6937 CPU_POWERPC_G2LEgp1 = 0x80822011,
6938 CPU_POWERPC_G2LEgp3 = 0x80822013,
6939 /* MPC52xx microcontrollers */
6940 /* XXX: MPC 5121 ? */
6941 #define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
6942 #define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
6943 #define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
6944 #define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
6945 #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
6946 #define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
6947 #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
6948 #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
6949 /* MPC82xx microcontrollers */
6950 #define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
6951 #define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
6952 #define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
6953 #define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
6954 #define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
6955 #define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
6956 #define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
6957 #define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
6958 #define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
6959 #define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
6960 #define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
6961 #define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
6962 #define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
6963 #define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
6964 #define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
6965 #define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
6966 #define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
6967 #define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
6968 #define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
6969 #define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
6970 #define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
6971 #define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
6972 #define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
6973 #define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
6974 #define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
6975 #define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
6976 #define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
6977 #define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
6978 #define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
6979 /* e200 family */
6980 /* e200 cores */
6981 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
6982 #if 0
6983 CPU_POWERPC_e200z0 = xxx,
6984 #endif
6985 #if 0
6986 CPU_POWERPC_e200z1 = xxx,
6987 #endif
6988 #if 0 /* ? */
6989 CPU_POWERPC_e200z3 = 0x81120000,
6990 #endif
6991 CPU_POWERPC_e200z5 = 0x81000000,
6992 CPU_POWERPC_e200z6 = 0x81120000,
6993 /* MPC55xx microcontrollers */
6994 #define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
6995 #if 0
6996 #define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
6997 #define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
6998 #define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
6999 #define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
7000 #define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
7001 #define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
7002 #define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
7003 #define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
7004 #define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
7005 #define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
7006 #define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
7007 #define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
7008 #define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
7009 #define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
7010 #endif
7011 #if 0
7012 #define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
7013 #define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
7014 #endif
7015 #define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
7016 #define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
7017 #define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
7018 #define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
7019 #define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
7020 #define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
7021 /* e300 family */
7022 /* e300 cores */
7023 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
7024 CPU_POWERPC_e300c1 = 0x00830010,
7025 CPU_POWERPC_e300c2 = 0x00840010,
7026 CPU_POWERPC_e300c3 = 0x00850010,
7027 CPU_POWERPC_e300c4 = 0x00860010,
7028 /* MPC83xx microcontrollers */
7029 #define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
7030 #define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
7031 #define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
7032 #define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
7033 #define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
7034 #define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
7035 /* e500 family */
7036 /* e500 cores */
7037 #define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
7038 #define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
7039 #define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
7040 CPU_POWERPC_e500v1_v10 = 0x80200010,
7041 CPU_POWERPC_e500v1_v20 = 0x80200020,
7042 CPU_POWERPC_e500v2_v10 = 0x80210010,
7043 CPU_POWERPC_e500v2_v11 = 0x80210011,
7044 CPU_POWERPC_e500v2_v20 = 0x80210020,
7045 CPU_POWERPC_e500v2_v21 = 0x80210021,
7046 CPU_POWERPC_e500v2_v22 = 0x80210022,
7047 CPU_POWERPC_e500v2_v30 = 0x80210030,
7048 /* MPC85xx microcontrollers */
7049 #define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
7050 #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
7051 #define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
7052 #define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
7053 #define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
7054 #define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
7055 #define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
7056 #define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
7057 #define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
7058 #define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
7059 #define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
7060 #define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
7061 #define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
7062 #define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
7063 #define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
7064 #define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
7065 #define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
7066 #define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
7067 #define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
7068 #define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
7069 #define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
7070 #define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
7071 #define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
7072 #define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
7073 #define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
7074 #define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
7075 #define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
7076 #define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
7077 #define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
7078 #define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
7079 #define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
7080 #define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
7081 #define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
7082 #define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
7083 #define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
7084 #define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
7085 #define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
7086 #define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
7087 #define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
7088 #define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
7089 #define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
7090 #define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
7091 #define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
7092 #define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
7093 #define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
7094 #define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
7095 #define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
7096 #define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
7097 #define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
7098 #define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
7099 #define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
7100 #define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
7101 #define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
7102 #define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
7103 #define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
7104 #define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
7105 #define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
7106 #define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
7107 #define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
7108 #define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
7109 #define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
7110 #define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
7111 #define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
7112 #define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
7113 #define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
7114 #define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
7115 #define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
7116 #define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
7117 #define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
7118 #define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
7119 /* e600 family */
7120 /* e600 cores */
7121 CPU_POWERPC_e600 = 0x80040010,
7122 /* MPC86xx microcontrollers */
7123 #define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
7124 #define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
7125 #define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
7126 /* PowerPC 6xx cores */
7127 #define CPU_POWERPC_601 CPU_POWERPC_601_v2
7128 CPU_POWERPC_601_v0 = 0x00010001,
7129 CPU_POWERPC_601_v1 = 0x00010001,
7130 #define CPU_POWERPC_601v CPU_POWERPC_601_v2
7131 CPU_POWERPC_601_v2 = 0x00010002,
7132 CPU_POWERPC_602 = 0x00050100,
7133 CPU_POWERPC_603 = 0x00030100,
7134 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
7135 CPU_POWERPC_603E_v11 = 0x00060101,
7136 CPU_POWERPC_603E_v12 = 0x00060102,
7137 CPU_POWERPC_603E_v13 = 0x00060103,
7138 CPU_POWERPC_603E_v14 = 0x00060104,
7139 CPU_POWERPC_603E_v22 = 0x00060202,
7140 CPU_POWERPC_603E_v3 = 0x00060300,
7141 CPU_POWERPC_603E_v4 = 0x00060400,
7142 CPU_POWERPC_603E_v41 = 0x00060401,
7143 CPU_POWERPC_603E7t = 0x00071201,
7144 CPU_POWERPC_603E7v = 0x00070100,
7145 CPU_POWERPC_603E7v1 = 0x00070101,
7146 CPU_POWERPC_603E7v2 = 0x00070201,
7147 CPU_POWERPC_603E7 = 0x00070200,
7148 CPU_POWERPC_603P = 0x00070000,
7149 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
7150 /* XXX: missing 0x00040303 (604) */
7151 CPU_POWERPC_604 = 0x00040103,
7152 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
7153 /* XXX: missing 0x00091203 */
7154 /* XXX: missing 0x00092110 */
7155 /* XXX: missing 0x00092120 */
7156 CPU_POWERPC_604E_v10 = 0x00090100,
7157 CPU_POWERPC_604E_v22 = 0x00090202,
7158 CPU_POWERPC_604E_v24 = 0x00090204,
7159 /* XXX: missing 0x000a0100 */
7160 /* XXX: missing 0x00093102 */
7161 CPU_POWERPC_604R = 0x000a0101,
7162 #if 0
7163 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
7164 #endif
7165 /* PowerPC 740/750 cores (aka G3) */
7166 /* XXX: missing 0x00084202 */
7167 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
7168 CPU_POWERPC_7x0_v10 = 0x00080100,
7169 CPU_POWERPC_7x0_v20 = 0x00080200,
7170 CPU_POWERPC_7x0_v21 = 0x00080201,
7171 CPU_POWERPC_7x0_v22 = 0x00080202,
7172 CPU_POWERPC_7x0_v30 = 0x00080300,
7173 CPU_POWERPC_7x0_v31 = 0x00080301,
7174 CPU_POWERPC_740E = 0x00080100,
7175 CPU_POWERPC_750E = 0x00080200,
7176 CPU_POWERPC_7x0P = 0x10080000,
7177 /* XXX: missing 0x00087010 (CL ?) */
7178 #define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
7179 CPU_POWERPC_750CL_v10 = 0x00087200,
7180 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
7181 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
7182 CPU_POWERPC_750CX_v10 = 0x00082100,
7183 CPU_POWERPC_750CX_v20 = 0x00082200,
7184 CPU_POWERPC_750CX_v21 = 0x00082201,
7185 CPU_POWERPC_750CX_v22 = 0x00082202,
7186 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
7187 CPU_POWERPC_750CXE_v21 = 0x00082211,
7188 CPU_POWERPC_750CXE_v22 = 0x00082212,
7189 CPU_POWERPC_750CXE_v23 = 0x00082213,
7190 CPU_POWERPC_750CXE_v24 = 0x00082214,
7191 CPU_POWERPC_750CXE_v24b = 0x00083214,
7192 CPU_POWERPC_750CXE_v30 = 0x00082310,
7193 CPU_POWERPC_750CXE_v31 = 0x00082311,
7194 CPU_POWERPC_750CXE_v31b = 0x00083311,
7195 CPU_POWERPC_750CXR = 0x00083410,
7196 CPU_POWERPC_750FL = 0x70000203,
7197 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
7198 CPU_POWERPC_750FX_v10 = 0x70000100,
7199 CPU_POWERPC_750FX_v20 = 0x70000200,
7200 CPU_POWERPC_750FX_v21 = 0x70000201,
7201 CPU_POWERPC_750FX_v22 = 0x70000202,
7202 CPU_POWERPC_750FX_v23 = 0x70000203,
7203 CPU_POWERPC_750GL = 0x70020102,
7204 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
7205 CPU_POWERPC_750GX_v10 = 0x70020100,
7206 CPU_POWERPC_750GX_v11 = 0x70020101,
7207 CPU_POWERPC_750GX_v12 = 0x70020102,
7208 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
7209 CPU_POWERPC_750L_v20 = 0x00088200,
7210 CPU_POWERPC_750L_v21 = 0x00088201,
7211 CPU_POWERPC_750L_v22 = 0x00088202,
7212 CPU_POWERPC_750L_v30 = 0x00088300,
7213 CPU_POWERPC_750L_v32 = 0x00088302,
7214 /* PowerPC 745/755 cores */
7215 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
7216 CPU_POWERPC_7x5_v10 = 0x00083100,
7217 CPU_POWERPC_7x5_v11 = 0x00083101,
7218 CPU_POWERPC_7x5_v20 = 0x00083200,
7219 CPU_POWERPC_7x5_v21 = 0x00083201,
7220 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
7221 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
7222 CPU_POWERPC_7x5_v24 = 0x00083204,
7223 CPU_POWERPC_7x5_v25 = 0x00083205,
7224 CPU_POWERPC_7x5_v26 = 0x00083206,
7225 CPU_POWERPC_7x5_v27 = 0x00083207,
7226 CPU_POWERPC_7x5_v28 = 0x00083208,
7227 #if 0
7228 CPU_POWERPC_7x5P = xxx,
7229 #endif
7230 /* PowerPC 74xx cores (aka G4) */
7231 /* XXX: missing 0x000C1101 */
7232 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
7233 CPU_POWERPC_7400_v10 = 0x000C0100,
7234 CPU_POWERPC_7400_v11 = 0x000C0101,
7235 CPU_POWERPC_7400_v20 = 0x000C0200,
7236 CPU_POWERPC_7400_v21 = 0x000C0201,
7237 CPU_POWERPC_7400_v22 = 0x000C0202,
7238 CPU_POWERPC_7400_v26 = 0x000C0206,
7239 CPU_POWERPC_7400_v27 = 0x000C0207,
7240 CPU_POWERPC_7400_v28 = 0x000C0208,
7241 CPU_POWERPC_7400_v29 = 0x000C0209,
7242 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
7243 CPU_POWERPC_7410_v10 = 0x800C1100,
7244 CPU_POWERPC_7410_v11 = 0x800C1101,
7245 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
7246 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
7247 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
7248 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
7249 CPU_POWERPC_7448_v10 = 0x80040100,
7250 CPU_POWERPC_7448_v11 = 0x80040101,
7251 CPU_POWERPC_7448_v20 = 0x80040200,
7252 CPU_POWERPC_7448_v21 = 0x80040201,
7253 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
7254 CPU_POWERPC_7450_v10 = 0x80000100,
7255 CPU_POWERPC_7450_v11 = 0x80000101,
7256 CPU_POWERPC_7450_v12 = 0x80000102,
7257 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
7258 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
7259 #define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
7260 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
7261 /* XXX: this entry might be a bug in some documentation */
7262 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
7263 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
7264 CPU_POWERPC_74x5_v10 = 0x80010100,
7265 /* XXX: missing 0x80010200 */
7266 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
7267 CPU_POWERPC_74x5_v32 = 0x80010302,
7268 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
7269 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
7270 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
7271 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
7272 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
7273 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
7274 #define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
7275 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
7276 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
7277 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
7278 /* 64 bits PowerPC */
7279 #if defined(TARGET_PPC64)
7280 CPU_POWERPC_620 = 0x00140000,
7281 CPU_POWERPC_630 = 0x00400000,
7282 CPU_POWERPC_631 = 0x00410104,
7283 CPU_POWERPC_POWER4 = 0x00350000,
7284 CPU_POWERPC_POWER4P = 0x00380000,
7285 /* XXX: missing 0x003A0201 */
7286 CPU_POWERPC_POWER5 = 0x003A0203,
7287 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
7288 CPU_POWERPC_POWER5P = 0x003B0000,
7289 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
7290 CPU_POWERPC_POWER6 = 0x003E0000,
7291 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
7292 CPU_POWERPC_POWER6A = 0x0F000002,
7293 #define CPU_POWERPC_POWER7 CPU_POWERPC_POWER7_v20
7294 CPU_POWERPC_POWER7_v20 = 0x003F0200,
7295 CPU_POWERPC_970 = 0x00390202,
7296 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
7297 CPU_POWERPC_970FX_v10 = 0x00391100,
7298 CPU_POWERPC_970FX_v20 = 0x003C0200,
7299 CPU_POWERPC_970FX_v21 = 0x003C0201,
7300 CPU_POWERPC_970FX_v30 = 0x003C0300,
7301 CPU_POWERPC_970FX_v31 = 0x003C0301,
7302 CPU_POWERPC_970GX = 0x00450000,
7303 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
7304 CPU_POWERPC_970MP_v10 = 0x00440100,
7305 CPU_POWERPC_970MP_v11 = 0x00440101,
7306 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
7307 CPU_POWERPC_CELL_v10 = 0x00700100,
7308 CPU_POWERPC_CELL_v20 = 0x00700400,
7309 CPU_POWERPC_CELL_v30 = 0x00700500,
7310 CPU_POWERPC_CELL_v31 = 0x00700501,
7311 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
7312 CPU_POWERPC_RS64 = 0x00330000,
7313 CPU_POWERPC_RS64II = 0x00340000,
7314 CPU_POWERPC_RS64III = 0x00360000,
7315 CPU_POWERPC_RS64IV = 0x00370000,
7316 #endif /* defined(TARGET_PPC64) */
7317 /* Original POWER */
7318 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7319 * POWER2 (RIOS2) & RSC2 (P2SC) here
7320 */
7321 #if 0
7322 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
7323 #endif
7324 #if 0
7325 CPU_POWER2 = xxx, /* 0x40000 ? */
7326 #endif
7327 /* PA Semi core */
7328 CPU_POWERPC_PA6T = 0x00900000,
7329 };
7330
7331 /* System version register (used on MPC 8xxx) */
7332 enum {
7333 POWERPC_SVR_NONE = 0x00000000,
7334 #define POWERPC_SVR_52xx POWERPC_SVR_5200
7335 #define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7336 POWERPC_SVR_5200_v10 = 0x80110010,
7337 POWERPC_SVR_5200_v11 = 0x80110011,
7338 POWERPC_SVR_5200_v12 = 0x80110012,
7339 #define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7340 POWERPC_SVR_5200B_v20 = 0x80110020,
7341 POWERPC_SVR_5200B_v21 = 0x80110021,
7342 #define POWERPC_SVR_55xx POWERPC_SVR_5567
7343 #if 0
7344 POWERPC_SVR_5533 = xxx,
7345 #endif
7346 #if 0
7347 POWERPC_SVR_5534 = xxx,
7348 #endif
7349 #if 0
7350 POWERPC_SVR_5553 = xxx,
7351 #endif
7352 #if 0
7353 POWERPC_SVR_5554 = xxx,
7354 #endif
7355 #if 0
7356 POWERPC_SVR_5561 = xxx,
7357 #endif
7358 #if 0
7359 POWERPC_SVR_5565 = xxx,
7360 #endif
7361 #if 0
7362 POWERPC_SVR_5566 = xxx,
7363 #endif
7364 #if 0
7365 POWERPC_SVR_5567 = xxx,
7366 #endif
7367 #if 0
7368 POWERPC_SVR_8313 = xxx,
7369 #endif
7370 #if 0
7371 POWERPC_SVR_8313E = xxx,
7372 #endif
7373 #if 0
7374 POWERPC_SVR_8314 = xxx,
7375 #endif
7376 #if 0
7377 POWERPC_SVR_8314E = xxx,
7378 #endif
7379 #if 0
7380 POWERPC_SVR_8315 = xxx,
7381 #endif
7382 #if 0
7383 POWERPC_SVR_8315E = xxx,
7384 #endif
7385 #if 0
7386 POWERPC_SVR_8321 = xxx,
7387 #endif
7388 #if 0
7389 POWERPC_SVR_8321E = xxx,
7390 #endif
7391 #if 0
7392 POWERPC_SVR_8323 = xxx,
7393 #endif
7394 #if 0
7395 POWERPC_SVR_8323E = xxx,
7396 #endif
7397 POWERPC_SVR_8343 = 0x80570010,
7398 POWERPC_SVR_8343A = 0x80570030,
7399 POWERPC_SVR_8343E = 0x80560010,
7400 POWERPC_SVR_8343EA = 0x80560030,
7401 #define POWERPC_SVR_8347 POWERPC_SVR_8347T
7402 POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
7403 POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
7404 #define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7405 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7406 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
7407 #define POWERPC_SVR_8347E POWERPC_SVR_8347ET
7408 POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
7409 POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
7410 #define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7411 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7412 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7413 POWERPC_SVR_8349 = 0x80510010,
7414 POWERPC_SVR_8349A = 0x80510030,
7415 POWERPC_SVR_8349E = 0x80500010,
7416 POWERPC_SVR_8349EA = 0x80500030,
7417 #if 0
7418 POWERPC_SVR_8358E = xxx,
7419 #endif
7420 #if 0
7421 POWERPC_SVR_8360E = xxx,
7422 #endif
7423 #define POWERPC_SVR_E500 0x40000000
7424 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7425 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7426 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7427 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7428 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7429 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7430 #define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7431 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7432 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7433 #define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7434 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7435 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7436 #define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7437 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7438 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7439 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7440 #define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7441 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7442 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7443 #define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7444 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7445 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7446 #define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7447 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7448 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7449 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7450 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7451 #define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7452 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7453 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7454 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7455 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7456 #define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7457 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7458 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7459 #define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7460 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7461 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7462 #define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7463 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7464 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7465 #define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7466 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7467 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7468 #define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7469 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7470 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7471 #define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7472 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7473 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7474 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7475 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7476 #define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7477 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7478 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7479 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7480 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7481 #define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7482 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7483 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7484 #define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7485 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7486 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7487 #define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7488 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7489 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7490 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7491 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7492 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7493 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7494 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7495 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7496 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
7497 #if 0
7498 POWERPC_SVR_8610 = xxx,
7499 #endif
7500 POWERPC_SVR_8641 = 0x80900021,
7501 POWERPC_SVR_8641D = 0x80900121,
7502 };
7503
7504 /*****************************************************************************/
7505 /* PowerPC CPU definitions */
7506 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
7507 { \
7508 .name = _name, \
7509 .pvr = _pvr, \
7510 .svr = _svr, \
7511 .insns_flags = glue(POWERPC_INSNS_,_type), \
7512 .insns_flags2 = glue(POWERPC_INSNS2_,_type), \
7513 .msr_mask = glue(POWERPC_MSRM_,_type), \
7514 .mmu_model = glue(POWERPC_MMU_,_type), \
7515 .excp_model = glue(POWERPC_EXCP_,_type), \
7516 .bus_model = glue(POWERPC_INPUT_,_type), \
7517 .bfd_mach = glue(POWERPC_BFDM_,_type), \
7518 .flags = glue(POWERPC_FLAG_,_type), \
7519 .init_proc = &glue(init_proc_,_type), \
7520 .check_pow = &glue(check_pow_,_type), \
7521 }
7522 #define POWERPC_DEF(_name, _pvr, _type) \
7523 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
7524
7525 static const ppc_def_t ppc_defs[] = {
7526 /* Embedded PowerPC */
7527 /* PowerPC 401 family */
7528 /* Generic PowerPC 401 */
7529 POWERPC_DEF("401", CPU_POWERPC_401, 401),
7530 /* PowerPC 401 cores */
7531 /* PowerPC 401A1 */
7532 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
7533 /* PowerPC 401B2 */
7534 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
7535 #if defined (TODO)
7536 /* PowerPC 401B3 */
7537 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
7538 #endif
7539 /* PowerPC 401C2 */
7540 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
7541 /* PowerPC 401D2 */
7542 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
7543 /* PowerPC 401E2 */
7544 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
7545 /* PowerPC 401F2 */
7546 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
7547 /* PowerPC 401G2 */
7548 /* XXX: to be checked */
7549 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
7550 /* PowerPC 401 microcontrolers */
7551 #if defined (TODO)
7552 /* PowerPC 401GF */
7553 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
7554 #endif
7555 /* IOP480 (401 microcontroler) */
7556 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
7557 /* IBM Processor for Network Resources */
7558 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
7559 #if defined (TODO)
7560 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
7561 #endif
7562 /* PowerPC 403 family */
7563 /* Generic PowerPC 403 */
7564 POWERPC_DEF("403", CPU_POWERPC_403, 403),
7565 /* PowerPC 403 microcontrolers */
7566 /* PowerPC 403 GA */
7567 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
7568 /* PowerPC 403 GB */
7569 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
7570 /* PowerPC 403 GC */
7571 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
7572 /* PowerPC 403 GCX */
7573 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
7574 #if defined (TODO)
7575 /* PowerPC 403 GP */
7576 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
7577 #endif
7578 /* PowerPC 405 family */
7579 /* Generic PowerPC 405 */
7580 POWERPC_DEF("405", CPU_POWERPC_405, 405),
7581 /* PowerPC 405 cores */
7582 #if defined (TODO)
7583 /* PowerPC 405 A3 */
7584 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
7585 #endif
7586 #if defined (TODO)
7587 /* PowerPC 405 A4 */
7588 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
7589 #endif
7590 #if defined (TODO)
7591 /* PowerPC 405 B3 */
7592 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
7593 #endif
7594 #if defined (TODO)
7595 /* PowerPC 405 B4 */
7596 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
7597 #endif
7598 #if defined (TODO)
7599 /* PowerPC 405 C3 */
7600 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
7601 #endif
7602 #if defined (TODO)
7603 /* PowerPC 405 C4 */
7604 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
7605 #endif
7606 /* PowerPC 405 D2 */
7607 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
7608 #if defined (TODO)
7609 /* PowerPC 405 D3 */
7610 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
7611 #endif
7612 /* PowerPC 405 D4 */
7613 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
7614 #if defined (TODO)
7615 /* PowerPC 405 D5 */
7616 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
7617 #endif
7618 #if defined (TODO)
7619 /* PowerPC 405 E4 */
7620 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
7621 #endif
7622 #if defined (TODO)
7623 /* PowerPC 405 F4 */
7624 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
7625 #endif
7626 #if defined (TODO)
7627 /* PowerPC 405 F5 */
7628 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
7629 #endif
7630 #if defined (TODO)
7631 /* PowerPC 405 F6 */
7632 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
7633 #endif
7634 /* PowerPC 405 microcontrolers */
7635 /* PowerPC 405 CR */
7636 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
7637 /* PowerPC 405 CRa */
7638 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
7639 /* PowerPC 405 CRb */
7640 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
7641 /* PowerPC 405 CRc */
7642 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
7643 /* PowerPC 405 EP */
7644 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
7645 #if defined(TODO)
7646 /* PowerPC 405 EXr */
7647 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
7648 #endif
7649 /* PowerPC 405 EZ */
7650 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
7651 #if defined(TODO)
7652 /* PowerPC 405 FX */
7653 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
7654 #endif
7655 /* PowerPC 405 GP */
7656 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
7657 /* PowerPC 405 GPa */
7658 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
7659 /* PowerPC 405 GPb */
7660 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
7661 /* PowerPC 405 GPc */
7662 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
7663 /* PowerPC 405 GPd */
7664 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
7665 /* PowerPC 405 GPe */
7666 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
7667 /* PowerPC 405 GPR */
7668 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
7669 #if defined(TODO)
7670 /* PowerPC 405 H */
7671 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
7672 #endif
7673 #if defined(TODO)
7674 /* PowerPC 405 L */
7675 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
7676 #endif
7677 /* PowerPC 405 LP */
7678 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
7679 #if defined(TODO)
7680 /* PowerPC 405 PM */
7681 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
7682 #endif
7683 #if defined(TODO)
7684 /* PowerPC 405 PS */
7685 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
7686 #endif
7687 #if defined(TODO)
7688 /* PowerPC 405 S */
7689 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
7690 #endif
7691 /* Npe405 H */
7692 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
7693 /* Npe405 H2 */
7694 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
7695 /* Npe405 L */
7696 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
7697 /* Npe4GS3 */
7698 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
7699 #if defined (TODO)
7700 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
7701 #endif
7702 #if defined (TODO)
7703 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
7704 #endif
7705 #if defined (TODO)
7706 /* PowerPC LC77700 (Sanyo) */
7707 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
7708 #endif
7709 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7710 #if defined (TODO)
7711 /* STB010000 */
7712 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
7713 #endif
7714 #if defined (TODO)
7715 /* STB01010 */
7716 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
7717 #endif
7718 #if defined (TODO)
7719 /* STB0210 */
7720 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
7721 #endif
7722 /* STB03xx */
7723 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
7724 #if defined (TODO)
7725 /* STB043x */
7726 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
7727 #endif
7728 #if defined (TODO)
7729 /* STB045x */
7730 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
7731 #endif
7732 /* STB04xx */
7733 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
7734 /* STB25xx */
7735 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
7736 #if defined (TODO)
7737 /* STB130 */
7738 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
7739 #endif
7740 /* Xilinx PowerPC 405 cores */
7741 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
7742 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
7743 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
7744 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
7745 #if defined (TODO)
7746 /* Zarlink ZL10310 */
7747 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
7748 #endif
7749 #if defined (TODO)
7750 /* Zarlink ZL10311 */
7751 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
7752 #endif
7753 #if defined (TODO)
7754 /* Zarlink ZL10320 */
7755 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
7756 #endif
7757 #if defined (TODO)
7758 /* Zarlink ZL10321 */
7759 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
7760 #endif
7761 /* PowerPC 440 family */
7762 #if defined(TODO_USER_ONLY)
7763 /* Generic PowerPC 440 */
7764 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
7765 #endif
7766 /* PowerPC 440 cores */
7767 #if defined (TODO)
7768 /* PowerPC 440 A4 */
7769 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
7770 #endif
7771 /* PowerPC 440 Xilinx 5 */
7772 POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5),
7773 #if defined (TODO)
7774 /* PowerPC 440 A5 */
7775 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
7776 #endif
7777 #if defined (TODO)
7778 /* PowerPC 440 B4 */
7779 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
7780 #endif
7781 #if defined (TODO)
7782 /* PowerPC 440 G4 */
7783 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
7784 #endif
7785 #if defined (TODO)
7786 /* PowerPC 440 F5 */
7787 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
7788 #endif
7789 #if defined (TODO)
7790 /* PowerPC 440 G5 */
7791 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
7792 #endif
7793 #if defined (TODO)
7794 /* PowerPC 440H4 */
7795 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
7796 #endif
7797 #if defined (TODO)
7798 /* PowerPC 440H6 */
7799 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
7800 #endif
7801 /* PowerPC 440 microcontrolers */
7802 #if defined(TODO_USER_ONLY)
7803 /* PowerPC 440 EP */
7804 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
7805 #endif
7806 #if defined(TODO_USER_ONLY)
7807 /* PowerPC 440 EPa */
7808 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
7809 #endif
7810 #if defined(TODO_USER_ONLY)
7811 /* PowerPC 440 EPb */
7812 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
7813 #endif
7814 #if defined(TODO_USER_ONLY)
7815 /* PowerPC 440 EPX */
7816 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
7817 #endif
7818 #if defined(TODO_USER_ONLY)
7819 /* PowerPC 440 GP */
7820 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
7821 #endif
7822 #if defined(TODO_USER_ONLY)
7823 /* PowerPC 440 GPb */
7824 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
7825 #endif
7826 #if defined(TODO_USER_ONLY)
7827 /* PowerPC 440 GPc */
7828 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
7829 #endif
7830 #if defined(TODO_USER_ONLY)
7831 /* PowerPC 440 GR */
7832 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
7833 #endif
7834 #if defined(TODO_USER_ONLY)
7835 /* PowerPC 440 GRa */
7836 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
7837 #endif
7838 #if defined(TODO_USER_ONLY)
7839 /* PowerPC 440 GRX */
7840 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
7841 #endif
7842 #if defined(TODO_USER_ONLY)
7843 /* PowerPC 440 GX */
7844 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
7845 #endif
7846 #if defined(TODO_USER_ONLY)
7847 /* PowerPC 440 GXa */
7848 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
7849 #endif
7850 #if defined(TODO_USER_ONLY)
7851 /* PowerPC 440 GXb */
7852 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
7853 #endif
7854 #if defined(TODO_USER_ONLY)
7855 /* PowerPC 440 GXc */
7856 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
7857 #endif
7858 #if defined(TODO_USER_ONLY)
7859 /* PowerPC 440 GXf */
7860 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
7861 #endif
7862 #if defined(TODO)
7863 /* PowerPC 440 S */
7864 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
7865 #endif
7866 #if defined(TODO_USER_ONLY)
7867 /* PowerPC 440 SP */
7868 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
7869 #endif
7870 #if defined(TODO_USER_ONLY)
7871 /* PowerPC 440 SP2 */
7872 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
7873 #endif
7874 #if defined(TODO_USER_ONLY)
7875 /* PowerPC 440 SPE */
7876 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
7877 #endif
7878 /* PowerPC 460 family */
7879 #if defined (TODO)
7880 /* Generic PowerPC 464 */
7881 POWERPC_DEF("464", CPU_POWERPC_464, 460),
7882 #endif
7883 /* PowerPC 464 microcontrolers */
7884 #if defined (TODO)
7885 /* PowerPC 464H90 */
7886 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
7887 #endif
7888 #if defined (TODO)
7889 /* PowerPC 464H90F */
7890 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
7891 #endif
7892 /* Freescale embedded PowerPC cores */
7893 /* MPC5xx family (aka RCPU) */
7894 #if defined(TODO_USER_ONLY)
7895 /* Generic MPC5xx core */
7896 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
7897 #endif
7898 #if defined(TODO_USER_ONLY)
7899 /* Codename for MPC5xx core */
7900 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
7901 #endif
7902 /* MPC5xx microcontrollers */
7903 #if defined(TODO_USER_ONLY)
7904 /* MGT560 */
7905 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
7906 #endif
7907 #if defined(TODO_USER_ONLY)
7908 /* MPC509 */
7909 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
7910 #endif
7911 #if defined(TODO_USER_ONLY)
7912 /* MPC533 */
7913 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
7914 #endif
7915 #if defined(TODO_USER_ONLY)
7916 /* MPC534 */
7917 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
7918 #endif
7919 #if defined(TODO_USER_ONLY)
7920 /* MPC555 */
7921 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
7922 #endif
7923 #if defined(TODO_USER_ONLY)
7924 /* MPC556 */
7925 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
7926 #endif
7927 #if defined(TODO_USER_ONLY)
7928 /* MPC560 */
7929 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
7930 #endif
7931 #if defined(TODO_USER_ONLY)
7932 /* MPC561 */
7933 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
7934 #endif
7935 #if defined(TODO_USER_ONLY)
7936 /* MPC562 */
7937 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
7938 #endif
7939 #if defined(TODO_USER_ONLY)
7940 /* MPC563 */
7941 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
7942 #endif
7943 #if defined(TODO_USER_ONLY)
7944 /* MPC564 */
7945 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
7946 #endif
7947 #if defined(TODO_USER_ONLY)
7948 /* MPC565 */
7949 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
7950 #endif
7951 #if defined(TODO_USER_ONLY)
7952 /* MPC566 */
7953 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
7954 #endif
7955 /* MPC8xx family (aka PowerQUICC) */
7956 #if defined(TODO_USER_ONLY)
7957 /* Generic MPC8xx core */
7958 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
7959 #endif
7960 #if defined(TODO_USER_ONLY)
7961 /* Codename for MPC8xx core */
7962 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
7963 #endif
7964 /* MPC8xx microcontrollers */
7965 #if defined(TODO_USER_ONLY)
7966 /* MGT823 */
7967 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
7968 #endif
7969 #if defined(TODO_USER_ONLY)
7970 /* MPC821 */
7971 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
7972 #endif
7973 #if defined(TODO_USER_ONLY)
7974 /* MPC823 */
7975 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
7976 #endif
7977 #if defined(TODO_USER_ONLY)
7978 /* MPC850 */
7979 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
7980 #endif
7981 #if defined(TODO_USER_ONLY)
7982 /* MPC852T */
7983 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
7984 #endif
7985 #if defined(TODO_USER_ONLY)
7986 /* MPC855T */
7987 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
7988 #endif
7989 #if defined(TODO_USER_ONLY)
7990 /* MPC857 */
7991 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
7992 #endif
7993 #if defined(TODO_USER_ONLY)
7994 /* MPC859 */
7995 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
7996 #endif
7997 #if defined(TODO_USER_ONLY)
7998 /* MPC860 */
7999 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
8000 #endif
8001 #if defined(TODO_USER_ONLY)
8002 /* MPC862 */
8003 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
8004 #endif
8005 #if defined(TODO_USER_ONLY)
8006 /* MPC866 */
8007 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
8008 #endif
8009 #if defined(TODO_USER_ONLY)
8010 /* MPC870 */
8011 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
8012 #endif
8013 #if defined(TODO_USER_ONLY)
8014 /* MPC875 */
8015 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
8016 #endif
8017 #if defined(TODO_USER_ONLY)
8018 /* MPC880 */
8019 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
8020 #endif
8021 #if defined(TODO_USER_ONLY)
8022 /* MPC885 */
8023 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
8024 #endif
8025 /* MPC82xx family (aka PowerQUICC-II) */
8026 /* Generic MPC52xx core */
8027 POWERPC_DEF_SVR("MPC52xx",
8028 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
8029 /* Generic MPC82xx core */
8030 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
8031 /* Codename for MPC82xx */
8032 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
8033 /* PowerPC G2 core */
8034 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
8035 /* PowerPC G2 H4 core */
8036 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
8037 /* PowerPC G2 GP core */
8038 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
8039 /* PowerPC G2 LS core */
8040 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
8041 /* PowerPC G2 HiP3 core */
8042 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
8043 /* PowerPC G2 HiP4 core */
8044 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
8045 /* PowerPC MPC603 core */
8046 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
8047 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
8048 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
8049 /* PowerPC G2LE GP core */
8050 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
8051 /* PowerPC G2LE LS core */
8052 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
8053 /* PowerPC G2LE GP1 core */
8054 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
8055 /* PowerPC G2LE GP3 core */
8056 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
8057 /* PowerPC MPC603 microcontrollers */
8058 /* MPC8240 */
8059 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
8060 /* PowerPC G2 microcontrollers */
8061 #if defined(TODO)
8062 /* MPC5121 */
8063 POWERPC_DEF_SVR("MPC5121",
8064 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
8065 #endif
8066 /* MPC5200 */
8067 POWERPC_DEF_SVR("MPC5200",
8068 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
8069 /* MPC5200 v1.0 */
8070 POWERPC_DEF_SVR("MPC5200_v10",
8071 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
8072 /* MPC5200 v1.1 */
8073 POWERPC_DEF_SVR("MPC5200_v11",
8074 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
8075 /* MPC5200 v1.2 */
8076 POWERPC_DEF_SVR("MPC5200_v12",
8077 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
8078 /* MPC5200B */
8079 POWERPC_DEF_SVR("MPC5200B",
8080 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
8081 /* MPC5200B v2.0 */
8082 POWERPC_DEF_SVR("MPC5200B_v20",
8083 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
8084 /* MPC5200B v2.1 */
8085 POWERPC_DEF_SVR("MPC5200B_v21",
8086 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
8087 /* MPC8241 */
8088 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
8089 /* MPC8245 */
8090 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
8091 /* MPC8247 */
8092 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
8093 /* MPC8248 */
8094 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
8095 /* MPC8250 */
8096 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
8097 /* MPC8250 HiP3 */
8098 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
8099 /* MPC8250 HiP4 */
8100 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
8101 /* MPC8255 */
8102 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
8103 /* MPC8255 HiP3 */
8104 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
8105 /* MPC8255 HiP4 */
8106 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
8107 /* MPC8260 */
8108 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
8109 /* MPC8260 HiP3 */
8110 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
8111 /* MPC8260 HiP4 */
8112 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
8113 /* MPC8264 */
8114 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
8115 /* MPC8264 HiP3 */
8116 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
8117 /* MPC8264 HiP4 */
8118 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
8119 /* MPC8265 */
8120 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
8121 /* MPC8265 HiP3 */
8122 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
8123 /* MPC8265 HiP4 */
8124 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
8125 /* MPC8266 */
8126 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
8127 /* MPC8266 HiP3 */
8128 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
8129 /* MPC8266 HiP4 */
8130 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
8131 /* MPC8270 */
8132 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
8133 /* MPC8271 */
8134 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
8135 /* MPC8272 */
8136 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
8137 /* MPC8275 */
8138 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
8139 /* MPC8280 */
8140 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
8141 /* e200 family */
8142 /* Generic PowerPC e200 core */
8143 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
8144 /* Generic MPC55xx core */
8145 #if defined (TODO)
8146 POWERPC_DEF_SVR("MPC55xx",
8147 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
8148 #endif
8149 #if defined (TODO)
8150 /* PowerPC e200z0 core */
8151 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
8152 #endif
8153 #if defined (TODO)
8154 /* PowerPC e200z1 core */
8155 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
8156 #endif
8157 #if defined (TODO)
8158 /* PowerPC e200z3 core */
8159 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
8160 #endif
8161 /* PowerPC e200z5 core */
8162 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
8163 /* PowerPC e200z6 core */
8164 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
8165 /* PowerPC e200 microcontrollers */
8166 #if defined (TODO)
8167 /* MPC5514E */
8168 POWERPC_DEF_SVR("MPC5514E",
8169 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
8170 #endif
8171 #if defined (TODO)
8172 /* MPC5514E v0 */
8173 POWERPC_DEF_SVR("MPC5514E_v0",
8174 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
8175 #endif
8176 #if defined (TODO)
8177 /* MPC5514E v1 */
8178 POWERPC_DEF_SVR("MPC5514E_v1",
8179 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
8180 #endif
8181 #if defined (TODO)
8182 /* MPC5514G */
8183 POWERPC_DEF_SVR("MPC5514G",
8184 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
8185 #endif
8186 #if defined (TODO)
8187 /* MPC5514G v0 */
8188 POWERPC_DEF_SVR("MPC5514G_v0",
8189 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
8190 #endif
8191 #if defined (TODO)
8192 /* MPC5514G v1 */
8193 POWERPC_DEF_SVR("MPC5514G_v1",
8194 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
8195 #endif
8196 #if defined (TODO)
8197 /* MPC5515S */
8198 POWERPC_DEF_SVR("MPC5515S",
8199 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
8200 #endif
8201 #if defined (TODO)
8202 /* MPC5516E */
8203 POWERPC_DEF_SVR("MPC5516E",
8204 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
8205 #endif
8206 #if defined (TODO)
8207 /* MPC5516E v0 */
8208 POWERPC_DEF_SVR("MPC5516E_v0",
8209 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
8210 #endif
8211 #if defined (TODO)
8212 /* MPC5516E v1 */
8213 POWERPC_DEF_SVR("MPC5516E_v1",
8214 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
8215 #endif
8216 #if defined (TODO)
8217 /* MPC5516G */
8218 POWERPC_DEF_SVR("MPC5516G",
8219 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
8220 #endif
8221 #if defined (TODO)
8222 /* MPC5516G v0 */
8223 POWERPC_DEF_SVR("MPC5516G_v0",
8224 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
8225 #endif
8226 #if defined (TODO)
8227 /* MPC5516G v1 */
8228 POWERPC_DEF_SVR("MPC5516G_v1",
8229 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
8230 #endif
8231 #if defined (TODO)
8232 /* MPC5516S */
8233 POWERPC_DEF_SVR("MPC5516S",
8234 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
8235 #endif
8236 #if defined (TODO)
8237 /* MPC5533 */
8238 POWERPC_DEF_SVR("MPC5533",
8239 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
8240 #endif
8241 #if defined (TODO)
8242 /* MPC5534 */
8243 POWERPC_DEF_SVR("MPC5534",
8244 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
8245 #endif
8246 #if defined (TODO)
8247 /* MPC5553 */
8248 POWERPC_DEF_SVR("MPC5553",
8249 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
8250 #endif
8251 #if defined (TODO)
8252 /* MPC5554 */
8253 POWERPC_DEF_SVR("MPC5554",
8254 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
8255 #endif
8256 #if defined (TODO)
8257 /* MPC5561 */
8258 POWERPC_DEF_SVR("MPC5561",
8259 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
8260 #endif
8261 #if defined (TODO)
8262 /* MPC5565 */
8263 POWERPC_DEF_SVR("MPC5565",
8264 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
8265 #endif
8266 #if defined (TODO)
8267 /* MPC5566 */
8268 POWERPC_DEF_SVR("MPC5566",
8269 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
8270 #endif
8271 #if defined (TODO)
8272 /* MPC5567 */
8273 POWERPC_DEF_SVR("MPC5567",
8274 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
8275 #endif
8276 /* e300 family */
8277 /* Generic PowerPC e300 core */
8278 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
8279 /* PowerPC e300c1 core */
8280 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
8281 /* PowerPC e300c2 core */
8282 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
8283 /* PowerPC e300c3 core */
8284 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
8285 /* PowerPC e300c4 core */
8286 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
8287 /* PowerPC e300 microcontrollers */
8288 #if defined (TODO)
8289 /* MPC8313 */
8290 POWERPC_DEF_SVR("MPC8313",
8291 CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300),
8292 #endif
8293 #if defined (TODO)
8294 /* MPC8313E */
8295 POWERPC_DEF_SVR("MPC8313E",
8296 CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300),
8297 #endif
8298 #if defined (TODO)
8299 /* MPC8314 */
8300 POWERPC_DEF_SVR("MPC8314",
8301 CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300),
8302 #endif
8303 #if defined (TODO)
8304 /* MPC8314E */
8305 POWERPC_DEF_SVR("MPC8314E",
8306 CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300),
8307 #endif
8308 #if defined (TODO)
8309 /* MPC8315 */
8310 POWERPC_DEF_SVR("MPC8315",
8311 CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300),
8312 #endif
8313 #if defined (TODO)
8314 /* MPC8315E */
8315 POWERPC_DEF_SVR("MPC8315E",
8316 CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300),
8317 #endif
8318 #if defined (TODO)
8319 /* MPC8321 */
8320 POWERPC_DEF_SVR("MPC8321",
8321 CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300),
8322 #endif
8323 #if defined (TODO)
8324 /* MPC8321E */
8325 POWERPC_DEF_SVR("MPC8321E",
8326 CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300),
8327 #endif
8328 #if defined (TODO)
8329 /* MPC8323 */
8330 POWERPC_DEF_SVR("MPC8323",
8331 CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300),
8332 #endif
8333 #if defined (TODO)
8334 /* MPC8323E */
8335 POWERPC_DEF_SVR("MPC8323E",
8336 CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300),
8337 #endif
8338 /* MPC8343 */
8339 POWERPC_DEF_SVR("MPC8343",
8340 CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300),
8341 /* MPC8343A */
8342 POWERPC_DEF_SVR("MPC8343A",
8343 CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300),
8344 /* MPC8343E */
8345 POWERPC_DEF_SVR("MPC8343E",
8346 CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300),
8347 /* MPC8343EA */
8348 POWERPC_DEF_SVR("MPC8343EA",
8349 CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300),
8350 /* MPC8347 */
8351 POWERPC_DEF_SVR("MPC8347",
8352 CPU_POWERPC_MPC834x, POWERPC_SVR_8347, e300),
8353 /* MPC8347T */
8354 POWERPC_DEF_SVR("MPC8347T",
8355 CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300),
8356 /* MPC8347P */
8357 POWERPC_DEF_SVR("MPC8347P",
8358 CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300),
8359 /* MPC8347A */
8360 POWERPC_DEF_SVR("MPC8347A",
8361 CPU_POWERPC_MPC834x, POWERPC_SVR_8347A, e300),
8362 /* MPC8347AT */
8363 POWERPC_DEF_SVR("MPC8347AT",
8364 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300),
8365 /* MPC8347AP */
8366 POWERPC_DEF_SVR("MPC8347AP",
8367 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300),
8368 /* MPC8347E */
8369 POWERPC_DEF_SVR("MPC8347E",
8370 CPU_POWERPC_MPC834x, POWERPC_SVR_8347E, e300),
8371 /* MPC8347ET */
8372 POWERPC_DEF_SVR("MPC8347ET",
8373 CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300),
8374 /* MPC8343EP */
8375 POWERPC_DEF_SVR("MPC8347EP",
8376 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300),
8377 /* MPC8347EA */
8378 POWERPC_DEF_SVR("MPC8347EA",
8379 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EA, e300),
8380 /* MPC8347EAT */
8381 POWERPC_DEF_SVR("MPC8347EAT",
8382 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300),
8383 /* MPC8343EAP */
8384 POWERPC_DEF_SVR("MPC8347EAP",
8385 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300),
8386 /* MPC8349 */
8387 POWERPC_DEF_SVR("MPC8349",
8388 CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300),
8389 /* MPC8349A */
8390 POWERPC_DEF_SVR("MPC8349A",
8391 CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300),
8392 /* MPC8349E */
8393 POWERPC_DEF_SVR("MPC8349E",
8394 CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300),
8395 /* MPC8349EA */
8396 POWERPC_DEF_SVR("MPC8349EA",
8397 CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300),
8398 #if defined (TODO)
8399 /* MPC8358E */
8400 POWERPC_DEF_SVR("MPC8358E",
8401 CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300),
8402 #endif
8403 #if defined (TODO)
8404 /* MPC8360E */
8405 POWERPC_DEF_SVR("MPC8360E",
8406 CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300),
8407 #endif
8408 /* MPC8377 */
8409 POWERPC_DEF_SVR("MPC8377",
8410 CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300),
8411 /* MPC8377E */
8412 POWERPC_DEF_SVR("MPC8377E",
8413 CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300),
8414 /* MPC8378 */
8415 POWERPC_DEF_SVR("MPC8378",
8416 CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300),
8417 /* MPC8378E */
8418 POWERPC_DEF_SVR("MPC8378E",
8419 CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300),
8420 /* MPC8379 */
8421 POWERPC_DEF_SVR("MPC8379",
8422 CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300),
8423 /* MPC8379E */
8424 POWERPC_DEF_SVR("MPC8379E",
8425 CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300),
8426 /* e500 family */
8427 /* PowerPC e500 core */
8428 POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
8429 /* PowerPC e500v1 core */
8430 POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
8431 /* PowerPC e500 v1.0 core */
8432 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
8433 /* PowerPC e500 v2.0 core */
8434 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
8435 /* PowerPC e500v2 core */
8436 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
8437 /* PowerPC e500v2 v1.0 core */
8438 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
8439 /* PowerPC e500v2 v2.0 core */
8440 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
8441 /* PowerPC e500v2 v2.1 core */
8442 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
8443 /* PowerPC e500v2 v2.2 core */
8444 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
8445 /* PowerPC e500v2 v3.0 core */
8446 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
8447 /* PowerPC e500 microcontrollers */
8448 /* MPC8533 */
8449 POWERPC_DEF_SVR("MPC8533",
8450 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2),
8451 /* MPC8533 v1.0 */
8452 POWERPC_DEF_SVR("MPC8533_v10",
8453 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2),
8454 /* MPC8533 v1.1 */
8455 POWERPC_DEF_SVR("MPC8533_v11",
8456 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2),
8457 /* MPC8533E */
8458 POWERPC_DEF_SVR("MPC8533E",
8459 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2),
8460 /* MPC8533E v1.0 */
8461 POWERPC_DEF_SVR("MPC8533E_v10",
8462 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
8463 POWERPC_DEF_SVR("MPC8533E_v11",
8464 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
8465 /* MPC8540 */
8466 POWERPC_DEF_SVR("MPC8540",
8467 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1),
8468 /* MPC8540 v1.0 */
8469 POWERPC_DEF_SVR("MPC8540_v10",
8470 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1),
8471 /* MPC8540 v2.0 */
8472 POWERPC_DEF_SVR("MPC8540_v20",
8473 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1),
8474 /* MPC8540 v2.1 */
8475 POWERPC_DEF_SVR("MPC8540_v21",
8476 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1),
8477 /* MPC8541 */
8478 POWERPC_DEF_SVR("MPC8541",
8479 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1),
8480 /* MPC8541 v1.0 */
8481 POWERPC_DEF_SVR("MPC8541_v10",
8482 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1),
8483 /* MPC8541 v1.1 */
8484 POWERPC_DEF_SVR("MPC8541_v11",
8485 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1),
8486 /* MPC8541E */
8487 POWERPC_DEF_SVR("MPC8541E",
8488 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1),
8489 /* MPC8541E v1.0 */
8490 POWERPC_DEF_SVR("MPC8541E_v10",
8491 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
8492 /* MPC8541E v1.1 */
8493 POWERPC_DEF_SVR("MPC8541E_v11",
8494 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
8495 /* MPC8543 */
8496 POWERPC_DEF_SVR("MPC8543",
8497 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2),
8498 /* MPC8543 v1.0 */
8499 POWERPC_DEF_SVR("MPC8543_v10",
8500 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2),
8501 /* MPC8543 v1.1 */
8502 POWERPC_DEF_SVR("MPC8543_v11",
8503 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2),
8504 /* MPC8543 v2.0 */
8505 POWERPC_DEF_SVR("MPC8543_v20",
8506 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2),
8507 /* MPC8543 v2.1 */
8508 POWERPC_DEF_SVR("MPC8543_v21",
8509 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2),
8510 /* MPC8543E */
8511 POWERPC_DEF_SVR("MPC8543E",
8512 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2),
8513 /* MPC8543E v1.0 */
8514 POWERPC_DEF_SVR("MPC8543E_v10",
8515 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
8516 /* MPC8543E v1.1 */
8517 POWERPC_DEF_SVR("MPC8543E_v11",
8518 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
8519 /* MPC8543E v2.0 */
8520 POWERPC_DEF_SVR("MPC8543E_v20",
8521 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
8522 /* MPC8543E v2.1 */
8523 POWERPC_DEF_SVR("MPC8543E_v21",
8524 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
8525 /* MPC8544 */
8526 POWERPC_DEF_SVR("MPC8544",
8527 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2),
8528 /* MPC8544 v1.0 */
8529 POWERPC_DEF_SVR("MPC8544_v10",
8530 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2),
8531 /* MPC8544 v1.1 */
8532 POWERPC_DEF_SVR("MPC8544_v11",
8533 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2),
8534 /* MPC8544E */
8535 POWERPC_DEF_SVR("MPC8544E",
8536 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2),
8537 /* MPC8544E v1.0 */
8538 POWERPC_DEF_SVR("MPC8544E_v10",
8539 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
8540 /* MPC8544E v1.1 */
8541 POWERPC_DEF_SVR("MPC8544E_v11",
8542 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
8543 /* MPC8545 */
8544 POWERPC_DEF_SVR("MPC8545",
8545 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2),
8546 /* MPC8545 v2.0 */
8547 POWERPC_DEF_SVR("MPC8545_v20",
8548 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2),
8549 /* MPC8545 v2.1 */
8550 POWERPC_DEF_SVR("MPC8545_v21",
8551 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2),
8552 /* MPC8545E */
8553 POWERPC_DEF_SVR("MPC8545E",
8554 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2),
8555 /* MPC8545E v2.0 */
8556 POWERPC_DEF_SVR("MPC8545E_v20",
8557 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
8558 /* MPC8545E v2.1 */
8559 POWERPC_DEF_SVR("MPC8545E_v21",
8560 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
8561 /* MPC8547E */
8562 POWERPC_DEF_SVR("MPC8547E",
8563 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2),
8564 /* MPC8547E v2.0 */
8565 POWERPC_DEF_SVR("MPC8547E_v20",
8566 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
8567 /* MPC8547E v2.1 */
8568 POWERPC_DEF_SVR("MPC8547E_v21",
8569 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
8570 /* MPC8548 */
8571 POWERPC_DEF_SVR("MPC8548",
8572 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2),
8573 /* MPC8548 v1.0 */
8574 POWERPC_DEF_SVR("MPC8548_v10",
8575 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2),
8576 /* MPC8548 v1.1 */
8577 POWERPC_DEF_SVR("MPC8548_v11",
8578 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2),
8579 /* MPC8548 v2.0 */
8580 POWERPC_DEF_SVR("MPC8548_v20",
8581 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2),
8582 /* MPC8548 v2.1 */
8583 POWERPC_DEF_SVR("MPC8548_v21",
8584 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2),
8585 /* MPC8548E */
8586 POWERPC_DEF_SVR("MPC8548E",
8587 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2),
8588 /* MPC8548E v1.0 */
8589 POWERPC_DEF_SVR("MPC8548E_v10",
8590 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
8591 /* MPC8548E v1.1 */
8592 POWERPC_DEF_SVR("MPC8548E_v11",
8593 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
8594 /* MPC8548E v2.0 */
8595 POWERPC_DEF_SVR("MPC8548E_v20",
8596 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
8597 /* MPC8548E v2.1 */
8598 POWERPC_DEF_SVR("MPC8548E_v21",
8599 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
8600 /* MPC8555 */
8601 POWERPC_DEF_SVR("MPC8555",
8602 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2),
8603 /* MPC8555 v1.0 */
8604 POWERPC_DEF_SVR("MPC8555_v10",
8605 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2),
8606 /* MPC8555 v1.1 */
8607 POWERPC_DEF_SVR("MPC8555_v11",
8608 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2),
8609 /* MPC8555E */
8610 POWERPC_DEF_SVR("MPC8555E",
8611 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2),
8612 /* MPC8555E v1.0 */
8613 POWERPC_DEF_SVR("MPC8555E_v10",
8614 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
8615 /* MPC8555E v1.1 */
8616 POWERPC_DEF_SVR("MPC8555E_v11",
8617 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
8618 /* MPC8560 */
8619 POWERPC_DEF_SVR("MPC8560",
8620 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2),
8621 /* MPC8560 v1.0 */
8622 POWERPC_DEF_SVR("MPC8560_v10",
8623 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2),
8624 /* MPC8560 v2.0 */
8625 POWERPC_DEF_SVR("MPC8560_v20",
8626 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2),
8627 /* MPC8560 v2.1 */
8628 POWERPC_DEF_SVR("MPC8560_v21",
8629 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2),
8630 /* MPC8567 */
8631 POWERPC_DEF_SVR("MPC8567",
8632 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2),
8633 /* MPC8567E */
8634 POWERPC_DEF_SVR("MPC8567E",
8635 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2),
8636 /* MPC8568 */
8637 POWERPC_DEF_SVR("MPC8568",
8638 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2),
8639 /* MPC8568E */
8640 POWERPC_DEF_SVR("MPC8568E",
8641 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2),
8642 /* MPC8572 */
8643 POWERPC_DEF_SVR("MPC8572",
8644 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2),
8645 /* MPC8572E */
8646 POWERPC_DEF_SVR("MPC8572E",
8647 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
8648 /* e600 family */
8649 /* PowerPC e600 core */
8650 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
8651 /* PowerPC e600 microcontrollers */
8652 #if defined (TODO)
8653 /* MPC8610 */
8654 POWERPC_DEF_SVR("MPC8610",
8655 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
8656 #endif
8657 /* MPC8641 */
8658 POWERPC_DEF_SVR("MPC8641",
8659 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
8660 /* MPC8641D */
8661 POWERPC_DEF_SVR("MPC8641D",
8662 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
8663 /* 32 bits "classic" PowerPC */
8664 /* PowerPC 6xx family */
8665 /* PowerPC 601 */
8666 POWERPC_DEF("601", CPU_POWERPC_601, 601v),
8667 /* PowerPC 601v0 */
8668 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
8669 /* PowerPC 601v1 */
8670 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
8671 /* PowerPC 601v */
8672 POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
8673 /* PowerPC 601v2 */
8674 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
8675 /* PowerPC 602 */
8676 POWERPC_DEF("602", CPU_POWERPC_602, 602),
8677 /* PowerPC 603 */
8678 POWERPC_DEF("603", CPU_POWERPC_603, 603),
8679 /* Code name for PowerPC 603 */
8680 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
8681 /* PowerPC 603e (aka PID6) */
8682 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
8683 /* Code name for PowerPC 603e */
8684 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
8685 /* PowerPC 603e v1.1 */
8686 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
8687 /* PowerPC 603e v1.2 */
8688 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
8689 /* PowerPC 603e v1.3 */
8690 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
8691 /* PowerPC 603e v1.4 */
8692 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
8693 /* PowerPC 603e v2.2 */
8694 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
8695 /* PowerPC 603e v3 */
8696 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
8697 /* PowerPC 603e v4 */
8698 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
8699 /* PowerPC 603e v4.1 */
8700 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
8701 /* PowerPC 603e (aka PID7) */
8702 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
8703 /* PowerPC 603e7t */
8704 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
8705 /* PowerPC 603e7v */
8706 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
8707 /* Code name for PowerPC 603ev */
8708 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
8709 /* PowerPC 603e7v1 */
8710 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
8711 /* PowerPC 603e7v2 */
8712 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
8713 /* PowerPC 603p (aka PID7v) */
8714 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
8715 /* PowerPC 603r (aka PID7t) */
8716 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
8717 /* Code name for PowerPC 603r */
8718 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
8719 /* PowerPC 604 */
8720 POWERPC_DEF("604", CPU_POWERPC_604, 604),
8721 /* PowerPC 604e (aka PID9) */
8722 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
8723 /* Code name for PowerPC 604e */
8724 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
8725 /* PowerPC 604e v1.0 */
8726 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
8727 /* PowerPC 604e v2.2 */
8728 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
8729 /* PowerPC 604e v2.4 */
8730 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
8731 /* PowerPC 604r (aka PIDA) */
8732 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
8733 /* Code name for PowerPC 604r */
8734 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
8735 #if defined(TODO)
8736 /* PowerPC 604ev */
8737 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
8738 #endif
8739 /* PowerPC 7xx family */
8740 /* Generic PowerPC 740 (G3) */
8741 POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
8742 /* Code name for PowerPC 740 */
8743 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
8744 /* Generic PowerPC 750 (G3) */
8745 POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
8746 /* Code name for PowerPC 750 */
8747 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
8748 /* PowerPC 740/750 is also known as G3 */
8749 POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
8750 /* PowerPC 740 v1.0 (G3) */
8751 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
8752 /* PowerPC 750 v1.0 (G3) */
8753 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
8754 /* PowerPC 740 v2.0 (G3) */
8755 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
8756 /* PowerPC 750 v2.0 (G3) */
8757 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
8758 /* PowerPC 740 v2.1 (G3) */
8759 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
8760 /* PowerPC 750 v2.1 (G3) */
8761 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
8762 /* PowerPC 740 v2.2 (G3) */
8763 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
8764 /* PowerPC 750 v2.2 (G3) */
8765 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
8766 /* PowerPC 740 v3.0 (G3) */
8767 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
8768 /* PowerPC 750 v3.0 (G3) */
8769 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
8770 /* PowerPC 740 v3.1 (G3) */
8771 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
8772 /* PowerPC 750 v3.1 (G3) */
8773 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
8774 /* PowerPC 740E (G3) */
8775 POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
8776 /* PowerPC 750E (G3) */
8777 POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
8778 /* PowerPC 740P (G3) */
8779 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
8780 /* PowerPC 750P (G3) */
8781 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
8782 /* Code name for PowerPC 740P/750P (G3) */
8783 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
8784 /* PowerPC 750CL (G3 embedded) */
8785 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
8786 /* PowerPC 750CL v1.0 */
8787 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
8788 /* PowerPC 750CL v2.0 */
8789 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
8790 /* PowerPC 750CX (G3 embedded) */
8791 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
8792 /* PowerPC 750CX v1.0 (G3 embedded) */
8793 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
8794 /* PowerPC 750CX v2.1 (G3 embedded) */
8795 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
8796 /* PowerPC 750CX v2.1 (G3 embedded) */
8797 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
8798 /* PowerPC 750CX v2.2 (G3 embedded) */
8799 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
8800 /* PowerPC 750CXe (G3 embedded) */
8801 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
8802 /* PowerPC 750CXe v2.1 (G3 embedded) */
8803 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
8804 /* PowerPC 750CXe v2.2 (G3 embedded) */
8805 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
8806 /* PowerPC 750CXe v2.3 (G3 embedded) */
8807 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
8808 /* PowerPC 750CXe v2.4 (G3 embedded) */
8809 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
8810 /* PowerPC 750CXe v2.4b (G3 embedded) */
8811 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
8812 /* PowerPC 750CXe v3.0 (G3 embedded) */
8813 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
8814 /* PowerPC 750CXe v3.1 (G3 embedded) */
8815 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
8816 /* PowerPC 750CXe v3.1b (G3 embedded) */
8817 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
8818 /* PowerPC 750CXr (G3 embedded) */
8819 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
8820 /* PowerPC 750FL (G3 embedded) */
8821 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
8822 /* PowerPC 750FX (G3 embedded) */
8823 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
8824 /* PowerPC 750FX v1.0 (G3 embedded) */
8825 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
8826 /* PowerPC 750FX v2.0 (G3 embedded) */
8827 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
8828 /* PowerPC 750FX v2.1 (G3 embedded) */
8829 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
8830 /* PowerPC 750FX v2.2 (G3 embedded) */
8831 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
8832 /* PowerPC 750FX v2.3 (G3 embedded) */
8833 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
8834 /* PowerPC 750GL (G3 embedded) */
8835 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
8836 /* PowerPC 750GX (G3 embedded) */
8837 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
8838 /* PowerPC 750GX v1.0 (G3 embedded) */
8839 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
8840 /* PowerPC 750GX v1.1 (G3 embedded) */
8841 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
8842 /* PowerPC 750GX v1.2 (G3 embedded) */
8843 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
8844 /* PowerPC 750L (G3 embedded) */
8845 POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
8846 /* Code name for PowerPC 750L (G3 embedded) */
8847 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
8848 /* PowerPC 750L v2.0 (G3 embedded) */
8849 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
8850 /* PowerPC 750L v2.1 (G3 embedded) */
8851 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
8852 /* PowerPC 750L v2.2 (G3 embedded) */
8853 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
8854 /* PowerPC 750L v3.0 (G3 embedded) */
8855 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
8856 /* PowerPC 750L v3.2 (G3 embedded) */
8857 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
8858 /* Generic PowerPC 745 */
8859 POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
8860 /* Generic PowerPC 755 */
8861 POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
8862 /* Code name for PowerPC 745/755 */
8863 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
8864 /* PowerPC 745 v1.0 */
8865 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
8866 /* PowerPC 755 v1.0 */
8867 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
8868 /* PowerPC 745 v1.1 */
8869 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
8870 /* PowerPC 755 v1.1 */
8871 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
8872 /* PowerPC 745 v2.0 */
8873 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
8874 /* PowerPC 755 v2.0 */
8875 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
8876 /* PowerPC 745 v2.1 */
8877 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
8878 /* PowerPC 755 v2.1 */
8879 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
8880 /* PowerPC 745 v2.2 */
8881 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
8882 /* PowerPC 755 v2.2 */
8883 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
8884 /* PowerPC 745 v2.3 */
8885 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
8886 /* PowerPC 755 v2.3 */
8887 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
8888 /* PowerPC 745 v2.4 */
8889 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
8890 /* PowerPC 755 v2.4 */
8891 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
8892 /* PowerPC 745 v2.5 */
8893 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
8894 /* PowerPC 755 v2.5 */
8895 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
8896 /* PowerPC 745 v2.6 */
8897 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
8898 /* PowerPC 755 v2.6 */
8899 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
8900 /* PowerPC 745 v2.7 */
8901 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
8902 /* PowerPC 755 v2.7 */
8903 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
8904 /* PowerPC 745 v2.8 */
8905 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
8906 /* PowerPC 755 v2.8 */
8907 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
8908 #if defined (TODO)
8909 /* PowerPC 745P (G3) */
8910 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
8911 /* PowerPC 755P (G3) */
8912 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
8913 #endif
8914 /* PowerPC 74xx family */
8915 /* PowerPC 7400 (G4) */
8916 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
8917 /* Code name for PowerPC 7400 */
8918 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
8919 /* PowerPC 74xx is also well known as G4 */
8920 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
8921 /* PowerPC 7400 v1.0 (G4) */
8922 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
8923 /* PowerPC 7400 v1.1 (G4) */
8924 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
8925 /* PowerPC 7400 v2.0 (G4) */
8926 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
8927 /* PowerPC 7400 v2.1 (G4) */
8928 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
8929 /* PowerPC 7400 v2.2 (G4) */
8930 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
8931 /* PowerPC 7400 v2.6 (G4) */
8932 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
8933 /* PowerPC 7400 v2.7 (G4) */
8934 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
8935 /* PowerPC 7400 v2.8 (G4) */
8936 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
8937 /* PowerPC 7400 v2.9 (G4) */
8938 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
8939 /* PowerPC 7410 (G4) */
8940 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
8941 /* Code name for PowerPC 7410 */
8942 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
8943 /* PowerPC 7410 v1.0 (G4) */
8944 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
8945 /* PowerPC 7410 v1.1 (G4) */
8946 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
8947 /* PowerPC 7410 v1.2 (G4) */
8948 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
8949 /* PowerPC 7410 v1.3 (G4) */
8950 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
8951 /* PowerPC 7410 v1.4 (G4) */
8952 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
8953 /* PowerPC 7448 (G4) */
8954 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
8955 /* PowerPC 7448 v1.0 (G4) */
8956 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
8957 /* PowerPC 7448 v1.1 (G4) */
8958 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
8959 /* PowerPC 7448 v2.0 (G4) */
8960 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
8961 /* PowerPC 7448 v2.1 (G4) */
8962 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
8963 /* PowerPC 7450 (G4) */
8964 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
8965 /* Code name for PowerPC 7450 */
8966 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
8967 /* PowerPC 7450 v1.0 (G4) */
8968 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
8969 /* PowerPC 7450 v1.1 (G4) */
8970 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
8971 /* PowerPC 7450 v1.2 (G4) */
8972 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
8973 /* PowerPC 7450 v2.0 (G4) */
8974 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
8975 /* PowerPC 7450 v2.1 (G4) */
8976 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
8977 /* PowerPC 7441 (G4) */
8978 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
8979 /* PowerPC 7451 (G4) */
8980 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
8981 /* PowerPC 7441 v2.1 (G4) */
8982 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
8983 /* PowerPC 7441 v2.3 (G4) */
8984 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
8985 /* PowerPC 7451 v2.3 (G4) */
8986 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
8987 /* PowerPC 7441 v2.10 (G4) */
8988 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
8989 /* PowerPC 7451 v2.10 (G4) */
8990 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
8991 /* PowerPC 7445 (G4) */
8992 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
8993 /* PowerPC 7455 (G4) */
8994 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
8995 /* Code name for PowerPC 7445/7455 */
8996 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
8997 /* PowerPC 7445 v1.0 (G4) */
8998 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
8999 /* PowerPC 7455 v1.0 (G4) */
9000 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
9001 /* PowerPC 7445 v2.1 (G4) */
9002 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
9003 /* PowerPC 7455 v2.1 (G4) */
9004 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
9005 /* PowerPC 7445 v3.2 (G4) */
9006 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
9007 /* PowerPC 7455 v3.2 (G4) */
9008 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
9009 /* PowerPC 7445 v3.3 (G4) */
9010 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
9011 /* PowerPC 7455 v3.3 (G4) */
9012 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
9013 /* PowerPC 7445 v3.4 (G4) */
9014 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
9015 /* PowerPC 7455 v3.4 (G4) */
9016 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
9017 /* PowerPC 7447 (G4) */
9018 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
9019 /* PowerPC 7457 (G4) */
9020 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
9021 /* Code name for PowerPC 7447/7457 */
9022 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
9023 /* PowerPC 7447 v1.0 (G4) */
9024 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
9025 /* PowerPC 7457 v1.0 (G4) */
9026 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
9027 /* PowerPC 7447 v1.1 (G4) */
9028 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
9029 /* PowerPC 7457 v1.1 (G4) */
9030 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
9031 /* PowerPC 7457 v1.2 (G4) */
9032 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
9033 /* PowerPC 7447A (G4) */
9034 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
9035 /* PowerPC 7457A (G4) */
9036 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
9037 /* PowerPC 7447A v1.0 (G4) */
9038 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
9039 /* PowerPC 7457A v1.0 (G4) */
9040 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
9041 /* Code name for PowerPC 7447A/7457A */
9042 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
9043 /* PowerPC 7447A v1.1 (G4) */
9044 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
9045 /* PowerPC 7457A v1.1 (G4) */
9046 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
9047 /* PowerPC 7447A v1.2 (G4) */
9048 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
9049 /* PowerPC 7457A v1.2 (G4) */
9050 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
9051 /* 64 bits PowerPC */
9052 #if defined (TARGET_PPC64)
9053 /* PowerPC 620 */
9054 POWERPC_DEF("620", CPU_POWERPC_620, 620),
9055 /* Code name for PowerPC 620 */
9056 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
9057 #if defined (TODO)
9058 /* PowerPC 630 (POWER3) */
9059 POWERPC_DEF("630", CPU_POWERPC_630, 630),
9060 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
9061 /* Code names for POWER3 */
9062 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
9063 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
9064 #endif
9065 #if defined (TODO)
9066 /* PowerPC 631 (Power 3+) */
9067 POWERPC_DEF("631", CPU_POWERPC_631, 631),
9068 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
9069 #endif
9070 #if defined (TODO)
9071 /* POWER4 */
9072 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
9073 #endif
9074 #if defined (TODO)
9075 /* POWER4p */
9076 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
9077 #endif
9078 #if defined (TODO)
9079 /* POWER5 */
9080 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
9081 /* POWER5GR */
9082 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
9083 #endif
9084 #if defined (TODO)
9085 /* POWER5+ */
9086 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
9087 /* POWER5GS */
9088 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
9089 #endif
9090 #if defined (TODO)
9091 /* POWER6 */
9092 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
9093 /* POWER6 running in POWER5 mode */
9094 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
9095 /* POWER6A */
9096 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
9097 #endif
9098 /* POWER7 */
9099 POWERPC_DEF("POWER7", CPU_POWERPC_POWER7, POWER7),
9100 POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7),
9101 /* PowerPC 970 */
9102 POWERPC_DEF("970", CPU_POWERPC_970, 970),
9103 /* PowerPC 970FX (G5) */
9104 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
9105 /* PowerPC 970FX v1.0 (G5) */
9106 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
9107 /* PowerPC 970FX v2.0 (G5) */
9108 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
9109 /* PowerPC 970FX v2.1 (G5) */
9110 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
9111 /* PowerPC 970FX v3.0 (G5) */
9112 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
9113 /* PowerPC 970FX v3.1 (G5) */
9114 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
9115 /* PowerPC 970GX (G5) */
9116 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
9117 /* PowerPC 970MP */
9118 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
9119 /* PowerPC 970MP v1.0 */
9120 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
9121 /* PowerPC 970MP v1.1 */
9122 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
9123 #if defined (TODO)
9124 /* PowerPC Cell */
9125 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
9126 #endif
9127 #if defined (TODO)
9128 /* PowerPC Cell v1.0 */
9129 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
9130 #endif
9131 #if defined (TODO)
9132 /* PowerPC Cell v2.0 */
9133 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
9134 #endif
9135 #if defined (TODO)
9136 /* PowerPC Cell v3.0 */
9137 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
9138 #endif
9139 #if defined (TODO)
9140 /* PowerPC Cell v3.1 */
9141 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
9142 #endif
9143 #if defined (TODO)
9144 /* PowerPC Cell v3.2 */
9145 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
9146 #endif
9147 #if defined (TODO)
9148 /* RS64 (Apache/A35) */
9149 /* This one seems to support the whole POWER2 instruction set
9150 * and the PowerPC 64 one.
9151 */
9152 /* What about A10 & A30 ? */
9153 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
9154 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
9155 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
9156 #endif
9157 #if defined (TODO)
9158 /* RS64-II (NorthStar/A50) */
9159 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
9160 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
9161 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
9162 #endif
9163 #if defined (TODO)
9164 /* RS64-III (Pulsar) */
9165 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
9166 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
9167 #endif
9168 #if defined (TODO)
9169 /* RS64-IV (IceStar/IStar/SStar) */
9170 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
9171 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
9172 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
9173 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
9174 #endif
9175 #endif /* defined (TARGET_PPC64) */
9176 /* POWER */
9177 #if defined (TODO)
9178 /* Original POWER */
9179 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
9180 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
9181 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
9182 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
9183 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
9184 #endif
9185 #if defined (TODO)
9186 /* POWER2 */
9187 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
9188 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
9189 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
9190 #endif
9191 /* PA semi cores */
9192 #if defined (TODO)
9193 /* PA PA6T */
9194 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
9195 #endif
9196 /* Generic PowerPCs */
9197 #if defined (TARGET_PPC64)
9198 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
9199 #endif
9200 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
9201 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
9202 /* Fallback */
9203 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
9204 };
9205
9206 /*****************************************************************************/
9207 /* Generic CPU instantiation routine */
9208 static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
9209 {
9210 #if !defined(CONFIG_USER_ONLY)
9211 int i;
9212
9213 env->irq_inputs = NULL;
9214 /* Set all exception vectors to an invalid address */
9215 for (i = 0; i < POWERPC_EXCP_NB; i++)
9216 env->excp_vectors[i] = (target_ulong)(-1ULL);
9217 env->hreset_excp_prefix = 0x00000000;
9218 env->ivor_mask = 0x00000000;
9219 env->ivpr_mask = 0x00000000;
9220 /* Default MMU definitions */
9221 env->nb_BATs = 0;
9222 env->nb_tlb = 0;
9223 env->nb_ways = 0;
9224 env->tlb_type = TLB_NONE;
9225 #endif
9226 /* Register SPR common to all PowerPC implementations */
9227 gen_spr_generic(env);
9228 spr_register(env, SPR_PVR, "PVR",
9229 /* Linux permits userspace to read PVR */
9230 #if defined(CONFIG_LINUX_USER)
9231 &spr_read_generic,
9232 #else
9233 SPR_NOACCESS,
9234 #endif
9235 SPR_NOACCESS,
9236 &spr_read_generic, SPR_NOACCESS,
9237 def->pvr);
9238 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9239 if (def->svr != POWERPC_SVR_NONE) {
9240 if (def->svr & POWERPC_SVR_E500) {
9241 spr_register(env, SPR_E500_SVR, "SVR",
9242 SPR_NOACCESS, SPR_NOACCESS,
9243 &spr_read_generic, SPR_NOACCESS,
9244 def->svr & ~POWERPC_SVR_E500);
9245 } else {
9246 spr_register(env, SPR_SVR, "SVR",
9247 SPR_NOACCESS, SPR_NOACCESS,
9248 &spr_read_generic, SPR_NOACCESS,
9249 def->svr);
9250 }
9251 }
9252 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9253 (*def->init_proc)(env);
9254 #if !defined(CONFIG_USER_ONLY)
9255 env->excp_prefix = env->hreset_excp_prefix;
9256 #endif
9257 /* MSR bits & flags consistency checks */
9258 if (env->msr_mask & (1 << 25)) {
9259 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9260 case POWERPC_FLAG_SPE:
9261 case POWERPC_FLAG_VRE:
9262 break;
9263 default:
9264 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9265 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9266 exit(1);
9267 }
9268 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9269 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9270 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9271 exit(1);
9272 }
9273 if (env->msr_mask & (1 << 17)) {
9274 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9275 case POWERPC_FLAG_TGPR:
9276 case POWERPC_FLAG_CE:
9277 break;
9278 default:
9279 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9280 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9281 exit(1);
9282 }
9283 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9284 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9285 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9286 exit(1);
9287 }
9288 if (env->msr_mask & (1 << 10)) {
9289 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9290 POWERPC_FLAG_UBLE)) {
9291 case POWERPC_FLAG_SE:
9292 case POWERPC_FLAG_DWE:
9293 case POWERPC_FLAG_UBLE:
9294 break;
9295 default:
9296 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9297 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9298 "POWERPC_FLAG_UBLE\n");
9299 exit(1);
9300 }
9301 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9302 POWERPC_FLAG_UBLE)) {
9303 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9304 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9305 "POWERPC_FLAG_UBLE\n");
9306 exit(1);
9307 }
9308 if (env->msr_mask & (1 << 9)) {
9309 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9310 case POWERPC_FLAG_BE:
9311 case POWERPC_FLAG_DE:
9312 break;
9313 default:
9314 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9315 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9316 exit(1);
9317 }
9318 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9319 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9320 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9321 exit(1);
9322 }
9323 if (env->msr_mask & (1 << 2)) {
9324 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9325 case POWERPC_FLAG_PX:
9326 case POWERPC_FLAG_PMM:
9327 break;
9328 default:
9329 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9330 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9331 exit(1);
9332 }
9333 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9334 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9335 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9336 exit(1);
9337 }
9338 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9339 fprintf(stderr, "PowerPC flags inconsistency\n"
9340 "Should define the time-base and decrementer clock source\n");
9341 exit(1);
9342 }
9343 /* Allocate TLBs buffer when needed */
9344 #if !defined(CONFIG_USER_ONLY)
9345 if (env->nb_tlb != 0) {
9346 int nb_tlb = env->nb_tlb;
9347 if (env->id_tlbs != 0)
9348 nb_tlb *= 2;
9349 switch (env->tlb_type) {
9350 case TLB_6XX:
9351 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
9352 break;
9353 case TLB_EMB:
9354 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
9355 break;
9356 case TLB_MAS:
9357 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
9358 break;
9359 }
9360 /* Pre-compute some useful values */
9361 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9362 }
9363 if (env->irq_inputs == NULL) {
9364 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
9365 " Attempt Qemu to crash very soon !\n");
9366 }
9367 #endif
9368 if (env->check_pow == NULL) {
9369 fprintf(stderr, "WARNING: no power management check handler "
9370 "registered.\n"
9371 " Attempt Qemu to crash very soon !\n");
9372 }
9373 }
9374
9375 #if defined(PPC_DUMP_CPU)
9376 static void dump_ppc_sprs (CPUPPCState *env)
9377 {
9378 ppc_spr_t *spr;
9379 #if !defined(CONFIG_USER_ONLY)
9380 uint32_t sr, sw;
9381 #endif
9382 uint32_t ur, uw;
9383 int i, j, n;
9384
9385 printf("Special purpose registers:\n");
9386 for (i = 0; i < 32; i++) {
9387 for (j = 0; j < 32; j++) {
9388 n = (i << 5) | j;
9389 spr = &env->spr_cb[n];
9390 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9391 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9392 #if !defined(CONFIG_USER_ONLY)
9393 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9394 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9395 if (sw || sr || uw || ur) {
9396 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9397 (i << 5) | j, (i << 5) | j, spr->name,
9398 sw ? 'w' : '-', sr ? 'r' : '-',
9399 uw ? 'w' : '-', ur ? 'r' : '-');
9400 }
9401 #else
9402 if (uw || ur) {
9403 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9404 (i << 5) | j, (i << 5) | j, spr->name,
9405 uw ? 'w' : '-', ur ? 'r' : '-');
9406 }
9407 #endif
9408 }
9409 }
9410 fflush(stdout);
9411 fflush(stderr);
9412 }
9413 #endif
9414
9415 /*****************************************************************************/
9416 #include <stdlib.h>
9417 #include <string.h>
9418
9419 /* Opcode types */
9420 enum {
9421 PPC_DIRECT = 0, /* Opcode routine */
9422 PPC_INDIRECT = 1, /* Indirect opcode table */
9423 };
9424
9425 static inline int is_indirect_opcode (void *handler)
9426 {
9427 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
9428 }
9429
9430 static inline opc_handler_t **ind_table(void *handler)
9431 {
9432 return (opc_handler_t **)((unsigned long)handler & ~3);
9433 }
9434
9435 /* Instruction table creation */
9436 /* Opcodes tables creation */
9437 static void fill_new_table (opc_handler_t **table, int len)
9438 {
9439 int i;
9440
9441 for (i = 0; i < len; i++)
9442 table[i] = &invalid_handler;
9443 }
9444
9445 static int create_new_table (opc_handler_t **table, unsigned char idx)
9446 {
9447 opc_handler_t **tmp;
9448
9449 tmp = malloc(0x20 * sizeof(opc_handler_t));
9450 fill_new_table(tmp, 0x20);
9451 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
9452
9453 return 0;
9454 }
9455
9456 static int insert_in_table (opc_handler_t **table, unsigned char idx,
9457 opc_handler_t *handler)
9458 {
9459 if (table[idx] != &invalid_handler)
9460 return -1;
9461 table[idx] = handler;
9462
9463 return 0;
9464 }
9465
9466 static int register_direct_insn (opc_handler_t **ppc_opcodes,
9467 unsigned char idx, opc_handler_t *handler)
9468 {
9469 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9470 printf("*** ERROR: opcode %02x already assigned in main "
9471 "opcode table\n", idx);
9472 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9473 printf(" Registered handler '%s' - new handler '%s'\n",
9474 ppc_opcodes[idx]->oname, handler->oname);
9475 #endif
9476 return -1;
9477 }
9478
9479 return 0;
9480 }
9481
9482 static int register_ind_in_table (opc_handler_t **table,
9483 unsigned char idx1, unsigned char idx2,
9484 opc_handler_t *handler)
9485 {
9486 if (table[idx1] == &invalid_handler) {
9487 if (create_new_table(table, idx1) < 0) {
9488 printf("*** ERROR: unable to create indirect table "
9489 "idx=%02x\n", idx1);
9490 return -1;
9491 }
9492 } else {
9493 if (!is_indirect_opcode(table[idx1])) {
9494 printf("*** ERROR: idx %02x already assigned to a direct "
9495 "opcode\n", idx1);
9496 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9497 printf(" Registered handler '%s' - new handler '%s'\n",
9498 ind_table(table[idx1])[idx2]->oname, handler->oname);
9499 #endif
9500 return -1;
9501 }
9502 }
9503 if (handler != NULL &&
9504 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9505 printf("*** ERROR: opcode %02x already assigned in "
9506 "opcode table %02x\n", idx2, idx1);
9507 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9508 printf(" Registered handler '%s' - new handler '%s'\n",
9509 ind_table(table[idx1])[idx2]->oname, handler->oname);
9510 #endif
9511 return -1;
9512 }
9513
9514 return 0;
9515 }
9516
9517 static int register_ind_insn (opc_handler_t **ppc_opcodes,
9518 unsigned char idx1, unsigned char idx2,
9519 opc_handler_t *handler)
9520 {
9521 int ret;
9522
9523 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9524
9525 return ret;
9526 }
9527
9528 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9529 unsigned char idx1, unsigned char idx2,
9530 unsigned char idx3, opc_handler_t *handler)
9531 {
9532 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9533 printf("*** ERROR: unable to join indirect table idx "
9534 "[%02x-%02x]\n", idx1, idx2);
9535 return -1;
9536 }
9537 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9538 handler) < 0) {
9539 printf("*** ERROR: unable to insert opcode "
9540 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9541 return -1;
9542 }
9543
9544 return 0;
9545 }
9546
9547 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9548 {
9549 if (insn->opc2 != 0xFF) {
9550 if (insn->opc3 != 0xFF) {
9551 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9552 insn->opc3, &insn->handler) < 0)
9553 return -1;
9554 } else {
9555 if (register_ind_insn(ppc_opcodes, insn->opc1,
9556 insn->opc2, &insn->handler) < 0)
9557 return -1;
9558 }
9559 } else {
9560 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9561 return -1;
9562 }
9563
9564 return 0;
9565 }
9566
9567 static int test_opcode_table (opc_handler_t **table, int len)
9568 {
9569 int i, count, tmp;
9570
9571 for (i = 0, count = 0; i < len; i++) {
9572 /* Consistency fixup */
9573 if (table[i] == NULL)
9574 table[i] = &invalid_handler;
9575 if (table[i] != &invalid_handler) {
9576 if (is_indirect_opcode(table[i])) {
9577 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9578 if (tmp == 0) {
9579 free(table[i]);
9580 table[i] = &invalid_handler;
9581 } else {
9582 count++;
9583 }
9584 } else {
9585 count++;
9586 }
9587 }
9588 }
9589
9590 return count;
9591 }
9592
9593 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9594 {
9595 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9596 printf("*** WARNING: no opcode defined !\n");
9597 }
9598
9599 /*****************************************************************************/
9600 static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
9601 {
9602 opcode_t *opc;
9603
9604 fill_new_table(env->opcodes, 0x40);
9605 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9606 if (((opc->handler.type & def->insns_flags) != 0) ||
9607 ((opc->handler.type2 & def->insns_flags2) != 0)) {
9608 if (register_insn(env->opcodes, opc) < 0) {
9609 printf("*** ERROR initializing PowerPC instruction "
9610 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9611 opc->opc3);
9612 return -1;
9613 }
9614 }
9615 }
9616 fix_opcode_tables(env->opcodes);
9617 fflush(stdout);
9618 fflush(stderr);
9619
9620 return 0;
9621 }
9622
9623 #if defined(PPC_DUMP_CPU)
9624 static void dump_ppc_insns (CPUPPCState *env)
9625 {
9626 opc_handler_t **table, *handler;
9627 const char *p, *q;
9628 uint8_t opc1, opc2, opc3;
9629
9630 printf("Instructions set:\n");
9631 /* opc1 is 6 bits long */
9632 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9633 table = env->opcodes;
9634 handler = table[opc1];
9635 if (is_indirect_opcode(handler)) {
9636 /* opc2 is 5 bits long */
9637 for (opc2 = 0; opc2 < 0x20; opc2++) {
9638 table = env->opcodes;
9639 handler = env->opcodes[opc1];
9640 table = ind_table(handler);
9641 handler = table[opc2];
9642 if (is_indirect_opcode(handler)) {
9643 table = ind_table(handler);
9644 /* opc3 is 5 bits long */
9645 for (opc3 = 0; opc3 < 0x20; opc3++) {
9646 handler = table[opc3];
9647 if (handler->handler != &gen_invalid) {
9648 /* Special hack to properly dump SPE insns */
9649 p = strchr(handler->oname, '_');
9650 if (p == NULL) {
9651 printf("INSN: %02x %02x %02x (%02d %04d) : "
9652 "%s\n",
9653 opc1, opc2, opc3, opc1,
9654 (opc3 << 5) | opc2,
9655 handler->oname);
9656 } else {
9657 q = "speundef";
9658 if ((p - handler->oname) != strlen(q) ||
9659 memcmp(handler->oname, q, strlen(q)) != 0) {
9660 /* First instruction */
9661 printf("INSN: %02x %02x %02x (%02d %04d) : "
9662 "%.*s\n",
9663 opc1, opc2 << 1, opc3, opc1,
9664 (opc3 << 6) | (opc2 << 1),
9665 (int)(p - handler->oname),
9666 handler->oname);
9667 }
9668 if (strcmp(p + 1, q) != 0) {
9669 /* Second instruction */
9670 printf("INSN: %02x %02x %02x (%02d %04d) : "
9671 "%s\n",
9672 opc1, (opc2 << 1) | 1, opc3, opc1,
9673 (opc3 << 6) | (opc2 << 1) | 1,
9674 p + 1);
9675 }
9676 }
9677 }
9678 }
9679 } else {
9680 if (handler->handler != &gen_invalid) {
9681 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9682 opc1, opc2, opc1, opc2, handler->oname);
9683 }
9684 }
9685 }
9686 } else {
9687 if (handler->handler != &gen_invalid) {
9688 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9689 opc1, opc1, handler->oname);
9690 }
9691 }
9692 }
9693 }
9694 #endif
9695
9696 static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9697 {
9698 if (n < 32) {
9699 stfq_p(mem_buf, env->fpr[n]);
9700 return 8;
9701 }
9702 if (n == 32) {
9703 stl_p(mem_buf, env->fpscr);
9704 return 4;
9705 }
9706 return 0;
9707 }
9708
9709 static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9710 {
9711 if (n < 32) {
9712 env->fpr[n] = ldfq_p(mem_buf);
9713 return 8;
9714 }
9715 if (n == 32) {
9716 /* FPSCR not implemented */
9717 return 4;
9718 }
9719 return 0;
9720 }
9721
9722 static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9723 {
9724 if (n < 32) {
9725 #ifdef HOST_WORDS_BIGENDIAN
9726 stq_p(mem_buf, env->avr[n].u64[0]);
9727 stq_p(mem_buf+8, env->avr[n].u64[1]);
9728 #else
9729 stq_p(mem_buf, env->avr[n].u64[1]);
9730 stq_p(mem_buf+8, env->avr[n].u64[0]);
9731 #endif
9732 return 16;
9733 }
9734 if (n == 32) {
9735 stl_p(mem_buf, env->vscr);
9736 return 4;
9737 }
9738 if (n == 33) {
9739 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9740 return 4;
9741 }
9742 return 0;
9743 }
9744
9745 static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9746 {
9747 if (n < 32) {
9748 #ifdef HOST_WORDS_BIGENDIAN
9749 env->avr[n].u64[0] = ldq_p(mem_buf);
9750 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9751 #else
9752 env->avr[n].u64[1] = ldq_p(mem_buf);
9753 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9754 #endif
9755 return 16;
9756 }
9757 if (n == 32) {
9758 env->vscr = ldl_p(mem_buf);
9759 return 4;
9760 }
9761 if (n == 33) {
9762 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9763 return 4;
9764 }
9765 return 0;
9766 }
9767
9768 static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9769 {
9770 if (n < 32) {
9771 #if defined(TARGET_PPC64)
9772 stl_p(mem_buf, env->gpr[n] >> 32);
9773 #else
9774 stl_p(mem_buf, env->gprh[n]);
9775 #endif
9776 return 4;
9777 }
9778 if (n == 32) {
9779 stq_p(mem_buf, env->spe_acc);
9780 return 8;
9781 }
9782 if (n == 33) {
9783 stl_p(mem_buf, env->spe_fscr);
9784 return 4;
9785 }
9786 return 0;
9787 }
9788
9789 static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9790 {
9791 if (n < 32) {
9792 #if defined(TARGET_PPC64)
9793 target_ulong lo = (uint32_t)env->gpr[n];
9794 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9795 env->gpr[n] = lo | hi;
9796 #else
9797 env->gprh[n] = ldl_p(mem_buf);
9798 #endif
9799 return 4;
9800 }
9801 if (n == 32) {
9802 env->spe_acc = ldq_p(mem_buf);
9803 return 8;
9804 }
9805 if (n == 33) {
9806 env->spe_fscr = ldl_p(mem_buf);
9807 return 4;
9808 }
9809 return 0;
9810 }
9811
9812 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
9813 {
9814 env->msr_mask = def->msr_mask;
9815 env->mmu_model = def->mmu_model;
9816 env->excp_model = def->excp_model;
9817 env->bus_model = def->bus_model;
9818 env->insns_flags = def->insns_flags;
9819 env->insns_flags2 = def->insns_flags2;
9820 env->flags = def->flags;
9821 env->bfd_mach = def->bfd_mach;
9822 env->check_pow = def->check_pow;
9823 if (create_ppc_opcodes(env, def) < 0)
9824 return -1;
9825 init_ppc_proc(env, def);
9826
9827 if (def->insns_flags & PPC_FLOAT) {
9828 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9829 33, "power-fpu.xml", 0);
9830 }
9831 if (def->insns_flags & PPC_ALTIVEC) {
9832 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9833 34, "power-altivec.xml", 0);
9834 }
9835 if (def->insns_flags & PPC_SPE) {
9836 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9837 34, "power-spe.xml", 0);
9838 }
9839
9840 #if defined(PPC_DUMP_CPU)
9841 {
9842 const char *mmu_model, *excp_model, *bus_model;
9843 switch (env->mmu_model) {
9844 case POWERPC_MMU_32B:
9845 mmu_model = "PowerPC 32";
9846 break;
9847 case POWERPC_MMU_SOFT_6xx:
9848 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9849 break;
9850 case POWERPC_MMU_SOFT_74xx:
9851 mmu_model = "PowerPC 74xx with software driven TLBs";
9852 break;
9853 case POWERPC_MMU_SOFT_4xx:
9854 mmu_model = "PowerPC 4xx with software driven TLBs";
9855 break;
9856 case POWERPC_MMU_SOFT_4xx_Z:
9857 mmu_model = "PowerPC 4xx with software driven TLBs "
9858 "and zones protections";
9859 break;
9860 case POWERPC_MMU_REAL:
9861 mmu_model = "PowerPC real mode only";
9862 break;
9863 case POWERPC_MMU_MPC8xx:
9864 mmu_model = "PowerPC MPC8xx";
9865 break;
9866 case POWERPC_MMU_BOOKE:
9867 mmu_model = "PowerPC BookE";
9868 break;
9869 case POWERPC_MMU_BOOKE206:
9870 mmu_model = "PowerPC BookE 2.06";
9871 break;
9872 case POWERPC_MMU_601:
9873 mmu_model = "PowerPC 601";
9874 break;
9875 #if defined (TARGET_PPC64)
9876 case POWERPC_MMU_64B:
9877 mmu_model = "PowerPC 64";
9878 break;
9879 case POWERPC_MMU_620:
9880 mmu_model = "PowerPC 620";
9881 break;
9882 #endif
9883 default:
9884 mmu_model = "Unknown or invalid";
9885 break;
9886 }
9887 switch (env->excp_model) {
9888 case POWERPC_EXCP_STD:
9889 excp_model = "PowerPC";
9890 break;
9891 case POWERPC_EXCP_40x:
9892 excp_model = "PowerPC 40x";
9893 break;
9894 case POWERPC_EXCP_601:
9895 excp_model = "PowerPC 601";
9896 break;
9897 case POWERPC_EXCP_602:
9898 excp_model = "PowerPC 602";
9899 break;
9900 case POWERPC_EXCP_603:
9901 excp_model = "PowerPC 603";
9902 break;
9903 case POWERPC_EXCP_603E:
9904 excp_model = "PowerPC 603e";
9905 break;
9906 case POWERPC_EXCP_604:
9907 excp_model = "PowerPC 604";
9908 break;
9909 case POWERPC_EXCP_7x0:
9910 excp_model = "PowerPC 740/750";
9911 break;
9912 case POWERPC_EXCP_7x5:
9913 excp_model = "PowerPC 745/755";
9914 break;
9915 case POWERPC_EXCP_74xx:
9916 excp_model = "PowerPC 74xx";
9917 break;
9918 case POWERPC_EXCP_BOOKE:
9919 excp_model = "PowerPC BookE";
9920 break;
9921 #if defined (TARGET_PPC64)
9922 case POWERPC_EXCP_970:
9923 excp_model = "PowerPC 970";
9924 break;
9925 #endif
9926 default:
9927 excp_model = "Unknown or invalid";
9928 break;
9929 }
9930 switch (env->bus_model) {
9931 case PPC_FLAGS_INPUT_6xx:
9932 bus_model = "PowerPC 6xx";
9933 break;
9934 case PPC_FLAGS_INPUT_BookE:
9935 bus_model = "PowerPC BookE";
9936 break;
9937 case PPC_FLAGS_INPUT_405:
9938 bus_model = "PowerPC 405";
9939 break;
9940 case PPC_FLAGS_INPUT_401:
9941 bus_model = "PowerPC 401/403";
9942 break;
9943 case PPC_FLAGS_INPUT_RCPU:
9944 bus_model = "RCPU / MPC8xx";
9945 break;
9946 #if defined (TARGET_PPC64)
9947 case PPC_FLAGS_INPUT_970:
9948 bus_model = "PowerPC 970";
9949 break;
9950 #endif
9951 default:
9952 bus_model = "Unknown or invalid";
9953 break;
9954 }
9955 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9956 " MMU model : %s\n",
9957 def->name, def->pvr, def->msr_mask, mmu_model);
9958 #if !defined(CONFIG_USER_ONLY)
9959 if (env->tlb != NULL) {
9960 printf(" %d %s TLB in %d ways\n",
9961 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9962 env->nb_ways);
9963 }
9964 #endif
9965 printf(" Exceptions model : %s\n"
9966 " Bus model : %s\n",
9967 excp_model, bus_model);
9968 printf(" MSR features :\n");
9969 if (env->flags & POWERPC_FLAG_SPE)
9970 printf(" signal processing engine enable"
9971 "\n");
9972 else if (env->flags & POWERPC_FLAG_VRE)
9973 printf(" vector processor enable\n");
9974 if (env->flags & POWERPC_FLAG_TGPR)
9975 printf(" temporary GPRs\n");
9976 else if (env->flags & POWERPC_FLAG_CE)
9977 printf(" critical input enable\n");
9978 if (env->flags & POWERPC_FLAG_SE)
9979 printf(" single-step trace mode\n");
9980 else if (env->flags & POWERPC_FLAG_DWE)
9981 printf(" debug wait enable\n");
9982 else if (env->flags & POWERPC_FLAG_UBLE)
9983 printf(" user BTB lock enable\n");
9984 if (env->flags & POWERPC_FLAG_BE)
9985 printf(" branch-step trace mode\n");
9986 else if (env->flags & POWERPC_FLAG_DE)
9987 printf(" debug interrupt enable\n");
9988 if (env->flags & POWERPC_FLAG_PX)
9989 printf(" inclusive protection\n");
9990 else if (env->flags & POWERPC_FLAG_PMM)
9991 printf(" performance monitor mark\n");
9992 if (env->flags == POWERPC_FLAG_NONE)
9993 printf(" none\n");
9994 printf(" Time-base/decrementer clock source: %s\n",
9995 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
9996 }
9997 dump_ppc_insns(env);
9998 dump_ppc_sprs(env);
9999 fflush(stdout);
10000 #endif
10001
10002 return 0;
10003 }
10004
10005 static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
10006 {
10007 const ppc_def_t *ret;
10008 uint32_t pvr_rev;
10009 int i, best, match, best_match, max;
10010
10011 ret = NULL;
10012 max = ARRAY_SIZE(ppc_defs);
10013 best = -1;
10014 pvr_rev = pvr & 0xFFFF;
10015 /* We want all specified bits to match */
10016 best_match = 32 - ctz32(pvr_rev);
10017 for (i = 0; i < max; i++) {
10018 /* We check that the 16 higher bits are the same to ensure the CPU
10019 * model will be the choosen one.
10020 */
10021 if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
10022 /* We want as much as possible of the low-level 16 bits
10023 * to be the same but we allow inexact matches.
10024 */
10025 match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
10026 /* We check '>=' instead of '>' because the PPC_defs table
10027 * is ordered by increasing revision.
10028 * Then, we will match the higher revision compatible
10029 * with the requested PVR
10030 */
10031 if (match >= best_match) {
10032 best = i;
10033 best_match = match;
10034 }
10035 }
10036 }
10037 if (best != -1)
10038 ret = &ppc_defs[best];
10039
10040 return ret;
10041 }
10042
10043 #include <ctype.h>
10044
10045 const ppc_def_t *cpu_ppc_find_by_name (const char *name)
10046 {
10047 const ppc_def_t *ret;
10048 const char *p;
10049 int i, max, len;
10050
10051 /* Check if the given name is a PVR */
10052 len = strlen(name);
10053 if (len == 10 && name[0] == '0' && name[1] == 'x') {
10054 p = name + 2;
10055 goto check_pvr;
10056 } else if (len == 8) {
10057 p = name;
10058 check_pvr:
10059 for (i = 0; i < 8; i++) {
10060 if (!qemu_isxdigit(*p++))
10061 break;
10062 }
10063 if (i == 8)
10064 return ppc_find_by_pvr(strtoul(name, NULL, 16));
10065 }
10066 ret = NULL;
10067 max = ARRAY_SIZE(ppc_defs);
10068 for (i = 0; i < max; i++) {
10069 if (strcasecmp(name, ppc_defs[i].name) == 0) {
10070 ret = &ppc_defs[i];
10071 break;
10072 }
10073 }
10074
10075 return ret;
10076 }
10077
10078 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
10079 {
10080 int i, max;
10081
10082 max = ARRAY_SIZE(ppc_defs);
10083 for (i = 0; i < max; i++) {
10084 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
10085 ppc_defs[i].name, ppc_defs[i].pvr);
10086 }
10087 }
Qemu copy for testing