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target-ppc: Extract MPC83xx aliases
[qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26 #include "disas/bfd.h"
27 #include "exec/gdbstub.h"
28 #include <sysemu/kvm.h>
29 #include "kvm_ppc.h"
30 #include "sysemu/arch_init.h"
31 #include "sysemu/cpus.h"
32
33 //#define PPC_DUMP_CPU
34 //#define PPC_DEBUG_SPR
35 //#define PPC_DUMP_SPR_ACCESSES
36 #if defined(CONFIG_USER_ONLY)
37 #define TODO_USER_ONLY 1
38 #endif
39
40 /* For user-mode emulation, we don't emulate any IRQ controller */
41 #if defined(CONFIG_USER_ONLY)
42 #define PPC_IRQ_INIT_FN(name) \
43 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
44 { \
45 }
46 #else
47 #define PPC_IRQ_INIT_FN(name) \
48 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
49 #endif
50
51 PPC_IRQ_INIT_FN(40x);
52 PPC_IRQ_INIT_FN(6xx);
53 PPC_IRQ_INIT_FN(970);
54 PPC_IRQ_INIT_FN(POWER7);
55 PPC_IRQ_INIT_FN(e500);
56
57 /* Generic callbacks:
58 * do nothing but store/retrieve spr value
59 */
60 static void spr_load_dump_spr(int sprn)
61 {
62 #ifdef PPC_DUMP_SPR_ACCESSES
63 TCGv_i32 t0 = tcg_const_i32(sprn);
64 gen_helper_load_dump_spr(t0);
65 tcg_temp_free_i32(t0);
66 #endif
67 }
68
69 static void spr_read_generic (void *opaque, int gprn, int sprn)
70 {
71 gen_load_spr(cpu_gpr[gprn], sprn);
72 spr_load_dump_spr(sprn);
73 }
74
75 static void spr_store_dump_spr(int sprn)
76 {
77 #ifdef PPC_DUMP_SPR_ACCESSES
78 TCGv_i32 t0 = tcg_const_i32(sprn);
79 gen_helper_store_dump_spr(t0);
80 tcg_temp_free_i32(t0);
81 #endif
82 }
83
84 static void spr_write_generic (void *opaque, int sprn, int gprn)
85 {
86 gen_store_spr(sprn, cpu_gpr[gprn]);
87 spr_store_dump_spr(sprn);
88 }
89
90 #if !defined(CONFIG_USER_ONLY)
91 static void spr_write_generic32(void *opaque, int sprn, int gprn)
92 {
93 #ifdef TARGET_PPC64
94 TCGv t0 = tcg_temp_new();
95 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
96 gen_store_spr(sprn, t0);
97 tcg_temp_free(t0);
98 spr_store_dump_spr(sprn);
99 #else
100 spr_write_generic(opaque, sprn, gprn);
101 #endif
102 }
103
104 static void spr_write_clear (void *opaque, int sprn, int gprn)
105 {
106 TCGv t0 = tcg_temp_new();
107 TCGv t1 = tcg_temp_new();
108 gen_load_spr(t0, sprn);
109 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
110 tcg_gen_and_tl(t0, t0, t1);
111 gen_store_spr(sprn, t0);
112 tcg_temp_free(t0);
113 tcg_temp_free(t1);
114 }
115 #endif
116
117 /* SPR common to all PowerPC */
118 /* XER */
119 static void spr_read_xer (void *opaque, int gprn, int sprn)
120 {
121 gen_read_xer(cpu_gpr[gprn]);
122 }
123
124 static void spr_write_xer (void *opaque, int sprn, int gprn)
125 {
126 gen_write_xer(cpu_gpr[gprn]);
127 }
128
129 /* LR */
130 static void spr_read_lr (void *opaque, int gprn, int sprn)
131 {
132 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
133 }
134
135 static void spr_write_lr (void *opaque, int sprn, int gprn)
136 {
137 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
138 }
139
140 /* CFAR */
141 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
142 static void spr_read_cfar (void *opaque, int gprn, int sprn)
143 {
144 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
145 }
146
147 static void spr_write_cfar (void *opaque, int sprn, int gprn)
148 {
149 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
150 }
151 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
152
153 /* CTR */
154 static void spr_read_ctr (void *opaque, int gprn, int sprn)
155 {
156 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
157 }
158
159 static void spr_write_ctr (void *opaque, int sprn, int gprn)
160 {
161 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
162 }
163
164 /* User read access to SPR */
165 /* USPRx */
166 /* UMMCRx */
167 /* UPMCx */
168 /* USIA */
169 /* UDECR */
170 static void spr_read_ureg (void *opaque, int gprn, int sprn)
171 {
172 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
173 }
174
175 /* SPR common to all non-embedded PowerPC */
176 /* DECR */
177 #if !defined(CONFIG_USER_ONLY)
178 static void spr_read_decr (void *opaque, int gprn, int sprn)
179 {
180 if (use_icount) {
181 gen_io_start();
182 }
183 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
184 if (use_icount) {
185 gen_io_end();
186 gen_stop_exception(opaque);
187 }
188 }
189
190 static void spr_write_decr (void *opaque, int sprn, int gprn)
191 {
192 if (use_icount) {
193 gen_io_start();
194 }
195 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
196 if (use_icount) {
197 gen_io_end();
198 gen_stop_exception(opaque);
199 }
200 }
201 #endif
202
203 /* SPR common to all non-embedded PowerPC, except 601 */
204 /* Time base */
205 static void spr_read_tbl (void *opaque, int gprn, int sprn)
206 {
207 if (use_icount) {
208 gen_io_start();
209 }
210 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
211 if (use_icount) {
212 gen_io_end();
213 gen_stop_exception(opaque);
214 }
215 }
216
217 static void spr_read_tbu (void *opaque, int gprn, int sprn)
218 {
219 if (use_icount) {
220 gen_io_start();
221 }
222 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
223 if (use_icount) {
224 gen_io_end();
225 gen_stop_exception(opaque);
226 }
227 }
228
229 __attribute__ (( unused ))
230 static void spr_read_atbl (void *opaque, int gprn, int sprn)
231 {
232 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
233 }
234
235 __attribute__ (( unused ))
236 static void spr_read_atbu (void *opaque, int gprn, int sprn)
237 {
238 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
239 }
240
241 #if !defined(CONFIG_USER_ONLY)
242 static void spr_write_tbl (void *opaque, int sprn, int gprn)
243 {
244 if (use_icount) {
245 gen_io_start();
246 }
247 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
248 if (use_icount) {
249 gen_io_end();
250 gen_stop_exception(opaque);
251 }
252 }
253
254 static void spr_write_tbu (void *opaque, int sprn, int gprn)
255 {
256 if (use_icount) {
257 gen_io_start();
258 }
259 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
260 if (use_icount) {
261 gen_io_end();
262 gen_stop_exception(opaque);
263 }
264 }
265
266 __attribute__ (( unused ))
267 static void spr_write_atbl (void *opaque, int sprn, int gprn)
268 {
269 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
270 }
271
272 __attribute__ (( unused ))
273 static void spr_write_atbu (void *opaque, int sprn, int gprn)
274 {
275 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
276 }
277
278 #if defined(TARGET_PPC64)
279 __attribute__ (( unused ))
280 static void spr_read_purr (void *opaque, int gprn, int sprn)
281 {
282 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
283 }
284 #endif
285 #endif
286
287 #if !defined(CONFIG_USER_ONLY)
288 /* IBAT0U...IBAT0U */
289 /* IBAT0L...IBAT7L */
290 static void spr_read_ibat (void *opaque, int gprn, int sprn)
291 {
292 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
293 }
294
295 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
296 {
297 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
298 }
299
300 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
301 {
302 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
303 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
304 tcg_temp_free_i32(t0);
305 }
306
307 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
308 {
309 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
310 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
311 tcg_temp_free_i32(t0);
312 }
313
314 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
315 {
316 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
317 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
318 tcg_temp_free_i32(t0);
319 }
320
321 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
322 {
323 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
324 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
325 tcg_temp_free_i32(t0);
326 }
327
328 /* DBAT0U...DBAT7U */
329 /* DBAT0L...DBAT7L */
330 static void spr_read_dbat (void *opaque, int gprn, int sprn)
331 {
332 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
333 }
334
335 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
336 {
337 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
338 }
339
340 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
341 {
342 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
343 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
344 tcg_temp_free_i32(t0);
345 }
346
347 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
348 {
349 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
350 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
351 tcg_temp_free_i32(t0);
352 }
353
354 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
355 {
356 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
357 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
358 tcg_temp_free_i32(t0);
359 }
360
361 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
362 {
363 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
364 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
365 tcg_temp_free_i32(t0);
366 }
367
368 /* SDR1 */
369 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
370 {
371 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
372 }
373
374 /* 64 bits PowerPC specific SPRs */
375 /* ASR */
376 #if defined(TARGET_PPC64)
377 static void spr_read_hior (void *opaque, int gprn, int sprn)
378 {
379 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
380 }
381
382 static void spr_write_hior (void *opaque, int sprn, int gprn)
383 {
384 TCGv t0 = tcg_temp_new();
385 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
386 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
387 tcg_temp_free(t0);
388 }
389
390 static void spr_read_asr (void *opaque, int gprn, int sprn)
391 {
392 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, asr));
393 }
394
395 static void spr_write_asr (void *opaque, int sprn, int gprn)
396 {
397 gen_helper_store_asr(cpu_env, cpu_gpr[gprn]);
398 }
399 #endif
400 #endif
401
402 /* PowerPC 601 specific registers */
403 /* RTC */
404 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
405 {
406 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
407 }
408
409 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
410 {
411 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
412 }
413
414 #if !defined(CONFIG_USER_ONLY)
415 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
416 {
417 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
418 }
419
420 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
421 {
422 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
423 }
424
425 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
426 {
427 DisasContext *ctx = opaque;
428
429 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
430 /* Must stop the translation as endianness may have changed */
431 gen_stop_exception(ctx);
432 }
433 #endif
434
435 /* Unified bats */
436 #if !defined(CONFIG_USER_ONLY)
437 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
438 {
439 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
440 }
441
442 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
443 {
444 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
445 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
446 tcg_temp_free_i32(t0);
447 }
448
449 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
450 {
451 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
452 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
453 tcg_temp_free_i32(t0);
454 }
455 #endif
456
457 /* PowerPC 40x specific registers */
458 #if !defined(CONFIG_USER_ONLY)
459 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
460 {
461 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
462 }
463
464 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
465 {
466 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
467 }
468
469 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
470 {
471 DisasContext *ctx = opaque;
472
473 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
474 /* We must stop translation as we may have rebooted */
475 gen_stop_exception(ctx);
476 }
477
478 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
479 {
480 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
481 }
482
483 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
484 {
485 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
486 }
487
488 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
489 {
490 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
491 }
492 #endif
493
494 /* PowerPC 403 specific registers */
495 /* PBL1 / PBU1 / PBL2 / PBU2 */
496 #if !defined(CONFIG_USER_ONLY)
497 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
498 {
499 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
500 }
501
502 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
503 {
504 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
505 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
506 tcg_temp_free_i32(t0);
507 }
508
509 static void spr_write_pir (void *opaque, int sprn, int gprn)
510 {
511 TCGv t0 = tcg_temp_new();
512 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
513 gen_store_spr(SPR_PIR, t0);
514 tcg_temp_free(t0);
515 }
516 #endif
517
518 /* SPE specific registers */
519 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
520 {
521 TCGv_i32 t0 = tcg_temp_new_i32();
522 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
523 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
524 tcg_temp_free_i32(t0);
525 }
526
527 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
528 {
529 TCGv_i32 t0 = tcg_temp_new_i32();
530 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
531 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
532 tcg_temp_free_i32(t0);
533 }
534
535 #if !defined(CONFIG_USER_ONLY)
536 /* Callback used to write the exception vector base */
537 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
538 {
539 TCGv t0 = tcg_temp_new();
540 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
541 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
542 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
543 gen_store_spr(sprn, t0);
544 tcg_temp_free(t0);
545 }
546
547 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
548 {
549 DisasContext *ctx = opaque;
550 int sprn_offs;
551
552 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
553 sprn_offs = sprn - SPR_BOOKE_IVOR0;
554 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
555 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
556 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
557 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
558 } else {
559 printf("Trying to write an unknown exception vector %d %03x\n",
560 sprn, sprn);
561 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
562 return;
563 }
564
565 TCGv t0 = tcg_temp_new();
566 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
567 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
568 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
569 gen_store_spr(sprn, t0);
570 tcg_temp_free(t0);
571 }
572 #endif
573
574 static inline void vscr_init (CPUPPCState *env, uint32_t val)
575 {
576 env->vscr = val;
577 /* Altivec always uses round-to-nearest */
578 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
579 set_flush_to_zero(vscr_nj, &env->vec_status);
580 }
581
582 #if defined(CONFIG_USER_ONLY)
583 #define spr_register(env, num, name, uea_read, uea_write, \
584 oea_read, oea_write, initial_value) \
585 do { \
586 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
587 } while (0)
588 static inline void _spr_register (CPUPPCState *env, int num,
589 const char *name,
590 void (*uea_read)(void *opaque, int gprn, int sprn),
591 void (*uea_write)(void *opaque, int sprn, int gprn),
592 target_ulong initial_value)
593 #else
594 static inline void spr_register (CPUPPCState *env, int num,
595 const char *name,
596 void (*uea_read)(void *opaque, int gprn, int sprn),
597 void (*uea_write)(void *opaque, int sprn, int gprn),
598 void (*oea_read)(void *opaque, int gprn, int sprn),
599 void (*oea_write)(void *opaque, int sprn, int gprn),
600 target_ulong initial_value)
601 #endif
602 {
603 ppc_spr_t *spr;
604
605 spr = &env->spr_cb[num];
606 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
607 #if !defined(CONFIG_USER_ONLY)
608 spr->oea_read != NULL || spr->oea_write != NULL ||
609 #endif
610 spr->uea_read != NULL || spr->uea_write != NULL) {
611 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
612 exit(1);
613 }
614 #if defined(PPC_DEBUG_SPR)
615 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
616 name, initial_value);
617 #endif
618 spr->name = name;
619 spr->uea_read = uea_read;
620 spr->uea_write = uea_write;
621 #if !defined(CONFIG_USER_ONLY)
622 spr->oea_read = oea_read;
623 spr->oea_write = oea_write;
624 #endif
625 env->spr[num] = initial_value;
626 }
627
628 /* Generic PowerPC SPRs */
629 static void gen_spr_generic (CPUPPCState *env)
630 {
631 /* Integer processing */
632 spr_register(env, SPR_XER, "XER",
633 &spr_read_xer, &spr_write_xer,
634 &spr_read_xer, &spr_write_xer,
635 0x00000000);
636 /* Branch contol */
637 spr_register(env, SPR_LR, "LR",
638 &spr_read_lr, &spr_write_lr,
639 &spr_read_lr, &spr_write_lr,
640 0x00000000);
641 spr_register(env, SPR_CTR, "CTR",
642 &spr_read_ctr, &spr_write_ctr,
643 &spr_read_ctr, &spr_write_ctr,
644 0x00000000);
645 /* Interrupt processing */
646 spr_register(env, SPR_SRR0, "SRR0",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_generic, &spr_write_generic,
649 0x00000000);
650 spr_register(env, SPR_SRR1, "SRR1",
651 SPR_NOACCESS, SPR_NOACCESS,
652 &spr_read_generic, &spr_write_generic,
653 0x00000000);
654 /* Processor control */
655 spr_register(env, SPR_SPRG0, "SPRG0",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 spr_register(env, SPR_SPRG1, "SPRG1",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 spr_register(env, SPR_SPRG2, "SPRG2",
664 SPR_NOACCESS, SPR_NOACCESS,
665 &spr_read_generic, &spr_write_generic,
666 0x00000000);
667 spr_register(env, SPR_SPRG3, "SPRG3",
668 SPR_NOACCESS, SPR_NOACCESS,
669 &spr_read_generic, &spr_write_generic,
670 0x00000000);
671 }
672
673 /* SPR common to all non-embedded PowerPC, including 601 */
674 static void gen_spr_ne_601 (CPUPPCState *env)
675 {
676 /* Exception processing */
677 spr_register(env, SPR_DSISR, "DSISR",
678 SPR_NOACCESS, SPR_NOACCESS,
679 &spr_read_generic, &spr_write_generic,
680 0x00000000);
681 spr_register(env, SPR_DAR, "DAR",
682 SPR_NOACCESS, SPR_NOACCESS,
683 &spr_read_generic, &spr_write_generic,
684 0x00000000);
685 /* Timer */
686 spr_register(env, SPR_DECR, "DECR",
687 SPR_NOACCESS, SPR_NOACCESS,
688 &spr_read_decr, &spr_write_decr,
689 0x00000000);
690 /* Memory management */
691 spr_register(env, SPR_SDR1, "SDR1",
692 SPR_NOACCESS, SPR_NOACCESS,
693 &spr_read_generic, &spr_write_sdr1,
694 0x00000000);
695 }
696
697 /* BATs 0-3 */
698 static void gen_low_BATs (CPUPPCState *env)
699 {
700 #if !defined(CONFIG_USER_ONLY)
701 spr_register(env, SPR_IBAT0U, "IBAT0U",
702 SPR_NOACCESS, SPR_NOACCESS,
703 &spr_read_ibat, &spr_write_ibatu,
704 0x00000000);
705 spr_register(env, SPR_IBAT0L, "IBAT0L",
706 SPR_NOACCESS, SPR_NOACCESS,
707 &spr_read_ibat, &spr_write_ibatl,
708 0x00000000);
709 spr_register(env, SPR_IBAT1U, "IBAT1U",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_ibat, &spr_write_ibatu,
712 0x00000000);
713 spr_register(env, SPR_IBAT1L, "IBAT1L",
714 SPR_NOACCESS, SPR_NOACCESS,
715 &spr_read_ibat, &spr_write_ibatl,
716 0x00000000);
717 spr_register(env, SPR_IBAT2U, "IBAT2U",
718 SPR_NOACCESS, SPR_NOACCESS,
719 &spr_read_ibat, &spr_write_ibatu,
720 0x00000000);
721 spr_register(env, SPR_IBAT2L, "IBAT2L",
722 SPR_NOACCESS, SPR_NOACCESS,
723 &spr_read_ibat, &spr_write_ibatl,
724 0x00000000);
725 spr_register(env, SPR_IBAT3U, "IBAT3U",
726 SPR_NOACCESS, SPR_NOACCESS,
727 &spr_read_ibat, &spr_write_ibatu,
728 0x00000000);
729 spr_register(env, SPR_IBAT3L, "IBAT3L",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_ibat, &spr_write_ibatl,
732 0x00000000);
733 spr_register(env, SPR_DBAT0U, "DBAT0U",
734 SPR_NOACCESS, SPR_NOACCESS,
735 &spr_read_dbat, &spr_write_dbatu,
736 0x00000000);
737 spr_register(env, SPR_DBAT0L, "DBAT0L",
738 SPR_NOACCESS, SPR_NOACCESS,
739 &spr_read_dbat, &spr_write_dbatl,
740 0x00000000);
741 spr_register(env, SPR_DBAT1U, "DBAT1U",
742 SPR_NOACCESS, SPR_NOACCESS,
743 &spr_read_dbat, &spr_write_dbatu,
744 0x00000000);
745 spr_register(env, SPR_DBAT1L, "DBAT1L",
746 SPR_NOACCESS, SPR_NOACCESS,
747 &spr_read_dbat, &spr_write_dbatl,
748 0x00000000);
749 spr_register(env, SPR_DBAT2U, "DBAT2U",
750 SPR_NOACCESS, SPR_NOACCESS,
751 &spr_read_dbat, &spr_write_dbatu,
752 0x00000000);
753 spr_register(env, SPR_DBAT2L, "DBAT2L",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_dbat, &spr_write_dbatl,
756 0x00000000);
757 spr_register(env, SPR_DBAT3U, "DBAT3U",
758 SPR_NOACCESS, SPR_NOACCESS,
759 &spr_read_dbat, &spr_write_dbatu,
760 0x00000000);
761 spr_register(env, SPR_DBAT3L, "DBAT3L",
762 SPR_NOACCESS, SPR_NOACCESS,
763 &spr_read_dbat, &spr_write_dbatl,
764 0x00000000);
765 env->nb_BATs += 4;
766 #endif
767 }
768
769 /* BATs 4-7 */
770 static void gen_high_BATs (CPUPPCState *env)
771 {
772 #if !defined(CONFIG_USER_ONLY)
773 spr_register(env, SPR_IBAT4U, "IBAT4U",
774 SPR_NOACCESS, SPR_NOACCESS,
775 &spr_read_ibat_h, &spr_write_ibatu_h,
776 0x00000000);
777 spr_register(env, SPR_IBAT4L, "IBAT4L",
778 SPR_NOACCESS, SPR_NOACCESS,
779 &spr_read_ibat_h, &spr_write_ibatl_h,
780 0x00000000);
781 spr_register(env, SPR_IBAT5U, "IBAT5U",
782 SPR_NOACCESS, SPR_NOACCESS,
783 &spr_read_ibat_h, &spr_write_ibatu_h,
784 0x00000000);
785 spr_register(env, SPR_IBAT5L, "IBAT5L",
786 SPR_NOACCESS, SPR_NOACCESS,
787 &spr_read_ibat_h, &spr_write_ibatl_h,
788 0x00000000);
789 spr_register(env, SPR_IBAT6U, "IBAT6U",
790 SPR_NOACCESS, SPR_NOACCESS,
791 &spr_read_ibat_h, &spr_write_ibatu_h,
792 0x00000000);
793 spr_register(env, SPR_IBAT6L, "IBAT6L",
794 SPR_NOACCESS, SPR_NOACCESS,
795 &spr_read_ibat_h, &spr_write_ibatl_h,
796 0x00000000);
797 spr_register(env, SPR_IBAT7U, "IBAT7U",
798 SPR_NOACCESS, SPR_NOACCESS,
799 &spr_read_ibat_h, &spr_write_ibatu_h,
800 0x00000000);
801 spr_register(env, SPR_IBAT7L, "IBAT7L",
802 SPR_NOACCESS, SPR_NOACCESS,
803 &spr_read_ibat_h, &spr_write_ibatl_h,
804 0x00000000);
805 spr_register(env, SPR_DBAT4U, "DBAT4U",
806 SPR_NOACCESS, SPR_NOACCESS,
807 &spr_read_dbat_h, &spr_write_dbatu_h,
808 0x00000000);
809 spr_register(env, SPR_DBAT4L, "DBAT4L",
810 SPR_NOACCESS, SPR_NOACCESS,
811 &spr_read_dbat_h, &spr_write_dbatl_h,
812 0x00000000);
813 spr_register(env, SPR_DBAT5U, "DBAT5U",
814 SPR_NOACCESS, SPR_NOACCESS,
815 &spr_read_dbat_h, &spr_write_dbatu_h,
816 0x00000000);
817 spr_register(env, SPR_DBAT5L, "DBAT5L",
818 SPR_NOACCESS, SPR_NOACCESS,
819 &spr_read_dbat_h, &spr_write_dbatl_h,
820 0x00000000);
821 spr_register(env, SPR_DBAT6U, "DBAT6U",
822 SPR_NOACCESS, SPR_NOACCESS,
823 &spr_read_dbat_h, &spr_write_dbatu_h,
824 0x00000000);
825 spr_register(env, SPR_DBAT6L, "DBAT6L",
826 SPR_NOACCESS, SPR_NOACCESS,
827 &spr_read_dbat_h, &spr_write_dbatl_h,
828 0x00000000);
829 spr_register(env, SPR_DBAT7U, "DBAT7U",
830 SPR_NOACCESS, SPR_NOACCESS,
831 &spr_read_dbat_h, &spr_write_dbatu_h,
832 0x00000000);
833 spr_register(env, SPR_DBAT7L, "DBAT7L",
834 SPR_NOACCESS, SPR_NOACCESS,
835 &spr_read_dbat_h, &spr_write_dbatl_h,
836 0x00000000);
837 env->nb_BATs += 4;
838 #endif
839 }
840
841 /* Generic PowerPC time base */
842 static void gen_tbl (CPUPPCState *env)
843 {
844 spr_register(env, SPR_VTBL, "TBL",
845 &spr_read_tbl, SPR_NOACCESS,
846 &spr_read_tbl, SPR_NOACCESS,
847 0x00000000);
848 spr_register(env, SPR_TBL, "TBL",
849 &spr_read_tbl, SPR_NOACCESS,
850 &spr_read_tbl, &spr_write_tbl,
851 0x00000000);
852 spr_register(env, SPR_VTBU, "TBU",
853 &spr_read_tbu, SPR_NOACCESS,
854 &spr_read_tbu, SPR_NOACCESS,
855 0x00000000);
856 spr_register(env, SPR_TBU, "TBU",
857 &spr_read_tbu, SPR_NOACCESS,
858 &spr_read_tbu, &spr_write_tbu,
859 0x00000000);
860 }
861
862 /* Softare table search registers */
863 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
864 {
865 #if !defined(CONFIG_USER_ONLY)
866 env->nb_tlb = nb_tlbs;
867 env->nb_ways = nb_ways;
868 env->id_tlbs = 1;
869 env->tlb_type = TLB_6XX;
870 spr_register(env, SPR_DMISS, "DMISS",
871 SPR_NOACCESS, SPR_NOACCESS,
872 &spr_read_generic, SPR_NOACCESS,
873 0x00000000);
874 spr_register(env, SPR_DCMP, "DCMP",
875 SPR_NOACCESS, SPR_NOACCESS,
876 &spr_read_generic, SPR_NOACCESS,
877 0x00000000);
878 spr_register(env, SPR_HASH1, "HASH1",
879 SPR_NOACCESS, SPR_NOACCESS,
880 &spr_read_generic, SPR_NOACCESS,
881 0x00000000);
882 spr_register(env, SPR_HASH2, "HASH2",
883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_generic, SPR_NOACCESS,
885 0x00000000);
886 spr_register(env, SPR_IMISS, "IMISS",
887 SPR_NOACCESS, SPR_NOACCESS,
888 &spr_read_generic, SPR_NOACCESS,
889 0x00000000);
890 spr_register(env, SPR_ICMP, "ICMP",
891 SPR_NOACCESS, SPR_NOACCESS,
892 &spr_read_generic, SPR_NOACCESS,
893 0x00000000);
894 spr_register(env, SPR_RPA, "RPA",
895 SPR_NOACCESS, SPR_NOACCESS,
896 &spr_read_generic, &spr_write_generic,
897 0x00000000);
898 #endif
899 }
900
901 /* SPR common to MPC755 and G2 */
902 static void gen_spr_G2_755 (CPUPPCState *env)
903 {
904 /* SGPRs */
905 spr_register(env, SPR_SPRG4, "SPRG4",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, &spr_write_generic,
908 0x00000000);
909 spr_register(env, SPR_SPRG5, "SPRG5",
910 SPR_NOACCESS, SPR_NOACCESS,
911 &spr_read_generic, &spr_write_generic,
912 0x00000000);
913 spr_register(env, SPR_SPRG6, "SPRG6",
914 SPR_NOACCESS, SPR_NOACCESS,
915 &spr_read_generic, &spr_write_generic,
916 0x00000000);
917 spr_register(env, SPR_SPRG7, "SPRG7",
918 SPR_NOACCESS, SPR_NOACCESS,
919 &spr_read_generic, &spr_write_generic,
920 0x00000000);
921 }
922
923 /* SPR common to all 7xx PowerPC implementations */
924 static void gen_spr_7xx (CPUPPCState *env)
925 {
926 /* Breakpoints */
927 /* XXX : not implemented */
928 spr_register(env, SPR_DABR, "DABR",
929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_generic, &spr_write_generic,
931 0x00000000);
932 /* XXX : not implemented */
933 spr_register(env, SPR_IABR, "IABR",
934 SPR_NOACCESS, SPR_NOACCESS,
935 &spr_read_generic, &spr_write_generic,
936 0x00000000);
937 /* Cache management */
938 /* XXX : not implemented */
939 spr_register(env, SPR_ICTC, "ICTC",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943 /* Performance monitors */
944 /* XXX : not implemented */
945 spr_register(env, SPR_MMCR0, "MMCR0",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_generic, &spr_write_generic,
948 0x00000000);
949 /* XXX : not implemented */
950 spr_register(env, SPR_MMCR1, "MMCR1",
951 SPR_NOACCESS, SPR_NOACCESS,
952 &spr_read_generic, &spr_write_generic,
953 0x00000000);
954 /* XXX : not implemented */
955 spr_register(env, SPR_PMC1, "PMC1",
956 SPR_NOACCESS, SPR_NOACCESS,
957 &spr_read_generic, &spr_write_generic,
958 0x00000000);
959 /* XXX : not implemented */
960 spr_register(env, SPR_PMC2, "PMC2",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, &spr_write_generic,
963 0x00000000);
964 /* XXX : not implemented */
965 spr_register(env, SPR_PMC3, "PMC3",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, &spr_write_generic,
968 0x00000000);
969 /* XXX : not implemented */
970 spr_register(env, SPR_PMC4, "PMC4",
971 SPR_NOACCESS, SPR_NOACCESS,
972 &spr_read_generic, &spr_write_generic,
973 0x00000000);
974 /* XXX : not implemented */
975 spr_register(env, SPR_SIAR, "SIAR",
976 SPR_NOACCESS, SPR_NOACCESS,
977 &spr_read_generic, SPR_NOACCESS,
978 0x00000000);
979 /* XXX : not implemented */
980 spr_register(env, SPR_UMMCR0, "UMMCR0",
981 &spr_read_ureg, SPR_NOACCESS,
982 &spr_read_ureg, SPR_NOACCESS,
983 0x00000000);
984 /* XXX : not implemented */
985 spr_register(env, SPR_UMMCR1, "UMMCR1",
986 &spr_read_ureg, SPR_NOACCESS,
987 &spr_read_ureg, SPR_NOACCESS,
988 0x00000000);
989 /* XXX : not implemented */
990 spr_register(env, SPR_UPMC1, "UPMC1",
991 &spr_read_ureg, SPR_NOACCESS,
992 &spr_read_ureg, SPR_NOACCESS,
993 0x00000000);
994 /* XXX : not implemented */
995 spr_register(env, SPR_UPMC2, "UPMC2",
996 &spr_read_ureg, SPR_NOACCESS,
997 &spr_read_ureg, SPR_NOACCESS,
998 0x00000000);
999 /* XXX : not implemented */
1000 spr_register(env, SPR_UPMC3, "UPMC3",
1001 &spr_read_ureg, SPR_NOACCESS,
1002 &spr_read_ureg, SPR_NOACCESS,
1003 0x00000000);
1004 /* XXX : not implemented */
1005 spr_register(env, SPR_UPMC4, "UPMC4",
1006 &spr_read_ureg, SPR_NOACCESS,
1007 &spr_read_ureg, SPR_NOACCESS,
1008 0x00000000);
1009 /* XXX : not implemented */
1010 spr_register(env, SPR_USIAR, "USIAR",
1011 &spr_read_ureg, SPR_NOACCESS,
1012 &spr_read_ureg, SPR_NOACCESS,
1013 0x00000000);
1014 /* External access control */
1015 /* XXX : not implemented */
1016 spr_register(env, SPR_EAR, "EAR",
1017 SPR_NOACCESS, SPR_NOACCESS,
1018 &spr_read_generic, &spr_write_generic,
1019 0x00000000);
1020 }
1021
1022 static void gen_spr_thrm (CPUPPCState *env)
1023 {
1024 /* Thermal management */
1025 /* XXX : not implemented */
1026 spr_register(env, SPR_THRM1, "THRM1",
1027 SPR_NOACCESS, SPR_NOACCESS,
1028 &spr_read_generic, &spr_write_generic,
1029 0x00000000);
1030 /* XXX : not implemented */
1031 spr_register(env, SPR_THRM2, "THRM2",
1032 SPR_NOACCESS, SPR_NOACCESS,
1033 &spr_read_generic, &spr_write_generic,
1034 0x00000000);
1035 /* XXX : not implemented */
1036 spr_register(env, SPR_THRM3, "THRM3",
1037 SPR_NOACCESS, SPR_NOACCESS,
1038 &spr_read_generic, &spr_write_generic,
1039 0x00000000);
1040 }
1041
1042 /* SPR specific to PowerPC 604 implementation */
1043 static void gen_spr_604 (CPUPPCState *env)
1044 {
1045 /* Processor identification */
1046 spr_register(env, SPR_PIR, "PIR",
1047 SPR_NOACCESS, SPR_NOACCESS,
1048 &spr_read_generic, &spr_write_pir,
1049 0x00000000);
1050 /* Breakpoints */
1051 /* XXX : not implemented */
1052 spr_register(env, SPR_IABR, "IABR",
1053 SPR_NOACCESS, SPR_NOACCESS,
1054 &spr_read_generic, &spr_write_generic,
1055 0x00000000);
1056 /* XXX : not implemented */
1057 spr_register(env, SPR_DABR, "DABR",
1058 SPR_NOACCESS, SPR_NOACCESS,
1059 &spr_read_generic, &spr_write_generic,
1060 0x00000000);
1061 /* Performance counters */
1062 /* XXX : not implemented */
1063 spr_register(env, SPR_MMCR0, "MMCR0",
1064 SPR_NOACCESS, SPR_NOACCESS,
1065 &spr_read_generic, &spr_write_generic,
1066 0x00000000);
1067 /* XXX : not implemented */
1068 spr_register(env, SPR_PMC1, "PMC1",
1069 SPR_NOACCESS, SPR_NOACCESS,
1070 &spr_read_generic, &spr_write_generic,
1071 0x00000000);
1072 /* XXX : not implemented */
1073 spr_register(env, SPR_PMC2, "PMC2",
1074 SPR_NOACCESS, SPR_NOACCESS,
1075 &spr_read_generic, &spr_write_generic,
1076 0x00000000);
1077 /* XXX : not implemented */
1078 spr_register(env, SPR_SIAR, "SIAR",
1079 SPR_NOACCESS, SPR_NOACCESS,
1080 &spr_read_generic, SPR_NOACCESS,
1081 0x00000000);
1082 /* XXX : not implemented */
1083 spr_register(env, SPR_SDA, "SDA",
1084 SPR_NOACCESS, SPR_NOACCESS,
1085 &spr_read_generic, SPR_NOACCESS,
1086 0x00000000);
1087 /* External access control */
1088 /* XXX : not implemented */
1089 spr_register(env, SPR_EAR, "EAR",
1090 SPR_NOACCESS, SPR_NOACCESS,
1091 &spr_read_generic, &spr_write_generic,
1092 0x00000000);
1093 }
1094
1095 /* SPR specific to PowerPC 603 implementation */
1096 static void gen_spr_603 (CPUPPCState *env)
1097 {
1098 /* External access control */
1099 /* XXX : not implemented */
1100 spr_register(env, SPR_EAR, "EAR",
1101 SPR_NOACCESS, SPR_NOACCESS,
1102 &spr_read_generic, &spr_write_generic,
1103 0x00000000);
1104 }
1105
1106 /* SPR specific to PowerPC G2 implementation */
1107 static void gen_spr_G2 (CPUPPCState *env)
1108 {
1109 /* Memory base address */
1110 /* MBAR */
1111 /* XXX : not implemented */
1112 spr_register(env, SPR_MBAR, "MBAR",
1113 SPR_NOACCESS, SPR_NOACCESS,
1114 &spr_read_generic, &spr_write_generic,
1115 0x00000000);
1116 /* Exception processing */
1117 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1118 SPR_NOACCESS, SPR_NOACCESS,
1119 &spr_read_generic, &spr_write_generic,
1120 0x00000000);
1121 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1122 SPR_NOACCESS, SPR_NOACCESS,
1123 &spr_read_generic, &spr_write_generic,
1124 0x00000000);
1125 /* Breakpoints */
1126 /* XXX : not implemented */
1127 spr_register(env, SPR_DABR, "DABR",
1128 SPR_NOACCESS, SPR_NOACCESS,
1129 &spr_read_generic, &spr_write_generic,
1130 0x00000000);
1131 /* XXX : not implemented */
1132 spr_register(env, SPR_DABR2, "DABR2",
1133 SPR_NOACCESS, SPR_NOACCESS,
1134 &spr_read_generic, &spr_write_generic,
1135 0x00000000);
1136 /* XXX : not implemented */
1137 spr_register(env, SPR_IABR, "IABR",
1138 SPR_NOACCESS, SPR_NOACCESS,
1139 &spr_read_generic, &spr_write_generic,
1140 0x00000000);
1141 /* XXX : not implemented */
1142 spr_register(env, SPR_IABR2, "IABR2",
1143 SPR_NOACCESS, SPR_NOACCESS,
1144 &spr_read_generic, &spr_write_generic,
1145 0x00000000);
1146 /* XXX : not implemented */
1147 spr_register(env, SPR_IBCR, "IBCR",
1148 SPR_NOACCESS, SPR_NOACCESS,
1149 &spr_read_generic, &spr_write_generic,
1150 0x00000000);
1151 /* XXX : not implemented */
1152 spr_register(env, SPR_DBCR, "DBCR",
1153 SPR_NOACCESS, SPR_NOACCESS,
1154 &spr_read_generic, &spr_write_generic,
1155 0x00000000);
1156 }
1157
1158 /* SPR specific to PowerPC 602 implementation */
1159 static void gen_spr_602 (CPUPPCState *env)
1160 {
1161 /* ESA registers */
1162 /* XXX : not implemented */
1163 spr_register(env, SPR_SER, "SER",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_generic, &spr_write_generic,
1166 0x00000000);
1167 /* XXX : not implemented */
1168 spr_register(env, SPR_SEBR, "SEBR",
1169 SPR_NOACCESS, SPR_NOACCESS,
1170 &spr_read_generic, &spr_write_generic,
1171 0x00000000);
1172 /* XXX : not implemented */
1173 spr_register(env, SPR_ESASRR, "ESASRR",
1174 SPR_NOACCESS, SPR_NOACCESS,
1175 &spr_read_generic, &spr_write_generic,
1176 0x00000000);
1177 /* Floating point status */
1178 /* XXX : not implemented */
1179 spr_register(env, SPR_SP, "SP",
1180 SPR_NOACCESS, SPR_NOACCESS,
1181 &spr_read_generic, &spr_write_generic,
1182 0x00000000);
1183 /* XXX : not implemented */
1184 spr_register(env, SPR_LT, "LT",
1185 SPR_NOACCESS, SPR_NOACCESS,
1186 &spr_read_generic, &spr_write_generic,
1187 0x00000000);
1188 /* Watchdog timer */
1189 /* XXX : not implemented */
1190 spr_register(env, SPR_TCR, "TCR",
1191 SPR_NOACCESS, SPR_NOACCESS,
1192 &spr_read_generic, &spr_write_generic,
1193 0x00000000);
1194 /* Interrupt base */
1195 spr_register(env, SPR_IBR, "IBR",
1196 SPR_NOACCESS, SPR_NOACCESS,
1197 &spr_read_generic, &spr_write_generic,
1198 0x00000000);
1199 /* XXX : not implemented */
1200 spr_register(env, SPR_IABR, "IABR",
1201 SPR_NOACCESS, SPR_NOACCESS,
1202 &spr_read_generic, &spr_write_generic,
1203 0x00000000);
1204 }
1205
1206 /* SPR specific to PowerPC 601 implementation */
1207 static void gen_spr_601 (CPUPPCState *env)
1208 {
1209 /* Multiplication/division register */
1210 /* MQ */
1211 spr_register(env, SPR_MQ, "MQ",
1212 &spr_read_generic, &spr_write_generic,
1213 &spr_read_generic, &spr_write_generic,
1214 0x00000000);
1215 /* RTC registers */
1216 spr_register(env, SPR_601_RTCU, "RTCU",
1217 SPR_NOACCESS, SPR_NOACCESS,
1218 SPR_NOACCESS, &spr_write_601_rtcu,
1219 0x00000000);
1220 spr_register(env, SPR_601_VRTCU, "RTCU",
1221 &spr_read_601_rtcu, SPR_NOACCESS,
1222 &spr_read_601_rtcu, SPR_NOACCESS,
1223 0x00000000);
1224 spr_register(env, SPR_601_RTCL, "RTCL",
1225 SPR_NOACCESS, SPR_NOACCESS,
1226 SPR_NOACCESS, &spr_write_601_rtcl,
1227 0x00000000);
1228 spr_register(env, SPR_601_VRTCL, "RTCL",
1229 &spr_read_601_rtcl, SPR_NOACCESS,
1230 &spr_read_601_rtcl, SPR_NOACCESS,
1231 0x00000000);
1232 /* Timer */
1233 #if 0 /* ? */
1234 spr_register(env, SPR_601_UDECR, "UDECR",
1235 &spr_read_decr, SPR_NOACCESS,
1236 &spr_read_decr, SPR_NOACCESS,
1237 0x00000000);
1238 #endif
1239 /* External access control */
1240 /* XXX : not implemented */
1241 spr_register(env, SPR_EAR, "EAR",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_generic, &spr_write_generic,
1244 0x00000000);
1245 /* Memory management */
1246 #if !defined(CONFIG_USER_ONLY)
1247 spr_register(env, SPR_IBAT0U, "IBAT0U",
1248 SPR_NOACCESS, SPR_NOACCESS,
1249 &spr_read_601_ubat, &spr_write_601_ubatu,
1250 0x00000000);
1251 spr_register(env, SPR_IBAT0L, "IBAT0L",
1252 SPR_NOACCESS, SPR_NOACCESS,
1253 &spr_read_601_ubat, &spr_write_601_ubatl,
1254 0x00000000);
1255 spr_register(env, SPR_IBAT1U, "IBAT1U",
1256 SPR_NOACCESS, SPR_NOACCESS,
1257 &spr_read_601_ubat, &spr_write_601_ubatu,
1258 0x00000000);
1259 spr_register(env, SPR_IBAT1L, "IBAT1L",
1260 SPR_NOACCESS, SPR_NOACCESS,
1261 &spr_read_601_ubat, &spr_write_601_ubatl,
1262 0x00000000);
1263 spr_register(env, SPR_IBAT2U, "IBAT2U",
1264 SPR_NOACCESS, SPR_NOACCESS,
1265 &spr_read_601_ubat, &spr_write_601_ubatu,
1266 0x00000000);
1267 spr_register(env, SPR_IBAT2L, "IBAT2L",
1268 SPR_NOACCESS, SPR_NOACCESS,
1269 &spr_read_601_ubat, &spr_write_601_ubatl,
1270 0x00000000);
1271 spr_register(env, SPR_IBAT3U, "IBAT3U",
1272 SPR_NOACCESS, SPR_NOACCESS,
1273 &spr_read_601_ubat, &spr_write_601_ubatu,
1274 0x00000000);
1275 spr_register(env, SPR_IBAT3L, "IBAT3L",
1276 SPR_NOACCESS, SPR_NOACCESS,
1277 &spr_read_601_ubat, &spr_write_601_ubatl,
1278 0x00000000);
1279 env->nb_BATs = 4;
1280 #endif
1281 }
1282
1283 static void gen_spr_74xx (CPUPPCState *env)
1284 {
1285 /* Processor identification */
1286 spr_register(env, SPR_PIR, "PIR",
1287 SPR_NOACCESS, SPR_NOACCESS,
1288 &spr_read_generic, &spr_write_pir,
1289 0x00000000);
1290 /* XXX : not implemented */
1291 spr_register(env, SPR_MMCR2, "MMCR2",
1292 SPR_NOACCESS, SPR_NOACCESS,
1293 &spr_read_generic, &spr_write_generic,
1294 0x00000000);
1295 /* XXX : not implemented */
1296 spr_register(env, SPR_UMMCR2, "UMMCR2",
1297 &spr_read_ureg, SPR_NOACCESS,
1298 &spr_read_ureg, SPR_NOACCESS,
1299 0x00000000);
1300 /* XXX: not implemented */
1301 spr_register(env, SPR_BAMR, "BAMR",
1302 SPR_NOACCESS, SPR_NOACCESS,
1303 &spr_read_generic, &spr_write_generic,
1304 0x00000000);
1305 /* XXX : not implemented */
1306 spr_register(env, SPR_MSSCR0, "MSSCR0",
1307 SPR_NOACCESS, SPR_NOACCESS,
1308 &spr_read_generic, &spr_write_generic,
1309 0x00000000);
1310 /* Hardware implementation registers */
1311 /* XXX : not implemented */
1312 spr_register(env, SPR_HID0, "HID0",
1313 SPR_NOACCESS, SPR_NOACCESS,
1314 &spr_read_generic, &spr_write_generic,
1315 0x00000000);
1316 /* XXX : not implemented */
1317 spr_register(env, SPR_HID1, "HID1",
1318 SPR_NOACCESS, SPR_NOACCESS,
1319 &spr_read_generic, &spr_write_generic,
1320 0x00000000);
1321 /* Altivec */
1322 spr_register(env, SPR_VRSAVE, "VRSAVE",
1323 &spr_read_generic, &spr_write_generic,
1324 &spr_read_generic, &spr_write_generic,
1325 0x00000000);
1326 /* XXX : not implemented */
1327 spr_register(env, SPR_L2CR, "L2CR",
1328 SPR_NOACCESS, SPR_NOACCESS,
1329 &spr_read_generic, &spr_write_generic,
1330 0x00000000);
1331 /* Not strictly an SPR */
1332 vscr_init(env, 0x00010000);
1333 }
1334
1335 static void gen_l3_ctrl (CPUPPCState *env)
1336 {
1337 /* L3CR */
1338 /* XXX : not implemented */
1339 spr_register(env, SPR_L3CR, "L3CR",
1340 SPR_NOACCESS, SPR_NOACCESS,
1341 &spr_read_generic, &spr_write_generic,
1342 0x00000000);
1343 /* L3ITCR0 */
1344 /* XXX : not implemented */
1345 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1346 SPR_NOACCESS, SPR_NOACCESS,
1347 &spr_read_generic, &spr_write_generic,
1348 0x00000000);
1349 /* L3PM */
1350 /* XXX : not implemented */
1351 spr_register(env, SPR_L3PM, "L3PM",
1352 SPR_NOACCESS, SPR_NOACCESS,
1353 &spr_read_generic, &spr_write_generic,
1354 0x00000000);
1355 }
1356
1357 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1358 {
1359 #if !defined(CONFIG_USER_ONLY)
1360 env->nb_tlb = nb_tlbs;
1361 env->nb_ways = nb_ways;
1362 env->id_tlbs = 1;
1363 env->tlb_type = TLB_6XX;
1364 /* XXX : not implemented */
1365 spr_register(env, SPR_PTEHI, "PTEHI",
1366 SPR_NOACCESS, SPR_NOACCESS,
1367 &spr_read_generic, &spr_write_generic,
1368 0x00000000);
1369 /* XXX : not implemented */
1370 spr_register(env, SPR_PTELO, "PTELO",
1371 SPR_NOACCESS, SPR_NOACCESS,
1372 &spr_read_generic, &spr_write_generic,
1373 0x00000000);
1374 /* XXX : not implemented */
1375 spr_register(env, SPR_TLBMISS, "TLBMISS",
1376 SPR_NOACCESS, SPR_NOACCESS,
1377 &spr_read_generic, &spr_write_generic,
1378 0x00000000);
1379 #endif
1380 }
1381
1382 #if !defined(CONFIG_USER_ONLY)
1383 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1384 {
1385 TCGv t0 = tcg_temp_new();
1386
1387 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1388 gen_store_spr(sprn, t0);
1389 tcg_temp_free(t0);
1390 }
1391
1392 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1393 {
1394 TCGv_i32 t0 = tcg_const_i32(sprn);
1395 gen_helper_booke206_tlbflush(cpu_env, t0);
1396 tcg_temp_free_i32(t0);
1397 }
1398
1399 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1400 {
1401 TCGv_i32 t0 = tcg_const_i32(sprn);
1402 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1403 tcg_temp_free_i32(t0);
1404 }
1405 #endif
1406
1407 static void gen_spr_usprgh (CPUPPCState *env)
1408 {
1409 spr_register(env, SPR_USPRG4, "USPRG4",
1410 &spr_read_ureg, SPR_NOACCESS,
1411 &spr_read_ureg, SPR_NOACCESS,
1412 0x00000000);
1413 spr_register(env, SPR_USPRG5, "USPRG5",
1414 &spr_read_ureg, SPR_NOACCESS,
1415 &spr_read_ureg, SPR_NOACCESS,
1416 0x00000000);
1417 spr_register(env, SPR_USPRG6, "USPRG6",
1418 &spr_read_ureg, SPR_NOACCESS,
1419 &spr_read_ureg, SPR_NOACCESS,
1420 0x00000000);
1421 spr_register(env, SPR_USPRG7, "USPRG7",
1422 &spr_read_ureg, SPR_NOACCESS,
1423 &spr_read_ureg, SPR_NOACCESS,
1424 0x00000000);
1425 }
1426
1427 /* PowerPC BookE SPR */
1428 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1429 {
1430 const char *ivor_names[64] = {
1431 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1432 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1433 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1434 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1435 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1436 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1437 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1438 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1439 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1440 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1441 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1442 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1443 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1444 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1445 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1446 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1447 };
1448 #define SPR_BOOKE_IVORxx (-1)
1449 int ivor_sprn[64] = {
1450 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1451 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1452 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1453 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1454 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1455 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1456 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1457 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1458 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1459 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1460 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1461 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1462 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1463 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1464 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1465 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1466 };
1467 int i;
1468
1469 /* Interrupt processing */
1470 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1471 SPR_NOACCESS, SPR_NOACCESS,
1472 &spr_read_generic, &spr_write_generic,
1473 0x00000000);
1474 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1475 SPR_NOACCESS, SPR_NOACCESS,
1476 &spr_read_generic, &spr_write_generic,
1477 0x00000000);
1478 /* Debug */
1479 /* XXX : not implemented */
1480 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1481 SPR_NOACCESS, SPR_NOACCESS,
1482 &spr_read_generic, &spr_write_generic,
1483 0x00000000);
1484 /* XXX : not implemented */
1485 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1486 SPR_NOACCESS, SPR_NOACCESS,
1487 &spr_read_generic, &spr_write_generic,
1488 0x00000000);
1489 /* XXX : not implemented */
1490 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1491 SPR_NOACCESS, SPR_NOACCESS,
1492 &spr_read_generic, &spr_write_generic,
1493 0x00000000);
1494 /* XXX : not implemented */
1495 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1496 SPR_NOACCESS, SPR_NOACCESS,
1497 &spr_read_generic, &spr_write_generic,
1498 0x00000000);
1499 /* XXX : not implemented */
1500 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1501 SPR_NOACCESS, SPR_NOACCESS,
1502 &spr_read_generic, &spr_write_40x_dbcr0,
1503 0x00000000);
1504 /* XXX : not implemented */
1505 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1506 SPR_NOACCESS, SPR_NOACCESS,
1507 &spr_read_generic, &spr_write_generic,
1508 0x00000000);
1509 /* XXX : not implemented */
1510 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1511 SPR_NOACCESS, SPR_NOACCESS,
1512 &spr_read_generic, &spr_write_generic,
1513 0x00000000);
1514 /* XXX : not implemented */
1515 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1516 SPR_NOACCESS, SPR_NOACCESS,
1517 &spr_read_generic, &spr_write_clear,
1518 0x00000000);
1519 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1520 SPR_NOACCESS, SPR_NOACCESS,
1521 &spr_read_generic, &spr_write_generic,
1522 0x00000000);
1523 spr_register(env, SPR_BOOKE_ESR, "ESR",
1524 SPR_NOACCESS, SPR_NOACCESS,
1525 &spr_read_generic, &spr_write_generic,
1526 0x00000000);
1527 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1528 SPR_NOACCESS, SPR_NOACCESS,
1529 &spr_read_generic, &spr_write_excp_prefix,
1530 0x00000000);
1531 /* Exception vectors */
1532 for (i = 0; i < 64; i++) {
1533 if (ivor_mask & (1ULL << i)) {
1534 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1535 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1536 exit(1);
1537 }
1538 spr_register(env, ivor_sprn[i], ivor_names[i],
1539 SPR_NOACCESS, SPR_NOACCESS,
1540 &spr_read_generic, &spr_write_excp_vector,
1541 0x00000000);
1542 }
1543 }
1544 spr_register(env, SPR_BOOKE_PID, "PID",
1545 SPR_NOACCESS, SPR_NOACCESS,
1546 &spr_read_generic, &spr_write_booke_pid,
1547 0x00000000);
1548 spr_register(env, SPR_BOOKE_TCR, "TCR",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_booke_tcr,
1551 0x00000000);
1552 spr_register(env, SPR_BOOKE_TSR, "TSR",
1553 SPR_NOACCESS, SPR_NOACCESS,
1554 &spr_read_generic, &spr_write_booke_tsr,
1555 0x00000000);
1556 /* Timer */
1557 spr_register(env, SPR_DECR, "DECR",
1558 SPR_NOACCESS, SPR_NOACCESS,
1559 &spr_read_decr, &spr_write_decr,
1560 0x00000000);
1561 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1562 SPR_NOACCESS, SPR_NOACCESS,
1563 SPR_NOACCESS, &spr_write_generic,
1564 0x00000000);
1565 /* SPRGs */
1566 spr_register(env, SPR_USPRG0, "USPRG0",
1567 &spr_read_generic, &spr_write_generic,
1568 &spr_read_generic, &spr_write_generic,
1569 0x00000000);
1570 spr_register(env, SPR_SPRG4, "SPRG4",
1571 SPR_NOACCESS, SPR_NOACCESS,
1572 &spr_read_generic, &spr_write_generic,
1573 0x00000000);
1574 spr_register(env, SPR_SPRG5, "SPRG5",
1575 SPR_NOACCESS, SPR_NOACCESS,
1576 &spr_read_generic, &spr_write_generic,
1577 0x00000000);
1578 spr_register(env, SPR_SPRG6, "SPRG6",
1579 SPR_NOACCESS, SPR_NOACCESS,
1580 &spr_read_generic, &spr_write_generic,
1581 0x00000000);
1582 spr_register(env, SPR_SPRG7, "SPRG7",
1583 SPR_NOACCESS, SPR_NOACCESS,
1584 &spr_read_generic, &spr_write_generic,
1585 0x00000000);
1586 }
1587
1588 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1589 uint32_t maxsize, uint32_t flags,
1590 uint32_t nentries)
1591 {
1592 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1593 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1594 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1595 flags | nentries;
1596 }
1597
1598 /* BookE 2.06 storage control registers */
1599 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1600 uint32_t *tlbncfg)
1601 {
1602 #if !defined(CONFIG_USER_ONLY)
1603 const char *mas_names[8] = {
1604 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1605 };
1606 int mas_sprn[8] = {
1607 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1608 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1609 };
1610 int i;
1611
1612 /* TLB assist registers */
1613 /* XXX : not implemented */
1614 for (i = 0; i < 8; i++) {
1615 void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1616 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1617 uea_write = &spr_write_generic;
1618 }
1619 if (mas_mask & (1 << i)) {
1620 spr_register(env, mas_sprn[i], mas_names[i],
1621 SPR_NOACCESS, SPR_NOACCESS,
1622 &spr_read_generic, uea_write,
1623 0x00000000);
1624 }
1625 }
1626 if (env->nb_pids > 1) {
1627 /* XXX : not implemented */
1628 spr_register(env, SPR_BOOKE_PID1, "PID1",
1629 SPR_NOACCESS, SPR_NOACCESS,
1630 &spr_read_generic, &spr_write_booke_pid,
1631 0x00000000);
1632 }
1633 if (env->nb_pids > 2) {
1634 /* XXX : not implemented */
1635 spr_register(env, SPR_BOOKE_PID2, "PID2",
1636 SPR_NOACCESS, SPR_NOACCESS,
1637 &spr_read_generic, &spr_write_booke_pid,
1638 0x00000000);
1639 }
1640 /* XXX : not implemented */
1641 spr_register(env, SPR_MMUCFG, "MMUCFG",
1642 SPR_NOACCESS, SPR_NOACCESS,
1643 &spr_read_generic, SPR_NOACCESS,
1644 0x00000000); /* TOFIX */
1645 switch (env->nb_ways) {
1646 case 4:
1647 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1648 SPR_NOACCESS, SPR_NOACCESS,
1649 &spr_read_generic, SPR_NOACCESS,
1650 tlbncfg[3]);
1651 /* Fallthru */
1652 case 3:
1653 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1654 SPR_NOACCESS, SPR_NOACCESS,
1655 &spr_read_generic, SPR_NOACCESS,
1656 tlbncfg[2]);
1657 /* Fallthru */
1658 case 2:
1659 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1660 SPR_NOACCESS, SPR_NOACCESS,
1661 &spr_read_generic, SPR_NOACCESS,
1662 tlbncfg[1]);
1663 /* Fallthru */
1664 case 1:
1665 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1666 SPR_NOACCESS, SPR_NOACCESS,
1667 &spr_read_generic, SPR_NOACCESS,
1668 tlbncfg[0]);
1669 /* Fallthru */
1670 case 0:
1671 default:
1672 break;
1673 }
1674 #endif
1675
1676 gen_spr_usprgh(env);
1677 }
1678
1679 /* SPR specific to PowerPC 440 implementation */
1680 static void gen_spr_440 (CPUPPCState *env)
1681 {
1682 /* Cache control */
1683 /* XXX : not implemented */
1684 spr_register(env, SPR_440_DNV0, "DNV0",
1685 SPR_NOACCESS, SPR_NOACCESS,
1686 &spr_read_generic, &spr_write_generic,
1687 0x00000000);
1688 /* XXX : not implemented */
1689 spr_register(env, SPR_440_DNV1, "DNV1",
1690 SPR_NOACCESS, SPR_NOACCESS,
1691 &spr_read_generic, &spr_write_generic,
1692 0x00000000);
1693 /* XXX : not implemented */
1694 spr_register(env, SPR_440_DNV2, "DNV2",
1695 SPR_NOACCESS, SPR_NOACCESS,
1696 &spr_read_generic, &spr_write_generic,
1697 0x00000000);
1698 /* XXX : not implemented */
1699 spr_register(env, SPR_440_DNV3, "DNV3",
1700 SPR_NOACCESS, SPR_NOACCESS,
1701 &spr_read_generic, &spr_write_generic,
1702 0x00000000);
1703 /* XXX : not implemented */
1704 spr_register(env, SPR_440_DTV0, "DTV0",
1705 SPR_NOACCESS, SPR_NOACCESS,
1706 &spr_read_generic, &spr_write_generic,
1707 0x00000000);
1708 /* XXX : not implemented */
1709 spr_register(env, SPR_440_DTV1, "DTV1",
1710 SPR_NOACCESS, SPR_NOACCESS,
1711 &spr_read_generic, &spr_write_generic,
1712 0x00000000);
1713 /* XXX : not implemented */
1714 spr_register(env, SPR_440_DTV2, "DTV2",
1715 SPR_NOACCESS, SPR_NOACCESS,
1716 &spr_read_generic, &spr_write_generic,
1717 0x00000000);
1718 /* XXX : not implemented */
1719 spr_register(env, SPR_440_DTV3, "DTV3",
1720 SPR_NOACCESS, SPR_NOACCESS,
1721 &spr_read_generic, &spr_write_generic,
1722 0x00000000);
1723 /* XXX : not implemented */
1724 spr_register(env, SPR_440_DVLIM, "DVLIM",
1725 SPR_NOACCESS, SPR_NOACCESS,
1726 &spr_read_generic, &spr_write_generic,
1727 0x00000000);
1728 /* XXX : not implemented */
1729 spr_register(env, SPR_440_INV0, "INV0",
1730 SPR_NOACCESS, SPR_NOACCESS,
1731 &spr_read_generic, &spr_write_generic,
1732 0x00000000);
1733 /* XXX : not implemented */
1734 spr_register(env, SPR_440_INV1, "INV1",
1735 SPR_NOACCESS, SPR_NOACCESS,
1736 &spr_read_generic, &spr_write_generic,
1737 0x00000000);
1738 /* XXX : not implemented */
1739 spr_register(env, SPR_440_INV2, "INV2",
1740 SPR_NOACCESS, SPR_NOACCESS,
1741 &spr_read_generic, &spr_write_generic,
1742 0x00000000);
1743 /* XXX : not implemented */
1744 spr_register(env, SPR_440_INV3, "INV3",
1745 SPR_NOACCESS, SPR_NOACCESS,
1746 &spr_read_generic, &spr_write_generic,
1747 0x00000000);
1748 /* XXX : not implemented */
1749 spr_register(env, SPR_440_ITV0, "ITV0",
1750 SPR_NOACCESS, SPR_NOACCESS,
1751 &spr_read_generic, &spr_write_generic,
1752 0x00000000);
1753 /* XXX : not implemented */
1754 spr_register(env, SPR_440_ITV1, "ITV1",
1755 SPR_NOACCESS, SPR_NOACCESS,
1756 &spr_read_generic, &spr_write_generic,
1757 0x00000000);
1758 /* XXX : not implemented */
1759 spr_register(env, SPR_440_ITV2, "ITV2",
1760 SPR_NOACCESS, SPR_NOACCESS,
1761 &spr_read_generic, &spr_write_generic,
1762 0x00000000);
1763 /* XXX : not implemented */
1764 spr_register(env, SPR_440_ITV3, "ITV3",
1765 SPR_NOACCESS, SPR_NOACCESS,
1766 &spr_read_generic, &spr_write_generic,
1767 0x00000000);
1768 /* XXX : not implemented */
1769 spr_register(env, SPR_440_IVLIM, "IVLIM",
1770 SPR_NOACCESS, SPR_NOACCESS,
1771 &spr_read_generic, &spr_write_generic,
1772 0x00000000);
1773 /* Cache debug */
1774 /* XXX : not implemented */
1775 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1776 SPR_NOACCESS, SPR_NOACCESS,
1777 &spr_read_generic, SPR_NOACCESS,
1778 0x00000000);
1779 /* XXX : not implemented */
1780 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1781 SPR_NOACCESS, SPR_NOACCESS,
1782 &spr_read_generic, SPR_NOACCESS,
1783 0x00000000);
1784 /* XXX : not implemented */
1785 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1786 SPR_NOACCESS, SPR_NOACCESS,
1787 &spr_read_generic, SPR_NOACCESS,
1788 0x00000000);
1789 /* XXX : not implemented */
1790 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1791 SPR_NOACCESS, SPR_NOACCESS,
1792 &spr_read_generic, SPR_NOACCESS,
1793 0x00000000);
1794 /* XXX : not implemented */
1795 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1796 SPR_NOACCESS, SPR_NOACCESS,
1797 &spr_read_generic, SPR_NOACCESS,
1798 0x00000000);
1799 /* XXX : not implemented */
1800 spr_register(env, SPR_440_DBDR, "DBDR",
1801 SPR_NOACCESS, SPR_NOACCESS,
1802 &spr_read_generic, &spr_write_generic,
1803 0x00000000);
1804 /* Processor control */
1805 spr_register(env, SPR_4xx_CCR0, "CCR0",
1806 SPR_NOACCESS, SPR_NOACCESS,
1807 &spr_read_generic, &spr_write_generic,
1808 0x00000000);
1809 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1810 SPR_NOACCESS, SPR_NOACCESS,
1811 &spr_read_generic, SPR_NOACCESS,
1812 0x00000000);
1813 /* Storage control */
1814 spr_register(env, SPR_440_MMUCR, "MMUCR",
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_generic, &spr_write_generic,
1817 0x00000000);
1818 }
1819
1820 /* SPR shared between PowerPC 40x implementations */
1821 static void gen_spr_40x (CPUPPCState *env)
1822 {
1823 /* Cache */
1824 /* not emulated, as QEMU do not emulate caches */
1825 spr_register(env, SPR_40x_DCCR, "DCCR",
1826 SPR_NOACCESS, SPR_NOACCESS,
1827 &spr_read_generic, &spr_write_generic,
1828 0x00000000);
1829 /* not emulated, as QEMU do not emulate caches */
1830 spr_register(env, SPR_40x_ICCR, "ICCR",
1831 SPR_NOACCESS, SPR_NOACCESS,
1832 &spr_read_generic, &spr_write_generic,
1833 0x00000000);
1834 /* not emulated, as QEMU do not emulate caches */
1835 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1836 SPR_NOACCESS, SPR_NOACCESS,
1837 &spr_read_generic, SPR_NOACCESS,
1838 0x00000000);
1839 /* Exception */
1840 spr_register(env, SPR_40x_DEAR, "DEAR",
1841 SPR_NOACCESS, SPR_NOACCESS,
1842 &spr_read_generic, &spr_write_generic,
1843 0x00000000);
1844 spr_register(env, SPR_40x_ESR, "ESR",
1845 SPR_NOACCESS, SPR_NOACCESS,
1846 &spr_read_generic, &spr_write_generic,
1847 0x00000000);
1848 spr_register(env, SPR_40x_EVPR, "EVPR",
1849 SPR_NOACCESS, SPR_NOACCESS,
1850 &spr_read_generic, &spr_write_excp_prefix,
1851 0x00000000);
1852 spr_register(env, SPR_40x_SRR2, "SRR2",
1853 &spr_read_generic, &spr_write_generic,
1854 &spr_read_generic, &spr_write_generic,
1855 0x00000000);
1856 spr_register(env, SPR_40x_SRR3, "SRR3",
1857 &spr_read_generic, &spr_write_generic,
1858 &spr_read_generic, &spr_write_generic,
1859 0x00000000);
1860 /* Timers */
1861 spr_register(env, SPR_40x_PIT, "PIT",
1862 SPR_NOACCESS, SPR_NOACCESS,
1863 &spr_read_40x_pit, &spr_write_40x_pit,
1864 0x00000000);
1865 spr_register(env, SPR_40x_TCR, "TCR",
1866 SPR_NOACCESS, SPR_NOACCESS,
1867 &spr_read_generic, &spr_write_booke_tcr,
1868 0x00000000);
1869 spr_register(env, SPR_40x_TSR, "TSR",
1870 SPR_NOACCESS, SPR_NOACCESS,
1871 &spr_read_generic, &spr_write_booke_tsr,
1872 0x00000000);
1873 }
1874
1875 /* SPR specific to PowerPC 405 implementation */
1876 static void gen_spr_405 (CPUPPCState *env)
1877 {
1878 /* MMU */
1879 spr_register(env, SPR_40x_PID, "PID",
1880 SPR_NOACCESS, SPR_NOACCESS,
1881 &spr_read_generic, &spr_write_generic,
1882 0x00000000);
1883 spr_register(env, SPR_4xx_CCR0, "CCR0",
1884 SPR_NOACCESS, SPR_NOACCESS,
1885 &spr_read_generic, &spr_write_generic,
1886 0x00700000);
1887 /* Debug interface */
1888 /* XXX : not implemented */
1889 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1890 SPR_NOACCESS, SPR_NOACCESS,
1891 &spr_read_generic, &spr_write_40x_dbcr0,
1892 0x00000000);
1893 /* XXX : not implemented */
1894 spr_register(env, SPR_405_DBCR1, "DBCR1",
1895 SPR_NOACCESS, SPR_NOACCESS,
1896 &spr_read_generic, &spr_write_generic,
1897 0x00000000);
1898 /* XXX : not implemented */
1899 spr_register(env, SPR_40x_DBSR, "DBSR",
1900 SPR_NOACCESS, SPR_NOACCESS,
1901 &spr_read_generic, &spr_write_clear,
1902 /* Last reset was system reset */
1903 0x00000300);
1904 /* XXX : not implemented */
1905 spr_register(env, SPR_40x_DAC1, "DAC1",
1906 SPR_NOACCESS, SPR_NOACCESS,
1907 &spr_read_generic, &spr_write_generic,
1908 0x00000000);
1909 spr_register(env, SPR_40x_DAC2, "DAC2",
1910 SPR_NOACCESS, SPR_NOACCESS,
1911 &spr_read_generic, &spr_write_generic,
1912 0x00000000);
1913 /* XXX : not implemented */
1914 spr_register(env, SPR_405_DVC1, "DVC1",
1915 SPR_NOACCESS, SPR_NOACCESS,
1916 &spr_read_generic, &spr_write_generic,
1917 0x00000000);
1918 /* XXX : not implemented */
1919 spr_register(env, SPR_405_DVC2, "DVC2",
1920 SPR_NOACCESS, SPR_NOACCESS,
1921 &spr_read_generic, &spr_write_generic,
1922 0x00000000);
1923 /* XXX : not implemented */
1924 spr_register(env, SPR_40x_IAC1, "IAC1",
1925 SPR_NOACCESS, SPR_NOACCESS,
1926 &spr_read_generic, &spr_write_generic,
1927 0x00000000);
1928 spr_register(env, SPR_40x_IAC2, "IAC2",
1929 SPR_NOACCESS, SPR_NOACCESS,
1930 &spr_read_generic, &spr_write_generic,
1931 0x00000000);
1932 /* XXX : not implemented */
1933 spr_register(env, SPR_405_IAC3, "IAC3",
1934 SPR_NOACCESS, SPR_NOACCESS,
1935 &spr_read_generic, &spr_write_generic,
1936 0x00000000);
1937 /* XXX : not implemented */
1938 spr_register(env, SPR_405_IAC4, "IAC4",
1939 SPR_NOACCESS, SPR_NOACCESS,
1940 &spr_read_generic, &spr_write_generic,
1941 0x00000000);
1942 /* Storage control */
1943 /* XXX: TODO: not implemented */
1944 spr_register(env, SPR_405_SLER, "SLER",
1945 SPR_NOACCESS, SPR_NOACCESS,
1946 &spr_read_generic, &spr_write_40x_sler,
1947 0x00000000);
1948 spr_register(env, SPR_40x_ZPR, "ZPR",
1949 SPR_NOACCESS, SPR_NOACCESS,
1950 &spr_read_generic, &spr_write_generic,
1951 0x00000000);
1952 /* XXX : not implemented */
1953 spr_register(env, SPR_405_SU0R, "SU0R",
1954 SPR_NOACCESS, SPR_NOACCESS,
1955 &spr_read_generic, &spr_write_generic,
1956 0x00000000);
1957 /* SPRG */
1958 spr_register(env, SPR_USPRG0, "USPRG0",
1959 &spr_read_ureg, SPR_NOACCESS,
1960 &spr_read_ureg, SPR_NOACCESS,
1961 0x00000000);
1962 spr_register(env, SPR_SPRG4, "SPRG4",
1963 SPR_NOACCESS, SPR_NOACCESS,
1964 &spr_read_generic, &spr_write_generic,
1965 0x00000000);
1966 spr_register(env, SPR_SPRG5, "SPRG5",
1967 SPR_NOACCESS, SPR_NOACCESS,
1968 spr_read_generic, &spr_write_generic,
1969 0x00000000);
1970 spr_register(env, SPR_SPRG6, "SPRG6",
1971 SPR_NOACCESS, SPR_NOACCESS,
1972 spr_read_generic, &spr_write_generic,
1973 0x00000000);
1974 spr_register(env, SPR_SPRG7, "SPRG7",
1975 SPR_NOACCESS, SPR_NOACCESS,
1976 spr_read_generic, &spr_write_generic,
1977 0x00000000);
1978 gen_spr_usprgh(env);
1979 }
1980
1981 /* SPR shared between PowerPC 401 & 403 implementations */
1982 static void gen_spr_401_403 (CPUPPCState *env)
1983 {
1984 /* Time base */
1985 spr_register(env, SPR_403_VTBL, "TBL",
1986 &spr_read_tbl, SPR_NOACCESS,
1987 &spr_read_tbl, SPR_NOACCESS,
1988 0x00000000);
1989 spr_register(env, SPR_403_TBL, "TBL",
1990 SPR_NOACCESS, SPR_NOACCESS,
1991 SPR_NOACCESS, &spr_write_tbl,
1992 0x00000000);
1993 spr_register(env, SPR_403_VTBU, "TBU",
1994 &spr_read_tbu, SPR_NOACCESS,
1995 &spr_read_tbu, SPR_NOACCESS,
1996 0x00000000);
1997 spr_register(env, SPR_403_TBU, "TBU",
1998 SPR_NOACCESS, SPR_NOACCESS,
1999 SPR_NOACCESS, &spr_write_tbu,
2000 0x00000000);
2001 /* Debug */
2002 /* not emulated, as QEMU do not emulate caches */
2003 spr_register(env, SPR_403_CDBCR, "CDBCR",
2004 SPR_NOACCESS, SPR_NOACCESS,
2005 &spr_read_generic, &spr_write_generic,
2006 0x00000000);
2007 }
2008
2009 /* SPR specific to PowerPC 401 implementation */
2010 static void gen_spr_401 (CPUPPCState *env)
2011 {
2012 /* Debug interface */
2013 /* XXX : not implemented */
2014 spr_register(env, SPR_40x_DBCR0, "DBCR",
2015 SPR_NOACCESS, SPR_NOACCESS,
2016 &spr_read_generic, &spr_write_40x_dbcr0,
2017 0x00000000);
2018 /* XXX : not implemented */
2019 spr_register(env, SPR_40x_DBSR, "DBSR",
2020 SPR_NOACCESS, SPR_NOACCESS,
2021 &spr_read_generic, &spr_write_clear,
2022 /* Last reset was system reset */
2023 0x00000300);
2024 /* XXX : not implemented */
2025 spr_register(env, SPR_40x_DAC1, "DAC",
2026 SPR_NOACCESS, SPR_NOACCESS,
2027 &spr_read_generic, &spr_write_generic,
2028 0x00000000);
2029 /* XXX : not implemented */
2030 spr_register(env, SPR_40x_IAC1, "IAC",
2031 SPR_NOACCESS, SPR_NOACCESS,
2032 &spr_read_generic, &spr_write_generic,
2033 0x00000000);
2034 /* Storage control */
2035 /* XXX: TODO: not implemented */
2036 spr_register(env, SPR_405_SLER, "SLER",
2037 SPR_NOACCESS, SPR_NOACCESS,
2038 &spr_read_generic, &spr_write_40x_sler,
2039 0x00000000);
2040 /* not emulated, as QEMU never does speculative access */
2041 spr_register(env, SPR_40x_SGR, "SGR",
2042 SPR_NOACCESS, SPR_NOACCESS,
2043 &spr_read_generic, &spr_write_generic,
2044 0xFFFFFFFF);
2045 /* not emulated, as QEMU do not emulate caches */
2046 spr_register(env, SPR_40x_DCWR, "DCWR",
2047 SPR_NOACCESS, SPR_NOACCESS,
2048 &spr_read_generic, &spr_write_generic,
2049 0x00000000);
2050 }
2051
2052 static void gen_spr_401x2 (CPUPPCState *env)
2053 {
2054 gen_spr_401(env);
2055 spr_register(env, SPR_40x_PID, "PID",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_generic, &spr_write_generic,
2058 0x00000000);
2059 spr_register(env, SPR_40x_ZPR, "ZPR",
2060 SPR_NOACCESS, SPR_NOACCESS,
2061 &spr_read_generic, &spr_write_generic,
2062 0x00000000);
2063 }
2064
2065 /* SPR specific to PowerPC 403 implementation */
2066 static void gen_spr_403 (CPUPPCState *env)
2067 {
2068 /* Debug interface */
2069 /* XXX : not implemented */
2070 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2071 SPR_NOACCESS, SPR_NOACCESS,
2072 &spr_read_generic, &spr_write_40x_dbcr0,
2073 0x00000000);
2074 /* XXX : not implemented */
2075 spr_register(env, SPR_40x_DBSR, "DBSR",
2076 SPR_NOACCESS, SPR_NOACCESS,
2077 &spr_read_generic, &spr_write_clear,
2078 /* Last reset was system reset */
2079 0x00000300);
2080 /* XXX : not implemented */
2081 spr_register(env, SPR_40x_DAC1, "DAC1",
2082 SPR_NOACCESS, SPR_NOACCESS,
2083 &spr_read_generic, &spr_write_generic,
2084 0x00000000);
2085 /* XXX : not implemented */
2086 spr_register(env, SPR_40x_DAC2, "DAC2",
2087 SPR_NOACCESS, SPR_NOACCESS,
2088 &spr_read_generic, &spr_write_generic,
2089 0x00000000);
2090 /* XXX : not implemented */
2091 spr_register(env, SPR_40x_IAC1, "IAC1",
2092 SPR_NOACCESS, SPR_NOACCESS,
2093 &spr_read_generic, &spr_write_generic,
2094 0x00000000);
2095 /* XXX : not implemented */
2096 spr_register(env, SPR_40x_IAC2, "IAC2",
2097 SPR_NOACCESS, SPR_NOACCESS,
2098 &spr_read_generic, &spr_write_generic,
2099 0x00000000);
2100 }
2101
2102 static void gen_spr_403_real (CPUPPCState *env)
2103 {
2104 spr_register(env, SPR_403_PBL1, "PBL1",
2105 SPR_NOACCESS, SPR_NOACCESS,
2106 &spr_read_403_pbr, &spr_write_403_pbr,
2107 0x00000000);
2108 spr_register(env, SPR_403_PBU1, "PBU1",
2109 SPR_NOACCESS, SPR_NOACCESS,
2110 &spr_read_403_pbr, &spr_write_403_pbr,
2111 0x00000000);
2112 spr_register(env, SPR_403_PBL2, "PBL2",
2113 SPR_NOACCESS, SPR_NOACCESS,
2114 &spr_read_403_pbr, &spr_write_403_pbr,
2115 0x00000000);
2116 spr_register(env, SPR_403_PBU2, "PBU2",
2117 SPR_NOACCESS, SPR_NOACCESS,
2118 &spr_read_403_pbr, &spr_write_403_pbr,
2119 0x00000000);
2120 }
2121
2122 static void gen_spr_403_mmu (CPUPPCState *env)
2123 {
2124 /* MMU */
2125 spr_register(env, SPR_40x_PID, "PID",
2126 SPR_NOACCESS, SPR_NOACCESS,
2127 &spr_read_generic, &spr_write_generic,
2128 0x00000000);
2129 spr_register(env, SPR_40x_ZPR, "ZPR",
2130 SPR_NOACCESS, SPR_NOACCESS,
2131 &spr_read_generic, &spr_write_generic,
2132 0x00000000);
2133 }
2134
2135 /* SPR specific to PowerPC compression coprocessor extension */
2136 static void gen_spr_compress (CPUPPCState *env)
2137 {
2138 /* XXX : not implemented */
2139 spr_register(env, SPR_401_SKR, "SKR",
2140 SPR_NOACCESS, SPR_NOACCESS,
2141 &spr_read_generic, &spr_write_generic,
2142 0x00000000);
2143 }
2144
2145 #if defined (TARGET_PPC64)
2146 /* SPR specific to PowerPC 620 */
2147 static void gen_spr_620 (CPUPPCState *env)
2148 {
2149 /* Processor identification */
2150 spr_register(env, SPR_PIR, "PIR",
2151 SPR_NOACCESS, SPR_NOACCESS,
2152 &spr_read_generic, &spr_write_pir,
2153 0x00000000);
2154 spr_register(env, SPR_ASR, "ASR",
2155 SPR_NOACCESS, SPR_NOACCESS,
2156 &spr_read_asr, &spr_write_asr,
2157 0x00000000);
2158 /* Breakpoints */
2159 /* XXX : not implemented */
2160 spr_register(env, SPR_IABR, "IABR",
2161 SPR_NOACCESS, SPR_NOACCESS,
2162 &spr_read_generic, &spr_write_generic,
2163 0x00000000);
2164 /* XXX : not implemented */
2165 spr_register(env, SPR_DABR, "DABR",
2166 SPR_NOACCESS, SPR_NOACCESS,
2167 &spr_read_generic, &spr_write_generic,
2168 0x00000000);
2169 /* XXX : not implemented */
2170 spr_register(env, SPR_SIAR, "SIAR",
2171 SPR_NOACCESS, SPR_NOACCESS,
2172 &spr_read_generic, SPR_NOACCESS,
2173 0x00000000);
2174 /* XXX : not implemented */
2175 spr_register(env, SPR_SDA, "SDA",
2176 SPR_NOACCESS, SPR_NOACCESS,
2177 &spr_read_generic, SPR_NOACCESS,
2178 0x00000000);
2179 /* XXX : not implemented */
2180 spr_register(env, SPR_620_PMC1R, "PMC1",
2181 SPR_NOACCESS, SPR_NOACCESS,
2182 &spr_read_generic, SPR_NOACCESS,
2183 0x00000000);
2184 spr_register(env, SPR_620_PMC1W, "PMC1",
2185 SPR_NOACCESS, SPR_NOACCESS,
2186 SPR_NOACCESS, &spr_write_generic,
2187 0x00000000);
2188 /* XXX : not implemented */
2189 spr_register(env, SPR_620_PMC2R, "PMC2",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 &spr_read_generic, SPR_NOACCESS,
2192 0x00000000);
2193 spr_register(env, SPR_620_PMC2W, "PMC2",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 SPR_NOACCESS, &spr_write_generic,
2196 0x00000000);
2197 /* XXX : not implemented */
2198 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2199 SPR_NOACCESS, SPR_NOACCESS,
2200 &spr_read_generic, SPR_NOACCESS,
2201 0x00000000);
2202 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2203 SPR_NOACCESS, SPR_NOACCESS,
2204 SPR_NOACCESS, &spr_write_generic,
2205 0x00000000);
2206 /* External access control */
2207 /* XXX : not implemented */
2208 spr_register(env, SPR_EAR, "EAR",
2209 SPR_NOACCESS, SPR_NOACCESS,
2210 &spr_read_generic, &spr_write_generic,
2211 0x00000000);
2212 #if 0 // XXX: check this
2213 /* XXX : not implemented */
2214 spr_register(env, SPR_620_PMR0, "PMR0",
2215 SPR_NOACCESS, SPR_NOACCESS,
2216 &spr_read_generic, &spr_write_generic,
2217 0x00000000);
2218 /* XXX : not implemented */
2219 spr_register(env, SPR_620_PMR1, "PMR1",
2220 SPR_NOACCESS, SPR_NOACCESS,
2221 &spr_read_generic, &spr_write_generic,
2222 0x00000000);
2223 /* XXX : not implemented */
2224 spr_register(env, SPR_620_PMR2, "PMR2",
2225 SPR_NOACCESS, SPR_NOACCESS,
2226 &spr_read_generic, &spr_write_generic,
2227 0x00000000);
2228 /* XXX : not implemented */
2229 spr_register(env, SPR_620_PMR3, "PMR3",
2230 SPR_NOACCESS, SPR_NOACCESS,
2231 &spr_read_generic, &spr_write_generic,
2232 0x00000000);
2233 /* XXX : not implemented */
2234 spr_register(env, SPR_620_PMR4, "PMR4",
2235 SPR_NOACCESS, SPR_NOACCESS,
2236 &spr_read_generic, &spr_write_generic,
2237 0x00000000);
2238 /* XXX : not implemented */
2239 spr_register(env, SPR_620_PMR5, "PMR5",
2240 SPR_NOACCESS, SPR_NOACCESS,
2241 &spr_read_generic, &spr_write_generic,
2242 0x00000000);
2243 /* XXX : not implemented */
2244 spr_register(env, SPR_620_PMR6, "PMR6",
2245 SPR_NOACCESS, SPR_NOACCESS,
2246 &spr_read_generic, &spr_write_generic,
2247 0x00000000);
2248 /* XXX : not implemented */
2249 spr_register(env, SPR_620_PMR7, "PMR7",
2250 SPR_NOACCESS, SPR_NOACCESS,
2251 &spr_read_generic, &spr_write_generic,
2252 0x00000000);
2253 /* XXX : not implemented */
2254 spr_register(env, SPR_620_PMR8, "PMR8",
2255 SPR_NOACCESS, SPR_NOACCESS,
2256 &spr_read_generic, &spr_write_generic,
2257 0x00000000);
2258 /* XXX : not implemented */
2259 spr_register(env, SPR_620_PMR9, "PMR9",
2260 SPR_NOACCESS, SPR_NOACCESS,
2261 &spr_read_generic, &spr_write_generic,
2262 0x00000000);
2263 /* XXX : not implemented */
2264 spr_register(env, SPR_620_PMRA, "PMR10",
2265 SPR_NOACCESS, SPR_NOACCESS,
2266 &spr_read_generic, &spr_write_generic,
2267 0x00000000);
2268 /* XXX : not implemented */
2269 spr_register(env, SPR_620_PMRB, "PMR11",
2270 SPR_NOACCESS, SPR_NOACCESS,
2271 &spr_read_generic, &spr_write_generic,
2272 0x00000000);
2273 /* XXX : not implemented */
2274 spr_register(env, SPR_620_PMRC, "PMR12",
2275 SPR_NOACCESS, SPR_NOACCESS,
2276 &spr_read_generic, &spr_write_generic,
2277 0x00000000);
2278 /* XXX : not implemented */
2279 spr_register(env, SPR_620_PMRD, "PMR13",
2280 SPR_NOACCESS, SPR_NOACCESS,
2281 &spr_read_generic, &spr_write_generic,
2282 0x00000000);
2283 /* XXX : not implemented */
2284 spr_register(env, SPR_620_PMRE, "PMR14",
2285 SPR_NOACCESS, SPR_NOACCESS,
2286 &spr_read_generic, &spr_write_generic,
2287 0x00000000);
2288 /* XXX : not implemented */
2289 spr_register(env, SPR_620_PMRF, "PMR15",
2290 SPR_NOACCESS, SPR_NOACCESS,
2291 &spr_read_generic, &spr_write_generic,
2292 0x00000000);
2293 #endif
2294 /* XXX : not implemented */
2295 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2296 SPR_NOACCESS, SPR_NOACCESS,
2297 &spr_read_generic, &spr_write_generic,
2298 0x00000000);
2299 /* XXX : not implemented */
2300 spr_register(env, SPR_620_L2CR, "L2CR",
2301 SPR_NOACCESS, SPR_NOACCESS,
2302 &spr_read_generic, &spr_write_generic,
2303 0x00000000);
2304 /* XXX : not implemented */
2305 spr_register(env, SPR_620_L2SR, "L2SR",
2306 SPR_NOACCESS, SPR_NOACCESS,
2307 &spr_read_generic, &spr_write_generic,
2308 0x00000000);
2309 }
2310 #endif /* defined (TARGET_PPC64) */
2311
2312 static void gen_spr_5xx_8xx (CPUPPCState *env)
2313 {
2314 /* Exception processing */
2315 spr_register(env, SPR_DSISR, "DSISR",
2316 SPR_NOACCESS, SPR_NOACCESS,
2317 &spr_read_generic, &spr_write_generic,
2318 0x00000000);
2319 spr_register(env, SPR_DAR, "DAR",
2320 SPR_NOACCESS, SPR_NOACCESS,
2321 &spr_read_generic, &spr_write_generic,
2322 0x00000000);
2323 /* Timer */
2324 spr_register(env, SPR_DECR, "DECR",
2325 SPR_NOACCESS, SPR_NOACCESS,
2326 &spr_read_decr, &spr_write_decr,
2327 0x00000000);
2328 /* XXX : not implemented */
2329 spr_register(env, SPR_MPC_EIE, "EIE",
2330 SPR_NOACCESS, SPR_NOACCESS,
2331 &spr_read_generic, &spr_write_generic,
2332 0x00000000);
2333 /* XXX : not implemented */
2334 spr_register(env, SPR_MPC_EID, "EID",
2335 SPR_NOACCESS, SPR_NOACCESS,
2336 &spr_read_generic, &spr_write_generic,
2337 0x00000000);
2338 /* XXX : not implemented */
2339 spr_register(env, SPR_MPC_NRI, "NRI",
2340 SPR_NOACCESS, SPR_NOACCESS,
2341 &spr_read_generic, &spr_write_generic,
2342 0x00000000);
2343 /* XXX : not implemented */
2344 spr_register(env, SPR_MPC_CMPA, "CMPA",
2345 SPR_NOACCESS, SPR_NOACCESS,
2346 &spr_read_generic, &spr_write_generic,
2347 0x00000000);
2348 /* XXX : not implemented */
2349 spr_register(env, SPR_MPC_CMPB, "CMPB",
2350 SPR_NOACCESS, SPR_NOACCESS,
2351 &spr_read_generic, &spr_write_generic,
2352 0x00000000);
2353 /* XXX : not implemented */
2354 spr_register(env, SPR_MPC_CMPC, "CMPC",
2355 SPR_NOACCESS, SPR_NOACCESS,
2356 &spr_read_generic, &spr_write_generic,
2357 0x00000000);
2358 /* XXX : not implemented */
2359 spr_register(env, SPR_MPC_CMPD, "CMPD",
2360 SPR_NOACCESS, SPR_NOACCESS,
2361 &spr_read_generic, &spr_write_generic,
2362 0x00000000);
2363 /* XXX : not implemented */
2364 spr_register(env, SPR_MPC_ECR, "ECR",
2365 SPR_NOACCESS, SPR_NOACCESS,
2366 &spr_read_generic, &spr_write_generic,
2367 0x00000000);
2368 /* XXX : not implemented */
2369 spr_register(env, SPR_MPC_DER, "DER",
2370 SPR_NOACCESS, SPR_NOACCESS,
2371 &spr_read_generic, &spr_write_generic,
2372 0x00000000);
2373 /* XXX : not implemented */
2374 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2375 SPR_NOACCESS, SPR_NOACCESS,
2376 &spr_read_generic, &spr_write_generic,
2377 0x00000000);
2378 /* XXX : not implemented */
2379 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2380 SPR_NOACCESS, SPR_NOACCESS,
2381 &spr_read_generic, &spr_write_generic,
2382 0x00000000);
2383 /* XXX : not implemented */
2384 spr_register(env, SPR_MPC_CMPE, "CMPE",
2385 SPR_NOACCESS, SPR_NOACCESS,
2386 &spr_read_generic, &spr_write_generic,
2387 0x00000000);
2388 /* XXX : not implemented */
2389 spr_register(env, SPR_MPC_CMPF, "CMPF",
2390 SPR_NOACCESS, SPR_NOACCESS,
2391 &spr_read_generic, &spr_write_generic,
2392 0x00000000);
2393 /* XXX : not implemented */
2394 spr_register(env, SPR_MPC_CMPG, "CMPG",
2395 SPR_NOACCESS, SPR_NOACCESS,
2396 &spr_read_generic, &spr_write_generic,
2397 0x00000000);
2398 /* XXX : not implemented */
2399 spr_register(env, SPR_MPC_CMPH, "CMPH",
2400 SPR_NOACCESS, SPR_NOACCESS,
2401 &spr_read_generic, &spr_write_generic,
2402 0x00000000);
2403 /* XXX : not implemented */
2404 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2405 SPR_NOACCESS, SPR_NOACCESS,
2406 &spr_read_generic, &spr_write_generic,
2407 0x00000000);
2408 /* XXX : not implemented */
2409 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2410 SPR_NOACCESS, SPR_NOACCESS,
2411 &spr_read_generic, &spr_write_generic,
2412 0x00000000);
2413 /* XXX : not implemented */
2414 spr_register(env, SPR_MPC_BAR, "BAR",
2415 SPR_NOACCESS, SPR_NOACCESS,
2416 &spr_read_generic, &spr_write_generic,
2417 0x00000000);
2418 /* XXX : not implemented */
2419 spr_register(env, SPR_MPC_DPDR, "DPDR",
2420 SPR_NOACCESS, SPR_NOACCESS,
2421 &spr_read_generic, &spr_write_generic,
2422 0x00000000);
2423 /* XXX : not implemented */
2424 spr_register(env, SPR_MPC_IMMR, "IMMR",
2425 SPR_NOACCESS, SPR_NOACCESS,
2426 &spr_read_generic, &spr_write_generic,
2427 0x00000000);
2428 }
2429
2430 static void gen_spr_5xx (CPUPPCState *env)
2431 {
2432 /* XXX : not implemented */
2433 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2434 SPR_NOACCESS, SPR_NOACCESS,
2435 &spr_read_generic, &spr_write_generic,
2436 0x00000000);
2437 /* XXX : not implemented */
2438 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2439 SPR_NOACCESS, SPR_NOACCESS,
2440 &spr_read_generic, &spr_write_generic,
2441 0x00000000);
2442 /* XXX : not implemented */
2443 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2444 SPR_NOACCESS, SPR_NOACCESS,
2445 &spr_read_generic, &spr_write_generic,
2446 0x00000000);
2447 /* XXX : not implemented */
2448 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2449 SPR_NOACCESS, SPR_NOACCESS,
2450 &spr_read_generic, &spr_write_generic,
2451 0x00000000);
2452 /* XXX : not implemented */
2453 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2454 SPR_NOACCESS, SPR_NOACCESS,
2455 &spr_read_generic, &spr_write_generic,
2456 0x00000000);
2457 /* XXX : not implemented */
2458 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2459 SPR_NOACCESS, SPR_NOACCESS,
2460 &spr_read_generic, &spr_write_generic,
2461 0x00000000);
2462 /* XXX : not implemented */
2463 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2464 SPR_NOACCESS, SPR_NOACCESS,
2465 &spr_read_generic, &spr_write_generic,
2466 0x00000000);
2467 /* XXX : not implemented */
2468 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2469 SPR_NOACCESS, SPR_NOACCESS,
2470 &spr_read_generic, &spr_write_generic,
2471 0x00000000);
2472 /* XXX : not implemented */
2473 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2474 SPR_NOACCESS, SPR_NOACCESS,
2475 &spr_read_generic, &spr_write_generic,
2476 0x00000000);
2477 /* XXX : not implemented */
2478 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2479 SPR_NOACCESS, SPR_NOACCESS,
2480 &spr_read_generic, &spr_write_generic,
2481 0x00000000);
2482 /* XXX : not implemented */
2483 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2484 SPR_NOACCESS, SPR_NOACCESS,
2485 &spr_read_generic, &spr_write_generic,
2486 0x00000000);
2487 /* XXX : not implemented */
2488 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2489 SPR_NOACCESS, SPR_NOACCESS,
2490 &spr_read_generic, &spr_write_generic,
2491 0x00000000);
2492 /* XXX : not implemented */
2493 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2494 SPR_NOACCESS, SPR_NOACCESS,
2495 &spr_read_generic, &spr_write_generic,
2496 0x00000000);
2497 /* XXX : not implemented */
2498 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2499 SPR_NOACCESS, SPR_NOACCESS,
2500 &spr_read_generic, &spr_write_generic,
2501 0x00000000);
2502 /* XXX : not implemented */
2503 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2504 SPR_NOACCESS, SPR_NOACCESS,
2505 &spr_read_generic, &spr_write_generic,
2506 0x00000000);
2507 /* XXX : not implemented */
2508 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2509 SPR_NOACCESS, SPR_NOACCESS,
2510 &spr_read_generic, &spr_write_generic,
2511 0x00000000);
2512 /* XXX : not implemented */
2513 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2514 SPR_NOACCESS, SPR_NOACCESS,
2515 &spr_read_generic, &spr_write_generic,
2516 0x00000000);
2517 /* XXX : not implemented */
2518 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2519 SPR_NOACCESS, SPR_NOACCESS,
2520 &spr_read_generic, &spr_write_generic,
2521 0x00000000);
2522 /* XXX : not implemented */
2523 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2524 SPR_NOACCESS, SPR_NOACCESS,
2525 &spr_read_generic, &spr_write_generic,
2526 0x00000000);
2527 /* XXX : not implemented */
2528 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2529 SPR_NOACCESS, SPR_NOACCESS,
2530 &spr_read_generic, &spr_write_generic,
2531 0x00000000);
2532 /* XXX : not implemented */
2533 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2534 SPR_NOACCESS, SPR_NOACCESS,
2535 &spr_read_generic, &spr_write_generic,
2536 0x00000000);
2537 }
2538
2539 static void gen_spr_8xx (CPUPPCState *env)
2540 {
2541 /* XXX : not implemented */
2542 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2543 SPR_NOACCESS, SPR_NOACCESS,
2544 &spr_read_generic, &spr_write_generic,
2545 0x00000000);
2546 /* XXX : not implemented */
2547 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2548 SPR_NOACCESS, SPR_NOACCESS,
2549 &spr_read_generic, &spr_write_generic,
2550 0x00000000);
2551 /* XXX : not implemented */
2552 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2553 SPR_NOACCESS, SPR_NOACCESS,
2554 &spr_read_generic, &spr_write_generic,
2555 0x00000000);
2556 /* XXX : not implemented */
2557 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2558 SPR_NOACCESS, SPR_NOACCESS,
2559 &spr_read_generic, &spr_write_generic,
2560 0x00000000);
2561 /* XXX : not implemented */
2562 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2563 SPR_NOACCESS, SPR_NOACCESS,
2564 &spr_read_generic, &spr_write_generic,
2565 0x00000000);
2566 /* XXX : not implemented */
2567 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2568 SPR_NOACCESS, SPR_NOACCESS,
2569 &spr_read_generic, &spr_write_generic,
2570 0x00000000);
2571 /* XXX : not implemented */
2572 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2573 SPR_NOACCESS, SPR_NOACCESS,
2574 &spr_read_generic, &spr_write_generic,
2575 0x00000000);
2576 /* XXX : not implemented */
2577 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2578 SPR_NOACCESS, SPR_NOACCESS,
2579 &spr_read_generic, &spr_write_generic,
2580 0x00000000);
2581 /* XXX : not implemented */
2582 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2583 SPR_NOACCESS, SPR_NOACCESS,
2584 &spr_read_generic, &spr_write_generic,
2585 0x00000000);
2586 /* XXX : not implemented */
2587 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2588 SPR_NOACCESS, SPR_NOACCESS,
2589 &spr_read_generic, &spr_write_generic,
2590 0x00000000);
2591 /* XXX : not implemented */
2592 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2593 SPR_NOACCESS, SPR_NOACCESS,
2594 &spr_read_generic, &spr_write_generic,
2595 0x00000000);
2596 /* XXX : not implemented */
2597 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2598 SPR_NOACCESS, SPR_NOACCESS,
2599 &spr_read_generic, &spr_write_generic,
2600 0x00000000);
2601 /* XXX : not implemented */
2602 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2603 SPR_NOACCESS, SPR_NOACCESS,
2604 &spr_read_generic, &spr_write_generic,
2605 0x00000000);
2606 /* XXX : not implemented */
2607 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2608 SPR_NOACCESS, SPR_NOACCESS,
2609 &spr_read_generic, &spr_write_generic,
2610 0x00000000);
2611 /* XXX : not implemented */
2612 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2613 SPR_NOACCESS, SPR_NOACCESS,
2614 &spr_read_generic, &spr_write_generic,
2615 0x00000000);
2616 /* XXX : not implemented */
2617 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2618 SPR_NOACCESS, SPR_NOACCESS,
2619 &spr_read_generic, &spr_write_generic,
2620 0x00000000);
2621 /* XXX : not implemented */
2622 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2623 SPR_NOACCESS, SPR_NOACCESS,
2624 &spr_read_generic, &spr_write_generic,
2625 0x00000000);
2626 /* XXX : not implemented */
2627 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2628 SPR_NOACCESS, SPR_NOACCESS,
2629 &spr_read_generic, &spr_write_generic,
2630 0x00000000);
2631 /* XXX : not implemented */
2632 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2633 SPR_NOACCESS, SPR_NOACCESS,
2634 &spr_read_generic, &spr_write_generic,
2635 0x00000000);
2636 /* XXX : not implemented */
2637 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2638 SPR_NOACCESS, SPR_NOACCESS,
2639 &spr_read_generic, &spr_write_generic,
2640 0x00000000);
2641 /* XXX : not implemented */
2642 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2643 SPR_NOACCESS, SPR_NOACCESS,
2644 &spr_read_generic, &spr_write_generic,
2645 0x00000000);
2646 /* XXX : not implemented */
2647 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2648 SPR_NOACCESS, SPR_NOACCESS,
2649 &spr_read_generic, &spr_write_generic,
2650 0x00000000);
2651 /* XXX : not implemented */
2652 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2653 SPR_NOACCESS, SPR_NOACCESS,
2654 &spr_read_generic, &spr_write_generic,
2655 0x00000000);
2656 /* XXX : not implemented */
2657 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2658 SPR_NOACCESS, SPR_NOACCESS,
2659 &spr_read_generic, &spr_write_generic,
2660 0x00000000);
2661 /* XXX : not implemented */
2662 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2663 SPR_NOACCESS, SPR_NOACCESS,
2664 &spr_read_generic, &spr_write_generic,
2665 0x00000000);
2666 }
2667
2668 // XXX: TODO
2669 /*
2670 * AMR => SPR 29 (Power 2.04)
2671 * CTRL => SPR 136 (Power 2.04)
2672 * CTRL => SPR 152 (Power 2.04)
2673 * SCOMC => SPR 276 (64 bits ?)
2674 * SCOMD => SPR 277 (64 bits ?)
2675 * TBU40 => SPR 286 (Power 2.04 hypv)
2676 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2677 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2678 * HDSISR => SPR 306 (Power 2.04 hypv)
2679 * HDAR => SPR 307 (Power 2.04 hypv)
2680 * PURR => SPR 309 (Power 2.04 hypv)
2681 * HDEC => SPR 310 (Power 2.04 hypv)
2682 * HIOR => SPR 311 (hypv)
2683 * RMOR => SPR 312 (970)
2684 * HRMOR => SPR 313 (Power 2.04 hypv)
2685 * HSRR0 => SPR 314 (Power 2.04 hypv)
2686 * HSRR1 => SPR 315 (Power 2.04 hypv)
2687 * LPCR => SPR 316 (970)
2688 * LPIDR => SPR 317 (970)
2689 * EPR => SPR 702 (Power 2.04 emb)
2690 * perf => 768-783 (Power 2.04)
2691 * perf => 784-799 (Power 2.04)
2692 * PPR => SPR 896 (Power 2.04)
2693 * EPLC => SPR 947 (Power 2.04 emb)
2694 * EPSC => SPR 948 (Power 2.04 emb)
2695 * DABRX => 1015 (Power 2.04 hypv)
2696 * FPECR => SPR 1022 (?)
2697 * ... and more (thermal management, performance counters, ...)
2698 */
2699
2700 /*****************************************************************************/
2701 /* Exception vectors models */
2702 static void init_excp_4xx_real (CPUPPCState *env)
2703 {
2704 #if !defined(CONFIG_USER_ONLY)
2705 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2706 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2707 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2708 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2709 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2710 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2711 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2712 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2713 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2714 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2715 env->hreset_excp_prefix = 0x00000000UL;
2716 env->ivor_mask = 0x0000FFF0UL;
2717 env->ivpr_mask = 0xFFFF0000UL;
2718 /* Hardware reset vector */
2719 env->hreset_vector = 0xFFFFFFFCUL;
2720 #endif
2721 }
2722
2723 static void init_excp_4xx_softmmu (CPUPPCState *env)
2724 {
2725 #if !defined(CONFIG_USER_ONLY)
2726 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2727 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2728 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2729 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2730 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2731 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2732 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2733 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2734 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2735 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2736 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2737 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2738 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2739 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2740 env->hreset_excp_prefix = 0x00000000UL;
2741 env->ivor_mask = 0x0000FFF0UL;
2742 env->ivpr_mask = 0xFFFF0000UL;
2743 /* Hardware reset vector */
2744 env->hreset_vector = 0xFFFFFFFCUL;
2745 #endif
2746 }
2747
2748 static void init_excp_MPC5xx (CPUPPCState *env)
2749 {
2750 #if !defined(CONFIG_USER_ONLY)
2751 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2752 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2753 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2754 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2755 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2756 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2757 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2758 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2759 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2760 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2761 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2762 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2763 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2764 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2765 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2766 env->hreset_excp_prefix = 0x00000000UL;
2767 env->ivor_mask = 0x0000FFF0UL;
2768 env->ivpr_mask = 0xFFFF0000UL;
2769 /* Hardware reset vector */
2770 env->hreset_vector = 0xFFFFFFFCUL;
2771 #endif
2772 }
2773
2774 static void init_excp_MPC8xx (CPUPPCState *env)
2775 {
2776 #if !defined(CONFIG_USER_ONLY)
2777 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2778 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2779 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2780 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2781 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2782 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2783 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2784 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2785 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2786 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2787 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2788 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2789 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2790 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2791 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2792 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2793 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2794 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2795 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2796 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2797 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2798 env->hreset_excp_prefix = 0x00000000UL;
2799 env->ivor_mask = 0x0000FFF0UL;
2800 env->ivpr_mask = 0xFFFF0000UL;
2801 /* Hardware reset vector */
2802 env->hreset_vector = 0xFFFFFFFCUL;
2803 #endif
2804 }
2805
2806 static void init_excp_G2 (CPUPPCState *env)
2807 {
2808 #if !defined(CONFIG_USER_ONLY)
2809 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2810 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2811 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2812 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2813 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2814 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2815 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2816 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2817 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2818 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2819 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2820 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2821 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2822 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2823 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2824 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2825 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2826 env->hreset_excp_prefix = 0x00000000UL;
2827 /* Hardware reset vector */
2828 env->hreset_vector = 0xFFFFFFFCUL;
2829 #endif
2830 }
2831
2832 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2833 {
2834 #if !defined(CONFIG_USER_ONLY)
2835 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2836 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2837 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2838 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2839 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2840 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2841 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2842 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2843 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2844 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2845 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2846 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2847 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2848 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2849 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2850 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2851 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2852 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2853 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2854 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2855 env->hreset_excp_prefix = 0x00000000UL;
2856 env->ivor_mask = 0x0000FFF7UL;
2857 env->ivpr_mask = ivpr_mask;
2858 /* Hardware reset vector */
2859 env->hreset_vector = 0xFFFFFFFCUL;
2860 #endif
2861 }
2862
2863 static void init_excp_BookE (CPUPPCState *env)
2864 {
2865 #if !defined(CONFIG_USER_ONLY)
2866 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2867 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2868 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2869 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2870 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2871 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2872 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2873 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2874 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2875 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2876 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2877 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2878 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2879 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2880 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2881 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2882 env->hreset_excp_prefix = 0x00000000UL;
2883 env->ivor_mask = 0x0000FFE0UL;
2884 env->ivpr_mask = 0xFFFF0000UL;
2885 /* Hardware reset vector */
2886 env->hreset_vector = 0xFFFFFFFCUL;
2887 #endif
2888 }
2889
2890 static void init_excp_601 (CPUPPCState *env)
2891 {
2892 #if !defined(CONFIG_USER_ONLY)
2893 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2894 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2895 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2896 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2897 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2898 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2899 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2900 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2901 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2902 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2903 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2904 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2905 env->hreset_excp_prefix = 0xFFF00000UL;
2906 /* Hardware reset vector */
2907 env->hreset_vector = 0x00000100UL;
2908 #endif
2909 }
2910
2911 static void init_excp_602 (CPUPPCState *env)
2912 {
2913 #if !defined(CONFIG_USER_ONLY)
2914 /* XXX: exception prefix has a special behavior on 602 */
2915 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2916 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2917 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2918 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2919 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2920 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2921 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2922 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2923 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2924 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2925 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2926 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2927 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2928 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2929 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2930 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2931 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2932 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2933 env->hreset_excp_prefix = 0xFFF00000UL;
2934 /* Hardware reset vector */
2935 env->hreset_vector = 0xFFFFFFFCUL;
2936 #endif
2937 }
2938
2939 static void init_excp_603 (CPUPPCState *env)
2940 {
2941 #if !defined(CONFIG_USER_ONLY)
2942 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2943 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2944 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2945 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2946 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2947 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2948 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2949 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2950 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2951 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2952 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2953 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2954 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2955 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2956 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2957 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2958 env->hreset_excp_prefix = 0x00000000UL;
2959 /* Hardware reset vector */
2960 env->hreset_vector = 0xFFFFFFFCUL;
2961 #endif
2962 }
2963
2964 static void init_excp_604 (CPUPPCState *env)
2965 {
2966 #if !defined(CONFIG_USER_ONLY)
2967 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2968 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2969 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2970 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2971 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2972 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2973 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2974 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2975 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2976 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2977 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2978 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2979 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2980 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2981 env->hreset_excp_prefix = 0xFFF00000UL;
2982 /* Hardware reset vector */
2983 env->hreset_vector = 0x00000100UL;
2984 #endif
2985 }
2986
2987 #if defined(TARGET_PPC64)
2988 static void init_excp_620 (CPUPPCState *env)
2989 {
2990 #if !defined(CONFIG_USER_ONLY)
2991 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2992 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2993 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2994 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2995 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2996 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2997 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2998 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2999 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3000 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3001 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3002 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3003 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3004 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3005 env->hreset_excp_prefix = 0xFFF00000UL;
3006 /* Hardware reset vector */
3007 env->hreset_vector = 0x0000000000000100ULL;
3008 #endif
3009 }
3010 #endif /* defined(TARGET_PPC64) */
3011
3012 static void init_excp_7x0 (CPUPPCState *env)
3013 {
3014 #if !defined(CONFIG_USER_ONLY)
3015 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3016 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3017 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3018 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3019 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3020 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3021 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3022 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3023 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3024 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3025 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3026 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3027 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3028 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3029 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3030 env->hreset_excp_prefix = 0x00000000UL;
3031 /* Hardware reset vector */
3032 env->hreset_vector = 0xFFFFFFFCUL;
3033 #endif
3034 }
3035
3036 static void init_excp_750cl (CPUPPCState *env)
3037 {
3038 #if !defined(CONFIG_USER_ONLY)
3039 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3040 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3041 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3042 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3043 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3044 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3045 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3046 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3047 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3048 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3049 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3050 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3051 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3052 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3053 env->hreset_excp_prefix = 0x00000000UL;
3054 /* Hardware reset vector */
3055 env->hreset_vector = 0xFFFFFFFCUL;
3056 #endif
3057 }
3058
3059 static void init_excp_750cx (CPUPPCState *env)
3060 {
3061 #if !defined(CONFIG_USER_ONLY)
3062 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3063 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3064 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3065 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3066 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3067 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3068 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3069 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3070 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3071 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3072 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3073 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3074 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3075 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3076 env->hreset_excp_prefix = 0x00000000UL;
3077 /* Hardware reset vector */
3078 env->hreset_vector = 0xFFFFFFFCUL;
3079 #endif
3080 }
3081
3082 /* XXX: Check if this is correct */
3083 static void init_excp_7x5 (CPUPPCState *env)
3084 {
3085 #if !defined(CONFIG_USER_ONLY)
3086 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3087 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3088 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3089 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3090 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3091 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3092 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3093 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3094 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3095 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3096 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3097 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3098 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3099 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3100 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3101 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3102 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3103 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3104 env->hreset_excp_prefix = 0x00000000UL;
3105 /* Hardware reset vector */
3106 env->hreset_vector = 0xFFFFFFFCUL;
3107 #endif
3108 }
3109
3110 static void init_excp_7400 (CPUPPCState *env)
3111 {
3112 #if !defined(CONFIG_USER_ONLY)
3113 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3114 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3115 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3116 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3117 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3118 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3119 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3120 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3121 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3122 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3123 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3124 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3125 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3126 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3127 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3128 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3129 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3130 env->hreset_excp_prefix = 0x00000000UL;
3131 /* Hardware reset vector */
3132 env->hreset_vector = 0xFFFFFFFCUL;
3133 #endif
3134 }
3135
3136 static void init_excp_7450 (CPUPPCState *env)
3137 {
3138 #if !defined(CONFIG_USER_ONLY)
3139 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3140 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3141 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3142 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3143 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3144 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3145 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3146 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3147 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3148 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3149 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3150 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3151 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3152 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3153 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3154 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3155 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3156 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3157 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3158 env->hreset_excp_prefix = 0x00000000UL;
3159 /* Hardware reset vector */
3160 env->hreset_vector = 0xFFFFFFFCUL;
3161 #endif
3162 }
3163
3164 #if defined (TARGET_PPC64)
3165 static void init_excp_970 (CPUPPCState *env)
3166 {
3167 #if !defined(CONFIG_USER_ONLY)
3168 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3169 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3170 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3171 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3172 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3173 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3174 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3175 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3176 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3177 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3178 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3179 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3180 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3181 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3182 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3183 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3184 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3185 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3186 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3187 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3188 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
3189 /* Hardware reset vector */
3190 env->hreset_vector = 0x0000000000000100ULL;
3191 #endif
3192 }
3193
3194 static void init_excp_POWER7 (CPUPPCState *env)
3195 {
3196 #if !defined(CONFIG_USER_ONLY)
3197 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3198 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3199 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3200 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3201 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3202 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3203 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3204 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3205 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3206 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3207 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3208 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3209 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3210 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3211 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3212 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3213 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3214 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3215 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3216 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3217 env->hreset_excp_prefix = 0;
3218 /* Hardware reset vector */
3219 env->hreset_vector = 0x0000000000000100ULL;
3220 #endif
3221 }
3222 #endif
3223
3224 /*****************************************************************************/
3225 /* Power management enable checks */
3226 static int check_pow_none (CPUPPCState *env)
3227 {
3228 return 0;
3229 }
3230
3231 static int check_pow_nocheck (CPUPPCState *env)
3232 {
3233 return 1;
3234 }
3235
3236 static int check_pow_hid0 (CPUPPCState *env)
3237 {
3238 if (env->spr[SPR_HID0] & 0x00E00000)
3239 return 1;
3240
3241 return 0;
3242 }
3243
3244 static int check_pow_hid0_74xx (CPUPPCState *env)
3245 {
3246 if (env->spr[SPR_HID0] & 0x00600000)
3247 return 1;
3248
3249 return 0;
3250 }
3251
3252 /*****************************************************************************/
3253 /* PowerPC implementations definitions */
3254
3255 /* PowerPC 401 */
3256 #define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3257 PPC_WRTEE | PPC_DCR | \
3258 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3259 PPC_CACHE_DCBZ | \
3260 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3261 PPC_4xx_COMMON | PPC_40x_EXCP)
3262 #define POWERPC_INSNS2_401 (PPC_NONE)
3263 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
3264 #define POWERPC_MMU_401 (POWERPC_MMU_REAL)
3265 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3266 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
3267 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
3268 #define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3269 POWERPC_FLAG_BUS_CLK)
3270 #define check_pow_401 check_pow_nocheck
3271
3272 static void init_proc_401 (CPUPPCState *env)
3273 {
3274 gen_spr_40x(env);
3275 gen_spr_401_403(env);
3276 gen_spr_401(env);
3277 init_excp_4xx_real(env);
3278 env->dcache_line_size = 32;
3279 env->icache_line_size = 32;
3280 /* Allocate hardware IRQ controller */
3281 ppc40x_irq_init(env);
3282
3283 SET_FIT_PERIOD(12, 16, 20, 24);
3284 SET_WDT_PERIOD(16, 20, 24, 28);
3285 }
3286
3287 /* PowerPC 401x2 */
3288 #define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3289 PPC_DCR | PPC_WRTEE | \
3290 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3291 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3292 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3293 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3294 PPC_4xx_COMMON | PPC_40x_EXCP)
3295 #define POWERPC_INSNS2_401x2 (PPC_NONE)
3296 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3297 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3298 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3299 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
3300 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
3301 #define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3302 POWERPC_FLAG_BUS_CLK)
3303 #define check_pow_401x2 check_pow_nocheck
3304
3305 static void init_proc_401x2 (CPUPPCState *env)
3306 {
3307 gen_spr_40x(env);
3308 gen_spr_401_403(env);
3309 gen_spr_401x2(env);
3310 gen_spr_compress(env);
3311 /* Memory management */
3312 #if !defined(CONFIG_USER_ONLY)
3313 env->nb_tlb = 64;
3314 env->nb_ways = 1;
3315 env->id_tlbs = 0;
3316 env->tlb_type = TLB_EMB;
3317 #endif
3318 init_excp_4xx_softmmu(env);
3319 env->dcache_line_size = 32;
3320 env->icache_line_size = 32;
3321 /* Allocate hardware IRQ controller */
3322 ppc40x_irq_init(env);
3323
3324 SET_FIT_PERIOD(12, 16, 20, 24);
3325 SET_WDT_PERIOD(16, 20, 24, 28);
3326 }
3327
3328 /* PowerPC 401x3 */
3329 #define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3330 PPC_DCR | PPC_WRTEE | \
3331 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3332 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3333 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3334 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3335 PPC_4xx_COMMON | PPC_40x_EXCP)
3336 #define POWERPC_INSNS2_401x3 (PPC_NONE)
3337 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3338 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3339 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3340 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
3341 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
3342 #define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3343 POWERPC_FLAG_BUS_CLK)
3344 #define check_pow_401x3 check_pow_nocheck
3345
3346 __attribute__ (( unused ))
3347 static void init_proc_401x3 (CPUPPCState *env)
3348 {
3349 gen_spr_40x(env);
3350 gen_spr_401_403(env);
3351 gen_spr_401(env);
3352 gen_spr_401x2(env);
3353 gen_spr_compress(env);
3354 init_excp_4xx_softmmu(env);
3355 env->dcache_line_size = 32;
3356 env->icache_line_size = 32;
3357 /* Allocate hardware IRQ controller */
3358 ppc40x_irq_init(env);
3359
3360 SET_FIT_PERIOD(12, 16, 20, 24);
3361 SET_WDT_PERIOD(16, 20, 24, 28);
3362 }
3363
3364 /* IOP480 */
3365 #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3366 PPC_DCR | PPC_WRTEE | \
3367 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3368 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3369 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3370 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3371 PPC_4xx_COMMON | PPC_40x_EXCP)
3372 #define POWERPC_INSNS2_IOP480 (PPC_NONE)
3373 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3374 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3375 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3376 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3377 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
3378 #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3379 POWERPC_FLAG_BUS_CLK)
3380 #define check_pow_IOP480 check_pow_nocheck
3381
3382 static void init_proc_IOP480 (CPUPPCState *env)
3383 {
3384 gen_spr_40x(env);
3385 gen_spr_401_403(env);
3386 gen_spr_401x2(env);
3387 gen_spr_compress(env);
3388 /* Memory management */
3389 #if !defined(CONFIG_USER_ONLY)
3390 env->nb_tlb = 64;
3391 env->nb_ways = 1;
3392 env->id_tlbs = 0;
3393 env->tlb_type = TLB_EMB;
3394 #endif
3395 init_excp_4xx_softmmu(env);
3396 env->dcache_line_size = 32;
3397 env->icache_line_size = 32;
3398 /* Allocate hardware IRQ controller */
3399 ppc40x_irq_init(env);
3400
3401 SET_FIT_PERIOD(8, 12, 16, 20);
3402 SET_WDT_PERIOD(16, 20, 24, 28);
3403 }
3404
3405 /* PowerPC 403 */
3406 #define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3407 PPC_DCR | PPC_WRTEE | \
3408 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3409 PPC_CACHE_DCBZ | \
3410 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3411 PPC_4xx_COMMON | PPC_40x_EXCP)
3412 #define POWERPC_INSNS2_403 (PPC_NONE)
3413 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
3414 #define POWERPC_MMU_403 (POWERPC_MMU_REAL)
3415 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3416 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
3417 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
3418 #define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3419 POWERPC_FLAG_BUS_CLK)
3420 #define check_pow_403 check_pow_nocheck
3421
3422 static void init_proc_403 (CPUPPCState *env)
3423 {
3424 gen_spr_40x(env);
3425 gen_spr_401_403(env);
3426 gen_spr_403(env);
3427 gen_spr_403_real(env);
3428 init_excp_4xx_real(env);
3429 env->dcache_line_size = 32;
3430 env->icache_line_size = 32;
3431 /* Allocate hardware IRQ controller */
3432 ppc40x_irq_init(env);
3433
3434 SET_FIT_PERIOD(8, 12, 16, 20);
3435 SET_WDT_PERIOD(16, 20, 24, 28);
3436 }
3437
3438 /* PowerPC 403 GCX */
3439 #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3440 PPC_DCR | PPC_WRTEE | \
3441 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3442 PPC_CACHE_DCBZ | \
3443 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3444 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3445 PPC_4xx_COMMON | PPC_40x_EXCP)
3446 #define POWERPC_INSNS2_403GCX (PPC_NONE)
3447 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3448 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3449 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3450 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3451 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
3452 #define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3453 POWERPC_FLAG_BUS_CLK)
3454 #define check_pow_403GCX check_pow_nocheck
3455
3456 static void init_proc_403GCX (CPUPPCState *env)
3457 {
3458 gen_spr_40x(env);
3459 gen_spr_401_403(env);
3460 gen_spr_403(env);
3461 gen_spr_403_real(env);
3462 gen_spr_403_mmu(env);
3463 /* Bus access control */
3464 /* not emulated, as QEMU never does speculative access */
3465 spr_register(env, SPR_40x_SGR, "SGR",
3466 SPR_NOACCESS, SPR_NOACCESS,
3467 &spr_read_generic, &spr_write_generic,
3468 0xFFFFFFFF);
3469 /* not emulated, as QEMU do not emulate caches */
3470 spr_register(env, SPR_40x_DCWR, "DCWR",
3471 SPR_NOACCESS, SPR_NOACCESS,
3472 &spr_read_generic, &spr_write_generic,
3473 0x00000000);
3474 /* Memory management */
3475 #if !defined(CONFIG_USER_ONLY)
3476 env->nb_tlb = 64;
3477 env->nb_ways = 1;
3478 env->id_tlbs = 0;
3479 env->tlb_type = TLB_EMB;
3480 #endif
3481 init_excp_4xx_softmmu(env);
3482 env->dcache_line_size = 32;
3483 env->icache_line_size = 32;
3484 /* Allocate hardware IRQ controller */
3485 ppc40x_irq_init(env);
3486
3487 SET_FIT_PERIOD(8, 12, 16, 20);
3488 SET_WDT_PERIOD(16, 20, 24, 28);
3489 }
3490
3491 /* PowerPC 405 */
3492 #define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3493 PPC_DCR | PPC_WRTEE | \
3494 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3495 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3496 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3497 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3498 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3499 #define POWERPC_INSNS2_405 (PPC_NONE)
3500 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
3501 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3502 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3503 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3504 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3505 #define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3506 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3507 #define check_pow_405 check_pow_nocheck
3508
3509 static void init_proc_405 (CPUPPCState *env)
3510 {
3511 /* Time base */
3512 gen_tbl(env);
3513 gen_spr_40x(env);
3514 gen_spr_405(env);
3515 /* Bus access control */
3516 /* not emulated, as QEMU never does speculative access */
3517 spr_register(env, SPR_40x_SGR, "SGR",
3518 SPR_NOACCESS, SPR_NOACCESS,
3519 &spr_read_generic, &spr_write_generic,
3520 0xFFFFFFFF);
3521 /* not emulated, as QEMU do not emulate caches */
3522 spr_register(env, SPR_40x_DCWR, "DCWR",
3523 SPR_NOACCESS, SPR_NOACCESS,
3524 &spr_read_generic, &spr_write_generic,
3525 0x00000000);
3526 /* Memory management */
3527 #if !defined(CONFIG_USER_ONLY)
3528 env->nb_tlb = 64;
3529 env->nb_ways = 1;
3530 env->id_tlbs = 0;
3531 env->tlb_type = TLB_EMB;
3532 #endif
3533 init_excp_4xx_softmmu(env);
3534 env->dcache_line_size = 32;
3535 env->icache_line_size = 32;
3536 /* Allocate hardware IRQ controller */
3537 ppc40x_irq_init(env);
3538
3539 SET_FIT_PERIOD(8, 12, 16, 20);
3540 SET_WDT_PERIOD(16, 20, 24, 28);
3541 }
3542
3543 /* PowerPC 440 EP */
3544 #define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3545 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3546 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3547 PPC_FLOAT_STFIWX | \
3548 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3549 PPC_CACHE | PPC_CACHE_ICBI | \
3550 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3551 PPC_MEM_TLBSYNC | PPC_MFTB | \
3552 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3553 PPC_440_SPEC)
3554 #define POWERPC_INSNS2_440EP (PPC_NONE)
3555 #define POWERPC_MSRM_440EP (0x000000000006FF30ULL)
3556 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3557 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3558 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3559 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3560 #define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3561 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3562 #define check_pow_440EP check_pow_nocheck
3563
3564 static void init_proc_440EP (CPUPPCState *env)
3565 {
3566 /* Time base */
3567 gen_tbl(env);
3568 gen_spr_BookE(env, 0x000000000000FFFFULL);
3569 gen_spr_440(env);
3570 gen_spr_usprgh(env);
3571 /* Processor identification */
3572 spr_register(env, SPR_BOOKE_PIR, "PIR",
3573 SPR_NOACCESS, SPR_NOACCESS,
3574 &spr_read_generic, &spr_write_pir,
3575 0x00000000);
3576 /* XXX : not implemented */
3577 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3578 SPR_NOACCESS, SPR_NOACCESS,
3579 &spr_read_generic, &spr_write_generic,
3580 0x00000000);
3581 /* XXX : not implemented */
3582 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3583 SPR_NOACCESS, SPR_NOACCESS,
3584 &spr_read_generic, &spr_write_generic,
3585 0x00000000);
3586 /* XXX : not implemented */
3587 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3588 SPR_NOACCESS, SPR_NOACCESS,
3589 &spr_read_generic, &spr_write_generic,
3590 0x00000000);
3591 /* XXX : not implemented */
3592 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3593 SPR_NOACCESS, SPR_NOACCESS,
3594 &spr_read_generic, &spr_write_generic,
3595 0x00000000);
3596 /* XXX : not implemented */
3597 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3598 SPR_NOACCESS, SPR_NOACCESS,
3599 &spr_read_generic, &spr_write_generic,
3600 0x00000000);
3601 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3602 SPR_NOACCESS, SPR_NOACCESS,
3603 &spr_read_generic, &spr_write_generic,
3604 0x00000000);
3605 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3606 SPR_NOACCESS, SPR_NOACCESS,
3607 &spr_read_generic, &spr_write_generic,
3608 0x00000000);
3609 /* XXX : not implemented */
3610 spr_register(env, SPR_440_CCR1, "CCR1",
3611 SPR_NOACCESS, SPR_NOACCESS,
3612 &spr_read_generic, &spr_write_generic,
3613 0x00000000);
3614 /* Memory management */
3615 #if !defined(CONFIG_USER_ONLY)
3616 env->nb_tlb = 64;
3617 env->nb_ways = 1;
3618 env->id_tlbs = 0;
3619 env->tlb_type = TLB_EMB;
3620 #endif
3621 init_excp_BookE(env);
3622 env->dcache_line_size = 32;
3623 env->icache_line_size = 32;
3624 ppc40x_irq_init(env);
3625
3626 SET_FIT_PERIOD(12, 16, 20, 24);
3627 SET_WDT_PERIOD(20, 24, 28, 32);
3628 }
3629
3630 /* PowerPC 440 GP */
3631 #define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3632 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3633 PPC_CACHE | PPC_CACHE_ICBI | \
3634 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3635 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \
3636 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3637 PPC_440_SPEC)
3638 #define POWERPC_INSNS2_440GP (PPC_NONE)
3639 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3640 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3641 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3642 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3643 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3644 #define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3645 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3646 #define check_pow_440GP check_pow_nocheck
3647
3648 __attribute__ (( unused ))
3649 static void init_proc_440GP (CPUPPCState *env)
3650 {
3651 /* Time base */
3652 gen_tbl(env);
3653 gen_spr_BookE(env, 0x000000000000FFFFULL);
3654 gen_spr_440(env);
3655 gen_spr_usprgh(env);
3656 /* Processor identification */
3657 spr_register(env, SPR_BOOKE_PIR, "PIR",
3658 SPR_NOACCESS, SPR_NOACCESS,
3659 &spr_read_generic, &spr_write_pir,
3660 0x00000000);
3661 /* XXX : not implemented */
3662 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3663 SPR_NOACCESS, SPR_NOACCESS,
3664 &spr_read_generic, &spr_write_generic,
3665 0x00000000);
3666 /* XXX : not implemented */
3667 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3668 SPR_NOACCESS, SPR_NOACCESS,
3669 &spr_read_generic, &spr_write_generic,
3670 0x00000000);
3671 /* XXX : not implemented */
3672 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3673 SPR_NOACCESS, SPR_NOACCESS,
3674 &spr_read_generic, &spr_write_generic,
3675 0x00000000);
3676 /* XXX : not implemented */
3677 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3678 SPR_NOACCESS, SPR_NOACCESS,
3679 &spr_read_generic, &spr_write_generic,
3680 0x00000000);
3681 /* Memory management */
3682 #if !defined(CONFIG_USER_ONLY)
3683 env->nb_tlb = 64;
3684 env->nb_ways = 1;
3685 env->id_tlbs = 0;
3686 env->tlb_type = TLB_EMB;
3687 #endif
3688 init_excp_BookE(env);
3689 env->dcache_line_size = 32;
3690 env->icache_line_size = 32;
3691 /* XXX: TODO: allocate internal IRQ controller */
3692
3693 SET_FIT_PERIOD(12, 16, 20, 24);
3694 SET_WDT_PERIOD(20, 24, 28, 32);
3695 }
3696
3697 /* PowerPC 440x4 */
3698 #define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3699 PPC_DCR | PPC_WRTEE | \
3700 PPC_CACHE | PPC_CACHE_ICBI | \
3701 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3702 PPC_MEM_TLBSYNC | PPC_MFTB | \
3703 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3704 PPC_440_SPEC)
3705 #define POWERPC_INSNS2_440x4 (PPC_NONE)
3706 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3707 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3708 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3709 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3710 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3711 #define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3712 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3713 #define check_pow_440x4 check_pow_nocheck
3714
3715 __attribute__ (( unused ))
3716 static void init_proc_440x4 (CPUPPCState *env)
3717 {
3718 /* Time base */
3719 gen_tbl(env);
3720 gen_spr_BookE(env, 0x000000000000FFFFULL);
3721 gen_spr_440(env);
3722 gen_spr_usprgh(env);
3723 /* Processor identification */
3724 spr_register(env, SPR_BOOKE_PIR, "PIR",
3725 SPR_NOACCESS, SPR_NOACCESS,
3726 &spr_read_generic, &spr_write_pir,
3727 0x00000000);
3728 /* XXX : not implemented */
3729 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3730 SPR_NOACCESS, SPR_NOACCESS,
3731 &spr_read_generic, &spr_write_generic,
3732 0x00000000);
3733 /* XXX : not implemented */
3734 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3735 SPR_NOACCESS, SPR_NOACCESS,
3736 &spr_read_generic, &spr_write_generic,
3737 0x00000000);
3738 /* XXX : not implemented */
3739 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3740 SPR_NOACCESS, SPR_NOACCESS,
3741 &spr_read_generic, &spr_write_generic,
3742 0x00000000);
3743 /* XXX : not implemented */
3744 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3745 SPR_NOACCESS, SPR_NOACCESS,
3746 &spr_read_generic, &spr_write_generic,
3747 0x00000000);
3748 /* Memory management */
3749 #if !defined(CONFIG_USER_ONLY)
3750 env->nb_tlb = 64;
3751 env->nb_ways = 1;
3752 env->id_tlbs = 0;
3753 env->tlb_type = TLB_EMB;
3754 #endif
3755 init_excp_BookE(env);
3756 env->dcache_line_size = 32;
3757 env->icache_line_size = 32;
3758 /* XXX: TODO: allocate internal IRQ controller */
3759
3760 SET_FIT_PERIOD(12, 16, 20, 24);
3761 SET_WDT_PERIOD(20, 24, 28, 32);
3762 }
3763
3764 /* PowerPC 440x5 */
3765 #define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3766 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3767 PPC_CACHE | PPC_CACHE_ICBI | \
3768 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3769 PPC_MEM_TLBSYNC | PPC_MFTB | \
3770 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3771 PPC_440_SPEC)
3772 #define POWERPC_INSNS2_440x5 (PPC_NONE)
3773 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3774 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3775 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3776 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3777 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3778 #define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3779 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3780 #define check_pow_440x5 check_pow_nocheck
3781
3782 static void init_proc_440x5 (CPUPPCState *env)
3783 {
3784 /* Time base */
3785 gen_tbl(env);
3786 gen_spr_BookE(env, 0x000000000000FFFFULL);
3787 gen_spr_440(env);
3788 gen_spr_usprgh(env);
3789 /* Processor identification */
3790 spr_register(env, SPR_BOOKE_PIR, "PIR",
3791 SPR_NOACCESS, SPR_NOACCESS,
3792 &spr_read_generic, &spr_write_pir,
3793 0x00000000);
3794 /* XXX : not implemented */
3795 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3796 SPR_NOACCESS, SPR_NOACCESS,
3797 &spr_read_generic, &spr_write_generic,
3798 0x00000000);
3799 /* XXX : not implemented */
3800 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3801 SPR_NOACCESS, SPR_NOACCESS,
3802 &spr_read_generic, &spr_write_generic,
3803 0x00000000);
3804 /* XXX : not implemented */
3805 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3806 SPR_NOACCESS, SPR_NOACCESS,
3807 &spr_read_generic, &spr_write_generic,
3808 0x00000000);
3809 /* XXX : not implemented */
3810 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3811 SPR_NOACCESS, SPR_NOACCESS,
3812 &spr_read_generic, &spr_write_generic,
3813 0x00000000);
3814 /* XXX : not implemented */
3815 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3816 SPR_NOACCESS, SPR_NOACCESS,
3817 &spr_read_generic, &spr_write_generic,
3818 0x00000000);
3819 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3820 SPR_NOACCESS, SPR_NOACCESS,
3821 &spr_read_generic, &spr_write_generic,
3822 0x00000000);
3823 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3824 SPR_NOACCESS, SPR_NOACCESS,
3825 &spr_read_generic, &spr_write_generic,
3826 0x00000000);
3827 /* XXX : not implemented */
3828 spr_register(env, SPR_440_CCR1, "CCR1",
3829 SPR_NOACCESS, SPR_NOACCESS,
3830 &spr_read_generic, &spr_write_generic,
3831 0x00000000);
3832 /* Memory management */
3833 #if !defined(CONFIG_USER_ONLY)
3834 env->nb_tlb = 64;
3835 env->nb_ways = 1;
3836 env->id_tlbs = 0;
3837 env->tlb_type = TLB_EMB;
3838 #endif
3839 init_excp_BookE(env);
3840 env->dcache_line_size = 32;
3841 env->icache_line_size = 32;
3842 ppc40x_irq_init(env);
3843
3844 SET_FIT_PERIOD(12, 16, 20, 24);
3845 SET_WDT_PERIOD(20, 24, 28, 32);
3846 }
3847
3848 /* PowerPC 460 (guessed) */
3849 #define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
3850 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3851 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \
3852 PPC_CACHE | PPC_CACHE_ICBI | \
3853 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3854 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3855 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3856 PPC_440_SPEC)
3857 #define POWERPC_INSNS2_460 (PPC_NONE)
3858 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3859 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3860 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3861 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3862 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3863 #define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3864 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3865 #define check_pow_460 check_pow_nocheck
3866
3867 __attribute__ (( unused ))
3868 static void init_proc_460 (CPUPPCState *env)
3869 {
3870 /* Time base */
3871 gen_tbl(env);
3872 gen_spr_BookE(env, 0x000000000000FFFFULL);
3873 gen_spr_440(env);
3874 gen_spr_usprgh(env);
3875 /* Processor identification */
3876 spr_register(env, SPR_BOOKE_PIR, "PIR",
3877 SPR_NOACCESS, SPR_NOACCESS,
3878 &spr_read_generic, &spr_write_pir,
3879 0x00000000);
3880 /* XXX : not implemented */
3881 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3882 SPR_NOACCESS, SPR_NOACCESS,
3883 &spr_read_generic, &spr_write_generic,
3884 0x00000000);
3885 /* XXX : not implemented */
3886 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3887 SPR_NOACCESS, SPR_NOACCESS,
3888 &spr_read_generic, &spr_write_generic,
3889 0x00000000);
3890 /* XXX : not implemented */
3891 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3892 SPR_NOACCESS, SPR_NOACCESS,
3893 &spr_read_generic, &spr_write_generic,
3894 0x00000000);
3895 /* XXX : not implemented */
3896 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3897 SPR_NOACCESS, SPR_NOACCESS,
3898 &spr_read_generic, &spr_write_generic,
3899 0x00000000);
3900 /* XXX : not implemented */
3901 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3902 SPR_NOACCESS, SPR_NOACCESS,
3903 &spr_read_generic, &spr_write_generic,
3904 0x00000000);
3905 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3906 SPR_NOACCESS, SPR_NOACCESS,
3907 &spr_read_generic, &spr_write_generic,
3908 0x00000000);
3909 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3910 SPR_NOACCESS, SPR_NOACCESS,
3911 &spr_read_generic, &spr_write_generic,
3912 0x00000000);
3913 /* XXX : not implemented */
3914 spr_register(env, SPR_440_CCR1, "CCR1",
3915 SPR_NOACCESS, SPR_NOACCESS,
3916 &spr_read_generic, &spr_write_generic,
3917 0x00000000);
3918 /* XXX : not implemented */
3919 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3920 &spr_read_generic, &spr_write_generic,
3921 &spr_read_generic, &spr_write_generic,
3922 0x00000000);
3923 /* Memory management */
3924 #if !defined(CONFIG_USER_ONLY)
3925 env->nb_tlb = 64;
3926 env->nb_ways = 1;
3927 env->id_tlbs = 0;
3928 env->tlb_type = TLB_EMB;
3929 #endif
3930 init_excp_BookE(env);
3931 env->dcache_line_size = 32;
3932 env->icache_line_size = 32;
3933 /* XXX: TODO: allocate internal IRQ controller */
3934
3935 SET_FIT_PERIOD(12, 16, 20, 24);
3936 SET_WDT_PERIOD(20, 24, 28, 32);
3937 }
3938
3939 /* PowerPC 460F (guessed) */
3940 #define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3941 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3942 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3943 PPC_FLOAT_STFIWX | PPC_MFTB | \
3944 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3945 PPC_WRTEE | PPC_MFAPIDI | \
3946 PPC_CACHE | PPC_CACHE_ICBI | \
3947 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3948 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3949 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3950 PPC_440_SPEC)
3951 #define POWERPC_INSNS2_460F (PPC_NONE)
3952 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3953 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3954 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3955 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3956 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3957 #define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3958 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3959 #define check_pow_460F check_pow_nocheck
3960
3961 __attribute__ (( unused ))
3962 static void init_proc_460F (CPUPPCState *env)
3963 {
3964 /* Time base */
3965 gen_tbl(env);
3966 gen_spr_BookE(env, 0x000000000000FFFFULL);
3967 gen_spr_440(env);
3968 gen_spr_usprgh(env);
3969 /* Processor identification */
3970 spr_register(env, SPR_BOOKE_PIR, "PIR",
3971 SPR_NOACCESS, SPR_NOACCESS,
3972 &spr_read_generic, &spr_write_pir,
3973 0x00000000);
3974 /* XXX : not implemented */
3975 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3976 SPR_NOACCESS, SPR_NOACCESS,
3977 &spr_read_generic, &spr_write_generic,
3978 0x00000000);
3979 /* XXX : not implemented */
3980 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3981 SPR_NOACCESS, SPR_NOACCESS,
3982 &spr_read_generic, &spr_write_generic,
3983 0x00000000);
3984 /* XXX : not implemented */
3985 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3986 SPR_NOACCESS, SPR_NOACCESS,
3987 &spr_read_generic, &spr_write_generic,
3988 0x00000000);
3989 /* XXX : not implemented */
3990 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3991 SPR_NOACCESS, SPR_NOACCESS,
3992 &spr_read_generic, &spr_write_generic,
3993 0x00000000);
3994 /* XXX : not implemented */
3995 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3996 SPR_NOACCESS, SPR_NOACCESS,
3997 &spr_read_generic, &spr_write_generic,
3998 0x00000000);
3999 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4000 SPR_NOACCESS, SPR_NOACCESS,
4001 &spr_read_generic, &spr_write_generic,
4002 0x00000000);
4003 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4004 SPR_NOACCESS, SPR_NOACCESS,
4005 &spr_read_generic, &spr_write_generic,
4006 0x00000000);
4007 /* XXX : not implemented */
4008 spr_register(env, SPR_440_CCR1, "CCR1",
4009 SPR_NOACCESS, SPR_NOACCESS,
4010 &spr_read_generic, &spr_write_generic,
4011 0x00000000);
4012 /* XXX : not implemented */
4013 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4014 &spr_read_generic, &spr_write_generic,
4015 &spr_read_generic, &spr_write_generic,
4016 0x00000000);
4017 /* Memory management */
4018 #if !defined(CONFIG_USER_ONLY)
4019 env->nb_tlb = 64;
4020 env->nb_ways = 1;
4021 env->id_tlbs = 0;
4022 env->tlb_type = TLB_EMB;
4023 #endif
4024 init_excp_BookE(env);
4025 env->dcache_line_size = 32;
4026 env->icache_line_size = 32;
4027 /* XXX: TODO: allocate internal IRQ controller */
4028
4029 SET_FIT_PERIOD(12, 16, 20, 24);
4030 SET_WDT_PERIOD(20, 24, 28, 32);
4031 }
4032
4033 /* Freescale 5xx cores (aka RCPU) */
4034 #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
4035 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4036 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
4037 PPC_MFTB)
4038 #define POWERPC_INSNS2_MPC5xx (PPC_NONE)
4039 #define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
4040 #define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
4041 #define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
4042 #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
4043 #define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4044 #define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4045 POWERPC_FLAG_BUS_CLK)
4046 #define check_pow_MPC5xx check_pow_none
4047
4048 __attribute__ (( unused ))
4049 static void init_proc_MPC5xx (CPUPPCState *env)
4050 {
4051 /* Time base */
4052 gen_tbl(env);
4053 gen_spr_5xx_8xx(env);
4054 gen_spr_5xx(env);
4055 init_excp_MPC5xx(env);
4056 env->dcache_line_size = 32;
4057 env->icache_line_size = 32;
4058 /* XXX: TODO: allocate internal IRQ controller */
4059 }
4060
4061 /* Freescale 8xx cores (aka PowerQUICC) */
4062 #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
4063 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4064 PPC_CACHE_ICBI | PPC_MFTB)
4065 #define POWERPC_INSNS2_MPC8xx (PPC_NONE)
4066 #define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
4067 #define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
4068 #define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
4069 #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
4070 #define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4071 #define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4072 POWERPC_FLAG_BUS_CLK)
4073 #define check_pow_MPC8xx check_pow_none
4074
4075 __attribute__ (( unused ))
4076 static void init_proc_MPC8xx (CPUPPCState *env)
4077 {
4078 /* Time base */
4079 gen_tbl(env);
4080 gen_spr_5xx_8xx(env);
4081 gen_spr_8xx(env);
4082 init_excp_MPC8xx(env);
4083 env->dcache_line_size = 32;
4084 env->icache_line_size = 32;
4085 /* XXX: TODO: allocate internal IRQ controller */
4086 }
4087
4088 /* Freescale 82xx cores (aka PowerQUICC-II) */
4089 /* PowerPC G2 */
4090 #define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4091 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4092 PPC_FLOAT_STFIWX | \
4093 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4094 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4095 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4096 PPC_SEGMENT | PPC_EXTERN)
4097 #define POWERPC_INSNS2_G2 (PPC_NONE)
4098 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
4099 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
4100 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
4101 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
4102 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
4103 #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4104 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4105 #define check_pow_G2 check_pow_hid0
4106
4107 static void init_proc_G2 (CPUPPCState *env)
4108 {
4109 gen_spr_ne_601(env);
4110 gen_spr_G2_755(env);
4111 gen_spr_G2(env);
4112 /* Time base */
4113 gen_tbl(env);
4114 /* External access control */
4115 /* XXX : not implemented */
4116 spr_register(env, SPR_EAR, "EAR",
4117 SPR_NOACCESS, SPR_NOACCESS,
4118 &spr_read_generic, &spr_write_generic,
4119 0x00000000);
4120 /* Hardware implementation register */
4121 /* XXX : not implemented */
4122 spr_register(env, SPR_HID0, "HID0",
4123 SPR_NOACCESS, SPR_NOACCESS,
4124 &spr_read_generic, &spr_write_generic,
4125 0x00000000);
4126 /* XXX : not implemented */
4127 spr_register(env, SPR_HID1, "HID1",
4128 SPR_NOACCESS, SPR_NOACCESS,
4129 &spr_read_generic, &spr_write_generic,
4130 0x00000000);
4131 /* XXX : not implemented */
4132 spr_register(env, SPR_HID2, "HID2",
4133 SPR_NOACCESS, SPR_NOACCESS,
4134 &spr_read_generic, &spr_write_generic,
4135 0x00000000);
4136 /* Memory management */
4137 gen_low_BATs(env);
4138 gen_high_BATs(env);
4139 gen_6xx_7xx_soft_tlb(env, 64, 2);
4140 init_excp_G2(env);
4141 env->dcache_line_size = 32;
4142 env->icache_line_size = 32;
4143 /* Allocate hardware IRQ controller */
4144 ppc6xx_irq_init(env);
4145 }
4146
4147 /* PowerPC G2LE */
4148 #define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4149 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4150 PPC_FLOAT_STFIWX | \
4151 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4152 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4153 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4154 PPC_SEGMENT | PPC_EXTERN)
4155 #define POWERPC_INSNS2_G2LE (PPC_NONE)
4156 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
4157 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
4158 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
4159 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
4160 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
4161 #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4162 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4163 #define check_pow_G2LE check_pow_hid0
4164
4165 static void init_proc_G2LE (CPUPPCState *env)
4166 {
4167 gen_spr_ne_601(env);
4168 gen_spr_G2_755(env);
4169 gen_spr_G2(env);
4170 /* Time base */
4171 gen_tbl(env);
4172 /* External access control */
4173 /* XXX : not implemented */
4174 spr_register(env, SPR_EAR, "EAR",
4175 SPR_NOACCESS, SPR_NOACCESS,
4176 &spr_read_generic, &spr_write_generic,
4177 0x00000000);
4178 /* Hardware implementation register */
4179 /* XXX : not implemented */
4180 spr_register(env, SPR_HID0, "HID0",
4181 SPR_NOACCESS, SPR_NOACCESS,
4182 &spr_read_generic, &spr_write_generic,
4183 0x00000000);
4184 /* XXX : not implemented */
4185 spr_register(env, SPR_HID1, "HID1",
4186 SPR_NOACCESS, SPR_NOACCESS,
4187 &spr_read_generic, &spr_write_generic,
4188 0x00000000);
4189 /* XXX : not implemented */
4190 spr_register(env, SPR_HID2, "HID2",
4191 SPR_NOACCESS, SPR_NOACCESS,
4192 &spr_read_generic, &spr_write_generic,
4193 0x00000000);
4194 /* Memory management */
4195 gen_low_BATs(env);
4196 gen_high_BATs(env);
4197 gen_6xx_7xx_soft_tlb(env, 64, 2);
4198 init_excp_G2(env);
4199 env->dcache_line_size = 32;
4200 env->icache_line_size = 32;
4201 /* Allocate hardware IRQ controller */
4202 ppc6xx_irq_init(env);
4203 }
4204
4205 /* e200 core */
4206 /* XXX: unimplemented instructions:
4207 * dcblc
4208 * dcbtlst
4209 * dcbtstls
4210 * icblc
4211 * icbtls
4212 * tlbivax
4213 * all SPE multiply-accumulate instructions
4214 */
4215 #define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
4216 PPC_SPE | PPC_SPE_SINGLE | \
4217 PPC_WRTEE | PPC_RFDI | \
4218 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4219 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4220 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4221 PPC_BOOKE)
4222 #define POWERPC_INSNS2_e200 (PPC_NONE)
4223 #define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
4224 #define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
4225 #define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
4226 #define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
4227 #define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
4228 #define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4229 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4230 POWERPC_FLAG_BUS_CLK)
4231 #define check_pow_e200 check_pow_hid0
4232
4233 __attribute__ (( unused ))
4234 static void init_proc_e200 (CPUPPCState *env)
4235 {
4236 /* Time base */
4237 gen_tbl(env);
4238 gen_spr_BookE(env, 0x000000070000FFFFULL);
4239 /* XXX : not implemented */
4240 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4241 &spr_read_spefscr, &spr_write_spefscr,
4242 &spr_read_spefscr, &spr_write_spefscr,
4243 0x00000000);
4244 /* Memory management */
4245 gen_spr_BookE206(env, 0x0000005D, NULL);
4246 /* XXX : not implemented */
4247 spr_register(env, SPR_HID0, "HID0",
4248 SPR_NOACCESS, SPR_NOACCESS,
4249 &spr_read_generic, &spr_write_generic,
4250 0x00000000);
4251 /* XXX : not implemented */
4252 spr_register(env, SPR_HID1, "HID1",
4253 SPR_NOACCESS, SPR_NOACCESS,
4254 &spr_read_generic, &spr_write_generic,
4255 0x00000000);
4256 /* XXX : not implemented */
4257 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4258 SPR_NOACCESS, SPR_NOACCESS,
4259 &spr_read_generic, &spr_write_generic,
4260 0x00000000);
4261 /* XXX : not implemented */
4262 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4263 SPR_NOACCESS, SPR_NOACCESS,
4264 &spr_read_generic, &spr_write_generic,
4265 0x00000000);
4266 /* XXX : not implemented */
4267 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4268 SPR_NOACCESS, SPR_NOACCESS,
4269 &spr_read_generic, &spr_write_generic,
4270 0x00000000);
4271 /* XXX : not implemented */
4272 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4273 SPR_NOACCESS, SPR_NOACCESS,
4274 &spr_read_generic, &spr_write_generic,
4275 0x00000000);
4276 /* XXX : not implemented */
4277 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4278 SPR_NOACCESS, SPR_NOACCESS,
4279 &spr_read_generic, &spr_write_generic,
4280 0x00000000);
4281 /* XXX : not implemented */
4282 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4283 SPR_NOACCESS, SPR_NOACCESS,
4284 &spr_read_generic, &spr_write_generic,
4285 0x00000000);
4286 /* XXX : not implemented */
4287 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4288 SPR_NOACCESS, SPR_NOACCESS,
4289 &spr_read_generic, &spr_write_generic,
4290 0x00000000);
4291 /* XXX : not implemented */
4292 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4293 SPR_NOACCESS, SPR_NOACCESS,
4294 &spr_read_generic, &spr_write_generic,
4295 0x00000000);
4296 /* XXX : not implemented */
4297 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4298 SPR_NOACCESS, SPR_NOACCESS,
4299 &spr_read_generic, &spr_write_generic,
4300 0x00000000);
4301 /* XXX : not implemented */
4302 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4303 SPR_NOACCESS, SPR_NOACCESS,
4304 &spr_read_generic, &spr_write_generic,
4305 0x00000000);
4306 /* XXX : not implemented */
4307 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4308 SPR_NOACCESS, SPR_NOACCESS,
4309 &spr_read_generic, &spr_write_generic,
4310 0x00000000);
4311 /* XXX : not implemented */
4312 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4313 SPR_NOACCESS, SPR_NOACCESS,
4314 &spr_read_generic, &spr_write_generic,
4315 0x00000000);
4316 /* XXX : not implemented */
4317 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4318 SPR_NOACCESS, SPR_NOACCESS,
4319 &spr_read_generic, &spr_write_generic,
4320 0x00000000); /* TOFIX */
4321 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4322 SPR_NOACCESS, SPR_NOACCESS,
4323 &spr_read_generic, &spr_write_generic,
4324 0x00000000);
4325 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4326 SPR_NOACCESS, SPR_NOACCESS,
4327 &spr_read_generic, &spr_write_generic,
4328 0x00000000);
4329 #if !defined(CONFIG_USER_ONLY)
4330 env->nb_tlb = 64;
4331 env->nb_ways = 1;
4332 env->id_tlbs = 0;
4333 env->tlb_type = TLB_EMB;
4334 #endif
4335 init_excp_e200(env, 0xFFFF0000UL);
4336 env->dcache_line_size = 32;
4337 env->icache_line_size = 32;
4338 /* XXX: TODO: allocate internal IRQ controller */
4339 }
4340
4341 /* e300 core */
4342 #define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4343 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4344 PPC_FLOAT_STFIWX | \
4345 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4346 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4347 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4348 PPC_SEGMENT | PPC_EXTERN)
4349 #define POWERPC_INSNS2_e300 (PPC_NONE)
4350 #define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4351 #define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4352 #define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4353 #define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4354 #define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4355 #define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4356 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4357 #define check_pow_e300 check_pow_hid0
4358
4359 __attribute__ (( unused ))
4360 static void init_proc_e300 (CPUPPCState *env)
4361 {
4362 gen_spr_ne_601(env);
4363 gen_spr_603(env);
4364 /* Time base */
4365 gen_tbl(env);
4366 /* hardware implementation registers */
4367 /* XXX : not implemented */
4368 spr_register(env, SPR_HID0, "HID0",
4369 SPR_NOACCESS, SPR_NOACCESS,
4370 &spr_read_generic, &spr_write_generic,
4371 0x00000000);
4372 /* XXX : not implemented */
4373 spr_register(env, SPR_HID1, "HID1",
4374 SPR_NOACCESS, SPR_NOACCESS,
4375 &spr_read_generic, &spr_write_generic,
4376 0x00000000);
4377 /* XXX : not implemented */
4378 spr_register(env, SPR_HID2, "HID2",
4379 SPR_NOACCESS, SPR_NOACCESS,
4380 &spr_read_generic, &spr_write_generic,
4381 0x00000000);
4382 /* Memory management */
4383 gen_low_BATs(env);
4384 gen_high_BATs(env);
4385 gen_6xx_7xx_soft_tlb(env, 64, 2);
4386 init_excp_603(env);
4387 env->dcache_line_size = 32;
4388 env->icache_line_size = 32;
4389 /* Allocate hardware IRQ controller */
4390 ppc6xx_irq_init(env);
4391 }
4392
4393 /* e500v1 core */
4394 #define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4395 PPC_SPE | PPC_SPE_SINGLE | \
4396 PPC_WRTEE | PPC_RFDI | \
4397 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4398 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4399 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
4400 #define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206)
4401 #define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
4402 #define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
4403 #define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4404 #define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4405 #define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4406 #define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4407 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4408 POWERPC_FLAG_BUS_CLK)
4409 #define check_pow_e500v1 check_pow_hid0
4410 #define init_proc_e500v1 init_proc_e500v1
4411
4412 /* e500v2 core */
4413 #define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4414 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4415 PPC_WRTEE | PPC_RFDI | \
4416 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4417 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4418 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
4419 #define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206)
4420 #define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
4421 #define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
4422 #define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4423 #define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4424 #define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4425 #define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4426 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4427 POWERPC_FLAG_BUS_CLK)
4428 #define check_pow_e500v2 check_pow_hid0
4429 #define init_proc_e500v2 init_proc_e500v2
4430
4431 /* e500mc core */
4432 #define POWERPC_INSNS_e500mc (PPC_INSNS_BASE | PPC_ISEL | \
4433 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | \
4434 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4435 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4436 PPC_FLOAT | PPC_FLOAT_FRES | \
4437 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
4438 PPC_FLOAT_STFIWX | PPC_WAIT | \
4439 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
4440 #define POWERPC_INSNS2_e500mc (PPC2_BOOKE206 | PPC2_PRCNTL)
4441 #define POWERPC_MSRM_e500mc (0x000000001402FB36ULL)
4442 #define POWERPC_MMU_e500mc (POWERPC_MMU_BOOKE206)
4443 #define POWERPC_EXCP_e500mc (POWERPC_EXCP_BOOKE)
4444 #define POWERPC_INPUT_e500mc (PPC_FLAGS_INPUT_BookE)
4445 /* Fixme: figure out the correct flag for e500mc */
4446 #define POWERPC_BFDM_e500mc (bfd_mach_ppc_e500)
4447 #define POWERPC_FLAG_e500mc (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
4448 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4449 #define check_pow_e500mc check_pow_none
4450 #define init_proc_e500mc init_proc_e500mc
4451
4452 /* e5500 core */
4453 #define POWERPC_INSNS_e5500 (PPC_INSNS_BASE | PPC_ISEL | \
4454 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | \
4455 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4456 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4457 PPC_FLOAT | PPC_FLOAT_FRES | \
4458 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
4459 PPC_FLOAT_STFIWX | PPC_WAIT | \
4460 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | \
4461 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD)
4462 #define POWERPC_INSNS2_e5500 (PPC2_BOOKE206 | PPC2_PRCNTL)
4463 #define POWERPC_MSRM_e5500 (0x000000009402FB36ULL)
4464 #define POWERPC_MMU_e5500 (POWERPC_MMU_BOOKE206)
4465 #define POWERPC_EXCP_e5500 (POWERPC_EXCP_BOOKE)
4466 #define POWERPC_INPUT_e5500 (PPC_FLAGS_INPUT_BookE)
4467 /* Fixme: figure out the correct flag for e5500 */
4468 #define POWERPC_BFDM_e5500 (bfd_mach_ppc_e500)
4469 #define POWERPC_FLAG_e5500 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
4470 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4471 #define check_pow_e5500 check_pow_none
4472 #define init_proc_e5500 init_proc_e5500
4473
4474 #if !defined(CONFIG_USER_ONLY)
4475 static void spr_write_mas73(void *opaque, int sprn, int gprn)
4476 {
4477 TCGv val = tcg_temp_new();
4478 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4479 gen_store_spr(SPR_BOOKE_MAS3, val);
4480 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4481 gen_store_spr(SPR_BOOKE_MAS7, val);
4482 tcg_temp_free(val);
4483 }
4484
4485 static void spr_read_mas73(void *opaque, int gprn, int sprn)
4486 {
4487 TCGv mas7 = tcg_temp_new();
4488 TCGv mas3 = tcg_temp_new();
4489 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4490 tcg_gen_shli_tl(mas7, mas7, 32);
4491 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4492 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4493 tcg_temp_free(mas3);
4494 tcg_temp_free(mas7);
4495 }
4496
4497 #endif
4498
4499 enum fsl_e500_version {
4500 fsl_e500v1,
4501 fsl_e500v2,
4502 fsl_e500mc,
4503 fsl_e5500,
4504 };
4505
4506 static void init_proc_e500 (CPUPPCState *env, int version)
4507 {
4508 uint32_t tlbncfg[2];
4509 uint64_t ivor_mask;
4510 uint64_t ivpr_mask = 0xFFFF0000ULL;
4511 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4512 | 0x0020; /* 32 kb */
4513 #if !defined(CONFIG_USER_ONLY)
4514 int i;
4515 #endif
4516
4517 /* Time base */
4518 gen_tbl(env);
4519 /*
4520 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4521 * complain when accessing them.
4522 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4523 */
4524 switch (version) {
4525 case fsl_e500v1:
4526 case fsl_e500v2:
4527 default:
4528 ivor_mask = 0x0000000F0000FFFFULL;
4529 break;
4530 case fsl_e500mc:
4531 case fsl_e5500:
4532 ivor_mask = 0x000003FE0000FFFFULL;
4533 break;
4534 }
4535 gen_spr_BookE(env, ivor_mask);
4536 /* Processor identification */
4537 spr_register(env, SPR_BOOKE_PIR, "PIR",
4538 SPR_NOACCESS, SPR_NOACCESS,
4539 &spr_read_generic, &spr_write_pir,
4540 0x00000000);
4541 /* XXX : not implemented */
4542 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4543 &spr_read_spefscr, &spr_write_spefscr,
4544 &spr_read_spefscr, &spr_write_spefscr,
4545 0x00000000);
4546 #if !defined(CONFIG_USER_ONLY)
4547 /* Memory management */
4548 env->nb_pids = 3;
4549 env->nb_ways = 2;
4550 env->id_tlbs = 0;
4551 switch (version) {
4552 case fsl_e500v1:
4553 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4554 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4555 break;
4556 case fsl_e500v2:
4557 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4558 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4559 break;
4560 case fsl_e500mc:
4561 case fsl_e5500:
4562 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4563 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4564 break;
4565 default:
4566 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4567 }
4568 #endif
4569 /* Cache sizes */
4570 switch (version) {
4571 case fsl_e500v1:
4572 case fsl_e500v2:
4573 env->dcache_line_size = 32;
4574 env->icache_line_size = 32;
4575 break;
4576 case fsl_e500mc:
4577 case fsl_e5500:
4578 env->dcache_line_size = 64;
4579 env->icache_line_size = 64;
4580 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4581 break;
4582 default:
4583 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4584 }
4585 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4586 /* XXX : not implemented */
4587 spr_register(env, SPR_HID0, "HID0",
4588 SPR_NOACCESS, SPR_NOACCESS,
4589 &spr_read_generic, &spr_write_generic,
4590 0x00000000);
4591 /* XXX : not implemented */
4592 spr_register(env, SPR_HID1, "HID1",
4593 SPR_NOACCESS, SPR_NOACCESS,
4594 &spr_read_generic, &spr_write_generic,
4595 0x00000000);
4596 /* XXX : not implemented */
4597 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4598 SPR_NOACCESS, SPR_NOACCESS,
4599 &spr_read_generic, &spr_write_generic,
4600 0x00000000);
4601 /* XXX : not implemented */
4602 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4603 SPR_NOACCESS, SPR_NOACCESS,
4604 &spr_read_generic, &spr_write_generic,
4605 0x00000000);
4606 /* XXX : not implemented */
4607 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4608 SPR_NOACCESS, SPR_NOACCESS,
4609 &spr_read_generic, &spr_write_generic,
4610 0x00000000);
4611 /* XXX : not implemented */
4612 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4613 SPR_NOACCESS, SPR_NOACCESS,
4614 &spr_read_generic, &spr_write_generic,
4615 0x00000000);
4616 /* XXX : not implemented */
4617 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4618 SPR_NOACCESS, SPR_NOACCESS,
4619 &spr_read_generic, &spr_write_generic,
4620 0x00000000);
4621 /* XXX : not implemented */
4622 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4623 SPR_NOACCESS, SPR_NOACCESS,
4624 &spr_read_generic, &spr_write_generic,
4625 0x00000000);
4626 /* XXX : not implemented */
4627 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4628 SPR_NOACCESS, SPR_NOACCESS,
4629 &spr_read_generic, &spr_write_generic,
4630 l1cfg0);
4631 /* XXX : not implemented */
4632 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4633 SPR_NOACCESS, SPR_NOACCESS,
4634 &spr_read_generic, &spr_write_e500_l1csr0,
4635 0x00000000);
4636 /* XXX : not implemented */
4637 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4638 SPR_NOACCESS, SPR_NOACCESS,
4639 &spr_read_generic, &spr_write_generic,
4640 0x00000000);
4641 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4642 SPR_NOACCESS, SPR_NOACCESS,
4643 &spr_read_generic, &spr_write_generic,
4644 0x00000000);
4645 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4646 SPR_NOACCESS, SPR_NOACCESS,
4647 &spr_read_generic, &spr_write_generic,
4648 0x00000000);
4649 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4650 SPR_NOACCESS, SPR_NOACCESS,
4651 &spr_read_generic, &spr_write_booke206_mmucsr0,
4652 0x00000000);
4653 spr_register(env, SPR_BOOKE_EPR, "EPR",
4654 SPR_NOACCESS, SPR_NOACCESS,
4655 &spr_read_generic, SPR_NOACCESS,
4656 0x00000000);
4657 /* XXX better abstract into Emb.xxx features */
4658 if (version == fsl_e5500) {
4659 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4660 SPR_NOACCESS, SPR_NOACCESS,
4661 &spr_read_generic, &spr_write_generic,
4662 0x00000000);
4663 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4664 SPR_NOACCESS, SPR_NOACCESS,
4665 &spr_read_mas73, &spr_write_mas73,
4666 0x00000000);
4667 ivpr_mask = (target_ulong)~0xFFFFULL;
4668 }
4669
4670 #if !defined(CONFIG_USER_ONLY)
4671 env->nb_tlb = 0;
4672 env->tlb_type = TLB_MAS;
4673 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4674 env->nb_tlb += booke206_tlb_size(env, i);
4675 }
4676 #endif
4677
4678 init_excp_e200(env, ivpr_mask);
4679 /* Allocate hardware IRQ controller */
4680 ppce500_irq_init(env);
4681 }
4682
4683 static void init_proc_e500v1(CPUPPCState *env)
4684 {
4685 init_proc_e500(env, fsl_e500v1);
4686 }
4687
4688 static void init_proc_e500v2(CPUPPCState *env)
4689 {
4690 init_proc_e500(env, fsl_e500v2);
4691 }
4692
4693 static void init_proc_e500mc(CPUPPCState *env)
4694 {
4695 init_proc_e500(env, fsl_e500mc);
4696 }
4697
4698 #ifdef TARGET_PPC64
4699 static void init_proc_e5500(CPUPPCState *env)
4700 {
4701 init_proc_e500(env, fsl_e5500);
4702 }
4703 #endif
4704
4705 /* Non-embedded PowerPC */
4706
4707 /* POWER : same as 601, without mfmsr, mfsr */
4708 #if defined(TODO)
4709 #define POWERPC_INSNS_POWER (XXX_TODO)
4710 /* POWER RSC (from RAD6000) */
4711 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4712 #endif /* TODO */
4713
4714 /* PowerPC 601 */
4715 #define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4716 PPC_FLOAT | \
4717 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4718 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4719 PPC_SEGMENT | PPC_EXTERN)
4720 #define POWERPC_INSNS2_601 (PPC_NONE)
4721 #define POWERPC_MSRM_601 (0x000000000000FD70ULL)
4722 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4723 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
4724 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4725 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
4726 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4727 #define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4728 #define check_pow_601 check_pow_none
4729
4730 static void init_proc_601 (CPUPPCState *env)
4731 {
4732 gen_spr_ne_601(env);
4733 gen_spr_601(env);
4734 /* Hardware implementation registers */
4735 /* XXX : not implemented */
4736 spr_register(env, SPR_HID0, "HID0",
4737 SPR_NOACCESS, SPR_NOACCESS,
4738 &spr_read_generic, &spr_write_hid0_601,
4739 0x80010080);
4740 /* XXX : not implemented */
4741 spr_register(env, SPR_HID1, "HID1",
4742 SPR_NOACCESS, SPR_NOACCESS,
4743 &spr_read_generic, &spr_write_generic,
4744 0x00000000);
4745 /* XXX : not implemented */
4746 spr_register(env, SPR_601_HID2, "HID2",
4747 SPR_NOACCESS, SPR_NOACCESS,
4748 &spr_read_generic, &spr_write_generic,
4749 0x00000000);
4750 /* XXX : not implemented */
4751 spr_register(env, SPR_601_HID5, "HID5",
4752 SPR_NOACCESS, SPR_NOACCESS,
4753 &spr_read_generic, &spr_write_generic,
4754 0x00000000);
4755 /* Memory management */
4756 init_excp_601(env);
4757 /* XXX: beware that dcache line size is 64
4758 * but dcbz uses 32 bytes "sectors"
4759 * XXX: this breaks clcs instruction !
4760 */
4761 env->dcache_line_size = 32;
4762 env->icache_line_size = 64;
4763 /* Allocate hardware IRQ controller */
4764 ppc6xx_irq_init(env);
4765 }
4766
4767 /* PowerPC 601v */
4768 #define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4769 PPC_FLOAT | \
4770 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4771 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4772 PPC_SEGMENT | PPC_EXTERN)
4773 #define POWERPC_INSNS2_601v (PPC_NONE)
4774 #define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4775 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4776 #define POWERPC_MMU_601v (POWERPC_MMU_601)
4777 #define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4778 #define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4779 #define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4780 #define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4781 #define check_pow_601v check_pow_none
4782
4783 static void init_proc_601v (CPUPPCState *env)
4784 {
4785 init_proc_601(env);
4786 /* XXX : not implemented */
4787 spr_register(env, SPR_601_HID15, "HID15",
4788 SPR_NOACCESS, SPR_NOACCESS,
4789 &spr_read_generic, &spr_write_generic,
4790 0x00000000);
4791 }
4792
4793 /* PowerPC 602 */
4794 #define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4795 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4796 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4797 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4798 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4799 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4800 PPC_SEGMENT | PPC_602_SPEC)
4801 #define POWERPC_INSNS2_602 (PPC_NONE)
4802 #define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4803 /* XXX: 602 MMU is quite specific. Should add a special case */
4804 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4805 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4806 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
4807 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
4808 #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4809 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4810 #define check_pow_602 check_pow_hid0
4811
4812 static void init_proc_602 (CPUPPCState *env)
4813 {
4814 gen_spr_ne_601(env);
4815 gen_spr_602(env);
4816 /* Time base */
4817 gen_tbl(env);
4818 /* hardware implementation registers */
4819 /* XXX : not implemented */
4820 spr_register(env, SPR_HID0, "HID0",
4821 SPR_NOACCESS, SPR_NOACCESS,
4822 &spr_read_generic, &spr_write_generic,
4823 0x00000000);
4824 /* XXX : not implemented */
4825 spr_register(env, SPR_HID1, "HID1",
4826 SPR_NOACCESS, SPR_NOACCESS,
4827 &spr_read_generic, &spr_write_generic,
4828 0x00000000);
4829 /* Memory management */
4830 gen_low_BATs(env);
4831 gen_6xx_7xx_soft_tlb(env, 64, 2);
4832 init_excp_602(env);
4833 env->dcache_line_size = 32;
4834 env->icache_line_size = 32;
4835 /* Allocate hardware IRQ controller */
4836 ppc6xx_irq_init(env);
4837 }
4838
4839 /* PowerPC 603 */
4840 #define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4841 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4842 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4843 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4844 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4845 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4846 PPC_SEGMENT | PPC_EXTERN)
4847 #define POWERPC_INSNS2_603 (PPC_NONE)
4848 #define POWERPC_MSRM_603 (0x000000000007FF73ULL)
4849 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4850 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4851 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
4852 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
4853 #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4854 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4855 #define check_pow_603 check_pow_hid0
4856
4857 static void init_proc_603 (CPUPPCState *env)
4858 {
4859 gen_spr_ne_601(env);
4860 gen_spr_603(env);
4861 /* Time base */
4862 gen_tbl(env);
4863 /* hardware implementation registers */
4864 /* XXX : not implemented */
4865 spr_register(env, SPR_HID0, "HID0",
4866 SPR_NOACCESS, SPR_NOACCESS,
4867 &spr_read_generic, &spr_write_generic,
4868 0x00000000);
4869 /* XXX : not implemented */
4870 spr_register(env, SPR_HID1, "HID1",
4871 SPR_NOACCESS, SPR_NOACCESS,
4872 &spr_read_generic, &spr_write_generic,
4873 0x00000000);
4874 /* Memory management */
4875 gen_low_BATs(env);
4876 gen_6xx_7xx_soft_tlb(env, 64, 2);
4877 init_excp_603(env);
4878 env->dcache_line_size = 32;
4879 env->icache_line_size = 32;
4880 /* Allocate hardware IRQ controller */
4881 ppc6xx_irq_init(env);
4882 }
4883
4884 /* PowerPC 603e */
4885 #define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4886 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4887 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4888 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4889 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4890 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4891 PPC_SEGMENT | PPC_EXTERN)
4892 #define POWERPC_INSNS2_603E (PPC_NONE)
4893 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4894 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4895 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4896 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
4897 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
4898 #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4899 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4900 #define check_pow_603E check_pow_hid0
4901
4902 static void init_proc_603E (CPUPPCState *env)
4903 {
4904 gen_spr_ne_601(env);
4905 gen_spr_603(env);
4906 /* Time base */
4907 gen_tbl(env);
4908 /* hardware implementation registers */
4909 /* XXX : not implemented */
4910 spr_register(env, SPR_HID0, "HID0",
4911 SPR_NOACCESS, SPR_NOACCESS,
4912 &spr_read_generic, &spr_write_generic,
4913 0x00000000);
4914 /* XXX : not implemented */
4915 spr_register(env, SPR_HID1, "HID1",
4916 SPR_NOACCESS, SPR_NOACCESS,
4917 &spr_read_generic, &spr_write_generic,
4918 0x00000000);
4919 /* XXX : not implemented */
4920 spr_register(env, SPR_IABR, "IABR",
4921 SPR_NOACCESS, SPR_NOACCESS,
4922 &spr_read_generic, &spr_write_generic,
4923 0x00000000);
4924 /* Memory management */
4925 gen_low_BATs(env);
4926 gen_6xx_7xx_soft_tlb(env, 64, 2);
4927 init_excp_603(env);
4928 env->dcache_line_size = 32;
4929 env->icache_line_size = 32;
4930 /* Allocate hardware IRQ controller */
4931 ppc6xx_irq_init(env);
4932 }
4933
4934 /* PowerPC 604 */
4935 #define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4936 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4937 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4938 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4939 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4940 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4941 PPC_SEGMENT | PPC_EXTERN)
4942 #define POWERPC_INSNS2_604 (PPC_NONE)
4943 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4944 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
4945 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4946 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
4947 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
4948 #define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4949 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4950 #define check_pow_604 check_pow_nocheck
4951
4952 static void init_proc_604 (CPUPPCState *env)
4953 {
4954 gen_spr_ne_601(env);
4955 gen_spr_604(env);
4956 /* Time base */
4957 gen_tbl(env);
4958 /* Hardware implementation registers */
4959 /* XXX : not implemented */
4960 spr_register(env, SPR_HID0, "HID0",
4961 SPR_NOACCESS, SPR_NOACCESS,
4962 &spr_read_generic, &spr_write_generic,
4963 0x00000000);
4964 /* Memory management */
4965 gen_low_BATs(env);
4966 init_excp_604(env);
4967 env->dcache_line_size = 32;
4968 env->icache_line_size = 32;
4969 /* Allocate hardware IRQ controller */
4970 ppc6xx_irq_init(env);
4971 }
4972
4973 /* PowerPC 604E */
4974 #define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4975 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4976 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4977 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4978 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4979 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4980 PPC_SEGMENT | PPC_EXTERN)
4981 #define POWERPC_INSNS2_604E (PPC_NONE)
4982 #define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4983 #define POWERPC_MMU_604E (POWERPC_MMU_32B)
4984 #define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4985 #define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4986 #define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4987 #define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4988 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4989 #define check_pow_604E check_pow_nocheck
4990
4991 static void init_proc_604E (CPUPPCState *env)
4992 {
4993 gen_spr_ne_601(env);
4994 gen_spr_604(env);
4995 /* XXX : not implemented */
4996 spr_register(env, SPR_MMCR1, "MMCR1",
4997 SPR_NOACCESS, SPR_NOACCESS,
4998 &spr_read_generic, &spr_write_generic,
4999 0x00000000);
5000 /* XXX : not implemented */
5001 spr_register(env, SPR_PMC3, "PMC3",
5002 SPR_NOACCESS, SPR_NOACCESS,
5003 &spr_read_generic, &spr_write_generic,
5004 0x00000000);
5005 /* XXX : not implemented */
5006 spr_register(env, SPR_PMC4, "PMC4",
5007 SPR_NOACCESS, SPR_NOACCESS,
5008 &spr_read_generic, &spr_write_generic,
5009 0x00000000);
5010 /* Time base */
5011 gen_tbl(env);
5012 /* Hardware implementation registers */
5013 /* XXX : not implemented */
5014 spr_register(env, SPR_HID0, "HID0",
5015 SPR_NOACCESS, SPR_NOACCESS,
5016 &spr_read_generic, &spr_write_generic,
5017 0x00000000);
5018 /* XXX : not implemented */
5019 spr_register(env, SPR_HID1, "HID1",
5020 SPR_NOACCESS, SPR_NOACCESS,
5021 &spr_read_generic, &spr_write_generic,
5022 0x00000000);
5023 /* Memory management */
5024 gen_low_BATs(env);
5025 init_excp_604(env);
5026 env->dcache_line_size = 32;
5027 env->icache_line_size = 32;
5028 /* Allocate hardware IRQ controller */
5029 ppc6xx_irq_init(env);
5030 }
5031
5032 /* PowerPC 740 */
5033 #define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5034 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5035 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5036 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5037 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5038 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5039 PPC_SEGMENT | PPC_EXTERN)
5040 #define POWERPC_INSNS2_740 (PPC_NONE)
5041 #define POWERPC_MSRM_740 (0x000000000005FF77ULL)
5042 #define POWERPC_MMU_740 (POWERPC_MMU_32B)
5043 #define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
5044 #define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
5045 #define POWERPC_BFDM_740 (bfd_mach_ppc_750)
5046 #define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5047 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5048 #define check_pow_740 check_pow_hid0
5049
5050 static void init_proc_740 (CPUPPCState *env)
5051 {
5052 gen_spr_ne_601(env);
5053 gen_spr_7xx(env);
5054 /* Time base */
5055 gen_tbl(env);
5056 /* Thermal management */
5057 gen_spr_thrm(env);
5058 /* Hardware implementation registers */
5059 /* XXX : not implemented */
5060 spr_register(env, SPR_HID0, "HID0",
5061 SPR_NOACCESS, SPR_NOACCESS,
5062 &spr_read_generic, &spr_write_generic,
5063 0x00000000);
5064 /* XXX : not implemented */
5065 spr_register(env, SPR_HID1, "HID1",
5066 SPR_NOACCESS, SPR_NOACCESS,
5067 &spr_read_generic, &spr_write_generic,
5068 0x00000000);
5069 /* Memory management */
5070 gen_low_BATs(env);
5071 init_excp_7x0(env);
5072 env->dcache_line_size = 32;
5073 env->icache_line_size = 32;
5074 /* Allocate hardware IRQ controller */
5075 ppc6xx_irq_init(env);
5076 }
5077
5078 /* PowerPC 750 */
5079 #define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5080 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5081 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5082 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5083 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5084 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5085 PPC_SEGMENT | PPC_EXTERN)
5086 #define POWERPC_INSNS2_750 (PPC_NONE)
5087 #define POWERPC_MSRM_750 (0x000000000005FF77ULL)
5088 #define POWERPC_MMU_750 (POWERPC_MMU_32B)
5089 #define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
5090 #define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
5091 #define POWERPC_BFDM_750 (bfd_mach_ppc_750)
5092 #define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5093 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5094 #define check_pow_750 check_pow_hid0
5095
5096 static void init_proc_750 (CPUPPCState *env)
5097 {
5098 gen_spr_ne_601(env);
5099 gen_spr_7xx(env);
5100 /* XXX : not implemented */
5101 spr_register(env, SPR_L2CR, "L2CR",
5102 SPR_NOACCESS, SPR_NOACCESS,
5103 &spr_read_generic, &spr_write_generic,
5104 0x00000000);
5105 /* Time base */
5106 gen_tbl(env);
5107 /* Thermal management */
5108 gen_spr_thrm(env);
5109 /* Hardware implementation registers */
5110 /* XXX : not implemented */
5111 spr_register(env, SPR_HID0, "HID0",
5112 SPR_NOACCESS, SPR_NOACCESS,
5113 &spr_read_generic, &spr_write_generic,
5114 0x00000000);
5115 /* XXX : not implemented */
5116 spr_register(env, SPR_HID1, "HID1",
5117 SPR_NOACCESS, SPR_NOACCESS,
5118 &spr_read_generic, &spr_write_generic,
5119 0x00000000);
5120 /* Memory management */
5121 gen_low_BATs(env);
5122 /* XXX: high BATs are also present but are known to be bugged on
5123 * die version 1.x
5124 */
5125 init_excp_7x0(env);
5126 env->dcache_line_size = 32;
5127 env->icache_line_size = 32;
5128 /* Allocate hardware IRQ controller */
5129 ppc6xx_irq_init(env);
5130 }
5131
5132 /* PowerPC 750 CL */
5133 /* XXX: not implemented:
5134 * cache lock instructions:
5135 * dcbz_l
5136 * floating point paired instructions
5137 * psq_lux
5138 * psq_lx
5139 * psq_stux
5140 * psq_stx
5141 * ps_abs
5142 * ps_add
5143 * ps_cmpo0
5144 * ps_cmpo1
5145 * ps_cmpu0
5146 * ps_cmpu1
5147 * ps_div
5148 * ps_madd
5149 * ps_madds0
5150 * ps_madds1
5151 * ps_merge00
5152 * ps_merge01
5153 * ps_merge10
5154 * ps_merge11
5155 * ps_mr
5156 * ps_msub
5157 * ps_mul
5158 * ps_muls0
5159 * ps_muls1
5160 * ps_nabs
5161 * ps_neg
5162 * ps_nmadd
5163 * ps_nmsub
5164 * ps_res
5165 * ps_rsqrte
5166 * ps_sel
5167 * ps_sub
5168 * ps_sum0
5169 * ps_sum1
5170 */
5171 #define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5172 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5173 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5174 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5175 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5176 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5177 PPC_SEGMENT | PPC_EXTERN)
5178 #define POWERPC_INSNS2_750cl (PPC_NONE)
5179 #define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
5180 #define POWERPC_MMU_750cl (POWERPC_MMU_32B)
5181 #define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
5182 #define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
5183 #define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
5184 #define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5185 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5186 #define check_pow_750cl check_pow_hid0
5187
5188 static void init_proc_750cl (CPUPPCState *env)
5189 {
5190 gen_spr_ne_601(env);
5191 gen_spr_7xx(env);
5192 /* XXX : not implemented */
5193 spr_register(env, SPR_L2CR, "L2CR",
5194 SPR_NOACCESS, SPR_NOACCESS,
5195 &spr_read_generic, &spr_write_generic,
5196 0x00000000);
5197 /* Time base */
5198 gen_tbl(env);
5199 /* Thermal management */
5200 /* Those registers are fake on 750CL */
5201 spr_register(env, SPR_THRM1, "THRM1",
5202 SPR_NOACCESS, SPR_NOACCESS,
5203 &spr_read_generic, &spr_write_generic,
5204 0x00000000);
5205 spr_register(env, SPR_THRM2, "THRM2",
5206 SPR_NOACCESS, SPR_NOACCESS,
5207 &spr_read_generic, &spr_write_generic,
5208 0x00000000);
5209 spr_register(env, SPR_THRM3, "THRM3",
5210 SPR_NOACCESS, SPR_NOACCESS,
5211 &spr_read_generic, &spr_write_generic,
5212 0x00000000);
5213 /* XXX: not implemented */
5214 spr_register(env, SPR_750_TDCL, "TDCL",
5215 SPR_NOACCESS, SPR_NOACCESS,
5216 &spr_read_generic, &spr_write_generic,
5217 0x00000000);
5218 spr_register(env, SPR_750_TDCH, "TDCH",
5219 SPR_NOACCESS, SPR_NOACCESS,
5220 &spr_read_generic, &spr_write_generic,
5221 0x00000000);
5222 /* DMA */
5223 /* XXX : not implemented */
5224 spr_register(env, SPR_750_WPAR, "WPAR",
5225 SPR_NOACCESS, SPR_NOACCESS,
5226 &spr_read_generic, &spr_write_generic,
5227 0x00000000);
5228 spr_register(env, SPR_750_DMAL, "DMAL",
5229 SPR_NOACCESS, SPR_NOACCESS,
5230 &spr_read_generic, &spr_write_generic,
5231 0x00000000);
5232 spr_register(env, SPR_750_DMAU, "DMAU",
5233 SPR_NOACCESS, SPR_NOACCESS,
5234 &spr_read_generic, &spr_write_generic,
5235 0x00000000);
5236 /* Hardware implementation registers */
5237 /* XXX : not implemented */
5238 spr_register(env, SPR_HID0, "HID0",
5239 SPR_NOACCESS, SPR_NOACCESS,
5240 &spr_read_generic, &spr_write_generic,
5241 0x00000000);
5242 /* XXX : not implemented */
5243 spr_register(env, SPR_HID1, "HID1",
5244 SPR_NOACCESS, SPR_NOACCESS,
5245 &spr_read_generic, &spr_write_generic,
5246 0x00000000);
5247 /* XXX : not implemented */
5248 spr_register(env, SPR_750CL_HID2, "HID2",
5249 SPR_NOACCESS, SPR_NOACCESS,
5250 &spr_read_generic, &spr_write_generic,
5251 0x00000000);
5252 /* XXX : not implemented */
5253 spr_register(env, SPR_750CL_HID4, "HID4",
5254 SPR_NOACCESS, SPR_NOACCESS,
5255 &spr_read_generic, &spr_write_generic,
5256 0x00000000);
5257 /* Quantization registers */
5258 /* XXX : not implemented */
5259 spr_register(env, SPR_750_GQR0, "GQR0",
5260 SPR_NOACCESS, SPR_NOACCESS,
5261 &spr_read_generic, &spr_write_generic,
5262 0x00000000);
5263 /* XXX : not implemented */
5264 spr_register(env, SPR_750_GQR1, "GQR1",
5265 SPR_NOACCESS, SPR_NOACCESS,
5266 &spr_read_generic, &spr_write_generic,
5267 0x00000000);
5268 /* XXX : not implemented */
5269 spr_register(env, SPR_750_GQR2, "GQR2",
5270 SPR_NOACCESS, SPR_NOACCESS,
5271 &spr_read_generic, &spr_write_generic,
5272 0x00000000);
5273 /* XXX : not implemented */
5274 spr_register(env, SPR_750_GQR3, "GQR3",
5275 SPR_NOACCESS, SPR_NOACCESS,
5276 &spr_read_generic, &spr_write_generic,
5277 0x00000000);
5278 /* XXX : not implemented */
5279 spr_register(env, SPR_750_GQR4, "GQR4",
5280 SPR_NOACCESS, SPR_NOACCESS,
5281 &spr_read_generic, &spr_write_generic,
5282 0x00000000);
5283 /* XXX : not implemented */
5284 spr_register(env, SPR_750_GQR5, "GQR5",
5285 SPR_NOACCESS, SPR_NOACCESS,
5286 &spr_read_generic, &spr_write_generic,
5287 0x00000000);
5288 /* XXX : not implemented */
5289 spr_register(env, SPR_750_GQR6, "GQR6",
5290 SPR_NOACCESS, SPR_NOACCESS,
5291 &spr_read_generic, &spr_write_generic,
5292 0x00000000);
5293 /* XXX : not implemented */
5294 spr_register(env, SPR_750_GQR7, "GQR7",
5295 SPR_NOACCESS, SPR_NOACCESS,
5296 &spr_read_generic, &spr_write_generic,
5297 0x00000000);
5298 /* Memory management */
5299 gen_low_BATs(env);
5300 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5301 gen_high_BATs(env);
5302 init_excp_750cl(env);
5303 env->dcache_line_size = 32;
5304 env->icache_line_size = 32;
5305 /* Allocate hardware IRQ controller */
5306 ppc6xx_irq_init(env);
5307 }
5308
5309 /* PowerPC 750CX */
5310 #define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5311 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5312 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5313 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5314 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5315 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5316 PPC_SEGMENT | PPC_EXTERN)
5317 #define POWERPC_INSNS2_750cx (PPC_NONE)
5318 #define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
5319 #define POWERPC_MMU_750cx (POWERPC_MMU_32B)
5320 #define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
5321 #define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
5322 #define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
5323 #define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5324 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5325 #define check_pow_750cx check_pow_hid0
5326
5327 static void init_proc_750cx (CPUPPCState *env)
5328 {
5329 gen_spr_ne_601(env);
5330 gen_spr_7xx(env);
5331 /* XXX : not implemented */
5332 spr_register(env, SPR_L2CR, "L2CR",
5333 SPR_NOACCESS, SPR_NOACCESS,
5334 &spr_read_generic, &spr_write_generic,
5335 0x00000000);
5336 /* Time base */
5337 gen_tbl(env);
5338 /* Thermal management */
5339 gen_spr_thrm(env);
5340 /* This register is not implemented but is present for compatibility */
5341 spr_register(env, SPR_SDA, "SDA",
5342 SPR_NOACCESS, SPR_NOACCESS,
5343 &spr_read_generic, &spr_write_generic,
5344 0x00000000);
5345 /* Hardware implementation registers */
5346 /* XXX : not implemented */
5347 spr_register(env, SPR_HID0, "HID0",
5348 SPR_NOACCESS, SPR_NOACCESS,
5349 &spr_read_generic, &spr_write_generic,
5350 0x00000000);
5351 /* XXX : not implemented */
5352 spr_register(env, SPR_HID1, "HID1",
5353 SPR_NOACCESS, SPR_NOACCESS,
5354 &spr_read_generic, &spr_write_generic,
5355 0x00000000);
5356 /* Memory management */
5357 gen_low_BATs(env);
5358 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5359 gen_high_BATs(env);
5360 init_excp_750cx(env);
5361 env->dcache_line_size = 32;
5362 env->icache_line_size = 32;
5363 /* Allocate hardware IRQ controller */
5364 ppc6xx_irq_init(env);
5365 }
5366
5367 /* PowerPC 750FX */
5368 #define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5369 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5370 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5371 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5372 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5373 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5374 PPC_SEGMENT | PPC_EXTERN)
5375 #define POWERPC_INSNS2_750fx (PPC_NONE)
5376 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
5377 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
5378 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
5379 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
5380 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
5381 #define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5382 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5383 #define check_pow_750fx check_pow_hid0
5384
5385 static void init_proc_750fx (CPUPPCState *env)
5386 {
5387 gen_spr_ne_601(env);
5388 gen_spr_7xx(env);
5389 /* XXX : not implemented */
5390 spr_register(env, SPR_L2CR, "L2CR",
5391 SPR_NOACCESS, SPR_NOACCESS,
5392 &spr_read_generic, &spr_write_generic,
5393 0x00000000);
5394 /* Time base */
5395 gen_tbl(env);
5396 /* Thermal management */
5397 gen_spr_thrm(env);
5398 /* XXX : not implemented */
5399 spr_register(env, SPR_750_THRM4, "THRM4",
5400 SPR_NOACCESS, SPR_NOACCESS,
5401 &spr_read_generic, &spr_write_generic,
5402 0x00000000);
5403 /* Hardware implementation registers */
5404 /* XXX : not implemented */
5405 spr_register(env, SPR_HID0, "HID0",
5406 SPR_NOACCESS, SPR_NOACCESS,
5407 &spr_read_generic, &spr_write_generic,
5408 0x00000000);
5409 /* XXX : not implemented */
5410 spr_register(env, SPR_HID1, "HID1",
5411 SPR_NOACCESS, SPR_NOACCESS,
5412 &spr_read_generic, &spr_write_generic,
5413 0x00000000);
5414 /* XXX : not implemented */
5415 spr_register(env, SPR_750FX_HID2, "HID2",
5416 SPR_NOACCESS, SPR_NOACCESS,
5417 &spr_read_generic, &spr_write_generic,
5418 0x00000000);
5419 /* Memory management */
5420 gen_low_BATs(env);
5421 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5422 gen_high_BATs(env);
5423 init_excp_7x0(env);
5424 env->dcache_line_size = 32;
5425 env->icache_line_size = 32;
5426 /* Allocate hardware IRQ controller */
5427 ppc6xx_irq_init(env);
5428 }
5429
5430 /* PowerPC 750GX */
5431 #define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5432 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5433 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5434 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5435 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5436 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5437 PPC_SEGMENT | PPC_EXTERN)
5438 #define POWERPC_INSNS2_750gx (PPC_NONE)
5439 #define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5440 #define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5441 #define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5442 #define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5443 #define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5444 #define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5445 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5446 #define check_pow_750gx check_pow_hid0
5447
5448 static void init_proc_750gx (CPUPPCState *env)
5449 {
5450 gen_spr_ne_601(env);
5451 gen_spr_7xx(env);
5452 /* XXX : not implemented (XXX: different from 750fx) */
5453 spr_register(env, SPR_L2CR, "L2CR",
5454 SPR_NOACCESS, SPR_NOACCESS,
5455 &spr_read_generic, &spr_write_generic,
5456 0x00000000);
5457 /* Time base */
5458 gen_tbl(env);
5459 /* Thermal management */
5460 gen_spr_thrm(env);
5461 /* XXX : not implemented */
5462 spr_register(env, SPR_750_THRM4, "THRM4",
5463 SPR_NOACCESS, SPR_NOACCESS,
5464 &spr_read_generic, &spr_write_generic,
5465 0x00000000);
5466 /* Hardware implementation registers */
5467 /* XXX : not implemented (XXX: different from 750fx) */
5468 spr_register(env, SPR_HID0, "HID0",
5469 SPR_NOACCESS, SPR_NOACCESS,
5470 &spr_read_generic, &spr_write_generic,
5471 0x00000000);
5472 /* XXX : not implemented */
5473 spr_register(env, SPR_HID1, "HID1",
5474 SPR_NOACCESS, SPR_NOACCESS,
5475 &spr_read_generic, &spr_write_generic,
5476 0x00000000);
5477 /* XXX : not implemented (XXX: different from 750fx) */
5478 spr_register(env, SPR_750FX_HID2, "HID2",
5479 SPR_NOACCESS, SPR_NOACCESS,
5480 &spr_read_generic, &spr_write_generic,
5481 0x00000000);
5482 /* Memory management */
5483 gen_low_BATs(env);
5484 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5485 gen_high_BATs(env);
5486 init_excp_7x0(env);
5487 env->dcache_line_size = 32;
5488 env->icache_line_size = 32;
5489 /* Allocate hardware IRQ controller */
5490 ppc6xx_irq_init(env);
5491 }
5492
5493 /* PowerPC 745 */
5494 #define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5495 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5496 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5497 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5498 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5499 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5500 PPC_SEGMENT | PPC_EXTERN)
5501 #define POWERPC_INSNS2_745 (PPC_NONE)
5502 #define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5503 #define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5504 #define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5505 #define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5506 #define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5507 #define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5508 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5509 #define check_pow_745 check_pow_hid0
5510
5511 static void init_proc_745 (CPUPPCState *env)
5512 {
5513 gen_spr_ne_601(env);
5514 gen_spr_7xx(env);
5515 gen_spr_G2_755(env);
5516 /* Time base */
5517 gen_tbl(env);
5518 /* Thermal management */
5519 gen_spr_thrm(env);
5520 /* Hardware implementation registers */
5521 /* XXX : not implemented */
5522 spr_register(env, SPR_HID0, "HID0",
5523 SPR_NOACCESS, SPR_NOACCESS,
5524 &spr_read_generic, &spr_write_generic,
5525 0x00000000);
5526 /* XXX : not implemented */
5527 spr_register(env, SPR_HID1, "HID1",
5528 SPR_NOACCESS, SPR_NOACCESS,
5529 &spr_read_generic, &spr_write_generic,
5530 0x00000000);
5531 /* XXX : not implemented */
5532 spr_register(env, SPR_HID2, "HID2",
5533 SPR_NOACCESS, SPR_NOACCESS,
5534 &spr_read_generic, &spr_write_generic,
5535 0x00000000);
5536 /* Memory management */
5537 gen_low_BATs(env);
5538 gen_high_BATs(env);
5539 gen_6xx_7xx_soft_tlb(env, 64, 2);
5540 init_excp_7x5(env);
5541 env->dcache_line_size = 32;
5542 env->icache_line_size = 32;
5543 /* Allocate hardware IRQ controller */
5544 ppc6xx_irq_init(env);
5545 }
5546
5547 /* PowerPC 755 */
5548 #define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5549 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5550 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5551 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5552 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5553 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5554 PPC_SEGMENT | PPC_EXTERN)
5555 #define POWERPC_INSNS2_755 (PPC_NONE)
5556 #define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5557 #define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5558 #define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5559 #define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5560 #define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5561 #define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5562 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5563 #define check_pow_755 check_pow_hid0
5564
5565 static void init_proc_755 (CPUPPCState *env)
5566 {
5567 gen_spr_ne_601(env);
5568 gen_spr_7xx(env);
5569 gen_spr_G2_755(env);
5570 /* Time base */
5571 gen_tbl(env);
5572 /* L2 cache control */
5573 /* XXX : not implemented */
5574 spr_register(env, SPR_L2CR, "L2CR",
5575 SPR_NOACCESS, SPR_NOACCESS,
5576 &spr_read_generic, &spr_write_generic,
5577 0x00000000);
5578 /* XXX : not implemented */
5579 spr_register(env, SPR_L2PMCR, "L2PMCR",
5580 SPR_NOACCESS, SPR_NOACCESS,
5581 &spr_read_generic, &spr_write_generic,
5582 0x00000000);
5583 /* Thermal management */
5584 gen_spr_thrm(env);
5585 /* Hardware implementation registers */
5586 /* XXX : not implemented */
5587 spr_register(env, SPR_HID0, "HID0",
5588 SPR_NOACCESS, SPR_NOACCESS,
5589 &spr_read_generic, &spr_write_generic,
5590 0x00000000);
5591 /* XXX : not implemented */
5592 spr_register(env, SPR_HID1, "HID1",
5593 SPR_NOACCESS, SPR_NOACCESS,
5594 &spr_read_generic, &spr_write_generic,
5595 0x00000000);
5596 /* XXX : not implemented */
5597 spr_register(env, SPR_HID2, "HID2",
5598 SPR_NOACCESS, SPR_NOACCESS,
5599 &spr_read_generic, &spr_write_generic,
5600 0x00000000);
5601 /* Memory management */
5602 gen_low_BATs(env);
5603 gen_high_BATs(env);
5604 gen_6xx_7xx_soft_tlb(env, 64, 2);
5605 init_excp_7x5(env);
5606 env->dcache_line_size = 32;
5607 env->icache_line_size = 32;
5608 /* Allocate hardware IRQ controller */
5609 ppc6xx_irq_init(env);
5610 }
5611
5612 /* PowerPC 7400 (aka G4) */
5613 #define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5614 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5615 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5616 PPC_FLOAT_STFIWX | \
5617 PPC_CACHE | PPC_CACHE_ICBI | \
5618 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5619 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5620 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5621 PPC_MEM_TLBIA | \
5622 PPC_SEGMENT | PPC_EXTERN | \
5623 PPC_ALTIVEC)
5624 #define POWERPC_INSNS2_7400 (PPC_NONE)
5625 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5626 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5627 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5628 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
5629 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
5630 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5631 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5632 POWERPC_FLAG_BUS_CLK)
5633 #define check_pow_7400 check_pow_hid0
5634
5635 static void init_proc_7400 (CPUPPCState *env)
5636 {
5637 gen_spr_ne_601(env);
5638 gen_spr_7xx(env);
5639 /* Time base */
5640 gen_tbl(env);
5641 /* 74xx specific SPR */
5642 gen_spr_74xx(env);
5643 /* XXX : not implemented */
5644 spr_register(env, SPR_UBAMR, "UBAMR",
5645 &spr_read_ureg, SPR_NOACCESS,
5646 &spr_read_ureg, SPR_NOACCESS,
5647 0x00000000);
5648 /* XXX: this seems not implemented on all revisions. */
5649 /* XXX : not implemented */
5650 spr_register(env, SPR_MSSCR1, "MSSCR1",
5651 SPR_NOACCESS, SPR_NOACCESS,
5652 &spr_read_generic, &spr_write_generic,
5653 0x00000000);
5654 /* Thermal management */
5655 gen_spr_thrm(env);
5656 /* Memory management */
5657 gen_low_BATs(env);
5658 init_excp_7400(env);
5659 env->dcache_line_size = 32;
5660 env->icache_line_size = 32;
5661 /* Allocate hardware IRQ controller */
5662 ppc6xx_irq_init(env);
5663 }
5664
5665 /* PowerPC 7410 (aka G4) */
5666 #define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5667 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5668 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5669 PPC_FLOAT_STFIWX | \
5670 PPC_CACHE | PPC_CACHE_ICBI | \
5671 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5672 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5673 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5674 PPC_MEM_TLBIA | \
5675 PPC_SEGMENT | PPC_EXTERN | \
5676 PPC_ALTIVEC)
5677 #define POWERPC_INSNS2_7410 (PPC_NONE)
5678 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5679 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5680 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5681 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
5682 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
5683 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5684 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5685 POWERPC_FLAG_BUS_CLK)
5686 #define check_pow_7410 check_pow_hid0
5687
5688 static void init_proc_7410 (CPUPPCState *env)
5689 {
5690 gen_spr_ne_601(env);
5691 gen_spr_7xx(env);
5692 /* Time base */
5693 gen_tbl(env);
5694 /* 74xx specific SPR */
5695 gen_spr_74xx(env);
5696 /* XXX : not implemented */
5697 spr_register(env, SPR_UBAMR, "UBAMR",
5698 &spr_read_ureg, SPR_NOACCESS,
5699 &spr_read_ureg, SPR_NOACCESS,
5700 0x00000000);
5701 /* Thermal management */
5702 gen_spr_thrm(env);
5703 /* L2PMCR */
5704 /* XXX : not implemented */
5705 spr_register(env, SPR_L2PMCR, "L2PMCR",
5706 SPR_NOACCESS, SPR_NOACCESS,
5707 &spr_read_generic, &spr_write_generic,
5708 0x00000000);
5709 /* LDSTDB */
5710 /* XXX : not implemented */
5711 spr_register(env, SPR_LDSTDB, "LDSTDB",
5712 SPR_NOACCESS, SPR_NOACCESS,
5713 &spr_read_generic, &spr_write_generic,
5714 0x00000000);
5715 /* Memory management */
5716 gen_low_BATs(env);
5717 init_excp_7400(env);
5718 env->dcache_line_size = 32;
5719 env->icache_line_size = 32;
5720 /* Allocate hardware IRQ controller */
5721 ppc6xx_irq_init(env);
5722 }
5723
5724 /* PowerPC 7440 (aka G4) */
5725 #define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5726 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5727 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5728 PPC_FLOAT_STFIWX | \
5729 PPC_CACHE | PPC_CACHE_ICBI | \
5730 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5731 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5732 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5733 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5734 PPC_SEGMENT | PPC_EXTERN | \
5735 PPC_ALTIVEC)
5736 #define POWERPC_INSNS2_7440 (PPC_NONE)
5737 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5738 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5739 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5740 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
5741 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
5742 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5743 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5744 POWERPC_FLAG_BUS_CLK)
5745 #define check_pow_7440 check_pow_hid0_74xx
5746
5747 __attribute__ (( unused ))
5748 static void init_proc_7440 (CPUPPCState *env)
5749 {
5750 gen_spr_ne_601(env);
5751 gen_spr_7xx(env);
5752 /* Time base */
5753 gen_tbl(env);
5754 /* 74xx specific SPR */
5755 gen_spr_74xx(env);
5756 /* XXX : not implemented */
5757 spr_register(env, SPR_UBAMR, "UBAMR",
5758 &spr_read_ureg, SPR_NOACCESS,
5759 &spr_read_ureg, SPR_NOACCESS,
5760 0x00000000);
5761 /* LDSTCR */
5762 /* XXX : not implemented */
5763 spr_register(env, SPR_LDSTCR, "LDSTCR",
5764 SPR_NOACCESS, SPR_NOACCESS,
5765 &spr_read_generic, &spr_write_generic,
5766 0x00000000);
5767 /* ICTRL */
5768 /* XXX : not implemented */
5769 spr_register(env, SPR_ICTRL, "ICTRL",
5770 SPR_NOACCESS, SPR_NOACCESS,
5771 &spr_read_generic, &spr_write_generic,
5772 0x00000000);
5773 /* MSSSR0 */
5774 /* XXX : not implemented */
5775 spr_register(env, SPR_MSSSR0, "MSSSR0",
5776 SPR_NOACCESS, SPR_NOACCESS,
5777 &spr_read_generic, &spr_write_generic,
5778 0x00000000);
5779 /* PMC */
5780 /* XXX : not implemented */
5781 spr_register(env, SPR_PMC5, "PMC5",
5782 SPR_NOACCESS, SPR_NOACCESS,
5783 &spr_read_generic, &spr_write_generic,
5784 0x00000000);
5785 /* XXX : not implemented */
5786 spr_register(env, SPR_UPMC5, "UPMC5",
5787 &spr_read_ureg, SPR_NOACCESS,
5788 &spr_read_ureg, SPR_NOACCESS,
5789 0x00000000);
5790 /* XXX : not implemented */
5791 spr_register(env, SPR_PMC6, "PMC6",
5792 SPR_NOACCESS, SPR_NOACCESS,
5793 &spr_read_generic, &spr_write_generic,
5794 0x00000000);
5795 /* XXX : not implemented */
5796 spr_register(env, SPR_UPMC6, "UPMC6",
5797 &spr_read_ureg, SPR_NOACCESS,
5798 &spr_read_ureg, SPR_NOACCESS,
5799 0x00000000);
5800 /* Memory management */
5801 gen_low_BATs(env);
5802 gen_74xx_soft_tlb(env, 128, 2);
5803 init_excp_7450(env);
5804 env->dcache_line_size = 32;
5805 env->icache_line_size = 32;
5806 /* Allocate hardware IRQ controller */
5807 ppc6xx_irq_init(env);
5808 }
5809
5810 /* PowerPC 7450 (aka G4) */
5811 #define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5812 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5813 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5814 PPC_FLOAT_STFIWX | \
5815 PPC_CACHE | PPC_CACHE_ICBI | \
5816 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5817 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5818 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5819 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5820 PPC_SEGMENT | PPC_EXTERN | \
5821 PPC_ALTIVEC)
5822 #define POWERPC_INSNS2_7450 (PPC_NONE)
5823 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5824 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5825 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5826 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
5827 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
5828 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5829 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5830 POWERPC_FLAG_BUS_CLK)
5831 #define check_pow_7450 check_pow_hid0_74xx
5832
5833 __attribute__ (( unused ))
5834 static void init_proc_7450 (CPUPPCState *env)
5835 {
5836 gen_spr_ne_601(env);
5837 gen_spr_7xx(env);
5838 /* Time base */
5839 gen_tbl(env);
5840 /* 74xx specific SPR */
5841 gen_spr_74xx(env);
5842 /* Level 3 cache control */
5843 gen_l3_ctrl(env);
5844 /* L3ITCR1 */
5845 /* XXX : not implemented */
5846 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5847 SPR_NOACCESS, SPR_NOACCESS,
5848 &spr_read_generic, &spr_write_generic,
5849 0x00000000);
5850 /* L3ITCR2 */
5851 /* XXX : not implemented */
5852 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5853 SPR_NOACCESS, SPR_NOACCESS,
5854 &spr_read_generic, &spr_write_generic,
5855 0x00000000);
5856 /* L3ITCR3 */
5857 /* XXX : not implemented */
5858 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5859 SPR_NOACCESS, SPR_NOACCESS,
5860 &spr_read_generic, &spr_write_generic,
5861 0x00000000);
5862 /* L3OHCR */
5863 /* XXX : not implemented */
5864 spr_register(env, SPR_L3OHCR, "L3OHCR",
5865 SPR_NOACCESS, SPR_NOACCESS,
5866 &spr_read_generic, &spr_write_generic,
5867 0x00000000);
5868 /* XXX : not implemented */
5869 spr_register(env, SPR_UBAMR, "UBAMR",
5870 &spr_read_ureg, SPR_NOACCESS,
5871 &spr_read_ureg, SPR_NOACCESS,
5872 0x00000000);
5873 /* LDSTCR */
5874 /* XXX : not implemented */
5875 spr_register(env, SPR_LDSTCR, "LDSTCR",
5876 SPR_NOACCESS, SPR_NOACCESS,
5877 &spr_read_generic, &spr_write_generic,
5878 0x00000000);
5879 /* ICTRL */
5880 /* XXX : not implemented */
5881 spr_register(env, SPR_ICTRL, "ICTRL",
5882 SPR_NOACCESS, SPR_NOACCESS,
5883 &spr_read_generic, &spr_write_generic,
5884 0x00000000);
5885 /* MSSSR0 */
5886 /* XXX : not implemented */
5887 spr_register(env, SPR_MSSSR0, "MSSSR0",
5888 SPR_NOACCESS, SPR_NOACCESS,
5889 &spr_read_generic, &spr_write_generic,
5890 0x00000000);
5891 /* PMC */
5892 /* XXX : not implemented */
5893 spr_register(env, SPR_PMC5, "PMC5",
5894 SPR_NOACCESS, SPR_NOACCESS,
5895 &spr_read_generic, &spr_write_generic,
5896 0x00000000);
5897 /* XXX : not implemented */
5898 spr_register(env, SPR_UPMC5, "UPMC5",
5899 &spr_read_ureg, SPR_NOACCESS,
5900 &spr_read_ureg, SPR_NOACCESS,
5901 0x00000000);
5902 /* XXX : not implemented */
5903 spr_register(env, SPR_PMC6, "PMC6",
5904 SPR_NOACCESS, SPR_NOACCESS,
5905 &spr_read_generic, &spr_write_generic,
5906 0x00000000);
5907 /* XXX : not implemented */
5908 spr_register(env, SPR_UPMC6, "UPMC6",
5909 &spr_read_ureg, SPR_NOACCESS,
5910 &spr_read_ureg, SPR_NOACCESS,
5911 0x00000000);
5912 /* Memory management */
5913 gen_low_BATs(env);
5914 gen_74xx_soft_tlb(env, 128, 2);
5915 init_excp_7450(env);
5916 env->dcache_line_size = 32;
5917 env->icache_line_size = 32;
5918 /* Allocate hardware IRQ controller */
5919 ppc6xx_irq_init(env);
5920 }
5921
5922 /* PowerPC 7445 (aka G4) */
5923 #define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5924 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5925 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5926 PPC_FLOAT_STFIWX | \
5927 PPC_CACHE | PPC_CACHE_ICBI | \
5928 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5929 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5930 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5931 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5932 PPC_SEGMENT | PPC_EXTERN | \
5933 PPC_ALTIVEC)
5934 #define POWERPC_INSNS2_7445 (PPC_NONE)
5935 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5936 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5937 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5938 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
5939 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
5940 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5941 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5942 POWERPC_FLAG_BUS_CLK)
5943 #define check_pow_7445 check_pow_hid0_74xx
5944
5945 __attribute__ (( unused ))
5946 static void init_proc_7445 (CPUPPCState *env)
5947 {
5948 gen_spr_ne_601(env);
5949 gen_spr_7xx(env);
5950 /* Time base */
5951 gen_tbl(env);
5952 /* 74xx specific SPR */
5953 gen_spr_74xx(env);
5954 /* LDSTCR */
5955 /* XXX : not implemented */
5956 spr_register(env, SPR_LDSTCR, "LDSTCR",
5957 SPR_NOACCESS, SPR_NOACCESS,
5958 &spr_read_generic, &spr_write_generic,
5959 0x00000000);
5960 /* ICTRL */
5961 /* XXX : not implemented */
5962 spr_register(env, SPR_ICTRL, "ICTRL",
5963 SPR_NOACCESS, SPR_NOACCESS,
5964 &spr_read_generic, &spr_write_generic,
5965 0x00000000);
5966 /* MSSSR0 */
5967 /* XXX : not implemented */
5968 spr_register(env, SPR_MSSSR0, "MSSSR0",
5969 SPR_NOACCESS, SPR_NOACCESS,
5970 &spr_read_generic, &spr_write_generic,
5971 0x00000000);
5972 /* PMC */
5973 /* XXX : not implemented */
5974 spr_register(env, SPR_PMC5, "PMC5",
5975 SPR_NOACCESS, SPR_NOACCESS,
5976 &spr_read_generic, &spr_write_generic,
5977 0x00000000);
5978 /* XXX : not implemented */
5979 spr_register(env, SPR_UPMC5, "UPMC5",
5980 &spr_read_ureg, SPR_NOACCESS,
5981 &spr_read_ureg, SPR_NOACCESS,
5982 0x00000000);
5983 /* XXX : not implemented */
5984 spr_register(env, SPR_PMC6, "PMC6",
5985 SPR_NOACCESS, SPR_NOACCESS,
5986 &spr_read_generic, &spr_write_generic,
5987 0x00000000);
5988 /* XXX : not implemented */
5989 spr_register(env, SPR_UPMC6, "UPMC6",
5990 &spr_read_ureg, SPR_NOACCESS,
5991 &spr_read_ureg, SPR_NOACCESS,
5992 0x00000000);
5993 /* SPRGs */
5994 spr_register(env, SPR_SPRG4, "SPRG4",
5995 SPR_NOACCESS, SPR_NOACCESS,
5996 &spr_read_generic, &spr_write_generic,
5997 0x00000000);
5998 spr_register(env, SPR_USPRG4, "USPRG4",
5999 &spr_read_ureg, SPR_NOACCESS,
6000 &spr_read_ureg, SPR_NOACCESS,
6001 0x00000000);
6002 spr_register(env, SPR_SPRG5, "SPRG5",
6003 SPR_NOACCESS, SPR_NOACCESS,
6004 &spr_read_generic, &spr_write_generic,
6005 0x00000000);
6006 spr_register(env, SPR_USPRG5, "USPRG5",
6007 &spr_read_ureg, SPR_NOACCESS,
6008 &spr_read_ureg, SPR_NOACCESS,
6009 0x00000000);
6010 spr_register(env, SPR_SPRG6, "SPRG6",
6011 SPR_NOACCESS, SPR_NOACCESS,
6012 &spr_read_generic, &spr_write_generic,
6013 0x00000000);
6014 spr_register(env, SPR_USPRG6, "USPRG6",
6015 &spr_read_ureg, SPR_NOACCESS,
6016 &spr_read_ureg, SPR_NOACCESS,
6017 0x00000000);
6018 spr_register(env, SPR_SPRG7, "SPRG7",
6019 SPR_NOACCESS, SPR_NOACCESS,
6020 &spr_read_generic, &spr_write_generic,
6021 0x00000000);
6022 spr_register(env, SPR_USPRG7, "USPRG7",
6023 &spr_read_ureg, SPR_NOACCESS,
6024 &spr_read_ureg, SPR_NOACCESS,
6025 0x00000000);
6026 /* Memory management */
6027 gen_low_BATs(env);
6028 gen_high_BATs(env);
6029 gen_74xx_soft_tlb(env, 128, 2);
6030 init_excp_7450(env);
6031 env->dcache_line_size = 32;
6032 env->icache_line_size = 32;
6033 /* Allocate hardware IRQ controller */
6034 ppc6xx_irq_init(env);
6035 }
6036
6037 /* PowerPC 7455 (aka G4) */
6038 #define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6039 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6040 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6041 PPC_FLOAT_STFIWX | \
6042 PPC_CACHE | PPC_CACHE_ICBI | \
6043 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
6044 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6045 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6046 PPC_MEM_TLBIA | PPC_74xx_TLB | \
6047 PPC_SEGMENT | PPC_EXTERN | \
6048 PPC_ALTIVEC)
6049 #define POWERPC_INSNS2_7455 (PPC_NONE)
6050 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
6051 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
6052 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
6053 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
6054 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
6055 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6056 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6057 POWERPC_FLAG_BUS_CLK)
6058 #define check_pow_7455 check_pow_hid0_74xx
6059
6060 __attribute__ (( unused ))
6061 static void init_proc_7455 (CPUPPCState *env)
6062 {
6063 gen_spr_ne_601(env);
6064 gen_spr_7xx(env);
6065 /* Time base */
6066 gen_tbl(env);
6067 /* 74xx specific SPR */
6068 gen_spr_74xx(env);
6069 /* Level 3 cache control */
6070 gen_l3_ctrl(env);
6071 /* LDSTCR */
6072 /* XXX : not implemented */
6073 spr_register(env, SPR_LDSTCR, "LDSTCR",
6074 SPR_NOACCESS, SPR_NOACCESS,
6075 &spr_read_generic, &spr_write_generic,
6076 0x00000000);
6077 /* ICTRL */
6078 /* XXX : not implemented */
6079 spr_register(env, SPR_ICTRL, "ICTRL",
6080 SPR_NOACCESS, SPR_NOACCESS,
6081 &spr_read_generic, &spr_write_generic,
6082 0x00000000);
6083 /* MSSSR0 */
6084 /* XXX : not implemented */
6085 spr_register(env, SPR_MSSSR0, "MSSSR0",
6086 SPR_NOACCESS, SPR_NOACCESS,
6087 &spr_read_generic, &spr_write_generic,
6088 0x00000000);
6089 /* PMC */
6090 /* XXX : not implemented */
6091 spr_register(env, SPR_PMC5, "PMC5",
6092 SPR_NOACCESS, SPR_NOACCESS,
6093 &spr_read_generic, &spr_write_generic,
6094 0x00000000);
6095 /* XXX : not implemented */
6096 spr_register(env, SPR_UPMC5, "UPMC5",
6097 &spr_read_ureg, SPR_NOACCESS,
6098 &spr_read_ureg, SPR_NOACCESS,
6099 0x00000000);
6100 /* XXX : not implemented */
6101 spr_register(env, SPR_PMC6, "PMC6",
6102 SPR_NOACCESS, SPR_NOACCESS,
6103 &spr_read_generic, &spr_write_generic,
6104 0x00000000);
6105 /* XXX : not implemented */
6106 spr_register(env, SPR_UPMC6, "UPMC6",
6107 &spr_read_ureg, SPR_NOACCESS,
6108 &spr_read_ureg, SPR_NOACCESS,
6109 0x00000000);
6110 /* SPRGs */
6111 spr_register(env, SPR_SPRG4, "SPRG4",
6112 SPR_NOACCESS, SPR_NOACCESS,
6113 &spr_read_generic, &spr_write_generic,
6114 0x00000000);
6115 spr_register(env, SPR_USPRG4, "USPRG4",
6116 &spr_read_ureg, SPR_NOACCESS,
6117 &spr_read_ureg, SPR_NOACCESS,
6118 0x00000000);
6119 spr_register(env, SPR_SPRG5, "SPRG5",
6120 SPR_NOACCESS, SPR_NOACCESS,
6121 &spr_read_generic, &spr_write_generic,
6122 0x00000000);
6123 spr_register(env, SPR_USPRG5, "USPRG5",
6124 &spr_read_ureg, SPR_NOACCESS,
6125 &spr_read_ureg, SPR_NOACCESS,
6126 0x00000000);
6127 spr_register(env, SPR_SPRG6, "SPRG6",
6128 SPR_NOACCESS, SPR_NOACCESS,
6129 &spr_read_generic, &spr_write_generic,
6130 0x00000000);
6131 spr_register(env, SPR_USPRG6, "USPRG6",
6132 &spr_read_ureg, SPR_NOACCESS,
6133 &spr_read_ureg, SPR_NOACCESS,
6134 0x00000000);
6135 spr_register(env, SPR_SPRG7, "SPRG7",
6136 SPR_NOACCESS, SPR_NOACCESS,
6137 &spr_read_generic, &spr_write_generic,
6138 0x00000000);
6139 spr_register(env, SPR_USPRG7, "USPRG7",
6140 &spr_read_ureg, SPR_NOACCESS,
6141 &spr_read_ureg, SPR_NOACCESS,
6142 0x00000000);
6143 /* Memory management */
6144 gen_low_BATs(env);
6145 gen_high_BATs(env);
6146 gen_74xx_soft_tlb(env, 128, 2);
6147 init_excp_7450(env);
6148 env->dcache_line_size = 32;
6149 env->icache_line_size = 32;
6150 /* Allocate hardware IRQ controller */
6151 ppc6xx_irq_init(env);
6152 }
6153
6154 /* PowerPC 7457 (aka G4) */
6155 #define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6156 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6157 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6158 PPC_FLOAT_STFIWX | \
6159 PPC_CACHE | PPC_CACHE_ICBI | \
6160 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
6161 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6162 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6163 PPC_MEM_TLBIA | PPC_74xx_TLB | \
6164 PPC_SEGMENT | PPC_EXTERN | \
6165 PPC_ALTIVEC)
6166 #define POWERPC_INSNS2_7457 (PPC_NONE)
6167 #define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
6168 #define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
6169 #define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
6170 #define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
6171 #define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
6172 #define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6173 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6174 POWERPC_FLAG_BUS_CLK)
6175 #define check_pow_7457 check_pow_hid0_74xx
6176
6177 __attribute__ (( unused ))
6178 static void init_proc_7457 (CPUPPCState *env)
6179 {
6180 gen_spr_ne_601(env);
6181 gen_spr_7xx(env);
6182 /* Time base */
6183 gen_tbl(env);
6184 /* 74xx specific SPR */
6185 gen_spr_74xx(env);
6186 /* Level 3 cache control */
6187 gen_l3_ctrl(env);
6188 /* L3ITCR1 */
6189 /* XXX : not implemented */
6190 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6191 SPR_NOACCESS, SPR_NOACCESS,
6192 &spr_read_generic, &spr_write_generic,
6193 0x00000000);
6194 /* L3ITCR2 */
6195 /* XXX : not implemented */
6196 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6197 SPR_NOACCESS, SPR_NOACCESS,
6198 &spr_read_generic, &spr_write_generic,
6199 0x00000000);
6200 /* L3ITCR3 */
6201 /* XXX : not implemented */
6202 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6203 SPR_NOACCESS, SPR_NOACCESS,
6204 &spr_read_generic, &spr_write_generic,
6205 0x00000000);
6206 /* L3OHCR */
6207 /* XXX : not implemented */
6208 spr_register(env, SPR_L3OHCR, "L3OHCR",
6209 SPR_NOACCESS, SPR_NOACCESS,
6210 &spr_read_generic, &spr_write_generic,
6211 0x00000000);
6212 /* LDSTCR */
6213 /* XXX : not implemented */
6214 spr_register(env, SPR_LDSTCR, "LDSTCR",
6215 SPR_NOACCESS, SPR_NOACCESS,
6216 &spr_read_generic, &spr_write_generic,
6217 0x00000000);
6218 /* ICTRL */
6219 /* XXX : not implemented */
6220 spr_register(env, SPR_ICTRL, "ICTRL",
6221 SPR_NOACCESS, SPR_NOACCESS,
6222 &spr_read_generic, &spr_write_generic,
6223 0x00000000);
6224 /* MSSSR0 */
6225 /* XXX : not implemented */
6226 spr_register(env, SPR_MSSSR0, "MSSSR0",
6227 SPR_NOACCESS, SPR_NOACCESS,
6228 &spr_read_generic, &spr_write_generic,
6229 0x00000000);
6230 /* PMC */
6231 /* XXX : not implemented */
6232 spr_register(env, SPR_PMC5, "PMC5",
6233 SPR_NOACCESS, SPR_NOACCESS,
6234 &spr_read_generic, &spr_write_generic,
6235 0x00000000);
6236 /* XXX : not implemented */
6237 spr_register(env, SPR_UPMC5, "UPMC5",
6238 &spr_read_ureg, SPR_NOACCESS,
6239 &spr_read_ureg, SPR_NOACCESS,
6240 0x00000000);
6241 /* XXX : not implemented */
6242 spr_register(env, SPR_PMC6, "PMC6",
6243 SPR_NOACCESS, SPR_NOACCESS,
6244 &spr_read_generic, &spr_write_generic,
6245 0x00000000);
6246 /* XXX : not implemented */
6247 spr_register(env, SPR_UPMC6, "UPMC6",
6248 &spr_read_ureg, SPR_NOACCESS,
6249 &spr_read_ureg, SPR_NOACCESS,
6250 0x00000000);
6251 /* SPRGs */
6252 spr_register(env, SPR_SPRG4, "SPRG4",
6253 SPR_NOACCESS, SPR_NOACCESS,
6254 &spr_read_generic, &spr_write_generic,
6255 0x00000000);
6256 spr_register(env, SPR_USPRG4, "USPRG4",
6257 &spr_read_ureg, SPR_NOACCESS,
6258 &spr_read_ureg, SPR_NOACCESS,
6259 0x00000000);
6260 spr_register(env, SPR_SPRG5, "SPRG5",
6261 SPR_NOACCESS, SPR_NOACCESS,
6262 &spr_read_generic, &spr_write_generic,
6263 0x00000000);
6264 spr_register(env, SPR_USPRG5, "USPRG5",
6265 &spr_read_ureg, SPR_NOACCESS,
6266 &spr_read_ureg, SPR_NOACCESS,
6267 0x00000000);
6268 spr_register(env, SPR_SPRG6, "SPRG6",
6269 SPR_NOACCESS, SPR_NOACCESS,
6270 &spr_read_generic, &spr_write_generic,
6271 0x00000000);
6272 spr_register(env, SPR_USPRG6, "USPRG6",
6273 &spr_read_ureg, SPR_NOACCESS,
6274 &spr_read_ureg, SPR_NOACCESS,
6275 0x00000000);
6276 spr_register(env, SPR_SPRG7, "SPRG7",
6277 SPR_NOACCESS, SPR_NOACCESS,
6278 &spr_read_generic, &spr_write_generic,
6279 0x00000000);
6280 spr_register(env, SPR_USPRG7, "USPRG7",
6281 &spr_read_ureg, SPR_NOACCESS,
6282 &spr_read_ureg, SPR_NOACCESS,
6283 0x00000000);
6284 /* Memory management */
6285 gen_low_BATs(env);
6286 gen_high_BATs(env);
6287 gen_74xx_soft_tlb(env, 128, 2);
6288 init_excp_7450(env);
6289 env->dcache_line_size = 32;
6290 env->icache_line_size = 32;
6291 /* Allocate hardware IRQ controller */
6292 ppc6xx_irq_init(env);
6293 }
6294
6295 #if defined (TARGET_PPC64)
6296 /* PowerPC 970 */
6297 #define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6298 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6299 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6300 PPC_FLOAT_STFIWX | \
6301 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6302 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6303 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6304 PPC_64B | PPC_ALTIVEC | \
6305 PPC_SEGMENT_64B | PPC_SLBI)
6306 #define POWERPC_INSNS2_970 (PPC_NONE)
6307 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
6308 #define POWERPC_MMU_970 (POWERPC_MMU_64B)
6309 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
6310 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
6311 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
6312 #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6313 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6314 POWERPC_FLAG_BUS_CLK)
6315
6316 #if defined(CONFIG_USER_ONLY)
6317 #define POWERPC970_HID5_INIT 0x00000080
6318 #else
6319 #define POWERPC970_HID5_INIT 0x00000000
6320 #endif
6321
6322 static int check_pow_970 (CPUPPCState *env)
6323 {
6324 if (env->spr[SPR_HID0] & 0x00600000)
6325 return 1;
6326
6327 return 0;
6328 }
6329
6330 static void init_proc_970 (CPUPPCState *env)
6331 {
6332 gen_spr_ne_601(env);
6333 gen_spr_7xx(env);
6334 /* Time base */
6335 gen_tbl(env);
6336 /* Hardware implementation registers */
6337 /* XXX : not implemented */
6338 spr_register(env, SPR_HID0, "HID0",
6339 SPR_NOACCESS, SPR_NOACCESS,
6340 &spr_read_generic, &spr_write_clear,
6341 0x60000000);
6342 /* XXX : not implemented */
6343 spr_register(env, SPR_HID1, "HID1",
6344 SPR_NOACCESS, SPR_NOACCESS,
6345 &spr_read_generic, &spr_write_generic,
6346 0x00000000);
6347 /* XXX : not implemented */
6348 spr_register(env, SPR_750FX_HID2, "HID2",
6349 SPR_NOACCESS, SPR_NOACCESS,
6350 &spr_read_generic, &spr_write_generic,
6351 0x00000000);
6352 /* XXX : not implemented */
6353 spr_register(env, SPR_970_HID5, "HID5",
6354 SPR_NOACCESS, SPR_NOACCESS,
6355 &spr_read_generic, &spr_write_generic,
6356 POWERPC970_HID5_INIT);
6357 /* XXX : not implemented */
6358 spr_register(env, SPR_L2CR, "L2CR",
6359 SPR_NOACCESS, SPR_NOACCESS,
6360 &spr_read_generic, &spr_write_generic,
6361 0x00000000);
6362 /* Memory management */
6363 /* XXX: not correct */
6364 gen_low_BATs(env);
6365 /* XXX : not implemented */
6366 spr_register(env, SPR_MMUCFG, "MMUCFG",
6367 SPR_NOACCESS, SPR_NOACCESS,
6368 &spr_read_generic, SPR_NOACCESS,
6369 0x00000000); /* TOFIX */
6370 /* XXX : not implemented */
6371 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6372 SPR_NOACCESS, SPR_NOACCESS,
6373 &spr_read_generic, &spr_write_generic,
6374 0x00000000); /* TOFIX */
6375 spr_register(env, SPR_HIOR, "SPR_HIOR",
6376 SPR_NOACCESS, SPR_NOACCESS,
6377 &spr_read_hior, &spr_write_hior,
6378 0x00000000);
6379 #if !defined(CONFIG_USER_ONLY)
6380 env->slb_nr = 32;
6381 #endif
6382 init_excp_970(env);
6383 env->dcache_line_size = 128;
6384 env->icache_line_size = 128;
6385 /* Allocate hardware IRQ controller */
6386 ppc970_irq_init(env);
6387 /* Can't find information on what this should be on reset. This
6388 * value is the one used by 74xx processors. */
6389 vscr_init(env, 0x00010000);
6390 }
6391
6392 /* PowerPC 970FX (aka G5) */
6393 #define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6394 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6395 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6396 PPC_FLOAT_STFIWX | \
6397 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6398 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6399 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6400 PPC_64B | PPC_ALTIVEC | \
6401 PPC_SEGMENT_64B | PPC_SLBI)
6402 #define POWERPC_INSNS2_970FX (PPC_NONE)
6403 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
6404 #define POWERPC_MMU_970FX (POWERPC_MMU_64B)
6405 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
6406 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
6407 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
6408 #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6409 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6410 POWERPC_FLAG_BUS_CLK)
6411
6412 static int check_pow_970FX (CPUPPCState *env)
6413 {
6414 if (env->spr[SPR_HID0] & 0x00600000)
6415 return 1;
6416
6417 return 0;
6418 }
6419
6420 static void init_proc_970FX (CPUPPCState *env)
6421 {
6422 gen_spr_ne_601(env);
6423 gen_spr_7xx(env);
6424 /* Time base */
6425 gen_tbl(env);
6426 /* Hardware implementation registers */
6427 /* XXX : not implemented */
6428 spr_register(env, SPR_HID0, "HID0",
6429 SPR_NOACCESS, SPR_NOACCESS,
6430 &spr_read_generic, &spr_write_clear,
6431 0x60000000);
6432 /* XXX : not implemented */
6433 spr_register(env, SPR_HID1, "HID1",
6434 SPR_NOACCESS, SPR_NOACCESS,
6435 &spr_read_generic, &spr_write_generic,
6436 0x00000000);
6437 /* XXX : not implemented */
6438 spr_register(env, SPR_750FX_HID2, "HID2",
6439 SPR_NOACCESS, SPR_NOACCESS,
6440 &spr_read_generic, &spr_write_generic,
6441 0x00000000);
6442 /* XXX : not implemented */
6443 spr_register(env, SPR_970_HID5, "HID5",
6444 SPR_NOACCESS, SPR_NOACCESS,
6445 &spr_read_generic, &spr_write_generic,
6446 POWERPC970_HID5_INIT);
6447 /* XXX : not implemented */
6448 spr_register(env, SPR_L2CR, "L2CR",
6449 SPR_NOACCESS, SPR_NOACCESS,
6450 &spr_read_generic, &spr_write_generic,
6451 0x00000000);
6452 /* Memory management */
6453 /* XXX: not correct */
6454 gen_low_BATs(env);
6455 /* XXX : not implemented */
6456 spr_register(env, SPR_MMUCFG, "MMUCFG",
6457 SPR_NOACCESS, SPR_NOACCESS,
6458 &spr_read_generic, SPR_NOACCESS,
6459 0x00000000); /* TOFIX */
6460 /* XXX : not implemented */
6461 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6462 SPR_NOACCESS, SPR_NOACCESS,
6463 &spr_read_generic, &spr_write_generic,
6464 0x00000000); /* TOFIX */
6465 spr_register(env, SPR_HIOR, "SPR_HIOR",
6466 SPR_NOACCESS, SPR_NOACCESS,
6467 &spr_read_hior, &spr_write_hior,
6468 0x00000000);
6469 spr_register(env, SPR_CTRL, "SPR_CTRL",
6470 SPR_NOACCESS, SPR_NOACCESS,
6471 &spr_read_generic, &spr_write_generic,
6472 0x00000000);
6473 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6474 SPR_NOACCESS, SPR_NOACCESS,
6475 &spr_read_generic, &spr_write_generic,
6476 0x00000000);
6477 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6478 &spr_read_generic, &spr_write_generic,
6479 &spr_read_generic, &spr_write_generic,
6480 0x00000000);
6481 #if !defined(CONFIG_USER_ONLY)
6482 env->slb_nr = 64;
6483 #endif
6484 init_excp_970(env);
6485 env->dcache_line_size = 128;
6486 env->icache_line_size = 128;
6487 /* Allocate hardware IRQ controller */
6488 ppc970_irq_init(env);
6489 /* Can't find information on what this should be on reset. This
6490 * value is the one used by 74xx processors. */
6491 vscr_init(env, 0x00010000);
6492 }
6493
6494 /* PowerPC 970 GX */
6495 #define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6496 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6497 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6498 PPC_FLOAT_STFIWX | \
6499 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6500 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6501 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6502 PPC_64B | PPC_ALTIVEC | \
6503 PPC_SEGMENT_64B | PPC_SLBI)
6504 #define POWERPC_INSNS2_970GX (PPC_NONE)
6505 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
6506 #define POWERPC_MMU_970GX (POWERPC_MMU_64B)
6507 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6508 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
6509 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
6510 #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6511 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6512 POWERPC_FLAG_BUS_CLK)
6513
6514 static int check_pow_970GX (CPUPPCState *env)
6515 {
6516 if (env->spr[SPR_HID0] & 0x00600000)
6517 return 1;
6518
6519 return 0;
6520 }
6521
6522 static void init_proc_970GX (CPUPPCState *env)
6523 {
6524 gen_spr_ne_601(env);
6525 gen_spr_7xx(env);
6526 /* Time base */
6527 gen_tbl(env);
6528 /* Hardware implementation registers */
6529 /* XXX : not implemented */
6530 spr_register(env, SPR_HID0, "HID0",
6531 SPR_NOACCESS, SPR_NOACCESS,
6532 &spr_read_generic, &spr_write_clear,
6533 0x60000000);
6534 /* XXX : not implemented */
6535 spr_register(env, SPR_HID1, "HID1",
6536 SPR_NOACCESS, SPR_NOACCESS,
6537 &spr_read_generic, &spr_write_generic,
6538 0x00000000);
6539 /* XXX : not implemented */
6540 spr_register(env, SPR_750FX_HID2, "HID2",
6541 SPR_NOACCESS, SPR_NOACCESS,
6542 &spr_read_generic, &spr_write_generic,
6543 0x00000000);
6544 /* XXX : not implemented */
6545 spr_register(env, SPR_970_HID5, "HID5",
6546 SPR_NOACCESS, SPR_NOACCESS,
6547 &spr_read_generic, &spr_write_generic,
6548 POWERPC970_HID5_INIT);
6549 /* XXX : not implemented */
6550 spr_register(env, SPR_L2CR, "L2CR",
6551 SPR_NOACCESS, SPR_NOACCESS,
6552 &spr_read_generic, &spr_write_generic,
6553 0x00000000);
6554 /* Memory management */
6555 /* XXX: not correct */
6556 gen_low_BATs(env);
6557 /* XXX : not implemented */
6558 spr_register(env, SPR_MMUCFG, "MMUCFG",
6559 SPR_NOACCESS, SPR_NOACCESS,
6560 &spr_read_generic, SPR_NOACCESS,
6561 0x00000000); /* TOFIX */
6562 /* XXX : not implemented */
6563 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6564 SPR_NOACCESS, SPR_NOACCESS,
6565 &spr_read_generic, &spr_write_generic,
6566 0x00000000); /* TOFIX */
6567 spr_register(env, SPR_HIOR, "SPR_HIOR",
6568 SPR_NOACCESS, SPR_NOACCESS,
6569 &spr_read_hior, &spr_write_hior,
6570 0x00000000);
6571 #if !defined(CONFIG_USER_ONLY)
6572 env->slb_nr = 32;
6573 #endif
6574 init_excp_970(env);
6575 env->dcache_line_size = 128;
6576 env->icache_line_size = 128;
6577 /* Allocate hardware IRQ controller */
6578 ppc970_irq_init(env);
6579 /* Can't find information on what this should be on reset. This
6580 * value is the one used by 74xx processors. */
6581 vscr_init(env, 0x00010000);
6582 }
6583
6584 /* PowerPC 970 MP */
6585 #define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6586 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6587 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6588 PPC_FLOAT_STFIWX | \
6589 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6590 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6591 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6592 PPC_64B | PPC_ALTIVEC | \
6593 PPC_SEGMENT_64B | PPC_SLBI)
6594 #define POWERPC_INSNS2_970MP (PPC_NONE)
6595 #define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6596 #define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6597 #define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6598 #define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6599 #define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6600 #define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6601 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6602 POWERPC_FLAG_BUS_CLK)
6603
6604 static int check_pow_970MP (CPUPPCState *env)
6605 {
6606 if (env->spr[SPR_HID0] & 0x01C00000)
6607 return 1;
6608
6609 return 0;
6610 }
6611
6612 static void init_proc_970MP (CPUPPCState *env)
6613 {
6614 gen_spr_ne_601(env);
6615 gen_spr_7xx(env);
6616 /* Time base */
6617 gen_tbl(env);
6618 /* Hardware implementation registers */
6619 /* XXX : not implemented */
6620 spr_register(env, SPR_HID0, "HID0",
6621 SPR_NOACCESS, SPR_NOACCESS,
6622 &spr_read_generic, &spr_write_clear,
6623 0x60000000);
6624 /* XXX : not implemented */
6625 spr_register(env, SPR_HID1, "HID1",
6626 SPR_NOACCESS, SPR_NOACCESS,
6627 &spr_read_generic, &spr_write_generic,
6628 0x00000000);
6629 /* XXX : not implemented */
6630 spr_register(env, SPR_750FX_HID2, "HID2",
6631 SPR_NOACCESS, SPR_NOACCESS,
6632 &spr_read_generic, &spr_write_generic,
6633 0x00000000);
6634 /* XXX : not implemented */
6635 spr_register(env, SPR_970_HID5, "HID5",
6636 SPR_NOACCESS, SPR_NOACCESS,
6637 &spr_read_generic, &spr_write_generic,
6638 POWERPC970_HID5_INIT);
6639 /* XXX : not implemented */
6640 spr_register(env, SPR_L2CR, "L2CR",
6641 SPR_NOACCESS, SPR_NOACCESS,
6642 &spr_read_generic, &spr_write_generic,
6643 0x00000000);
6644 /* Memory management */
6645 /* XXX: not correct */
6646 gen_low_BATs(env);
6647 /* XXX : not implemented */
6648 spr_register(env, SPR_MMUCFG, "MMUCFG",
6649 SPR_NOACCESS, SPR_NOACCESS,
6650 &spr_read_generic, SPR_NOACCESS,
6651 0x00000000); /* TOFIX */
6652 /* XXX : not implemented */
6653 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6654 SPR_NOACCESS, SPR_NOACCESS,
6655 &spr_read_generic, &spr_write_generic,
6656 0x00000000); /* TOFIX */
6657 spr_register(env, SPR_HIOR, "SPR_HIOR",
6658 SPR_NOACCESS, SPR_NOACCESS,
6659 &spr_read_hior, &spr_write_hior,
6660 0x00000000);
6661 #if !defined(CONFIG_USER_ONLY)
6662 env->slb_nr = 32;
6663 #endif
6664 init_excp_970(env);
6665 env->dcache_line_size = 128;
6666 env->icache_line_size = 128;
6667 /* Allocate hardware IRQ controller */
6668 ppc970_irq_init(env);
6669 /* Can't find information on what this should be on reset. This
6670 * value is the one used by 74xx processors. */
6671 vscr_init(env, 0x00010000);
6672 }
6673
6674 /* POWER7 */
6675 #define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6676 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6677 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6678 PPC_FLOAT_STFIWX | \
6679 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6680 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6681 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6682 PPC_64B | PPC_ALTIVEC | \
6683 PPC_SEGMENT_64B | PPC_SLBI | \
6684 PPC_POPCNTB | PPC_POPCNTWD)
6685 #define POWERPC_INSNS2_POWER7 (PPC2_VSX | PPC2_DFP | PPC2_DBRX)
6686 #define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
6687 #define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
6688 #define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
6689 #define POWERPC_INPUT_POWER7 (PPC_FLAGS_INPUT_POWER7)
6690 #define POWERPC_BFDM_POWER7 (bfd_mach_ppc64)
6691 #define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6692 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6693 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR)
6694 #define check_pow_POWER7 check_pow_nocheck
6695
6696 static void init_proc_POWER7 (CPUPPCState *env)
6697 {
6698 gen_spr_ne_601(env);
6699 gen_spr_7xx(env);
6700 /* Time base */
6701 gen_tbl(env);
6702 /* Processor identification */
6703 spr_register(env, SPR_PIR, "PIR",
6704 SPR_NOACCESS, SPR_NOACCESS,
6705 &spr_read_generic, &spr_write_pir,
6706 0x00000000);
6707 #if !defined(CONFIG_USER_ONLY)
6708 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6709 spr_register(env, SPR_PURR, "PURR",
6710 &spr_read_purr, SPR_NOACCESS,
6711 &spr_read_purr, SPR_NOACCESS,
6712 0x00000000);
6713 spr_register(env, SPR_SPURR, "SPURR",
6714 &spr_read_purr, SPR_NOACCESS,
6715 &spr_read_purr, SPR_NOACCESS,
6716 0x00000000);
6717 spr_register(env, SPR_CFAR, "SPR_CFAR",
6718 SPR_NOACCESS, SPR_NOACCESS,
6719 &spr_read_cfar, &spr_write_cfar,
6720 0x00000000);
6721 spr_register(env, SPR_DSCR, "SPR_DSCR",
6722 SPR_NOACCESS, SPR_NOACCESS,
6723 &spr_read_generic, &spr_write_generic,
6724 0x00000000);
6725 #endif /* !CONFIG_USER_ONLY */
6726 /* Memory management */
6727 /* XXX : not implemented */
6728 spr_register(env, SPR_MMUCFG, "MMUCFG",
6729 SPR_NOACCESS, SPR_NOACCESS,
6730 &spr_read_generic, SPR_NOACCESS,
6731 0x00000000); /* TOFIX */
6732 /* XXX : not implemented */
6733 spr_register(env, SPR_CTRL, "SPR_CTRLT",
6734 SPR_NOACCESS, SPR_NOACCESS,
6735 &spr_read_generic, &spr_write_generic,
6736 0x80800000);
6737 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
6738 SPR_NOACCESS, SPR_NOACCESS,
6739 &spr_read_generic, &spr_write_generic,
6740 0x80800000);
6741 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6742 &spr_read_generic, &spr_write_generic,
6743 &spr_read_generic, &spr_write_generic,
6744 0x00000000);
6745 #if !defined(CONFIG_USER_ONLY)
6746 env->slb_nr = 32;
6747 #endif
6748 init_excp_POWER7(env);
6749 env->dcache_line_size = 128;
6750 env->icache_line_size = 128;
6751 /* Allocate hardware IRQ controller */
6752 ppcPOWER7_irq_init(env);
6753 /* Can't find information on what this should be on reset. This
6754 * value is the one used by 74xx processors. */
6755 vscr_init(env, 0x00010000);
6756 }
6757
6758 /* PowerPC 620 */
6759 #define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6760 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6761 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6762 PPC_FLOAT_STFIWX | \
6763 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6764 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6765 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6766 PPC_SEGMENT | PPC_EXTERN | \
6767 PPC_64B | PPC_SLBI)
6768 #define POWERPC_INSNS2_620 (PPC_NONE)
6769 #define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6770 //#define POWERPC_MMU_620 (POWERPC_MMU_620)
6771 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
6772 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
6773 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
6774 #define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
6775 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
6776 #define check_pow_620 check_pow_nocheck /* Check this */
6777
6778 __attribute__ (( unused ))
6779 static void init_proc_620 (CPUPPCState *env)
6780 {
6781 gen_spr_ne_601(env);
6782 gen_spr_620(env);
6783 /* Time base */
6784 gen_tbl(env);
6785 /* Hardware implementation registers */
6786 /* XXX : not implemented */
6787 spr_register(env, SPR_HID0, "HID0",
6788 SPR_NOACCESS, SPR_NOACCESS,
6789 &spr_read_generic, &spr_write_generic,
6790 0x00000000);
6791 /* Memory management */
6792 gen_low_BATs(env);
6793 init_excp_620(env);
6794 env->dcache_line_size = 64;
6795 env->icache_line_size = 64;
6796 /* Allocate hardware IRQ controller */
6797 ppc6xx_irq_init(env);
6798 }
6799 #endif /* defined (TARGET_PPC64) */
6800
6801 /*****************************************************************************/
6802 /* PVR definitions for most known PowerPC */
6803 enum {
6804 /* PowerPC 401 family */
6805 /* Generic PowerPC 401 */
6806 #define CPU_POWERPC_401 CPU_POWERPC_401G2
6807 /* PowerPC 401 cores */
6808 CPU_POWERPC_401A1 = 0x00210000,
6809 CPU_POWERPC_401B2 = 0x00220000,
6810 #if 0
6811 CPU_POWERPC_401B3 = xxx,
6812 #endif
6813 CPU_POWERPC_401C2 = 0x00230000,
6814 CPU_POWERPC_401D2 = 0x00240000,
6815 CPU_POWERPC_401E2 = 0x00250000,
6816 CPU_POWERPC_401F2 = 0x00260000,
6817 CPU_POWERPC_401G2 = 0x00270000,
6818 /* PowerPC 401 microcontrolers */
6819 #if 0
6820 CPU_POWERPC_401GF = xxx,
6821 #endif
6822 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
6823 /* IBM Processor for Network Resources */
6824 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
6825 #if 0
6826 CPU_POWERPC_XIPCHIP = xxx,
6827 #endif
6828 /* PowerPC 403 family */
6829 /* PowerPC 403 microcontrollers */
6830 CPU_POWERPC_403GA = 0x00200011,
6831 CPU_POWERPC_403GB = 0x00200100,
6832 CPU_POWERPC_403GC = 0x00200200,
6833 CPU_POWERPC_403GCX = 0x00201400,
6834 #if 0
6835 CPU_POWERPC_403GP = xxx,
6836 #endif
6837 /* PowerPC 405 family */
6838 /* PowerPC 405 cores */
6839 #if 0
6840 CPU_POWERPC_405A3 = xxx,
6841 #endif
6842 #if 0
6843 CPU_POWERPC_405A4 = xxx,
6844 #endif
6845 #if 0
6846 CPU_POWERPC_405B3 = xxx,
6847 #endif
6848 #if 0
6849 CPU_POWERPC_405B4 = xxx,
6850 #endif
6851 #if 0
6852 CPU_POWERPC_405C3 = xxx,
6853 #endif
6854 #if 0
6855 CPU_POWERPC_405C4 = xxx,
6856 #endif
6857 CPU_POWERPC_405D2 = 0x20010000,
6858 #if 0
6859 CPU_POWERPC_405D3 = xxx,
6860 #endif
6861 CPU_POWERPC_405D4 = 0x41810000,
6862 #if 0
6863 CPU_POWERPC_405D5 = xxx,
6864 #endif
6865 #if 0
6866 CPU_POWERPC_405E4 = xxx,
6867 #endif
6868 #if 0
6869 CPU_POWERPC_405F4 = xxx,
6870 #endif
6871 #if 0
6872 CPU_POWERPC_405F5 = xxx,
6873 #endif
6874 #if 0
6875 CPU_POWERPC_405F6 = xxx,
6876 #endif
6877 /* PowerPC 405 microcontrolers */
6878 /* XXX: missing 0x200108a0 */
6879 CPU_POWERPC_405CRa = 0x40110041,
6880 CPU_POWERPC_405CRb = 0x401100C5,
6881 CPU_POWERPC_405CRc = 0x40110145,
6882 CPU_POWERPC_405EP = 0x51210950,
6883 #if 0
6884 CPU_POWERPC_405EXr = xxx,
6885 #endif
6886 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
6887 #if 0
6888 CPU_POWERPC_405FX = xxx,
6889 #endif
6890 CPU_POWERPC_405GPa = 0x40110000,
6891 CPU_POWERPC_405GPb = 0x40110040,
6892 CPU_POWERPC_405GPc = 0x40110082,
6893 CPU_POWERPC_405GPd = 0x401100C4,
6894 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6895 CPU_POWERPC_405GPR = 0x50910951,
6896 #if 0
6897 CPU_POWERPC_405H = xxx,
6898 #endif
6899 #if 0
6900 CPU_POWERPC_405L = xxx,
6901 #endif
6902 CPU_POWERPC_405LP = 0x41F10000,
6903 #if 0
6904 CPU_POWERPC_405PM = xxx,
6905 #endif
6906 #if 0
6907 CPU_POWERPC_405PS = xxx,
6908 #endif
6909 #if 0
6910 CPU_POWERPC_405S = xxx,
6911 #endif
6912 /* IBM network processors */
6913 CPU_POWERPC_NPE405H = 0x414100C0,
6914 CPU_POWERPC_NPE405H2 = 0x41410140,
6915 CPU_POWERPC_NPE405L = 0x416100C0,
6916 CPU_POWERPC_NPE4GS3 = 0x40B10000,
6917 #if 0
6918 CPU_POWERPC_NPCxx1 = xxx,
6919 #endif
6920 #if 0
6921 CPU_POWERPC_NPR161 = xxx,
6922 #endif
6923 #if 0
6924 CPU_POWERPC_LC77700 = xxx,
6925 #endif
6926 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6927 #if 0
6928 CPU_POWERPC_STB01000 = xxx,
6929 #endif
6930 #if 0
6931 CPU_POWERPC_STB01010 = xxx,
6932 #endif
6933 #if 0
6934 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
6935 #endif
6936 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
6937 #if 0
6938 CPU_POWERPC_STB043 = xxx,
6939 #endif
6940 #if 0
6941 CPU_POWERPC_STB045 = xxx,
6942 #endif
6943 CPU_POWERPC_STB04 = 0x41810000,
6944 CPU_POWERPC_STB25 = 0x51510950,
6945 #if 0
6946 CPU_POWERPC_STB130 = xxx,
6947 #endif
6948 /* Xilinx cores */
6949 CPU_POWERPC_X2VP4 = 0x20010820,
6950 CPU_POWERPC_X2VP20 = 0x20010860,
6951 #if 0
6952 CPU_POWERPC_ZL10310 = xxx,
6953 #endif
6954 #if 0
6955 CPU_POWERPC_ZL10311 = xxx,
6956 #endif
6957 #if 0
6958 CPU_POWERPC_ZL10320 = xxx,
6959 #endif
6960 #if 0
6961 CPU_POWERPC_ZL10321 = xxx,
6962 #endif
6963 /* PowerPC 440 family */
6964 /* Generic PowerPC 440 */
6965 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
6966 /* PowerPC 440 cores */
6967 #if 0
6968 CPU_POWERPC_440A4 = xxx,
6969 #endif
6970 CPU_POWERPC_440_XILINX = 0x7ff21910,
6971 #if 0
6972 CPU_POWERPC_440A5 = xxx,
6973 #endif
6974 #if 0
6975 CPU_POWERPC_440B4 = xxx,
6976 #endif
6977 #if 0
6978 CPU_POWERPC_440F5 = xxx,
6979 #endif
6980 #if 0
6981 CPU_POWERPC_440G5 = xxx,
6982 #endif
6983 #if 0
6984 CPU_POWERPC_440H4 = xxx,
6985 #endif
6986 #if 0
6987 CPU_POWERPC_440H6 = xxx,
6988 #endif
6989 /* PowerPC 440 microcontrolers */
6990 CPU_POWERPC_440EPa = 0x42221850,
6991 CPU_POWERPC_440EPb = 0x422218D3,
6992 CPU_POWERPC_440GPb = 0x40120440,
6993 CPU_POWERPC_440GPc = 0x40120481,
6994 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
6995 CPU_POWERPC_440GRX = 0x200008D0,
6996 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
6997 CPU_POWERPC_440GXa = 0x51B21850,
6998 CPU_POWERPC_440GXb = 0x51B21851,
6999 CPU_POWERPC_440GXc = 0x51B21892,
7000 CPU_POWERPC_440GXf = 0x51B21894,
7001 #if 0
7002 CPU_POWERPC_440S = xxx,
7003 #endif
7004 CPU_POWERPC_440SP = 0x53221850,
7005 CPU_POWERPC_440SP2 = 0x53221891,
7006 CPU_POWERPC_440SPE = 0x53421890,
7007 /* PowerPC 460 family */
7008 #if 0
7009 /* Generic PowerPC 464 */
7010 #define CPU_POWERPC_464 CPU_POWERPC_464H90
7011 #endif
7012 /* PowerPC 464 microcontrolers */
7013 #if 0
7014 CPU_POWERPC_464H90 = xxx,
7015 #endif
7016 #if 0
7017 CPU_POWERPC_464H90FP = xxx,
7018 #endif
7019 /* Freescale embedded PowerPC cores */
7020 /* PowerPC MPC 5xx cores (aka RCPU) */
7021 CPU_POWERPC_MPC5xx = 0x00020020,
7022 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
7023 CPU_POWERPC_MPC8xx = 0x00500000,
7024 /* G2 cores (aka PowerQUICC-II) */
7025 CPU_POWERPC_G2 = 0x00810011,
7026 CPU_POWERPC_G2H4 = 0x80811010,
7027 CPU_POWERPC_G2gp = 0x80821010,
7028 CPU_POWERPC_G2ls = 0x90810010,
7029 CPU_POWERPC_MPC603 = 0x00810100,
7030 CPU_POWERPC_G2_HIP3 = 0x00810101,
7031 CPU_POWERPC_G2_HIP4 = 0x80811014,
7032 /* G2_LE core (aka PowerQUICC-II) */
7033 CPU_POWERPC_G2LE = 0x80820010,
7034 CPU_POWERPC_G2LEgp = 0x80822010,
7035 CPU_POWERPC_G2LEls = 0xA0822010,
7036 CPU_POWERPC_G2LEgp1 = 0x80822011,
7037 CPU_POWERPC_G2LEgp3 = 0x80822013,
7038 /* MPC52xx microcontrollers */
7039 /* XXX: MPC 5121 ? */
7040 #define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
7041 #define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
7042 #define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
7043 #define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
7044 #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
7045 #define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
7046 #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
7047 #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
7048 /* MPC82xx microcontrollers */
7049 #define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
7050 #define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
7051 #define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
7052 #define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
7053 #define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
7054 #define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
7055 #define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
7056 #define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
7057 #define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
7058 #define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
7059 #define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
7060 #define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
7061 #define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
7062 #define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
7063 #define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
7064 #define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
7065 #define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
7066 #define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
7067 #define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
7068 #define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
7069 #define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
7070 #define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
7071 #define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
7072 #define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
7073 #define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
7074 #define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
7075 #define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
7076 #define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
7077 #define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
7078 /* e200 family */
7079 /* e200 cores */
7080 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
7081 #if 0
7082 CPU_POWERPC_e200z0 = xxx,
7083 #endif
7084 #if 0
7085 CPU_POWERPC_e200z1 = xxx,
7086 #endif
7087 #if 0 /* ? */
7088 CPU_POWERPC_e200z3 = 0x81120000,
7089 #endif
7090 CPU_POWERPC_e200z5 = 0x81000000,
7091 CPU_POWERPC_e200z6 = 0x81120000,
7092 /* MPC55xx microcontrollers */
7093 #define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
7094 #if 0
7095 #define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
7096 #define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
7097 #define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
7098 #define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
7099 #define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
7100 #define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
7101 #define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
7102 #define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
7103 #define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
7104 #define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
7105 #define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
7106 #define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
7107 #define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
7108 #define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
7109 #endif
7110 #if 0
7111 #define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
7112 #define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
7113 #endif
7114 #define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
7115 #define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
7116 #define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
7117 #define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
7118 #define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
7119 #define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
7120 /* e300 family */
7121 /* e300 cores */
7122 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
7123 CPU_POWERPC_e300c1 = 0x00830010,
7124 CPU_POWERPC_e300c2 = 0x00840010,
7125 CPU_POWERPC_e300c3 = 0x00850010,
7126 CPU_POWERPC_e300c4 = 0x00860010,
7127 /* MPC83xx microcontrollers */
7128 #define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
7129 #define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
7130 #define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
7131 #define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
7132 #define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
7133 #define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
7134 /* e500 family */
7135 /* e500 cores */
7136 #define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
7137 CPU_POWERPC_e500v1_v10 = 0x80200010,
7138 CPU_POWERPC_e500v1_v20 = 0x80200020,
7139 CPU_POWERPC_e500v2_v10 = 0x80210010,
7140 CPU_POWERPC_e500v2_v11 = 0x80210011,
7141 CPU_POWERPC_e500v2_v20 = 0x80210020,
7142 CPU_POWERPC_e500v2_v21 = 0x80210021,
7143 CPU_POWERPC_e500v2_v22 = 0x80210022,
7144 CPU_POWERPC_e500v2_v30 = 0x80210030,
7145 CPU_POWERPC_e500mc = 0x80230020,
7146 CPU_POWERPC_e5500 = 0x80240020,
7147 /* MPC85xx microcontrollers */
7148 #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
7149 #define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
7150 #define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
7151 #define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
7152 #define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
7153 #define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
7154 #define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
7155 #define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
7156 #define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
7157 #define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
7158 #define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
7159 #define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
7160 #define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
7161 #define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
7162 #define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
7163 #define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
7164 #define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
7165 #define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
7166 #define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
7167 #define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
7168 #define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
7169 #define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
7170 #define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
7171 #define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
7172 #define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
7173 #define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
7174 #define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
7175 #define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
7176 #define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
7177 #define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
7178 #define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
7179 #define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
7180 #define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
7181 #define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
7182 #define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
7183 #define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
7184 #define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
7185 #define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
7186 #define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
7187 #define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
7188 #define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
7189 #define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
7190 #define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
7191 #define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
7192 #define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
7193 #define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
7194 #define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
7195 #define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
7196 #define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
7197 #define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
7198 #define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
7199 #define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
7200 #define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
7201 /* e600 family */
7202 /* e600 cores */
7203 CPU_POWERPC_e600 = 0x80040010,
7204 /* MPC86xx microcontrollers */
7205 #define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
7206 #define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
7207 #define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
7208 /* PowerPC 6xx cores */
7209 CPU_POWERPC_601_v0 = 0x00010001,
7210 CPU_POWERPC_601_v1 = 0x00010001,
7211 CPU_POWERPC_601_v2 = 0x00010002,
7212 CPU_POWERPC_602 = 0x00050100,
7213 CPU_POWERPC_603 = 0x00030100,
7214 CPU_POWERPC_603E_v11 = 0x00060101,
7215 CPU_POWERPC_603E_v12 = 0x00060102,
7216 CPU_POWERPC_603E_v13 = 0x00060103,
7217 CPU_POWERPC_603E_v14 = 0x00060104,
7218 CPU_POWERPC_603E_v22 = 0x00060202,
7219 CPU_POWERPC_603E_v3 = 0x00060300,
7220 CPU_POWERPC_603E_v4 = 0x00060400,
7221 CPU_POWERPC_603E_v41 = 0x00060401,
7222 CPU_POWERPC_603E7t = 0x00071201,
7223 CPU_POWERPC_603E7v = 0x00070100,
7224 CPU_POWERPC_603E7v1 = 0x00070101,
7225 CPU_POWERPC_603E7v2 = 0x00070201,
7226 CPU_POWERPC_603E7 = 0x00070200,
7227 CPU_POWERPC_603P = 0x00070000,
7228 /* XXX: missing 0x00040303 (604) */
7229 CPU_POWERPC_604 = 0x00040103,
7230 /* XXX: missing 0x00091203 */
7231 /* XXX: missing 0x00092110 */
7232 /* XXX: missing 0x00092120 */
7233 CPU_POWERPC_604E_v10 = 0x00090100,
7234 CPU_POWERPC_604E_v22 = 0x00090202,
7235 CPU_POWERPC_604E_v24 = 0x00090204,
7236 /* XXX: missing 0x000a0100 */
7237 /* XXX: missing 0x00093102 */
7238 CPU_POWERPC_604R = 0x000a0101,
7239 #if 0
7240 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
7241 #endif
7242 /* PowerPC 740/750 cores (aka G3) */
7243 /* XXX: missing 0x00084202 */
7244 CPU_POWERPC_7x0_v10 = 0x00080100,
7245 CPU_POWERPC_7x0_v20 = 0x00080200,
7246 CPU_POWERPC_7x0_v21 = 0x00080201,
7247 CPU_POWERPC_7x0_v22 = 0x00080202,
7248 CPU_POWERPC_7x0_v30 = 0x00080300,
7249 CPU_POWERPC_7x0_v31 = 0x00080301,
7250 CPU_POWERPC_740E = 0x00080100,
7251 CPU_POWERPC_750E = 0x00080200,
7252 CPU_POWERPC_7x0P = 0x10080000,
7253 /* XXX: missing 0x00087010 (CL ?) */
7254 CPU_POWERPC_750CL_v10 = 0x00087200,
7255 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
7256 CPU_POWERPC_750CX_v10 = 0x00082100,
7257 CPU_POWERPC_750CX_v20 = 0x00082200,
7258 CPU_POWERPC_750CX_v21 = 0x00082201,
7259 CPU_POWERPC_750CX_v22 = 0x00082202,
7260 CPU_POWERPC_750CXE_v21 = 0x00082211,
7261 CPU_POWERPC_750CXE_v22 = 0x00082212,
7262 CPU_POWERPC_750CXE_v23 = 0x00082213,
7263 CPU_POWERPC_750CXE_v24 = 0x00082214,
7264 CPU_POWERPC_750CXE_v24b = 0x00083214,
7265 CPU_POWERPC_750CXE_v30 = 0x00082310,
7266 CPU_POWERPC_750CXE_v31 = 0x00082311,
7267 CPU_POWERPC_750CXE_v31b = 0x00083311,
7268 CPU_POWERPC_750CXR = 0x00083410,
7269 CPU_POWERPC_750FL = 0x70000203,
7270 CPU_POWERPC_750FX_v10 = 0x70000100,
7271 CPU_POWERPC_750FX_v20 = 0x70000200,
7272 CPU_POWERPC_750FX_v21 = 0x70000201,
7273 CPU_POWERPC_750FX_v22 = 0x70000202,
7274 CPU_POWERPC_750FX_v23 = 0x70000203,
7275 CPU_POWERPC_750GL = 0x70020102,
7276 CPU_POWERPC_750GX_v10 = 0x70020100,
7277 CPU_POWERPC_750GX_v11 = 0x70020101,
7278 CPU_POWERPC_750GX_v12 = 0x70020102,
7279 CPU_POWERPC_750L_v20 = 0x00088200,
7280 CPU_POWERPC_750L_v21 = 0x00088201,
7281 CPU_POWERPC_750L_v22 = 0x00088202,
7282 CPU_POWERPC_750L_v30 = 0x00088300,
7283 CPU_POWERPC_750L_v32 = 0x00088302,
7284 /* PowerPC 745/755 cores */
7285 CPU_POWERPC_7x5_v10 = 0x00083100,
7286 CPU_POWERPC_7x5_v11 = 0x00083101,
7287 CPU_POWERPC_7x5_v20 = 0x00083200,
7288 CPU_POWERPC_7x5_v21 = 0x00083201,
7289 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
7290 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
7291 CPU_POWERPC_7x5_v24 = 0x00083204,
7292 CPU_POWERPC_7x5_v25 = 0x00083205,
7293 CPU_POWERPC_7x5_v26 = 0x00083206,
7294 CPU_POWERPC_7x5_v27 = 0x00083207,
7295 CPU_POWERPC_7x5_v28 = 0x00083208,
7296 #if 0
7297 CPU_POWERPC_7x5P = xxx,
7298 #endif
7299 /* PowerPC 74xx cores (aka G4) */
7300 /* XXX: missing 0x000C1101 */
7301 CPU_POWERPC_7400_v10 = 0x000C0100,
7302 CPU_POWERPC_7400_v11 = 0x000C0101,
7303 CPU_POWERPC_7400_v20 = 0x000C0200,
7304 CPU_POWERPC_7400_v21 = 0x000C0201,
7305 CPU_POWERPC_7400_v22 = 0x000C0202,
7306 CPU_POWERPC_7400_v26 = 0x000C0206,
7307 CPU_POWERPC_7400_v27 = 0x000C0207,
7308 CPU_POWERPC_7400_v28 = 0x000C0208,
7309 CPU_POWERPC_7400_v29 = 0x000C0209,
7310 CPU_POWERPC_7410_v10 = 0x800C1100,
7311 CPU_POWERPC_7410_v11 = 0x800C1101,
7312 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
7313 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
7314 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
7315 CPU_POWERPC_7448_v10 = 0x80040100,
7316 CPU_POWERPC_7448_v11 = 0x80040101,
7317 CPU_POWERPC_7448_v20 = 0x80040200,
7318 CPU_POWERPC_7448_v21 = 0x80040201,
7319 CPU_POWERPC_7450_v10 = 0x80000100,
7320 CPU_POWERPC_7450_v11 = 0x80000101,
7321 CPU_POWERPC_7450_v12 = 0x80000102,
7322 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
7323 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
7324 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
7325 /* XXX: this entry might be a bug in some documentation */
7326 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
7327 CPU_POWERPC_74x5_v10 = 0x80010100,
7328 /* XXX: missing 0x80010200 */
7329 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
7330 CPU_POWERPC_74x5_v32 = 0x80010302,
7331 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
7332 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
7333 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
7334 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
7335 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
7336 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
7337 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
7338 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
7339 /* 64 bits PowerPC */
7340 #if defined(TARGET_PPC64)
7341 CPU_POWERPC_620 = 0x00140000,
7342 CPU_POWERPC_630 = 0x00400000,
7343 CPU_POWERPC_631 = 0x00410104,
7344 CPU_POWERPC_POWER4 = 0x00350000,
7345 CPU_POWERPC_POWER4P = 0x00380000,
7346 /* XXX: missing 0x003A0201 */
7347 CPU_POWERPC_POWER5 = 0x003A0203,
7348 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
7349 CPU_POWERPC_POWER5P = 0x003B0000,
7350 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
7351 CPU_POWERPC_POWER6 = 0x003E0000,
7352 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
7353 CPU_POWERPC_POWER6A = 0x0F000002,
7354 #define CPU_POWERPC_POWER7 CPU_POWERPC_POWER7_v20
7355 CPU_POWERPC_POWER7_v20 = 0x003F0200,
7356 CPU_POWERPC_POWER7_v21 = 0x003F0201,
7357 CPU_POWERPC_POWER7_v23 = 0x003F0203,
7358 CPU_POWERPC_970 = 0x00390202,
7359 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
7360 CPU_POWERPC_970FX_v10 = 0x00391100,
7361 CPU_POWERPC_970FX_v20 = 0x003C0200,
7362 CPU_POWERPC_970FX_v21 = 0x003C0201,
7363 CPU_POWERPC_970FX_v30 = 0x003C0300,
7364 CPU_POWERPC_970FX_v31 = 0x003C0301,
7365 CPU_POWERPC_970GX = 0x00450000,
7366 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
7367 CPU_POWERPC_970MP_v10 = 0x00440100,
7368 CPU_POWERPC_970MP_v11 = 0x00440101,
7369 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
7370 CPU_POWERPC_CELL_v10 = 0x00700100,
7371 CPU_POWERPC_CELL_v20 = 0x00700400,
7372 CPU_POWERPC_CELL_v30 = 0x00700500,
7373 CPU_POWERPC_CELL_v31 = 0x00700501,
7374 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
7375 CPU_POWERPC_RS64 = 0x00330000,
7376 CPU_POWERPC_RS64II = 0x00340000,
7377 CPU_POWERPC_RS64III = 0x00360000,
7378 CPU_POWERPC_RS64IV = 0x00370000,
7379 #endif /* defined(TARGET_PPC64) */
7380 /* Original POWER */
7381 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7382 * POWER2 (RIOS2) & RSC2 (P2SC) here
7383 */
7384 #if 0
7385 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
7386 #endif
7387 #if 0
7388 CPU_POWER2 = xxx, /* 0x40000 ? */
7389 #endif
7390 /* PA Semi core */
7391 CPU_POWERPC_PA6T = 0x00900000,
7392 };
7393
7394 /* System version register (used on MPC 8xxx) */
7395 enum {
7396 POWERPC_SVR_NONE = 0x00000000,
7397 #define POWERPC_SVR_52xx POWERPC_SVR_5200
7398 #define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7399 POWERPC_SVR_5200_v10 = 0x80110010,
7400 POWERPC_SVR_5200_v11 = 0x80110011,
7401 POWERPC_SVR_5200_v12 = 0x80110012,
7402 #define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7403 POWERPC_SVR_5200B_v20 = 0x80110020,
7404 POWERPC_SVR_5200B_v21 = 0x80110021,
7405 #define POWERPC_SVR_55xx POWERPC_SVR_5567
7406 #if 0
7407 POWERPC_SVR_5533 = xxx,
7408 #endif
7409 #if 0
7410 POWERPC_SVR_5534 = xxx,
7411 #endif
7412 #if 0
7413 POWERPC_SVR_5553 = xxx,
7414 #endif
7415 #if 0
7416 POWERPC_SVR_5554 = xxx,
7417 #endif
7418 #if 0
7419 POWERPC_SVR_5561 = xxx,
7420 #endif
7421 #if 0
7422 POWERPC_SVR_5565 = xxx,
7423 #endif
7424 #if 0
7425 POWERPC_SVR_5566 = xxx,
7426 #endif
7427 #if 0
7428 POWERPC_SVR_5567 = xxx,
7429 #endif
7430 #if 0
7431 POWERPC_SVR_8313 = xxx,
7432 #endif
7433 #if 0
7434 POWERPC_SVR_8313E = xxx,
7435 #endif
7436 #if 0
7437 POWERPC_SVR_8314 = xxx,
7438 #endif
7439 #if 0
7440 POWERPC_SVR_8314E = xxx,
7441 #endif
7442 #if 0
7443 POWERPC_SVR_8315 = xxx,
7444 #endif
7445 #if 0
7446 POWERPC_SVR_8315E = xxx,
7447 #endif
7448 #if 0
7449 POWERPC_SVR_8321 = xxx,
7450 #endif
7451 #if 0
7452 POWERPC_SVR_8321E = xxx,
7453 #endif
7454 #if 0
7455 POWERPC_SVR_8323 = xxx,
7456 #endif
7457 #if 0
7458 POWERPC_SVR_8323E = xxx,
7459 #endif
7460 POWERPC_SVR_8343 = 0x80570010,
7461 POWERPC_SVR_8343A = 0x80570030,
7462 POWERPC_SVR_8343E = 0x80560010,
7463 POWERPC_SVR_8343EA = 0x80560030,
7464 POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
7465 POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
7466 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7467 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
7468 POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
7469 POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
7470 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7471 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7472 POWERPC_SVR_8349 = 0x80510010,
7473 POWERPC_SVR_8349A = 0x80510030,
7474 POWERPC_SVR_8349E = 0x80500010,
7475 POWERPC_SVR_8349EA = 0x80500030,
7476 #if 0
7477 POWERPC_SVR_8358E = xxx,
7478 #endif
7479 #if 0
7480 POWERPC_SVR_8360E = xxx,
7481 #endif
7482 #define POWERPC_SVR_E500 0x40000000
7483 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7484 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7485 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7486 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7487 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7488 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7489 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7490 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7491 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7492 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7493 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7494 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7495 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7496 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7497 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7498 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7499 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7500 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7501 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7502 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7503 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7504 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7505 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7506 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7507 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7508 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7509 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7510 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7511 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7512 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7513 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7514 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7515 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7516 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7517 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7518 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7519 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7520 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7521 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7522 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7523 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7524 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7525 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7526 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7527 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7528 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7529 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7530 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7531 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7532 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7533 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7534 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7535 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7536 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7537 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7538 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
7539 #if 0
7540 POWERPC_SVR_8610 = xxx,
7541 #endif
7542 POWERPC_SVR_8641 = 0x80900021,
7543 POWERPC_SVR_8641D = 0x80900121,
7544 };
7545
7546 /*****************************************************************************/
7547 /* PowerPC CPU definitions */
7548 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
7549 { \
7550 .name = _name, \
7551 .pvr = _pvr, \
7552 .svr = _svr, \
7553 .insns_flags = glue(POWERPC_INSNS_,_type), \
7554 .insns_flags2 = glue(POWERPC_INSNS2_,_type), \
7555 .msr_mask = glue(POWERPC_MSRM_,_type), \
7556 .mmu_model = glue(POWERPC_MMU_,_type), \
7557 .excp_model = glue(POWERPC_EXCP_,_type), \
7558 .bus_model = glue(POWERPC_INPUT_,_type), \
7559 .bfd_mach = glue(POWERPC_BFDM_,_type), \
7560 .flags = glue(POWERPC_FLAG_,_type), \
7561 .init_proc = &glue(init_proc_,_type), \
7562 .check_pow = &glue(check_pow_,_type), \
7563 },
7564 #define POWERPC_DEF(_name, _pvr, _type) \
7565 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
7566
7567 static const ppc_def_t ppc_defs[] = {
7568 /* Embedded PowerPC */
7569 /* PowerPC 401 family */
7570 /* Generic PowerPC 401 */
7571 POWERPC_DEF("401", CPU_POWERPC_401, 401)
7572 /* PowerPC 401 cores */
7573 /* PowerPC 401A1 */
7574 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401)
7575 /* PowerPC 401B2 */
7576 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2)
7577 #if defined (TODO)
7578 /* PowerPC 401B3 */
7579 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3)
7580 #endif
7581 /* PowerPC 401C2 */
7582 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2)
7583 /* PowerPC 401D2 */
7584 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2)
7585 /* PowerPC 401E2 */
7586 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2)
7587 /* PowerPC 401F2 */
7588 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2)
7589 /* PowerPC 401G2 */
7590 /* XXX: to be checked */
7591 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2)
7592 /* PowerPC 401 microcontrolers */
7593 #if defined (TODO)
7594 /* PowerPC 401GF */
7595 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401)
7596 #endif
7597 /* IOP480 (401 microcontroler) */
7598 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480)
7599 /* IBM Processor for Network Resources */
7600 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401)
7601 #if defined (TODO)
7602 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401)
7603 #endif
7604 /* PowerPC 403 family */
7605 /* PowerPC 403 microcontrolers */
7606 /* PowerPC 403 GA */
7607 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403)
7608 /* PowerPC 403 GB */
7609 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403)
7610 /* PowerPC 403 GC */
7611 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403)
7612 /* PowerPC 403 GCX */
7613 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX)
7614 #if defined (TODO)
7615 /* PowerPC 403 GP */
7616 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403)
7617 #endif
7618 /* PowerPC 405 family */
7619 /* PowerPC 405 cores */
7620 #if defined (TODO)
7621 /* PowerPC 405 A3 */
7622 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405)
7623 #endif
7624 #if defined (TODO)
7625 /* PowerPC 405 A4 */
7626 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405)
7627 #endif
7628 #if defined (TODO)
7629 /* PowerPC 405 B3 */
7630 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405)
7631 #endif
7632 #if defined (TODO)
7633 /* PowerPC 405 B4 */
7634 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405)
7635 #endif
7636 #if defined (TODO)
7637 /* PowerPC 405 C3 */
7638 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405)
7639 #endif
7640 #if defined (TODO)
7641 /* PowerPC 405 C4 */
7642 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405)
7643 #endif
7644 /* PowerPC 405 D2 */
7645 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405)
7646 #if defined (TODO)
7647 /* PowerPC 405 D3 */
7648 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405)
7649 #endif
7650 /* PowerPC 405 D4 */
7651 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405)
7652 #if defined (TODO)
7653 /* PowerPC 405 D5 */
7654 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405)
7655 #endif
7656 #if defined (TODO)
7657 /* PowerPC 405 E4 */
7658 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405)
7659 #endif
7660 #if defined (TODO)
7661 /* PowerPC 405 F4 */
7662 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405)
7663 #endif
7664 #if defined (TODO)
7665 /* PowerPC 405 F5 */
7666 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405)
7667 #endif
7668 #if defined (TODO)
7669 /* PowerPC 405 F6 */
7670 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405)
7671 #endif
7672 /* PowerPC 405 microcontrolers */
7673 /* PowerPC 405 CRa */
7674 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405)
7675 /* PowerPC 405 CRb */
7676 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405)
7677 /* PowerPC 405 CRc */
7678 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405)
7679 /* PowerPC 405 EP */
7680 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405)
7681 #if defined(TODO)
7682 /* PowerPC 405 EXr */
7683 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405)
7684 #endif
7685 /* PowerPC 405 EZ */
7686 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405)
7687 #if defined(TODO)
7688 /* PowerPC 405 FX */
7689 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405)
7690 #endif
7691 /* PowerPC 405 GPa */
7692 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405)
7693 /* PowerPC 405 GPb */
7694 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405)
7695 /* PowerPC 405 GPc */
7696 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405)
7697 /* PowerPC 405 GPd */
7698 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405)
7699 /* PowerPC 405 GPe */
7700 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405)
7701 /* PowerPC 405 GPR */
7702 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405)
7703 #if defined(TODO)
7704 /* PowerPC 405 H */
7705 POWERPC_DEF("405H", CPU_POWERPC_405H, 405)
7706 #endif
7707 #if defined(TODO)
7708 /* PowerPC 405 L */
7709 POWERPC_DEF("405L", CPU_POWERPC_405L, 405)
7710 #endif
7711 /* PowerPC 405 LP */
7712 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405)
7713 #if defined(TODO)
7714 /* PowerPC 405 PM */
7715 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405)
7716 #endif
7717 #if defined(TODO)
7718 /* PowerPC 405 PS */
7719 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405)
7720 #endif
7721 #if defined(TODO)
7722 /* PowerPC 405 S */
7723 POWERPC_DEF("405S", CPU_POWERPC_405S, 405)
7724 #endif
7725 /* Npe405 H */
7726 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405)
7727 /* Npe405 H2 */
7728 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405)
7729 /* Npe405 L */
7730 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405)
7731 /* Npe4GS3 */
7732 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405)
7733 #if defined (TODO)
7734 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405)
7735 #endif
7736 #if defined (TODO)
7737 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405)
7738 #endif
7739 #if defined (TODO)
7740 /* PowerPC LC77700 (Sanyo) */
7741 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405)
7742 #endif
7743 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7744 #if defined (TODO)
7745 /* STB010000 */
7746 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2)
7747 #endif
7748 #if defined (TODO)
7749 /* STB01010 */
7750 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2)
7751 #endif
7752 #if defined (TODO)
7753 /* STB0210 */
7754 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3)
7755 #endif
7756 /* STB03xx */
7757 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405)
7758 #if defined (TODO)
7759 /* STB043x */
7760 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405)
7761 #endif
7762 #if defined (TODO)
7763 /* STB045x */
7764 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405)
7765 #endif
7766 /* STB04xx */
7767 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405)
7768 /* STB25xx */
7769 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405)
7770 #if defined (TODO)
7771 /* STB130 */
7772 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405)
7773 #endif
7774 /* Xilinx PowerPC 405 cores */
7775 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405)
7776 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405)
7777 #if defined (TODO)
7778 /* Zarlink ZL10310 */
7779 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405)
7780 #endif
7781 #if defined (TODO)
7782 /* Zarlink ZL10311 */
7783 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405)
7784 #endif
7785 #if defined (TODO)
7786 /* Zarlink ZL10320 */
7787 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405)
7788 #endif
7789 #if defined (TODO)
7790 /* Zarlink ZL10321 */
7791 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405)
7792 #endif
7793 /* PowerPC 440 family */
7794 #if defined(TODO_USER_ONLY)
7795 /* Generic PowerPC 440 */
7796 POWERPC_DEF("440", CPU_POWERPC_440, 440GP)
7797 #endif
7798 /* PowerPC 440 cores */
7799 #if defined (TODO)
7800 /* PowerPC 440 A4 */
7801 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4)
7802 #endif
7803 /* PowerPC 440 Xilinx 5 */
7804 POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5)
7805 #if defined (TODO)
7806 /* PowerPC 440 A5 */
7807 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5)
7808 #endif
7809 #if defined (TODO)
7810 /* PowerPC 440 B4 */
7811 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4)
7812 #endif
7813 #if defined (TODO)
7814 /* PowerPC 440 G4 */
7815 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4)
7816 #endif
7817 #if defined (TODO)
7818 /* PowerPC 440 F5 */
7819 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5)
7820 #endif
7821 #if defined (TODO)
7822 /* PowerPC 440 G5 */
7823 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5)
7824 #endif
7825 #if defined (TODO)
7826 /* PowerPC 440H4 */
7827 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4)
7828 #endif
7829 #if defined (TODO)
7830 /* PowerPC 440H6 */
7831 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5)
7832 #endif
7833 /* PowerPC 440 microcontrolers */
7834 /* PowerPC 440 EPa */
7835 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP)
7836 /* PowerPC 440 EPb */
7837 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP)
7838 /* PowerPC 440 EPX */
7839 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP)
7840 #if defined(TODO_USER_ONLY)
7841 /* PowerPC 440 GPb */
7842 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP)
7843 #endif
7844 #if defined(TODO_USER_ONLY)
7845 /* PowerPC 440 GPc */
7846 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP)
7847 #endif
7848 #if defined(TODO_USER_ONLY)
7849 /* PowerPC 440 GRa */
7850 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5)
7851 #endif
7852 #if defined(TODO_USER_ONLY)
7853 /* PowerPC 440 GRX */
7854 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5)
7855 #endif
7856 #if defined(TODO_USER_ONLY)
7857 /* PowerPC 440 GXa */
7858 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP)
7859 #endif
7860 #if defined(TODO_USER_ONLY)
7861 /* PowerPC 440 GXb */
7862 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP)
7863 #endif
7864 #if defined(TODO_USER_ONLY)
7865 /* PowerPC 440 GXc */
7866 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP)
7867 #endif
7868 #if defined(TODO_USER_ONLY)
7869 /* PowerPC 440 GXf */
7870 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP)
7871 #endif
7872 #if defined(TODO)
7873 /* PowerPC 440 S */
7874 POWERPC_DEF("440S", CPU_POWERPC_440S, 440)
7875 #endif
7876 #if defined(TODO_USER_ONLY)
7877 /* PowerPC 440 SP */
7878 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP)
7879 #endif
7880 #if defined(TODO_USER_ONLY)
7881 /* PowerPC 440 SP2 */
7882 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP)
7883 #endif
7884 #if defined(TODO_USER_ONLY)
7885 /* PowerPC 440 SPE */
7886 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP)
7887 #endif
7888 /* PowerPC 460 family */
7889 #if defined (TODO)
7890 /* Generic PowerPC 464 */
7891 POWERPC_DEF("464", CPU_POWERPC_464, 460)
7892 #endif
7893 /* PowerPC 464 microcontrolers */
7894 #if defined (TODO)
7895 /* PowerPC 464H90 */
7896 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460)
7897 #endif
7898 #if defined (TODO)
7899 /* PowerPC 464H90F */
7900 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F)
7901 #endif
7902 /* Freescale embedded PowerPC cores */
7903 /* MPC5xx family (aka RCPU) */
7904 #if defined(TODO_USER_ONLY)
7905 /* Generic MPC5xx core */
7906 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx)
7907 #endif
7908 /* MPC8xx family (aka PowerQUICC) */
7909 #if defined(TODO_USER_ONLY)
7910 /* Generic MPC8xx core */
7911 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx)
7912 #endif
7913 /* MPC82xx family (aka PowerQUICC-II) */
7914 /* Generic MPC52xx core */
7915 POWERPC_DEF_SVR("MPC52xx",
7916 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE)
7917 /* Generic MPC82xx core */
7918 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2)
7919 /* PowerPC G2 core */
7920 POWERPC_DEF("G2", CPU_POWERPC_G2, G2)
7921 /* PowerPC G2 H4 core */
7922 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2)
7923 /* PowerPC G2 GP core */
7924 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2)
7925 /* PowerPC G2 LS core */
7926 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2)
7927 /* PowerPC G2 HiP3 core */
7928 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2)
7929 /* PowerPC G2 HiP4 core */
7930 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2)
7931 /* PowerPC MPC603 core */
7932 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E)
7933 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
7934 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE)
7935 /* PowerPC G2LE GP core */
7936 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE)
7937 /* PowerPC G2LE LS core */
7938 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE)
7939 /* PowerPC G2LE GP1 core */
7940 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE)
7941 /* PowerPC G2LE GP3 core */
7942 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp3, G2LE)
7943 /* PowerPC MPC603 microcontrollers */
7944 /* MPC8240 */
7945 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E)
7946 /* PowerPC G2 microcontrollers */
7947 #if defined(TODO)
7948 /* MPC5121 */
7949 POWERPC_DEF_SVR("MPC5121",
7950 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE)
7951 #endif
7952 /* MPC5200 */
7953 POWERPC_DEF_SVR("MPC5200",
7954 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE)
7955 /* MPC5200 v1.0 */
7956 POWERPC_DEF_SVR("MPC5200_v10",
7957 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE)
7958 /* MPC5200 v1.1 */
7959 POWERPC_DEF_SVR("MPC5200_v11",
7960 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE)
7961 /* MPC5200 v1.2 */
7962 POWERPC_DEF_SVR("MPC5200_v12",
7963 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE)
7964 /* MPC5200B */
7965 POWERPC_DEF_SVR("MPC5200B",
7966 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE)
7967 /* MPC5200B v2.0 */
7968 POWERPC_DEF_SVR("MPC5200B_v20",
7969 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE)
7970 /* MPC5200B v2.1 */
7971 POWERPC_DEF_SVR("MPC5200B_v21",
7972 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE)
7973 /* MPC8241 */
7974 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2)
7975 /* MPC8245 */
7976 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2)
7977 /* MPC8247 */
7978 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE)
7979 /* MPC8248 */
7980 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE)
7981 /* MPC8250 */
7982 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2)
7983 /* MPC8250 HiP3 */
7984 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2)
7985 /* MPC8250 HiP4 */
7986 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2)
7987 /* MPC8255 */
7988 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2)
7989 /* MPC8255 HiP3 */
7990 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2)
7991 /* MPC8255 HiP4 */
7992 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2)
7993 /* MPC8260 */
7994 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2)
7995 /* MPC8260 HiP3 */
7996 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2)
7997 /* MPC8260 HiP4 */
7998 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2)
7999 /* MPC8264 */
8000 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2)
8001 /* MPC8264 HiP3 */
8002 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2)
8003 /* MPC8264 HiP4 */
8004 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2)
8005 /* MPC8265 */
8006 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2)
8007 /* MPC8265 HiP3 */
8008 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2)
8009 /* MPC8265 HiP4 */
8010 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2)
8011 /* MPC8266 */
8012 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2)
8013 /* MPC8266 HiP3 */
8014 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2)
8015 /* MPC8266 HiP4 */
8016 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2)
8017 /* MPC8270 */
8018 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE)
8019 /* MPC8271 */
8020 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE)
8021 /* MPC8272 */
8022 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE)
8023 /* MPC8275 */
8024 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE)
8025 /* MPC8280 */
8026 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE)
8027 /* e200 family */
8028 /* Generic PowerPC e200 core */
8029 POWERPC_DEF("e200", CPU_POWERPC_e200, e200)
8030 /* Generic MPC55xx core */
8031 #if defined (TODO)
8032 POWERPC_DEF_SVR("MPC55xx",
8033 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200)
8034 #endif
8035 #if defined (TODO)
8036 /* PowerPC e200z0 core */
8037 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200)
8038 #endif
8039 #if defined (TODO)
8040 /* PowerPC e200z1 core */
8041 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200)
8042 #endif
8043 #if defined (TODO)
8044 /* PowerPC e200z3 core */
8045 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200)
8046 #endif
8047 /* PowerPC e200z5 core */
8048 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200)
8049 /* PowerPC e200z6 core */
8050 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200)
8051 /* PowerPC e200 microcontrollers */
8052 #if defined (TODO)
8053 /* MPC5514E */
8054 POWERPC_DEF_SVR("MPC5514E",
8055 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200)
8056 #endif
8057 #if defined (TODO)
8058 /* MPC5514E v0 */
8059 POWERPC_DEF_SVR("MPC5514E_v0",
8060 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200)
8061 #endif
8062 #if defined (TODO)
8063 /* MPC5514E v1 */
8064 POWERPC_DEF_SVR("MPC5514E_v1",
8065 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200)
8066 #endif
8067 #if defined (TODO)
8068 /* MPC5514G */
8069 POWERPC_DEF_SVR("MPC5514G",
8070 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200)
8071 #endif
8072 #if defined (TODO)
8073 /* MPC5514G v0 */
8074 POWERPC_DEF_SVR("MPC5514G_v0",
8075 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200)
8076 #endif
8077 #if defined (TODO)
8078 /* MPC5514G v1 */
8079 POWERPC_DEF_SVR("MPC5514G_v1",
8080 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200)
8081 #endif
8082 #if defined (TODO)
8083 /* MPC5515S */
8084 POWERPC_DEF_SVR("MPC5515S",
8085 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200)
8086 #endif
8087 #if defined (TODO)
8088 /* MPC5516E */
8089 POWERPC_DEF_SVR("MPC5516E",
8090 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200)
8091 #endif
8092 #if defined (TODO)
8093 /* MPC5516E v0 */
8094 POWERPC_DEF_SVR("MPC5516E_v0",
8095 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200)
8096 #endif
8097 #if defined (TODO)
8098 /* MPC5516E v1 */
8099 POWERPC_DEF_SVR("MPC5516E_v1",
8100 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200)
8101 #endif
8102 #if defined (TODO)
8103 /* MPC5516G */
8104 POWERPC_DEF_SVR("MPC5516G",
8105 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200)
8106 #endif
8107 #if defined (TODO)
8108 /* MPC5516G v0 */
8109 POWERPC_DEF_SVR("MPC5516G_v0",
8110 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200)
8111 #endif
8112 #if defined (TODO)
8113 /* MPC5516G v1 */
8114 POWERPC_DEF_SVR("MPC5516G_v1",
8115 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200)
8116 #endif
8117 #if defined (TODO)
8118 /* MPC5516S */
8119 POWERPC_DEF_SVR("MPC5516S",
8120 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200)
8121 #endif
8122 #if defined (TODO)
8123 /* MPC5533 */
8124 POWERPC_DEF_SVR("MPC5533",
8125 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200)
8126 #endif
8127 #if defined (TODO)
8128 /* MPC5534 */
8129 POWERPC_DEF_SVR("MPC5534",
8130 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200)
8131 #endif
8132 #if defined (TODO)
8133 /* MPC5553 */
8134 POWERPC_DEF_SVR("MPC5553",
8135 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200)
8136 #endif
8137 #if defined (TODO)
8138 /* MPC5554 */
8139 POWERPC_DEF_SVR("MPC5554",
8140 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200)
8141 #endif
8142 #if defined (TODO)
8143 /* MPC5561 */
8144 POWERPC_DEF_SVR("MPC5561",
8145 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200)
8146 #endif
8147 #if defined (TODO)
8148 /* MPC5565 */
8149 POWERPC_DEF_SVR("MPC5565",
8150 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200)
8151 #endif
8152 #if defined (TODO)
8153 /* MPC5566 */
8154 POWERPC_DEF_SVR("MPC5566",
8155 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200)
8156 #endif
8157 #if defined (TODO)
8158 /* MPC5567 */
8159 POWERPC_DEF_SVR("MPC5567",
8160 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200)
8161 #endif
8162 /* e300 family */
8163 /* Generic PowerPC e300 core */
8164 POWERPC_DEF("e300", CPU_POWERPC_e300, e300)
8165 /* PowerPC e300c1 core */
8166 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300)
8167 /* PowerPC e300c2 core */
8168 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300)
8169 /* PowerPC e300c3 core */
8170 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300)
8171 /* PowerPC e300c4 core */
8172 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300)
8173 /* PowerPC e300 microcontrollers */
8174 #if defined (TODO)
8175 /* MPC8313 */
8176 POWERPC_DEF_SVR("MPC8313",
8177 CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300)
8178 #endif
8179 #if defined (TODO)
8180 /* MPC8313E */
8181 POWERPC_DEF_SVR("MPC8313E",
8182 CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300)
8183 #endif
8184 #if defined (TODO)
8185 /* MPC8314 */
8186 POWERPC_DEF_SVR("MPC8314",
8187 CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300)
8188 #endif
8189 #if defined (TODO)
8190 /* MPC8314E */
8191 POWERPC_DEF_SVR("MPC8314E",
8192 CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300)
8193 #endif
8194 #if defined (TODO)
8195 /* MPC8315 */
8196 POWERPC_DEF_SVR("MPC8315",
8197 CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300)
8198 #endif
8199 #if defined (TODO)
8200 /* MPC8315E */
8201 POWERPC_DEF_SVR("MPC8315E",
8202 CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300)
8203 #endif
8204 #if defined (TODO)
8205 /* MPC8321 */
8206 POWERPC_DEF_SVR("MPC8321",
8207 CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300)
8208 #endif
8209 #if defined (TODO)
8210 /* MPC8321E */
8211 POWERPC_DEF_SVR("MPC8321E",
8212 CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300)
8213 #endif
8214 #if defined (TODO)
8215 /* MPC8323 */
8216 POWERPC_DEF_SVR("MPC8323",
8217 CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300)
8218 #endif
8219 #if defined (TODO)
8220 /* MPC8323E */
8221 POWERPC_DEF_SVR("MPC8323E",
8222 CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300)
8223 #endif
8224 /* MPC8343 */
8225 POWERPC_DEF_SVR("MPC8343",
8226 CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300)
8227 /* MPC8343A */
8228 POWERPC_DEF_SVR("MPC8343A",
8229 CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300)
8230 /* MPC8343E */
8231 POWERPC_DEF_SVR("MPC8343E",
8232 CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300)
8233 /* MPC8343EA */
8234 POWERPC_DEF_SVR("MPC8343EA",
8235 CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300)
8236 /* MPC8347T */
8237 POWERPC_DEF_SVR("MPC8347T",
8238 CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300)
8239 /* MPC8347P */
8240 POWERPC_DEF_SVR("MPC8347P",
8241 CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300)
8242 /* MPC8347AT */
8243 POWERPC_DEF_SVR("MPC8347AT",
8244 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300)
8245 /* MPC8347AP */
8246 POWERPC_DEF_SVR("MPC8347AP",
8247 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300)
8248 /* MPC8347ET */
8249 POWERPC_DEF_SVR("MPC8347ET",
8250 CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300)
8251 /* MPC8343EP */
8252 POWERPC_DEF_SVR("MPC8347EP",
8253 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300)
8254 /* MPC8347EAT */
8255 POWERPC_DEF_SVR("MPC8347EAT",
8256 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300)
8257 /* MPC8343EAP */
8258 POWERPC_DEF_SVR("MPC8347EAP",
8259 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300)
8260 /* MPC8349 */
8261 POWERPC_DEF_SVR("MPC8349",
8262 CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300)
8263 /* MPC8349A */
8264 POWERPC_DEF_SVR("MPC8349A",
8265 CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300)
8266 /* MPC8349E */
8267 POWERPC_DEF_SVR("MPC8349E",
8268 CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300)
8269 /* MPC8349EA */
8270 POWERPC_DEF_SVR("MPC8349EA",
8271 CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300)
8272 #if defined (TODO)
8273 /* MPC8358E */
8274 POWERPC_DEF_SVR("MPC8358E",
8275 CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300)
8276 #endif
8277 #if defined (TODO)
8278 /* MPC8360E */
8279 POWERPC_DEF_SVR("MPC8360E",
8280 CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300)
8281 #endif
8282 /* MPC8377 */
8283 POWERPC_DEF_SVR("MPC8377",
8284 CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300)
8285 /* MPC8377E */
8286 POWERPC_DEF_SVR("MPC8377E",
8287 CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300)
8288 /* MPC8378 */
8289 POWERPC_DEF_SVR("MPC8378",
8290 CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300)
8291 /* MPC8378E */
8292 POWERPC_DEF_SVR("MPC8378E",
8293 CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300)
8294 /* MPC8379 */
8295 POWERPC_DEF_SVR("MPC8379",
8296 CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300)
8297 /* MPC8379E */
8298 POWERPC_DEF_SVR("MPC8379E",
8299 CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300)
8300 /* e500 family */
8301 /* PowerPC e500 v1.0 core */
8302 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1)
8303 /* PowerPC e500 v2.0 core */
8304 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1)
8305 /* PowerPC e500v2 v1.0 core */
8306 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2)
8307 /* PowerPC e500v2 v2.0 core */
8308 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2)
8309 /* PowerPC e500v2 v2.1 core */
8310 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2)
8311 /* PowerPC e500v2 v2.2 core */
8312 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2)
8313 /* PowerPC e500v2 v3.0 core */
8314 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2)
8315 POWERPC_DEF_SVR("e500mc", CPU_POWERPC_e500mc, POWERPC_SVR_E500, e500mc)
8316 #ifdef TARGET_PPC64
8317 POWERPC_DEF_SVR("e5500", CPU_POWERPC_e5500, POWERPC_SVR_E500, e5500)
8318 #endif
8319 /* PowerPC e500 microcontrollers */
8320 /* MPC8533 v1.0 */
8321 POWERPC_DEF_SVR("MPC8533_v10",
8322 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2)
8323 /* MPC8533 v1.1 */
8324 POWERPC_DEF_SVR("MPC8533_v11",
8325 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2)
8326 /* MPC8533E v1.0 */
8327 POWERPC_DEF_SVR("MPC8533E_v10",
8328 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2)
8329 POWERPC_DEF_SVR("MPC8533E_v11",
8330 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2)
8331 /* MPC8540 v1.0 */
8332 POWERPC_DEF_SVR("MPC8540_v10",
8333 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1)
8334 /* MPC8540 v2.0 */
8335 POWERPC_DEF_SVR("MPC8540_v20",
8336 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1)
8337 /* MPC8540 v2.1 */
8338 POWERPC_DEF_SVR("MPC8540_v21",
8339 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1)
8340 /* MPC8541 v1.0 */
8341 POWERPC_DEF_SVR("MPC8541_v10",
8342 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1)
8343 /* MPC8541 v1.1 */
8344 POWERPC_DEF_SVR("MPC8541_v11",
8345 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1)
8346 /* MPC8541E v1.0 */
8347 POWERPC_DEF_SVR("MPC8541E_v10",
8348 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1)
8349 /* MPC8541E v1.1 */
8350 POWERPC_DEF_SVR("MPC8541E_v11",
8351 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1)
8352 /* MPC8543 v1.0 */
8353 POWERPC_DEF_SVR("MPC8543_v10",
8354 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2)
8355 /* MPC8543 v1.1 */
8356 POWERPC_DEF_SVR("MPC8543_v11",
8357 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2)
8358 /* MPC8543 v2.0 */
8359 POWERPC_DEF_SVR("MPC8543_v20",
8360 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2)
8361 /* MPC8543 v2.1 */
8362 POWERPC_DEF_SVR("MPC8543_v21",
8363 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2)
8364 /* MPC8543E v1.0 */
8365 POWERPC_DEF_SVR("MPC8543E_v10",
8366 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2)
8367 /* MPC8543E v1.1 */
8368 POWERPC_DEF_SVR("MPC8543E_v11",
8369 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2)
8370 /* MPC8543E v2.0 */
8371 POWERPC_DEF_SVR("MPC8543E_v20",
8372 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2)
8373 /* MPC8543E v2.1 */
8374 POWERPC_DEF_SVR("MPC8543E_v21",
8375 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2)
8376 /* MPC8544 v1.0 */
8377 POWERPC_DEF_SVR("MPC8544_v10",
8378 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2)
8379 /* MPC8544 v1.1 */
8380 POWERPC_DEF_SVR("MPC8544_v11",
8381 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2)
8382 /* MPC8544E v1.0 */
8383 POWERPC_DEF_SVR("MPC8544E_v10",
8384 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2)
8385 /* MPC8544E v1.1 */
8386 POWERPC_DEF_SVR("MPC8544E_v11",
8387 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2)
8388 /* MPC8545 v2.0 */
8389 POWERPC_DEF_SVR("MPC8545_v20",
8390 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2)
8391 /* MPC8545 v2.1 */
8392 POWERPC_DEF_SVR("MPC8545_v21",
8393 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2)
8394 /* MPC8545E v2.0 */
8395 POWERPC_DEF_SVR("MPC8545E_v20",
8396 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2)
8397 /* MPC8545E v2.1 */
8398 POWERPC_DEF_SVR("MPC8545E_v21",
8399 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2)
8400 /* MPC8547E v2.0 */
8401 POWERPC_DEF_SVR("MPC8547E_v20",
8402 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2)
8403 /* MPC8547E v2.1 */
8404 POWERPC_DEF_SVR("MPC8547E_v21",
8405 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2)
8406 /* MPC8548 v1.0 */
8407 POWERPC_DEF_SVR("MPC8548_v10",
8408 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2)
8409 /* MPC8548 v1.1 */
8410 POWERPC_DEF_SVR("MPC8548_v11",
8411 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2)
8412 /* MPC8548 v2.0 */
8413 POWERPC_DEF_SVR("MPC8548_v20",
8414 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2)
8415 /* MPC8548 v2.1 */
8416 POWERPC_DEF_SVR("MPC8548_v21",
8417 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2)
8418 /* MPC8548E v1.0 */
8419 POWERPC_DEF_SVR("MPC8548E_v10",
8420 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2)
8421 /* MPC8548E v1.1 */
8422 POWERPC_DEF_SVR("MPC8548E_v11",
8423 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2)
8424 /* MPC8548E v2.0 */
8425 POWERPC_DEF_SVR("MPC8548E_v20",
8426 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2)
8427 /* MPC8548E v2.1 */
8428 POWERPC_DEF_SVR("MPC8548E_v21",
8429 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2)
8430 /* MPC8555 v1.0 */
8431 POWERPC_DEF_SVR("MPC8555_v10",
8432 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2)
8433 /* MPC8555 v1.1 */
8434 POWERPC_DEF_SVR("MPC8555_v11",
8435 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2)
8436 /* MPC8555E v1.0 */
8437 POWERPC_DEF_SVR("MPC8555E_v10",
8438 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2)
8439 /* MPC8555E v1.1 */
8440 POWERPC_DEF_SVR("MPC8555E_v11",
8441 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2)
8442 /* MPC8560 v1.0 */
8443 POWERPC_DEF_SVR("MPC8560_v10",
8444 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2)
8445 /* MPC8560 v2.0 */
8446 POWERPC_DEF_SVR("MPC8560_v20",
8447 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2)
8448 /* MPC8560 v2.1 */
8449 POWERPC_DEF_SVR("MPC8560_v21",
8450 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2)
8451 /* MPC8567 */
8452 POWERPC_DEF_SVR("MPC8567",
8453 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2)
8454 /* MPC8567E */
8455 POWERPC_DEF_SVR("MPC8567E",
8456 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2)
8457 /* MPC8568 */
8458 POWERPC_DEF_SVR("MPC8568",
8459 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2)
8460 /* MPC8568E */
8461 POWERPC_DEF_SVR("MPC8568E",
8462 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2)
8463 /* MPC8572 */
8464 POWERPC_DEF_SVR("MPC8572",
8465 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2)
8466 /* MPC8572E */
8467 POWERPC_DEF_SVR("MPC8572E",
8468 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2)
8469 /* e600 family */
8470 /* PowerPC e600 core */
8471 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400)
8472 /* PowerPC e600 microcontrollers */
8473 #if defined (TODO)
8474 /* MPC8610 */
8475 POWERPC_DEF_SVR("MPC8610",
8476 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400)
8477 #endif
8478 /* MPC8641 */
8479 POWERPC_DEF_SVR("MPC8641",
8480 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400)
8481 /* MPC8641D */
8482 POWERPC_DEF_SVR("MPC8641D",
8483 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400)
8484 /* 32 bits "classic" PowerPC */
8485 /* PowerPC 6xx family */
8486 /* PowerPC 601v0 */
8487 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601)
8488 /* PowerPC 601v1 */
8489 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601)
8490 /* PowerPC 601v2 */
8491 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v)
8492 /* PowerPC 602 */
8493 POWERPC_DEF("602", CPU_POWERPC_602, 602)
8494 /* PowerPC 603 */
8495 POWERPC_DEF("603", CPU_POWERPC_603, 603)
8496 /* PowerPC 603e v1.1 */
8497 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E)
8498 /* PowerPC 603e v1.2 */
8499 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E)
8500 /* PowerPC 603e v1.3 */
8501 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E)
8502 /* PowerPC 603e v1.4 */
8503 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E)
8504 /* PowerPC 603e v2.2 */
8505 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E)
8506 /* PowerPC 603e v3 */
8507 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E)
8508 /* PowerPC 603e v4 */
8509 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E)
8510 /* PowerPC 603e v4.1 */
8511 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E)
8512 /* PowerPC 603e (aka PID7) */
8513 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E)
8514 /* PowerPC 603e7t */
8515 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E)
8516 /* PowerPC 603e7v */
8517 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E)
8518 /* PowerPC 603e7v1 */
8519 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E)
8520 /* PowerPC 603e7v2 */
8521 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E)
8522 /* PowerPC 603p (aka PID7v) */
8523 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E)
8524 /* PowerPC 604 */
8525 POWERPC_DEF("604", CPU_POWERPC_604, 604)
8526 /* PowerPC 604e v1.0 */
8527 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E)
8528 /* PowerPC 604e v2.2 */
8529 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E)
8530 /* PowerPC 604e v2.4 */
8531 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E)
8532 /* PowerPC 604r (aka PIDA) */
8533 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E)
8534 #if defined(TODO)
8535 /* PowerPC 604ev */
8536 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E)
8537 #endif
8538 /* PowerPC 7xx family */
8539 /* PowerPC 740 v1.0 (G3) */
8540 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740)
8541 /* PowerPC 750 v1.0 (G3) */
8542 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750)
8543 /* PowerPC 740 v2.0 (G3) */
8544 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740)
8545 /* PowerPC 750 v2.0 (G3) */
8546 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750)
8547 /* PowerPC 740 v2.1 (G3) */
8548 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740)
8549 /* PowerPC 750 v2.1 (G3) */
8550 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750)
8551 /* PowerPC 740 v2.2 (G3) */
8552 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740)
8553 /* PowerPC 750 v2.2 (G3) */
8554 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750)
8555 /* PowerPC 740 v3.0 (G3) */
8556 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740)
8557 /* PowerPC 750 v3.0 (G3) */
8558 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750)
8559 /* PowerPC 740 v3.1 (G3) */
8560 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740)
8561 /* PowerPC 750 v3.1 (G3) */
8562 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750)
8563 /* PowerPC 740E (G3) */
8564 POWERPC_DEF("740e", CPU_POWERPC_740E, 740)
8565 /* PowerPC 750E (G3) */
8566 POWERPC_DEF("750e", CPU_POWERPC_750E, 750)
8567 /* PowerPC 740P (G3) */
8568 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740)
8569 /* PowerPC 750P (G3) */
8570 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750)
8571 /* PowerPC 750CL v1.0 */
8572 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl)
8573 /* PowerPC 750CL v2.0 */
8574 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl)
8575 /* PowerPC 750CX v1.0 (G3 embedded) */
8576 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx)
8577 /* PowerPC 750CX v2.1 (G3 embedded) */
8578 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx)
8579 /* PowerPC 750CX v2.1 (G3 embedded) */
8580 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx)
8581 /* PowerPC 750CX v2.2 (G3 embedded) */
8582 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx)
8583 /* PowerPC 750CXe v2.1 (G3 embedded) */
8584 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx)
8585 /* PowerPC 750CXe v2.2 (G3 embedded) */
8586 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx)
8587 /* PowerPC 750CXe v2.3 (G3 embedded) */
8588 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx)
8589 /* PowerPC 750CXe v2.4 (G3 embedded) */
8590 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx)
8591 /* PowerPC 750CXe v2.4b (G3 embedded) */
8592 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx)
8593 /* PowerPC 750CXe v3.0 (G3 embedded) */
8594 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx)
8595 /* PowerPC 750CXe v3.1 (G3 embedded) */
8596 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx)
8597 /* PowerPC 750CXe v3.1b (G3 embedded) */
8598 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx)
8599 /* PowerPC 750CXr (G3 embedded) */
8600 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx)
8601 /* PowerPC 750FL (G3 embedded) */
8602 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx)
8603 /* PowerPC 750FX v1.0 (G3 embedded) */
8604 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx)
8605 /* PowerPC 750FX v2.0 (G3 embedded) */
8606 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx)
8607 /* PowerPC 750FX v2.1 (G3 embedded) */
8608 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx)
8609 /* PowerPC 750FX v2.2 (G3 embedded) */
8610 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx)
8611 /* PowerPC 750FX v2.3 (G3 embedded) */
8612 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx)
8613 /* PowerPC 750GL (G3 embedded) */
8614 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx)
8615 /* PowerPC 750GX v1.0 (G3 embedded) */
8616 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx)
8617 /* PowerPC 750GX v1.1 (G3 embedded) */
8618 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx)
8619 /* PowerPC 750GX v1.2 (G3 embedded) */
8620 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx)
8621 /* PowerPC 750L v2.0 (G3 embedded) */
8622 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750)
8623 /* PowerPC 750L v2.1 (G3 embedded) */
8624 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750)
8625 /* PowerPC 750L v2.2 (G3 embedded) */
8626 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750)
8627 /* PowerPC 750L v3.0 (G3 embedded) */
8628 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750)
8629 /* PowerPC 750L v3.2 (G3 embedded) */
8630 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750)
8631 /* PowerPC 745 v1.0 */
8632 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745)
8633 /* PowerPC 755 v1.0 */
8634 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755)
8635 /* PowerPC 745 v1.1 */
8636 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745)
8637 /* PowerPC 755 v1.1 */
8638 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755)
8639 /* PowerPC 745 v2.0 */
8640 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745)
8641 /* PowerPC 755 v2.0 */
8642 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755)
8643 /* PowerPC 745 v2.1 */
8644 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745)
8645 /* PowerPC 755 v2.1 */
8646 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755)
8647 /* PowerPC 745 v2.2 */
8648 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745)
8649 /* PowerPC 755 v2.2 */
8650 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755)
8651 /* PowerPC 745 v2.3 */
8652 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745)
8653 /* PowerPC 755 v2.3 */
8654 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755)
8655 /* PowerPC 745 v2.4 */
8656 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745)
8657 /* PowerPC 755 v2.4 */
8658 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755)
8659 /* PowerPC 745 v2.5 */
8660 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745)
8661 /* PowerPC 755 v2.5 */
8662 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755)
8663 /* PowerPC 745 v2.6 */
8664 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745)
8665 /* PowerPC 755 v2.6 */
8666 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755)
8667 /* PowerPC 745 v2.7 */
8668 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745)
8669 /* PowerPC 755 v2.7 */
8670 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755)
8671 /* PowerPC 745 v2.8 */
8672 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745)
8673 /* PowerPC 755 v2.8 */
8674 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755)
8675 #if defined (TODO)
8676 /* PowerPC 745P (G3) */
8677 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745)
8678 /* PowerPC 755P (G3) */
8679 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755)
8680 #endif
8681 /* PowerPC 74xx family */
8682 /* PowerPC 7400 v1.0 (G4) */
8683 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400)
8684 /* PowerPC 7400 v1.1 (G4) */
8685 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400)
8686 /* PowerPC 7400 v2.0 (G4) */
8687 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400)
8688 /* PowerPC 7400 v2.1 (G4) */
8689 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400)
8690 /* PowerPC 7400 v2.2 (G4) */
8691 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400)
8692 /* PowerPC 7400 v2.6 (G4) */
8693 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400)
8694 /* PowerPC 7400 v2.7 (G4) */
8695 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400)
8696 /* PowerPC 7400 v2.8 (G4) */
8697 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400)
8698 /* PowerPC 7400 v2.9 (G4) */
8699 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400)
8700 /* PowerPC 7410 v1.0 (G4) */
8701 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410)
8702 /* PowerPC 7410 v1.1 (G4) */
8703 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410)
8704 /* PowerPC 7410 v1.2 (G4) */
8705 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410)
8706 /* PowerPC 7410 v1.3 (G4) */
8707 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410)
8708 /* PowerPC 7410 v1.4 (G4) */
8709 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410)
8710 /* PowerPC 7448 v1.0 (G4) */
8711 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400)
8712 /* PowerPC 7448 v1.1 (G4) */
8713 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400)
8714 /* PowerPC 7448 v2.0 (G4) */
8715 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400)
8716 /* PowerPC 7448 v2.1 (G4) */
8717 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400)
8718 /* PowerPC 7450 v1.0 (G4) */
8719 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450)
8720 /* PowerPC 7450 v1.1 (G4) */
8721 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450)
8722 /* PowerPC 7450 v1.2 (G4) */
8723 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450)
8724 /* PowerPC 7450 v2.0 (G4) */
8725 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450)
8726 /* PowerPC 7450 v2.1 (G4) */
8727 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450)
8728 /* PowerPC 7441 v2.1 (G4) */
8729 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440)
8730 /* PowerPC 7441 v2.3 (G4) */
8731 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440)
8732 /* PowerPC 7451 v2.3 (G4) */
8733 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450)
8734 /* PowerPC 7441 v2.10 (G4) */
8735 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440)
8736 /* PowerPC 7451 v2.10 (G4) */
8737 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450)
8738 /* PowerPC 7445 v1.0 (G4) */
8739 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445)
8740 /* PowerPC 7455 v1.0 (G4) */
8741 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455)
8742 /* PowerPC 7445 v2.1 (G4) */
8743 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445)
8744 /* PowerPC 7455 v2.1 (G4) */
8745 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455)
8746 /* PowerPC 7445 v3.2 (G4) */
8747 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445)
8748 /* PowerPC 7455 v3.2 (G4) */
8749 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455)
8750 /* PowerPC 7445 v3.3 (G4) */
8751 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445)
8752 /* PowerPC 7455 v3.3 (G4) */
8753 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455)
8754 /* PowerPC 7445 v3.4 (G4) */
8755 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445)
8756 /* PowerPC 7455 v3.4 (G4) */
8757 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455)
8758 /* PowerPC 7447 v1.0 (G4) */
8759 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445)
8760 /* PowerPC 7457 v1.0 (G4) */
8761 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455)
8762 /* PowerPC 7447 v1.1 (G4) */
8763 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445)
8764 /* PowerPC 7457 v1.1 (G4) */
8765 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455)
8766 /* PowerPC 7457 v1.2 (G4) */
8767 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455)
8768 /* PowerPC 7447A v1.0 (G4) */
8769 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445)
8770 /* PowerPC 7457A v1.0 (G4) */
8771 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455)
8772 /* PowerPC 7447A v1.1 (G4) */
8773 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445)
8774 /* PowerPC 7457A v1.1 (G4) */
8775 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455)
8776 /* PowerPC 7447A v1.2 (G4) */
8777 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445)
8778 /* PowerPC 7457A v1.2 (G4) */
8779 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455)
8780 /* 64 bits PowerPC */
8781 #if defined (TARGET_PPC64)
8782 /* PowerPC 620 */
8783 POWERPC_DEF("620", CPU_POWERPC_620, 620)
8784 #if defined (TODO)
8785 /* PowerPC 630 (POWER3) */
8786 POWERPC_DEF("630", CPU_POWERPC_630, 630)
8787 #endif
8788 #if defined (TODO)
8789 /* PowerPC 631 (Power 3+) */
8790 POWERPC_DEF("631", CPU_POWERPC_631, 631)
8791 #endif
8792 #if defined (TODO)
8793 /* POWER4 */
8794 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4)
8795 #endif
8796 #if defined (TODO)
8797 /* POWER4p */
8798 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P)
8799 #endif
8800 #if defined (TODO)
8801 /* POWER5 */
8802 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5)
8803 /* POWER5GR */
8804 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5)
8805 #endif
8806 #if defined (TODO)
8807 /* POWER5+ */
8808 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P)
8809 /* POWER5GS */
8810 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P)
8811 #endif
8812 #if defined (TODO)
8813 /* POWER6 */
8814 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6)
8815 /* POWER6 running in POWER5 mode */
8816 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5)
8817 /* POWER6A */
8818 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6)
8819 #endif
8820 /* POWER7 */
8821 POWERPC_DEF("POWER7", CPU_POWERPC_POWER7, POWER7)
8822 POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7)
8823 POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POWER7)
8824 POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7)
8825 /* PowerPC 970 */
8826 POWERPC_DEF("970", CPU_POWERPC_970, 970)
8827 /* PowerPC 970FX (G5) */
8828 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX)
8829 /* PowerPC 970FX v1.0 (G5) */
8830 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX)
8831 /* PowerPC 970FX v2.0 (G5) */
8832 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX)
8833 /* PowerPC 970FX v2.1 (G5) */
8834 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX)
8835 /* PowerPC 970FX v3.0 (G5) */
8836 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX)
8837 /* PowerPC 970FX v3.1 (G5) */
8838 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX)
8839 /* PowerPC 970GX (G5) */
8840 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX)
8841 /* PowerPC 970MP */
8842 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP)
8843 /* PowerPC 970MP v1.0 */
8844 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP)
8845 /* PowerPC 970MP v1.1 */
8846 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP)
8847 #if defined (TODO)
8848 /* PowerPC Cell */
8849 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970)
8850 #endif
8851 #if defined (TODO)
8852 /* PowerPC Cell v1.0 */
8853 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970)
8854 #endif
8855 #if defined (TODO)
8856 /* PowerPC Cell v2.0 */
8857 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970)
8858 #endif
8859 #if defined (TODO)
8860 /* PowerPC Cell v3.0 */
8861 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970)
8862 #endif
8863 #if defined (TODO)
8864 /* PowerPC Cell v3.1 */
8865 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970)
8866 #endif
8867 #if defined (TODO)
8868 /* PowerPC Cell v3.2 */
8869 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970)
8870 #endif
8871 #if defined (TODO)
8872 /* RS64 (Apache/A35) */
8873 /* This one seems to support the whole POWER2 instruction set
8874 * and the PowerPC 64 one.
8875 */
8876 /* What about A10 & A30 ? */
8877 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64)
8878 #endif
8879 #if defined (TODO)
8880 /* RS64-II (NorthStar/A50) */
8881 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64)
8882 #endif
8883 #if defined (TODO)
8884 /* RS64-III (Pulsar) */
8885 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64)
8886 #endif
8887 #if defined (TODO)
8888 /* RS64-IV (IceStar/IStar/SStar) */
8889 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64)
8890 #endif
8891 #endif /* defined (TARGET_PPC64) */
8892 /* POWER */
8893 #if defined (TODO)
8894 /* Original POWER */
8895 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER)
8896 #endif
8897 #if defined (TODO)
8898 /* POWER2 */
8899 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER)
8900 #endif
8901 /* PA semi cores */
8902 #if defined (TODO)
8903 /* PA PA6T */
8904 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T)
8905 #endif
8906 };
8907
8908 typedef struct PowerPCCPUAlias {
8909 const char *alias;
8910 const char *model;
8911 } PowerPCCPUAlias;
8912
8913 static const PowerPCCPUAlias ppc_cpu_aliases[] = {
8914 { "403", "403GC" },
8915 { "405", "405D4" },
8916 { "405CR", "405CRc" },
8917 { "405GP", "405GPd" },
8918 { "x2vp7", "x2vp4" },
8919 { "x2vp50", "x2vp20" },
8920
8921 { "440EP", "440EPb" },
8922 { "440GP", "440GPc" },
8923 { "440GR", "440GRa" },
8924 { "440GX", "440GXf" },
8925
8926 { "RCPU", "MPC5xx" },
8927 /* MPC5xx microcontrollers */
8928 { "MGT560", "MPC5xx" },
8929 { "MPC509", "MPC5xx" },
8930 { "MPC533", "MPC5xx" },
8931 { "MPC534", "MPC5xx" },
8932 { "MPC555", "MPC5xx" },
8933 { "MPC556", "MPC5xx" },
8934 { "MPC560", "MPC5xx" },
8935 { "MPC561", "MPC5xx" },
8936 { "MPC562", "MPC5xx" },
8937 { "MPC563", "MPC5xx" },
8938 { "MPC564", "MPC5xx" },
8939 { "MPC565", "MPC5xx" },
8940 { "MPC566", "MPC5xx" },
8941
8942 { "PowerQUICC", "MPC8xx" },
8943 /* MPC8xx microcontrollers */
8944 { "MGT823", "MPC8xx" },
8945 { "MPC821", "MPC8xx" },
8946 { "MPC823", "MPC8xx" },
8947 { "MPC850", "MPC8xx" },
8948 { "MPC852T", "MPC8xx" },
8949 { "MPC855T", "MPC8xx" },
8950 { "MPC857", "MPC8xx" },
8951 { "MPC859", "MPC8xx" },
8952 { "MPC860", "MPC8xx" },
8953 { "MPC862", "MPC8xx" },
8954 { "MPC866", "MPC8xx" },
8955 { "MPC870", "MPC8xx" },
8956 { "MPC875", "MPC8xx" },
8957 { "MPC880", "MPC8xx" },
8958 { "MPC885", "MPC8xx" },
8959
8960 { "PowerQUICC-II", "MPC82xx" },
8961 { "MPC8347", "MPC8347T" },
8962 { "MPC8347A", "MPC8347AT" },
8963 { "MPC8347E", "MPC8347ET" },
8964 { "MPC8347EA", "MPC8347EAT" },
8965 { "e500", "e500v2_v22" },
8966 { "e500v1", "e500_v20" },
8967 { "e500v2", "e500v2_v22" },
8968 { "MPC8533", "MPC8533_v11" },
8969 { "MPC8533E", "MPC8533E_v11" },
8970 { "MPC8540", "MPC8540_v21" },
8971 { "MPC8541", "MPC8541_v11" },
8972 { "MPC8541E", "MPC8541E_v11" },
8973 { "MPC8543", "MPC8543_v21" },
8974 { "MPC8543E", "MPC8543E_v21" },
8975 { "MPC8544", "MPC8544_v11" },
8976 { "MPC8544E", "MPC8544E_v11" },
8977 { "MPC8545", "MPC8545_v21" },
8978 { "MPC8545E", "MPC8545E_v21" },
8979 { "MPC8547E", "MPC8547E_v21" },
8980 { "MPC8548", "MPC8548_v21" },
8981 { "MPC8548E", "MPC8548E_v21" },
8982 { "MPC8555", "MPC8555_v11" },
8983 { "MPC8555E", "MPC8555E_v11" },
8984 { "MPC8560", "MPC8560_v21" },
8985 { "601", "601_v2" },
8986 { "601v", "601_v2" },
8987 { "Vanilla", "603" },
8988 { "603e", "603e_v4.1" },
8989 { "Stretch", "603e" },
8990 { "Vaillant", "603e7v" },
8991 { "603r", "603e7t" },
8992 { "Goldeneye", "603r" },
8993 { "604e", "604e_v2.4" },
8994 { "Sirocco", "604e" },
8995 { "Mach5", "604r" },
8996 { "740", "740_v3.1" },
8997 { "Arthur", "740" },
8998 { "750", "750_v3.1" },
8999 { "Typhoon", "750" },
9000 { "G3", "750" },
9001 { "Conan/Doyle", "750p" },
9002 { "750cl", "750cl_v2.0" },
9003 { "750cx", "750cx_v2.2" },
9004 { "750cxe", "750cxe_v3.1b" },
9005 { "750fx", "750fx_v2.3" },
9006 { "750gx", "750gx_v1.2" },
9007 { "750l", "750l_v3.2" },
9008 { "LoneStar", "750l" },
9009 { "745", "745_v2.8" },
9010 { "755", "755_v2.8" },
9011 { "Goldfinger", "755" },
9012 { "7400", "7400_v2.9" },
9013 { "Max", "7400" },
9014 { "G4", "7400" },
9015 { "7410", "7410_v1.4" },
9016 { "Nitro", "7410" },
9017 { "7448", "7448_v2.1" },
9018 { "7450", "7450_v2.1" },
9019 { "Vger", "7450" },
9020 { "7441", "7441_v2.3" },
9021 { "7451", "7451_v2.3" },
9022 { "7445", "7445_v3.2" },
9023 { "7455", "7455_v3.2" },
9024 { "Apollo6", "7455" },
9025 { "7447", "7447_v1.2" },
9026 { "7457", "7457_v1.2" },
9027 { "Apollo7", "7457" },
9028 { "7447A", "7447A_v1.2" },
9029 { "7457A", "7457A_v1.2" },
9030 { "Apollo7PM", "7457A_v1.0" },
9031 #if defined(TARGET_PPC64)
9032 { "Trident", "620" },
9033 { "POWER3", "630" },
9034 { "Boxer", "POWER3" },
9035 { "Dino", "POWER3" },
9036 { "POWER3+", "631" },
9037 { "Apache", "RS64" },
9038 { "A35", "RS64" },
9039 { "NorthStar", "RS64-II" },
9040 { "A50", "RS64-II" },
9041 { "Pulsar", "RS64-III" },
9042 { "IceStar", "RS64-IV" },
9043 { "IStar", "RS64-IV" },
9044 { "SStar", "RS64-IV" },
9045 #endif
9046 { "RIOS", "POWER" },
9047 { "RSC", "POWER" },
9048 { "RSC3308", "POWER" },
9049 { "RSC4608", "POWER" },
9050 { "RSC2", "POWER2" },
9051 { "P2SC", "POWER2" },
9052
9053 /* Generic PowerPCs */
9054 #if defined(TARGET_PPC64)
9055 { "ppc64", "970fx" },
9056 #endif
9057 { "ppc32", "604" },
9058 { "ppc", "ppc32" },
9059 { "default", "ppc" },
9060 };
9061
9062 /*****************************************************************************/
9063 /* Generic CPU instantiation routine */
9064 static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
9065 {
9066 #if !defined(CONFIG_USER_ONLY)
9067 int i;
9068
9069 env->irq_inputs = NULL;
9070 /* Set all exception vectors to an invalid address */
9071 for (i = 0; i < POWERPC_EXCP_NB; i++)
9072 env->excp_vectors[i] = (target_ulong)(-1ULL);
9073 env->hreset_excp_prefix = 0x00000000;
9074 env->ivor_mask = 0x00000000;
9075 env->ivpr_mask = 0x00000000;
9076 /* Default MMU definitions */
9077 env->nb_BATs = 0;
9078 env->nb_tlb = 0;
9079 env->nb_ways = 0;
9080 env->tlb_type = TLB_NONE;
9081 #endif
9082 /* Register SPR common to all PowerPC implementations */
9083 gen_spr_generic(env);
9084 spr_register(env, SPR_PVR, "PVR",
9085 /* Linux permits userspace to read PVR */
9086 #if defined(CONFIG_LINUX_USER)
9087 &spr_read_generic,
9088 #else
9089 SPR_NOACCESS,
9090 #endif
9091 SPR_NOACCESS,
9092 &spr_read_generic, SPR_NOACCESS,
9093 def->pvr);
9094 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9095 if (def->svr != POWERPC_SVR_NONE) {
9096 if (def->svr & POWERPC_SVR_E500) {
9097 spr_register(env, SPR_E500_SVR, "SVR",
9098 SPR_NOACCESS, SPR_NOACCESS,
9099 &spr_read_generic, SPR_NOACCESS,
9100 def->svr & ~POWERPC_SVR_E500);
9101 } else {
9102 spr_register(env, SPR_SVR, "SVR",
9103 SPR_NOACCESS, SPR_NOACCESS,
9104 &spr_read_generic, SPR_NOACCESS,
9105 def->svr);
9106 }
9107 }
9108 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9109 (*def->init_proc)(env);
9110 #if !defined(CONFIG_USER_ONLY)
9111 env->excp_prefix = env->hreset_excp_prefix;
9112 #endif
9113 /* MSR bits & flags consistency checks */
9114 if (env->msr_mask & (1 << 25)) {
9115 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9116 case POWERPC_FLAG_SPE:
9117 case POWERPC_FLAG_VRE:
9118 break;
9119 default:
9120 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9121 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9122 exit(1);
9123 }
9124 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9125 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9126 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9127 exit(1);
9128 }
9129 if (env->msr_mask & (1 << 17)) {
9130 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9131 case POWERPC_FLAG_TGPR:
9132 case POWERPC_FLAG_CE:
9133 break;
9134 default:
9135 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9136 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9137 exit(1);
9138 }
9139 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9140 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9141 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9142 exit(1);
9143 }
9144 if (env->msr_mask & (1 << 10)) {
9145 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9146 POWERPC_FLAG_UBLE)) {
9147 case POWERPC_FLAG_SE:
9148 case POWERPC_FLAG_DWE:
9149 case POWERPC_FLAG_UBLE:
9150 break;
9151 default:
9152 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9153 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9154 "POWERPC_FLAG_UBLE\n");
9155 exit(1);
9156 }
9157 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9158 POWERPC_FLAG_UBLE)) {
9159 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9160 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9161 "POWERPC_FLAG_UBLE\n");
9162 exit(1);
9163 }
9164 if (env->msr_mask & (1 << 9)) {
9165 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9166 case POWERPC_FLAG_BE:
9167 case POWERPC_FLAG_DE:
9168 break;
9169 default:
9170 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9171 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9172 exit(1);
9173 }
9174 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9175 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9176 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9177 exit(1);
9178 }
9179 if (env->msr_mask & (1 << 2)) {
9180 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9181 case POWERPC_FLAG_PX:
9182 case POWERPC_FLAG_PMM:
9183 break;
9184 default:
9185 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9186 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9187 exit(1);
9188 }
9189 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9190 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9191 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9192 exit(1);
9193 }
9194 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9195 fprintf(stderr, "PowerPC flags inconsistency\n"
9196 "Should define the time-base and decrementer clock source\n");
9197 exit(1);
9198 }
9199 /* Allocate TLBs buffer when needed */
9200 #if !defined(CONFIG_USER_ONLY)
9201 if (env->nb_tlb != 0) {
9202 int nb_tlb = env->nb_tlb;
9203 if (env->id_tlbs != 0)
9204 nb_tlb *= 2;
9205 switch (env->tlb_type) {
9206 case TLB_6XX:
9207 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
9208 break;
9209 case TLB_EMB:
9210 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
9211 break;
9212 case TLB_MAS:
9213 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
9214 break;
9215 }
9216 /* Pre-compute some useful values */
9217 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9218 }
9219 if (env->irq_inputs == NULL) {
9220 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
9221 " Attempt QEMU to crash very soon !\n");
9222 }
9223 #endif
9224 if (env->check_pow == NULL) {
9225 fprintf(stderr, "WARNING: no power management check handler "
9226 "registered.\n"
9227 " Attempt QEMU to crash very soon !\n");
9228 }
9229 }
9230
9231 #if defined(PPC_DUMP_CPU)
9232 static void dump_ppc_sprs (CPUPPCState *env)
9233 {
9234 ppc_spr_t *spr;
9235 #if !defined(CONFIG_USER_ONLY)
9236 uint32_t sr, sw;
9237 #endif
9238 uint32_t ur, uw;
9239 int i, j, n;
9240
9241 printf("Special purpose registers:\n");
9242 for (i = 0; i < 32; i++) {
9243 for (j = 0; j < 32; j++) {
9244 n = (i << 5) | j;
9245 spr = &env->spr_cb[n];
9246 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9247 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9248 #if !defined(CONFIG_USER_ONLY)
9249 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9250 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9251 if (sw || sr || uw || ur) {
9252 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9253 (i << 5) | j, (i << 5) | j, spr->name,
9254 sw ? 'w' : '-', sr ? 'r' : '-',
9255 uw ? 'w' : '-', ur ? 'r' : '-');
9256 }
9257 #else
9258 if (uw || ur) {
9259 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9260 (i << 5) | j, (i << 5) | j, spr->name,
9261 uw ? 'w' : '-', ur ? 'r' : '-');
9262 }
9263 #endif
9264 }
9265 }
9266 fflush(stdout);
9267 fflush(stderr);
9268 }
9269 #endif
9270
9271 /*****************************************************************************/
9272 #include <stdlib.h>
9273 #include <string.h>
9274
9275 /* Opcode types */
9276 enum {
9277 PPC_DIRECT = 0, /* Opcode routine */
9278 PPC_INDIRECT = 1, /* Indirect opcode table */
9279 };
9280
9281 static inline int is_indirect_opcode (void *handler)
9282 {
9283 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
9284 }
9285
9286 static inline opc_handler_t **ind_table(void *handler)
9287 {
9288 return (opc_handler_t **)((uintptr_t)handler & ~3);
9289 }
9290
9291 /* Instruction table creation */
9292 /* Opcodes tables creation */
9293 static void fill_new_table (opc_handler_t **table, int len)
9294 {
9295 int i;
9296
9297 for (i = 0; i < len; i++)
9298 table[i] = &invalid_handler;
9299 }
9300
9301 static int create_new_table (opc_handler_t **table, unsigned char idx)
9302 {
9303 opc_handler_t **tmp;
9304
9305 tmp = malloc(0x20 * sizeof(opc_handler_t));
9306 fill_new_table(tmp, 0x20);
9307 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
9308
9309 return 0;
9310 }
9311
9312 static int insert_in_table (opc_handler_t **table, unsigned char idx,
9313 opc_handler_t *handler)
9314 {
9315 if (table[idx] != &invalid_handler)
9316 return -1;
9317 table[idx] = handler;
9318
9319 return 0;
9320 }
9321
9322 static int register_direct_insn (opc_handler_t **ppc_opcodes,
9323 unsigned char idx, opc_handler_t *handler)
9324 {
9325 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9326 printf("*** ERROR: opcode %02x already assigned in main "
9327 "opcode table\n", idx);
9328 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9329 printf(" Registered handler '%s' - new handler '%s'\n",
9330 ppc_opcodes[idx]->oname, handler->oname);
9331 #endif
9332 return -1;
9333 }
9334
9335 return 0;
9336 }
9337
9338 static int register_ind_in_table (opc_handler_t **table,
9339 unsigned char idx1, unsigned char idx2,
9340 opc_handler_t *handler)
9341 {
9342 if (table[idx1] == &invalid_handler) {
9343 if (create_new_table(table, idx1) < 0) {
9344 printf("*** ERROR: unable to create indirect table "
9345 "idx=%02x\n", idx1);
9346 return -1;
9347 }
9348 } else {
9349 if (!is_indirect_opcode(table[idx1])) {
9350 printf("*** ERROR: idx %02x already assigned to a direct "
9351 "opcode\n", idx1);
9352 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9353 printf(" Registered handler '%s' - new handler '%s'\n",
9354 ind_table(table[idx1])[idx2]->oname, handler->oname);
9355 #endif
9356 return -1;
9357 }
9358 }
9359 if (handler != NULL &&
9360 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9361 printf("*** ERROR: opcode %02x already assigned in "
9362 "opcode table %02x\n", idx2, idx1);
9363 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9364 printf(" Registered handler '%s' - new handler '%s'\n",
9365 ind_table(table[idx1])[idx2]->oname, handler->oname);
9366 #endif
9367 return -1;
9368 }
9369
9370 return 0;
9371 }
9372
9373 static int register_ind_insn (opc_handler_t **ppc_opcodes,
9374 unsigned char idx1, unsigned char idx2,
9375 opc_handler_t *handler)
9376 {
9377 int ret;
9378
9379 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9380
9381 return ret;
9382 }
9383
9384 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9385 unsigned char idx1, unsigned char idx2,
9386 unsigned char idx3, opc_handler_t *handler)
9387 {
9388 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9389 printf("*** ERROR: unable to join indirect table idx "
9390 "[%02x-%02x]\n", idx1, idx2);
9391 return -1;
9392 }
9393 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9394 handler) < 0) {
9395 printf("*** ERROR: unable to insert opcode "
9396 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9397 return -1;
9398 }
9399
9400 return 0;
9401 }
9402
9403 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9404 {
9405 if (insn->opc2 != 0xFF) {
9406 if (insn->opc3 != 0xFF) {
9407 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9408 insn->opc3, &insn->handler) < 0)
9409 return -1;
9410 } else {
9411 if (register_ind_insn(ppc_opcodes, insn->opc1,
9412 insn->opc2, &insn->handler) < 0)
9413 return -1;
9414 }
9415 } else {
9416 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9417 return -1;
9418 }
9419
9420 return 0;
9421 }
9422
9423 static int test_opcode_table (opc_handler_t **table, int len)
9424 {
9425 int i, count, tmp;
9426
9427 for (i = 0, count = 0; i < len; i++) {
9428 /* Consistency fixup */
9429 if (table[i] == NULL)
9430 table[i] = &invalid_handler;
9431 if (table[i] != &invalid_handler) {
9432 if (is_indirect_opcode(table[i])) {
9433 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9434 if (tmp == 0) {
9435 free(table[i]);
9436 table[i] = &invalid_handler;
9437 } else {
9438 count++;
9439 }
9440 } else {
9441 count++;
9442 }
9443 }
9444 }
9445
9446 return count;
9447 }
9448
9449 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9450 {
9451 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9452 printf("*** WARNING: no opcode defined !\n");
9453 }
9454
9455 /*****************************************************************************/
9456 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
9457 {
9458 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9459 CPUPPCState *env = &cpu->env;
9460 const ppc_def_t *def = pcc->info;
9461 opcode_t *opc;
9462
9463 fill_new_table(env->opcodes, 0x40);
9464 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9465 if (((opc->handler.type & def->insns_flags) != 0) ||
9466 ((opc->handler.type2 & def->insns_flags2) != 0)) {
9467 if (register_insn(env->opcodes, opc) < 0) {
9468 error_setg(errp, "ERROR initializing PowerPC instruction "
9469 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
9470 opc->opc3);
9471 return;
9472 }
9473 }
9474 }
9475 fix_opcode_tables(env->opcodes);
9476 fflush(stdout);
9477 fflush(stderr);
9478 }
9479
9480 #if defined(PPC_DUMP_CPU)
9481 static void dump_ppc_insns (CPUPPCState *env)
9482 {
9483 opc_handler_t **table, *handler;
9484 const char *p, *q;
9485 uint8_t opc1, opc2, opc3;
9486
9487 printf("Instructions set:\n");
9488 /* opc1 is 6 bits long */
9489 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9490 table = env->opcodes;
9491 handler = table[opc1];
9492 if (is_indirect_opcode(handler)) {
9493 /* opc2 is 5 bits long */
9494 for (opc2 = 0; opc2 < 0x20; opc2++) {
9495 table = env->opcodes;
9496 handler = env->opcodes[opc1];
9497 table = ind_table(handler);
9498 handler = table[opc2];
9499 if (is_indirect_opcode(handler)) {
9500 table = ind_table(handler);
9501 /* opc3 is 5 bits long */
9502 for (opc3 = 0; opc3 < 0x20; opc3++) {
9503 handler = table[opc3];
9504 if (handler->handler != &gen_invalid) {
9505 /* Special hack to properly dump SPE insns */
9506 p = strchr(handler->oname, '_');
9507 if (p == NULL) {
9508 printf("INSN: %02x %02x %02x (%02d %04d) : "
9509 "%s\n",
9510 opc1, opc2, opc3, opc1,
9511 (opc3 << 5) | opc2,
9512 handler->oname);
9513 } else {
9514 q = "speundef";
9515 if ((p - handler->oname) != strlen(q) ||
9516 memcmp(handler->oname, q, strlen(q)) != 0) {
9517 /* First instruction */
9518 printf("INSN: %02x %02x %02x (%02d %04d) : "
9519 "%.*s\n",
9520 opc1, opc2 << 1, opc3, opc1,
9521 (opc3 << 6) | (opc2 << 1),
9522 (int)(p - handler->oname),
9523 handler->oname);
9524 }
9525 if (strcmp(p + 1, q) != 0) {
9526 /* Second instruction */
9527 printf("INSN: %02x %02x %02x (%02d %04d) : "
9528 "%s\n",
9529 opc1, (opc2 << 1) | 1, opc3, opc1,
9530 (opc3 << 6) | (opc2 << 1) | 1,
9531 p + 1);
9532 }
9533 }
9534 }
9535 }
9536 } else {
9537 if (handler->handler != &gen_invalid) {
9538 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9539 opc1, opc2, opc1, opc2, handler->oname);
9540 }
9541 }
9542 }
9543 } else {
9544 if (handler->handler != &gen_invalid) {
9545 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9546 opc1, opc1, handler->oname);
9547 }
9548 }
9549 }
9550 }
9551 #endif
9552
9553 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9554 {
9555 if (n < 32) {
9556 stfq_p(mem_buf, env->fpr[n]);
9557 return 8;
9558 }
9559 if (n == 32) {
9560 stl_p(mem_buf, env->fpscr);
9561 return 4;
9562 }
9563 return 0;
9564 }
9565
9566 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9567 {
9568 if (n < 32) {
9569 env->fpr[n] = ldfq_p(mem_buf);
9570 return 8;
9571 }
9572 if (n == 32) {
9573 /* FPSCR not implemented */
9574 return 4;
9575 }
9576 return 0;
9577 }
9578
9579 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9580 {
9581 if (n < 32) {
9582 #ifdef HOST_WORDS_BIGENDIAN
9583 stq_p(mem_buf, env->avr[n].u64[0]);
9584 stq_p(mem_buf+8, env->avr[n].u64[1]);
9585 #else
9586 stq_p(mem_buf, env->avr[n].u64[1]);
9587 stq_p(mem_buf+8, env->avr[n].u64[0]);
9588 #endif
9589 return 16;
9590 }
9591 if (n == 32) {
9592 stl_p(mem_buf, env->vscr);
9593 return 4;
9594 }
9595 if (n == 33) {
9596 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9597 return 4;
9598 }
9599 return 0;
9600 }
9601
9602 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9603 {
9604 if (n < 32) {
9605 #ifdef HOST_WORDS_BIGENDIAN
9606 env->avr[n].u64[0] = ldq_p(mem_buf);
9607 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9608 #else
9609 env->avr[n].u64[1] = ldq_p(mem_buf);
9610 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9611 #endif
9612 return 16;
9613 }
9614 if (n == 32) {
9615 env->vscr = ldl_p(mem_buf);
9616 return 4;
9617 }
9618 if (n == 33) {
9619 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9620 return 4;
9621 }
9622 return 0;
9623 }
9624
9625 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9626 {
9627 if (n < 32) {
9628 #if defined(TARGET_PPC64)
9629 stl_p(mem_buf, env->gpr[n] >> 32);
9630 #else
9631 stl_p(mem_buf, env->gprh[n]);
9632 #endif
9633 return 4;
9634 }
9635 if (n == 32) {
9636 stq_p(mem_buf, env->spe_acc);
9637 return 8;
9638 }
9639 if (n == 33) {
9640 stl_p(mem_buf, env->spe_fscr);
9641 return 4;
9642 }
9643 return 0;
9644 }
9645
9646 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9647 {
9648 if (n < 32) {
9649 #if defined(TARGET_PPC64)
9650 target_ulong lo = (uint32_t)env->gpr[n];
9651 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9652 env->gpr[n] = lo | hi;
9653 #else
9654 env->gprh[n] = ldl_p(mem_buf);
9655 #endif
9656 return 4;
9657 }
9658 if (n == 32) {
9659 env->spe_acc = ldq_p(mem_buf);
9660 return 8;
9661 }
9662 if (n == 33) {
9663 env->spe_fscr = ldl_p(mem_buf);
9664 return 4;
9665 }
9666 return 0;
9667 }
9668
9669 static int ppc_fixup_cpu(PowerPCCPU *cpu)
9670 {
9671 CPUPPCState *env = &cpu->env;
9672
9673 /* TCG doesn't (yet) emulate some groups of instructions that
9674 * are implemented on some otherwise supported CPUs (e.g. VSX
9675 * and decimal floating point instructions on POWER7). We
9676 * remove unsupported instruction groups from the cpu state's
9677 * instruction masks and hope the guest can cope. For at
9678 * least the pseries machine, the unavailability of these
9679 * instructions can be advertised to the guest via the device
9680 * tree. */
9681 if ((env->insns_flags & ~PPC_TCG_INSNS)
9682 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
9683 fprintf(stderr, "Warning: Disabling some instructions which are not "
9684 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
9685 env->insns_flags & ~PPC_TCG_INSNS,
9686 env->insns_flags2 & ~PPC_TCG_INSNS2);
9687 }
9688 env->insns_flags &= PPC_TCG_INSNS;
9689 env->insns_flags2 &= PPC_TCG_INSNS2;
9690 return 0;
9691 }
9692
9693 static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
9694 {
9695 PowerPCCPU *cpu = POWERPC_CPU(dev);
9696 CPUPPCState *env = &cpu->env;
9697 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9698 ppc_def_t *def = pcc->info;
9699 Error *local_err = NULL;
9700 #if !defined(CONFIG_USER_ONLY)
9701 int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
9702 #endif
9703
9704 #if !defined(CONFIG_USER_ONLY)
9705 if (smp_threads > max_smt) {
9706 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
9707 max_smt, kvm_enabled() ? "KVM" : "TCG");
9708 return;
9709 }
9710 #endif
9711
9712 if (kvm_enabled()) {
9713 if (kvmppc_fixup_cpu(cpu) != 0) {
9714 error_setg(errp, "Unable to virtualize selected CPU with KVM");
9715 return;
9716 }
9717 } else {
9718 if (ppc_fixup_cpu(cpu) != 0) {
9719 error_setg(errp, "Unable to emulate selected CPU with TCG");
9720 return;
9721 }
9722 }
9723
9724 create_ppc_opcodes(cpu, &local_err);
9725 if (local_err != NULL) {
9726 error_propagate(errp, local_err);
9727 return;
9728 }
9729 init_ppc_proc(env, def);
9730
9731 if (def->insns_flags & PPC_FLOAT) {
9732 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9733 33, "power-fpu.xml", 0);
9734 }
9735 if (def->insns_flags & PPC_ALTIVEC) {
9736 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9737 34, "power-altivec.xml", 0);
9738 }
9739 if (def->insns_flags & PPC_SPE) {
9740 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9741 34, "power-spe.xml", 0);
9742 }
9743
9744 qemu_init_vcpu(env);
9745
9746 pcc->parent_realize(dev, errp);
9747
9748 #if defined(PPC_DUMP_CPU)
9749 {
9750 const char *mmu_model, *excp_model, *bus_model;
9751 switch (env->mmu_model) {
9752 case POWERPC_MMU_32B:
9753 mmu_model = "PowerPC 32";
9754 break;
9755 case POWERPC_MMU_SOFT_6xx:
9756 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9757 break;
9758 case POWERPC_MMU_SOFT_74xx:
9759 mmu_model = "PowerPC 74xx with software driven TLBs";
9760 break;
9761 case POWERPC_MMU_SOFT_4xx:
9762 mmu_model = "PowerPC 4xx with software driven TLBs";
9763 break;
9764 case POWERPC_MMU_SOFT_4xx_Z:
9765 mmu_model = "PowerPC 4xx with software driven TLBs "
9766 "and zones protections";
9767 break;
9768 case POWERPC_MMU_REAL:
9769 mmu_model = "PowerPC real mode only";
9770 break;
9771 case POWERPC_MMU_MPC8xx:
9772 mmu_model = "PowerPC MPC8xx";
9773 break;
9774 case POWERPC_MMU_BOOKE:
9775 mmu_model = "PowerPC BookE";
9776 break;
9777 case POWERPC_MMU_BOOKE206:
9778 mmu_model = "PowerPC BookE 2.06";
9779 break;
9780 case POWERPC_MMU_601:
9781 mmu_model = "PowerPC 601";
9782 break;
9783 #if defined (TARGET_PPC64)
9784 case POWERPC_MMU_64B:
9785 mmu_model = "PowerPC 64";
9786 break;
9787 case POWERPC_MMU_620:
9788 mmu_model = "PowerPC 620";
9789 break;
9790 #endif
9791 default:
9792 mmu_model = "Unknown or invalid";
9793 break;
9794 }
9795 switch (env->excp_model) {
9796 case POWERPC_EXCP_STD:
9797 excp_model = "PowerPC";
9798 break;
9799 case POWERPC_EXCP_40x:
9800 excp_model = "PowerPC 40x";
9801 break;
9802 case POWERPC_EXCP_601:
9803 excp_model = "PowerPC 601";
9804 break;
9805 case POWERPC_EXCP_602:
9806 excp_model = "PowerPC 602";
9807 break;
9808 case POWERPC_EXCP_603:
9809 excp_model = "PowerPC 603";
9810 break;
9811 case POWERPC_EXCP_603E:
9812 excp_model = "PowerPC 603e";
9813 break;
9814 case POWERPC_EXCP_604:
9815 excp_model = "PowerPC 604";
9816 break;
9817 case POWERPC_EXCP_7x0:
9818 excp_model = "PowerPC 740/750";
9819 break;
9820 case POWERPC_EXCP_7x5:
9821 excp_model = "PowerPC 745/755";
9822 break;
9823 case POWERPC_EXCP_74xx:
9824 excp_model = "PowerPC 74xx";
9825 break;
9826 case POWERPC_EXCP_BOOKE:
9827 excp_model = "PowerPC BookE";
9828 break;
9829 #if defined (TARGET_PPC64)
9830 case POWERPC_EXCP_970:
9831 excp_model = "PowerPC 970";
9832 break;
9833 #endif
9834 default:
9835 excp_model = "Unknown or invalid";
9836 break;
9837 }
9838 switch (env->bus_model) {
9839 case PPC_FLAGS_INPUT_6xx:
9840 bus_model = "PowerPC 6xx";
9841 break;
9842 case PPC_FLAGS_INPUT_BookE:
9843 bus_model = "PowerPC BookE";
9844 break;
9845 case PPC_FLAGS_INPUT_405:
9846 bus_model = "PowerPC 405";
9847 break;
9848 case PPC_FLAGS_INPUT_401:
9849 bus_model = "PowerPC 401/403";
9850 break;
9851 case PPC_FLAGS_INPUT_RCPU:
9852 bus_model = "RCPU / MPC8xx";
9853 break;
9854 #if defined (TARGET_PPC64)
9855 case PPC_FLAGS_INPUT_970:
9856 bus_model = "PowerPC 970";
9857 break;
9858 #endif
9859 default:
9860 bus_model = "Unknown or invalid";
9861 break;
9862 }
9863 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9864 " MMU model : %s\n",
9865 def->name, def->pvr, def->msr_mask, mmu_model);
9866 #if !defined(CONFIG_USER_ONLY)
9867 if (env->tlb != NULL) {
9868 printf(" %d %s TLB in %d ways\n",
9869 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9870 env->nb_ways);
9871 }
9872 #endif
9873 printf(" Exceptions model : %s\n"
9874 " Bus model : %s\n",
9875 excp_model, bus_model);
9876 printf(" MSR features :\n");
9877 if (env->flags & POWERPC_FLAG_SPE)
9878 printf(" signal processing engine enable"
9879 "\n");
9880 else if (env->flags & POWERPC_FLAG_VRE)
9881 printf(" vector processor enable\n");
9882 if (env->flags & POWERPC_FLAG_TGPR)
9883 printf(" temporary GPRs\n");
9884 else if (env->flags & POWERPC_FLAG_CE)
9885 printf(" critical input enable\n");
9886 if (env->flags & POWERPC_FLAG_SE)
9887 printf(" single-step trace mode\n");
9888 else if (env->flags & POWERPC_FLAG_DWE)
9889 printf(" debug wait enable\n");
9890 else if (env->flags & POWERPC_FLAG_UBLE)
9891 printf(" user BTB lock enable\n");
9892 if (env->flags & POWERPC_FLAG_BE)
9893 printf(" branch-step trace mode\n");
9894 else if (env->flags & POWERPC_FLAG_DE)
9895 printf(" debug interrupt enable\n");
9896 if (env->flags & POWERPC_FLAG_PX)
9897 printf(" inclusive protection\n");
9898 else if (env->flags & POWERPC_FLAG_PMM)
9899 printf(" performance monitor mark\n");
9900 if (env->flags == POWERPC_FLAG_NONE)
9901 printf(" none\n");
9902 printf(" Time-base/decrementer clock source: %s\n",
9903 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
9904 }
9905 dump_ppc_insns(env);
9906 dump_ppc_sprs(env);
9907 fflush(stdout);
9908 #endif
9909 }
9910
9911 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
9912 {
9913 ObjectClass *oc = (ObjectClass *)a;
9914 uint32_t pvr = *(uint32_t *)b;
9915 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
9916
9917 /* -cpu host does a PVR lookup during construction */
9918 if (unlikely(strcmp(object_class_get_name(oc),
9919 TYPE_HOST_POWERPC_CPU) == 0)) {
9920 return -1;
9921 }
9922
9923 return pcc->info->pvr == pvr ? 0 : -1;
9924 }
9925
9926 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
9927 {
9928 GSList *list, *item;
9929 PowerPCCPUClass *pcc = NULL;
9930
9931 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9932 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
9933 if (item != NULL) {
9934 pcc = POWERPC_CPU_CLASS(item->data);
9935 }
9936 g_slist_free(list);
9937
9938 return pcc;
9939 }
9940
9941 static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
9942 {
9943 ObjectClass *oc = (ObjectClass *)a;
9944 const char *name = b;
9945
9946 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
9947 strcmp(object_class_get_name(oc) + strlen(name),
9948 "-" TYPE_POWERPC_CPU) == 0) {
9949 return 0;
9950 }
9951 return -1;
9952 }
9953
9954 #include <ctype.h>
9955
9956 static ObjectClass *ppc_cpu_class_by_name(const char *name)
9957 {
9958 GSList *list, *item;
9959 ObjectClass *ret = NULL;
9960 const char *p;
9961 int i, len;
9962
9963 if (strcasecmp(name, "host") == 0) {
9964 if (kvm_enabled()) {
9965 ret = object_class_by_name(TYPE_HOST_POWERPC_CPU);
9966 }
9967 return ret;
9968 }
9969
9970 /* Check if the given name is a PVR */
9971 len = strlen(name);
9972 if (len == 10 && name[0] == '0' && name[1] == 'x') {
9973 p = name + 2;
9974 goto check_pvr;
9975 } else if (len == 8) {
9976 p = name;
9977 check_pvr:
9978 for (i = 0; i < 8; i++) {
9979 if (!qemu_isxdigit(*p++))
9980 break;
9981 }
9982 if (i == 8) {
9983 ret = OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
9984 return ret;
9985 }
9986 }
9987
9988 for (i = 0; i < ARRAY_SIZE(ppc_cpu_aliases); i++) {
9989 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
9990 return ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
9991 }
9992 }
9993
9994 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9995 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
9996 if (item != NULL) {
9997 ret = OBJECT_CLASS(item->data);
9998 }
9999 g_slist_free(list);
10000
10001 return ret;
10002 }
10003
10004 PowerPCCPU *cpu_ppc_init(const char *cpu_model)
10005 {
10006 PowerPCCPU *cpu;
10007 CPUPPCState *env;
10008 ObjectClass *oc;
10009 Error *err = NULL;
10010
10011 oc = ppc_cpu_class_by_name(cpu_model);
10012 if (oc == NULL) {
10013 return NULL;
10014 }
10015
10016 cpu = POWERPC_CPU(object_new(object_class_get_name(oc)));
10017 env = &cpu->env;
10018 env->cpu_model_str = cpu_model;
10019
10020 object_property_set_bool(OBJECT(cpu), true, "realized", &err);
10021 if (err != NULL) {
10022 fprintf(stderr, "%s\n", error_get_pretty(err));
10023 error_free(err);
10024 object_unref(OBJECT(cpu));
10025 return NULL;
10026 }
10027
10028 return cpu;
10029 }
10030
10031 /* Sort by PVR, ordering special case "host" last. */
10032 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
10033 {
10034 ObjectClass *oc_a = (ObjectClass *)a;
10035 ObjectClass *oc_b = (ObjectClass *)b;
10036 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
10037 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
10038 const char *name_a = object_class_get_name(oc_a);
10039 const char *name_b = object_class_get_name(oc_b);
10040
10041 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
10042 return 1;
10043 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
10044 return -1;
10045 } else {
10046 /* Avoid an integer overflow during subtraction */
10047 if (pcc_a->info->pvr < pcc_b->info->pvr) {
10048 return -1;
10049 } else if (pcc_a->info->pvr > pcc_b->info->pvr) {
10050 return 1;
10051 } else {
10052 return 0;
10053 }
10054 }
10055 }
10056
10057 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
10058 {
10059 ObjectClass *oc = data;
10060 CPUListState *s = user_data;
10061 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10062
10063 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
10064 pcc->info->name, pcc->info->pvr);
10065 }
10066
10067 void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
10068 {
10069 CPUListState s = {
10070 .file = f,
10071 .cpu_fprintf = cpu_fprintf,
10072 };
10073 GSList *list;
10074 int i;
10075
10076 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10077 list = g_slist_sort(list, ppc_cpu_list_compare);
10078 g_slist_foreach(list, ppc_cpu_list_entry, &s);
10079 g_slist_free(list);
10080
10081 cpu_fprintf(f, "\n");
10082 for (i = 0; i < ARRAY_SIZE(ppc_cpu_aliases); i++) {
10083 ObjectClass *oc = ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
10084 if (oc == NULL) {
10085 /* Hide aliases that point to a TODO or TODO_USER_ONLY model */
10086 continue;
10087 }
10088 cpu_fprintf(f, "PowerPC %-16s\n",
10089 ppc_cpu_aliases[i].alias);
10090 }
10091 }
10092
10093 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
10094 {
10095 ObjectClass *oc = data;
10096 CpuDefinitionInfoList **first = user_data;
10097 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10098 CpuDefinitionInfoList *entry;
10099 CpuDefinitionInfo *info;
10100
10101 info = g_malloc0(sizeof(*info));
10102 info->name = g_strdup(pcc->info->name);
10103
10104 entry = g_malloc0(sizeof(*entry));
10105 entry->value = info;
10106 entry->next = *first;
10107 *first = entry;
10108 }
10109
10110 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
10111 {
10112 CpuDefinitionInfoList *cpu_list = NULL;
10113 GSList *list;
10114
10115 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10116 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
10117 g_slist_free(list);
10118
10119 return cpu_list;
10120 }
10121
10122 static void ppc_cpu_def_class_init(ObjectClass *oc, void *data)
10123 {
10124 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10125 ppc_def_t *info = data;
10126
10127 pcc->info = info;
10128 }
10129
10130 static void ppc_cpu_register_model(const ppc_def_t *def)
10131 {
10132 TypeInfo type_info = {
10133 .parent = TYPE_POWERPC_CPU,
10134 .class_init = ppc_cpu_def_class_init,
10135 .class_data = (void *)def,
10136 };
10137
10138 type_info.name = g_strdup_printf("%s-" TYPE_POWERPC_CPU, def->name),
10139 type_register(&type_info);
10140 g_free((gpointer)type_info.name);
10141 }
10142
10143 /* CPUClass::reset() */
10144 static void ppc_cpu_reset(CPUState *s)
10145 {
10146 PowerPCCPU *cpu = POWERPC_CPU(s);
10147 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10148 CPUPPCState *env = &cpu->env;
10149 target_ulong msr;
10150
10151 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
10152 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
10153 log_cpu_state(env, 0);
10154 }
10155
10156 pcc->parent_reset(s);
10157
10158 msr = (target_ulong)0;
10159 if (0) {
10160 /* XXX: find a suitable condition to enable the hypervisor mode */
10161 msr |= (target_ulong)MSR_HVB;
10162 }
10163 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
10164 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
10165 msr |= (target_ulong)1 << MSR_EP;
10166 #if defined(DO_SINGLE_STEP) && 0
10167 /* Single step trace mode */
10168 msr |= (target_ulong)1 << MSR_SE;
10169 msr |= (target_ulong)1 << MSR_BE;
10170 #endif
10171 #if defined(CONFIG_USER_ONLY)
10172 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
10173 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
10174 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
10175 msr |= (target_ulong)1 << MSR_PR;
10176 #else
10177 env->excp_prefix = env->hreset_excp_prefix;
10178 env->nip = env->hreset_vector | env->excp_prefix;
10179 if (env->mmu_model != POWERPC_MMU_REAL) {
10180 ppc_tlb_invalidate_all(env);
10181 }
10182 #endif
10183 env->msr = msr & env->msr_mask;
10184 #if defined(TARGET_PPC64)
10185 if (env->mmu_model & POWERPC_MMU_64) {
10186 env->msr |= (1ULL << MSR_SF);
10187 }
10188 #endif
10189 hreg_compute_hflags(env);
10190 env->reserve_addr = (target_ulong)-1ULL;
10191 /* Be sure no exception or interrupt is pending */
10192 env->pending_interrupts = 0;
10193 env->exception_index = POWERPC_EXCP_NONE;
10194 env->error_code = 0;
10195
10196 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
10197 env->vpa_addr = 0;
10198 env->slb_shadow_addr = 0;
10199 env->slb_shadow_size = 0;
10200 env->dtl_addr = 0;
10201 env->dtl_size = 0;
10202 #endif /* TARGET_PPC64 */
10203
10204 /* Flush all TLBs */
10205 tlb_flush(env, 1);
10206 }
10207
10208 static void ppc_cpu_initfn(Object *obj)
10209 {
10210 CPUState *cs = CPU(obj);
10211 PowerPCCPU *cpu = POWERPC_CPU(obj);
10212 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10213 CPUPPCState *env = &cpu->env;
10214 ppc_def_t *def = pcc->info;
10215
10216 cs->env_ptr = env;
10217 cpu_exec_init(env);
10218
10219 env->msr_mask = def->msr_mask;
10220 env->mmu_model = def->mmu_model;
10221 env->excp_model = def->excp_model;
10222 env->bus_model = def->bus_model;
10223 env->insns_flags = def->insns_flags;
10224 env->insns_flags2 = def->insns_flags2;
10225 env->flags = def->flags;
10226 env->bfd_mach = def->bfd_mach;
10227 env->check_pow = def->check_pow;
10228
10229 #if defined(TARGET_PPC64)
10230 if (def->sps) {
10231 env->sps = *def->sps;
10232 } else if (env->mmu_model & POWERPC_MMU_64) {
10233 /* Use default sets of page sizes */
10234 static const struct ppc_segment_page_sizes defsps = {
10235 .sps = {
10236 { .page_shift = 12, /* 4K */
10237 .slb_enc = 0,
10238 .enc = { { .page_shift = 12, .pte_enc = 0 } }
10239 },
10240 { .page_shift = 24, /* 16M */
10241 .slb_enc = 0x100,
10242 .enc = { { .page_shift = 24, .pte_enc = 0 } }
10243 },
10244 },
10245 };
10246 env->sps = defsps;
10247 }
10248 #endif /* defined(TARGET_PPC64) */
10249
10250 if (tcg_enabled()) {
10251 ppc_translate_init();
10252 }
10253 }
10254
10255 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
10256 {
10257 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10258 CPUClass *cc = CPU_CLASS(oc);
10259 DeviceClass *dc = DEVICE_CLASS(oc);
10260
10261 pcc->parent_realize = dc->realize;
10262 dc->realize = ppc_cpu_realizefn;
10263
10264 pcc->parent_reset = cc->reset;
10265 cc->reset = ppc_cpu_reset;
10266
10267 cc->class_by_name = ppc_cpu_class_by_name;
10268 }
10269
10270 static const TypeInfo ppc_cpu_type_info = {
10271 .name = TYPE_POWERPC_CPU,
10272 .parent = TYPE_CPU,
10273 .instance_size = sizeof(PowerPCCPU),
10274 .instance_init = ppc_cpu_initfn,
10275 .abstract = true,
10276 .class_size = sizeof(PowerPCCPUClass),
10277 .class_init = ppc_cpu_class_init,
10278 };
10279
10280 static void ppc_cpu_register_types(void)
10281 {
10282 int i;
10283
10284 type_register_static(&ppc_cpu_type_info);
10285
10286 for (i = 0; i < ARRAY_SIZE(ppc_defs); i++) {
10287 const ppc_def_t *def = &ppc_defs[i];
10288 #if defined(TARGET_PPCEMB)
10289 /* When using the ppcemb target, we only support 440 style cores */
10290 if (def->mmu_model != POWERPC_MMU_BOOKE) {
10291 continue;
10292 }
10293 #endif
10294 ppc_cpu_register_model(def);
10295 }
10296 }
10297
10298 type_init(ppc_cpu_register_types)
Qemu copy for testing