]> git.proxmox.com Git - qemu.git/blob - target-ppc/translate_init.c
projects / qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
target-ppc: Split model definitions out of translate_init.c
[qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "disas/bfd.h"
22 #include "exec/gdbstub.h"
23 #include <sysemu/kvm.h>
24 #include "kvm_ppc.h"
25 #include "sysemu/arch_init.h"
26 #include "sysemu/cpus.h"
27 #include "cpu-models.h"
28
29 //#define PPC_DUMP_CPU
30 //#define PPC_DEBUG_SPR
31 //#define PPC_DUMP_SPR_ACCESSES
32
33 /* For user-mode emulation, we don't emulate any IRQ controller */
34 #if defined(CONFIG_USER_ONLY)
35 #define PPC_IRQ_INIT_FN(name) \
36 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
37 { \
38 }
39 #else
40 #define PPC_IRQ_INIT_FN(name) \
41 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
42 #endif
43
44 PPC_IRQ_INIT_FN(40x);
45 PPC_IRQ_INIT_FN(6xx);
46 PPC_IRQ_INIT_FN(970);
47 PPC_IRQ_INIT_FN(POWER7);
48 PPC_IRQ_INIT_FN(e500);
49
50 /* Generic callbacks:
51 * do nothing but store/retrieve spr value
52 */
53 static void spr_load_dump_spr(int sprn)
54 {
55 #ifdef PPC_DUMP_SPR_ACCESSES
56 TCGv_i32 t0 = tcg_const_i32(sprn);
57 gen_helper_load_dump_spr(t0);
58 tcg_temp_free_i32(t0);
59 #endif
60 }
61
62 static void spr_read_generic (void *opaque, int gprn, int sprn)
63 {
64 gen_load_spr(cpu_gpr[gprn], sprn);
65 spr_load_dump_spr(sprn);
66 }
67
68 static void spr_store_dump_spr(int sprn)
69 {
70 #ifdef PPC_DUMP_SPR_ACCESSES
71 TCGv_i32 t0 = tcg_const_i32(sprn);
72 gen_helper_store_dump_spr(t0);
73 tcg_temp_free_i32(t0);
74 #endif
75 }
76
77 static void spr_write_generic (void *opaque, int sprn, int gprn)
78 {
79 gen_store_spr(sprn, cpu_gpr[gprn]);
80 spr_store_dump_spr(sprn);
81 }
82
83 #if !defined(CONFIG_USER_ONLY)
84 static void spr_write_generic32(void *opaque, int sprn, int gprn)
85 {
86 #ifdef TARGET_PPC64
87 TCGv t0 = tcg_temp_new();
88 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
89 gen_store_spr(sprn, t0);
90 tcg_temp_free(t0);
91 spr_store_dump_spr(sprn);
92 #else
93 spr_write_generic(opaque, sprn, gprn);
94 #endif
95 }
96
97 static void spr_write_clear (void *opaque, int sprn, int gprn)
98 {
99 TCGv t0 = tcg_temp_new();
100 TCGv t1 = tcg_temp_new();
101 gen_load_spr(t0, sprn);
102 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
103 tcg_gen_and_tl(t0, t0, t1);
104 gen_store_spr(sprn, t0);
105 tcg_temp_free(t0);
106 tcg_temp_free(t1);
107 }
108 #endif
109
110 /* SPR common to all PowerPC */
111 /* XER */
112 static void spr_read_xer (void *opaque, int gprn, int sprn)
113 {
114 gen_read_xer(cpu_gpr[gprn]);
115 }
116
117 static void spr_write_xer (void *opaque, int sprn, int gprn)
118 {
119 gen_write_xer(cpu_gpr[gprn]);
120 }
121
122 /* LR */
123 static void spr_read_lr (void *opaque, int gprn, int sprn)
124 {
125 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
126 }
127
128 static void spr_write_lr (void *opaque, int sprn, int gprn)
129 {
130 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
131 }
132
133 /* CFAR */
134 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
135 static void spr_read_cfar (void *opaque, int gprn, int sprn)
136 {
137 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
138 }
139
140 static void spr_write_cfar (void *opaque, int sprn, int gprn)
141 {
142 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
143 }
144 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
145
146 /* CTR */
147 static void spr_read_ctr (void *opaque, int gprn, int sprn)
148 {
149 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
150 }
151
152 static void spr_write_ctr (void *opaque, int sprn, int gprn)
153 {
154 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
155 }
156
157 /* User read access to SPR */
158 /* USPRx */
159 /* UMMCRx */
160 /* UPMCx */
161 /* USIA */
162 /* UDECR */
163 static void spr_read_ureg (void *opaque, int gprn, int sprn)
164 {
165 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
166 }
167
168 /* SPR common to all non-embedded PowerPC */
169 /* DECR */
170 #if !defined(CONFIG_USER_ONLY)
171 static void spr_read_decr (void *opaque, int gprn, int sprn)
172 {
173 if (use_icount) {
174 gen_io_start();
175 }
176 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
177 if (use_icount) {
178 gen_io_end();
179 gen_stop_exception(opaque);
180 }
181 }
182
183 static void spr_write_decr (void *opaque, int sprn, int gprn)
184 {
185 if (use_icount) {
186 gen_io_start();
187 }
188 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
189 if (use_icount) {
190 gen_io_end();
191 gen_stop_exception(opaque);
192 }
193 }
194 #endif
195
196 /* SPR common to all non-embedded PowerPC, except 601 */
197 /* Time base */
198 static void spr_read_tbl (void *opaque, int gprn, int sprn)
199 {
200 if (use_icount) {
201 gen_io_start();
202 }
203 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
204 if (use_icount) {
205 gen_io_end();
206 gen_stop_exception(opaque);
207 }
208 }
209
210 static void spr_read_tbu (void *opaque, int gprn, int sprn)
211 {
212 if (use_icount) {
213 gen_io_start();
214 }
215 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
216 if (use_icount) {
217 gen_io_end();
218 gen_stop_exception(opaque);
219 }
220 }
221
222 __attribute__ (( unused ))
223 static void spr_read_atbl (void *opaque, int gprn, int sprn)
224 {
225 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
226 }
227
228 __attribute__ (( unused ))
229 static void spr_read_atbu (void *opaque, int gprn, int sprn)
230 {
231 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
232 }
233
234 #if !defined(CONFIG_USER_ONLY)
235 static void spr_write_tbl (void *opaque, int sprn, int gprn)
236 {
237 if (use_icount) {
238 gen_io_start();
239 }
240 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
241 if (use_icount) {
242 gen_io_end();
243 gen_stop_exception(opaque);
244 }
245 }
246
247 static void spr_write_tbu (void *opaque, int sprn, int gprn)
248 {
249 if (use_icount) {
250 gen_io_start();
251 }
252 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
253 if (use_icount) {
254 gen_io_end();
255 gen_stop_exception(opaque);
256 }
257 }
258
259 __attribute__ (( unused ))
260 static void spr_write_atbl (void *opaque, int sprn, int gprn)
261 {
262 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
263 }
264
265 __attribute__ (( unused ))
266 static void spr_write_atbu (void *opaque, int sprn, int gprn)
267 {
268 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
269 }
270
271 #if defined(TARGET_PPC64)
272 __attribute__ (( unused ))
273 static void spr_read_purr (void *opaque, int gprn, int sprn)
274 {
275 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
276 }
277 #endif
278 #endif
279
280 #if !defined(CONFIG_USER_ONLY)
281 /* IBAT0U...IBAT0U */
282 /* IBAT0L...IBAT7L */
283 static void spr_read_ibat (void *opaque, int gprn, int sprn)
284 {
285 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
286 }
287
288 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
289 {
290 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
291 }
292
293 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
294 {
295 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
296 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
297 tcg_temp_free_i32(t0);
298 }
299
300 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
301 {
302 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
303 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
304 tcg_temp_free_i32(t0);
305 }
306
307 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
308 {
309 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
310 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
311 tcg_temp_free_i32(t0);
312 }
313
314 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
315 {
316 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
317 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
318 tcg_temp_free_i32(t0);
319 }
320
321 /* DBAT0U...DBAT7U */
322 /* DBAT0L...DBAT7L */
323 static void spr_read_dbat (void *opaque, int gprn, int sprn)
324 {
325 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
326 }
327
328 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
329 {
330 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
331 }
332
333 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
334 {
335 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
336 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
337 tcg_temp_free_i32(t0);
338 }
339
340 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
341 {
342 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
343 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
344 tcg_temp_free_i32(t0);
345 }
346
347 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
348 {
349 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
350 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
351 tcg_temp_free_i32(t0);
352 }
353
354 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
355 {
356 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
357 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
358 tcg_temp_free_i32(t0);
359 }
360
361 /* SDR1 */
362 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
363 {
364 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
365 }
366
367 /* 64 bits PowerPC specific SPRs */
368 /* ASR */
369 #if defined(TARGET_PPC64)
370 static void spr_read_hior (void *opaque, int gprn, int sprn)
371 {
372 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
373 }
374
375 static void spr_write_hior (void *opaque, int sprn, int gprn)
376 {
377 TCGv t0 = tcg_temp_new();
378 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
379 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
380 tcg_temp_free(t0);
381 }
382
383 static void spr_read_asr (void *opaque, int gprn, int sprn)
384 {
385 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, asr));
386 }
387
388 static void spr_write_asr (void *opaque, int sprn, int gprn)
389 {
390 gen_helper_store_asr(cpu_env, cpu_gpr[gprn]);
391 }
392 #endif
393 #endif
394
395 /* PowerPC 601 specific registers */
396 /* RTC */
397 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
398 {
399 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
400 }
401
402 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
403 {
404 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
405 }
406
407 #if !defined(CONFIG_USER_ONLY)
408 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
409 {
410 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
411 }
412
413 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
414 {
415 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
416 }
417
418 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
419 {
420 DisasContext *ctx = opaque;
421
422 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
423 /* Must stop the translation as endianness may have changed */
424 gen_stop_exception(ctx);
425 }
426 #endif
427
428 /* Unified bats */
429 #if !defined(CONFIG_USER_ONLY)
430 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
431 {
432 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
433 }
434
435 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
436 {
437 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
438 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
439 tcg_temp_free_i32(t0);
440 }
441
442 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
443 {
444 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
445 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
446 tcg_temp_free_i32(t0);
447 }
448 #endif
449
450 /* PowerPC 40x specific registers */
451 #if !defined(CONFIG_USER_ONLY)
452 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
453 {
454 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
455 }
456
457 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
458 {
459 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
460 }
461
462 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
463 {
464 DisasContext *ctx = opaque;
465
466 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
467 /* We must stop translation as we may have rebooted */
468 gen_stop_exception(ctx);
469 }
470
471 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
472 {
473 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
474 }
475
476 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
477 {
478 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
479 }
480
481 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
482 {
483 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
484 }
485 #endif
486
487 /* PowerPC 403 specific registers */
488 /* PBL1 / PBU1 / PBL2 / PBU2 */
489 #if !defined(CONFIG_USER_ONLY)
490 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
491 {
492 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
493 }
494
495 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
496 {
497 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
498 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
499 tcg_temp_free_i32(t0);
500 }
501
502 static void spr_write_pir (void *opaque, int sprn, int gprn)
503 {
504 TCGv t0 = tcg_temp_new();
505 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
506 gen_store_spr(SPR_PIR, t0);
507 tcg_temp_free(t0);
508 }
509 #endif
510
511 /* SPE specific registers */
512 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
513 {
514 TCGv_i32 t0 = tcg_temp_new_i32();
515 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
516 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
517 tcg_temp_free_i32(t0);
518 }
519
520 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
521 {
522 TCGv_i32 t0 = tcg_temp_new_i32();
523 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
524 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
525 tcg_temp_free_i32(t0);
526 }
527
528 #if !defined(CONFIG_USER_ONLY)
529 /* Callback used to write the exception vector base */
530 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
531 {
532 TCGv t0 = tcg_temp_new();
533 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
534 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
535 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
536 gen_store_spr(sprn, t0);
537 tcg_temp_free(t0);
538 }
539
540 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
541 {
542 DisasContext *ctx = opaque;
543 int sprn_offs;
544
545 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
546 sprn_offs = sprn - SPR_BOOKE_IVOR0;
547 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
548 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
549 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
550 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
551 } else {
552 printf("Trying to write an unknown exception vector %d %03x\n",
553 sprn, sprn);
554 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
555 return;
556 }
557
558 TCGv t0 = tcg_temp_new();
559 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
560 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
561 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
562 gen_store_spr(sprn, t0);
563 tcg_temp_free(t0);
564 }
565 #endif
566
567 static inline void vscr_init (CPUPPCState *env, uint32_t val)
568 {
569 env->vscr = val;
570 /* Altivec always uses round-to-nearest */
571 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
572 set_flush_to_zero(vscr_nj, &env->vec_status);
573 }
574
575 #if defined(CONFIG_USER_ONLY)
576 #define spr_register(env, num, name, uea_read, uea_write, \
577 oea_read, oea_write, initial_value) \
578 do { \
579 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
580 } while (0)
581 static inline void _spr_register (CPUPPCState *env, int num,
582 const char *name,
583 void (*uea_read)(void *opaque, int gprn, int sprn),
584 void (*uea_write)(void *opaque, int sprn, int gprn),
585 target_ulong initial_value)
586 #else
587 static inline void spr_register (CPUPPCState *env, int num,
588 const char *name,
589 void (*uea_read)(void *opaque, int gprn, int sprn),
590 void (*uea_write)(void *opaque, int sprn, int gprn),
591 void (*oea_read)(void *opaque, int gprn, int sprn),
592 void (*oea_write)(void *opaque, int sprn, int gprn),
593 target_ulong initial_value)
594 #endif
595 {
596 ppc_spr_t *spr;
597
598 spr = &env->spr_cb[num];
599 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
600 #if !defined(CONFIG_USER_ONLY)
601 spr->oea_read != NULL || spr->oea_write != NULL ||
602 #endif
603 spr->uea_read != NULL || spr->uea_write != NULL) {
604 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
605 exit(1);
606 }
607 #if defined(PPC_DEBUG_SPR)
608 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
609 name, initial_value);
610 #endif
611 spr->name = name;
612 spr->uea_read = uea_read;
613 spr->uea_write = uea_write;
614 #if !defined(CONFIG_USER_ONLY)
615 spr->oea_read = oea_read;
616 spr->oea_write = oea_write;
617 #endif
618 env->spr[num] = initial_value;
619 }
620
621 /* Generic PowerPC SPRs */
622 static void gen_spr_generic (CPUPPCState *env)
623 {
624 /* Integer processing */
625 spr_register(env, SPR_XER, "XER",
626 &spr_read_xer, &spr_write_xer,
627 &spr_read_xer, &spr_write_xer,
628 0x00000000);
629 /* Branch contol */
630 spr_register(env, SPR_LR, "LR",
631 &spr_read_lr, &spr_write_lr,
632 &spr_read_lr, &spr_write_lr,
633 0x00000000);
634 spr_register(env, SPR_CTR, "CTR",
635 &spr_read_ctr, &spr_write_ctr,
636 &spr_read_ctr, &spr_write_ctr,
637 0x00000000);
638 /* Interrupt processing */
639 spr_register(env, SPR_SRR0, "SRR0",
640 SPR_NOACCESS, SPR_NOACCESS,
641 &spr_read_generic, &spr_write_generic,
642 0x00000000);
643 spr_register(env, SPR_SRR1, "SRR1",
644 SPR_NOACCESS, SPR_NOACCESS,
645 &spr_read_generic, &spr_write_generic,
646 0x00000000);
647 /* Processor control */
648 spr_register(env, SPR_SPRG0, "SPRG0",
649 SPR_NOACCESS, SPR_NOACCESS,
650 &spr_read_generic, &spr_write_generic,
651 0x00000000);
652 spr_register(env, SPR_SPRG1, "SPRG1",
653 SPR_NOACCESS, SPR_NOACCESS,
654 &spr_read_generic, &spr_write_generic,
655 0x00000000);
656 spr_register(env, SPR_SPRG2, "SPRG2",
657 SPR_NOACCESS, SPR_NOACCESS,
658 &spr_read_generic, &spr_write_generic,
659 0x00000000);
660 spr_register(env, SPR_SPRG3, "SPRG3",
661 SPR_NOACCESS, SPR_NOACCESS,
662 &spr_read_generic, &spr_write_generic,
663 0x00000000);
664 }
665
666 /* SPR common to all non-embedded PowerPC, including 601 */
667 static void gen_spr_ne_601 (CPUPPCState *env)
668 {
669 /* Exception processing */
670 spr_register(env, SPR_DSISR, "DSISR",
671 SPR_NOACCESS, SPR_NOACCESS,
672 &spr_read_generic, &spr_write_generic,
673 0x00000000);
674 spr_register(env, SPR_DAR, "DAR",
675 SPR_NOACCESS, SPR_NOACCESS,
676 &spr_read_generic, &spr_write_generic,
677 0x00000000);
678 /* Timer */
679 spr_register(env, SPR_DECR, "DECR",
680 SPR_NOACCESS, SPR_NOACCESS,
681 &spr_read_decr, &spr_write_decr,
682 0x00000000);
683 /* Memory management */
684 spr_register(env, SPR_SDR1, "SDR1",
685 SPR_NOACCESS, SPR_NOACCESS,
686 &spr_read_generic, &spr_write_sdr1,
687 0x00000000);
688 }
689
690 /* BATs 0-3 */
691 static void gen_low_BATs (CPUPPCState *env)
692 {
693 #if !defined(CONFIG_USER_ONLY)
694 spr_register(env, SPR_IBAT0U, "IBAT0U",
695 SPR_NOACCESS, SPR_NOACCESS,
696 &spr_read_ibat, &spr_write_ibatu,
697 0x00000000);
698 spr_register(env, SPR_IBAT0L, "IBAT0L",
699 SPR_NOACCESS, SPR_NOACCESS,
700 &spr_read_ibat, &spr_write_ibatl,
701 0x00000000);
702 spr_register(env, SPR_IBAT1U, "IBAT1U",
703 SPR_NOACCESS, SPR_NOACCESS,
704 &spr_read_ibat, &spr_write_ibatu,
705 0x00000000);
706 spr_register(env, SPR_IBAT1L, "IBAT1L",
707 SPR_NOACCESS, SPR_NOACCESS,
708 &spr_read_ibat, &spr_write_ibatl,
709 0x00000000);
710 spr_register(env, SPR_IBAT2U, "IBAT2U",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_ibat, &spr_write_ibatu,
713 0x00000000);
714 spr_register(env, SPR_IBAT2L, "IBAT2L",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_ibat, &spr_write_ibatl,
717 0x00000000);
718 spr_register(env, SPR_IBAT3U, "IBAT3U",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_ibat, &spr_write_ibatu,
721 0x00000000);
722 spr_register(env, SPR_IBAT3L, "IBAT3L",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_ibat, &spr_write_ibatl,
725 0x00000000);
726 spr_register(env, SPR_DBAT0U, "DBAT0U",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_dbat, &spr_write_dbatu,
729 0x00000000);
730 spr_register(env, SPR_DBAT0L, "DBAT0L",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_dbat, &spr_write_dbatl,
733 0x00000000);
734 spr_register(env, SPR_DBAT1U, "DBAT1U",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_dbat, &spr_write_dbatu,
737 0x00000000);
738 spr_register(env, SPR_DBAT1L, "DBAT1L",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_dbat, &spr_write_dbatl,
741 0x00000000);
742 spr_register(env, SPR_DBAT2U, "DBAT2U",
743 SPR_NOACCESS, SPR_NOACCESS,
744 &spr_read_dbat, &spr_write_dbatu,
745 0x00000000);
746 spr_register(env, SPR_DBAT2L, "DBAT2L",
747 SPR_NOACCESS, SPR_NOACCESS,
748 &spr_read_dbat, &spr_write_dbatl,
749 0x00000000);
750 spr_register(env, SPR_DBAT3U, "DBAT3U",
751 SPR_NOACCESS, SPR_NOACCESS,
752 &spr_read_dbat, &spr_write_dbatu,
753 0x00000000);
754 spr_register(env, SPR_DBAT3L, "DBAT3L",
755 SPR_NOACCESS, SPR_NOACCESS,
756 &spr_read_dbat, &spr_write_dbatl,
757 0x00000000);
758 env->nb_BATs += 4;
759 #endif
760 }
761
762 /* BATs 4-7 */
763 static void gen_high_BATs (CPUPPCState *env)
764 {
765 #if !defined(CONFIG_USER_ONLY)
766 spr_register(env, SPR_IBAT4U, "IBAT4U",
767 SPR_NOACCESS, SPR_NOACCESS,
768 &spr_read_ibat_h, &spr_write_ibatu_h,
769 0x00000000);
770 spr_register(env, SPR_IBAT4L, "IBAT4L",
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_ibat_h, &spr_write_ibatl_h,
773 0x00000000);
774 spr_register(env, SPR_IBAT5U, "IBAT5U",
775 SPR_NOACCESS, SPR_NOACCESS,
776 &spr_read_ibat_h, &spr_write_ibatu_h,
777 0x00000000);
778 spr_register(env, SPR_IBAT5L, "IBAT5L",
779 SPR_NOACCESS, SPR_NOACCESS,
780 &spr_read_ibat_h, &spr_write_ibatl_h,
781 0x00000000);
782 spr_register(env, SPR_IBAT6U, "IBAT6U",
783 SPR_NOACCESS, SPR_NOACCESS,
784 &spr_read_ibat_h, &spr_write_ibatu_h,
785 0x00000000);
786 spr_register(env, SPR_IBAT6L, "IBAT6L",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_ibat_h, &spr_write_ibatl_h,
789 0x00000000);
790 spr_register(env, SPR_IBAT7U, "IBAT7U",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_ibat_h, &spr_write_ibatu_h,
793 0x00000000);
794 spr_register(env, SPR_IBAT7L, "IBAT7L",
795 SPR_NOACCESS, SPR_NOACCESS,
796 &spr_read_ibat_h, &spr_write_ibatl_h,
797 0x00000000);
798 spr_register(env, SPR_DBAT4U, "DBAT4U",
799 SPR_NOACCESS, SPR_NOACCESS,
800 &spr_read_dbat_h, &spr_write_dbatu_h,
801 0x00000000);
802 spr_register(env, SPR_DBAT4L, "DBAT4L",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_dbat_h, &spr_write_dbatl_h,
805 0x00000000);
806 spr_register(env, SPR_DBAT5U, "DBAT5U",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_dbat_h, &spr_write_dbatu_h,
809 0x00000000);
810 spr_register(env, SPR_DBAT5L, "DBAT5L",
811 SPR_NOACCESS, SPR_NOACCESS,
812 &spr_read_dbat_h, &spr_write_dbatl_h,
813 0x00000000);
814 spr_register(env, SPR_DBAT6U, "DBAT6U",
815 SPR_NOACCESS, SPR_NOACCESS,
816 &spr_read_dbat_h, &spr_write_dbatu_h,
817 0x00000000);
818 spr_register(env, SPR_DBAT6L, "DBAT6L",
819 SPR_NOACCESS, SPR_NOACCESS,
820 &spr_read_dbat_h, &spr_write_dbatl_h,
821 0x00000000);
822 spr_register(env, SPR_DBAT7U, "DBAT7U",
823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_dbat_h, &spr_write_dbatu_h,
825 0x00000000);
826 spr_register(env, SPR_DBAT7L, "DBAT7L",
827 SPR_NOACCESS, SPR_NOACCESS,
828 &spr_read_dbat_h, &spr_write_dbatl_h,
829 0x00000000);
830 env->nb_BATs += 4;
831 #endif
832 }
833
834 /* Generic PowerPC time base */
835 static void gen_tbl (CPUPPCState *env)
836 {
837 spr_register(env, SPR_VTBL, "TBL",
838 &spr_read_tbl, SPR_NOACCESS,
839 &spr_read_tbl, SPR_NOACCESS,
840 0x00000000);
841 spr_register(env, SPR_TBL, "TBL",
842 &spr_read_tbl, SPR_NOACCESS,
843 &spr_read_tbl, &spr_write_tbl,
844 0x00000000);
845 spr_register(env, SPR_VTBU, "TBU",
846 &spr_read_tbu, SPR_NOACCESS,
847 &spr_read_tbu, SPR_NOACCESS,
848 0x00000000);
849 spr_register(env, SPR_TBU, "TBU",
850 &spr_read_tbu, SPR_NOACCESS,
851 &spr_read_tbu, &spr_write_tbu,
852 0x00000000);
853 }
854
855 /* Softare table search registers */
856 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
857 {
858 #if !defined(CONFIG_USER_ONLY)
859 env->nb_tlb = nb_tlbs;
860 env->nb_ways = nb_ways;
861 env->id_tlbs = 1;
862 env->tlb_type = TLB_6XX;
863 spr_register(env, SPR_DMISS, "DMISS",
864 SPR_NOACCESS, SPR_NOACCESS,
865 &spr_read_generic, SPR_NOACCESS,
866 0x00000000);
867 spr_register(env, SPR_DCMP, "DCMP",
868 SPR_NOACCESS, SPR_NOACCESS,
869 &spr_read_generic, SPR_NOACCESS,
870 0x00000000);
871 spr_register(env, SPR_HASH1, "HASH1",
872 SPR_NOACCESS, SPR_NOACCESS,
873 &spr_read_generic, SPR_NOACCESS,
874 0x00000000);
875 spr_register(env, SPR_HASH2, "HASH2",
876 SPR_NOACCESS, SPR_NOACCESS,
877 &spr_read_generic, SPR_NOACCESS,
878 0x00000000);
879 spr_register(env, SPR_IMISS, "IMISS",
880 SPR_NOACCESS, SPR_NOACCESS,
881 &spr_read_generic, SPR_NOACCESS,
882 0x00000000);
883 spr_register(env, SPR_ICMP, "ICMP",
884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_generic, SPR_NOACCESS,
886 0x00000000);
887 spr_register(env, SPR_RPA, "RPA",
888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_generic, &spr_write_generic,
890 0x00000000);
891 #endif
892 }
893
894 /* SPR common to MPC755 and G2 */
895 static void gen_spr_G2_755 (CPUPPCState *env)
896 {
897 /* SGPRs */
898 spr_register(env, SPR_SPRG4, "SPRG4",
899 SPR_NOACCESS, SPR_NOACCESS,
900 &spr_read_generic, &spr_write_generic,
901 0x00000000);
902 spr_register(env, SPR_SPRG5, "SPRG5",
903 SPR_NOACCESS, SPR_NOACCESS,
904 &spr_read_generic, &spr_write_generic,
905 0x00000000);
906 spr_register(env, SPR_SPRG6, "SPRG6",
907 SPR_NOACCESS, SPR_NOACCESS,
908 &spr_read_generic, &spr_write_generic,
909 0x00000000);
910 spr_register(env, SPR_SPRG7, "SPRG7",
911 SPR_NOACCESS, SPR_NOACCESS,
912 &spr_read_generic, &spr_write_generic,
913 0x00000000);
914 }
915
916 /* SPR common to all 7xx PowerPC implementations */
917 static void gen_spr_7xx (CPUPPCState *env)
918 {
919 /* Breakpoints */
920 /* XXX : not implemented */
921 spr_register(env, SPR_DABR, "DABR",
922 SPR_NOACCESS, SPR_NOACCESS,
923 &spr_read_generic, &spr_write_generic,
924 0x00000000);
925 /* XXX : not implemented */
926 spr_register(env, SPR_IABR, "IABR",
927 SPR_NOACCESS, SPR_NOACCESS,
928 &spr_read_generic, &spr_write_generic,
929 0x00000000);
930 /* Cache management */
931 /* XXX : not implemented */
932 spr_register(env, SPR_ICTC, "ICTC",
933 SPR_NOACCESS, SPR_NOACCESS,
934 &spr_read_generic, &spr_write_generic,
935 0x00000000);
936 /* Performance monitors */
937 /* XXX : not implemented */
938 spr_register(env, SPR_MMCR0, "MMCR0",
939 SPR_NOACCESS, SPR_NOACCESS,
940 &spr_read_generic, &spr_write_generic,
941 0x00000000);
942 /* XXX : not implemented */
943 spr_register(env, SPR_MMCR1, "MMCR1",
944 SPR_NOACCESS, SPR_NOACCESS,
945 &spr_read_generic, &spr_write_generic,
946 0x00000000);
947 /* XXX : not implemented */
948 spr_register(env, SPR_PMC1, "PMC1",
949 SPR_NOACCESS, SPR_NOACCESS,
950 &spr_read_generic, &spr_write_generic,
951 0x00000000);
952 /* XXX : not implemented */
953 spr_register(env, SPR_PMC2, "PMC2",
954 SPR_NOACCESS, SPR_NOACCESS,
955 &spr_read_generic, &spr_write_generic,
956 0x00000000);
957 /* XXX : not implemented */
958 spr_register(env, SPR_PMC3, "PMC3",
959 SPR_NOACCESS, SPR_NOACCESS,
960 &spr_read_generic, &spr_write_generic,
961 0x00000000);
962 /* XXX : not implemented */
963 spr_register(env, SPR_PMC4, "PMC4",
964 SPR_NOACCESS, SPR_NOACCESS,
965 &spr_read_generic, &spr_write_generic,
966 0x00000000);
967 /* XXX : not implemented */
968 spr_register(env, SPR_SIAR, "SIAR",
969 SPR_NOACCESS, SPR_NOACCESS,
970 &spr_read_generic, SPR_NOACCESS,
971 0x00000000);
972 /* XXX : not implemented */
973 spr_register(env, SPR_UMMCR0, "UMMCR0",
974 &spr_read_ureg, SPR_NOACCESS,
975 &spr_read_ureg, SPR_NOACCESS,
976 0x00000000);
977 /* XXX : not implemented */
978 spr_register(env, SPR_UMMCR1, "UMMCR1",
979 &spr_read_ureg, SPR_NOACCESS,
980 &spr_read_ureg, SPR_NOACCESS,
981 0x00000000);
982 /* XXX : not implemented */
983 spr_register(env, SPR_UPMC1, "UPMC1",
984 &spr_read_ureg, SPR_NOACCESS,
985 &spr_read_ureg, SPR_NOACCESS,
986 0x00000000);
987 /* XXX : not implemented */
988 spr_register(env, SPR_UPMC2, "UPMC2",
989 &spr_read_ureg, SPR_NOACCESS,
990 &spr_read_ureg, SPR_NOACCESS,
991 0x00000000);
992 /* XXX : not implemented */
993 spr_register(env, SPR_UPMC3, "UPMC3",
994 &spr_read_ureg, SPR_NOACCESS,
995 &spr_read_ureg, SPR_NOACCESS,
996 0x00000000);
997 /* XXX : not implemented */
998 spr_register(env, SPR_UPMC4, "UPMC4",
999 &spr_read_ureg, SPR_NOACCESS,
1000 &spr_read_ureg, SPR_NOACCESS,
1001 0x00000000);
1002 /* XXX : not implemented */
1003 spr_register(env, SPR_USIAR, "USIAR",
1004 &spr_read_ureg, SPR_NOACCESS,
1005 &spr_read_ureg, SPR_NOACCESS,
1006 0x00000000);
1007 /* External access control */
1008 /* XXX : not implemented */
1009 spr_register(env, SPR_EAR, "EAR",
1010 SPR_NOACCESS, SPR_NOACCESS,
1011 &spr_read_generic, &spr_write_generic,
1012 0x00000000);
1013 }
1014
1015 static void gen_spr_thrm (CPUPPCState *env)
1016 {
1017 /* Thermal management */
1018 /* XXX : not implemented */
1019 spr_register(env, SPR_THRM1, "THRM1",
1020 SPR_NOACCESS, SPR_NOACCESS,
1021 &spr_read_generic, &spr_write_generic,
1022 0x00000000);
1023 /* XXX : not implemented */
1024 spr_register(env, SPR_THRM2, "THRM2",
1025 SPR_NOACCESS, SPR_NOACCESS,
1026 &spr_read_generic, &spr_write_generic,
1027 0x00000000);
1028 /* XXX : not implemented */
1029 spr_register(env, SPR_THRM3, "THRM3",
1030 SPR_NOACCESS, SPR_NOACCESS,
1031 &spr_read_generic, &spr_write_generic,
1032 0x00000000);
1033 }
1034
1035 /* SPR specific to PowerPC 604 implementation */
1036 static void gen_spr_604 (CPUPPCState *env)
1037 {
1038 /* Processor identification */
1039 spr_register(env, SPR_PIR, "PIR",
1040 SPR_NOACCESS, SPR_NOACCESS,
1041 &spr_read_generic, &spr_write_pir,
1042 0x00000000);
1043 /* Breakpoints */
1044 /* XXX : not implemented */
1045 spr_register(env, SPR_IABR, "IABR",
1046 SPR_NOACCESS, SPR_NOACCESS,
1047 &spr_read_generic, &spr_write_generic,
1048 0x00000000);
1049 /* XXX : not implemented */
1050 spr_register(env, SPR_DABR, "DABR",
1051 SPR_NOACCESS, SPR_NOACCESS,
1052 &spr_read_generic, &spr_write_generic,
1053 0x00000000);
1054 /* Performance counters */
1055 /* XXX : not implemented */
1056 spr_register(env, SPR_MMCR0, "MMCR0",
1057 SPR_NOACCESS, SPR_NOACCESS,
1058 &spr_read_generic, &spr_write_generic,
1059 0x00000000);
1060 /* XXX : not implemented */
1061 spr_register(env, SPR_PMC1, "PMC1",
1062 SPR_NOACCESS, SPR_NOACCESS,
1063 &spr_read_generic, &spr_write_generic,
1064 0x00000000);
1065 /* XXX : not implemented */
1066 spr_register(env, SPR_PMC2, "PMC2",
1067 SPR_NOACCESS, SPR_NOACCESS,
1068 &spr_read_generic, &spr_write_generic,
1069 0x00000000);
1070 /* XXX : not implemented */
1071 spr_register(env, SPR_SIAR, "SIAR",
1072 SPR_NOACCESS, SPR_NOACCESS,
1073 &spr_read_generic, SPR_NOACCESS,
1074 0x00000000);
1075 /* XXX : not implemented */
1076 spr_register(env, SPR_SDA, "SDA",
1077 SPR_NOACCESS, SPR_NOACCESS,
1078 &spr_read_generic, SPR_NOACCESS,
1079 0x00000000);
1080 /* External access control */
1081 /* XXX : not implemented */
1082 spr_register(env, SPR_EAR, "EAR",
1083 SPR_NOACCESS, SPR_NOACCESS,
1084 &spr_read_generic, &spr_write_generic,
1085 0x00000000);
1086 }
1087
1088 /* SPR specific to PowerPC 603 implementation */
1089 static void gen_spr_603 (CPUPPCState *env)
1090 {
1091 /* External access control */
1092 /* XXX : not implemented */
1093 spr_register(env, SPR_EAR, "EAR",
1094 SPR_NOACCESS, SPR_NOACCESS,
1095 &spr_read_generic, &spr_write_generic,
1096 0x00000000);
1097 }
1098
1099 /* SPR specific to PowerPC G2 implementation */
1100 static void gen_spr_G2 (CPUPPCState *env)
1101 {
1102 /* Memory base address */
1103 /* MBAR */
1104 /* XXX : not implemented */
1105 spr_register(env, SPR_MBAR, "MBAR",
1106 SPR_NOACCESS, SPR_NOACCESS,
1107 &spr_read_generic, &spr_write_generic,
1108 0x00000000);
1109 /* Exception processing */
1110 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1111 SPR_NOACCESS, SPR_NOACCESS,
1112 &spr_read_generic, &spr_write_generic,
1113 0x00000000);
1114 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1115 SPR_NOACCESS, SPR_NOACCESS,
1116 &spr_read_generic, &spr_write_generic,
1117 0x00000000);
1118 /* Breakpoints */
1119 /* XXX : not implemented */
1120 spr_register(env, SPR_DABR, "DABR",
1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_generic, &spr_write_generic,
1123 0x00000000);
1124 /* XXX : not implemented */
1125 spr_register(env, SPR_DABR2, "DABR2",
1126 SPR_NOACCESS, SPR_NOACCESS,
1127 &spr_read_generic, &spr_write_generic,
1128 0x00000000);
1129 /* XXX : not implemented */
1130 spr_register(env, SPR_IABR, "IABR",
1131 SPR_NOACCESS, SPR_NOACCESS,
1132 &spr_read_generic, &spr_write_generic,
1133 0x00000000);
1134 /* XXX : not implemented */
1135 spr_register(env, SPR_IABR2, "IABR2",
1136 SPR_NOACCESS, SPR_NOACCESS,
1137 &spr_read_generic, &spr_write_generic,
1138 0x00000000);
1139 /* XXX : not implemented */
1140 spr_register(env, SPR_IBCR, "IBCR",
1141 SPR_NOACCESS, SPR_NOACCESS,
1142 &spr_read_generic, &spr_write_generic,
1143 0x00000000);
1144 /* XXX : not implemented */
1145 spr_register(env, SPR_DBCR, "DBCR",
1146 SPR_NOACCESS, SPR_NOACCESS,
1147 &spr_read_generic, &spr_write_generic,
1148 0x00000000);
1149 }
1150
1151 /* SPR specific to PowerPC 602 implementation */
1152 static void gen_spr_602 (CPUPPCState *env)
1153 {
1154 /* ESA registers */
1155 /* XXX : not implemented */
1156 spr_register(env, SPR_SER, "SER",
1157 SPR_NOACCESS, SPR_NOACCESS,
1158 &spr_read_generic, &spr_write_generic,
1159 0x00000000);
1160 /* XXX : not implemented */
1161 spr_register(env, SPR_SEBR, "SEBR",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_generic, &spr_write_generic,
1164 0x00000000);
1165 /* XXX : not implemented */
1166 spr_register(env, SPR_ESASRR, "ESASRR",
1167 SPR_NOACCESS, SPR_NOACCESS,
1168 &spr_read_generic, &spr_write_generic,
1169 0x00000000);
1170 /* Floating point status */
1171 /* XXX : not implemented */
1172 spr_register(env, SPR_SP, "SP",
1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_generic,
1175 0x00000000);
1176 /* XXX : not implemented */
1177 spr_register(env, SPR_LT, "LT",
1178 SPR_NOACCESS, SPR_NOACCESS,
1179 &spr_read_generic, &spr_write_generic,
1180 0x00000000);
1181 /* Watchdog timer */
1182 /* XXX : not implemented */
1183 spr_register(env, SPR_TCR, "TCR",
1184 SPR_NOACCESS, SPR_NOACCESS,
1185 &spr_read_generic, &spr_write_generic,
1186 0x00000000);
1187 /* Interrupt base */
1188 spr_register(env, SPR_IBR, "IBR",
1189 SPR_NOACCESS, SPR_NOACCESS,
1190 &spr_read_generic, &spr_write_generic,
1191 0x00000000);
1192 /* XXX : not implemented */
1193 spr_register(env, SPR_IABR, "IABR",
1194 SPR_NOACCESS, SPR_NOACCESS,
1195 &spr_read_generic, &spr_write_generic,
1196 0x00000000);
1197 }
1198
1199 /* SPR specific to PowerPC 601 implementation */
1200 static void gen_spr_601 (CPUPPCState *env)
1201 {
1202 /* Multiplication/division register */
1203 /* MQ */
1204 spr_register(env, SPR_MQ, "MQ",
1205 &spr_read_generic, &spr_write_generic,
1206 &spr_read_generic, &spr_write_generic,
1207 0x00000000);
1208 /* RTC registers */
1209 spr_register(env, SPR_601_RTCU, "RTCU",
1210 SPR_NOACCESS, SPR_NOACCESS,
1211 SPR_NOACCESS, &spr_write_601_rtcu,
1212 0x00000000);
1213 spr_register(env, SPR_601_VRTCU, "RTCU",
1214 &spr_read_601_rtcu, SPR_NOACCESS,
1215 &spr_read_601_rtcu, SPR_NOACCESS,
1216 0x00000000);
1217 spr_register(env, SPR_601_RTCL, "RTCL",
1218 SPR_NOACCESS, SPR_NOACCESS,
1219 SPR_NOACCESS, &spr_write_601_rtcl,
1220 0x00000000);
1221 spr_register(env, SPR_601_VRTCL, "RTCL",
1222 &spr_read_601_rtcl, SPR_NOACCESS,
1223 &spr_read_601_rtcl, SPR_NOACCESS,
1224 0x00000000);
1225 /* Timer */
1226 #if 0 /* ? */
1227 spr_register(env, SPR_601_UDECR, "UDECR",
1228 &spr_read_decr, SPR_NOACCESS,
1229 &spr_read_decr, SPR_NOACCESS,
1230 0x00000000);
1231 #endif
1232 /* External access control */
1233 /* XXX : not implemented */
1234 spr_register(env, SPR_EAR, "EAR",
1235 SPR_NOACCESS, SPR_NOACCESS,
1236 &spr_read_generic, &spr_write_generic,
1237 0x00000000);
1238 /* Memory management */
1239 #if !defined(CONFIG_USER_ONLY)
1240 spr_register(env, SPR_IBAT0U, "IBAT0U",
1241 SPR_NOACCESS, SPR_NOACCESS,
1242 &spr_read_601_ubat, &spr_write_601_ubatu,
1243 0x00000000);
1244 spr_register(env, SPR_IBAT0L, "IBAT0L",
1245 SPR_NOACCESS, SPR_NOACCESS,
1246 &spr_read_601_ubat, &spr_write_601_ubatl,
1247 0x00000000);
1248 spr_register(env, SPR_IBAT1U, "IBAT1U",
1249 SPR_NOACCESS, SPR_NOACCESS,
1250 &spr_read_601_ubat, &spr_write_601_ubatu,
1251 0x00000000);
1252 spr_register(env, SPR_IBAT1L, "IBAT1L",
1253 SPR_NOACCESS, SPR_NOACCESS,
1254 &spr_read_601_ubat, &spr_write_601_ubatl,
1255 0x00000000);
1256 spr_register(env, SPR_IBAT2U, "IBAT2U",
1257 SPR_NOACCESS, SPR_NOACCESS,
1258 &spr_read_601_ubat, &spr_write_601_ubatu,
1259 0x00000000);
1260 spr_register(env, SPR_IBAT2L, "IBAT2L",
1261 SPR_NOACCESS, SPR_NOACCESS,
1262 &spr_read_601_ubat, &spr_write_601_ubatl,
1263 0x00000000);
1264 spr_register(env, SPR_IBAT3U, "IBAT3U",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_601_ubat, &spr_write_601_ubatu,
1267 0x00000000);
1268 spr_register(env, SPR_IBAT3L, "IBAT3L",
1269 SPR_NOACCESS, SPR_NOACCESS,
1270 &spr_read_601_ubat, &spr_write_601_ubatl,
1271 0x00000000);
1272 env->nb_BATs = 4;
1273 #endif
1274 }
1275
1276 static void gen_spr_74xx (CPUPPCState *env)
1277 {
1278 /* Processor identification */
1279 spr_register(env, SPR_PIR, "PIR",
1280 SPR_NOACCESS, SPR_NOACCESS,
1281 &spr_read_generic, &spr_write_pir,
1282 0x00000000);
1283 /* XXX : not implemented */
1284 spr_register(env, SPR_MMCR2, "MMCR2",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_generic, &spr_write_generic,
1287 0x00000000);
1288 /* XXX : not implemented */
1289 spr_register(env, SPR_UMMCR2, "UMMCR2",
1290 &spr_read_ureg, SPR_NOACCESS,
1291 &spr_read_ureg, SPR_NOACCESS,
1292 0x00000000);
1293 /* XXX: not implemented */
1294 spr_register(env, SPR_BAMR, "BAMR",
1295 SPR_NOACCESS, SPR_NOACCESS,
1296 &spr_read_generic, &spr_write_generic,
1297 0x00000000);
1298 /* XXX : not implemented */
1299 spr_register(env, SPR_MSSCR0, "MSSCR0",
1300 SPR_NOACCESS, SPR_NOACCESS,
1301 &spr_read_generic, &spr_write_generic,
1302 0x00000000);
1303 /* Hardware implementation registers */
1304 /* XXX : not implemented */
1305 spr_register(env, SPR_HID0, "HID0",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, &spr_write_generic,
1308 0x00000000);
1309 /* XXX : not implemented */
1310 spr_register(env, SPR_HID1, "HID1",
1311 SPR_NOACCESS, SPR_NOACCESS,
1312 &spr_read_generic, &spr_write_generic,
1313 0x00000000);
1314 /* Altivec */
1315 spr_register(env, SPR_VRSAVE, "VRSAVE",
1316 &spr_read_generic, &spr_write_generic,
1317 &spr_read_generic, &spr_write_generic,
1318 0x00000000);
1319 /* XXX : not implemented */
1320 spr_register(env, SPR_L2CR, "L2CR",
1321 SPR_NOACCESS, SPR_NOACCESS,
1322 &spr_read_generic, &spr_write_generic,
1323 0x00000000);
1324 /* Not strictly an SPR */
1325 vscr_init(env, 0x00010000);
1326 }
1327
1328 static void gen_l3_ctrl (CPUPPCState *env)
1329 {
1330 /* L3CR */
1331 /* XXX : not implemented */
1332 spr_register(env, SPR_L3CR, "L3CR",
1333 SPR_NOACCESS, SPR_NOACCESS,
1334 &spr_read_generic, &spr_write_generic,
1335 0x00000000);
1336 /* L3ITCR0 */
1337 /* XXX : not implemented */
1338 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1339 SPR_NOACCESS, SPR_NOACCESS,
1340 &spr_read_generic, &spr_write_generic,
1341 0x00000000);
1342 /* L3PM */
1343 /* XXX : not implemented */
1344 spr_register(env, SPR_L3PM, "L3PM",
1345 SPR_NOACCESS, SPR_NOACCESS,
1346 &spr_read_generic, &spr_write_generic,
1347 0x00000000);
1348 }
1349
1350 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1351 {
1352 #if !defined(CONFIG_USER_ONLY)
1353 env->nb_tlb = nb_tlbs;
1354 env->nb_ways = nb_ways;
1355 env->id_tlbs = 1;
1356 env->tlb_type = TLB_6XX;
1357 /* XXX : not implemented */
1358 spr_register(env, SPR_PTEHI, "PTEHI",
1359 SPR_NOACCESS, SPR_NOACCESS,
1360 &spr_read_generic, &spr_write_generic,
1361 0x00000000);
1362 /* XXX : not implemented */
1363 spr_register(env, SPR_PTELO, "PTELO",
1364 SPR_NOACCESS, SPR_NOACCESS,
1365 &spr_read_generic, &spr_write_generic,
1366 0x00000000);
1367 /* XXX : not implemented */
1368 spr_register(env, SPR_TLBMISS, "TLBMISS",
1369 SPR_NOACCESS, SPR_NOACCESS,
1370 &spr_read_generic, &spr_write_generic,
1371 0x00000000);
1372 #endif
1373 }
1374
1375 #if !defined(CONFIG_USER_ONLY)
1376 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1377 {
1378 TCGv t0 = tcg_temp_new();
1379
1380 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1381 gen_store_spr(sprn, t0);
1382 tcg_temp_free(t0);
1383 }
1384
1385 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1386 {
1387 TCGv_i32 t0 = tcg_const_i32(sprn);
1388 gen_helper_booke206_tlbflush(cpu_env, t0);
1389 tcg_temp_free_i32(t0);
1390 }
1391
1392 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1393 {
1394 TCGv_i32 t0 = tcg_const_i32(sprn);
1395 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1396 tcg_temp_free_i32(t0);
1397 }
1398 #endif
1399
1400 static void gen_spr_usprgh (CPUPPCState *env)
1401 {
1402 spr_register(env, SPR_USPRG4, "USPRG4",
1403 &spr_read_ureg, SPR_NOACCESS,
1404 &spr_read_ureg, SPR_NOACCESS,
1405 0x00000000);
1406 spr_register(env, SPR_USPRG5, "USPRG5",
1407 &spr_read_ureg, SPR_NOACCESS,
1408 &spr_read_ureg, SPR_NOACCESS,
1409 0x00000000);
1410 spr_register(env, SPR_USPRG6, "USPRG6",
1411 &spr_read_ureg, SPR_NOACCESS,
1412 &spr_read_ureg, SPR_NOACCESS,
1413 0x00000000);
1414 spr_register(env, SPR_USPRG7, "USPRG7",
1415 &spr_read_ureg, SPR_NOACCESS,
1416 &spr_read_ureg, SPR_NOACCESS,
1417 0x00000000);
1418 }
1419
1420 /* PowerPC BookE SPR */
1421 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1422 {
1423 const char *ivor_names[64] = {
1424 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1425 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1426 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1427 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1428 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1429 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1430 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1431 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1432 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1433 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1434 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1435 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1436 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1437 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1438 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1439 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1440 };
1441 #define SPR_BOOKE_IVORxx (-1)
1442 int ivor_sprn[64] = {
1443 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1444 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1445 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1446 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1447 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1448 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1449 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1450 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1451 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1452 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1453 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1454 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1455 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1456 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1457 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1458 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1459 };
1460 int i;
1461
1462 /* Interrupt processing */
1463 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1464 SPR_NOACCESS, SPR_NOACCESS,
1465 &spr_read_generic, &spr_write_generic,
1466 0x00000000);
1467 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1468 SPR_NOACCESS, SPR_NOACCESS,
1469 &spr_read_generic, &spr_write_generic,
1470 0x00000000);
1471 /* Debug */
1472 /* XXX : not implemented */
1473 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1474 SPR_NOACCESS, SPR_NOACCESS,
1475 &spr_read_generic, &spr_write_generic,
1476 0x00000000);
1477 /* XXX : not implemented */
1478 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1479 SPR_NOACCESS, SPR_NOACCESS,
1480 &spr_read_generic, &spr_write_generic,
1481 0x00000000);
1482 /* XXX : not implemented */
1483 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1484 SPR_NOACCESS, SPR_NOACCESS,
1485 &spr_read_generic, &spr_write_generic,
1486 0x00000000);
1487 /* XXX : not implemented */
1488 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1489 SPR_NOACCESS, SPR_NOACCESS,
1490 &spr_read_generic, &spr_write_generic,
1491 0x00000000);
1492 /* XXX : not implemented */
1493 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1494 SPR_NOACCESS, SPR_NOACCESS,
1495 &spr_read_generic, &spr_write_40x_dbcr0,
1496 0x00000000);
1497 /* XXX : not implemented */
1498 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1499 SPR_NOACCESS, SPR_NOACCESS,
1500 &spr_read_generic, &spr_write_generic,
1501 0x00000000);
1502 /* XXX : not implemented */
1503 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1504 SPR_NOACCESS, SPR_NOACCESS,
1505 &spr_read_generic, &spr_write_generic,
1506 0x00000000);
1507 /* XXX : not implemented */
1508 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1509 SPR_NOACCESS, SPR_NOACCESS,
1510 &spr_read_generic, &spr_write_clear,
1511 0x00000000);
1512 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1513 SPR_NOACCESS, SPR_NOACCESS,
1514 &spr_read_generic, &spr_write_generic,
1515 0x00000000);
1516 spr_register(env, SPR_BOOKE_ESR, "ESR",
1517 SPR_NOACCESS, SPR_NOACCESS,
1518 &spr_read_generic, &spr_write_generic,
1519 0x00000000);
1520 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1521 SPR_NOACCESS, SPR_NOACCESS,
1522 &spr_read_generic, &spr_write_excp_prefix,
1523 0x00000000);
1524 /* Exception vectors */
1525 for (i = 0; i < 64; i++) {
1526 if (ivor_mask & (1ULL << i)) {
1527 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1528 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1529 exit(1);
1530 }
1531 spr_register(env, ivor_sprn[i], ivor_names[i],
1532 SPR_NOACCESS, SPR_NOACCESS,
1533 &spr_read_generic, &spr_write_excp_vector,
1534 0x00000000);
1535 }
1536 }
1537 spr_register(env, SPR_BOOKE_PID, "PID",
1538 SPR_NOACCESS, SPR_NOACCESS,
1539 &spr_read_generic, &spr_write_booke_pid,
1540 0x00000000);
1541 spr_register(env, SPR_BOOKE_TCR, "TCR",
1542 SPR_NOACCESS, SPR_NOACCESS,
1543 &spr_read_generic, &spr_write_booke_tcr,
1544 0x00000000);
1545 spr_register(env, SPR_BOOKE_TSR, "TSR",
1546 SPR_NOACCESS, SPR_NOACCESS,
1547 &spr_read_generic, &spr_write_booke_tsr,
1548 0x00000000);
1549 /* Timer */
1550 spr_register(env, SPR_DECR, "DECR",
1551 SPR_NOACCESS, SPR_NOACCESS,
1552 &spr_read_decr, &spr_write_decr,
1553 0x00000000);
1554 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1555 SPR_NOACCESS, SPR_NOACCESS,
1556 SPR_NOACCESS, &spr_write_generic,
1557 0x00000000);
1558 /* SPRGs */
1559 spr_register(env, SPR_USPRG0, "USPRG0",
1560 &spr_read_generic, &spr_write_generic,
1561 &spr_read_generic, &spr_write_generic,
1562 0x00000000);
1563 spr_register(env, SPR_SPRG4, "SPRG4",
1564 SPR_NOACCESS, SPR_NOACCESS,
1565 &spr_read_generic, &spr_write_generic,
1566 0x00000000);
1567 spr_register(env, SPR_SPRG5, "SPRG5",
1568 SPR_NOACCESS, SPR_NOACCESS,
1569 &spr_read_generic, &spr_write_generic,
1570 0x00000000);
1571 spr_register(env, SPR_SPRG6, "SPRG6",
1572 SPR_NOACCESS, SPR_NOACCESS,
1573 &spr_read_generic, &spr_write_generic,
1574 0x00000000);
1575 spr_register(env, SPR_SPRG7, "SPRG7",
1576 SPR_NOACCESS, SPR_NOACCESS,
1577 &spr_read_generic, &spr_write_generic,
1578 0x00000000);
1579 }
1580
1581 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1582 uint32_t maxsize, uint32_t flags,
1583 uint32_t nentries)
1584 {
1585 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1586 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1587 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1588 flags | nentries;
1589 }
1590
1591 /* BookE 2.06 storage control registers */
1592 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1593 uint32_t *tlbncfg)
1594 {
1595 #if !defined(CONFIG_USER_ONLY)
1596 const char *mas_names[8] = {
1597 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1598 };
1599 int mas_sprn[8] = {
1600 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1601 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1602 };
1603 int i;
1604
1605 /* TLB assist registers */
1606 /* XXX : not implemented */
1607 for (i = 0; i < 8; i++) {
1608 void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1609 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1610 uea_write = &spr_write_generic;
1611 }
1612 if (mas_mask & (1 << i)) {
1613 spr_register(env, mas_sprn[i], mas_names[i],
1614 SPR_NOACCESS, SPR_NOACCESS,
1615 &spr_read_generic, uea_write,
1616 0x00000000);
1617 }
1618 }
1619 if (env->nb_pids > 1) {
1620 /* XXX : not implemented */
1621 spr_register(env, SPR_BOOKE_PID1, "PID1",
1622 SPR_NOACCESS, SPR_NOACCESS,
1623 &spr_read_generic, &spr_write_booke_pid,
1624 0x00000000);
1625 }
1626 if (env->nb_pids > 2) {
1627 /* XXX : not implemented */
1628 spr_register(env, SPR_BOOKE_PID2, "PID2",
1629 SPR_NOACCESS, SPR_NOACCESS,
1630 &spr_read_generic, &spr_write_booke_pid,
1631 0x00000000);
1632 }
1633 /* XXX : not implemented */
1634 spr_register(env, SPR_MMUCFG, "MMUCFG",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_generic, SPR_NOACCESS,
1637 0x00000000); /* TOFIX */
1638 switch (env->nb_ways) {
1639 case 4:
1640 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1641 SPR_NOACCESS, SPR_NOACCESS,
1642 &spr_read_generic, SPR_NOACCESS,
1643 tlbncfg[3]);
1644 /* Fallthru */
1645 case 3:
1646 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1647 SPR_NOACCESS, SPR_NOACCESS,
1648 &spr_read_generic, SPR_NOACCESS,
1649 tlbncfg[2]);
1650 /* Fallthru */
1651 case 2:
1652 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1653 SPR_NOACCESS, SPR_NOACCESS,
1654 &spr_read_generic, SPR_NOACCESS,
1655 tlbncfg[1]);
1656 /* Fallthru */
1657 case 1:
1658 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1659 SPR_NOACCESS, SPR_NOACCESS,
1660 &spr_read_generic, SPR_NOACCESS,
1661 tlbncfg[0]);
1662 /* Fallthru */
1663 case 0:
1664 default:
1665 break;
1666 }
1667 #endif
1668
1669 gen_spr_usprgh(env);
1670 }
1671
1672 /* SPR specific to PowerPC 440 implementation */
1673 static void gen_spr_440 (CPUPPCState *env)
1674 {
1675 /* Cache control */
1676 /* XXX : not implemented */
1677 spr_register(env, SPR_440_DNV0, "DNV0",
1678 SPR_NOACCESS, SPR_NOACCESS,
1679 &spr_read_generic, &spr_write_generic,
1680 0x00000000);
1681 /* XXX : not implemented */
1682 spr_register(env, SPR_440_DNV1, "DNV1",
1683 SPR_NOACCESS, SPR_NOACCESS,
1684 &spr_read_generic, &spr_write_generic,
1685 0x00000000);
1686 /* XXX : not implemented */
1687 spr_register(env, SPR_440_DNV2, "DNV2",
1688 SPR_NOACCESS, SPR_NOACCESS,
1689 &spr_read_generic, &spr_write_generic,
1690 0x00000000);
1691 /* XXX : not implemented */
1692 spr_register(env, SPR_440_DNV3, "DNV3",
1693 SPR_NOACCESS, SPR_NOACCESS,
1694 &spr_read_generic, &spr_write_generic,
1695 0x00000000);
1696 /* XXX : not implemented */
1697 spr_register(env, SPR_440_DTV0, "DTV0",
1698 SPR_NOACCESS, SPR_NOACCESS,
1699 &spr_read_generic, &spr_write_generic,
1700 0x00000000);
1701 /* XXX : not implemented */
1702 spr_register(env, SPR_440_DTV1, "DTV1",
1703 SPR_NOACCESS, SPR_NOACCESS,
1704 &spr_read_generic, &spr_write_generic,
1705 0x00000000);
1706 /* XXX : not implemented */
1707 spr_register(env, SPR_440_DTV2, "DTV2",
1708 SPR_NOACCESS, SPR_NOACCESS,
1709 &spr_read_generic, &spr_write_generic,
1710 0x00000000);
1711 /* XXX : not implemented */
1712 spr_register(env, SPR_440_DTV3, "DTV3",
1713 SPR_NOACCESS, SPR_NOACCESS,
1714 &spr_read_generic, &spr_write_generic,
1715 0x00000000);
1716 /* XXX : not implemented */
1717 spr_register(env, SPR_440_DVLIM, "DVLIM",
1718 SPR_NOACCESS, SPR_NOACCESS,
1719 &spr_read_generic, &spr_write_generic,
1720 0x00000000);
1721 /* XXX : not implemented */
1722 spr_register(env, SPR_440_INV0, "INV0",
1723 SPR_NOACCESS, SPR_NOACCESS,
1724 &spr_read_generic, &spr_write_generic,
1725 0x00000000);
1726 /* XXX : not implemented */
1727 spr_register(env, SPR_440_INV1, "INV1",
1728 SPR_NOACCESS, SPR_NOACCESS,
1729 &spr_read_generic, &spr_write_generic,
1730 0x00000000);
1731 /* XXX : not implemented */
1732 spr_register(env, SPR_440_INV2, "INV2",
1733 SPR_NOACCESS, SPR_NOACCESS,
1734 &spr_read_generic, &spr_write_generic,
1735 0x00000000);
1736 /* XXX : not implemented */
1737 spr_register(env, SPR_440_INV3, "INV3",
1738 SPR_NOACCESS, SPR_NOACCESS,
1739 &spr_read_generic, &spr_write_generic,
1740 0x00000000);
1741 /* XXX : not implemented */
1742 spr_register(env, SPR_440_ITV0, "ITV0",
1743 SPR_NOACCESS, SPR_NOACCESS,
1744 &spr_read_generic, &spr_write_generic,
1745 0x00000000);
1746 /* XXX : not implemented */
1747 spr_register(env, SPR_440_ITV1, "ITV1",
1748 SPR_NOACCESS, SPR_NOACCESS,
1749 &spr_read_generic, &spr_write_generic,
1750 0x00000000);
1751 /* XXX : not implemented */
1752 spr_register(env, SPR_440_ITV2, "ITV2",
1753 SPR_NOACCESS, SPR_NOACCESS,
1754 &spr_read_generic, &spr_write_generic,
1755 0x00000000);
1756 /* XXX : not implemented */
1757 spr_register(env, SPR_440_ITV3, "ITV3",
1758 SPR_NOACCESS, SPR_NOACCESS,
1759 &spr_read_generic, &spr_write_generic,
1760 0x00000000);
1761 /* XXX : not implemented */
1762 spr_register(env, SPR_440_IVLIM, "IVLIM",
1763 SPR_NOACCESS, SPR_NOACCESS,
1764 &spr_read_generic, &spr_write_generic,
1765 0x00000000);
1766 /* Cache debug */
1767 /* XXX : not implemented */
1768 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1769 SPR_NOACCESS, SPR_NOACCESS,
1770 &spr_read_generic, SPR_NOACCESS,
1771 0x00000000);
1772 /* XXX : not implemented */
1773 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, SPR_NOACCESS,
1776 0x00000000);
1777 /* XXX : not implemented */
1778 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1779 SPR_NOACCESS, SPR_NOACCESS,
1780 &spr_read_generic, SPR_NOACCESS,
1781 0x00000000);
1782 /* XXX : not implemented */
1783 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1784 SPR_NOACCESS, SPR_NOACCESS,
1785 &spr_read_generic, SPR_NOACCESS,
1786 0x00000000);
1787 /* XXX : not implemented */
1788 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1789 SPR_NOACCESS, SPR_NOACCESS,
1790 &spr_read_generic, SPR_NOACCESS,
1791 0x00000000);
1792 /* XXX : not implemented */
1793 spr_register(env, SPR_440_DBDR, "DBDR",
1794 SPR_NOACCESS, SPR_NOACCESS,
1795 &spr_read_generic, &spr_write_generic,
1796 0x00000000);
1797 /* Processor control */
1798 spr_register(env, SPR_4xx_CCR0, "CCR0",
1799 SPR_NOACCESS, SPR_NOACCESS,
1800 &spr_read_generic, &spr_write_generic,
1801 0x00000000);
1802 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1803 SPR_NOACCESS, SPR_NOACCESS,
1804 &spr_read_generic, SPR_NOACCESS,
1805 0x00000000);
1806 /* Storage control */
1807 spr_register(env, SPR_440_MMUCR, "MMUCR",
1808 SPR_NOACCESS, SPR_NOACCESS,
1809 &spr_read_generic, &spr_write_generic,
1810 0x00000000);
1811 }
1812
1813 /* SPR shared between PowerPC 40x implementations */
1814 static void gen_spr_40x (CPUPPCState *env)
1815 {
1816 /* Cache */
1817 /* not emulated, as QEMU do not emulate caches */
1818 spr_register(env, SPR_40x_DCCR, "DCCR",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, &spr_write_generic,
1821 0x00000000);
1822 /* not emulated, as QEMU do not emulate caches */
1823 spr_register(env, SPR_40x_ICCR, "ICCR",
1824 SPR_NOACCESS, SPR_NOACCESS,
1825 &spr_read_generic, &spr_write_generic,
1826 0x00000000);
1827 /* not emulated, as QEMU do not emulate caches */
1828 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1829 SPR_NOACCESS, SPR_NOACCESS,
1830 &spr_read_generic, SPR_NOACCESS,
1831 0x00000000);
1832 /* Exception */
1833 spr_register(env, SPR_40x_DEAR, "DEAR",
1834 SPR_NOACCESS, SPR_NOACCESS,
1835 &spr_read_generic, &spr_write_generic,
1836 0x00000000);
1837 spr_register(env, SPR_40x_ESR, "ESR",
1838 SPR_NOACCESS, SPR_NOACCESS,
1839 &spr_read_generic, &spr_write_generic,
1840 0x00000000);
1841 spr_register(env, SPR_40x_EVPR, "EVPR",
1842 SPR_NOACCESS, SPR_NOACCESS,
1843 &spr_read_generic, &spr_write_excp_prefix,
1844 0x00000000);
1845 spr_register(env, SPR_40x_SRR2, "SRR2",
1846 &spr_read_generic, &spr_write_generic,
1847 &spr_read_generic, &spr_write_generic,
1848 0x00000000);
1849 spr_register(env, SPR_40x_SRR3, "SRR3",
1850 &spr_read_generic, &spr_write_generic,
1851 &spr_read_generic, &spr_write_generic,
1852 0x00000000);
1853 /* Timers */
1854 spr_register(env, SPR_40x_PIT, "PIT",
1855 SPR_NOACCESS, SPR_NOACCESS,
1856 &spr_read_40x_pit, &spr_write_40x_pit,
1857 0x00000000);
1858 spr_register(env, SPR_40x_TCR, "TCR",
1859 SPR_NOACCESS, SPR_NOACCESS,
1860 &spr_read_generic, &spr_write_booke_tcr,
1861 0x00000000);
1862 spr_register(env, SPR_40x_TSR, "TSR",
1863 SPR_NOACCESS, SPR_NOACCESS,
1864 &spr_read_generic, &spr_write_booke_tsr,
1865 0x00000000);
1866 }
1867
1868 /* SPR specific to PowerPC 405 implementation */
1869 static void gen_spr_405 (CPUPPCState *env)
1870 {
1871 /* MMU */
1872 spr_register(env, SPR_40x_PID, "PID",
1873 SPR_NOACCESS, SPR_NOACCESS,
1874 &spr_read_generic, &spr_write_generic,
1875 0x00000000);
1876 spr_register(env, SPR_4xx_CCR0, "CCR0",
1877 SPR_NOACCESS, SPR_NOACCESS,
1878 &spr_read_generic, &spr_write_generic,
1879 0x00700000);
1880 /* Debug interface */
1881 /* XXX : not implemented */
1882 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1883 SPR_NOACCESS, SPR_NOACCESS,
1884 &spr_read_generic, &spr_write_40x_dbcr0,
1885 0x00000000);
1886 /* XXX : not implemented */
1887 spr_register(env, SPR_405_DBCR1, "DBCR1",
1888 SPR_NOACCESS, SPR_NOACCESS,
1889 &spr_read_generic, &spr_write_generic,
1890 0x00000000);
1891 /* XXX : not implemented */
1892 spr_register(env, SPR_40x_DBSR, "DBSR",
1893 SPR_NOACCESS, SPR_NOACCESS,
1894 &spr_read_generic, &spr_write_clear,
1895 /* Last reset was system reset */
1896 0x00000300);
1897 /* XXX : not implemented */
1898 spr_register(env, SPR_40x_DAC1, "DAC1",
1899 SPR_NOACCESS, SPR_NOACCESS,
1900 &spr_read_generic, &spr_write_generic,
1901 0x00000000);
1902 spr_register(env, SPR_40x_DAC2, "DAC2",
1903 SPR_NOACCESS, SPR_NOACCESS,
1904 &spr_read_generic, &spr_write_generic,
1905 0x00000000);
1906 /* XXX : not implemented */
1907 spr_register(env, SPR_405_DVC1, "DVC1",
1908 SPR_NOACCESS, SPR_NOACCESS,
1909 &spr_read_generic, &spr_write_generic,
1910 0x00000000);
1911 /* XXX : not implemented */
1912 spr_register(env, SPR_405_DVC2, "DVC2",
1913 SPR_NOACCESS, SPR_NOACCESS,
1914 &spr_read_generic, &spr_write_generic,
1915 0x00000000);
1916 /* XXX : not implemented */
1917 spr_register(env, SPR_40x_IAC1, "IAC1",
1918 SPR_NOACCESS, SPR_NOACCESS,
1919 &spr_read_generic, &spr_write_generic,
1920 0x00000000);
1921 spr_register(env, SPR_40x_IAC2, "IAC2",
1922 SPR_NOACCESS, SPR_NOACCESS,
1923 &spr_read_generic, &spr_write_generic,
1924 0x00000000);
1925 /* XXX : not implemented */
1926 spr_register(env, SPR_405_IAC3, "IAC3",
1927 SPR_NOACCESS, SPR_NOACCESS,
1928 &spr_read_generic, &spr_write_generic,
1929 0x00000000);
1930 /* XXX : not implemented */
1931 spr_register(env, SPR_405_IAC4, "IAC4",
1932 SPR_NOACCESS, SPR_NOACCESS,
1933 &spr_read_generic, &spr_write_generic,
1934 0x00000000);
1935 /* Storage control */
1936 /* XXX: TODO: not implemented */
1937 spr_register(env, SPR_405_SLER, "SLER",
1938 SPR_NOACCESS, SPR_NOACCESS,
1939 &spr_read_generic, &spr_write_40x_sler,
1940 0x00000000);
1941 spr_register(env, SPR_40x_ZPR, "ZPR",
1942 SPR_NOACCESS, SPR_NOACCESS,
1943 &spr_read_generic, &spr_write_generic,
1944 0x00000000);
1945 /* XXX : not implemented */
1946 spr_register(env, SPR_405_SU0R, "SU0R",
1947 SPR_NOACCESS, SPR_NOACCESS,
1948 &spr_read_generic, &spr_write_generic,
1949 0x00000000);
1950 /* SPRG */
1951 spr_register(env, SPR_USPRG0, "USPRG0",
1952 &spr_read_ureg, SPR_NOACCESS,
1953 &spr_read_ureg, SPR_NOACCESS,
1954 0x00000000);
1955 spr_register(env, SPR_SPRG4, "SPRG4",
1956 SPR_NOACCESS, SPR_NOACCESS,
1957 &spr_read_generic, &spr_write_generic,
1958 0x00000000);
1959 spr_register(env, SPR_SPRG5, "SPRG5",
1960 SPR_NOACCESS, SPR_NOACCESS,
1961 spr_read_generic, &spr_write_generic,
1962 0x00000000);
1963 spr_register(env, SPR_SPRG6, "SPRG6",
1964 SPR_NOACCESS, SPR_NOACCESS,
1965 spr_read_generic, &spr_write_generic,
1966 0x00000000);
1967 spr_register(env, SPR_SPRG7, "SPRG7",
1968 SPR_NOACCESS, SPR_NOACCESS,
1969 spr_read_generic, &spr_write_generic,
1970 0x00000000);
1971 gen_spr_usprgh(env);
1972 }
1973
1974 /* SPR shared between PowerPC 401 & 403 implementations */
1975 static void gen_spr_401_403 (CPUPPCState *env)
1976 {
1977 /* Time base */
1978 spr_register(env, SPR_403_VTBL, "TBL",
1979 &spr_read_tbl, SPR_NOACCESS,
1980 &spr_read_tbl, SPR_NOACCESS,
1981 0x00000000);
1982 spr_register(env, SPR_403_TBL, "TBL",
1983 SPR_NOACCESS, SPR_NOACCESS,
1984 SPR_NOACCESS, &spr_write_tbl,
1985 0x00000000);
1986 spr_register(env, SPR_403_VTBU, "TBU",
1987 &spr_read_tbu, SPR_NOACCESS,
1988 &spr_read_tbu, SPR_NOACCESS,
1989 0x00000000);
1990 spr_register(env, SPR_403_TBU, "TBU",
1991 SPR_NOACCESS, SPR_NOACCESS,
1992 SPR_NOACCESS, &spr_write_tbu,
1993 0x00000000);
1994 /* Debug */
1995 /* not emulated, as QEMU do not emulate caches */
1996 spr_register(env, SPR_403_CDBCR, "CDBCR",
1997 SPR_NOACCESS, SPR_NOACCESS,
1998 &spr_read_generic, &spr_write_generic,
1999 0x00000000);
2000 }
2001
2002 /* SPR specific to PowerPC 401 implementation */
2003 static void gen_spr_401 (CPUPPCState *env)
2004 {
2005 /* Debug interface */
2006 /* XXX : not implemented */
2007 spr_register(env, SPR_40x_DBCR0, "DBCR",
2008 SPR_NOACCESS, SPR_NOACCESS,
2009 &spr_read_generic, &spr_write_40x_dbcr0,
2010 0x00000000);
2011 /* XXX : not implemented */
2012 spr_register(env, SPR_40x_DBSR, "DBSR",
2013 SPR_NOACCESS, SPR_NOACCESS,
2014 &spr_read_generic, &spr_write_clear,
2015 /* Last reset was system reset */
2016 0x00000300);
2017 /* XXX : not implemented */
2018 spr_register(env, SPR_40x_DAC1, "DAC",
2019 SPR_NOACCESS, SPR_NOACCESS,
2020 &spr_read_generic, &spr_write_generic,
2021 0x00000000);
2022 /* XXX : not implemented */
2023 spr_register(env, SPR_40x_IAC1, "IAC",
2024 SPR_NOACCESS, SPR_NOACCESS,
2025 &spr_read_generic, &spr_write_generic,
2026 0x00000000);
2027 /* Storage control */
2028 /* XXX: TODO: not implemented */
2029 spr_register(env, SPR_405_SLER, "SLER",
2030 SPR_NOACCESS, SPR_NOACCESS,
2031 &spr_read_generic, &spr_write_40x_sler,
2032 0x00000000);
2033 /* not emulated, as QEMU never does speculative access */
2034 spr_register(env, SPR_40x_SGR, "SGR",
2035 SPR_NOACCESS, SPR_NOACCESS,
2036 &spr_read_generic, &spr_write_generic,
2037 0xFFFFFFFF);
2038 /* not emulated, as QEMU do not emulate caches */
2039 spr_register(env, SPR_40x_DCWR, "DCWR",
2040 SPR_NOACCESS, SPR_NOACCESS,
2041 &spr_read_generic, &spr_write_generic,
2042 0x00000000);
2043 }
2044
2045 static void gen_spr_401x2 (CPUPPCState *env)
2046 {
2047 gen_spr_401(env);
2048 spr_register(env, SPR_40x_PID, "PID",
2049 SPR_NOACCESS, SPR_NOACCESS,
2050 &spr_read_generic, &spr_write_generic,
2051 0x00000000);
2052 spr_register(env, SPR_40x_ZPR, "ZPR",
2053 SPR_NOACCESS, SPR_NOACCESS,
2054 &spr_read_generic, &spr_write_generic,
2055 0x00000000);
2056 }
2057
2058 /* SPR specific to PowerPC 403 implementation */
2059 static void gen_spr_403 (CPUPPCState *env)
2060 {
2061 /* Debug interface */
2062 /* XXX : not implemented */
2063 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2064 SPR_NOACCESS, SPR_NOACCESS,
2065 &spr_read_generic, &spr_write_40x_dbcr0,
2066 0x00000000);
2067 /* XXX : not implemented */
2068 spr_register(env, SPR_40x_DBSR, "DBSR",
2069 SPR_NOACCESS, SPR_NOACCESS,
2070 &spr_read_generic, &spr_write_clear,
2071 /* Last reset was system reset */
2072 0x00000300);
2073 /* XXX : not implemented */
2074 spr_register(env, SPR_40x_DAC1, "DAC1",
2075 SPR_NOACCESS, SPR_NOACCESS,
2076 &spr_read_generic, &spr_write_generic,
2077 0x00000000);
2078 /* XXX : not implemented */
2079 spr_register(env, SPR_40x_DAC2, "DAC2",
2080 SPR_NOACCESS, SPR_NOACCESS,
2081 &spr_read_generic, &spr_write_generic,
2082 0x00000000);
2083 /* XXX : not implemented */
2084 spr_register(env, SPR_40x_IAC1, "IAC1",
2085 SPR_NOACCESS, SPR_NOACCESS,
2086 &spr_read_generic, &spr_write_generic,
2087 0x00000000);
2088 /* XXX : not implemented */
2089 spr_register(env, SPR_40x_IAC2, "IAC2",
2090 SPR_NOACCESS, SPR_NOACCESS,
2091 &spr_read_generic, &spr_write_generic,
2092 0x00000000);
2093 }
2094
2095 static void gen_spr_403_real (CPUPPCState *env)
2096 {
2097 spr_register(env, SPR_403_PBL1, "PBL1",
2098 SPR_NOACCESS, SPR_NOACCESS,
2099 &spr_read_403_pbr, &spr_write_403_pbr,
2100 0x00000000);
2101 spr_register(env, SPR_403_PBU1, "PBU1",
2102 SPR_NOACCESS, SPR_NOACCESS,
2103 &spr_read_403_pbr, &spr_write_403_pbr,
2104 0x00000000);
2105 spr_register(env, SPR_403_PBL2, "PBL2",
2106 SPR_NOACCESS, SPR_NOACCESS,
2107 &spr_read_403_pbr, &spr_write_403_pbr,
2108 0x00000000);
2109 spr_register(env, SPR_403_PBU2, "PBU2",
2110 SPR_NOACCESS, SPR_NOACCESS,
2111 &spr_read_403_pbr, &spr_write_403_pbr,
2112 0x00000000);
2113 }
2114
2115 static void gen_spr_403_mmu (CPUPPCState *env)
2116 {
2117 /* MMU */
2118 spr_register(env, SPR_40x_PID, "PID",
2119 SPR_NOACCESS, SPR_NOACCESS,
2120 &spr_read_generic, &spr_write_generic,
2121 0x00000000);
2122 spr_register(env, SPR_40x_ZPR, "ZPR",
2123 SPR_NOACCESS, SPR_NOACCESS,
2124 &spr_read_generic, &spr_write_generic,
2125 0x00000000);
2126 }
2127
2128 /* SPR specific to PowerPC compression coprocessor extension */
2129 static void gen_spr_compress (CPUPPCState *env)
2130 {
2131 /* XXX : not implemented */
2132 spr_register(env, SPR_401_SKR, "SKR",
2133 SPR_NOACCESS, SPR_NOACCESS,
2134 &spr_read_generic, &spr_write_generic,
2135 0x00000000);
2136 }
2137
2138 #if defined (TARGET_PPC64)
2139 /* SPR specific to PowerPC 620 */
2140 static void gen_spr_620 (CPUPPCState *env)
2141 {
2142 /* Processor identification */
2143 spr_register(env, SPR_PIR, "PIR",
2144 SPR_NOACCESS, SPR_NOACCESS,
2145 &spr_read_generic, &spr_write_pir,
2146 0x00000000);
2147 spr_register(env, SPR_ASR, "ASR",
2148 SPR_NOACCESS, SPR_NOACCESS,
2149 &spr_read_asr, &spr_write_asr,
2150 0x00000000);
2151 /* Breakpoints */
2152 /* XXX : not implemented */
2153 spr_register(env, SPR_IABR, "IABR",
2154 SPR_NOACCESS, SPR_NOACCESS,
2155 &spr_read_generic, &spr_write_generic,
2156 0x00000000);
2157 /* XXX : not implemented */
2158 spr_register(env, SPR_DABR, "DABR",
2159 SPR_NOACCESS, SPR_NOACCESS,
2160 &spr_read_generic, &spr_write_generic,
2161 0x00000000);
2162 /* XXX : not implemented */
2163 spr_register(env, SPR_SIAR, "SIAR",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 &spr_read_generic, SPR_NOACCESS,
2166 0x00000000);
2167 /* XXX : not implemented */
2168 spr_register(env, SPR_SDA, "SDA",
2169 SPR_NOACCESS, SPR_NOACCESS,
2170 &spr_read_generic, SPR_NOACCESS,
2171 0x00000000);
2172 /* XXX : not implemented */
2173 spr_register(env, SPR_620_PMC1R, "PMC1",
2174 SPR_NOACCESS, SPR_NOACCESS,
2175 &spr_read_generic, SPR_NOACCESS,
2176 0x00000000);
2177 spr_register(env, SPR_620_PMC1W, "PMC1",
2178 SPR_NOACCESS, SPR_NOACCESS,
2179 SPR_NOACCESS, &spr_write_generic,
2180 0x00000000);
2181 /* XXX : not implemented */
2182 spr_register(env, SPR_620_PMC2R, "PMC2",
2183 SPR_NOACCESS, SPR_NOACCESS,
2184 &spr_read_generic, SPR_NOACCESS,
2185 0x00000000);
2186 spr_register(env, SPR_620_PMC2W, "PMC2",
2187 SPR_NOACCESS, SPR_NOACCESS,
2188 SPR_NOACCESS, &spr_write_generic,
2189 0x00000000);
2190 /* XXX : not implemented */
2191 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2192 SPR_NOACCESS, SPR_NOACCESS,
2193 &spr_read_generic, SPR_NOACCESS,
2194 0x00000000);
2195 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2196 SPR_NOACCESS, SPR_NOACCESS,
2197 SPR_NOACCESS, &spr_write_generic,
2198 0x00000000);
2199 /* External access control */
2200 /* XXX : not implemented */
2201 spr_register(env, SPR_EAR, "EAR",
2202 SPR_NOACCESS, SPR_NOACCESS,
2203 &spr_read_generic, &spr_write_generic,
2204 0x00000000);
2205 #if 0 // XXX: check this
2206 /* XXX : not implemented */
2207 spr_register(env, SPR_620_PMR0, "PMR0",
2208 SPR_NOACCESS, SPR_NOACCESS,
2209 &spr_read_generic, &spr_write_generic,
2210 0x00000000);
2211 /* XXX : not implemented */
2212 spr_register(env, SPR_620_PMR1, "PMR1",
2213 SPR_NOACCESS, SPR_NOACCESS,
2214 &spr_read_generic, &spr_write_generic,
2215 0x00000000);
2216 /* XXX : not implemented */
2217 spr_register(env, SPR_620_PMR2, "PMR2",
2218 SPR_NOACCESS, SPR_NOACCESS,
2219 &spr_read_generic, &spr_write_generic,
2220 0x00000000);
2221 /* XXX : not implemented */
2222 spr_register(env, SPR_620_PMR3, "PMR3",
2223 SPR_NOACCESS, SPR_NOACCESS,
2224 &spr_read_generic, &spr_write_generic,
2225 0x00000000);
2226 /* XXX : not implemented */
2227 spr_register(env, SPR_620_PMR4, "PMR4",
2228 SPR_NOACCESS, SPR_NOACCESS,
2229 &spr_read_generic, &spr_write_generic,
2230 0x00000000);
2231 /* XXX : not implemented */
2232 spr_register(env, SPR_620_PMR5, "PMR5",
2233 SPR_NOACCESS, SPR_NOACCESS,
2234 &spr_read_generic, &spr_write_generic,
2235 0x00000000);
2236 /* XXX : not implemented */
2237 spr_register(env, SPR_620_PMR6, "PMR6",
2238 SPR_NOACCESS, SPR_NOACCESS,
2239 &spr_read_generic, &spr_write_generic,
2240 0x00000000);
2241 /* XXX : not implemented */
2242 spr_register(env, SPR_620_PMR7, "PMR7",
2243 SPR_NOACCESS, SPR_NOACCESS,
2244 &spr_read_generic, &spr_write_generic,
2245 0x00000000);
2246 /* XXX : not implemented */
2247 spr_register(env, SPR_620_PMR8, "PMR8",
2248 SPR_NOACCESS, SPR_NOACCESS,
2249 &spr_read_generic, &spr_write_generic,
2250 0x00000000);
2251 /* XXX : not implemented */
2252 spr_register(env, SPR_620_PMR9, "PMR9",
2253 SPR_NOACCESS, SPR_NOACCESS,
2254 &spr_read_generic, &spr_write_generic,
2255 0x00000000);
2256 /* XXX : not implemented */
2257 spr_register(env, SPR_620_PMRA, "PMR10",
2258 SPR_NOACCESS, SPR_NOACCESS,
2259 &spr_read_generic, &spr_write_generic,
2260 0x00000000);
2261 /* XXX : not implemented */
2262 spr_register(env, SPR_620_PMRB, "PMR11",
2263 SPR_NOACCESS, SPR_NOACCESS,
2264 &spr_read_generic, &spr_write_generic,
2265 0x00000000);
2266 /* XXX : not implemented */
2267 spr_register(env, SPR_620_PMRC, "PMR12",
2268 SPR_NOACCESS, SPR_NOACCESS,
2269 &spr_read_generic, &spr_write_generic,
2270 0x00000000);
2271 /* XXX : not implemented */
2272 spr_register(env, SPR_620_PMRD, "PMR13",
2273 SPR_NOACCESS, SPR_NOACCESS,
2274 &spr_read_generic, &spr_write_generic,
2275 0x00000000);
2276 /* XXX : not implemented */
2277 spr_register(env, SPR_620_PMRE, "PMR14",
2278 SPR_NOACCESS, SPR_NOACCESS,
2279 &spr_read_generic, &spr_write_generic,
2280 0x00000000);
2281 /* XXX : not implemented */
2282 spr_register(env, SPR_620_PMRF, "PMR15",
2283 SPR_NOACCESS, SPR_NOACCESS,
2284 &spr_read_generic, &spr_write_generic,
2285 0x00000000);
2286 #endif
2287 /* XXX : not implemented */
2288 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2289 SPR_NOACCESS, SPR_NOACCESS,
2290 &spr_read_generic, &spr_write_generic,
2291 0x00000000);
2292 /* XXX : not implemented */
2293 spr_register(env, SPR_620_L2CR, "L2CR",
2294 SPR_NOACCESS, SPR_NOACCESS,
2295 &spr_read_generic, &spr_write_generic,
2296 0x00000000);
2297 /* XXX : not implemented */
2298 spr_register(env, SPR_620_L2SR, "L2SR",
2299 SPR_NOACCESS, SPR_NOACCESS,
2300 &spr_read_generic, &spr_write_generic,
2301 0x00000000);
2302 }
2303 #endif /* defined (TARGET_PPC64) */
2304
2305 static void gen_spr_5xx_8xx (CPUPPCState *env)
2306 {
2307 /* Exception processing */
2308 spr_register(env, SPR_DSISR, "DSISR",
2309 SPR_NOACCESS, SPR_NOACCESS,
2310 &spr_read_generic, &spr_write_generic,
2311 0x00000000);
2312 spr_register(env, SPR_DAR, "DAR",
2313 SPR_NOACCESS, SPR_NOACCESS,
2314 &spr_read_generic, &spr_write_generic,
2315 0x00000000);
2316 /* Timer */
2317 spr_register(env, SPR_DECR, "DECR",
2318 SPR_NOACCESS, SPR_NOACCESS,
2319 &spr_read_decr, &spr_write_decr,
2320 0x00000000);
2321 /* XXX : not implemented */
2322 spr_register(env, SPR_MPC_EIE, "EIE",
2323 SPR_NOACCESS, SPR_NOACCESS,
2324 &spr_read_generic, &spr_write_generic,
2325 0x00000000);
2326 /* XXX : not implemented */
2327 spr_register(env, SPR_MPC_EID, "EID",
2328 SPR_NOACCESS, SPR_NOACCESS,
2329 &spr_read_generic, &spr_write_generic,
2330 0x00000000);
2331 /* XXX : not implemented */
2332 spr_register(env, SPR_MPC_NRI, "NRI",
2333 SPR_NOACCESS, SPR_NOACCESS,
2334 &spr_read_generic, &spr_write_generic,
2335 0x00000000);
2336 /* XXX : not implemented */
2337 spr_register(env, SPR_MPC_CMPA, "CMPA",
2338 SPR_NOACCESS, SPR_NOACCESS,
2339 &spr_read_generic, &spr_write_generic,
2340 0x00000000);
2341 /* XXX : not implemented */
2342 spr_register(env, SPR_MPC_CMPB, "CMPB",
2343 SPR_NOACCESS, SPR_NOACCESS,
2344 &spr_read_generic, &spr_write_generic,
2345 0x00000000);
2346 /* XXX : not implemented */
2347 spr_register(env, SPR_MPC_CMPC, "CMPC",
2348 SPR_NOACCESS, SPR_NOACCESS,
2349 &spr_read_generic, &spr_write_generic,
2350 0x00000000);
2351 /* XXX : not implemented */
2352 spr_register(env, SPR_MPC_CMPD, "CMPD",
2353 SPR_NOACCESS, SPR_NOACCESS,
2354 &spr_read_generic, &spr_write_generic,
2355 0x00000000);
2356 /* XXX : not implemented */
2357 spr_register(env, SPR_MPC_ECR, "ECR",
2358 SPR_NOACCESS, SPR_NOACCESS,
2359 &spr_read_generic, &spr_write_generic,
2360 0x00000000);
2361 /* XXX : not implemented */
2362 spr_register(env, SPR_MPC_DER, "DER",
2363 SPR_NOACCESS, SPR_NOACCESS,
2364 &spr_read_generic, &spr_write_generic,
2365 0x00000000);
2366 /* XXX : not implemented */
2367 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2368 SPR_NOACCESS, SPR_NOACCESS,
2369 &spr_read_generic, &spr_write_generic,
2370 0x00000000);
2371 /* XXX : not implemented */
2372 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2373 SPR_NOACCESS, SPR_NOACCESS,
2374 &spr_read_generic, &spr_write_generic,
2375 0x00000000);
2376 /* XXX : not implemented */
2377 spr_register(env, SPR_MPC_CMPE, "CMPE",
2378 SPR_NOACCESS, SPR_NOACCESS,
2379 &spr_read_generic, &spr_write_generic,
2380 0x00000000);
2381 /* XXX : not implemented */
2382 spr_register(env, SPR_MPC_CMPF, "CMPF",
2383 SPR_NOACCESS, SPR_NOACCESS,
2384 &spr_read_generic, &spr_write_generic,
2385 0x00000000);
2386 /* XXX : not implemented */
2387 spr_register(env, SPR_MPC_CMPG, "CMPG",
2388 SPR_NOACCESS, SPR_NOACCESS,
2389 &spr_read_generic, &spr_write_generic,
2390 0x00000000);
2391 /* XXX : not implemented */
2392 spr_register(env, SPR_MPC_CMPH, "CMPH",
2393 SPR_NOACCESS, SPR_NOACCESS,
2394 &spr_read_generic, &spr_write_generic,
2395 0x00000000);
2396 /* XXX : not implemented */
2397 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2398 SPR_NOACCESS, SPR_NOACCESS,
2399 &spr_read_generic, &spr_write_generic,
2400 0x00000000);
2401 /* XXX : not implemented */
2402 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2403 SPR_NOACCESS, SPR_NOACCESS,
2404 &spr_read_generic, &spr_write_generic,
2405 0x00000000);
2406 /* XXX : not implemented */
2407 spr_register(env, SPR_MPC_BAR, "BAR",
2408 SPR_NOACCESS, SPR_NOACCESS,
2409 &spr_read_generic, &spr_write_generic,
2410 0x00000000);
2411 /* XXX : not implemented */
2412 spr_register(env, SPR_MPC_DPDR, "DPDR",
2413 SPR_NOACCESS, SPR_NOACCESS,
2414 &spr_read_generic, &spr_write_generic,
2415 0x00000000);
2416 /* XXX : not implemented */
2417 spr_register(env, SPR_MPC_IMMR, "IMMR",
2418 SPR_NOACCESS, SPR_NOACCESS,
2419 &spr_read_generic, &spr_write_generic,
2420 0x00000000);
2421 }
2422
2423 static void gen_spr_5xx (CPUPPCState *env)
2424 {
2425 /* XXX : not implemented */
2426 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2427 SPR_NOACCESS, SPR_NOACCESS,
2428 &spr_read_generic, &spr_write_generic,
2429 0x00000000);
2430 /* XXX : not implemented */
2431 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2432 SPR_NOACCESS, SPR_NOACCESS,
2433 &spr_read_generic, &spr_write_generic,
2434 0x00000000);
2435 /* XXX : not implemented */
2436 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2437 SPR_NOACCESS, SPR_NOACCESS,
2438 &spr_read_generic, &spr_write_generic,
2439 0x00000000);
2440 /* XXX : not implemented */
2441 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2442 SPR_NOACCESS, SPR_NOACCESS,
2443 &spr_read_generic, &spr_write_generic,
2444 0x00000000);
2445 /* XXX : not implemented */
2446 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2447 SPR_NOACCESS, SPR_NOACCESS,
2448 &spr_read_generic, &spr_write_generic,
2449 0x00000000);
2450 /* XXX : not implemented */
2451 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2452 SPR_NOACCESS, SPR_NOACCESS,
2453 &spr_read_generic, &spr_write_generic,
2454 0x00000000);
2455 /* XXX : not implemented */
2456 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2457 SPR_NOACCESS, SPR_NOACCESS,
2458 &spr_read_generic, &spr_write_generic,
2459 0x00000000);
2460 /* XXX : not implemented */
2461 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2462 SPR_NOACCESS, SPR_NOACCESS,
2463 &spr_read_generic, &spr_write_generic,
2464 0x00000000);
2465 /* XXX : not implemented */
2466 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2467 SPR_NOACCESS, SPR_NOACCESS,
2468 &spr_read_generic, &spr_write_generic,
2469 0x00000000);
2470 /* XXX : not implemented */
2471 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2472 SPR_NOACCESS, SPR_NOACCESS,
2473 &spr_read_generic, &spr_write_generic,
2474 0x00000000);
2475 /* XXX : not implemented */
2476 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2477 SPR_NOACCESS, SPR_NOACCESS,
2478 &spr_read_generic, &spr_write_generic,
2479 0x00000000);
2480 /* XXX : not implemented */
2481 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2482 SPR_NOACCESS, SPR_NOACCESS,
2483 &spr_read_generic, &spr_write_generic,
2484 0x00000000);
2485 /* XXX : not implemented */
2486 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2487 SPR_NOACCESS, SPR_NOACCESS,
2488 &spr_read_generic, &spr_write_generic,
2489 0x00000000);
2490 /* XXX : not implemented */
2491 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2492 SPR_NOACCESS, SPR_NOACCESS,
2493 &spr_read_generic, &spr_write_generic,
2494 0x00000000);
2495 /* XXX : not implemented */
2496 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2497 SPR_NOACCESS, SPR_NOACCESS,
2498 &spr_read_generic, &spr_write_generic,
2499 0x00000000);
2500 /* XXX : not implemented */
2501 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2502 SPR_NOACCESS, SPR_NOACCESS,
2503 &spr_read_generic, &spr_write_generic,
2504 0x00000000);
2505 /* XXX : not implemented */
2506 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2507 SPR_NOACCESS, SPR_NOACCESS,
2508 &spr_read_generic, &spr_write_generic,
2509 0x00000000);
2510 /* XXX : not implemented */
2511 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2512 SPR_NOACCESS, SPR_NOACCESS,
2513 &spr_read_generic, &spr_write_generic,
2514 0x00000000);
2515 /* XXX : not implemented */
2516 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2517 SPR_NOACCESS, SPR_NOACCESS,
2518 &spr_read_generic, &spr_write_generic,
2519 0x00000000);
2520 /* XXX : not implemented */
2521 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2522 SPR_NOACCESS, SPR_NOACCESS,
2523 &spr_read_generic, &spr_write_generic,
2524 0x00000000);
2525 /* XXX : not implemented */
2526 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2527 SPR_NOACCESS, SPR_NOACCESS,
2528 &spr_read_generic, &spr_write_generic,
2529 0x00000000);
2530 }
2531
2532 static void gen_spr_8xx (CPUPPCState *env)
2533 {
2534 /* XXX : not implemented */
2535 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2536 SPR_NOACCESS, SPR_NOACCESS,
2537 &spr_read_generic, &spr_write_generic,
2538 0x00000000);
2539 /* XXX : not implemented */
2540 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2541 SPR_NOACCESS, SPR_NOACCESS,
2542 &spr_read_generic, &spr_write_generic,
2543 0x00000000);
2544 /* XXX : not implemented */
2545 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2546 SPR_NOACCESS, SPR_NOACCESS,
2547 &spr_read_generic, &spr_write_generic,
2548 0x00000000);
2549 /* XXX : not implemented */
2550 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2551 SPR_NOACCESS, SPR_NOACCESS,
2552 &spr_read_generic, &spr_write_generic,
2553 0x00000000);
2554 /* XXX : not implemented */
2555 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2556 SPR_NOACCESS, SPR_NOACCESS,
2557 &spr_read_generic, &spr_write_generic,
2558 0x00000000);
2559 /* XXX : not implemented */
2560 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2561 SPR_NOACCESS, SPR_NOACCESS,
2562 &spr_read_generic, &spr_write_generic,
2563 0x00000000);
2564 /* XXX : not implemented */
2565 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2566 SPR_NOACCESS, SPR_NOACCESS,
2567 &spr_read_generic, &spr_write_generic,
2568 0x00000000);
2569 /* XXX : not implemented */
2570 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2571 SPR_NOACCESS, SPR_NOACCESS,
2572 &spr_read_generic, &spr_write_generic,
2573 0x00000000);
2574 /* XXX : not implemented */
2575 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2576 SPR_NOACCESS, SPR_NOACCESS,
2577 &spr_read_generic, &spr_write_generic,
2578 0x00000000);
2579 /* XXX : not implemented */
2580 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2581 SPR_NOACCESS, SPR_NOACCESS,
2582 &spr_read_generic, &spr_write_generic,
2583 0x00000000);
2584 /* XXX : not implemented */
2585 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2586 SPR_NOACCESS, SPR_NOACCESS,
2587 &spr_read_generic, &spr_write_generic,
2588 0x00000000);
2589 /* XXX : not implemented */
2590 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2591 SPR_NOACCESS, SPR_NOACCESS,
2592 &spr_read_generic, &spr_write_generic,
2593 0x00000000);
2594 /* XXX : not implemented */
2595 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2596 SPR_NOACCESS, SPR_NOACCESS,
2597 &spr_read_generic, &spr_write_generic,
2598 0x00000000);
2599 /* XXX : not implemented */
2600 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2601 SPR_NOACCESS, SPR_NOACCESS,
2602 &spr_read_generic, &spr_write_generic,
2603 0x00000000);
2604 /* XXX : not implemented */
2605 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2606 SPR_NOACCESS, SPR_NOACCESS,
2607 &spr_read_generic, &spr_write_generic,
2608 0x00000000);
2609 /* XXX : not implemented */
2610 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2611 SPR_NOACCESS, SPR_NOACCESS,
2612 &spr_read_generic, &spr_write_generic,
2613 0x00000000);
2614 /* XXX : not implemented */
2615 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2616 SPR_NOACCESS, SPR_NOACCESS,
2617 &spr_read_generic, &spr_write_generic,
2618 0x00000000);
2619 /* XXX : not implemented */
2620 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2621 SPR_NOACCESS, SPR_NOACCESS,
2622 &spr_read_generic, &spr_write_generic,
2623 0x00000000);
2624 /* XXX : not implemented */
2625 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2626 SPR_NOACCESS, SPR_NOACCESS,
2627 &spr_read_generic, &spr_write_generic,
2628 0x00000000);
2629 /* XXX : not implemented */
2630 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2631 SPR_NOACCESS, SPR_NOACCESS,
2632 &spr_read_generic, &spr_write_generic,
2633 0x00000000);
2634 /* XXX : not implemented */
2635 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2636 SPR_NOACCESS, SPR_NOACCESS,
2637 &spr_read_generic, &spr_write_generic,
2638 0x00000000);
2639 /* XXX : not implemented */
2640 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2641 SPR_NOACCESS, SPR_NOACCESS,
2642 &spr_read_generic, &spr_write_generic,
2643 0x00000000);
2644 /* XXX : not implemented */
2645 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2646 SPR_NOACCESS, SPR_NOACCESS,
2647 &spr_read_generic, &spr_write_generic,
2648 0x00000000);
2649 /* XXX : not implemented */
2650 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2651 SPR_NOACCESS, SPR_NOACCESS,
2652 &spr_read_generic, &spr_write_generic,
2653 0x00000000);
2654 /* XXX : not implemented */
2655 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2656 SPR_NOACCESS, SPR_NOACCESS,
2657 &spr_read_generic, &spr_write_generic,
2658 0x00000000);
2659 }
2660
2661 // XXX: TODO
2662 /*
2663 * AMR => SPR 29 (Power 2.04)
2664 * CTRL => SPR 136 (Power 2.04)
2665 * CTRL => SPR 152 (Power 2.04)
2666 * SCOMC => SPR 276 (64 bits ?)
2667 * SCOMD => SPR 277 (64 bits ?)
2668 * TBU40 => SPR 286 (Power 2.04 hypv)
2669 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2670 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2671 * HDSISR => SPR 306 (Power 2.04 hypv)
2672 * HDAR => SPR 307 (Power 2.04 hypv)
2673 * PURR => SPR 309 (Power 2.04 hypv)
2674 * HDEC => SPR 310 (Power 2.04 hypv)
2675 * HIOR => SPR 311 (hypv)
2676 * RMOR => SPR 312 (970)
2677 * HRMOR => SPR 313 (Power 2.04 hypv)
2678 * HSRR0 => SPR 314 (Power 2.04 hypv)
2679 * HSRR1 => SPR 315 (Power 2.04 hypv)
2680 * LPCR => SPR 316 (970)
2681 * LPIDR => SPR 317 (970)
2682 * EPR => SPR 702 (Power 2.04 emb)
2683 * perf => 768-783 (Power 2.04)
2684 * perf => 784-799 (Power 2.04)
2685 * PPR => SPR 896 (Power 2.04)
2686 * EPLC => SPR 947 (Power 2.04 emb)
2687 * EPSC => SPR 948 (Power 2.04 emb)
2688 * DABRX => 1015 (Power 2.04 hypv)
2689 * FPECR => SPR 1022 (?)
2690 * ... and more (thermal management, performance counters, ...)
2691 */
2692
2693 /*****************************************************************************/
2694 /* Exception vectors models */
2695 static void init_excp_4xx_real (CPUPPCState *env)
2696 {
2697 #if !defined(CONFIG_USER_ONLY)
2698 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2699 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2700 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2701 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2702 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2703 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2704 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2705 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2706 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2707 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2708 env->hreset_excp_prefix = 0x00000000UL;
2709 env->ivor_mask = 0x0000FFF0UL;
2710 env->ivpr_mask = 0xFFFF0000UL;
2711 /* Hardware reset vector */
2712 env->hreset_vector = 0xFFFFFFFCUL;
2713 #endif
2714 }
2715
2716 static void init_excp_4xx_softmmu (CPUPPCState *env)
2717 {
2718 #if !defined(CONFIG_USER_ONLY)
2719 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2720 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2721 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2722 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2723 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2724 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2725 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2726 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2727 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2728 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2729 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2730 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2731 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2732 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2733 env->hreset_excp_prefix = 0x00000000UL;
2734 env->ivor_mask = 0x0000FFF0UL;
2735 env->ivpr_mask = 0xFFFF0000UL;
2736 /* Hardware reset vector */
2737 env->hreset_vector = 0xFFFFFFFCUL;
2738 #endif
2739 }
2740
2741 static void init_excp_MPC5xx (CPUPPCState *env)
2742 {
2743 #if !defined(CONFIG_USER_ONLY)
2744 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2745 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2746 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2747 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2748 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2749 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2750 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2751 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2752 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2753 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2754 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2755 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2756 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2757 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2758 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2759 env->hreset_excp_prefix = 0x00000000UL;
2760 env->ivor_mask = 0x0000FFF0UL;
2761 env->ivpr_mask = 0xFFFF0000UL;
2762 /* Hardware reset vector */
2763 env->hreset_vector = 0xFFFFFFFCUL;
2764 #endif
2765 }
2766
2767 static void init_excp_MPC8xx (CPUPPCState *env)
2768 {
2769 #if !defined(CONFIG_USER_ONLY)
2770 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2771 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2772 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2773 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2774 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2775 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2776 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2777 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2778 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2779 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2780 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2781 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2782 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2783 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2784 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2785 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2786 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2787 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2788 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2789 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2790 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2791 env->hreset_excp_prefix = 0x00000000UL;
2792 env->ivor_mask = 0x0000FFF0UL;
2793 env->ivpr_mask = 0xFFFF0000UL;
2794 /* Hardware reset vector */
2795 env->hreset_vector = 0xFFFFFFFCUL;
2796 #endif
2797 }
2798
2799 static void init_excp_G2 (CPUPPCState *env)
2800 {
2801 #if !defined(CONFIG_USER_ONLY)
2802 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2803 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2804 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2805 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2806 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2807 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2808 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2809 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2810 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2811 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2812 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2813 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2814 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2815 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2816 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2817 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2818 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2819 env->hreset_excp_prefix = 0x00000000UL;
2820 /* Hardware reset vector */
2821 env->hreset_vector = 0xFFFFFFFCUL;
2822 #endif
2823 }
2824
2825 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2826 {
2827 #if !defined(CONFIG_USER_ONLY)
2828 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2829 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2830 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2831 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2832 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2833 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2834 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2835 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2836 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2837 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2838 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2839 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2840 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2841 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2842 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2843 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2844 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2845 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2846 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2847 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2848 env->hreset_excp_prefix = 0x00000000UL;
2849 env->ivor_mask = 0x0000FFF7UL;
2850 env->ivpr_mask = ivpr_mask;
2851 /* Hardware reset vector */
2852 env->hreset_vector = 0xFFFFFFFCUL;
2853 #endif
2854 }
2855
2856 static void init_excp_BookE (CPUPPCState *env)
2857 {
2858 #if !defined(CONFIG_USER_ONLY)
2859 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2860 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2861 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2862 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2863 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2864 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2865 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2866 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2867 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2868 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2869 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2870 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2871 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2872 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2873 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2874 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2875 env->hreset_excp_prefix = 0x00000000UL;
2876 env->ivor_mask = 0x0000FFE0UL;
2877 env->ivpr_mask = 0xFFFF0000UL;
2878 /* Hardware reset vector */
2879 env->hreset_vector = 0xFFFFFFFCUL;
2880 #endif
2881 }
2882
2883 static void init_excp_601 (CPUPPCState *env)
2884 {
2885 #if !defined(CONFIG_USER_ONLY)
2886 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2887 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2888 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2889 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2890 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2891 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2892 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2893 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2894 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2895 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2896 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2897 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2898 env->hreset_excp_prefix = 0xFFF00000UL;
2899 /* Hardware reset vector */
2900 env->hreset_vector = 0x00000100UL;
2901 #endif
2902 }
2903
2904 static void init_excp_602 (CPUPPCState *env)
2905 {
2906 #if !defined(CONFIG_USER_ONLY)
2907 /* XXX: exception prefix has a special behavior on 602 */
2908 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2909 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2910 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2911 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2912 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2913 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2914 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2915 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2916 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2917 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2918 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2919 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2920 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2921 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2922 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2923 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2924 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2925 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2926 env->hreset_excp_prefix = 0xFFF00000UL;
2927 /* Hardware reset vector */
2928 env->hreset_vector = 0xFFFFFFFCUL;
2929 #endif
2930 }
2931
2932 static void init_excp_603 (CPUPPCState *env)
2933 {
2934 #if !defined(CONFIG_USER_ONLY)
2935 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2936 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2937 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2938 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2939 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2940 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2941 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2942 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2943 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2944 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2945 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2946 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2947 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2948 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2949 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2950 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2951 env->hreset_excp_prefix = 0x00000000UL;
2952 /* Hardware reset vector */
2953 env->hreset_vector = 0xFFFFFFFCUL;
2954 #endif
2955 }
2956
2957 static void init_excp_604 (CPUPPCState *env)
2958 {
2959 #if !defined(CONFIG_USER_ONLY)
2960 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2961 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2962 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2963 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2964 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2965 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2966 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2967 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2968 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2969 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2970 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2971 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2972 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2973 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2974 env->hreset_excp_prefix = 0xFFF00000UL;
2975 /* Hardware reset vector */
2976 env->hreset_vector = 0x00000100UL;
2977 #endif
2978 }
2979
2980 #if defined(TARGET_PPC64)
2981 static void init_excp_620 (CPUPPCState *env)
2982 {
2983 #if !defined(CONFIG_USER_ONLY)
2984 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2985 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2986 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2987 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2988 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2989 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2990 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2991 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2992 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2993 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2994 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2995 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2996 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2997 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2998 env->hreset_excp_prefix = 0xFFF00000UL;
2999 /* Hardware reset vector */
3000 env->hreset_vector = 0x0000000000000100ULL;
3001 #endif
3002 }
3003 #endif /* defined(TARGET_PPC64) */
3004
3005 static void init_excp_7x0 (CPUPPCState *env)
3006 {
3007 #if !defined(CONFIG_USER_ONLY)
3008 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3009 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3010 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3011 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3012 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3013 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3014 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3015 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3016 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3017 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3018 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3019 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3020 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3021 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3022 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3023 env->hreset_excp_prefix = 0x00000000UL;
3024 /* Hardware reset vector */
3025 env->hreset_vector = 0xFFFFFFFCUL;
3026 #endif
3027 }
3028
3029 static void init_excp_750cl (CPUPPCState *env)
3030 {
3031 #if !defined(CONFIG_USER_ONLY)
3032 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3033 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3034 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3035 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3036 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3037 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3038 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3039 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3040 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3041 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3042 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3043 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3044 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3045 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3046 env->hreset_excp_prefix = 0x00000000UL;
3047 /* Hardware reset vector */
3048 env->hreset_vector = 0xFFFFFFFCUL;
3049 #endif
3050 }
3051
3052 static void init_excp_750cx (CPUPPCState *env)
3053 {
3054 #if !defined(CONFIG_USER_ONLY)
3055 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3056 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3057 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3058 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3059 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3060 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3061 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3062 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3063 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3064 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3065 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3066 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3067 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3068 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3069 env->hreset_excp_prefix = 0x00000000UL;
3070 /* Hardware reset vector */
3071 env->hreset_vector = 0xFFFFFFFCUL;
3072 #endif
3073 }
3074
3075 /* XXX: Check if this is correct */
3076 static void init_excp_7x5 (CPUPPCState *env)
3077 {
3078 #if !defined(CONFIG_USER_ONLY)
3079 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3080 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3081 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3082 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3083 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3084 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3085 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3086 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3087 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3088 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3089 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3090 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3091 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3092 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3093 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3094 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3095 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3096 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3097 env->hreset_excp_prefix = 0x00000000UL;
3098 /* Hardware reset vector */
3099 env->hreset_vector = 0xFFFFFFFCUL;
3100 #endif
3101 }
3102
3103 static void init_excp_7400 (CPUPPCState *env)
3104 {
3105 #if !defined(CONFIG_USER_ONLY)
3106 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3107 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3108 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3109 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3110 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3111 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3112 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3113 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3114 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3115 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3116 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3117 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3118 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3119 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3120 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3121 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3122 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3123 env->hreset_excp_prefix = 0x00000000UL;
3124 /* Hardware reset vector */
3125 env->hreset_vector = 0xFFFFFFFCUL;
3126 #endif
3127 }
3128
3129 static void init_excp_7450 (CPUPPCState *env)
3130 {
3131 #if !defined(CONFIG_USER_ONLY)
3132 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3133 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3134 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3135 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3136 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3137 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3138 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3139 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3140 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3141 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3142 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3143 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3144 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3145 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3146 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3147 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3148 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3149 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3150 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3151 env->hreset_excp_prefix = 0x00000000UL;
3152 /* Hardware reset vector */
3153 env->hreset_vector = 0xFFFFFFFCUL;
3154 #endif
3155 }
3156
3157 #if defined (TARGET_PPC64)
3158 static void init_excp_970 (CPUPPCState *env)
3159 {
3160 #if !defined(CONFIG_USER_ONLY)
3161 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3162 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3163 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3164 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3165 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3166 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3167 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3168 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3169 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3170 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3171 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3172 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3173 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3174 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3175 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3176 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3177 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3178 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3179 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3180 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3181 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
3182 /* Hardware reset vector */
3183 env->hreset_vector = 0x0000000000000100ULL;
3184 #endif
3185 }
3186
3187 static void init_excp_POWER7 (CPUPPCState *env)
3188 {
3189 #if !defined(CONFIG_USER_ONLY)
3190 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3191 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3192 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3193 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3194 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3195 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3196 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3197 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3198 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3199 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3200 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3201 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3202 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3203 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3204 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3205 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3206 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3207 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3208 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3209 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3210 env->hreset_excp_prefix = 0;
3211 /* Hardware reset vector */
3212 env->hreset_vector = 0x0000000000000100ULL;
3213 #endif
3214 }
3215 #endif
3216
3217 /*****************************************************************************/
3218 /* Power management enable checks */
3219 static int check_pow_none (CPUPPCState *env)
3220 {
3221 return 0;
3222 }
3223
3224 static int check_pow_nocheck (CPUPPCState *env)
3225 {
3226 return 1;
3227 }
3228
3229 static int check_pow_hid0 (CPUPPCState *env)
3230 {
3231 if (env->spr[SPR_HID0] & 0x00E00000)
3232 return 1;
3233
3234 return 0;
3235 }
3236
3237 static int check_pow_hid0_74xx (CPUPPCState *env)
3238 {
3239 if (env->spr[SPR_HID0] & 0x00600000)
3240 return 1;
3241
3242 return 0;
3243 }
3244
3245 /*****************************************************************************/
3246 /* PowerPC implementations definitions */
3247
3248 #define POWERPC_FAMILY(_name) \
3249 static void \
3250 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3251 \
3252 static const TypeInfo \
3253 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3254 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3255 .parent = TYPE_POWERPC_CPU, \
3256 .abstract = true, \
3257 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3258 }; \
3259 \
3260 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3261 { \
3262 type_register_static( \
3263 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3264 } \
3265 \
3266 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3267 \
3268 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3269
3270 static void init_proc_401 (CPUPPCState *env)
3271 {
3272 gen_spr_40x(env);
3273 gen_spr_401_403(env);
3274 gen_spr_401(env);
3275 init_excp_4xx_real(env);
3276 env->dcache_line_size = 32;
3277 env->icache_line_size = 32;
3278 /* Allocate hardware IRQ controller */
3279 ppc40x_irq_init(env);
3280
3281 SET_FIT_PERIOD(12, 16, 20, 24);
3282 SET_WDT_PERIOD(16, 20, 24, 28);
3283 }
3284
3285 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3286 {
3287 DeviceClass *dc = DEVICE_CLASS(oc);
3288 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3289
3290 dc->desc = "PowerPC 401";
3291 pcc->init_proc = init_proc_401;
3292 pcc->check_pow = check_pow_nocheck;
3293 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3294 PPC_WRTEE | PPC_DCR |
3295 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3296 PPC_CACHE_DCBZ |
3297 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3298 PPC_4xx_COMMON | PPC_40x_EXCP;
3299 pcc->insns_flags2 = PPC_NONE;
3300 pcc->msr_mask = 0x00000000000FD201ULL;
3301 pcc->mmu_model = POWERPC_MMU_REAL;
3302 pcc->excp_model = POWERPC_EXCP_40x;
3303 pcc->bus_model = PPC_FLAGS_INPUT_401;
3304 pcc->bfd_mach = bfd_mach_ppc_403;
3305 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3306 POWERPC_FLAG_BUS_CLK;
3307 }
3308
3309 static void init_proc_401x2 (CPUPPCState *env)
3310 {
3311 gen_spr_40x(env);
3312 gen_spr_401_403(env);
3313 gen_spr_401x2(env);
3314 gen_spr_compress(env);
3315 /* Memory management */
3316 #if !defined(CONFIG_USER_ONLY)
3317 env->nb_tlb = 64;
3318 env->nb_ways = 1;
3319 env->id_tlbs = 0;
3320 env->tlb_type = TLB_EMB;
3321 #endif
3322 init_excp_4xx_softmmu(env);
3323 env->dcache_line_size = 32;
3324 env->icache_line_size = 32;
3325 /* Allocate hardware IRQ controller */
3326 ppc40x_irq_init(env);
3327
3328 SET_FIT_PERIOD(12, 16, 20, 24);
3329 SET_WDT_PERIOD(16, 20, 24, 28);
3330 }
3331
3332 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3333 {
3334 DeviceClass *dc = DEVICE_CLASS(oc);
3335 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3336
3337 dc->desc = "PowerPC 401x2";
3338 pcc->init_proc = init_proc_401x2;
3339 pcc->check_pow = check_pow_nocheck;
3340 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3341 PPC_DCR | PPC_WRTEE |
3342 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3343 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3344 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3345 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3346 PPC_4xx_COMMON | PPC_40x_EXCP;
3347 pcc->insns_flags2 = PPC_NONE;
3348 pcc->msr_mask = 0x00000000001FD231ULL;
3349 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3350 pcc->excp_model = POWERPC_EXCP_40x;
3351 pcc->bus_model = PPC_FLAGS_INPUT_401;
3352 pcc->bfd_mach = bfd_mach_ppc_403;
3353 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3354 POWERPC_FLAG_BUS_CLK;
3355 }
3356
3357 static void init_proc_401x3 (CPUPPCState *env)
3358 {
3359 gen_spr_40x(env);
3360 gen_spr_401_403(env);
3361 gen_spr_401(env);
3362 gen_spr_401x2(env);
3363 gen_spr_compress(env);
3364 init_excp_4xx_softmmu(env);
3365 env->dcache_line_size = 32;
3366 env->icache_line_size = 32;
3367 /* Allocate hardware IRQ controller */
3368 ppc40x_irq_init(env);
3369
3370 SET_FIT_PERIOD(12, 16, 20, 24);
3371 SET_WDT_PERIOD(16, 20, 24, 28);
3372 }
3373
3374 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3375 {
3376 DeviceClass *dc = DEVICE_CLASS(oc);
3377 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3378
3379 dc->desc = "PowerPC 401x3";
3380 pcc->init_proc = init_proc_401x3;
3381 pcc->check_pow = check_pow_nocheck;
3382 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3383 PPC_DCR | PPC_WRTEE |
3384 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3385 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3386 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3387 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3388 PPC_4xx_COMMON | PPC_40x_EXCP;
3389 pcc->insns_flags2 = PPC_NONE;
3390 pcc->msr_mask = 0x00000000001FD631ULL;
3391 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3392 pcc->excp_model = POWERPC_EXCP_40x;
3393 pcc->bus_model = PPC_FLAGS_INPUT_401;
3394 pcc->bfd_mach = bfd_mach_ppc_403;
3395 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3396 POWERPC_FLAG_BUS_CLK;
3397 }
3398
3399 static void init_proc_IOP480 (CPUPPCState *env)
3400 {
3401 gen_spr_40x(env);
3402 gen_spr_401_403(env);
3403 gen_spr_401x2(env);
3404 gen_spr_compress(env);
3405 /* Memory management */
3406 #if !defined(CONFIG_USER_ONLY)
3407 env->nb_tlb = 64;
3408 env->nb_ways = 1;
3409 env->id_tlbs = 0;
3410 env->tlb_type = TLB_EMB;
3411 #endif
3412 init_excp_4xx_softmmu(env);
3413 env->dcache_line_size = 32;
3414 env->icache_line_size = 32;
3415 /* Allocate hardware IRQ controller */
3416 ppc40x_irq_init(env);
3417
3418 SET_FIT_PERIOD(8, 12, 16, 20);
3419 SET_WDT_PERIOD(16, 20, 24, 28);
3420 }
3421
3422 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3423 {
3424 DeviceClass *dc = DEVICE_CLASS(oc);
3425 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3426
3427 dc->desc = "IOP480";
3428 pcc->init_proc = init_proc_IOP480;
3429 pcc->check_pow = check_pow_nocheck;
3430 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3431 PPC_DCR | PPC_WRTEE |
3432 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3433 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3434 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3435 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3436 PPC_4xx_COMMON | PPC_40x_EXCP;
3437 pcc->insns_flags2 = PPC_NONE;
3438 pcc->msr_mask = 0x00000000001FD231ULL;
3439 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3440 pcc->excp_model = POWERPC_EXCP_40x;
3441 pcc->bus_model = PPC_FLAGS_INPUT_401;
3442 pcc->bfd_mach = bfd_mach_ppc_403;
3443 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3444 POWERPC_FLAG_BUS_CLK;
3445 }
3446
3447 static void init_proc_403 (CPUPPCState *env)
3448 {
3449 gen_spr_40x(env);
3450 gen_spr_401_403(env);
3451 gen_spr_403(env);
3452 gen_spr_403_real(env);
3453 init_excp_4xx_real(env);
3454 env->dcache_line_size = 32;
3455 env->icache_line_size = 32;
3456 /* Allocate hardware IRQ controller */
3457 ppc40x_irq_init(env);
3458
3459 SET_FIT_PERIOD(8, 12, 16, 20);
3460 SET_WDT_PERIOD(16, 20, 24, 28);
3461 }
3462
3463 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3464 {
3465 DeviceClass *dc = DEVICE_CLASS(oc);
3466 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3467
3468 dc->desc = "PowerPC 403";
3469 pcc->init_proc = init_proc_403;
3470 pcc->check_pow = check_pow_nocheck;
3471 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3472 PPC_DCR | PPC_WRTEE |
3473 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3474 PPC_CACHE_DCBZ |
3475 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3476 PPC_4xx_COMMON | PPC_40x_EXCP;
3477 pcc->insns_flags2 = PPC_NONE;
3478 pcc->msr_mask = 0x000000000007D00DULL;
3479 pcc->mmu_model = POWERPC_MMU_REAL;
3480 pcc->excp_model = POWERPC_EXCP_40x;
3481 pcc->bus_model = PPC_FLAGS_INPUT_401;
3482 pcc->bfd_mach = bfd_mach_ppc_403;
3483 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3484 POWERPC_FLAG_BUS_CLK;
3485 }
3486
3487 static void init_proc_403GCX (CPUPPCState *env)
3488 {
3489 gen_spr_40x(env);
3490 gen_spr_401_403(env);
3491 gen_spr_403(env);
3492 gen_spr_403_real(env);
3493 gen_spr_403_mmu(env);
3494 /* Bus access control */
3495 /* not emulated, as QEMU never does speculative access */
3496 spr_register(env, SPR_40x_SGR, "SGR",
3497 SPR_NOACCESS, SPR_NOACCESS,
3498 &spr_read_generic, &spr_write_generic,
3499 0xFFFFFFFF);
3500 /* not emulated, as QEMU do not emulate caches */
3501 spr_register(env, SPR_40x_DCWR, "DCWR",
3502 SPR_NOACCESS, SPR_NOACCESS,
3503 &spr_read_generic, &spr_write_generic,
3504 0x00000000);
3505 /* Memory management */
3506 #if !defined(CONFIG_USER_ONLY)
3507 env->nb_tlb = 64;
3508 env->nb_ways = 1;
3509 env->id_tlbs = 0;
3510 env->tlb_type = TLB_EMB;
3511 #endif
3512 init_excp_4xx_softmmu(env);
3513 env->dcache_line_size = 32;
3514 env->icache_line_size = 32;
3515 /* Allocate hardware IRQ controller */
3516 ppc40x_irq_init(env);
3517
3518 SET_FIT_PERIOD(8, 12, 16, 20);
3519 SET_WDT_PERIOD(16, 20, 24, 28);
3520 }
3521
3522 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3523 {
3524 DeviceClass *dc = DEVICE_CLASS(oc);
3525 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3526
3527 dc->desc = "PowerPC 403 GCX";
3528 pcc->init_proc = init_proc_403GCX;
3529 pcc->check_pow = check_pow_nocheck;
3530 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3531 PPC_DCR | PPC_WRTEE |
3532 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3533 PPC_CACHE_DCBZ |
3534 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3535 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3536 PPC_4xx_COMMON | PPC_40x_EXCP;
3537 pcc->insns_flags2 = PPC_NONE;
3538 pcc->msr_mask = 0x000000000007D00DULL;
3539 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3540 pcc->excp_model = POWERPC_EXCP_40x;
3541 pcc->bus_model = PPC_FLAGS_INPUT_401;
3542 pcc->bfd_mach = bfd_mach_ppc_403;
3543 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3544 POWERPC_FLAG_BUS_CLK;
3545 }
3546
3547 static void init_proc_405 (CPUPPCState *env)
3548 {
3549 /* Time base */
3550 gen_tbl(env);
3551 gen_spr_40x(env);
3552 gen_spr_405(env);
3553 /* Bus access control */
3554 /* not emulated, as QEMU never does speculative access */
3555 spr_register(env, SPR_40x_SGR, "SGR",
3556 SPR_NOACCESS, SPR_NOACCESS,
3557 &spr_read_generic, &spr_write_generic,
3558 0xFFFFFFFF);
3559 /* not emulated, as QEMU do not emulate caches */
3560 spr_register(env, SPR_40x_DCWR, "DCWR",
3561 SPR_NOACCESS, SPR_NOACCESS,
3562 &spr_read_generic, &spr_write_generic,
3563 0x00000000);
3564 /* Memory management */
3565 #if !defined(CONFIG_USER_ONLY)
3566 env->nb_tlb = 64;
3567 env->nb_ways = 1;
3568 env->id_tlbs = 0;
3569 env->tlb_type = TLB_EMB;
3570 #endif
3571 init_excp_4xx_softmmu(env);
3572 env->dcache_line_size = 32;
3573 env->icache_line_size = 32;
3574 /* Allocate hardware IRQ controller */
3575 ppc40x_irq_init(env);
3576
3577 SET_FIT_PERIOD(8, 12, 16, 20);
3578 SET_WDT_PERIOD(16, 20, 24, 28);
3579 }
3580
3581 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3582 {
3583 DeviceClass *dc = DEVICE_CLASS(oc);
3584 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3585
3586 dc->desc = "PowerPC 405";
3587 pcc->init_proc = init_proc_405;
3588 pcc->check_pow = check_pow_nocheck;
3589 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3590 PPC_DCR | PPC_WRTEE |
3591 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3592 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3593 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3594 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3595 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3596 pcc->insns_flags2 = PPC_NONE;
3597 pcc->msr_mask = 0x000000000006E630ULL;
3598 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3599 pcc->excp_model = POWERPC_EXCP_40x;
3600 pcc->bus_model = PPC_FLAGS_INPUT_405;
3601 pcc->bfd_mach = bfd_mach_ppc_403;
3602 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3603 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3604 }
3605
3606 static void init_proc_440EP (CPUPPCState *env)
3607 {
3608 /* Time base */
3609 gen_tbl(env);
3610 gen_spr_BookE(env, 0x000000000000FFFFULL);
3611 gen_spr_440(env);
3612 gen_spr_usprgh(env);
3613 /* Processor identification */
3614 spr_register(env, SPR_BOOKE_PIR, "PIR",
3615 SPR_NOACCESS, SPR_NOACCESS,
3616 &spr_read_generic, &spr_write_pir,
3617 0x00000000);
3618 /* XXX : not implemented */
3619 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3620 SPR_NOACCESS, SPR_NOACCESS,
3621 &spr_read_generic, &spr_write_generic,
3622 0x00000000);
3623 /* XXX : not implemented */
3624 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3625 SPR_NOACCESS, SPR_NOACCESS,
3626 &spr_read_generic, &spr_write_generic,
3627 0x00000000);
3628 /* XXX : not implemented */
3629 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3630 SPR_NOACCESS, SPR_NOACCESS,
3631 &spr_read_generic, &spr_write_generic,
3632 0x00000000);
3633 /* XXX : not implemented */
3634 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3635 SPR_NOACCESS, SPR_NOACCESS,
3636 &spr_read_generic, &spr_write_generic,
3637 0x00000000);
3638 /* XXX : not implemented */
3639 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3640 SPR_NOACCESS, SPR_NOACCESS,
3641 &spr_read_generic, &spr_write_generic,
3642 0x00000000);
3643 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3644 SPR_NOACCESS, SPR_NOACCESS,
3645 &spr_read_generic, &spr_write_generic,
3646 0x00000000);
3647 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3648 SPR_NOACCESS, SPR_NOACCESS,
3649 &spr_read_generic, &spr_write_generic,
3650 0x00000000);
3651 /* XXX : not implemented */
3652 spr_register(env, SPR_440_CCR1, "CCR1",
3653 SPR_NOACCESS, SPR_NOACCESS,
3654 &spr_read_generic, &spr_write_generic,
3655 0x00000000);
3656 /* Memory management */
3657 #if !defined(CONFIG_USER_ONLY)
3658 env->nb_tlb = 64;
3659 env->nb_ways = 1;
3660 env->id_tlbs = 0;
3661 env->tlb_type = TLB_EMB;
3662 #endif
3663 init_excp_BookE(env);
3664 env->dcache_line_size = 32;
3665 env->icache_line_size = 32;
3666 ppc40x_irq_init(env);
3667
3668 SET_FIT_PERIOD(12, 16, 20, 24);
3669 SET_WDT_PERIOD(20, 24, 28, 32);
3670 }
3671
3672 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3673 {
3674 DeviceClass *dc = DEVICE_CLASS(oc);
3675 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3676
3677 dc->desc = "PowerPC 440 EP";
3678 pcc->init_proc = init_proc_440EP;
3679 pcc->check_pow = check_pow_nocheck;
3680 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3681 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3682 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3683 PPC_FLOAT_STFIWX |
3684 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3685 PPC_CACHE | PPC_CACHE_ICBI |
3686 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3687 PPC_MEM_TLBSYNC | PPC_MFTB |
3688 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3689 PPC_440_SPEC;
3690 pcc->insns_flags2 = PPC_NONE;
3691 pcc->msr_mask = 0x000000000006FF30ULL;
3692 pcc->mmu_model = POWERPC_MMU_BOOKE;
3693 pcc->excp_model = POWERPC_EXCP_BOOKE;
3694 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3695 pcc->bfd_mach = bfd_mach_ppc_403;
3696 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3697 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3698 }
3699
3700 static void init_proc_440GP (CPUPPCState *env)
3701 {
3702 /* Time base */
3703 gen_tbl(env);
3704 gen_spr_BookE(env, 0x000000000000FFFFULL);
3705 gen_spr_440(env);
3706 gen_spr_usprgh(env);
3707 /* Processor identification */
3708 spr_register(env, SPR_BOOKE_PIR, "PIR",
3709 SPR_NOACCESS, SPR_NOACCESS,
3710 &spr_read_generic, &spr_write_pir,
3711 0x00000000);
3712 /* XXX : not implemented */
3713 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3714 SPR_NOACCESS, SPR_NOACCESS,
3715 &spr_read_generic, &spr_write_generic,
3716 0x00000000);
3717 /* XXX : not implemented */
3718 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3719 SPR_NOACCESS, SPR_NOACCESS,
3720 &spr_read_generic, &spr_write_generic,
3721 0x00000000);
3722 /* XXX : not implemented */
3723 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3724 SPR_NOACCESS, SPR_NOACCESS,
3725 &spr_read_generic, &spr_write_generic,
3726 0x00000000);
3727 /* XXX : not implemented */
3728 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3729 SPR_NOACCESS, SPR_NOACCESS,
3730 &spr_read_generic, &spr_write_generic,
3731 0x00000000);
3732 /* Memory management */
3733 #if !defined(CONFIG_USER_ONLY)
3734 env->nb_tlb = 64;
3735 env->nb_ways = 1;
3736 env->id_tlbs = 0;
3737 env->tlb_type = TLB_EMB;
3738 #endif
3739 init_excp_BookE(env);
3740 env->dcache_line_size = 32;
3741 env->icache_line_size = 32;
3742 /* XXX: TODO: allocate internal IRQ controller */
3743
3744 SET_FIT_PERIOD(12, 16, 20, 24);
3745 SET_WDT_PERIOD(20, 24, 28, 32);
3746 }
3747
3748 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3749 {
3750 DeviceClass *dc = DEVICE_CLASS(oc);
3751 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3752
3753 dc->desc = "PowerPC 440 GP";
3754 pcc->init_proc = init_proc_440GP;
3755 pcc->check_pow = check_pow_nocheck;
3756 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3757 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3758 PPC_CACHE | PPC_CACHE_ICBI |
3759 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3760 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3761 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3762 PPC_440_SPEC;
3763 pcc->insns_flags2 = PPC_NONE;
3764 pcc->msr_mask = 0x000000000006FF30ULL;
3765 pcc->mmu_model = POWERPC_MMU_BOOKE;
3766 pcc->excp_model = POWERPC_EXCP_BOOKE;
3767 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3768 pcc->bfd_mach = bfd_mach_ppc_403;
3769 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3770 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3771 }
3772
3773 static void init_proc_440x4 (CPUPPCState *env)
3774 {
3775 /* Time base */
3776 gen_tbl(env);
3777 gen_spr_BookE(env, 0x000000000000FFFFULL);
3778 gen_spr_440(env);
3779 gen_spr_usprgh(env);
3780 /* Processor identification */
3781 spr_register(env, SPR_BOOKE_PIR, "PIR",
3782 SPR_NOACCESS, SPR_NOACCESS,
3783 &spr_read_generic, &spr_write_pir,
3784 0x00000000);
3785 /* XXX : not implemented */
3786 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3787 SPR_NOACCESS, SPR_NOACCESS,
3788 &spr_read_generic, &spr_write_generic,
3789 0x00000000);
3790 /* XXX : not implemented */
3791 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3792 SPR_NOACCESS, SPR_NOACCESS,
3793 &spr_read_generic, &spr_write_generic,
3794 0x00000000);
3795 /* XXX : not implemented */
3796 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3797 SPR_NOACCESS, SPR_NOACCESS,
3798 &spr_read_generic, &spr_write_generic,
3799 0x00000000);
3800 /* XXX : not implemented */
3801 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3802 SPR_NOACCESS, SPR_NOACCESS,
3803 &spr_read_generic, &spr_write_generic,
3804 0x00000000);
3805 /* Memory management */
3806 #if !defined(CONFIG_USER_ONLY)
3807 env->nb_tlb = 64;
3808 env->nb_ways = 1;
3809 env->id_tlbs = 0;
3810 env->tlb_type = TLB_EMB;
3811 #endif
3812 init_excp_BookE(env);
3813 env->dcache_line_size = 32;
3814 env->icache_line_size = 32;
3815 /* XXX: TODO: allocate internal IRQ controller */
3816
3817 SET_FIT_PERIOD(12, 16, 20, 24);
3818 SET_WDT_PERIOD(20, 24, 28, 32);
3819 }
3820
3821 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3822 {
3823 DeviceClass *dc = DEVICE_CLASS(oc);
3824 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3825
3826 dc->desc = "PowerPC 440x4";
3827 pcc->init_proc = init_proc_440x4;
3828 pcc->check_pow = check_pow_nocheck;
3829 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3830 PPC_DCR | PPC_WRTEE |
3831 PPC_CACHE | PPC_CACHE_ICBI |
3832 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3833 PPC_MEM_TLBSYNC | PPC_MFTB |
3834 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3835 PPC_440_SPEC;
3836 pcc->insns_flags2 = PPC_NONE;
3837 pcc->msr_mask = 0x000000000006FF30ULL;
3838 pcc->mmu_model = POWERPC_MMU_BOOKE;
3839 pcc->excp_model = POWERPC_EXCP_BOOKE;
3840 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3841 pcc->bfd_mach = bfd_mach_ppc_403;
3842 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3843 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3844 }
3845
3846 static void init_proc_440x5 (CPUPPCState *env)
3847 {
3848 /* Time base */
3849 gen_tbl(env);
3850 gen_spr_BookE(env, 0x000000000000FFFFULL);
3851 gen_spr_440(env);
3852 gen_spr_usprgh(env);
3853 /* Processor identification */
3854 spr_register(env, SPR_BOOKE_PIR, "PIR",
3855 SPR_NOACCESS, SPR_NOACCESS,
3856 &spr_read_generic, &spr_write_pir,
3857 0x00000000);
3858 /* XXX : not implemented */
3859 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3860 SPR_NOACCESS, SPR_NOACCESS,
3861 &spr_read_generic, &spr_write_generic,
3862 0x00000000);
3863 /* XXX : not implemented */
3864 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3865 SPR_NOACCESS, SPR_NOACCESS,
3866 &spr_read_generic, &spr_write_generic,
3867 0x00000000);
3868 /* XXX : not implemented */
3869 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3870 SPR_NOACCESS, SPR_NOACCESS,
3871 &spr_read_generic, &spr_write_generic,
3872 0x00000000);
3873 /* XXX : not implemented */
3874 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3875 SPR_NOACCESS, SPR_NOACCESS,
3876 &spr_read_generic, &spr_write_generic,
3877 0x00000000);
3878 /* XXX : not implemented */
3879 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3880 SPR_NOACCESS, SPR_NOACCESS,
3881 &spr_read_generic, &spr_write_generic,
3882 0x00000000);
3883 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3884 SPR_NOACCESS, SPR_NOACCESS,
3885 &spr_read_generic, &spr_write_generic,
3886 0x00000000);
3887 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3888 SPR_NOACCESS, SPR_NOACCESS,
3889 &spr_read_generic, &spr_write_generic,
3890 0x00000000);
3891 /* XXX : not implemented */
3892 spr_register(env, SPR_440_CCR1, "CCR1",
3893 SPR_NOACCESS, SPR_NOACCESS,
3894 &spr_read_generic, &spr_write_generic,
3895 0x00000000);
3896 /* Memory management */
3897 #if !defined(CONFIG_USER_ONLY)
3898 env->nb_tlb = 64;
3899 env->nb_ways = 1;
3900 env->id_tlbs = 0;
3901 env->tlb_type = TLB_EMB;
3902 #endif
3903 init_excp_BookE(env);
3904 env->dcache_line_size = 32;
3905 env->icache_line_size = 32;
3906 ppc40x_irq_init(env);
3907
3908 SET_FIT_PERIOD(12, 16, 20, 24);
3909 SET_WDT_PERIOD(20, 24, 28, 32);
3910 }
3911
3912 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3913 {
3914 DeviceClass *dc = DEVICE_CLASS(oc);
3915 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3916
3917 dc->desc = "PowerPC 440x5";
3918 pcc->init_proc = init_proc_440x5;
3919 pcc->check_pow = check_pow_nocheck;
3920 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3921 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3922 PPC_CACHE | PPC_CACHE_ICBI |
3923 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3924 PPC_MEM_TLBSYNC | PPC_MFTB |
3925 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3926 PPC_440_SPEC;
3927 pcc->insns_flags2 = PPC_NONE;
3928 pcc->msr_mask = 0x000000000006FF30ULL;
3929 pcc->mmu_model = POWERPC_MMU_BOOKE;
3930 pcc->excp_model = POWERPC_EXCP_BOOKE;
3931 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3932 pcc->bfd_mach = bfd_mach_ppc_403;
3933 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3934 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3935 }
3936
3937 static void init_proc_460 (CPUPPCState *env)
3938 {
3939 /* Time base */
3940 gen_tbl(env);
3941 gen_spr_BookE(env, 0x000000000000FFFFULL);
3942 gen_spr_440(env);
3943 gen_spr_usprgh(env);
3944 /* Processor identification */
3945 spr_register(env, SPR_BOOKE_PIR, "PIR",
3946 SPR_NOACCESS, SPR_NOACCESS,
3947 &spr_read_generic, &spr_write_pir,
3948 0x00000000);
3949 /* XXX : not implemented */
3950 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3951 SPR_NOACCESS, SPR_NOACCESS,
3952 &spr_read_generic, &spr_write_generic,
3953 0x00000000);
3954 /* XXX : not implemented */
3955 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3956 SPR_NOACCESS, SPR_NOACCESS,
3957 &spr_read_generic, &spr_write_generic,
3958 0x00000000);
3959 /* XXX : not implemented */
3960 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3961 SPR_NOACCESS, SPR_NOACCESS,
3962 &spr_read_generic, &spr_write_generic,
3963 0x00000000);
3964 /* XXX : not implemented */
3965 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3966 SPR_NOACCESS, SPR_NOACCESS,
3967 &spr_read_generic, &spr_write_generic,
3968 0x00000000);
3969 /* XXX : not implemented */
3970 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3971 SPR_NOACCESS, SPR_NOACCESS,
3972 &spr_read_generic, &spr_write_generic,
3973 0x00000000);
3974 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3975 SPR_NOACCESS, SPR_NOACCESS,
3976 &spr_read_generic, &spr_write_generic,
3977 0x00000000);
3978 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3979 SPR_NOACCESS, SPR_NOACCESS,
3980 &spr_read_generic, &spr_write_generic,
3981 0x00000000);
3982 /* XXX : not implemented */
3983 spr_register(env, SPR_440_CCR1, "CCR1",
3984 SPR_NOACCESS, SPR_NOACCESS,
3985 &spr_read_generic, &spr_write_generic,
3986 0x00000000);
3987 /* XXX : not implemented */
3988 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3989 &spr_read_generic, &spr_write_generic,
3990 &spr_read_generic, &spr_write_generic,
3991 0x00000000);
3992 /* Memory management */
3993 #if !defined(CONFIG_USER_ONLY)
3994 env->nb_tlb = 64;
3995 env->nb_ways = 1;
3996 env->id_tlbs = 0;
3997 env->tlb_type = TLB_EMB;
3998 #endif
3999 init_excp_BookE(env);
4000 env->dcache_line_size = 32;
4001 env->icache_line_size = 32;
4002 /* XXX: TODO: allocate internal IRQ controller */
4003
4004 SET_FIT_PERIOD(12, 16, 20, 24);
4005 SET_WDT_PERIOD(20, 24, 28, 32);
4006 }
4007
4008 POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
4009 {
4010 DeviceClass *dc = DEVICE_CLASS(oc);
4011 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4012
4013 dc->desc = "PowerPC 460 (guessed)";
4014 pcc->init_proc = init_proc_460;
4015 pcc->check_pow = check_pow_nocheck;
4016 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4017 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4018 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
4019 PPC_CACHE | PPC_CACHE_ICBI |
4020 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4021 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4022 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4023 PPC_440_SPEC;
4024 pcc->insns_flags2 = PPC_NONE;
4025 pcc->msr_mask = 0x000000000006FF30ULL;
4026 pcc->mmu_model = POWERPC_MMU_BOOKE;
4027 pcc->excp_model = POWERPC_EXCP_BOOKE;
4028 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4029 pcc->bfd_mach = bfd_mach_ppc_403;
4030 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4031 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4032 }
4033
4034 static void init_proc_460F (CPUPPCState *env)
4035 {
4036 /* Time base */
4037 gen_tbl(env);
4038 gen_spr_BookE(env, 0x000000000000FFFFULL);
4039 gen_spr_440(env);
4040 gen_spr_usprgh(env);
4041 /* Processor identification */
4042 spr_register(env, SPR_BOOKE_PIR, "PIR",
4043 SPR_NOACCESS, SPR_NOACCESS,
4044 &spr_read_generic, &spr_write_pir,
4045 0x00000000);
4046 /* XXX : not implemented */
4047 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4048 SPR_NOACCESS, SPR_NOACCESS,
4049 &spr_read_generic, &spr_write_generic,
4050 0x00000000);
4051 /* XXX : not implemented */
4052 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4053 SPR_NOACCESS, SPR_NOACCESS,
4054 &spr_read_generic, &spr_write_generic,
4055 0x00000000);
4056 /* XXX : not implemented */
4057 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4058 SPR_NOACCESS, SPR_NOACCESS,
4059 &spr_read_generic, &spr_write_generic,
4060 0x00000000);
4061 /* XXX : not implemented */
4062 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4063 SPR_NOACCESS, SPR_NOACCESS,
4064 &spr_read_generic, &spr_write_generic,
4065 0x00000000);
4066 /* XXX : not implemented */
4067 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4068 SPR_NOACCESS, SPR_NOACCESS,
4069 &spr_read_generic, &spr_write_generic,
4070 0x00000000);
4071 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4072 SPR_NOACCESS, SPR_NOACCESS,
4073 &spr_read_generic, &spr_write_generic,
4074 0x00000000);
4075 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4076 SPR_NOACCESS, SPR_NOACCESS,
4077 &spr_read_generic, &spr_write_generic,
4078 0x00000000);
4079 /* XXX : not implemented */
4080 spr_register(env, SPR_440_CCR1, "CCR1",
4081 SPR_NOACCESS, SPR_NOACCESS,
4082 &spr_read_generic, &spr_write_generic,
4083 0x00000000);
4084 /* XXX : not implemented */
4085 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4086 &spr_read_generic, &spr_write_generic,
4087 &spr_read_generic, &spr_write_generic,
4088 0x00000000);
4089 /* Memory management */
4090 #if !defined(CONFIG_USER_ONLY)
4091 env->nb_tlb = 64;
4092 env->nb_ways = 1;
4093 env->id_tlbs = 0;
4094 env->tlb_type = TLB_EMB;
4095 #endif
4096 init_excp_BookE(env);
4097 env->dcache_line_size = 32;
4098 env->icache_line_size = 32;
4099 /* XXX: TODO: allocate internal IRQ controller */
4100
4101 SET_FIT_PERIOD(12, 16, 20, 24);
4102 SET_WDT_PERIOD(20, 24, 28, 32);
4103 }
4104
4105 POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
4106 {
4107 DeviceClass *dc = DEVICE_CLASS(oc);
4108 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4109
4110 dc->desc = "PowerPC 460F (guessed)";
4111 pcc->init_proc = init_proc_460F;
4112 pcc->check_pow = check_pow_nocheck;
4113 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4114 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
4115 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4116 PPC_FLOAT_STFIWX | PPC_MFTB |
4117 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4118 PPC_WRTEE | PPC_MFAPIDI |
4119 PPC_CACHE | PPC_CACHE_ICBI |
4120 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4121 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4122 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4123 PPC_440_SPEC;
4124 pcc->insns_flags2 = PPC_NONE;
4125 pcc->msr_mask = 0x000000000006FF30ULL;
4126 pcc->mmu_model = POWERPC_MMU_BOOKE;
4127 pcc->excp_model = POWERPC_EXCP_BOOKE;
4128 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4129 pcc->bfd_mach = bfd_mach_ppc_403;
4130 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4131 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4132 }
4133
4134 static void init_proc_MPC5xx (CPUPPCState *env)
4135 {
4136 /* Time base */
4137 gen_tbl(env);
4138 gen_spr_5xx_8xx(env);
4139 gen_spr_5xx(env);
4140 init_excp_MPC5xx(env);
4141 env->dcache_line_size = 32;
4142 env->icache_line_size = 32;
4143 /* XXX: TODO: allocate internal IRQ controller */
4144 }
4145
4146 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4147 {
4148 DeviceClass *dc = DEVICE_CLASS(oc);
4149 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4150
4151 dc->desc = "Freescale 5xx cores (aka RCPU)";
4152 pcc->init_proc = init_proc_MPC5xx;
4153 pcc->check_pow = check_pow_none;
4154 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4155 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4156 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4157 PPC_MFTB;
4158 pcc->insns_flags2 = PPC_NONE;
4159 pcc->msr_mask = 0x000000000001FF43ULL;
4160 pcc->mmu_model = POWERPC_MMU_REAL;
4161 pcc->excp_model = POWERPC_EXCP_603;
4162 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4163 pcc->bfd_mach = bfd_mach_ppc_505;
4164 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4165 POWERPC_FLAG_BUS_CLK;
4166 }
4167
4168 static void init_proc_MPC8xx (CPUPPCState *env)
4169 {
4170 /* Time base */
4171 gen_tbl(env);
4172 gen_spr_5xx_8xx(env);
4173 gen_spr_8xx(env);
4174 init_excp_MPC8xx(env);
4175 env->dcache_line_size = 32;
4176 env->icache_line_size = 32;
4177 /* XXX: TODO: allocate internal IRQ controller */
4178 }
4179
4180 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4181 {
4182 DeviceClass *dc = DEVICE_CLASS(oc);
4183 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4184
4185 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4186 pcc->init_proc = init_proc_MPC8xx;
4187 pcc->check_pow = check_pow_none;
4188 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4189 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4190 PPC_CACHE_ICBI | PPC_MFTB;
4191 pcc->insns_flags2 = PPC_NONE;
4192 pcc->msr_mask = 0x000000000001F673ULL;
4193 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4194 pcc->excp_model = POWERPC_EXCP_603;
4195 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4196 pcc->bfd_mach = bfd_mach_ppc_860;
4197 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4198 POWERPC_FLAG_BUS_CLK;
4199 }
4200
4201 /* Freescale 82xx cores (aka PowerQUICC-II) */
4202
4203 static void init_proc_G2 (CPUPPCState *env)
4204 {
4205 gen_spr_ne_601(env);
4206 gen_spr_G2_755(env);
4207 gen_spr_G2(env);
4208 /* Time base */
4209 gen_tbl(env);
4210 /* External access control */
4211 /* XXX : not implemented */
4212 spr_register(env, SPR_EAR, "EAR",
4213 SPR_NOACCESS, SPR_NOACCESS,
4214 &spr_read_generic, &spr_write_generic,
4215 0x00000000);
4216 /* Hardware implementation register */
4217 /* XXX : not implemented */
4218 spr_register(env, SPR_HID0, "HID0",
4219 SPR_NOACCESS, SPR_NOACCESS,
4220 &spr_read_generic, &spr_write_generic,
4221 0x00000000);
4222 /* XXX : not implemented */
4223 spr_register(env, SPR_HID1, "HID1",
4224 SPR_NOACCESS, SPR_NOACCESS,
4225 &spr_read_generic, &spr_write_generic,
4226 0x00000000);
4227 /* XXX : not implemented */
4228 spr_register(env, SPR_HID2, "HID2",
4229 SPR_NOACCESS, SPR_NOACCESS,
4230 &spr_read_generic, &spr_write_generic,
4231 0x00000000);
4232 /* Memory management */
4233 gen_low_BATs(env);
4234 gen_high_BATs(env);
4235 gen_6xx_7xx_soft_tlb(env, 64, 2);
4236 init_excp_G2(env);
4237 env->dcache_line_size = 32;
4238 env->icache_line_size = 32;
4239 /* Allocate hardware IRQ controller */
4240 ppc6xx_irq_init(env);
4241 }
4242
4243 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4244 {
4245 DeviceClass *dc = DEVICE_CLASS(oc);
4246 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4247
4248 dc->desc = "PowerPC G2";
4249 pcc->init_proc = init_proc_G2;
4250 pcc->check_pow = check_pow_hid0;
4251 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4252 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4253 PPC_FLOAT_STFIWX |
4254 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4255 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4256 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4257 PPC_SEGMENT | PPC_EXTERN;
4258 pcc->insns_flags2 = PPC_NONE;
4259 pcc->msr_mask = 0x000000000006FFF2ULL;
4260 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4261 pcc->excp_model = POWERPC_EXCP_G2;
4262 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4263 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4264 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4265 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4266 }
4267
4268 static void init_proc_G2LE (CPUPPCState *env)
4269 {
4270 gen_spr_ne_601(env);
4271 gen_spr_G2_755(env);
4272 gen_spr_G2(env);
4273 /* Time base */
4274 gen_tbl(env);
4275 /* External access control */
4276 /* XXX : not implemented */
4277 spr_register(env, SPR_EAR, "EAR",
4278 SPR_NOACCESS, SPR_NOACCESS,
4279 &spr_read_generic, &spr_write_generic,
4280 0x00000000);
4281 /* Hardware implementation register */
4282 /* XXX : not implemented */
4283 spr_register(env, SPR_HID0, "HID0",
4284 SPR_NOACCESS, SPR_NOACCESS,
4285 &spr_read_generic, &spr_write_generic,
4286 0x00000000);
4287 /* XXX : not implemented */
4288 spr_register(env, SPR_HID1, "HID1",
4289 SPR_NOACCESS, SPR_NOACCESS,
4290 &spr_read_generic, &spr_write_generic,
4291 0x00000000);
4292 /* XXX : not implemented */
4293 spr_register(env, SPR_HID2, "HID2",
4294 SPR_NOACCESS, SPR_NOACCESS,
4295 &spr_read_generic, &spr_write_generic,
4296 0x00000000);
4297 /* Memory management */
4298 gen_low_BATs(env);
4299 gen_high_BATs(env);
4300 gen_6xx_7xx_soft_tlb(env, 64, 2);
4301 init_excp_G2(env);
4302 env->dcache_line_size = 32;
4303 env->icache_line_size = 32;
4304 /* Allocate hardware IRQ controller */
4305 ppc6xx_irq_init(env);
4306 }
4307
4308 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4309 {
4310 DeviceClass *dc = DEVICE_CLASS(oc);
4311 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4312
4313 dc->desc = "PowerPC G2LE";
4314 pcc->init_proc = init_proc_G2LE;
4315 pcc->check_pow = check_pow_hid0;
4316 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4317 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4318 PPC_FLOAT_STFIWX |
4319 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4320 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4321 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4322 PPC_SEGMENT | PPC_EXTERN;
4323 pcc->insns_flags2 = PPC_NONE;
4324 pcc->msr_mask = 0x000000000007FFF3ULL;
4325 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4326 pcc->excp_model = POWERPC_EXCP_G2;
4327 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4328 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4329 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4330 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4331 }
4332
4333 static void init_proc_e200 (CPUPPCState *env)
4334 {
4335 /* Time base */
4336 gen_tbl(env);
4337 gen_spr_BookE(env, 0x000000070000FFFFULL);
4338 /* XXX : not implemented */
4339 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4340 &spr_read_spefscr, &spr_write_spefscr,
4341 &spr_read_spefscr, &spr_write_spefscr,
4342 0x00000000);
4343 /* Memory management */
4344 gen_spr_BookE206(env, 0x0000005D, NULL);
4345 /* XXX : not implemented */
4346 spr_register(env, SPR_HID0, "HID0",
4347 SPR_NOACCESS, SPR_NOACCESS,
4348 &spr_read_generic, &spr_write_generic,
4349 0x00000000);
4350 /* XXX : not implemented */
4351 spr_register(env, SPR_HID1, "HID1",
4352 SPR_NOACCESS, SPR_NOACCESS,
4353 &spr_read_generic, &spr_write_generic,
4354 0x00000000);
4355 /* XXX : not implemented */
4356 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4357 SPR_NOACCESS, SPR_NOACCESS,
4358 &spr_read_generic, &spr_write_generic,
4359 0x00000000);
4360 /* XXX : not implemented */
4361 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4362 SPR_NOACCESS, SPR_NOACCESS,
4363 &spr_read_generic, &spr_write_generic,
4364 0x00000000);
4365 /* XXX : not implemented */
4366 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4367 SPR_NOACCESS, SPR_NOACCESS,
4368 &spr_read_generic, &spr_write_generic,
4369 0x00000000);
4370 /* XXX : not implemented */
4371 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4372 SPR_NOACCESS, SPR_NOACCESS,
4373 &spr_read_generic, &spr_write_generic,
4374 0x00000000);
4375 /* XXX : not implemented */
4376 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4377 SPR_NOACCESS, SPR_NOACCESS,
4378 &spr_read_generic, &spr_write_generic,
4379 0x00000000);
4380 /* XXX : not implemented */
4381 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4382 SPR_NOACCESS, SPR_NOACCESS,
4383 &spr_read_generic, &spr_write_generic,
4384 0x00000000);
4385 /* XXX : not implemented */
4386 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4387 SPR_NOACCESS, SPR_NOACCESS,
4388 &spr_read_generic, &spr_write_generic,
4389 0x00000000);
4390 /* XXX : not implemented */
4391 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4392 SPR_NOACCESS, SPR_NOACCESS,
4393 &spr_read_generic, &spr_write_generic,
4394 0x00000000);
4395 /* XXX : not implemented */
4396 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4397 SPR_NOACCESS, SPR_NOACCESS,
4398 &spr_read_generic, &spr_write_generic,
4399 0x00000000);
4400 /* XXX : not implemented */
4401 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4402 SPR_NOACCESS, SPR_NOACCESS,
4403 &spr_read_generic, &spr_write_generic,
4404 0x00000000);
4405 /* XXX : not implemented */
4406 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4407 SPR_NOACCESS, SPR_NOACCESS,
4408 &spr_read_generic, &spr_write_generic,
4409 0x00000000);
4410 /* XXX : not implemented */
4411 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4412 SPR_NOACCESS, SPR_NOACCESS,
4413 &spr_read_generic, &spr_write_generic,
4414 0x00000000);
4415 /* XXX : not implemented */
4416 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4417 SPR_NOACCESS, SPR_NOACCESS,
4418 &spr_read_generic, &spr_write_generic,
4419 0x00000000); /* TOFIX */
4420 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4421 SPR_NOACCESS, SPR_NOACCESS,
4422 &spr_read_generic, &spr_write_generic,
4423 0x00000000);
4424 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4425 SPR_NOACCESS, SPR_NOACCESS,
4426 &spr_read_generic, &spr_write_generic,
4427 0x00000000);
4428 #if !defined(CONFIG_USER_ONLY)
4429 env->nb_tlb = 64;
4430 env->nb_ways = 1;
4431 env->id_tlbs = 0;
4432 env->tlb_type = TLB_EMB;
4433 #endif
4434 init_excp_e200(env, 0xFFFF0000UL);
4435 env->dcache_line_size = 32;
4436 env->icache_line_size = 32;
4437 /* XXX: TODO: allocate internal IRQ controller */
4438 }
4439
4440 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4441 {
4442 DeviceClass *dc = DEVICE_CLASS(oc);
4443 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4444
4445 dc->desc = "e200 core";
4446 pcc->init_proc = init_proc_e200;
4447 pcc->check_pow = check_pow_hid0;
4448 /* XXX: unimplemented instructions:
4449 * dcblc
4450 * dcbtlst
4451 * dcbtstls
4452 * icblc
4453 * icbtls
4454 * tlbivax
4455 * all SPE multiply-accumulate instructions
4456 */
4457 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4458 PPC_SPE | PPC_SPE_SINGLE |
4459 PPC_WRTEE | PPC_RFDI |
4460 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4461 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4462 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4463 PPC_BOOKE;
4464 pcc->insns_flags2 = PPC_NONE;
4465 pcc->msr_mask = 0x000000000606FF30ULL;
4466 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4467 pcc->excp_model = POWERPC_EXCP_BOOKE;
4468 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4469 pcc->bfd_mach = bfd_mach_ppc_860;
4470 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4471 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4472 POWERPC_FLAG_BUS_CLK;
4473 }
4474
4475 static void init_proc_e300 (CPUPPCState *env)
4476 {
4477 gen_spr_ne_601(env);
4478 gen_spr_603(env);
4479 /* Time base */
4480 gen_tbl(env);
4481 /* hardware implementation registers */
4482 /* XXX : not implemented */
4483 spr_register(env, SPR_HID0, "HID0",
4484 SPR_NOACCESS, SPR_NOACCESS,
4485 &spr_read_generic, &spr_write_generic,
4486 0x00000000);
4487 /* XXX : not implemented */
4488 spr_register(env, SPR_HID1, "HID1",
4489 SPR_NOACCESS, SPR_NOACCESS,
4490 &spr_read_generic, &spr_write_generic,
4491 0x00000000);
4492 /* XXX : not implemented */
4493 spr_register(env, SPR_HID2, "HID2",
4494 SPR_NOACCESS, SPR_NOACCESS,
4495 &spr_read_generic, &spr_write_generic,
4496 0x00000000);
4497 /* Memory management */
4498 gen_low_BATs(env);
4499 gen_high_BATs(env);
4500 gen_6xx_7xx_soft_tlb(env, 64, 2);
4501 init_excp_603(env);
4502 env->dcache_line_size = 32;
4503 env->icache_line_size = 32;
4504 /* Allocate hardware IRQ controller */
4505 ppc6xx_irq_init(env);
4506 }
4507
4508 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4509 {
4510 DeviceClass *dc = DEVICE_CLASS(oc);
4511 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4512
4513 dc->desc = "e300 core";
4514 pcc->init_proc = init_proc_e300;
4515 pcc->check_pow = check_pow_hid0;
4516 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4517 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4518 PPC_FLOAT_STFIWX |
4519 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4520 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4521 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4522 PPC_SEGMENT | PPC_EXTERN;
4523 pcc->insns_flags2 = PPC_NONE;
4524 pcc->msr_mask = 0x000000000007FFF3ULL;
4525 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4526 pcc->excp_model = POWERPC_EXCP_603;
4527 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4528 pcc->bfd_mach = bfd_mach_ppc_603;
4529 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4530 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4531 }
4532
4533 #if !defined(CONFIG_USER_ONLY)
4534 static void spr_write_mas73(void *opaque, int sprn, int gprn)
4535 {
4536 TCGv val = tcg_temp_new();
4537 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4538 gen_store_spr(SPR_BOOKE_MAS3, val);
4539 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4540 gen_store_spr(SPR_BOOKE_MAS7, val);
4541 tcg_temp_free(val);
4542 }
4543
4544 static void spr_read_mas73(void *opaque, int gprn, int sprn)
4545 {
4546 TCGv mas7 = tcg_temp_new();
4547 TCGv mas3 = tcg_temp_new();
4548 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4549 tcg_gen_shli_tl(mas7, mas7, 32);
4550 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4551 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4552 tcg_temp_free(mas3);
4553 tcg_temp_free(mas7);
4554 }
4555
4556 #endif
4557
4558 enum fsl_e500_version {
4559 fsl_e500v1,
4560 fsl_e500v2,
4561 fsl_e500mc,
4562 fsl_e5500,
4563 };
4564
4565 static void init_proc_e500 (CPUPPCState *env, int version)
4566 {
4567 uint32_t tlbncfg[2];
4568 uint64_t ivor_mask;
4569 uint64_t ivpr_mask = 0xFFFF0000ULL;
4570 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4571 | 0x0020; /* 32 kb */
4572 #if !defined(CONFIG_USER_ONLY)
4573 int i;
4574 #endif
4575
4576 /* Time base */
4577 gen_tbl(env);
4578 /*
4579 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4580 * complain when accessing them.
4581 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4582 */
4583 switch (version) {
4584 case fsl_e500v1:
4585 case fsl_e500v2:
4586 default:
4587 ivor_mask = 0x0000000F0000FFFFULL;
4588 break;
4589 case fsl_e500mc:
4590 case fsl_e5500:
4591 ivor_mask = 0x000003FE0000FFFFULL;
4592 break;
4593 }
4594 gen_spr_BookE(env, ivor_mask);
4595 /* Processor identification */
4596 spr_register(env, SPR_BOOKE_PIR, "PIR",
4597 SPR_NOACCESS, SPR_NOACCESS,
4598 &spr_read_generic, &spr_write_pir,
4599 0x00000000);
4600 /* XXX : not implemented */
4601 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4602 &spr_read_spefscr, &spr_write_spefscr,
4603 &spr_read_spefscr, &spr_write_spefscr,
4604 0x00000000);
4605 #if !defined(CONFIG_USER_ONLY)
4606 /* Memory management */
4607 env->nb_pids = 3;
4608 env->nb_ways = 2;
4609 env->id_tlbs = 0;
4610 switch (version) {
4611 case fsl_e500v1:
4612 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4613 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4614 break;
4615 case fsl_e500v2:
4616 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4617 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4618 break;
4619 case fsl_e500mc:
4620 case fsl_e5500:
4621 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4622 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4623 break;
4624 default:
4625 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4626 }
4627 #endif
4628 /* Cache sizes */
4629 switch (version) {
4630 case fsl_e500v1:
4631 case fsl_e500v2:
4632 env->dcache_line_size = 32;
4633 env->icache_line_size = 32;
4634 break;
4635 case fsl_e500mc:
4636 case fsl_e5500:
4637 env->dcache_line_size = 64;
4638 env->icache_line_size = 64;
4639 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4640 break;
4641 default:
4642 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4643 }
4644 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4645 /* XXX : not implemented */
4646 spr_register(env, SPR_HID0, "HID0",
4647 SPR_NOACCESS, SPR_NOACCESS,
4648 &spr_read_generic, &spr_write_generic,
4649 0x00000000);
4650 /* XXX : not implemented */
4651 spr_register(env, SPR_HID1, "HID1",
4652 SPR_NOACCESS, SPR_NOACCESS,
4653 &spr_read_generic, &spr_write_generic,
4654 0x00000000);
4655 /* XXX : not implemented */
4656 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4657 SPR_NOACCESS, SPR_NOACCESS,
4658 &spr_read_generic, &spr_write_generic,
4659 0x00000000);
4660 /* XXX : not implemented */
4661 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4662 SPR_NOACCESS, SPR_NOACCESS,
4663 &spr_read_generic, &spr_write_generic,
4664 0x00000000);
4665 /* XXX : not implemented */
4666 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4667 SPR_NOACCESS, SPR_NOACCESS,
4668 &spr_read_generic, &spr_write_generic,
4669 0x00000000);
4670 /* XXX : not implemented */
4671 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4672 SPR_NOACCESS, SPR_NOACCESS,
4673 &spr_read_generic, &spr_write_generic,
4674 0x00000000);
4675 /* XXX : not implemented */
4676 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4677 SPR_NOACCESS, SPR_NOACCESS,
4678 &spr_read_generic, &spr_write_generic,
4679 0x00000000);
4680 /* XXX : not implemented */
4681 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4682 SPR_NOACCESS, SPR_NOACCESS,
4683 &spr_read_generic, &spr_write_generic,
4684 0x00000000);
4685 /* XXX : not implemented */
4686 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4687 SPR_NOACCESS, SPR_NOACCESS,
4688 &spr_read_generic, &spr_write_generic,
4689 l1cfg0);
4690 /* XXX : not implemented */
4691 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4692 SPR_NOACCESS, SPR_NOACCESS,
4693 &spr_read_generic, &spr_write_e500_l1csr0,
4694 0x00000000);
4695 /* XXX : not implemented */
4696 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4697 SPR_NOACCESS, SPR_NOACCESS,
4698 &spr_read_generic, &spr_write_generic,
4699 0x00000000);
4700 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4701 SPR_NOACCESS, SPR_NOACCESS,
4702 &spr_read_generic, &spr_write_generic,
4703 0x00000000);
4704 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4705 SPR_NOACCESS, SPR_NOACCESS,
4706 &spr_read_generic, &spr_write_generic,
4707 0x00000000);
4708 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4709 SPR_NOACCESS, SPR_NOACCESS,
4710 &spr_read_generic, &spr_write_booke206_mmucsr0,
4711 0x00000000);
4712 spr_register(env, SPR_BOOKE_EPR, "EPR",
4713 SPR_NOACCESS, SPR_NOACCESS,
4714 &spr_read_generic, SPR_NOACCESS,
4715 0x00000000);
4716 /* XXX better abstract into Emb.xxx features */
4717 if (version == fsl_e5500) {
4718 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4719 SPR_NOACCESS, SPR_NOACCESS,
4720 &spr_read_generic, &spr_write_generic,
4721 0x00000000);
4722 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4723 SPR_NOACCESS, SPR_NOACCESS,
4724 &spr_read_mas73, &spr_write_mas73,
4725 0x00000000);
4726 ivpr_mask = (target_ulong)~0xFFFFULL;
4727 }
4728
4729 #if !defined(CONFIG_USER_ONLY)
4730 env->nb_tlb = 0;
4731 env->tlb_type = TLB_MAS;
4732 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4733 env->nb_tlb += booke206_tlb_size(env, i);
4734 }
4735 #endif
4736
4737 init_excp_e200(env, ivpr_mask);
4738 /* Allocate hardware IRQ controller */
4739 ppce500_irq_init(env);
4740 }
4741
4742 static void init_proc_e500v1(CPUPPCState *env)
4743 {
4744 init_proc_e500(env, fsl_e500v1);
4745 }
4746
4747 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4748 {
4749 DeviceClass *dc = DEVICE_CLASS(oc);
4750 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4751
4752 dc->desc = "e500v1 core";
4753 pcc->init_proc = init_proc_e500v1;
4754 pcc->check_pow = check_pow_hid0;
4755 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4756 PPC_SPE | PPC_SPE_SINGLE |
4757 PPC_WRTEE | PPC_RFDI |
4758 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4759 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4760 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4761 pcc->insns_flags2 = PPC2_BOOKE206;
4762 pcc->msr_mask = 0x000000000606FF30ULL;
4763 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4764 pcc->excp_model = POWERPC_EXCP_BOOKE;
4765 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4766 pcc->bfd_mach = bfd_mach_ppc_860;
4767 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4768 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4769 POWERPC_FLAG_BUS_CLK;
4770 }
4771
4772 static void init_proc_e500v2(CPUPPCState *env)
4773 {
4774 init_proc_e500(env, fsl_e500v2);
4775 }
4776
4777 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4778 {
4779 DeviceClass *dc = DEVICE_CLASS(oc);
4780 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4781
4782 dc->desc = "e500v2 core";
4783 pcc->init_proc = init_proc_e500v2;
4784 pcc->check_pow = check_pow_hid0;
4785 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4786 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4787 PPC_WRTEE | PPC_RFDI |
4788 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4789 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4790 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4791 pcc->insns_flags2 = PPC2_BOOKE206;
4792 pcc->msr_mask = 0x000000000606FF30ULL;
4793 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4794 pcc->excp_model = POWERPC_EXCP_BOOKE;
4795 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4796 pcc->bfd_mach = bfd_mach_ppc_860;
4797 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4798 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4799 POWERPC_FLAG_BUS_CLK;
4800 }
4801
4802 static void init_proc_e500mc(CPUPPCState *env)
4803 {
4804 init_proc_e500(env, fsl_e500mc);
4805 }
4806
4807 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4808 {
4809 DeviceClass *dc = DEVICE_CLASS(oc);
4810 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4811
4812 dc->desc = "e500mc core";
4813 pcc->init_proc = init_proc_e500mc;
4814 pcc->check_pow = check_pow_none;
4815 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4816 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4817 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4818 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4819 PPC_FLOAT | PPC_FLOAT_FRES |
4820 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4821 PPC_FLOAT_STFIWX | PPC_WAIT |
4822 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4823 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4824 pcc->msr_mask = 0x000000001402FB36ULL;
4825 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4826 pcc->excp_model = POWERPC_EXCP_BOOKE;
4827 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4828 /* FIXME: figure out the correct flag for e500mc */
4829 pcc->bfd_mach = bfd_mach_ppc_e500;
4830 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4831 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4832 }
4833
4834 #ifdef TARGET_PPC64
4835 static void init_proc_e5500(CPUPPCState *env)
4836 {
4837 init_proc_e500(env, fsl_e5500);
4838 }
4839
4840 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
4841 {
4842 DeviceClass *dc = DEVICE_CLASS(oc);
4843 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4844
4845 dc->desc = "e5500 core";
4846 pcc->init_proc = init_proc_e5500;
4847 pcc->check_pow = check_pow_none;
4848 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4849 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4850 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4851 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4852 PPC_FLOAT | PPC_FLOAT_FRES |
4853 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4854 PPC_FLOAT_STFIWX | PPC_WAIT |
4855 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4856 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
4857 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4858 pcc->msr_mask = 0x000000009402FB36ULL;
4859 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4860 pcc->excp_model = POWERPC_EXCP_BOOKE;
4861 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4862 /* FIXME: figure out the correct flag for e5500 */
4863 pcc->bfd_mach = bfd_mach_ppc_e500;
4864 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4865 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4866 }
4867 #endif
4868
4869 /* Non-embedded PowerPC */
4870
4871 /* POWER : same as 601, without mfmsr, mfsr */
4872 POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
4873 {
4874 DeviceClass *dc = DEVICE_CLASS(oc);
4875 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4876
4877 dc->desc = "POWER";
4878 /* pcc->insns_flags = XXX_TODO; */
4879 /* POWER RSC (from RAD6000) */
4880 pcc->msr_mask = 0x00000000FEF0ULL;
4881 }
4882
4883 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4884
4885 static void init_proc_601 (CPUPPCState *env)
4886 {
4887 gen_spr_ne_601(env);
4888 gen_spr_601(env);
4889 /* Hardware implementation registers */
4890 /* XXX : not implemented */
4891 spr_register(env, SPR_HID0, "HID0",
4892 SPR_NOACCESS, SPR_NOACCESS,
4893 &spr_read_generic, &spr_write_hid0_601,
4894 0x80010080);
4895 /* XXX : not implemented */
4896 spr_register(env, SPR_HID1, "HID1",
4897 SPR_NOACCESS, SPR_NOACCESS,
4898 &spr_read_generic, &spr_write_generic,
4899 0x00000000);
4900 /* XXX : not implemented */
4901 spr_register(env, SPR_601_HID2, "HID2",
4902 SPR_NOACCESS, SPR_NOACCESS,
4903 &spr_read_generic, &spr_write_generic,
4904 0x00000000);
4905 /* XXX : not implemented */
4906 spr_register(env, SPR_601_HID5, "HID5",
4907 SPR_NOACCESS, SPR_NOACCESS,
4908 &spr_read_generic, &spr_write_generic,
4909 0x00000000);
4910 /* Memory management */
4911 init_excp_601(env);
4912 /* XXX: beware that dcache line size is 64
4913 * but dcbz uses 32 bytes "sectors"
4914 * XXX: this breaks clcs instruction !
4915 */
4916 env->dcache_line_size = 32;
4917 env->icache_line_size = 64;
4918 /* Allocate hardware IRQ controller */
4919 ppc6xx_irq_init(env);
4920 }
4921
4922 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
4923 {
4924 DeviceClass *dc = DEVICE_CLASS(oc);
4925 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4926
4927 dc->desc = "PowerPC 601";
4928 pcc->init_proc = init_proc_601;
4929 pcc->check_pow = check_pow_none;
4930 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4931 PPC_FLOAT |
4932 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4933 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4934 PPC_SEGMENT | PPC_EXTERN;
4935 pcc->insns_flags2 = PPC_NONE;
4936 pcc->msr_mask = 0x000000000000FD70ULL;
4937 pcc->mmu_model = POWERPC_MMU_601;
4938 pcc->excp_model = POWERPC_EXCP_601;
4939 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4940 pcc->bfd_mach = bfd_mach_ppc_601;
4941 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
4942 }
4943
4944 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4945
4946 static void init_proc_601v (CPUPPCState *env)
4947 {
4948 init_proc_601(env);
4949 /* XXX : not implemented */
4950 spr_register(env, SPR_601_HID15, "HID15",
4951 SPR_NOACCESS, SPR_NOACCESS,
4952 &spr_read_generic, &spr_write_generic,
4953 0x00000000);
4954 }
4955
4956 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
4957 {
4958 DeviceClass *dc = DEVICE_CLASS(oc);
4959 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4960
4961 dc->desc = "PowerPC 601v";
4962 pcc->init_proc = init_proc_601v;
4963 pcc->check_pow = check_pow_none;
4964 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4965 PPC_FLOAT |
4966 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4967 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4968 PPC_SEGMENT | PPC_EXTERN;
4969 pcc->insns_flags2 = PPC_NONE;
4970 pcc->msr_mask = 0x000000000000FD70ULL;
4971 pcc->mmu_model = POWERPC_MMU_601;
4972 pcc->excp_model = POWERPC_EXCP_601;
4973 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4974 pcc->bfd_mach = bfd_mach_ppc_601;
4975 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
4976 }
4977
4978 static void init_proc_602 (CPUPPCState *env)
4979 {
4980 gen_spr_ne_601(env);
4981 gen_spr_602(env);
4982 /* Time base */
4983 gen_tbl(env);
4984 /* hardware implementation registers */
4985 /* XXX : not implemented */
4986 spr_register(env, SPR_HID0, "HID0",
4987 SPR_NOACCESS, SPR_NOACCESS,
4988 &spr_read_generic, &spr_write_generic,
4989 0x00000000);
4990 /* XXX : not implemented */
4991 spr_register(env, SPR_HID1, "HID1",
4992 SPR_NOACCESS, SPR_NOACCESS,
4993 &spr_read_generic, &spr_write_generic,
4994 0x00000000);
4995 /* Memory management */
4996 gen_low_BATs(env);
4997 gen_6xx_7xx_soft_tlb(env, 64, 2);
4998 init_excp_602(env);
4999 env->dcache_line_size = 32;
5000 env->icache_line_size = 32;
5001 /* Allocate hardware IRQ controller */
5002 ppc6xx_irq_init(env);
5003 }
5004
5005 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
5006 {
5007 DeviceClass *dc = DEVICE_CLASS(oc);
5008 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5009
5010 dc->desc = "PowerPC 602";
5011 pcc->init_proc = init_proc_602;
5012 pcc->check_pow = check_pow_hid0;
5013 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5014 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5015 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5016 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5017 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5018 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
5019 PPC_SEGMENT | PPC_602_SPEC;
5020 pcc->insns_flags2 = PPC_NONE;
5021 pcc->msr_mask = 0x0000000000C7FF73ULL;
5022 /* XXX: 602 MMU is quite specific. Should add a special case */
5023 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5024 pcc->excp_model = POWERPC_EXCP_602;
5025 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5026 pcc->bfd_mach = bfd_mach_ppc_602;
5027 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5028 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5029 }
5030
5031 static void init_proc_603 (CPUPPCState *env)
5032 {
5033 gen_spr_ne_601(env);
5034 gen_spr_603(env);
5035 /* Time base */
5036 gen_tbl(env);
5037 /* hardware implementation registers */
5038 /* XXX : not implemented */
5039 spr_register(env, SPR_HID0, "HID0",
5040 SPR_NOACCESS, SPR_NOACCESS,
5041 &spr_read_generic, &spr_write_generic,
5042 0x00000000);
5043 /* XXX : not implemented */
5044 spr_register(env, SPR_HID1, "HID1",
5045 SPR_NOACCESS, SPR_NOACCESS,
5046 &spr_read_generic, &spr_write_generic,
5047 0x00000000);
5048 /* Memory management */
5049 gen_low_BATs(env);
5050 gen_6xx_7xx_soft_tlb(env, 64, 2);
5051 init_excp_603(env);
5052 env->dcache_line_size = 32;
5053 env->icache_line_size = 32;
5054 /* Allocate hardware IRQ controller */
5055 ppc6xx_irq_init(env);
5056 }
5057
5058 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
5059 {
5060 DeviceClass *dc = DEVICE_CLASS(oc);
5061 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5062
5063 dc->desc = "PowerPC 603";
5064 pcc->init_proc = init_proc_603;
5065 pcc->check_pow = check_pow_hid0;
5066 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5067 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5068 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5069 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5070 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5071 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5072 PPC_SEGMENT | PPC_EXTERN;
5073 pcc->insns_flags2 = PPC_NONE;
5074 pcc->msr_mask = 0x000000000007FF73ULL;
5075 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5076 pcc->excp_model = POWERPC_EXCP_603;
5077 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5078 pcc->bfd_mach = bfd_mach_ppc_603;
5079 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5080 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5081 }
5082
5083 static void init_proc_603E (CPUPPCState *env)
5084 {
5085 gen_spr_ne_601(env);
5086 gen_spr_603(env);
5087 /* Time base */
5088 gen_tbl(env);
5089 /* hardware implementation registers */
5090 /* XXX : not implemented */
5091 spr_register(env, SPR_HID0, "HID0",
5092 SPR_NOACCESS, SPR_NOACCESS,
5093 &spr_read_generic, &spr_write_generic,
5094 0x00000000);
5095 /* XXX : not implemented */
5096 spr_register(env, SPR_HID1, "HID1",
5097 SPR_NOACCESS, SPR_NOACCESS,
5098 &spr_read_generic, &spr_write_generic,
5099 0x00000000);
5100 /* XXX : not implemented */
5101 spr_register(env, SPR_IABR, "IABR",
5102 SPR_NOACCESS, SPR_NOACCESS,
5103 &spr_read_generic, &spr_write_generic,
5104 0x00000000);
5105 /* Memory management */
5106 gen_low_BATs(env);
5107 gen_6xx_7xx_soft_tlb(env, 64, 2);
5108 init_excp_603(env);
5109 env->dcache_line_size = 32;
5110 env->icache_line_size = 32;
5111 /* Allocate hardware IRQ controller */
5112 ppc6xx_irq_init(env);
5113 }
5114
5115 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
5116 {
5117 DeviceClass *dc = DEVICE_CLASS(oc);
5118 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5119
5120 dc->desc = "PowerPC 603e";
5121 pcc->init_proc = init_proc_603E;
5122 pcc->check_pow = check_pow_hid0;
5123 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5124 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5125 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5126 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5127 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5128 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5129 PPC_SEGMENT | PPC_EXTERN;
5130 pcc->insns_flags2 = PPC_NONE;
5131 pcc->msr_mask = 0x000000000007FF73ULL;
5132 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5133 pcc->excp_model = POWERPC_EXCP_603E;
5134 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5135 pcc->bfd_mach = bfd_mach_ppc_ec603e;
5136 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5137 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5138 }
5139
5140 static void init_proc_604 (CPUPPCState *env)
5141 {
5142 gen_spr_ne_601(env);
5143 gen_spr_604(env);
5144 /* Time base */
5145 gen_tbl(env);
5146 /* Hardware implementation registers */
5147 /* XXX : not implemented */
5148 spr_register(env, SPR_HID0, "HID0",
5149 SPR_NOACCESS, SPR_NOACCESS,
5150 &spr_read_generic, &spr_write_generic,
5151 0x00000000);
5152 /* Memory management */
5153 gen_low_BATs(env);
5154 init_excp_604(env);
5155 env->dcache_line_size = 32;
5156 env->icache_line_size = 32;
5157 /* Allocate hardware IRQ controller */
5158 ppc6xx_irq_init(env);
5159 }
5160
5161 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5162 {
5163 DeviceClass *dc = DEVICE_CLASS(oc);
5164 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5165
5166 dc->desc = "PowerPC 604";
5167 pcc->init_proc = init_proc_604;
5168 pcc->check_pow = check_pow_nocheck;
5169 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5170 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5171 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5172 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5173 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5174 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5175 PPC_SEGMENT | PPC_EXTERN;
5176 pcc->insns_flags2 = PPC_NONE;
5177 pcc->msr_mask = 0x000000000005FF77ULL;
5178 pcc->mmu_model = POWERPC_MMU_32B;
5179 pcc->excp_model = POWERPC_EXCP_604;
5180 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5181 pcc->bfd_mach = bfd_mach_ppc_604;
5182 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5183 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5184 }
5185
5186 static void init_proc_604E (CPUPPCState *env)
5187 {
5188 gen_spr_ne_601(env);
5189 gen_spr_604(env);
5190 /* XXX : not implemented */
5191 spr_register(env, SPR_MMCR1, "MMCR1",
5192 SPR_NOACCESS, SPR_NOACCESS,
5193 &spr_read_generic, &spr_write_generic,
5194 0x00000000);
5195 /* XXX : not implemented */
5196 spr_register(env, SPR_PMC3, "PMC3",
5197 SPR_NOACCESS, SPR_NOACCESS,
5198 &spr_read_generic, &spr_write_generic,
5199 0x00000000);
5200 /* XXX : not implemented */
5201 spr_register(env, SPR_PMC4, "PMC4",
5202 SPR_NOACCESS, SPR_NOACCESS,
5203 &spr_read_generic, &spr_write_generic,
5204 0x00000000);
5205 /* Time base */
5206 gen_tbl(env);
5207 /* Hardware implementation registers */
5208 /* XXX : not implemented */
5209 spr_register(env, SPR_HID0, "HID0",
5210 SPR_NOACCESS, SPR_NOACCESS,
5211 &spr_read_generic, &spr_write_generic,
5212 0x00000000);
5213 /* XXX : not implemented */
5214 spr_register(env, SPR_HID1, "HID1",
5215 SPR_NOACCESS, SPR_NOACCESS,
5216 &spr_read_generic, &spr_write_generic,
5217 0x00000000);
5218 /* Memory management */
5219 gen_low_BATs(env);
5220 init_excp_604(env);
5221 env->dcache_line_size = 32;
5222 env->icache_line_size = 32;
5223 /* Allocate hardware IRQ controller */
5224 ppc6xx_irq_init(env);
5225 }
5226
5227 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5228 {
5229 DeviceClass *dc = DEVICE_CLASS(oc);
5230 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5231
5232 dc->desc = "PowerPC 604E";
5233 pcc->init_proc = init_proc_604E;
5234 pcc->check_pow = check_pow_nocheck;
5235 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5236 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5237 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5238 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5239 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5240 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5241 PPC_SEGMENT | PPC_EXTERN;
5242 pcc->insns_flags2 = PPC_NONE;
5243 pcc->msr_mask = 0x000000000005FF77ULL;
5244 pcc->mmu_model = POWERPC_MMU_32B;
5245 pcc->excp_model = POWERPC_EXCP_604;
5246 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5247 pcc->bfd_mach = bfd_mach_ppc_604;
5248 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5249 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5250 }
5251
5252 static void init_proc_740 (CPUPPCState *env)
5253 {
5254 gen_spr_ne_601(env);
5255 gen_spr_7xx(env);
5256 /* Time base */
5257 gen_tbl(env);
5258 /* Thermal management */
5259 gen_spr_thrm(env);
5260 /* Hardware implementation registers */
5261 /* XXX : not implemented */
5262 spr_register(env, SPR_HID0, "HID0",
5263 SPR_NOACCESS, SPR_NOACCESS,
5264 &spr_read_generic, &spr_write_generic,
5265 0x00000000);
5266 /* XXX : not implemented */
5267 spr_register(env, SPR_HID1, "HID1",
5268 SPR_NOACCESS, SPR_NOACCESS,
5269 &spr_read_generic, &spr_write_generic,
5270 0x00000000);
5271 /* Memory management */
5272 gen_low_BATs(env);
5273 init_excp_7x0(env);
5274 env->dcache_line_size = 32;
5275 env->icache_line_size = 32;
5276 /* Allocate hardware IRQ controller */
5277 ppc6xx_irq_init(env);
5278 }
5279
5280 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5281 {
5282 DeviceClass *dc = DEVICE_CLASS(oc);
5283 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5284
5285 dc->desc = "PowerPC 740";
5286 pcc->init_proc = init_proc_740;
5287 pcc->check_pow = check_pow_hid0;
5288 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5289 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5290 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5291 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5292 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5293 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5294 PPC_SEGMENT | PPC_EXTERN;
5295 pcc->insns_flags2 = PPC_NONE;
5296 pcc->msr_mask = 0x000000000005FF77ULL;
5297 pcc->mmu_model = POWERPC_MMU_32B;
5298 pcc->excp_model = POWERPC_EXCP_7x0;
5299 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5300 pcc->bfd_mach = bfd_mach_ppc_750;
5301 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5302 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5303 }
5304
5305 static void init_proc_750 (CPUPPCState *env)
5306 {
5307 gen_spr_ne_601(env);
5308 gen_spr_7xx(env);
5309 /* XXX : not implemented */
5310 spr_register(env, SPR_L2CR, "L2CR",
5311 SPR_NOACCESS, SPR_NOACCESS,
5312 &spr_read_generic, &spr_write_generic,
5313 0x00000000);
5314 /* Time base */
5315 gen_tbl(env);
5316 /* Thermal management */
5317 gen_spr_thrm(env);
5318 /* Hardware implementation registers */
5319 /* XXX : not implemented */
5320 spr_register(env, SPR_HID0, "HID0",
5321 SPR_NOACCESS, SPR_NOACCESS,
5322 &spr_read_generic, &spr_write_generic,
5323 0x00000000);
5324 /* XXX : not implemented */
5325 spr_register(env, SPR_HID1, "HID1",
5326 SPR_NOACCESS, SPR_NOACCESS,
5327 &spr_read_generic, &spr_write_generic,
5328 0x00000000);
5329 /* Memory management */
5330 gen_low_BATs(env);
5331 /* XXX: high BATs are also present but are known to be bugged on
5332 * die version 1.x
5333 */
5334 init_excp_7x0(env);
5335 env->dcache_line_size = 32;
5336 env->icache_line_size = 32;
5337 /* Allocate hardware IRQ controller */
5338 ppc6xx_irq_init(env);
5339 }
5340
5341 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5342 {
5343 DeviceClass *dc = DEVICE_CLASS(oc);
5344 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5345
5346 dc->desc = "PowerPC 750";
5347 pcc->init_proc = init_proc_750;
5348 pcc->check_pow = check_pow_hid0;
5349 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5350 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5351 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5352 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5353 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5354 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5355 PPC_SEGMENT | PPC_EXTERN;
5356 pcc->insns_flags2 = PPC_NONE;
5357 pcc->msr_mask = 0x000000000005FF77ULL;
5358 pcc->mmu_model = POWERPC_MMU_32B;
5359 pcc->excp_model = POWERPC_EXCP_7x0;
5360 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5361 pcc->bfd_mach = bfd_mach_ppc_750;
5362 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5363 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5364 }
5365
5366 static void init_proc_750cl (CPUPPCState *env)
5367 {
5368 gen_spr_ne_601(env);
5369 gen_spr_7xx(env);
5370 /* XXX : not implemented */
5371 spr_register(env, SPR_L2CR, "L2CR",
5372 SPR_NOACCESS, SPR_NOACCESS,
5373 &spr_read_generic, &spr_write_generic,
5374 0x00000000);
5375 /* Time base */
5376 gen_tbl(env);
5377 /* Thermal management */
5378 /* Those registers are fake on 750CL */
5379 spr_register(env, SPR_THRM1, "THRM1",
5380 SPR_NOACCESS, SPR_NOACCESS,
5381 &spr_read_generic, &spr_write_generic,
5382 0x00000000);
5383 spr_register(env, SPR_THRM2, "THRM2",
5384 SPR_NOACCESS, SPR_NOACCESS,
5385 &spr_read_generic, &spr_write_generic,
5386 0x00000000);
5387 spr_register(env, SPR_THRM3, "THRM3",
5388 SPR_NOACCESS, SPR_NOACCESS,
5389 &spr_read_generic, &spr_write_generic,
5390 0x00000000);
5391 /* XXX: not implemented */
5392 spr_register(env, SPR_750_TDCL, "TDCL",
5393 SPR_NOACCESS, SPR_NOACCESS,
5394 &spr_read_generic, &spr_write_generic,
5395 0x00000000);
5396 spr_register(env, SPR_750_TDCH, "TDCH",
5397 SPR_NOACCESS, SPR_NOACCESS,
5398 &spr_read_generic, &spr_write_generic,
5399 0x00000000);
5400 /* DMA */
5401 /* XXX : not implemented */
5402 spr_register(env, SPR_750_WPAR, "WPAR",
5403 SPR_NOACCESS, SPR_NOACCESS,
5404 &spr_read_generic, &spr_write_generic,
5405 0x00000000);
5406 spr_register(env, SPR_750_DMAL, "DMAL",
5407 SPR_NOACCESS, SPR_NOACCESS,
5408 &spr_read_generic, &spr_write_generic,
5409 0x00000000);
5410 spr_register(env, SPR_750_DMAU, "DMAU",
5411 SPR_NOACCESS, SPR_NOACCESS,
5412 &spr_read_generic, &spr_write_generic,
5413 0x00000000);
5414 /* Hardware implementation registers */
5415 /* XXX : not implemented */
5416 spr_register(env, SPR_HID0, "HID0",
5417 SPR_NOACCESS, SPR_NOACCESS,
5418 &spr_read_generic, &spr_write_generic,
5419 0x00000000);
5420 /* XXX : not implemented */
5421 spr_register(env, SPR_HID1, "HID1",
5422 SPR_NOACCESS, SPR_NOACCESS,
5423 &spr_read_generic, &spr_write_generic,
5424 0x00000000);
5425 /* XXX : not implemented */
5426 spr_register(env, SPR_750CL_HID2, "HID2",
5427 SPR_NOACCESS, SPR_NOACCESS,
5428 &spr_read_generic, &spr_write_generic,
5429 0x00000000);
5430 /* XXX : not implemented */
5431 spr_register(env, SPR_750CL_HID4, "HID4",
5432 SPR_NOACCESS, SPR_NOACCESS,
5433 &spr_read_generic, &spr_write_generic,
5434 0x00000000);
5435 /* Quantization registers */
5436 /* XXX : not implemented */
5437 spr_register(env, SPR_750_GQR0, "GQR0",
5438 SPR_NOACCESS, SPR_NOACCESS,
5439 &spr_read_generic, &spr_write_generic,
5440 0x00000000);
5441 /* XXX : not implemented */
5442 spr_register(env, SPR_750_GQR1, "GQR1",
5443 SPR_NOACCESS, SPR_NOACCESS,
5444 &spr_read_generic, &spr_write_generic,
5445 0x00000000);
5446 /* XXX : not implemented */
5447 spr_register(env, SPR_750_GQR2, "GQR2",
5448 SPR_NOACCESS, SPR_NOACCESS,
5449 &spr_read_generic, &spr_write_generic,
5450 0x00000000);
5451 /* XXX : not implemented */
5452 spr_register(env, SPR_750_GQR3, "GQR3",
5453 SPR_NOACCESS, SPR_NOACCESS,
5454 &spr_read_generic, &spr_write_generic,
5455 0x00000000);
5456 /* XXX : not implemented */
5457 spr_register(env, SPR_750_GQR4, "GQR4",
5458 SPR_NOACCESS, SPR_NOACCESS,
5459 &spr_read_generic, &spr_write_generic,
5460 0x00000000);
5461 /* XXX : not implemented */
5462 spr_register(env, SPR_750_GQR5, "GQR5",
5463 SPR_NOACCESS, SPR_NOACCESS,
5464 &spr_read_generic, &spr_write_generic,
5465 0x00000000);
5466 /* XXX : not implemented */
5467 spr_register(env, SPR_750_GQR6, "GQR6",
5468 SPR_NOACCESS, SPR_NOACCESS,
5469 &spr_read_generic, &spr_write_generic,
5470 0x00000000);
5471 /* XXX : not implemented */
5472 spr_register(env, SPR_750_GQR7, "GQR7",
5473 SPR_NOACCESS, SPR_NOACCESS,
5474 &spr_read_generic, &spr_write_generic,
5475 0x00000000);
5476 /* Memory management */
5477 gen_low_BATs(env);
5478 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5479 gen_high_BATs(env);
5480 init_excp_750cl(env);
5481 env->dcache_line_size = 32;
5482 env->icache_line_size = 32;
5483 /* Allocate hardware IRQ controller */
5484 ppc6xx_irq_init(env);
5485 }
5486
5487 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5488 {
5489 DeviceClass *dc = DEVICE_CLASS(oc);
5490 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5491
5492 dc->desc = "PowerPC 750 CL";
5493 pcc->init_proc = init_proc_750cl;
5494 pcc->check_pow = check_pow_hid0;
5495 /* XXX: not implemented:
5496 * cache lock instructions:
5497 * dcbz_l
5498 * floating point paired instructions
5499 * psq_lux
5500 * psq_lx
5501 * psq_stux
5502 * psq_stx
5503 * ps_abs
5504 * ps_add
5505 * ps_cmpo0
5506 * ps_cmpo1
5507 * ps_cmpu0
5508 * ps_cmpu1
5509 * ps_div
5510 * ps_madd
5511 * ps_madds0
5512 * ps_madds1
5513 * ps_merge00
5514 * ps_merge01
5515 * ps_merge10
5516 * ps_merge11
5517 * ps_mr
5518 * ps_msub
5519 * ps_mul
5520 * ps_muls0
5521 * ps_muls1
5522 * ps_nabs
5523 * ps_neg
5524 * ps_nmadd
5525 * ps_nmsub
5526 * ps_res
5527 * ps_rsqrte
5528 * ps_sel
5529 * ps_sub
5530 * ps_sum0
5531 * ps_sum1
5532 */
5533 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5534 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5535 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5536 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5537 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5538 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5539 PPC_SEGMENT | PPC_EXTERN;
5540 pcc->insns_flags2 = PPC_NONE;
5541 pcc->msr_mask = 0x000000000005FF77ULL;
5542 pcc->mmu_model = POWERPC_MMU_32B;
5543 pcc->excp_model = POWERPC_EXCP_7x0;
5544 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5545 pcc->bfd_mach = bfd_mach_ppc_750;
5546 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5547 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5548 }
5549
5550 static void init_proc_750cx (CPUPPCState *env)
5551 {
5552 gen_spr_ne_601(env);
5553 gen_spr_7xx(env);
5554 /* XXX : not implemented */
5555 spr_register(env, SPR_L2CR, "L2CR",
5556 SPR_NOACCESS, SPR_NOACCESS,
5557 &spr_read_generic, &spr_write_generic,
5558 0x00000000);
5559 /* Time base */
5560 gen_tbl(env);
5561 /* Thermal management */
5562 gen_spr_thrm(env);
5563 /* This register is not implemented but is present for compatibility */
5564 spr_register(env, SPR_SDA, "SDA",
5565 SPR_NOACCESS, SPR_NOACCESS,
5566 &spr_read_generic, &spr_write_generic,
5567 0x00000000);
5568 /* Hardware implementation registers */
5569 /* XXX : not implemented */
5570 spr_register(env, SPR_HID0, "HID0",
5571 SPR_NOACCESS, SPR_NOACCESS,
5572 &spr_read_generic, &spr_write_generic,
5573 0x00000000);
5574 /* XXX : not implemented */
5575 spr_register(env, SPR_HID1, "HID1",
5576 SPR_NOACCESS, SPR_NOACCESS,
5577 &spr_read_generic, &spr_write_generic,
5578 0x00000000);
5579 /* Memory management */
5580 gen_low_BATs(env);
5581 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5582 gen_high_BATs(env);
5583 init_excp_750cx(env);
5584 env->dcache_line_size = 32;
5585 env->icache_line_size = 32;
5586 /* Allocate hardware IRQ controller */
5587 ppc6xx_irq_init(env);
5588 }
5589
5590 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
5591 {
5592 DeviceClass *dc = DEVICE_CLASS(oc);
5593 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5594
5595 dc->desc = "PowerPC 750CX";
5596 pcc->init_proc = init_proc_750cx;
5597 pcc->check_pow = check_pow_hid0;
5598 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5599 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5600 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5601 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5602 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5603 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5604 PPC_SEGMENT | PPC_EXTERN;
5605 pcc->insns_flags2 = PPC_NONE;
5606 pcc->msr_mask = 0x000000000005FF77ULL;
5607 pcc->mmu_model = POWERPC_MMU_32B;
5608 pcc->excp_model = POWERPC_EXCP_7x0;
5609 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5610 pcc->bfd_mach = bfd_mach_ppc_750;
5611 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5612 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5613 }
5614
5615 static void init_proc_750fx (CPUPPCState *env)
5616 {
5617 gen_spr_ne_601(env);
5618 gen_spr_7xx(env);
5619 /* XXX : not implemented */
5620 spr_register(env, SPR_L2CR, "L2CR",
5621 SPR_NOACCESS, SPR_NOACCESS,
5622 &spr_read_generic, &spr_write_generic,
5623 0x00000000);
5624 /* Time base */
5625 gen_tbl(env);
5626 /* Thermal management */
5627 gen_spr_thrm(env);
5628 /* XXX : not implemented */
5629 spr_register(env, SPR_750_THRM4, "THRM4",
5630 SPR_NOACCESS, SPR_NOACCESS,
5631 &spr_read_generic, &spr_write_generic,
5632 0x00000000);
5633 /* Hardware implementation registers */
5634 /* XXX : not implemented */
5635 spr_register(env, SPR_HID0, "HID0",
5636 SPR_NOACCESS, SPR_NOACCESS,
5637 &spr_read_generic, &spr_write_generic,
5638 0x00000000);
5639 /* XXX : not implemented */
5640 spr_register(env, SPR_HID1, "HID1",
5641 SPR_NOACCESS, SPR_NOACCESS,
5642 &spr_read_generic, &spr_write_generic,
5643 0x00000000);
5644 /* XXX : not implemented */
5645 spr_register(env, SPR_750FX_HID2, "HID2",
5646 SPR_NOACCESS, SPR_NOACCESS,
5647 &spr_read_generic, &spr_write_generic,
5648 0x00000000);
5649 /* Memory management */
5650 gen_low_BATs(env);
5651 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5652 gen_high_BATs(env);
5653 init_excp_7x0(env);
5654 env->dcache_line_size = 32;
5655 env->icache_line_size = 32;
5656 /* Allocate hardware IRQ controller */
5657 ppc6xx_irq_init(env);
5658 }
5659
5660 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
5661 {
5662 DeviceClass *dc = DEVICE_CLASS(oc);
5663 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5664
5665 dc->desc = "PowerPC 750FX";
5666 pcc->init_proc = init_proc_750fx;
5667 pcc->check_pow = check_pow_hid0;
5668 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5669 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5670 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5671 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5672 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5673 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5674 PPC_SEGMENT | PPC_EXTERN;
5675 pcc->insns_flags2 = PPC_NONE;
5676 pcc->msr_mask = 0x000000000005FF77ULL;
5677 pcc->mmu_model = POWERPC_MMU_32B;
5678 pcc->excp_model = POWERPC_EXCP_7x0;
5679 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5680 pcc->bfd_mach = bfd_mach_ppc_750;
5681 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5682 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5683 }
5684
5685 static void init_proc_750gx (CPUPPCState *env)
5686 {
5687 gen_spr_ne_601(env);
5688 gen_spr_7xx(env);
5689 /* XXX : not implemented (XXX: different from 750fx) */
5690 spr_register(env, SPR_L2CR, "L2CR",
5691 SPR_NOACCESS, SPR_NOACCESS,
5692 &spr_read_generic, &spr_write_generic,
5693 0x00000000);
5694 /* Time base */
5695 gen_tbl(env);
5696 /* Thermal management */
5697 gen_spr_thrm(env);
5698 /* XXX : not implemented */
5699 spr_register(env, SPR_750_THRM4, "THRM4",
5700 SPR_NOACCESS, SPR_NOACCESS,
5701 &spr_read_generic, &spr_write_generic,
5702 0x00000000);
5703 /* Hardware implementation registers */
5704 /* XXX : not implemented (XXX: different from 750fx) */
5705 spr_register(env, SPR_HID0, "HID0",
5706 SPR_NOACCESS, SPR_NOACCESS,
5707 &spr_read_generic, &spr_write_generic,
5708 0x00000000);
5709 /* XXX : not implemented */
5710 spr_register(env, SPR_HID1, "HID1",
5711 SPR_NOACCESS, SPR_NOACCESS,
5712 &spr_read_generic, &spr_write_generic,
5713 0x00000000);
5714 /* XXX : not implemented (XXX: different from 750fx) */
5715 spr_register(env, SPR_750FX_HID2, "HID2",
5716 SPR_NOACCESS, SPR_NOACCESS,
5717 &spr_read_generic, &spr_write_generic,
5718 0x00000000);
5719 /* Memory management */
5720 gen_low_BATs(env);
5721 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5722 gen_high_BATs(env);
5723 init_excp_7x0(env);
5724 env->dcache_line_size = 32;
5725 env->icache_line_size = 32;
5726 /* Allocate hardware IRQ controller */
5727 ppc6xx_irq_init(env);
5728 }
5729
5730 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
5731 {
5732 DeviceClass *dc = DEVICE_CLASS(oc);
5733 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5734
5735 dc->desc = "PowerPC 750GX";
5736 pcc->init_proc = init_proc_750gx;
5737 pcc->check_pow = check_pow_hid0;
5738 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5739 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5740 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5741 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5742 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5743 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5744 PPC_SEGMENT | PPC_EXTERN;
5745 pcc->insns_flags2 = PPC_NONE;
5746 pcc->msr_mask = 0x000000000005FF77ULL;
5747 pcc->mmu_model = POWERPC_MMU_32B;
5748 pcc->excp_model = POWERPC_EXCP_7x0;
5749 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5750 pcc->bfd_mach = bfd_mach_ppc_750;
5751 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5752 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5753 }
5754
5755 static void init_proc_745 (CPUPPCState *env)
5756 {
5757 gen_spr_ne_601(env);
5758 gen_spr_7xx(env);
5759 gen_spr_G2_755(env);
5760 /* Time base */
5761 gen_tbl(env);
5762 /* Thermal management */
5763 gen_spr_thrm(env);
5764 /* Hardware implementation registers */
5765 /* XXX : not implemented */
5766 spr_register(env, SPR_HID0, "HID0",
5767 SPR_NOACCESS, SPR_NOACCESS,
5768 &spr_read_generic, &spr_write_generic,
5769 0x00000000);
5770 /* XXX : not implemented */
5771 spr_register(env, SPR_HID1, "HID1",
5772 SPR_NOACCESS, SPR_NOACCESS,
5773 &spr_read_generic, &spr_write_generic,
5774 0x00000000);
5775 /* XXX : not implemented */
5776 spr_register(env, SPR_HID2, "HID2",
5777 SPR_NOACCESS, SPR_NOACCESS,
5778 &spr_read_generic, &spr_write_generic,
5779 0x00000000);
5780 /* Memory management */
5781 gen_low_BATs(env);
5782 gen_high_BATs(env);
5783 gen_6xx_7xx_soft_tlb(env, 64, 2);
5784 init_excp_7x5(env);
5785 env->dcache_line_size = 32;
5786 env->icache_line_size = 32;
5787 /* Allocate hardware IRQ controller */
5788 ppc6xx_irq_init(env);
5789 }
5790
5791 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
5792 {
5793 DeviceClass *dc = DEVICE_CLASS(oc);
5794 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5795
5796 dc->desc = "PowerPC 745";
5797 pcc->init_proc = init_proc_745;
5798 pcc->check_pow = check_pow_hid0;
5799 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5800 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5801 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5802 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5803 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5804 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5805 PPC_SEGMENT | PPC_EXTERN;
5806 pcc->insns_flags2 = PPC_NONE;
5807 pcc->msr_mask = 0x000000000005FF77ULL;
5808 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5809 pcc->excp_model = POWERPC_EXCP_7x5;
5810 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5811 pcc->bfd_mach = bfd_mach_ppc_750;
5812 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5813 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5814 }
5815
5816 static void init_proc_755 (CPUPPCState *env)
5817 {
5818 gen_spr_ne_601(env);
5819 gen_spr_7xx(env);
5820 gen_spr_G2_755(env);
5821 /* Time base */
5822 gen_tbl(env);
5823 /* L2 cache control */
5824 /* XXX : not implemented */
5825 spr_register(env, SPR_L2CR, "L2CR",
5826 SPR_NOACCESS, SPR_NOACCESS,
5827 &spr_read_generic, &spr_write_generic,
5828 0x00000000);
5829 /* XXX : not implemented */
5830 spr_register(env, SPR_L2PMCR, "L2PMCR",
5831 SPR_NOACCESS, SPR_NOACCESS,
5832 &spr_read_generic, &spr_write_generic,
5833 0x00000000);
5834 /* Thermal management */
5835 gen_spr_thrm(env);
5836 /* Hardware implementation registers */
5837 /* XXX : not implemented */
5838 spr_register(env, SPR_HID0, "HID0",
5839 SPR_NOACCESS, SPR_NOACCESS,
5840 &spr_read_generic, &spr_write_generic,
5841 0x00000000);
5842 /* XXX : not implemented */
5843 spr_register(env, SPR_HID1, "HID1",
5844 SPR_NOACCESS, SPR_NOACCESS,
5845 &spr_read_generic, &spr_write_generic,
5846 0x00000000);
5847 /* XXX : not implemented */
5848 spr_register(env, SPR_HID2, "HID2",
5849 SPR_NOACCESS, SPR_NOACCESS,
5850 &spr_read_generic, &spr_write_generic,
5851 0x00000000);
5852 /* Memory management */
5853 gen_low_BATs(env);
5854 gen_high_BATs(env);
5855 gen_6xx_7xx_soft_tlb(env, 64, 2);
5856 init_excp_7x5(env);
5857 env->dcache_line_size = 32;
5858 env->icache_line_size = 32;
5859 /* Allocate hardware IRQ controller */
5860 ppc6xx_irq_init(env);
5861 }
5862
5863 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
5864 {
5865 DeviceClass *dc = DEVICE_CLASS(oc);
5866 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5867
5868 dc->desc = "PowerPC 755";
5869 pcc->init_proc = init_proc_755;
5870 pcc->check_pow = check_pow_hid0;
5871 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5872 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5873 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5874 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5875 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5876 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5877 PPC_SEGMENT | PPC_EXTERN;
5878 pcc->insns_flags2 = PPC_NONE;
5879 pcc->msr_mask = 0x000000000005FF77ULL;
5880 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5881 pcc->excp_model = POWERPC_EXCP_7x5;
5882 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5883 pcc->bfd_mach = bfd_mach_ppc_750;
5884 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5885 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5886 }
5887
5888 static void init_proc_7400 (CPUPPCState *env)
5889 {
5890 gen_spr_ne_601(env);
5891 gen_spr_7xx(env);
5892 /* Time base */
5893 gen_tbl(env);
5894 /* 74xx specific SPR */
5895 gen_spr_74xx(env);
5896 /* XXX : not implemented */
5897 spr_register(env, SPR_UBAMR, "UBAMR",
5898 &spr_read_ureg, SPR_NOACCESS,
5899 &spr_read_ureg, SPR_NOACCESS,
5900 0x00000000);
5901 /* XXX: this seems not implemented on all revisions. */
5902 /* XXX : not implemented */
5903 spr_register(env, SPR_MSSCR1, "MSSCR1",
5904 SPR_NOACCESS, SPR_NOACCESS,
5905 &spr_read_generic, &spr_write_generic,
5906 0x00000000);
5907 /* Thermal management */
5908 gen_spr_thrm(env);
5909 /* Memory management */
5910 gen_low_BATs(env);
5911 init_excp_7400(env);
5912 env->dcache_line_size = 32;
5913 env->icache_line_size = 32;
5914 /* Allocate hardware IRQ controller */
5915 ppc6xx_irq_init(env);
5916 }
5917
5918 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
5919 {
5920 DeviceClass *dc = DEVICE_CLASS(oc);
5921 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5922
5923 dc->desc = "PowerPC 7400 (aka G4)";
5924 pcc->init_proc = init_proc_7400;
5925 pcc->check_pow = check_pow_hid0;
5926 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5927 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5928 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5929 PPC_FLOAT_STFIWX |
5930 PPC_CACHE | PPC_CACHE_ICBI |
5931 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5932 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5933 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5934 PPC_MEM_TLBIA |
5935 PPC_SEGMENT | PPC_EXTERN |
5936 PPC_ALTIVEC;
5937 pcc->insns_flags2 = PPC_NONE;
5938 pcc->msr_mask = 0x000000000205FF77ULL;
5939 pcc->mmu_model = POWERPC_MMU_32B;
5940 pcc->excp_model = POWERPC_EXCP_74xx;
5941 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5942 pcc->bfd_mach = bfd_mach_ppc_7400;
5943 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5944 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5945 POWERPC_FLAG_BUS_CLK;
5946 }
5947
5948 static void init_proc_7410 (CPUPPCState *env)
5949 {
5950 gen_spr_ne_601(env);
5951 gen_spr_7xx(env);
5952 /* Time base */
5953 gen_tbl(env);
5954 /* 74xx specific SPR */
5955 gen_spr_74xx(env);
5956 /* XXX : not implemented */
5957 spr_register(env, SPR_UBAMR, "UBAMR",
5958 &spr_read_ureg, SPR_NOACCESS,
5959 &spr_read_ureg, SPR_NOACCESS,
5960 0x00000000);
5961 /* Thermal management */
5962 gen_spr_thrm(env);
5963 /* L2PMCR */
5964 /* XXX : not implemented */
5965 spr_register(env, SPR_L2PMCR, "L2PMCR",
5966 SPR_NOACCESS, SPR_NOACCESS,
5967 &spr_read_generic, &spr_write_generic,
5968 0x00000000);
5969 /* LDSTDB */
5970 /* XXX : not implemented */
5971 spr_register(env, SPR_LDSTDB, "LDSTDB",
5972 SPR_NOACCESS, SPR_NOACCESS,
5973 &spr_read_generic, &spr_write_generic,
5974 0x00000000);
5975 /* Memory management */
5976 gen_low_BATs(env);
5977 init_excp_7400(env);
5978 env->dcache_line_size = 32;
5979 env->icache_line_size = 32;
5980 /* Allocate hardware IRQ controller */
5981 ppc6xx_irq_init(env);
5982 }
5983
5984 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
5985 {
5986 DeviceClass *dc = DEVICE_CLASS(oc);
5987 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5988
5989 dc->desc = "PowerPC 7410 (aka G4)";
5990 pcc->init_proc = init_proc_7410;
5991 pcc->check_pow = check_pow_hid0;
5992 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5993 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5994 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5995 PPC_FLOAT_STFIWX |
5996 PPC_CACHE | PPC_CACHE_ICBI |
5997 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5998 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5999 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6000 PPC_MEM_TLBIA |
6001 PPC_SEGMENT | PPC_EXTERN |
6002 PPC_ALTIVEC;
6003 pcc->insns_flags2 = PPC_NONE;
6004 pcc->msr_mask = 0x000000000205FF77ULL;
6005 pcc->mmu_model = POWERPC_MMU_32B;
6006 pcc->excp_model = POWERPC_EXCP_74xx;
6007 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6008 pcc->bfd_mach = bfd_mach_ppc_7400;
6009 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6010 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6011 POWERPC_FLAG_BUS_CLK;
6012 }
6013
6014 static void init_proc_7440 (CPUPPCState *env)
6015 {
6016 gen_spr_ne_601(env);
6017 gen_spr_7xx(env);
6018 /* Time base */
6019 gen_tbl(env);
6020 /* 74xx specific SPR */
6021 gen_spr_74xx(env);
6022 /* XXX : not implemented */
6023 spr_register(env, SPR_UBAMR, "UBAMR",
6024 &spr_read_ureg, SPR_NOACCESS,
6025 &spr_read_ureg, SPR_NOACCESS,
6026 0x00000000);
6027 /* LDSTCR */
6028 /* XXX : not implemented */
6029 spr_register(env, SPR_LDSTCR, "LDSTCR",
6030 SPR_NOACCESS, SPR_NOACCESS,
6031 &spr_read_generic, &spr_write_generic,
6032 0x00000000);
6033 /* ICTRL */
6034 /* XXX : not implemented */
6035 spr_register(env, SPR_ICTRL, "ICTRL",
6036 SPR_NOACCESS, SPR_NOACCESS,
6037 &spr_read_generic, &spr_write_generic,
6038 0x00000000);
6039 /* MSSSR0 */
6040 /* XXX : not implemented */
6041 spr_register(env, SPR_MSSSR0, "MSSSR0",
6042 SPR_NOACCESS, SPR_NOACCESS,
6043 &spr_read_generic, &spr_write_generic,
6044 0x00000000);
6045 /* PMC */
6046 /* XXX : not implemented */
6047 spr_register(env, SPR_PMC5, "PMC5",
6048 SPR_NOACCESS, SPR_NOACCESS,
6049 &spr_read_generic, &spr_write_generic,
6050 0x00000000);
6051 /* XXX : not implemented */
6052 spr_register(env, SPR_UPMC5, "UPMC5",
6053 &spr_read_ureg, SPR_NOACCESS,
6054 &spr_read_ureg, SPR_NOACCESS,
6055 0x00000000);
6056 /* XXX : not implemented */
6057 spr_register(env, SPR_PMC6, "PMC6",
6058 SPR_NOACCESS, SPR_NOACCESS,
6059 &spr_read_generic, &spr_write_generic,
6060 0x00000000);
6061 /* XXX : not implemented */
6062 spr_register(env, SPR_UPMC6, "UPMC6",
6063 &spr_read_ureg, SPR_NOACCESS,
6064 &spr_read_ureg, SPR_NOACCESS,
6065 0x00000000);
6066 /* Memory management */
6067 gen_low_BATs(env);
6068 gen_74xx_soft_tlb(env, 128, 2);
6069 init_excp_7450(env);
6070 env->dcache_line_size = 32;
6071 env->icache_line_size = 32;
6072 /* Allocate hardware IRQ controller */
6073 ppc6xx_irq_init(env);
6074 }
6075
6076 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
6077 {
6078 DeviceClass *dc = DEVICE_CLASS(oc);
6079 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6080
6081 dc->desc = "PowerPC 7440 (aka G4)";
6082 pcc->init_proc = init_proc_7440;
6083 pcc->check_pow = check_pow_hid0_74xx;
6084 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6085 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6086 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6087 PPC_FLOAT_STFIWX |
6088 PPC_CACHE | PPC_CACHE_ICBI |
6089 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6090 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6091 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6092 PPC_MEM_TLBIA | PPC_74xx_TLB |
6093 PPC_SEGMENT | PPC_EXTERN |
6094 PPC_ALTIVEC;
6095 pcc->insns_flags2 = PPC_NONE;
6096 pcc->msr_mask = 0x000000000205FF77ULL;
6097 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6098 pcc->excp_model = POWERPC_EXCP_74xx;
6099 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6100 pcc->bfd_mach = bfd_mach_ppc_7400;
6101 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6102 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6103 POWERPC_FLAG_BUS_CLK;
6104 }
6105
6106 static void init_proc_7450 (CPUPPCState *env)
6107 {
6108 gen_spr_ne_601(env);
6109 gen_spr_7xx(env);
6110 /* Time base */
6111 gen_tbl(env);
6112 /* 74xx specific SPR */
6113 gen_spr_74xx(env);
6114 /* Level 3 cache control */
6115 gen_l3_ctrl(env);
6116 /* L3ITCR1 */
6117 /* XXX : not implemented */
6118 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6119 SPR_NOACCESS, SPR_NOACCESS,
6120 &spr_read_generic, &spr_write_generic,
6121 0x00000000);
6122 /* L3ITCR2 */
6123 /* XXX : not implemented */
6124 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6125 SPR_NOACCESS, SPR_NOACCESS,
6126 &spr_read_generic, &spr_write_generic,
6127 0x00000000);
6128 /* L3ITCR3 */
6129 /* XXX : not implemented */
6130 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6131 SPR_NOACCESS, SPR_NOACCESS,
6132 &spr_read_generic, &spr_write_generic,
6133 0x00000000);
6134 /* L3OHCR */
6135 /* XXX : not implemented */
6136 spr_register(env, SPR_L3OHCR, "L3OHCR",
6137 SPR_NOACCESS, SPR_NOACCESS,
6138 &spr_read_generic, &spr_write_generic,
6139 0x00000000);
6140 /* XXX : not implemented */
6141 spr_register(env, SPR_UBAMR, "UBAMR",
6142 &spr_read_ureg, SPR_NOACCESS,
6143 &spr_read_ureg, SPR_NOACCESS,
6144 0x00000000);
6145 /* LDSTCR */
6146 /* XXX : not implemented */
6147 spr_register(env, SPR_LDSTCR, "LDSTCR",
6148 SPR_NOACCESS, SPR_NOACCESS,
6149 &spr_read_generic, &spr_write_generic,
6150 0x00000000);
6151 /* ICTRL */
6152 /* XXX : not implemented */
6153 spr_register(env, SPR_ICTRL, "ICTRL",
6154 SPR_NOACCESS, SPR_NOACCESS,
6155 &spr_read_generic, &spr_write_generic,
6156 0x00000000);
6157 /* MSSSR0 */
6158 /* XXX : not implemented */
6159 spr_register(env, SPR_MSSSR0, "MSSSR0",
6160 SPR_NOACCESS, SPR_NOACCESS,
6161 &spr_read_generic, &spr_write_generic,
6162 0x00000000);
6163 /* PMC */
6164 /* XXX : not implemented */
6165 spr_register(env, SPR_PMC5, "PMC5",
6166 SPR_NOACCESS, SPR_NOACCESS,
6167 &spr_read_generic, &spr_write_generic,
6168 0x00000000);
6169 /* XXX : not implemented */
6170 spr_register(env, SPR_UPMC5, "UPMC5",
6171 &spr_read_ureg, SPR_NOACCESS,
6172 &spr_read_ureg, SPR_NOACCESS,
6173 0x00000000);
6174 /* XXX : not implemented */
6175 spr_register(env, SPR_PMC6, "PMC6",
6176 SPR_NOACCESS, SPR_NOACCESS,
6177 &spr_read_generic, &spr_write_generic,
6178 0x00000000);
6179 /* XXX : not implemented */
6180 spr_register(env, SPR_UPMC6, "UPMC6",
6181 &spr_read_ureg, SPR_NOACCESS,
6182 &spr_read_ureg, SPR_NOACCESS,
6183 0x00000000);
6184 /* Memory management */
6185 gen_low_BATs(env);
6186 gen_74xx_soft_tlb(env, 128, 2);
6187 init_excp_7450(env);
6188 env->dcache_line_size = 32;
6189 env->icache_line_size = 32;
6190 /* Allocate hardware IRQ controller */
6191 ppc6xx_irq_init(env);
6192 }
6193
6194 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6195 {
6196 DeviceClass *dc = DEVICE_CLASS(oc);
6197 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6198
6199 dc->desc = "PowerPC 7450 (aka G4)";
6200 pcc->init_proc = init_proc_7450;
6201 pcc->check_pow = check_pow_hid0_74xx;
6202 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6203 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6204 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6205 PPC_FLOAT_STFIWX |
6206 PPC_CACHE | PPC_CACHE_ICBI |
6207 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6208 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6209 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6210 PPC_MEM_TLBIA | PPC_74xx_TLB |
6211 PPC_SEGMENT | PPC_EXTERN |
6212 PPC_ALTIVEC;
6213 pcc->insns_flags2 = PPC_NONE;
6214 pcc->msr_mask = 0x000000000205FF77ULL;
6215 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6216 pcc->excp_model = POWERPC_EXCP_74xx;
6217 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6218 pcc->bfd_mach = bfd_mach_ppc_7400;
6219 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6220 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6221 POWERPC_FLAG_BUS_CLK;
6222 }
6223
6224 static void init_proc_7445 (CPUPPCState *env)
6225 {
6226 gen_spr_ne_601(env);
6227 gen_spr_7xx(env);
6228 /* Time base */
6229 gen_tbl(env);
6230 /* 74xx specific SPR */
6231 gen_spr_74xx(env);
6232 /* LDSTCR */
6233 /* XXX : not implemented */
6234 spr_register(env, SPR_LDSTCR, "LDSTCR",
6235 SPR_NOACCESS, SPR_NOACCESS,
6236 &spr_read_generic, &spr_write_generic,
6237 0x00000000);
6238 /* ICTRL */
6239 /* XXX : not implemented */
6240 spr_register(env, SPR_ICTRL, "ICTRL",
6241 SPR_NOACCESS, SPR_NOACCESS,
6242 &spr_read_generic, &spr_write_generic,
6243 0x00000000);
6244 /* MSSSR0 */
6245 /* XXX : not implemented */
6246 spr_register(env, SPR_MSSSR0, "MSSSR0",
6247 SPR_NOACCESS, SPR_NOACCESS,
6248 &spr_read_generic, &spr_write_generic,
6249 0x00000000);
6250 /* PMC */
6251 /* XXX : not implemented */
6252 spr_register(env, SPR_PMC5, "PMC5",
6253 SPR_NOACCESS, SPR_NOACCESS,
6254 &spr_read_generic, &spr_write_generic,
6255 0x00000000);
6256 /* XXX : not implemented */
6257 spr_register(env, SPR_UPMC5, "UPMC5",
6258 &spr_read_ureg, SPR_NOACCESS,
6259 &spr_read_ureg, SPR_NOACCESS,
6260 0x00000000);
6261 /* XXX : not implemented */
6262 spr_register(env, SPR_PMC6, "PMC6",
6263 SPR_NOACCESS, SPR_NOACCESS,
6264 &spr_read_generic, &spr_write_generic,
6265 0x00000000);
6266 /* XXX : not implemented */
6267 spr_register(env, SPR_UPMC6, "UPMC6",
6268 &spr_read_ureg, SPR_NOACCESS,
6269 &spr_read_ureg, SPR_NOACCESS,
6270 0x00000000);
6271 /* SPRGs */
6272 spr_register(env, SPR_SPRG4, "SPRG4",
6273 SPR_NOACCESS, SPR_NOACCESS,
6274 &spr_read_generic, &spr_write_generic,
6275 0x00000000);
6276 spr_register(env, SPR_USPRG4, "USPRG4",
6277 &spr_read_ureg, SPR_NOACCESS,
6278 &spr_read_ureg, SPR_NOACCESS,
6279 0x00000000);
6280 spr_register(env, SPR_SPRG5, "SPRG5",
6281 SPR_NOACCESS, SPR_NOACCESS,
6282 &spr_read_generic, &spr_write_generic,
6283 0x00000000);
6284 spr_register(env, SPR_USPRG5, "USPRG5",
6285 &spr_read_ureg, SPR_NOACCESS,
6286 &spr_read_ureg, SPR_NOACCESS,
6287 0x00000000);
6288 spr_register(env, SPR_SPRG6, "SPRG6",
6289 SPR_NOACCESS, SPR_NOACCESS,
6290 &spr_read_generic, &spr_write_generic,
6291 0x00000000);
6292 spr_register(env, SPR_USPRG6, "USPRG6",
6293 &spr_read_ureg, SPR_NOACCESS,
6294 &spr_read_ureg, SPR_NOACCESS,
6295 0x00000000);
6296 spr_register(env, SPR_SPRG7, "SPRG7",
6297 SPR_NOACCESS, SPR_NOACCESS,
6298 &spr_read_generic, &spr_write_generic,
6299 0x00000000);
6300 spr_register(env, SPR_USPRG7, "USPRG7",
6301 &spr_read_ureg, SPR_NOACCESS,
6302 &spr_read_ureg, SPR_NOACCESS,
6303 0x00000000);
6304 /* Memory management */
6305 gen_low_BATs(env);
6306 gen_high_BATs(env);
6307 gen_74xx_soft_tlb(env, 128, 2);
6308 init_excp_7450(env);
6309 env->dcache_line_size = 32;
6310 env->icache_line_size = 32;
6311 /* Allocate hardware IRQ controller */
6312 ppc6xx_irq_init(env);
6313 }
6314
6315 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6316 {
6317 DeviceClass *dc = DEVICE_CLASS(oc);
6318 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6319
6320 dc->desc = "PowerPC 7445 (aka G4)";
6321 pcc->init_proc = init_proc_7445;
6322 pcc->check_pow = check_pow_hid0_74xx;
6323 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6324 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6325 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6326 PPC_FLOAT_STFIWX |
6327 PPC_CACHE | PPC_CACHE_ICBI |
6328 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6329 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6330 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6331 PPC_MEM_TLBIA | PPC_74xx_TLB |
6332 PPC_SEGMENT | PPC_EXTERN |
6333 PPC_ALTIVEC;
6334 pcc->insns_flags2 = PPC_NONE;
6335 pcc->msr_mask = 0x000000000205FF77ULL;
6336 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6337 pcc->excp_model = POWERPC_EXCP_74xx;
6338 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6339 pcc->bfd_mach = bfd_mach_ppc_7400;
6340 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6341 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6342 POWERPC_FLAG_BUS_CLK;
6343 }
6344
6345 static void init_proc_7455 (CPUPPCState *env)
6346 {
6347 gen_spr_ne_601(env);
6348 gen_spr_7xx(env);
6349 /* Time base */
6350 gen_tbl(env);
6351 /* 74xx specific SPR */
6352 gen_spr_74xx(env);
6353 /* Level 3 cache control */
6354 gen_l3_ctrl(env);
6355 /* LDSTCR */
6356 /* XXX : not implemented */
6357 spr_register(env, SPR_LDSTCR, "LDSTCR",
6358 SPR_NOACCESS, SPR_NOACCESS,
6359 &spr_read_generic, &spr_write_generic,
6360 0x00000000);
6361 /* ICTRL */
6362 /* XXX : not implemented */
6363 spr_register(env, SPR_ICTRL, "ICTRL",
6364 SPR_NOACCESS, SPR_NOACCESS,
6365 &spr_read_generic, &spr_write_generic,
6366 0x00000000);
6367 /* MSSSR0 */
6368 /* XXX : not implemented */
6369 spr_register(env, SPR_MSSSR0, "MSSSR0",
6370 SPR_NOACCESS, SPR_NOACCESS,
6371 &spr_read_generic, &spr_write_generic,
6372 0x00000000);
6373 /* PMC */
6374 /* XXX : not implemented */
6375 spr_register(env, SPR_PMC5, "PMC5",
6376 SPR_NOACCESS, SPR_NOACCESS,
6377 &spr_read_generic, &spr_write_generic,
6378 0x00000000);
6379 /* XXX : not implemented */
6380 spr_register(env, SPR_UPMC5, "UPMC5",
6381 &spr_read_ureg, SPR_NOACCESS,
6382 &spr_read_ureg, SPR_NOACCESS,
6383 0x00000000);
6384 /* XXX : not implemented */
6385 spr_register(env, SPR_PMC6, "PMC6",
6386 SPR_NOACCESS, SPR_NOACCESS,
6387 &spr_read_generic, &spr_write_generic,
6388 0x00000000);
6389 /* XXX : not implemented */
6390 spr_register(env, SPR_UPMC6, "UPMC6",
6391 &spr_read_ureg, SPR_NOACCESS,
6392 &spr_read_ureg, SPR_NOACCESS,
6393 0x00000000);
6394 /* SPRGs */
6395 spr_register(env, SPR_SPRG4, "SPRG4",
6396 SPR_NOACCESS, SPR_NOACCESS,
6397 &spr_read_generic, &spr_write_generic,
6398 0x00000000);
6399 spr_register(env, SPR_USPRG4, "USPRG4",
6400 &spr_read_ureg, SPR_NOACCESS,
6401 &spr_read_ureg, SPR_NOACCESS,
6402 0x00000000);
6403 spr_register(env, SPR_SPRG5, "SPRG5",
6404 SPR_NOACCESS, SPR_NOACCESS,
6405 &spr_read_generic, &spr_write_generic,
6406 0x00000000);
6407 spr_register(env, SPR_USPRG5, "USPRG5",
6408 &spr_read_ureg, SPR_NOACCESS,
6409 &spr_read_ureg, SPR_NOACCESS,
6410 0x00000000);
6411 spr_register(env, SPR_SPRG6, "SPRG6",
6412 SPR_NOACCESS, SPR_NOACCESS,
6413 &spr_read_generic, &spr_write_generic,
6414 0x00000000);
6415 spr_register(env, SPR_USPRG6, "USPRG6",
6416 &spr_read_ureg, SPR_NOACCESS,
6417 &spr_read_ureg, SPR_NOACCESS,
6418 0x00000000);
6419 spr_register(env, SPR_SPRG7, "SPRG7",
6420 SPR_NOACCESS, SPR_NOACCESS,
6421 &spr_read_generic, &spr_write_generic,
6422 0x00000000);
6423 spr_register(env, SPR_USPRG7, "USPRG7",
6424 &spr_read_ureg, SPR_NOACCESS,
6425 &spr_read_ureg, SPR_NOACCESS,
6426 0x00000000);
6427 /* Memory management */
6428 gen_low_BATs(env);
6429 gen_high_BATs(env);
6430 gen_74xx_soft_tlb(env, 128, 2);
6431 init_excp_7450(env);
6432 env->dcache_line_size = 32;
6433 env->icache_line_size = 32;
6434 /* Allocate hardware IRQ controller */
6435 ppc6xx_irq_init(env);
6436 }
6437
6438 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
6439 {
6440 DeviceClass *dc = DEVICE_CLASS(oc);
6441 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6442
6443 dc->desc = "PowerPC 7455 (aka G4)";
6444 pcc->init_proc = init_proc_7455;
6445 pcc->check_pow = check_pow_hid0_74xx;
6446 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6447 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6448 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6449 PPC_FLOAT_STFIWX |
6450 PPC_CACHE | PPC_CACHE_ICBI |
6451 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6452 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6453 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6454 PPC_MEM_TLBIA | PPC_74xx_TLB |
6455 PPC_SEGMENT | PPC_EXTERN |
6456 PPC_ALTIVEC;
6457 pcc->insns_flags2 = PPC_NONE;
6458 pcc->msr_mask = 0x000000000205FF77ULL;
6459 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6460 pcc->excp_model = POWERPC_EXCP_74xx;
6461 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6462 pcc->bfd_mach = bfd_mach_ppc_7400;
6463 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6464 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6465 POWERPC_FLAG_BUS_CLK;
6466 }
6467
6468 static void init_proc_7457 (CPUPPCState *env)
6469 {
6470 gen_spr_ne_601(env);
6471 gen_spr_7xx(env);
6472 /* Time base */
6473 gen_tbl(env);
6474 /* 74xx specific SPR */
6475 gen_spr_74xx(env);
6476 /* Level 3 cache control */
6477 gen_l3_ctrl(env);
6478 /* L3ITCR1 */
6479 /* XXX : not implemented */
6480 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6481 SPR_NOACCESS, SPR_NOACCESS,
6482 &spr_read_generic, &spr_write_generic,
6483 0x00000000);
6484 /* L3ITCR2 */
6485 /* XXX : not implemented */
6486 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6487 SPR_NOACCESS, SPR_NOACCESS,
6488 &spr_read_generic, &spr_write_generic,
6489 0x00000000);
6490 /* L3ITCR3 */
6491 /* XXX : not implemented */
6492 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6493 SPR_NOACCESS, SPR_NOACCESS,
6494 &spr_read_generic, &spr_write_generic,
6495 0x00000000);
6496 /* L3OHCR */
6497 /* XXX : not implemented */
6498 spr_register(env, SPR_L3OHCR, "L3OHCR",
6499 SPR_NOACCESS, SPR_NOACCESS,
6500 &spr_read_generic, &spr_write_generic,
6501 0x00000000);
6502 /* LDSTCR */
6503 /* XXX : not implemented */
6504 spr_register(env, SPR_LDSTCR, "LDSTCR",
6505 SPR_NOACCESS, SPR_NOACCESS,
6506 &spr_read_generic, &spr_write_generic,
6507 0x00000000);
6508 /* ICTRL */
6509 /* XXX : not implemented */
6510 spr_register(env, SPR_ICTRL, "ICTRL",
6511 SPR_NOACCESS, SPR_NOACCESS,
6512 &spr_read_generic, &spr_write_generic,
6513 0x00000000);
6514 /* MSSSR0 */
6515 /* XXX : not implemented */
6516 spr_register(env, SPR_MSSSR0, "MSSSR0",
6517 SPR_NOACCESS, SPR_NOACCESS,
6518 &spr_read_generic, &spr_write_generic,
6519 0x00000000);
6520 /* PMC */
6521 /* XXX : not implemented */
6522 spr_register(env, SPR_PMC5, "PMC5",
6523 SPR_NOACCESS, SPR_NOACCESS,
6524 &spr_read_generic, &spr_write_generic,
6525 0x00000000);
6526 /* XXX : not implemented */
6527 spr_register(env, SPR_UPMC5, "UPMC5",
6528 &spr_read_ureg, SPR_NOACCESS,
6529 &spr_read_ureg, SPR_NOACCESS,
6530 0x00000000);
6531 /* XXX : not implemented */
6532 spr_register(env, SPR_PMC6, "PMC6",
6533 SPR_NOACCESS, SPR_NOACCESS,
6534 &spr_read_generic, &spr_write_generic,
6535 0x00000000);
6536 /* XXX : not implemented */
6537 spr_register(env, SPR_UPMC6, "UPMC6",
6538 &spr_read_ureg, SPR_NOACCESS,
6539 &spr_read_ureg, SPR_NOACCESS,
6540 0x00000000);
6541 /* SPRGs */
6542 spr_register(env, SPR_SPRG4, "SPRG4",
6543 SPR_NOACCESS, SPR_NOACCESS,
6544 &spr_read_generic, &spr_write_generic,
6545 0x00000000);
6546 spr_register(env, SPR_USPRG4, "USPRG4",
6547 &spr_read_ureg, SPR_NOACCESS,
6548 &spr_read_ureg, SPR_NOACCESS,
6549 0x00000000);
6550 spr_register(env, SPR_SPRG5, "SPRG5",
6551 SPR_NOACCESS, SPR_NOACCESS,
6552 &spr_read_generic, &spr_write_generic,
6553 0x00000000);
6554 spr_register(env, SPR_USPRG5, "USPRG5",
6555 &spr_read_ureg, SPR_NOACCESS,
6556 &spr_read_ureg, SPR_NOACCESS,
6557 0x00000000);
6558 spr_register(env, SPR_SPRG6, "SPRG6",
6559 SPR_NOACCESS, SPR_NOACCESS,
6560 &spr_read_generic, &spr_write_generic,
6561 0x00000000);
6562 spr_register(env, SPR_USPRG6, "USPRG6",
6563 &spr_read_ureg, SPR_NOACCESS,
6564 &spr_read_ureg, SPR_NOACCESS,
6565 0x00000000);
6566 spr_register(env, SPR_SPRG7, "SPRG7",
6567 SPR_NOACCESS, SPR_NOACCESS,
6568 &spr_read_generic, &spr_write_generic,
6569 0x00000000);
6570 spr_register(env, SPR_USPRG7, "USPRG7",
6571 &spr_read_ureg, SPR_NOACCESS,
6572 &spr_read_ureg, SPR_NOACCESS,
6573 0x00000000);
6574 /* Memory management */
6575 gen_low_BATs(env);
6576 gen_high_BATs(env);
6577 gen_74xx_soft_tlb(env, 128, 2);
6578 init_excp_7450(env);
6579 env->dcache_line_size = 32;
6580 env->icache_line_size = 32;
6581 /* Allocate hardware IRQ controller */
6582 ppc6xx_irq_init(env);
6583 }
6584
6585 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
6586 {
6587 DeviceClass *dc = DEVICE_CLASS(oc);
6588 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6589
6590 dc->desc = "PowerPC 7457 (aka G4)";
6591 pcc->init_proc = init_proc_7457;
6592 pcc->check_pow = check_pow_hid0_74xx;
6593 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6594 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6595 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6596 PPC_FLOAT_STFIWX |
6597 PPC_CACHE | PPC_CACHE_ICBI |
6598 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6599 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6600 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6601 PPC_MEM_TLBIA | PPC_74xx_TLB |
6602 PPC_SEGMENT | PPC_EXTERN |
6603 PPC_ALTIVEC;
6604 pcc->insns_flags2 = PPC_NONE;
6605 pcc->msr_mask = 0x000000000205FF77ULL;
6606 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6607 pcc->excp_model = POWERPC_EXCP_74xx;
6608 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6609 pcc->bfd_mach = bfd_mach_ppc_7400;
6610 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6611 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6612 POWERPC_FLAG_BUS_CLK;
6613 }
6614
6615 #if defined (TARGET_PPC64)
6616 #if defined(CONFIG_USER_ONLY)
6617 #define POWERPC970_HID5_INIT 0x00000080
6618 #else
6619 #define POWERPC970_HID5_INIT 0x00000000
6620 #endif
6621
6622 static int check_pow_970 (CPUPPCState *env)
6623 {
6624 if (env->spr[SPR_HID0] & 0x00600000)
6625 return 1;
6626
6627 return 0;
6628 }
6629
6630 static void init_proc_970 (CPUPPCState *env)
6631 {
6632 gen_spr_ne_601(env);
6633 gen_spr_7xx(env);
6634 /* Time base */
6635 gen_tbl(env);
6636 /* Hardware implementation registers */
6637 /* XXX : not implemented */
6638 spr_register(env, SPR_HID0, "HID0",
6639 SPR_NOACCESS, SPR_NOACCESS,
6640 &spr_read_generic, &spr_write_clear,
6641 0x60000000);
6642 /* XXX : not implemented */
6643 spr_register(env, SPR_HID1, "HID1",
6644 SPR_NOACCESS, SPR_NOACCESS,
6645 &spr_read_generic, &spr_write_generic,
6646 0x00000000);
6647 /* XXX : not implemented */
6648 spr_register(env, SPR_750FX_HID2, "HID2",
6649 SPR_NOACCESS, SPR_NOACCESS,
6650 &spr_read_generic, &spr_write_generic,
6651 0x00000000);
6652 /* XXX : not implemented */
6653 spr_register(env, SPR_970_HID5, "HID5",
6654 SPR_NOACCESS, SPR_NOACCESS,
6655 &spr_read_generic, &spr_write_generic,
6656 POWERPC970_HID5_INIT);
6657 /* XXX : not implemented */
6658 spr_register(env, SPR_L2CR, "L2CR",
6659 SPR_NOACCESS, SPR_NOACCESS,
6660 &spr_read_generic, &spr_write_generic,
6661 0x00000000);
6662 /* Memory management */
6663 /* XXX: not correct */
6664 gen_low_BATs(env);
6665 /* XXX : not implemented */
6666 spr_register(env, SPR_MMUCFG, "MMUCFG",
6667 SPR_NOACCESS, SPR_NOACCESS,
6668 &spr_read_generic, SPR_NOACCESS,
6669 0x00000000); /* TOFIX */
6670 /* XXX : not implemented */
6671 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6672 SPR_NOACCESS, SPR_NOACCESS,
6673 &spr_read_generic, &spr_write_generic,
6674 0x00000000); /* TOFIX */
6675 spr_register(env, SPR_HIOR, "SPR_HIOR",
6676 SPR_NOACCESS, SPR_NOACCESS,
6677 &spr_read_hior, &spr_write_hior,
6678 0x00000000);
6679 #if !defined(CONFIG_USER_ONLY)
6680 env->slb_nr = 32;
6681 #endif
6682 init_excp_970(env);
6683 env->dcache_line_size = 128;
6684 env->icache_line_size = 128;
6685 /* Allocate hardware IRQ controller */
6686 ppc970_irq_init(env);
6687 /* Can't find information on what this should be on reset. This
6688 * value is the one used by 74xx processors. */
6689 vscr_init(env, 0x00010000);
6690 }
6691
6692 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
6693 {
6694 DeviceClass *dc = DEVICE_CLASS(oc);
6695 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6696
6697 dc->desc = "PowerPC 970";
6698 pcc->init_proc = init_proc_970;
6699 pcc->check_pow = check_pow_970;
6700 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6701 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6702 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6703 PPC_FLOAT_STFIWX |
6704 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6705 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6706 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6707 PPC_64B | PPC_ALTIVEC |
6708 PPC_SEGMENT_64B | PPC_SLBI;
6709 pcc->insns_flags2 = PPC_NONE;
6710 pcc->msr_mask = 0x900000000204FF36ULL;
6711 pcc->mmu_model = POWERPC_MMU_64B;
6712 pcc->excp_model = POWERPC_EXCP_970;
6713 pcc->bus_model = PPC_FLAGS_INPUT_970;
6714 pcc->bfd_mach = bfd_mach_ppc64;
6715 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6716 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6717 POWERPC_FLAG_BUS_CLK;
6718 }
6719
6720 static int check_pow_970FX (CPUPPCState *env)
6721 {
6722 if (env->spr[SPR_HID0] & 0x00600000)
6723 return 1;
6724
6725 return 0;
6726 }
6727
6728 static void init_proc_970FX (CPUPPCState *env)
6729 {
6730 gen_spr_ne_601(env);
6731 gen_spr_7xx(env);
6732 /* Time base */
6733 gen_tbl(env);
6734 /* Hardware implementation registers */
6735 /* XXX : not implemented */
6736 spr_register(env, SPR_HID0, "HID0",
6737 SPR_NOACCESS, SPR_NOACCESS,
6738 &spr_read_generic, &spr_write_clear,
6739 0x60000000);
6740 /* XXX : not implemented */
6741 spr_register(env, SPR_HID1, "HID1",
6742 SPR_NOACCESS, SPR_NOACCESS,
6743 &spr_read_generic, &spr_write_generic,
6744 0x00000000);
6745 /* XXX : not implemented */
6746 spr_register(env, SPR_750FX_HID2, "HID2",
6747 SPR_NOACCESS, SPR_NOACCESS,
6748 &spr_read_generic, &spr_write_generic,
6749 0x00000000);
6750 /* XXX : not implemented */
6751 spr_register(env, SPR_970_HID5, "HID5",
6752 SPR_NOACCESS, SPR_NOACCESS,
6753 &spr_read_generic, &spr_write_generic,
6754 POWERPC970_HID5_INIT);
6755 /* XXX : not implemented */
6756 spr_register(env, SPR_L2CR, "L2CR",
6757 SPR_NOACCESS, SPR_NOACCESS,
6758 &spr_read_generic, &spr_write_generic,
6759 0x00000000);
6760 /* Memory management */
6761 /* XXX: not correct */
6762 gen_low_BATs(env);
6763 /* XXX : not implemented */
6764 spr_register(env, SPR_MMUCFG, "MMUCFG",
6765 SPR_NOACCESS, SPR_NOACCESS,
6766 &spr_read_generic, SPR_NOACCESS,
6767 0x00000000); /* TOFIX */
6768 /* XXX : not implemented */
6769 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6770 SPR_NOACCESS, SPR_NOACCESS,
6771 &spr_read_generic, &spr_write_generic,
6772 0x00000000); /* TOFIX */
6773 spr_register(env, SPR_HIOR, "SPR_HIOR",
6774 SPR_NOACCESS, SPR_NOACCESS,
6775 &spr_read_hior, &spr_write_hior,
6776 0x00000000);
6777 spr_register(env, SPR_CTRL, "SPR_CTRL",
6778 SPR_NOACCESS, SPR_NOACCESS,
6779 &spr_read_generic, &spr_write_generic,
6780 0x00000000);
6781 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6782 SPR_NOACCESS, SPR_NOACCESS,
6783 &spr_read_generic, &spr_write_generic,
6784 0x00000000);
6785 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6786 &spr_read_generic, &spr_write_generic,
6787 &spr_read_generic, &spr_write_generic,
6788 0x00000000);
6789 #if !defined(CONFIG_USER_ONLY)
6790 env->slb_nr = 64;
6791 #endif
6792 init_excp_970(env);
6793 env->dcache_line_size = 128;
6794 env->icache_line_size = 128;
6795 /* Allocate hardware IRQ controller */
6796 ppc970_irq_init(env);
6797 /* Can't find information on what this should be on reset. This
6798 * value is the one used by 74xx processors. */
6799 vscr_init(env, 0x00010000);
6800 }
6801
6802 POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
6803 {
6804 DeviceClass *dc = DEVICE_CLASS(oc);
6805 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6806
6807 dc->desc = "PowerPC 970FX (aka G5)";
6808 pcc->init_proc = init_proc_970FX;
6809 pcc->check_pow = check_pow_970FX;
6810 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6811 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6812 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6813 PPC_FLOAT_STFIWX |
6814 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6815 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6816 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6817 PPC_64B | PPC_ALTIVEC |
6818 PPC_SEGMENT_64B | PPC_SLBI;
6819 pcc->insns_flags2 = PPC_NONE;
6820 pcc->msr_mask = 0x800000000204FF36ULL;
6821 pcc->mmu_model = POWERPC_MMU_64B;
6822 pcc->excp_model = POWERPC_EXCP_970;
6823 pcc->bus_model = PPC_FLAGS_INPUT_970;
6824 pcc->bfd_mach = bfd_mach_ppc64;
6825 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6826 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6827 POWERPC_FLAG_BUS_CLK;
6828 }
6829
6830 static int check_pow_970GX (CPUPPCState *env)
6831 {
6832 if (env->spr[SPR_HID0] & 0x00600000)
6833 return 1;
6834
6835 return 0;
6836 }
6837
6838 static void init_proc_970GX (CPUPPCState *env)
6839 {
6840 gen_spr_ne_601(env);
6841 gen_spr_7xx(env);
6842 /* Time base */
6843 gen_tbl(env);
6844 /* Hardware implementation registers */
6845 /* XXX : not implemented */
6846 spr_register(env, SPR_HID0, "HID0",
6847 SPR_NOACCESS, SPR_NOACCESS,
6848 &spr_read_generic, &spr_write_clear,
6849 0x60000000);
6850 /* XXX : not implemented */
6851 spr_register(env, SPR_HID1, "HID1",
6852 SPR_NOACCESS, SPR_NOACCESS,
6853 &spr_read_generic, &spr_write_generic,
6854 0x00000000);
6855 /* XXX : not implemented */
6856 spr_register(env, SPR_750FX_HID2, "HID2",
6857 SPR_NOACCESS, SPR_NOACCESS,
6858 &spr_read_generic, &spr_write_generic,
6859 0x00000000);
6860 /* XXX : not implemented */
6861 spr_register(env, SPR_970_HID5, "HID5",
6862 SPR_NOACCESS, SPR_NOACCESS,
6863 &spr_read_generic, &spr_write_generic,
6864 POWERPC970_HID5_INIT);
6865 /* XXX : not implemented */
6866 spr_register(env, SPR_L2CR, "L2CR",
6867 SPR_NOACCESS, SPR_NOACCESS,
6868 &spr_read_generic, &spr_write_generic,
6869 0x00000000);
6870 /* Memory management */
6871 /* XXX: not correct */
6872 gen_low_BATs(env);
6873 /* XXX : not implemented */
6874 spr_register(env, SPR_MMUCFG, "MMUCFG",
6875 SPR_NOACCESS, SPR_NOACCESS,
6876 &spr_read_generic, SPR_NOACCESS,
6877 0x00000000); /* TOFIX */
6878 /* XXX : not implemented */
6879 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6880 SPR_NOACCESS, SPR_NOACCESS,
6881 &spr_read_generic, &spr_write_generic,
6882 0x00000000); /* TOFIX */
6883 spr_register(env, SPR_HIOR, "SPR_HIOR",
6884 SPR_NOACCESS, SPR_NOACCESS,
6885 &spr_read_hior, &spr_write_hior,
6886 0x00000000);
6887 #if !defined(CONFIG_USER_ONLY)
6888 env->slb_nr = 32;
6889 #endif
6890 init_excp_970(env);
6891 env->dcache_line_size = 128;
6892 env->icache_line_size = 128;
6893 /* Allocate hardware IRQ controller */
6894 ppc970_irq_init(env);
6895 /* Can't find information on what this should be on reset. This
6896 * value is the one used by 74xx processors. */
6897 vscr_init(env, 0x00010000);
6898 }
6899
6900 POWERPC_FAMILY(970GX)(ObjectClass *oc, void *data)
6901 {
6902 DeviceClass *dc = DEVICE_CLASS(oc);
6903 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6904
6905 dc->desc = "PowerPC 970 GX";
6906 pcc->init_proc = init_proc_970GX;
6907 pcc->check_pow = check_pow_970GX;
6908 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6909 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6910 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6911 PPC_FLOAT_STFIWX |
6912 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6913 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6914 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6915 PPC_64B | PPC_ALTIVEC |
6916 PPC_SEGMENT_64B | PPC_SLBI;
6917 pcc->insns_flags2 = PPC_NONE;
6918 pcc->msr_mask = 0x800000000204FF36ULL;
6919 pcc->mmu_model = POWERPC_MMU_64B;
6920 pcc->excp_model = POWERPC_EXCP_970;
6921 pcc->bus_model = PPC_FLAGS_INPUT_970;
6922 pcc->bfd_mach = bfd_mach_ppc64;
6923 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6924 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6925 POWERPC_FLAG_BUS_CLK;
6926 }
6927
6928 static int check_pow_970MP (CPUPPCState *env)
6929 {
6930 if (env->spr[SPR_HID0] & 0x01C00000)
6931 return 1;
6932
6933 return 0;
6934 }
6935
6936 static void init_proc_970MP (CPUPPCState *env)
6937 {
6938 gen_spr_ne_601(env);
6939 gen_spr_7xx(env);
6940 /* Time base */
6941 gen_tbl(env);
6942 /* Hardware implementation registers */
6943 /* XXX : not implemented */
6944 spr_register(env, SPR_HID0, "HID0",
6945 SPR_NOACCESS, SPR_NOACCESS,
6946 &spr_read_generic, &spr_write_clear,
6947 0x60000000);
6948 /* XXX : not implemented */
6949 spr_register(env, SPR_HID1, "HID1",
6950 SPR_NOACCESS, SPR_NOACCESS,
6951 &spr_read_generic, &spr_write_generic,
6952 0x00000000);
6953 /* XXX : not implemented */
6954 spr_register(env, SPR_750FX_HID2, "HID2",
6955 SPR_NOACCESS, SPR_NOACCESS,
6956 &spr_read_generic, &spr_write_generic,
6957 0x00000000);
6958 /* XXX : not implemented */
6959 spr_register(env, SPR_970_HID5, "HID5",
6960 SPR_NOACCESS, SPR_NOACCESS,
6961 &spr_read_generic, &spr_write_generic,
6962 POWERPC970_HID5_INIT);
6963 /* XXX : not implemented */
6964 spr_register(env, SPR_L2CR, "L2CR",
6965 SPR_NOACCESS, SPR_NOACCESS,
6966 &spr_read_generic, &spr_write_generic,
6967 0x00000000);
6968 /* Memory management */
6969 /* XXX: not correct */
6970 gen_low_BATs(env);
6971 /* XXX : not implemented */
6972 spr_register(env, SPR_MMUCFG, "MMUCFG",
6973 SPR_NOACCESS, SPR_NOACCESS,
6974 &spr_read_generic, SPR_NOACCESS,
6975 0x00000000); /* TOFIX */
6976 /* XXX : not implemented */
6977 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6978 SPR_NOACCESS, SPR_NOACCESS,
6979 &spr_read_generic, &spr_write_generic,
6980 0x00000000); /* TOFIX */
6981 spr_register(env, SPR_HIOR, "SPR_HIOR",
6982 SPR_NOACCESS, SPR_NOACCESS,
6983 &spr_read_hior, &spr_write_hior,
6984 0x00000000);
6985 #if !defined(CONFIG_USER_ONLY)
6986 env->slb_nr = 32;
6987 #endif
6988 init_excp_970(env);
6989 env->dcache_line_size = 128;
6990 env->icache_line_size = 128;
6991 /* Allocate hardware IRQ controller */
6992 ppc970_irq_init(env);
6993 /* Can't find information on what this should be on reset. This
6994 * value is the one used by 74xx processors. */
6995 vscr_init(env, 0x00010000);
6996 }
6997
6998 POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
6999 {
7000 DeviceClass *dc = DEVICE_CLASS(oc);
7001 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7002
7003 dc->desc = "PowerPC 970 MP";
7004 pcc->init_proc = init_proc_970MP;
7005 pcc->check_pow = check_pow_970MP;
7006 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7007 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7008 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7009 PPC_FLOAT_STFIWX |
7010 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7011 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7012 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7013 PPC_64B | PPC_ALTIVEC |
7014 PPC_SEGMENT_64B | PPC_SLBI;
7015 pcc->insns_flags2 = PPC_NONE;
7016 pcc->msr_mask = 0x900000000204FF36ULL;
7017 pcc->mmu_model = POWERPC_MMU_64B;
7018 pcc->excp_model = POWERPC_EXCP_970;
7019 pcc->bus_model = PPC_FLAGS_INPUT_970;
7020 pcc->bfd_mach = bfd_mach_ppc64;
7021 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7022 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7023 POWERPC_FLAG_BUS_CLK;
7024 }
7025
7026 static void init_proc_POWER7 (CPUPPCState *env)
7027 {
7028 gen_spr_ne_601(env);
7029 gen_spr_7xx(env);
7030 /* Time base */
7031 gen_tbl(env);
7032 /* Processor identification */
7033 spr_register(env, SPR_PIR, "PIR",
7034 SPR_NOACCESS, SPR_NOACCESS,
7035 &spr_read_generic, &spr_write_pir,
7036 0x00000000);
7037 #if !defined(CONFIG_USER_ONLY)
7038 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
7039 spr_register(env, SPR_PURR, "PURR",
7040 &spr_read_purr, SPR_NOACCESS,
7041 &spr_read_purr, SPR_NOACCESS,
7042 0x00000000);
7043 spr_register(env, SPR_SPURR, "SPURR",
7044 &spr_read_purr, SPR_NOACCESS,
7045 &spr_read_purr, SPR_NOACCESS,
7046 0x00000000);
7047 spr_register(env, SPR_CFAR, "SPR_CFAR",
7048 SPR_NOACCESS, SPR_NOACCESS,
7049 &spr_read_cfar, &spr_write_cfar,
7050 0x00000000);
7051 spr_register(env, SPR_DSCR, "SPR_DSCR",
7052 SPR_NOACCESS, SPR_NOACCESS,
7053 &spr_read_generic, &spr_write_generic,
7054 0x00000000);
7055 #endif /* !CONFIG_USER_ONLY */
7056 /* Memory management */
7057 /* XXX : not implemented */
7058 spr_register(env, SPR_MMUCFG, "MMUCFG",
7059 SPR_NOACCESS, SPR_NOACCESS,
7060 &spr_read_generic, SPR_NOACCESS,
7061 0x00000000); /* TOFIX */
7062 /* XXX : not implemented */
7063 spr_register(env, SPR_CTRL, "SPR_CTRLT",
7064 SPR_NOACCESS, SPR_NOACCESS,
7065 &spr_read_generic, &spr_write_generic,
7066 0x80800000);
7067 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
7068 SPR_NOACCESS, SPR_NOACCESS,
7069 &spr_read_generic, &spr_write_generic,
7070 0x80800000);
7071 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
7072 &spr_read_generic, &spr_write_generic,
7073 &spr_read_generic, &spr_write_generic,
7074 0x00000000);
7075 #if !defined(CONFIG_USER_ONLY)
7076 env->slb_nr = 32;
7077 #endif
7078 init_excp_POWER7(env);
7079 env->dcache_line_size = 128;
7080 env->icache_line_size = 128;
7081 /* Allocate hardware IRQ controller */
7082 ppcPOWER7_irq_init(env);
7083 /* Can't find information on what this should be on reset. This
7084 * value is the one used by 74xx processors. */
7085 vscr_init(env, 0x00010000);
7086 }
7087
7088 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
7089 {
7090 DeviceClass *dc = DEVICE_CLASS(oc);
7091 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7092
7093 dc->desc = "POWER7";
7094 pcc->init_proc = init_proc_POWER7;
7095 pcc->check_pow = check_pow_nocheck;
7096 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7097 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7098 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7099 PPC_FLOAT_STFIWX |
7100 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7101 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7102 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7103 PPC_64B | PPC_ALTIVEC |
7104 PPC_SEGMENT_64B | PPC_SLBI |
7105 PPC_POPCNTB | PPC_POPCNTWD;
7106 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX;
7107 pcc->msr_mask = 0x800000000204FF36ULL;
7108 pcc->mmu_model = POWERPC_MMU_2_06;
7109 pcc->excp_model = POWERPC_EXCP_POWER7;
7110 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7111 pcc->bfd_mach = bfd_mach_ppc64;
7112 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7113 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7114 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR;
7115 }
7116
7117 static void init_proc_620 (CPUPPCState *env)
7118 {
7119 gen_spr_ne_601(env);
7120 gen_spr_620(env);
7121 /* Time base */
7122 gen_tbl(env);
7123 /* Hardware implementation registers */
7124 /* XXX : not implemented */
7125 spr_register(env, SPR_HID0, "HID0",
7126 SPR_NOACCESS, SPR_NOACCESS,
7127 &spr_read_generic, &spr_write_generic,
7128 0x00000000);
7129 /* Memory management */
7130 gen_low_BATs(env);
7131 init_excp_620(env);
7132 env->dcache_line_size = 64;
7133 env->icache_line_size = 64;
7134 /* Allocate hardware IRQ controller */
7135 ppc6xx_irq_init(env);
7136 }
7137
7138 POWERPC_FAMILY(620)(ObjectClass *oc, void *data)
7139 {
7140 DeviceClass *dc = DEVICE_CLASS(oc);
7141 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7142
7143 dc->desc = "PowerPC 620";
7144 pcc->init_proc = init_proc_620;
7145 pcc->check_pow = check_pow_nocheck; /* Check this */
7146 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7147 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7148 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7149 PPC_FLOAT_STFIWX |
7150 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7151 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7152 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7153 PPC_SEGMENT | PPC_EXTERN |
7154 PPC_64B | PPC_SLBI;
7155 pcc->insns_flags2 = PPC_NONE;
7156 pcc->msr_mask = 0x800000000005FF77ULL;
7157 pcc->mmu_model = POWERPC_MMU_620;
7158 pcc->excp_model = POWERPC_EXCP_970;
7159 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7160 pcc->bfd_mach = bfd_mach_ppc64;
7161 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
7162 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7163 }
7164
7165 #endif /* defined (TARGET_PPC64) */
7166
7167
7168 typedef struct PowerPCCPUAlias {
7169 const char *alias;
7170 const char *model;
7171 } PowerPCCPUAlias;
7172
7173 static const PowerPCCPUAlias ppc_cpu_aliases[] = {
7174 { "403", "403GC" },
7175 { "405", "405D4" },
7176 { "405CR", "405CRc" },
7177 { "405GP", "405GPd" },
7178 { "405GPe", "405CRc" },
7179 { "x2vp7", "x2vp4" },
7180 { "x2vp50", "x2vp20" },
7181
7182 { "440EP", "440EPb" },
7183 { "440GP", "440GPc" },
7184 { "440GR", "440GRa" },
7185 { "440GX", "440GXf" },
7186
7187 { "RCPU", "MPC5xx" },
7188 /* MPC5xx microcontrollers */
7189 { "MGT560", "MPC5xx" },
7190 { "MPC509", "MPC5xx" },
7191 { "MPC533", "MPC5xx" },
7192 { "MPC534", "MPC5xx" },
7193 { "MPC555", "MPC5xx" },
7194 { "MPC556", "MPC5xx" },
7195 { "MPC560", "MPC5xx" },
7196 { "MPC561", "MPC5xx" },
7197 { "MPC562", "MPC5xx" },
7198 { "MPC563", "MPC5xx" },
7199 { "MPC564", "MPC5xx" },
7200 { "MPC565", "MPC5xx" },
7201 { "MPC566", "MPC5xx" },
7202
7203 { "PowerQUICC", "MPC8xx" },
7204 /* MPC8xx microcontrollers */
7205 { "MGT823", "MPC8xx" },
7206 { "MPC821", "MPC8xx" },
7207 { "MPC823", "MPC8xx" },
7208 { "MPC850", "MPC8xx" },
7209 { "MPC852T", "MPC8xx" },
7210 { "MPC855T", "MPC8xx" },
7211 { "MPC857", "MPC8xx" },
7212 { "MPC859", "MPC8xx" },
7213 { "MPC860", "MPC8xx" },
7214 { "MPC862", "MPC8xx" },
7215 { "MPC866", "MPC8xx" },
7216 { "MPC870", "MPC8xx" },
7217 { "MPC875", "MPC8xx" },
7218 { "MPC880", "MPC8xx" },
7219 { "MPC885", "MPC8xx" },
7220
7221 /* PowerPC MPC603 microcontrollers */
7222 { "MPC8240", "603" },
7223
7224 { "MPC52xx", "MPC5200" },
7225 { "MPC5200", "MPC5200_v12" },
7226 { "MPC5200B", "MPC5200B_v21" },
7227
7228 { "MPC82xx", "MPC8280" },
7229 { "PowerQUICC-II", "MPC82xx" },
7230 { "MPC8241", "G2HiP4" },
7231 { "MPC8245", "G2HiP4" },
7232 { "MPC8247", "G2leGP3" },
7233 { "MPC8248", "G2leGP3" },
7234 { "MPC8250", "MPC8250_HiP4" },
7235 { "MPC8250_HiP3", "G2HiP3" },
7236 { "MPC8250_HiP4", "G2HiP4" },
7237 { "MPC8255", "MPC8255_HiP4" },
7238 { "MPC8255_HiP3", "G2HiP3" },
7239 { "MPC8255_HiP4", "G2HiP4" },
7240 { "MPC8260", "MPC8260_HiP4" },
7241 { "MPC8260_HiP3", "G2HiP3" },
7242 { "MPC8260_HiP4", "G2HiP4" },
7243 { "MPC8264", "MPC8264_HiP4" },
7244 { "MPC8264_HiP3", "G2HiP3" },
7245 { "MPC8264_HiP4", "G2HiP4" },
7246 { "MPC8265", "MPC8265_HiP4" },
7247 { "MPC8265_HiP3", "G2HiP3" },
7248 { "MPC8265_HiP4", "G2HiP4" },
7249 { "MPC8266", "MPC8266_HiP4" },
7250 { "MPC8266_HiP3", "G2HiP3" },
7251 { "MPC8266_HiP4", "G2HiP4" },
7252 { "MPC8270", "G2leGP3" },
7253 { "MPC8271", "G2leGP3" },
7254 { "MPC8272", "G2leGP3" },
7255 { "MPC8275", "G2leGP3" },
7256 { "MPC8280", "G2leGP3" },
7257 { "e200", "e200z6" },
7258 { "e300", "e300c3" },
7259 { "MPC8347", "MPC8347T" },
7260 { "MPC8347A", "MPC8347AT" },
7261 { "MPC8347E", "MPC8347ET" },
7262 { "MPC8347EA", "MPC8347EAT" },
7263 { "e500", "e500v2_v22" },
7264 { "e500v1", "e500_v20" },
7265 { "e500v2", "e500v2_v22" },
7266 { "MPC8533", "MPC8533_v11" },
7267 { "MPC8533E", "MPC8533E_v11" },
7268 { "MPC8540", "MPC8540_v21" },
7269 { "MPC8541", "MPC8541_v11" },
7270 { "MPC8541E", "MPC8541E_v11" },
7271 { "MPC8543", "MPC8543_v21" },
7272 { "MPC8543E", "MPC8543E_v21" },
7273 { "MPC8544", "MPC8544_v11" },
7274 { "MPC8544E", "MPC8544E_v11" },
7275 { "MPC8545", "MPC8545_v21" },
7276 { "MPC8545E", "MPC8545E_v21" },
7277 { "MPC8547E", "MPC8547E_v21" },
7278 { "MPC8548", "MPC8548_v21" },
7279 { "MPC8548E", "MPC8548E_v21" },
7280 { "MPC8555", "MPC8555_v11" },
7281 { "MPC8555E", "MPC8555E_v11" },
7282 { "MPC8560", "MPC8560_v21" },
7283 { "601", "601_v2" },
7284 { "601v", "601_v2" },
7285 { "Vanilla", "603" },
7286 { "603e", "603e_v4.1" },
7287 { "Stretch", "603e" },
7288 { "Vaillant", "603e7v" },
7289 { "603r", "603e7t" },
7290 { "Goldeneye", "603r" },
7291 { "604e", "604e_v2.4" },
7292 { "Sirocco", "604e" },
7293 { "Mach5", "604r" },
7294 { "740", "740_v3.1" },
7295 { "Arthur", "740" },
7296 { "750", "750_v3.1" },
7297 { "Typhoon", "750" },
7298 { "G3", "750" },
7299 { "Conan/Doyle", "750p" },
7300 { "750cl", "750cl_v2.0" },
7301 { "750cx", "750cx_v2.2" },
7302 { "750cxe", "750cxe_v3.1b" },
7303 { "750fx", "750fx_v2.3" },
7304 { "750gx", "750gx_v1.2" },
7305 { "750l", "750l_v3.2" },
7306 { "LoneStar", "750l" },
7307 { "745", "745_v2.8" },
7308 { "755", "755_v2.8" },
7309 { "Goldfinger", "755" },
7310 { "7400", "7400_v2.9" },
7311 { "Max", "7400" },
7312 { "G4", "7400" },
7313 { "7410", "7410_v1.4" },
7314 { "Nitro", "7410" },
7315 { "7448", "7448_v2.1" },
7316 { "7450", "7450_v2.1" },
7317 { "Vger", "7450" },
7318 { "7441", "7441_v2.3" },
7319 { "7451", "7451_v2.3" },
7320 { "7445", "7445_v3.2" },
7321 { "7455", "7455_v3.2" },
7322 { "Apollo6", "7455" },
7323 { "7447", "7447_v1.2" },
7324 { "7457", "7457_v1.2" },
7325 { "Apollo7", "7457" },
7326 { "7447A", "7447A_v1.2" },
7327 { "7457A", "7457A_v1.2" },
7328 { "Apollo7PM", "7457A_v1.0" },
7329 #if defined(TARGET_PPC64)
7330 { "Trident", "620" },
7331 { "POWER3", "630" },
7332 { "Boxer", "POWER3" },
7333 { "Dino", "POWER3" },
7334 { "POWER3+", "631" },
7335 { "POWER7", "POWER7_v2.0" },
7336 { "970fx", "970fx_v3.1" },
7337 { "970mp", "970mp_v1.1" },
7338 { "Apache", "RS64" },
7339 { "A35", "RS64" },
7340 { "NorthStar", "RS64-II" },
7341 { "A50", "RS64-II" },
7342 { "Pulsar", "RS64-III" },
7343 { "IceStar", "RS64-IV" },
7344 { "IStar", "RS64-IV" },
7345 { "SStar", "RS64-IV" },
7346 #endif
7347 { "RIOS", "POWER" },
7348 { "RSC", "POWER" },
7349 { "RSC3308", "POWER" },
7350 { "RSC4608", "POWER" },
7351 { "RSC2", "POWER2" },
7352 { "P2SC", "POWER2" },
7353
7354 /* Generic PowerPCs */
7355 #if defined(TARGET_PPC64)
7356 { "ppc64", "970fx" },
7357 #endif
7358 { "ppc32", "604" },
7359 { "ppc", "ppc32" },
7360 { "default", "ppc" },
7361 };
7362
7363 /*****************************************************************************/
7364 /* Generic CPU instantiation routine */
7365 static void init_ppc_proc(PowerPCCPU *cpu)
7366 {
7367 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7368 CPUPPCState *env = &cpu->env;
7369 #if !defined(CONFIG_USER_ONLY)
7370 int i;
7371
7372 env->irq_inputs = NULL;
7373 /* Set all exception vectors to an invalid address */
7374 for (i = 0; i < POWERPC_EXCP_NB; i++)
7375 env->excp_vectors[i] = (target_ulong)(-1ULL);
7376 env->hreset_excp_prefix = 0x00000000;
7377 env->ivor_mask = 0x00000000;
7378 env->ivpr_mask = 0x00000000;
7379 /* Default MMU definitions */
7380 env->nb_BATs = 0;
7381 env->nb_tlb = 0;
7382 env->nb_ways = 0;
7383 env->tlb_type = TLB_NONE;
7384 #endif
7385 /* Register SPR common to all PowerPC implementations */
7386 gen_spr_generic(env);
7387 spr_register(env, SPR_PVR, "PVR",
7388 /* Linux permits userspace to read PVR */
7389 #if defined(CONFIG_LINUX_USER)
7390 &spr_read_generic,
7391 #else
7392 SPR_NOACCESS,
7393 #endif
7394 SPR_NOACCESS,
7395 &spr_read_generic, SPR_NOACCESS,
7396 pcc->pvr);
7397 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
7398 if (pcc->svr != POWERPC_SVR_NONE) {
7399 if (pcc->svr & POWERPC_SVR_E500) {
7400 spr_register(env, SPR_E500_SVR, "SVR",
7401 SPR_NOACCESS, SPR_NOACCESS,
7402 &spr_read_generic, SPR_NOACCESS,
7403 pcc->svr & ~POWERPC_SVR_E500);
7404 } else {
7405 spr_register(env, SPR_SVR, "SVR",
7406 SPR_NOACCESS, SPR_NOACCESS,
7407 &spr_read_generic, SPR_NOACCESS,
7408 pcc->svr);
7409 }
7410 }
7411 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
7412 (*pcc->init_proc)(env);
7413 #if !defined(CONFIG_USER_ONLY)
7414 env->excp_prefix = env->hreset_excp_prefix;
7415 #endif
7416 /* MSR bits & flags consistency checks */
7417 if (env->msr_mask & (1 << 25)) {
7418 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7419 case POWERPC_FLAG_SPE:
7420 case POWERPC_FLAG_VRE:
7421 break;
7422 default:
7423 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7424 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
7425 exit(1);
7426 }
7427 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7428 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7429 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
7430 exit(1);
7431 }
7432 if (env->msr_mask & (1 << 17)) {
7433 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7434 case POWERPC_FLAG_TGPR:
7435 case POWERPC_FLAG_CE:
7436 break;
7437 default:
7438 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7439 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
7440 exit(1);
7441 }
7442 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7443 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7444 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
7445 exit(1);
7446 }
7447 if (env->msr_mask & (1 << 10)) {
7448 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7449 POWERPC_FLAG_UBLE)) {
7450 case POWERPC_FLAG_SE:
7451 case POWERPC_FLAG_DWE:
7452 case POWERPC_FLAG_UBLE:
7453 break;
7454 default:
7455 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7456 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
7457 "POWERPC_FLAG_UBLE\n");
7458 exit(1);
7459 }
7460 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7461 POWERPC_FLAG_UBLE)) {
7462 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7463 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
7464 "POWERPC_FLAG_UBLE\n");
7465 exit(1);
7466 }
7467 if (env->msr_mask & (1 << 9)) {
7468 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7469 case POWERPC_FLAG_BE:
7470 case POWERPC_FLAG_DE:
7471 break;
7472 default:
7473 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7474 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
7475 exit(1);
7476 }
7477 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7478 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7479 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
7480 exit(1);
7481 }
7482 if (env->msr_mask & (1 << 2)) {
7483 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7484 case POWERPC_FLAG_PX:
7485 case POWERPC_FLAG_PMM:
7486 break;
7487 default:
7488 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7489 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
7490 exit(1);
7491 }
7492 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7493 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7494 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
7495 exit(1);
7496 }
7497 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
7498 fprintf(stderr, "PowerPC flags inconsistency\n"
7499 "Should define the time-base and decrementer clock source\n");
7500 exit(1);
7501 }
7502 /* Allocate TLBs buffer when needed */
7503 #if !defined(CONFIG_USER_ONLY)
7504 if (env->nb_tlb != 0) {
7505 int nb_tlb = env->nb_tlb;
7506 if (env->id_tlbs != 0)
7507 nb_tlb *= 2;
7508 switch (env->tlb_type) {
7509 case TLB_6XX:
7510 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
7511 break;
7512 case TLB_EMB:
7513 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
7514 break;
7515 case TLB_MAS:
7516 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
7517 break;
7518 }
7519 /* Pre-compute some useful values */
7520 env->tlb_per_way = env->nb_tlb / env->nb_ways;
7521 }
7522 if (env->irq_inputs == NULL) {
7523 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
7524 " Attempt QEMU to crash very soon !\n");
7525 }
7526 #endif
7527 if (env->check_pow == NULL) {
7528 fprintf(stderr, "WARNING: no power management check handler "
7529 "registered.\n"
7530 " Attempt QEMU to crash very soon !\n");
7531 }
7532 }
7533
7534 #if defined(PPC_DUMP_CPU)
7535 static void dump_ppc_sprs (CPUPPCState *env)
7536 {
7537 ppc_spr_t *spr;
7538 #if !defined(CONFIG_USER_ONLY)
7539 uint32_t sr, sw;
7540 #endif
7541 uint32_t ur, uw;
7542 int i, j, n;
7543
7544 printf("Special purpose registers:\n");
7545 for (i = 0; i < 32; i++) {
7546 for (j = 0; j < 32; j++) {
7547 n = (i << 5) | j;
7548 spr = &env->spr_cb[n];
7549 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
7550 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
7551 #if !defined(CONFIG_USER_ONLY)
7552 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
7553 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
7554 if (sw || sr || uw || ur) {
7555 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
7556 (i << 5) | j, (i << 5) | j, spr->name,
7557 sw ? 'w' : '-', sr ? 'r' : '-',
7558 uw ? 'w' : '-', ur ? 'r' : '-');
7559 }
7560 #else
7561 if (uw || ur) {
7562 printf("SPR: %4d (%03x) %-8s u%c%c\n",
7563 (i << 5) | j, (i << 5) | j, spr->name,
7564 uw ? 'w' : '-', ur ? 'r' : '-');
7565 }
7566 #endif
7567 }
7568 }
7569 fflush(stdout);
7570 fflush(stderr);
7571 }
7572 #endif
7573
7574 /*****************************************************************************/
7575 #include <stdlib.h>
7576 #include <string.h>
7577
7578 /* Opcode types */
7579 enum {
7580 PPC_DIRECT = 0, /* Opcode routine */
7581 PPC_INDIRECT = 1, /* Indirect opcode table */
7582 };
7583
7584 static inline int is_indirect_opcode (void *handler)
7585 {
7586 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
7587 }
7588
7589 static inline opc_handler_t **ind_table(void *handler)
7590 {
7591 return (opc_handler_t **)((uintptr_t)handler & ~3);
7592 }
7593
7594 /* Instruction table creation */
7595 /* Opcodes tables creation */
7596 static void fill_new_table (opc_handler_t **table, int len)
7597 {
7598 int i;
7599
7600 for (i = 0; i < len; i++)
7601 table[i] = &invalid_handler;
7602 }
7603
7604 static int create_new_table (opc_handler_t **table, unsigned char idx)
7605 {
7606 opc_handler_t **tmp;
7607
7608 tmp = malloc(0x20 * sizeof(opc_handler_t));
7609 fill_new_table(tmp, 0x20);
7610 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
7611
7612 return 0;
7613 }
7614
7615 static int insert_in_table (opc_handler_t **table, unsigned char idx,
7616 opc_handler_t *handler)
7617 {
7618 if (table[idx] != &invalid_handler)
7619 return -1;
7620 table[idx] = handler;
7621
7622 return 0;
7623 }
7624
7625 static int register_direct_insn (opc_handler_t **ppc_opcodes,
7626 unsigned char idx, opc_handler_t *handler)
7627 {
7628 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
7629 printf("*** ERROR: opcode %02x already assigned in main "
7630 "opcode table\n", idx);
7631 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7632 printf(" Registered handler '%s' - new handler '%s'\n",
7633 ppc_opcodes[idx]->oname, handler->oname);
7634 #endif
7635 return -1;
7636 }
7637
7638 return 0;
7639 }
7640
7641 static int register_ind_in_table (opc_handler_t **table,
7642 unsigned char idx1, unsigned char idx2,
7643 opc_handler_t *handler)
7644 {
7645 if (table[idx1] == &invalid_handler) {
7646 if (create_new_table(table, idx1) < 0) {
7647 printf("*** ERROR: unable to create indirect table "
7648 "idx=%02x\n", idx1);
7649 return -1;
7650 }
7651 } else {
7652 if (!is_indirect_opcode(table[idx1])) {
7653 printf("*** ERROR: idx %02x already assigned to a direct "
7654 "opcode\n", idx1);
7655 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7656 printf(" Registered handler '%s' - new handler '%s'\n",
7657 ind_table(table[idx1])[idx2]->oname, handler->oname);
7658 #endif
7659 return -1;
7660 }
7661 }
7662 if (handler != NULL &&
7663 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
7664 printf("*** ERROR: opcode %02x already assigned in "
7665 "opcode table %02x\n", idx2, idx1);
7666 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7667 printf(" Registered handler '%s' - new handler '%s'\n",
7668 ind_table(table[idx1])[idx2]->oname, handler->oname);
7669 #endif
7670 return -1;
7671 }
7672
7673 return 0;
7674 }
7675
7676 static int register_ind_insn (opc_handler_t **ppc_opcodes,
7677 unsigned char idx1, unsigned char idx2,
7678 opc_handler_t *handler)
7679 {
7680 int ret;
7681
7682 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
7683
7684 return ret;
7685 }
7686
7687 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
7688 unsigned char idx1, unsigned char idx2,
7689 unsigned char idx3, opc_handler_t *handler)
7690 {
7691 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
7692 printf("*** ERROR: unable to join indirect table idx "
7693 "[%02x-%02x]\n", idx1, idx2);
7694 return -1;
7695 }
7696 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
7697 handler) < 0) {
7698 printf("*** ERROR: unable to insert opcode "
7699 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
7700 return -1;
7701 }
7702
7703 return 0;
7704 }
7705
7706 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
7707 {
7708 if (insn->opc2 != 0xFF) {
7709 if (insn->opc3 != 0xFF) {
7710 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
7711 insn->opc3, &insn->handler) < 0)
7712 return -1;
7713 } else {
7714 if (register_ind_insn(ppc_opcodes, insn->opc1,
7715 insn->opc2, &insn->handler) < 0)
7716 return -1;
7717 }
7718 } else {
7719 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
7720 return -1;
7721 }
7722
7723 return 0;
7724 }
7725
7726 static int test_opcode_table (opc_handler_t **table, int len)
7727 {
7728 int i, count, tmp;
7729
7730 for (i = 0, count = 0; i < len; i++) {
7731 /* Consistency fixup */
7732 if (table[i] == NULL)
7733 table[i] = &invalid_handler;
7734 if (table[i] != &invalid_handler) {
7735 if (is_indirect_opcode(table[i])) {
7736 tmp = test_opcode_table(ind_table(table[i]), 0x20);
7737 if (tmp == 0) {
7738 free(table[i]);
7739 table[i] = &invalid_handler;
7740 } else {
7741 count++;
7742 }
7743 } else {
7744 count++;
7745 }
7746 }
7747 }
7748
7749 return count;
7750 }
7751
7752 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
7753 {
7754 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
7755 printf("*** WARNING: no opcode defined !\n");
7756 }
7757
7758 /*****************************************************************************/
7759 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
7760 {
7761 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7762 CPUPPCState *env = &cpu->env;
7763 opcode_t *opc;
7764
7765 fill_new_table(env->opcodes, 0x40);
7766 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
7767 if (((opc->handler.type & pcc->insns_flags) != 0) ||
7768 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
7769 if (register_insn(env->opcodes, opc) < 0) {
7770 error_setg(errp, "ERROR initializing PowerPC instruction "
7771 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
7772 opc->opc3);
7773 return;
7774 }
7775 }
7776 }
7777 fix_opcode_tables(env->opcodes);
7778 fflush(stdout);
7779 fflush(stderr);
7780 }
7781
7782 #if defined(PPC_DUMP_CPU)
7783 static void dump_ppc_insns (CPUPPCState *env)
7784 {
7785 opc_handler_t **table, *handler;
7786 const char *p, *q;
7787 uint8_t opc1, opc2, opc3;
7788
7789 printf("Instructions set:\n");
7790 /* opc1 is 6 bits long */
7791 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
7792 table = env->opcodes;
7793 handler = table[opc1];
7794 if (is_indirect_opcode(handler)) {
7795 /* opc2 is 5 bits long */
7796 for (opc2 = 0; opc2 < 0x20; opc2++) {
7797 table = env->opcodes;
7798 handler = env->opcodes[opc1];
7799 table = ind_table(handler);
7800 handler = table[opc2];
7801 if (is_indirect_opcode(handler)) {
7802 table = ind_table(handler);
7803 /* opc3 is 5 bits long */
7804 for (opc3 = 0; opc3 < 0x20; opc3++) {
7805 handler = table[opc3];
7806 if (handler->handler != &gen_invalid) {
7807 /* Special hack to properly dump SPE insns */
7808 p = strchr(handler->oname, '_');
7809 if (p == NULL) {
7810 printf("INSN: %02x %02x %02x (%02d %04d) : "
7811 "%s\n",
7812 opc1, opc2, opc3, opc1,
7813 (opc3 << 5) | opc2,
7814 handler->oname);
7815 } else {
7816 q = "speundef";
7817 if ((p - handler->oname) != strlen(q) ||
7818 memcmp(handler->oname, q, strlen(q)) != 0) {
7819 /* First instruction */
7820 printf("INSN: %02x %02x %02x (%02d %04d) : "
7821 "%.*s\n",
7822 opc1, opc2 << 1, opc3, opc1,
7823 (opc3 << 6) | (opc2 << 1),
7824 (int)(p - handler->oname),
7825 handler->oname);
7826 }
7827 if (strcmp(p + 1, q) != 0) {
7828 /* Second instruction */
7829 printf("INSN: %02x %02x %02x (%02d %04d) : "
7830 "%s\n",
7831 opc1, (opc2 << 1) | 1, opc3, opc1,
7832 (opc3 << 6) | (opc2 << 1) | 1,
7833 p + 1);
7834 }
7835 }
7836 }
7837 }
7838 } else {
7839 if (handler->handler != &gen_invalid) {
7840 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
7841 opc1, opc2, opc1, opc2, handler->oname);
7842 }
7843 }
7844 }
7845 } else {
7846 if (handler->handler != &gen_invalid) {
7847 printf("INSN: %02x -- -- (%02d ----) : %s\n",
7848 opc1, opc1, handler->oname);
7849 }
7850 }
7851 }
7852 }
7853 #endif
7854
7855 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7856 {
7857 if (n < 32) {
7858 stfq_p(mem_buf, env->fpr[n]);
7859 return 8;
7860 }
7861 if (n == 32) {
7862 stl_p(mem_buf, env->fpscr);
7863 return 4;
7864 }
7865 return 0;
7866 }
7867
7868 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7869 {
7870 if (n < 32) {
7871 env->fpr[n] = ldfq_p(mem_buf);
7872 return 8;
7873 }
7874 if (n == 32) {
7875 /* FPSCR not implemented */
7876 return 4;
7877 }
7878 return 0;
7879 }
7880
7881 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7882 {
7883 if (n < 32) {
7884 #ifdef HOST_WORDS_BIGENDIAN
7885 stq_p(mem_buf, env->avr[n].u64[0]);
7886 stq_p(mem_buf+8, env->avr[n].u64[1]);
7887 #else
7888 stq_p(mem_buf, env->avr[n].u64[1]);
7889 stq_p(mem_buf+8, env->avr[n].u64[0]);
7890 #endif
7891 return 16;
7892 }
7893 if (n == 32) {
7894 stl_p(mem_buf, env->vscr);
7895 return 4;
7896 }
7897 if (n == 33) {
7898 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
7899 return 4;
7900 }
7901 return 0;
7902 }
7903
7904 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7905 {
7906 if (n < 32) {
7907 #ifdef HOST_WORDS_BIGENDIAN
7908 env->avr[n].u64[0] = ldq_p(mem_buf);
7909 env->avr[n].u64[1] = ldq_p(mem_buf+8);
7910 #else
7911 env->avr[n].u64[1] = ldq_p(mem_buf);
7912 env->avr[n].u64[0] = ldq_p(mem_buf+8);
7913 #endif
7914 return 16;
7915 }
7916 if (n == 32) {
7917 env->vscr = ldl_p(mem_buf);
7918 return 4;
7919 }
7920 if (n == 33) {
7921 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
7922 return 4;
7923 }
7924 return 0;
7925 }
7926
7927 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7928 {
7929 if (n < 32) {
7930 #if defined(TARGET_PPC64)
7931 stl_p(mem_buf, env->gpr[n] >> 32);
7932 #else
7933 stl_p(mem_buf, env->gprh[n]);
7934 #endif
7935 return 4;
7936 }
7937 if (n == 32) {
7938 stq_p(mem_buf, env->spe_acc);
7939 return 8;
7940 }
7941 if (n == 33) {
7942 stl_p(mem_buf, env->spe_fscr);
7943 return 4;
7944 }
7945 return 0;
7946 }
7947
7948 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7949 {
7950 if (n < 32) {
7951 #if defined(TARGET_PPC64)
7952 target_ulong lo = (uint32_t)env->gpr[n];
7953 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
7954 env->gpr[n] = lo | hi;
7955 #else
7956 env->gprh[n] = ldl_p(mem_buf);
7957 #endif
7958 return 4;
7959 }
7960 if (n == 32) {
7961 env->spe_acc = ldq_p(mem_buf);
7962 return 8;
7963 }
7964 if (n == 33) {
7965 env->spe_fscr = ldl_p(mem_buf);
7966 return 4;
7967 }
7968 return 0;
7969 }
7970
7971 static int ppc_fixup_cpu(PowerPCCPU *cpu)
7972 {
7973 CPUPPCState *env = &cpu->env;
7974
7975 /* TCG doesn't (yet) emulate some groups of instructions that
7976 * are implemented on some otherwise supported CPUs (e.g. VSX
7977 * and decimal floating point instructions on POWER7). We
7978 * remove unsupported instruction groups from the cpu state's
7979 * instruction masks and hope the guest can cope. For at
7980 * least the pseries machine, the unavailability of these
7981 * instructions can be advertised to the guest via the device
7982 * tree. */
7983 if ((env->insns_flags & ~PPC_TCG_INSNS)
7984 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
7985 fprintf(stderr, "Warning: Disabling some instructions which are not "
7986 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
7987 env->insns_flags & ~PPC_TCG_INSNS,
7988 env->insns_flags2 & ~PPC_TCG_INSNS2);
7989 }
7990 env->insns_flags &= PPC_TCG_INSNS;
7991 env->insns_flags2 &= PPC_TCG_INSNS2;
7992 return 0;
7993 }
7994
7995 static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
7996 {
7997 PowerPCCPU *cpu = POWERPC_CPU(dev);
7998 CPUPPCState *env = &cpu->env;
7999 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8000 Error *local_err = NULL;
8001 #if !defined(CONFIG_USER_ONLY)
8002 int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
8003 #endif
8004
8005 #if !defined(CONFIG_USER_ONLY)
8006 if (smp_threads > max_smt) {
8007 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
8008 max_smt, kvm_enabled() ? "KVM" : "TCG");
8009 return;
8010 }
8011 #endif
8012
8013 if (kvm_enabled()) {
8014 if (kvmppc_fixup_cpu(cpu) != 0) {
8015 error_setg(errp, "Unable to virtualize selected CPU with KVM");
8016 return;
8017 }
8018 } else {
8019 if (ppc_fixup_cpu(cpu) != 0) {
8020 error_setg(errp, "Unable to emulate selected CPU with TCG");
8021 return;
8022 }
8023 }
8024
8025 #if defined(TARGET_PPCEMB)
8026 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
8027 error_setg(errp, "CPU does not possess a BookE MMU. "
8028 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
8029 "or choose another CPU model.");
8030 return;
8031 }
8032 #endif
8033
8034 create_ppc_opcodes(cpu, &local_err);
8035 if (local_err != NULL) {
8036 error_propagate(errp, local_err);
8037 return;
8038 }
8039 init_ppc_proc(cpu);
8040
8041 if (pcc->insns_flags & PPC_FLOAT) {
8042 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
8043 33, "power-fpu.xml", 0);
8044 }
8045 if (pcc->insns_flags & PPC_ALTIVEC) {
8046 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
8047 34, "power-altivec.xml", 0);
8048 }
8049 if (pcc->insns_flags & PPC_SPE) {
8050 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
8051 34, "power-spe.xml", 0);
8052 }
8053
8054 qemu_init_vcpu(env);
8055
8056 pcc->parent_realize(dev, errp);
8057
8058 #if defined(PPC_DUMP_CPU)
8059 {
8060 const char *mmu_model, *excp_model, *bus_model;
8061 switch (env->mmu_model) {
8062 case POWERPC_MMU_32B:
8063 mmu_model = "PowerPC 32";
8064 break;
8065 case POWERPC_MMU_SOFT_6xx:
8066 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
8067 break;
8068 case POWERPC_MMU_SOFT_74xx:
8069 mmu_model = "PowerPC 74xx with software driven TLBs";
8070 break;
8071 case POWERPC_MMU_SOFT_4xx:
8072 mmu_model = "PowerPC 4xx with software driven TLBs";
8073 break;
8074 case POWERPC_MMU_SOFT_4xx_Z:
8075 mmu_model = "PowerPC 4xx with software driven TLBs "
8076 "and zones protections";
8077 break;
8078 case POWERPC_MMU_REAL:
8079 mmu_model = "PowerPC real mode only";
8080 break;
8081 case POWERPC_MMU_MPC8xx:
8082 mmu_model = "PowerPC MPC8xx";
8083 break;
8084 case POWERPC_MMU_BOOKE:
8085 mmu_model = "PowerPC BookE";
8086 break;
8087 case POWERPC_MMU_BOOKE206:
8088 mmu_model = "PowerPC BookE 2.06";
8089 break;
8090 case POWERPC_MMU_601:
8091 mmu_model = "PowerPC 601";
8092 break;
8093 #if defined (TARGET_PPC64)
8094 case POWERPC_MMU_64B:
8095 mmu_model = "PowerPC 64";
8096 break;
8097 case POWERPC_MMU_620:
8098 mmu_model = "PowerPC 620";
8099 break;
8100 #endif
8101 default:
8102 mmu_model = "Unknown or invalid";
8103 break;
8104 }
8105 switch (env->excp_model) {
8106 case POWERPC_EXCP_STD:
8107 excp_model = "PowerPC";
8108 break;
8109 case POWERPC_EXCP_40x:
8110 excp_model = "PowerPC 40x";
8111 break;
8112 case POWERPC_EXCP_601:
8113 excp_model = "PowerPC 601";
8114 break;
8115 case POWERPC_EXCP_602:
8116 excp_model = "PowerPC 602";
8117 break;
8118 case POWERPC_EXCP_603:
8119 excp_model = "PowerPC 603";
8120 break;
8121 case POWERPC_EXCP_603E:
8122 excp_model = "PowerPC 603e";
8123 break;
8124 case POWERPC_EXCP_604:
8125 excp_model = "PowerPC 604";
8126 break;
8127 case POWERPC_EXCP_7x0:
8128 excp_model = "PowerPC 740/750";
8129 break;
8130 case POWERPC_EXCP_7x5:
8131 excp_model = "PowerPC 745/755";
8132 break;
8133 case POWERPC_EXCP_74xx:
8134 excp_model = "PowerPC 74xx";
8135 break;
8136 case POWERPC_EXCP_BOOKE:
8137 excp_model = "PowerPC BookE";
8138 break;
8139 #if defined (TARGET_PPC64)
8140 case POWERPC_EXCP_970:
8141 excp_model = "PowerPC 970";
8142 break;
8143 #endif
8144 default:
8145 excp_model = "Unknown or invalid";
8146 break;
8147 }
8148 switch (env->bus_model) {
8149 case PPC_FLAGS_INPUT_6xx:
8150 bus_model = "PowerPC 6xx";
8151 break;
8152 case PPC_FLAGS_INPUT_BookE:
8153 bus_model = "PowerPC BookE";
8154 break;
8155 case PPC_FLAGS_INPUT_405:
8156 bus_model = "PowerPC 405";
8157 break;
8158 case PPC_FLAGS_INPUT_401:
8159 bus_model = "PowerPC 401/403";
8160 break;
8161 case PPC_FLAGS_INPUT_RCPU:
8162 bus_model = "RCPU / MPC8xx";
8163 break;
8164 #if defined (TARGET_PPC64)
8165 case PPC_FLAGS_INPUT_970:
8166 bus_model = "PowerPC 970";
8167 break;
8168 #endif
8169 default:
8170 bus_model = "Unknown or invalid";
8171 break;
8172 }
8173 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
8174 " MMU model : %s\n",
8175 pcc->name, pcc->pvr, pcc->msr_mask, mmu_model);
8176 #if !defined(CONFIG_USER_ONLY)
8177 if (env->tlb != NULL) {
8178 printf(" %d %s TLB in %d ways\n",
8179 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
8180 env->nb_ways);
8181 }
8182 #endif
8183 printf(" Exceptions model : %s\n"
8184 " Bus model : %s\n",
8185 excp_model, bus_model);
8186 printf(" MSR features :\n");
8187 if (env->flags & POWERPC_FLAG_SPE)
8188 printf(" signal processing engine enable"
8189 "\n");
8190 else if (env->flags & POWERPC_FLAG_VRE)
8191 printf(" vector processor enable\n");
8192 if (env->flags & POWERPC_FLAG_TGPR)
8193 printf(" temporary GPRs\n");
8194 else if (env->flags & POWERPC_FLAG_CE)
8195 printf(" critical input enable\n");
8196 if (env->flags & POWERPC_FLAG_SE)
8197 printf(" single-step trace mode\n");
8198 else if (env->flags & POWERPC_FLAG_DWE)
8199 printf(" debug wait enable\n");
8200 else if (env->flags & POWERPC_FLAG_UBLE)
8201 printf(" user BTB lock enable\n");
8202 if (env->flags & POWERPC_FLAG_BE)
8203 printf(" branch-step trace mode\n");
8204 else if (env->flags & POWERPC_FLAG_DE)
8205 printf(" debug interrupt enable\n");
8206 if (env->flags & POWERPC_FLAG_PX)
8207 printf(" inclusive protection\n");
8208 else if (env->flags & POWERPC_FLAG_PMM)
8209 printf(" performance monitor mark\n");
8210 if (env->flags == POWERPC_FLAG_NONE)
8211 printf(" none\n");
8212 printf(" Time-base/decrementer clock source: %s\n",
8213 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
8214 }
8215 dump_ppc_insns(env);
8216 dump_ppc_sprs(env);
8217 fflush(stdout);
8218 #endif
8219 }
8220
8221 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
8222 {
8223 ObjectClass *oc = (ObjectClass *)a;
8224 uint32_t pvr = *(uint32_t *)b;
8225 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8226
8227 /* -cpu host does a PVR lookup during construction */
8228 if (unlikely(strcmp(object_class_get_name(oc),
8229 TYPE_HOST_POWERPC_CPU) == 0)) {
8230 return -1;
8231 }
8232
8233 #if defined(TARGET_PPCEMB)
8234 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
8235 return -1;
8236 }
8237 #endif
8238
8239 return pcc->pvr == pvr ? 0 : -1;
8240 }
8241
8242 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
8243 {
8244 GSList *list, *item;
8245 PowerPCCPUClass *pcc = NULL;
8246
8247 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8248 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
8249 if (item != NULL) {
8250 pcc = POWERPC_CPU_CLASS(item->data);
8251 }
8252 g_slist_free(list);
8253
8254 return pcc;
8255 }
8256
8257 static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
8258 {
8259 ObjectClass *oc = (ObjectClass *)a;
8260 const char *name = b;
8261 #if defined(TARGET_PPCEMB)
8262 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8263 #endif
8264
8265 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
8266 #if defined(TARGET_PPCEMB)
8267 pcc->mmu_model == POWERPC_MMU_BOOKE &&
8268 #endif
8269 strcmp(object_class_get_name(oc) + strlen(name),
8270 "-" TYPE_POWERPC_CPU) == 0) {
8271 return 0;
8272 }
8273 return -1;
8274 }
8275
8276 #include <ctype.h>
8277
8278 static ObjectClass *ppc_cpu_class_by_name(const char *name)
8279 {
8280 GSList *list, *item;
8281 ObjectClass *ret = NULL;
8282 const char *p;
8283 int i, len;
8284
8285 if (strcasecmp(name, "host") == 0) {
8286 if (kvm_enabled()) {
8287 ret = object_class_by_name(TYPE_HOST_POWERPC_CPU);
8288 }
8289 return ret;
8290 }
8291
8292 /* Check if the given name is a PVR */
8293 len = strlen(name);
8294 if (len == 10 && name[0] == '0' && name[1] == 'x') {
8295 p = name + 2;
8296 goto check_pvr;
8297 } else if (len == 8) {
8298 p = name;
8299 check_pvr:
8300 for (i = 0; i < 8; i++) {
8301 if (!qemu_isxdigit(*p++))
8302 break;
8303 }
8304 if (i == 8) {
8305 ret = OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
8306 return ret;
8307 }
8308 }
8309
8310 for (i = 0; i < ARRAY_SIZE(ppc_cpu_aliases); i++) {
8311 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
8312 return ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
8313 }
8314 }
8315
8316 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8317 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
8318 if (item != NULL) {
8319 ret = OBJECT_CLASS(item->data);
8320 }
8321 g_slist_free(list);
8322
8323 return ret;
8324 }
8325
8326 PowerPCCPU *cpu_ppc_init(const char *cpu_model)
8327 {
8328 PowerPCCPU *cpu;
8329 CPUPPCState *env;
8330 ObjectClass *oc;
8331 Error *err = NULL;
8332
8333 oc = ppc_cpu_class_by_name(cpu_model);
8334 if (oc == NULL) {
8335 return NULL;
8336 }
8337
8338 cpu = POWERPC_CPU(object_new(object_class_get_name(oc)));
8339 env = &cpu->env;
8340 env->cpu_model_str = cpu_model;
8341
8342 object_property_set_bool(OBJECT(cpu), true, "realized", &err);
8343 if (err != NULL) {
8344 fprintf(stderr, "%s\n", error_get_pretty(err));
8345 error_free(err);
8346 object_unref(OBJECT(cpu));
8347 return NULL;
8348 }
8349
8350 return cpu;
8351 }
8352
8353 /* Sort by PVR, ordering special case "host" last. */
8354 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
8355 {
8356 ObjectClass *oc_a = (ObjectClass *)a;
8357 ObjectClass *oc_b = (ObjectClass *)b;
8358 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
8359 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
8360 const char *name_a = object_class_get_name(oc_a);
8361 const char *name_b = object_class_get_name(oc_b);
8362
8363 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
8364 return 1;
8365 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
8366 return -1;
8367 } else {
8368 /* Avoid an integer overflow during subtraction */
8369 if (pcc_a->pvr < pcc_b->pvr) {
8370 return -1;
8371 } else if (pcc_a->pvr > pcc_b->pvr) {
8372 return 1;
8373 } else {
8374 return 0;
8375 }
8376 }
8377 }
8378
8379 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
8380 {
8381 ObjectClass *oc = data;
8382 CPUListState *s = user_data;
8383 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8384 const char *typename = object_class_get_name(oc);
8385 char *name;
8386
8387 #if defined(TARGET_PPCEMB)
8388 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
8389 return;
8390 }
8391 #endif
8392
8393 name = g_strndup(typename,
8394 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
8395 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
8396 name, pcc->pvr);
8397 g_free(name);
8398 }
8399
8400 void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
8401 {
8402 CPUListState s = {
8403 .file = f,
8404 .cpu_fprintf = cpu_fprintf,
8405 };
8406 GSList *list;
8407 int i;
8408
8409 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8410 list = g_slist_sort(list, ppc_cpu_list_compare);
8411 g_slist_foreach(list, ppc_cpu_list_entry, &s);
8412 g_slist_free(list);
8413
8414 cpu_fprintf(f, "\n");
8415 for (i = 0; i < ARRAY_SIZE(ppc_cpu_aliases); i++) {
8416 ObjectClass *oc = ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
8417 if (oc == NULL) {
8418 /* Hide aliases that point to a TODO or TODO_USER_ONLY model */
8419 continue;
8420 }
8421 cpu_fprintf(f, "PowerPC %-16s\n",
8422 ppc_cpu_aliases[i].alias);
8423 }
8424 }
8425
8426 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
8427 {
8428 ObjectClass *oc = data;
8429 CpuDefinitionInfoList **first = user_data;
8430 const char *typename;
8431 CpuDefinitionInfoList *entry;
8432 CpuDefinitionInfo *info;
8433 #if defined(TARGET_PPCEMB)
8434 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8435
8436 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
8437 return;
8438 }
8439 #endif
8440
8441 typename = object_class_get_name(oc);
8442 info = g_malloc0(sizeof(*info));
8443 info->name = g_strndup(typename,
8444 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
8445
8446 entry = g_malloc0(sizeof(*entry));
8447 entry->value = info;
8448 entry->next = *first;
8449 *first = entry;
8450 }
8451
8452 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
8453 {
8454 CpuDefinitionInfoList *cpu_list = NULL;
8455 GSList *list;
8456
8457 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8458 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
8459 g_slist_free(list);
8460
8461 return cpu_list;
8462 }
8463
8464 /* CPUClass::reset() */
8465 static void ppc_cpu_reset(CPUState *s)
8466 {
8467 PowerPCCPU *cpu = POWERPC_CPU(s);
8468 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8469 CPUPPCState *env = &cpu->env;
8470 target_ulong msr;
8471
8472 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
8473 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
8474 log_cpu_state(env, 0);
8475 }
8476
8477 pcc->parent_reset(s);
8478
8479 msr = (target_ulong)0;
8480 if (0) {
8481 /* XXX: find a suitable condition to enable the hypervisor mode */
8482 msr |= (target_ulong)MSR_HVB;
8483 }
8484 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
8485 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
8486 msr |= (target_ulong)1 << MSR_EP;
8487 #if defined(DO_SINGLE_STEP) && 0
8488 /* Single step trace mode */
8489 msr |= (target_ulong)1 << MSR_SE;
8490 msr |= (target_ulong)1 << MSR_BE;
8491 #endif
8492 #if defined(CONFIG_USER_ONLY)
8493 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
8494 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
8495 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
8496 msr |= (target_ulong)1 << MSR_PR;
8497 #else
8498 env->excp_prefix = env->hreset_excp_prefix;
8499 env->nip = env->hreset_vector | env->excp_prefix;
8500 if (env->mmu_model != POWERPC_MMU_REAL) {
8501 ppc_tlb_invalidate_all(env);
8502 }
8503 #endif
8504 env->msr = msr & env->msr_mask;
8505 #if defined(TARGET_PPC64)
8506 if (env->mmu_model & POWERPC_MMU_64) {
8507 env->msr |= (1ULL << MSR_SF);
8508 }
8509 #endif
8510 hreg_compute_hflags(env);
8511 env->reserve_addr = (target_ulong)-1ULL;
8512 /* Be sure no exception or interrupt is pending */
8513 env->pending_interrupts = 0;
8514 env->exception_index = POWERPC_EXCP_NONE;
8515 env->error_code = 0;
8516
8517 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
8518 env->vpa_addr = 0;
8519 env->slb_shadow_addr = 0;
8520 env->slb_shadow_size = 0;
8521 env->dtl_addr = 0;
8522 env->dtl_size = 0;
8523 #endif /* TARGET_PPC64 */
8524
8525 /* Flush all TLBs */
8526 tlb_flush(env, 1);
8527 }
8528
8529 static void ppc_cpu_initfn(Object *obj)
8530 {
8531 CPUState *cs = CPU(obj);
8532 PowerPCCPU *cpu = POWERPC_CPU(obj);
8533 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8534 CPUPPCState *env = &cpu->env;
8535
8536 cs->env_ptr = env;
8537 cpu_exec_init(env);
8538
8539 env->msr_mask = pcc->msr_mask;
8540 env->mmu_model = pcc->mmu_model;
8541 env->excp_model = pcc->excp_model;
8542 env->bus_model = pcc->bus_model;
8543 env->insns_flags = pcc->insns_flags;
8544 env->insns_flags2 = pcc->insns_flags2;
8545 env->flags = pcc->flags;
8546 env->bfd_mach = pcc->bfd_mach;
8547 env->check_pow = pcc->check_pow;
8548
8549 #if defined(TARGET_PPC64)
8550 if (pcc->sps) {
8551 env->sps = *pcc->sps;
8552 } else if (env->mmu_model & POWERPC_MMU_64) {
8553 /* Use default sets of page sizes */
8554 static const struct ppc_segment_page_sizes defsps = {
8555 .sps = {
8556 { .page_shift = 12, /* 4K */
8557 .slb_enc = 0,
8558 .enc = { { .page_shift = 12, .pte_enc = 0 } }
8559 },
8560 { .page_shift = 24, /* 16M */
8561 .slb_enc = 0x100,
8562 .enc = { { .page_shift = 24, .pte_enc = 0 } }
8563 },
8564 },
8565 };
8566 env->sps = defsps;
8567 }
8568 #endif /* defined(TARGET_PPC64) */
8569
8570 if (tcg_enabled()) {
8571 ppc_translate_init();
8572 }
8573 }
8574
8575 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
8576 {
8577 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8578 CPUClass *cc = CPU_CLASS(oc);
8579 DeviceClass *dc = DEVICE_CLASS(oc);
8580
8581 pcc->parent_realize = dc->realize;
8582 dc->realize = ppc_cpu_realizefn;
8583
8584 pcc->parent_reset = cc->reset;
8585 cc->reset = ppc_cpu_reset;
8586
8587 cc->class_by_name = ppc_cpu_class_by_name;
8588 }
8589
8590 static const TypeInfo ppc_cpu_type_info = {
8591 .name = TYPE_POWERPC_CPU,
8592 .parent = TYPE_CPU,
8593 .instance_size = sizeof(PowerPCCPU),
8594 .instance_init = ppc_cpu_initfn,
8595 .abstract = true,
8596 .class_size = sizeof(PowerPCCPUClass),
8597 .class_init = ppc_cpu_class_init,
8598 };
8599
8600 static void ppc_cpu_register_types(void)
8601 {
8602 type_register_static(&ppc_cpu_type_info);
8603 }
8604
8605 type_init(ppc_cpu_register_types)
Qemu copy for testing