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target-ppc: Turn descriptive CPU family comments into device descriptions
[qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26 #include "disas/bfd.h"
27 #include "exec/gdbstub.h"
28 #include <sysemu/kvm.h>
29 #include "kvm_ppc.h"
30 #include "sysemu/arch_init.h"
31 #include "sysemu/cpus.h"
32
33 //#define PPC_DUMP_CPU
34 //#define PPC_DEBUG_SPR
35 //#define PPC_DUMP_SPR_ACCESSES
36 #if defined(CONFIG_USER_ONLY)
37 #define TODO_USER_ONLY 1
38 #endif
39
40 /* For user-mode emulation, we don't emulate any IRQ controller */
41 #if defined(CONFIG_USER_ONLY)
42 #define PPC_IRQ_INIT_FN(name) \
43 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
44 { \
45 }
46 #else
47 #define PPC_IRQ_INIT_FN(name) \
48 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
49 #endif
50
51 PPC_IRQ_INIT_FN(40x);
52 PPC_IRQ_INIT_FN(6xx);
53 PPC_IRQ_INIT_FN(970);
54 PPC_IRQ_INIT_FN(POWER7);
55 PPC_IRQ_INIT_FN(e500);
56
57 /* Generic callbacks:
58 * do nothing but store/retrieve spr value
59 */
60 static void spr_load_dump_spr(int sprn)
61 {
62 #ifdef PPC_DUMP_SPR_ACCESSES
63 TCGv_i32 t0 = tcg_const_i32(sprn);
64 gen_helper_load_dump_spr(t0);
65 tcg_temp_free_i32(t0);
66 #endif
67 }
68
69 static void spr_read_generic (void *opaque, int gprn, int sprn)
70 {
71 gen_load_spr(cpu_gpr[gprn], sprn);
72 spr_load_dump_spr(sprn);
73 }
74
75 static void spr_store_dump_spr(int sprn)
76 {
77 #ifdef PPC_DUMP_SPR_ACCESSES
78 TCGv_i32 t0 = tcg_const_i32(sprn);
79 gen_helper_store_dump_spr(t0);
80 tcg_temp_free_i32(t0);
81 #endif
82 }
83
84 static void spr_write_generic (void *opaque, int sprn, int gprn)
85 {
86 gen_store_spr(sprn, cpu_gpr[gprn]);
87 spr_store_dump_spr(sprn);
88 }
89
90 #if !defined(CONFIG_USER_ONLY)
91 static void spr_write_generic32(void *opaque, int sprn, int gprn)
92 {
93 #ifdef TARGET_PPC64
94 TCGv t0 = tcg_temp_new();
95 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
96 gen_store_spr(sprn, t0);
97 tcg_temp_free(t0);
98 spr_store_dump_spr(sprn);
99 #else
100 spr_write_generic(opaque, sprn, gprn);
101 #endif
102 }
103
104 static void spr_write_clear (void *opaque, int sprn, int gprn)
105 {
106 TCGv t0 = tcg_temp_new();
107 TCGv t1 = tcg_temp_new();
108 gen_load_spr(t0, sprn);
109 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
110 tcg_gen_and_tl(t0, t0, t1);
111 gen_store_spr(sprn, t0);
112 tcg_temp_free(t0);
113 tcg_temp_free(t1);
114 }
115 #endif
116
117 /* SPR common to all PowerPC */
118 /* XER */
119 static void spr_read_xer (void *opaque, int gprn, int sprn)
120 {
121 gen_read_xer(cpu_gpr[gprn]);
122 }
123
124 static void spr_write_xer (void *opaque, int sprn, int gprn)
125 {
126 gen_write_xer(cpu_gpr[gprn]);
127 }
128
129 /* LR */
130 static void spr_read_lr (void *opaque, int gprn, int sprn)
131 {
132 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
133 }
134
135 static void spr_write_lr (void *opaque, int sprn, int gprn)
136 {
137 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
138 }
139
140 /* CFAR */
141 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
142 static void spr_read_cfar (void *opaque, int gprn, int sprn)
143 {
144 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
145 }
146
147 static void spr_write_cfar (void *opaque, int sprn, int gprn)
148 {
149 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
150 }
151 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
152
153 /* CTR */
154 static void spr_read_ctr (void *opaque, int gprn, int sprn)
155 {
156 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
157 }
158
159 static void spr_write_ctr (void *opaque, int sprn, int gprn)
160 {
161 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
162 }
163
164 /* User read access to SPR */
165 /* USPRx */
166 /* UMMCRx */
167 /* UPMCx */
168 /* USIA */
169 /* UDECR */
170 static void spr_read_ureg (void *opaque, int gprn, int sprn)
171 {
172 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
173 }
174
175 /* SPR common to all non-embedded PowerPC */
176 /* DECR */
177 #if !defined(CONFIG_USER_ONLY)
178 static void spr_read_decr (void *opaque, int gprn, int sprn)
179 {
180 if (use_icount) {
181 gen_io_start();
182 }
183 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
184 if (use_icount) {
185 gen_io_end();
186 gen_stop_exception(opaque);
187 }
188 }
189
190 static void spr_write_decr (void *opaque, int sprn, int gprn)
191 {
192 if (use_icount) {
193 gen_io_start();
194 }
195 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
196 if (use_icount) {
197 gen_io_end();
198 gen_stop_exception(opaque);
199 }
200 }
201 #endif
202
203 /* SPR common to all non-embedded PowerPC, except 601 */
204 /* Time base */
205 static void spr_read_tbl (void *opaque, int gprn, int sprn)
206 {
207 if (use_icount) {
208 gen_io_start();
209 }
210 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
211 if (use_icount) {
212 gen_io_end();
213 gen_stop_exception(opaque);
214 }
215 }
216
217 static void spr_read_tbu (void *opaque, int gprn, int sprn)
218 {
219 if (use_icount) {
220 gen_io_start();
221 }
222 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
223 if (use_icount) {
224 gen_io_end();
225 gen_stop_exception(opaque);
226 }
227 }
228
229 __attribute__ (( unused ))
230 static void spr_read_atbl (void *opaque, int gprn, int sprn)
231 {
232 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
233 }
234
235 __attribute__ (( unused ))
236 static void spr_read_atbu (void *opaque, int gprn, int sprn)
237 {
238 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
239 }
240
241 #if !defined(CONFIG_USER_ONLY)
242 static void spr_write_tbl (void *opaque, int sprn, int gprn)
243 {
244 if (use_icount) {
245 gen_io_start();
246 }
247 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
248 if (use_icount) {
249 gen_io_end();
250 gen_stop_exception(opaque);
251 }
252 }
253
254 static void spr_write_tbu (void *opaque, int sprn, int gprn)
255 {
256 if (use_icount) {
257 gen_io_start();
258 }
259 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
260 if (use_icount) {
261 gen_io_end();
262 gen_stop_exception(opaque);
263 }
264 }
265
266 __attribute__ (( unused ))
267 static void spr_write_atbl (void *opaque, int sprn, int gprn)
268 {
269 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
270 }
271
272 __attribute__ (( unused ))
273 static void spr_write_atbu (void *opaque, int sprn, int gprn)
274 {
275 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
276 }
277
278 #if defined(TARGET_PPC64)
279 __attribute__ (( unused ))
280 static void spr_read_purr (void *opaque, int gprn, int sprn)
281 {
282 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
283 }
284 #endif
285 #endif
286
287 #if !defined(CONFIG_USER_ONLY)
288 /* IBAT0U...IBAT0U */
289 /* IBAT0L...IBAT7L */
290 static void spr_read_ibat (void *opaque, int gprn, int sprn)
291 {
292 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
293 }
294
295 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
296 {
297 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
298 }
299
300 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
301 {
302 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
303 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
304 tcg_temp_free_i32(t0);
305 }
306
307 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
308 {
309 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
310 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
311 tcg_temp_free_i32(t0);
312 }
313
314 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
315 {
316 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
317 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
318 tcg_temp_free_i32(t0);
319 }
320
321 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
322 {
323 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
324 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
325 tcg_temp_free_i32(t0);
326 }
327
328 /* DBAT0U...DBAT7U */
329 /* DBAT0L...DBAT7L */
330 static void spr_read_dbat (void *opaque, int gprn, int sprn)
331 {
332 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
333 }
334
335 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
336 {
337 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
338 }
339
340 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
341 {
342 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
343 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
344 tcg_temp_free_i32(t0);
345 }
346
347 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
348 {
349 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
350 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
351 tcg_temp_free_i32(t0);
352 }
353
354 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
355 {
356 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
357 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
358 tcg_temp_free_i32(t0);
359 }
360
361 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
362 {
363 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
364 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
365 tcg_temp_free_i32(t0);
366 }
367
368 /* SDR1 */
369 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
370 {
371 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
372 }
373
374 /* 64 bits PowerPC specific SPRs */
375 /* ASR */
376 #if defined(TARGET_PPC64)
377 static void spr_read_hior (void *opaque, int gprn, int sprn)
378 {
379 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
380 }
381
382 static void spr_write_hior (void *opaque, int sprn, int gprn)
383 {
384 TCGv t0 = tcg_temp_new();
385 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
386 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
387 tcg_temp_free(t0);
388 }
389
390 static void spr_read_asr (void *opaque, int gprn, int sprn)
391 {
392 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, asr));
393 }
394
395 static void spr_write_asr (void *opaque, int sprn, int gprn)
396 {
397 gen_helper_store_asr(cpu_env, cpu_gpr[gprn]);
398 }
399 #endif
400 #endif
401
402 /* PowerPC 601 specific registers */
403 /* RTC */
404 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
405 {
406 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
407 }
408
409 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
410 {
411 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
412 }
413
414 #if !defined(CONFIG_USER_ONLY)
415 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
416 {
417 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
418 }
419
420 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
421 {
422 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
423 }
424
425 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
426 {
427 DisasContext *ctx = opaque;
428
429 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
430 /* Must stop the translation as endianness may have changed */
431 gen_stop_exception(ctx);
432 }
433 #endif
434
435 /* Unified bats */
436 #if !defined(CONFIG_USER_ONLY)
437 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
438 {
439 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
440 }
441
442 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
443 {
444 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
445 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
446 tcg_temp_free_i32(t0);
447 }
448
449 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
450 {
451 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
452 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
453 tcg_temp_free_i32(t0);
454 }
455 #endif
456
457 /* PowerPC 40x specific registers */
458 #if !defined(CONFIG_USER_ONLY)
459 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
460 {
461 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
462 }
463
464 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
465 {
466 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
467 }
468
469 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
470 {
471 DisasContext *ctx = opaque;
472
473 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
474 /* We must stop translation as we may have rebooted */
475 gen_stop_exception(ctx);
476 }
477
478 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
479 {
480 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
481 }
482
483 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
484 {
485 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
486 }
487
488 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
489 {
490 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
491 }
492 #endif
493
494 /* PowerPC 403 specific registers */
495 /* PBL1 / PBU1 / PBL2 / PBU2 */
496 #if !defined(CONFIG_USER_ONLY)
497 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
498 {
499 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
500 }
501
502 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
503 {
504 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
505 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
506 tcg_temp_free_i32(t0);
507 }
508
509 static void spr_write_pir (void *opaque, int sprn, int gprn)
510 {
511 TCGv t0 = tcg_temp_new();
512 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
513 gen_store_spr(SPR_PIR, t0);
514 tcg_temp_free(t0);
515 }
516 #endif
517
518 /* SPE specific registers */
519 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
520 {
521 TCGv_i32 t0 = tcg_temp_new_i32();
522 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
523 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
524 tcg_temp_free_i32(t0);
525 }
526
527 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
528 {
529 TCGv_i32 t0 = tcg_temp_new_i32();
530 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
531 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
532 tcg_temp_free_i32(t0);
533 }
534
535 #if !defined(CONFIG_USER_ONLY)
536 /* Callback used to write the exception vector base */
537 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
538 {
539 TCGv t0 = tcg_temp_new();
540 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
541 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
542 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
543 gen_store_spr(sprn, t0);
544 tcg_temp_free(t0);
545 }
546
547 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
548 {
549 DisasContext *ctx = opaque;
550 int sprn_offs;
551
552 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
553 sprn_offs = sprn - SPR_BOOKE_IVOR0;
554 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
555 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
556 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
557 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
558 } else {
559 printf("Trying to write an unknown exception vector %d %03x\n",
560 sprn, sprn);
561 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
562 return;
563 }
564
565 TCGv t0 = tcg_temp_new();
566 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
567 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
568 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
569 gen_store_spr(sprn, t0);
570 tcg_temp_free(t0);
571 }
572 #endif
573
574 static inline void vscr_init (CPUPPCState *env, uint32_t val)
575 {
576 env->vscr = val;
577 /* Altivec always uses round-to-nearest */
578 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
579 set_flush_to_zero(vscr_nj, &env->vec_status);
580 }
581
582 #if defined(CONFIG_USER_ONLY)
583 #define spr_register(env, num, name, uea_read, uea_write, \
584 oea_read, oea_write, initial_value) \
585 do { \
586 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
587 } while (0)
588 static inline void _spr_register (CPUPPCState *env, int num,
589 const char *name,
590 void (*uea_read)(void *opaque, int gprn, int sprn),
591 void (*uea_write)(void *opaque, int sprn, int gprn),
592 target_ulong initial_value)
593 #else
594 static inline void spr_register (CPUPPCState *env, int num,
595 const char *name,
596 void (*uea_read)(void *opaque, int gprn, int sprn),
597 void (*uea_write)(void *opaque, int sprn, int gprn),
598 void (*oea_read)(void *opaque, int gprn, int sprn),
599 void (*oea_write)(void *opaque, int sprn, int gprn),
600 target_ulong initial_value)
601 #endif
602 {
603 ppc_spr_t *spr;
604
605 spr = &env->spr_cb[num];
606 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
607 #if !defined(CONFIG_USER_ONLY)
608 spr->oea_read != NULL || spr->oea_write != NULL ||
609 #endif
610 spr->uea_read != NULL || spr->uea_write != NULL) {
611 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
612 exit(1);
613 }
614 #if defined(PPC_DEBUG_SPR)
615 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
616 name, initial_value);
617 #endif
618 spr->name = name;
619 spr->uea_read = uea_read;
620 spr->uea_write = uea_write;
621 #if !defined(CONFIG_USER_ONLY)
622 spr->oea_read = oea_read;
623 spr->oea_write = oea_write;
624 #endif
625 env->spr[num] = initial_value;
626 }
627
628 /* Generic PowerPC SPRs */
629 static void gen_spr_generic (CPUPPCState *env)
630 {
631 /* Integer processing */
632 spr_register(env, SPR_XER, "XER",
633 &spr_read_xer, &spr_write_xer,
634 &spr_read_xer, &spr_write_xer,
635 0x00000000);
636 /* Branch contol */
637 spr_register(env, SPR_LR, "LR",
638 &spr_read_lr, &spr_write_lr,
639 &spr_read_lr, &spr_write_lr,
640 0x00000000);
641 spr_register(env, SPR_CTR, "CTR",
642 &spr_read_ctr, &spr_write_ctr,
643 &spr_read_ctr, &spr_write_ctr,
644 0x00000000);
645 /* Interrupt processing */
646 spr_register(env, SPR_SRR0, "SRR0",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_generic, &spr_write_generic,
649 0x00000000);
650 spr_register(env, SPR_SRR1, "SRR1",
651 SPR_NOACCESS, SPR_NOACCESS,
652 &spr_read_generic, &spr_write_generic,
653 0x00000000);
654 /* Processor control */
655 spr_register(env, SPR_SPRG0, "SPRG0",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 spr_register(env, SPR_SPRG1, "SPRG1",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 spr_register(env, SPR_SPRG2, "SPRG2",
664 SPR_NOACCESS, SPR_NOACCESS,
665 &spr_read_generic, &spr_write_generic,
666 0x00000000);
667 spr_register(env, SPR_SPRG3, "SPRG3",
668 SPR_NOACCESS, SPR_NOACCESS,
669 &spr_read_generic, &spr_write_generic,
670 0x00000000);
671 }
672
673 /* SPR common to all non-embedded PowerPC, including 601 */
674 static void gen_spr_ne_601 (CPUPPCState *env)
675 {
676 /* Exception processing */
677 spr_register(env, SPR_DSISR, "DSISR",
678 SPR_NOACCESS, SPR_NOACCESS,
679 &spr_read_generic, &spr_write_generic,
680 0x00000000);
681 spr_register(env, SPR_DAR, "DAR",
682 SPR_NOACCESS, SPR_NOACCESS,
683 &spr_read_generic, &spr_write_generic,
684 0x00000000);
685 /* Timer */
686 spr_register(env, SPR_DECR, "DECR",
687 SPR_NOACCESS, SPR_NOACCESS,
688 &spr_read_decr, &spr_write_decr,
689 0x00000000);
690 /* Memory management */
691 spr_register(env, SPR_SDR1, "SDR1",
692 SPR_NOACCESS, SPR_NOACCESS,
693 &spr_read_generic, &spr_write_sdr1,
694 0x00000000);
695 }
696
697 /* BATs 0-3 */
698 static void gen_low_BATs (CPUPPCState *env)
699 {
700 #if !defined(CONFIG_USER_ONLY)
701 spr_register(env, SPR_IBAT0U, "IBAT0U",
702 SPR_NOACCESS, SPR_NOACCESS,
703 &spr_read_ibat, &spr_write_ibatu,
704 0x00000000);
705 spr_register(env, SPR_IBAT0L, "IBAT0L",
706 SPR_NOACCESS, SPR_NOACCESS,
707 &spr_read_ibat, &spr_write_ibatl,
708 0x00000000);
709 spr_register(env, SPR_IBAT1U, "IBAT1U",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_ibat, &spr_write_ibatu,
712 0x00000000);
713 spr_register(env, SPR_IBAT1L, "IBAT1L",
714 SPR_NOACCESS, SPR_NOACCESS,
715 &spr_read_ibat, &spr_write_ibatl,
716 0x00000000);
717 spr_register(env, SPR_IBAT2U, "IBAT2U",
718 SPR_NOACCESS, SPR_NOACCESS,
719 &spr_read_ibat, &spr_write_ibatu,
720 0x00000000);
721 spr_register(env, SPR_IBAT2L, "IBAT2L",
722 SPR_NOACCESS, SPR_NOACCESS,
723 &spr_read_ibat, &spr_write_ibatl,
724 0x00000000);
725 spr_register(env, SPR_IBAT3U, "IBAT3U",
726 SPR_NOACCESS, SPR_NOACCESS,
727 &spr_read_ibat, &spr_write_ibatu,
728 0x00000000);
729 spr_register(env, SPR_IBAT3L, "IBAT3L",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_ibat, &spr_write_ibatl,
732 0x00000000);
733 spr_register(env, SPR_DBAT0U, "DBAT0U",
734 SPR_NOACCESS, SPR_NOACCESS,
735 &spr_read_dbat, &spr_write_dbatu,
736 0x00000000);
737 spr_register(env, SPR_DBAT0L, "DBAT0L",
738 SPR_NOACCESS, SPR_NOACCESS,
739 &spr_read_dbat, &spr_write_dbatl,
740 0x00000000);
741 spr_register(env, SPR_DBAT1U, "DBAT1U",
742 SPR_NOACCESS, SPR_NOACCESS,
743 &spr_read_dbat, &spr_write_dbatu,
744 0x00000000);
745 spr_register(env, SPR_DBAT1L, "DBAT1L",
746 SPR_NOACCESS, SPR_NOACCESS,
747 &spr_read_dbat, &spr_write_dbatl,
748 0x00000000);
749 spr_register(env, SPR_DBAT2U, "DBAT2U",
750 SPR_NOACCESS, SPR_NOACCESS,
751 &spr_read_dbat, &spr_write_dbatu,
752 0x00000000);
753 spr_register(env, SPR_DBAT2L, "DBAT2L",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_dbat, &spr_write_dbatl,
756 0x00000000);
757 spr_register(env, SPR_DBAT3U, "DBAT3U",
758 SPR_NOACCESS, SPR_NOACCESS,
759 &spr_read_dbat, &spr_write_dbatu,
760 0x00000000);
761 spr_register(env, SPR_DBAT3L, "DBAT3L",
762 SPR_NOACCESS, SPR_NOACCESS,
763 &spr_read_dbat, &spr_write_dbatl,
764 0x00000000);
765 env->nb_BATs += 4;
766 #endif
767 }
768
769 /* BATs 4-7 */
770 static void gen_high_BATs (CPUPPCState *env)
771 {
772 #if !defined(CONFIG_USER_ONLY)
773 spr_register(env, SPR_IBAT4U, "IBAT4U",
774 SPR_NOACCESS, SPR_NOACCESS,
775 &spr_read_ibat_h, &spr_write_ibatu_h,
776 0x00000000);
777 spr_register(env, SPR_IBAT4L, "IBAT4L",
778 SPR_NOACCESS, SPR_NOACCESS,
779 &spr_read_ibat_h, &spr_write_ibatl_h,
780 0x00000000);
781 spr_register(env, SPR_IBAT5U, "IBAT5U",
782 SPR_NOACCESS, SPR_NOACCESS,
783 &spr_read_ibat_h, &spr_write_ibatu_h,
784 0x00000000);
785 spr_register(env, SPR_IBAT5L, "IBAT5L",
786 SPR_NOACCESS, SPR_NOACCESS,
787 &spr_read_ibat_h, &spr_write_ibatl_h,
788 0x00000000);
789 spr_register(env, SPR_IBAT6U, "IBAT6U",
790 SPR_NOACCESS, SPR_NOACCESS,
791 &spr_read_ibat_h, &spr_write_ibatu_h,
792 0x00000000);
793 spr_register(env, SPR_IBAT6L, "IBAT6L",
794 SPR_NOACCESS, SPR_NOACCESS,
795 &spr_read_ibat_h, &spr_write_ibatl_h,
796 0x00000000);
797 spr_register(env, SPR_IBAT7U, "IBAT7U",
798 SPR_NOACCESS, SPR_NOACCESS,
799 &spr_read_ibat_h, &spr_write_ibatu_h,
800 0x00000000);
801 spr_register(env, SPR_IBAT7L, "IBAT7L",
802 SPR_NOACCESS, SPR_NOACCESS,
803 &spr_read_ibat_h, &spr_write_ibatl_h,
804 0x00000000);
805 spr_register(env, SPR_DBAT4U, "DBAT4U",
806 SPR_NOACCESS, SPR_NOACCESS,
807 &spr_read_dbat_h, &spr_write_dbatu_h,
808 0x00000000);
809 spr_register(env, SPR_DBAT4L, "DBAT4L",
810 SPR_NOACCESS, SPR_NOACCESS,
811 &spr_read_dbat_h, &spr_write_dbatl_h,
812 0x00000000);
813 spr_register(env, SPR_DBAT5U, "DBAT5U",
814 SPR_NOACCESS, SPR_NOACCESS,
815 &spr_read_dbat_h, &spr_write_dbatu_h,
816 0x00000000);
817 spr_register(env, SPR_DBAT5L, "DBAT5L",
818 SPR_NOACCESS, SPR_NOACCESS,
819 &spr_read_dbat_h, &spr_write_dbatl_h,
820 0x00000000);
821 spr_register(env, SPR_DBAT6U, "DBAT6U",
822 SPR_NOACCESS, SPR_NOACCESS,
823 &spr_read_dbat_h, &spr_write_dbatu_h,
824 0x00000000);
825 spr_register(env, SPR_DBAT6L, "DBAT6L",
826 SPR_NOACCESS, SPR_NOACCESS,
827 &spr_read_dbat_h, &spr_write_dbatl_h,
828 0x00000000);
829 spr_register(env, SPR_DBAT7U, "DBAT7U",
830 SPR_NOACCESS, SPR_NOACCESS,
831 &spr_read_dbat_h, &spr_write_dbatu_h,
832 0x00000000);
833 spr_register(env, SPR_DBAT7L, "DBAT7L",
834 SPR_NOACCESS, SPR_NOACCESS,
835 &spr_read_dbat_h, &spr_write_dbatl_h,
836 0x00000000);
837 env->nb_BATs += 4;
838 #endif
839 }
840
841 /* Generic PowerPC time base */
842 static void gen_tbl (CPUPPCState *env)
843 {
844 spr_register(env, SPR_VTBL, "TBL",
845 &spr_read_tbl, SPR_NOACCESS,
846 &spr_read_tbl, SPR_NOACCESS,
847 0x00000000);
848 spr_register(env, SPR_TBL, "TBL",
849 &spr_read_tbl, SPR_NOACCESS,
850 &spr_read_tbl, &spr_write_tbl,
851 0x00000000);
852 spr_register(env, SPR_VTBU, "TBU",
853 &spr_read_tbu, SPR_NOACCESS,
854 &spr_read_tbu, SPR_NOACCESS,
855 0x00000000);
856 spr_register(env, SPR_TBU, "TBU",
857 &spr_read_tbu, SPR_NOACCESS,
858 &spr_read_tbu, &spr_write_tbu,
859 0x00000000);
860 }
861
862 /* Softare table search registers */
863 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
864 {
865 #if !defined(CONFIG_USER_ONLY)
866 env->nb_tlb = nb_tlbs;
867 env->nb_ways = nb_ways;
868 env->id_tlbs = 1;
869 env->tlb_type = TLB_6XX;
870 spr_register(env, SPR_DMISS, "DMISS",
871 SPR_NOACCESS, SPR_NOACCESS,
872 &spr_read_generic, SPR_NOACCESS,
873 0x00000000);
874 spr_register(env, SPR_DCMP, "DCMP",
875 SPR_NOACCESS, SPR_NOACCESS,
876 &spr_read_generic, SPR_NOACCESS,
877 0x00000000);
878 spr_register(env, SPR_HASH1, "HASH1",
879 SPR_NOACCESS, SPR_NOACCESS,
880 &spr_read_generic, SPR_NOACCESS,
881 0x00000000);
882 spr_register(env, SPR_HASH2, "HASH2",
883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_generic, SPR_NOACCESS,
885 0x00000000);
886 spr_register(env, SPR_IMISS, "IMISS",
887 SPR_NOACCESS, SPR_NOACCESS,
888 &spr_read_generic, SPR_NOACCESS,
889 0x00000000);
890 spr_register(env, SPR_ICMP, "ICMP",
891 SPR_NOACCESS, SPR_NOACCESS,
892 &spr_read_generic, SPR_NOACCESS,
893 0x00000000);
894 spr_register(env, SPR_RPA, "RPA",
895 SPR_NOACCESS, SPR_NOACCESS,
896 &spr_read_generic, &spr_write_generic,
897 0x00000000);
898 #endif
899 }
900
901 /* SPR common to MPC755 and G2 */
902 static void gen_spr_G2_755 (CPUPPCState *env)
903 {
904 /* SGPRs */
905 spr_register(env, SPR_SPRG4, "SPRG4",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, &spr_write_generic,
908 0x00000000);
909 spr_register(env, SPR_SPRG5, "SPRG5",
910 SPR_NOACCESS, SPR_NOACCESS,
911 &spr_read_generic, &spr_write_generic,
912 0x00000000);
913 spr_register(env, SPR_SPRG6, "SPRG6",
914 SPR_NOACCESS, SPR_NOACCESS,
915 &spr_read_generic, &spr_write_generic,
916 0x00000000);
917 spr_register(env, SPR_SPRG7, "SPRG7",
918 SPR_NOACCESS, SPR_NOACCESS,
919 &spr_read_generic, &spr_write_generic,
920 0x00000000);
921 }
922
923 /* SPR common to all 7xx PowerPC implementations */
924 static void gen_spr_7xx (CPUPPCState *env)
925 {
926 /* Breakpoints */
927 /* XXX : not implemented */
928 spr_register(env, SPR_DABR, "DABR",
929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_generic, &spr_write_generic,
931 0x00000000);
932 /* XXX : not implemented */
933 spr_register(env, SPR_IABR, "IABR",
934 SPR_NOACCESS, SPR_NOACCESS,
935 &spr_read_generic, &spr_write_generic,
936 0x00000000);
937 /* Cache management */
938 /* XXX : not implemented */
939 spr_register(env, SPR_ICTC, "ICTC",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943 /* Performance monitors */
944 /* XXX : not implemented */
945 spr_register(env, SPR_MMCR0, "MMCR0",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_generic, &spr_write_generic,
948 0x00000000);
949 /* XXX : not implemented */
950 spr_register(env, SPR_MMCR1, "MMCR1",
951 SPR_NOACCESS, SPR_NOACCESS,
952 &spr_read_generic, &spr_write_generic,
953 0x00000000);
954 /* XXX : not implemented */
955 spr_register(env, SPR_PMC1, "PMC1",
956 SPR_NOACCESS, SPR_NOACCESS,
957 &spr_read_generic, &spr_write_generic,
958 0x00000000);
959 /* XXX : not implemented */
960 spr_register(env, SPR_PMC2, "PMC2",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, &spr_write_generic,
963 0x00000000);
964 /* XXX : not implemented */
965 spr_register(env, SPR_PMC3, "PMC3",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, &spr_write_generic,
968 0x00000000);
969 /* XXX : not implemented */
970 spr_register(env, SPR_PMC4, "PMC4",
971 SPR_NOACCESS, SPR_NOACCESS,
972 &spr_read_generic, &spr_write_generic,
973 0x00000000);
974 /* XXX : not implemented */
975 spr_register(env, SPR_SIAR, "SIAR",
976 SPR_NOACCESS, SPR_NOACCESS,
977 &spr_read_generic, SPR_NOACCESS,
978 0x00000000);
979 /* XXX : not implemented */
980 spr_register(env, SPR_UMMCR0, "UMMCR0",
981 &spr_read_ureg, SPR_NOACCESS,
982 &spr_read_ureg, SPR_NOACCESS,
983 0x00000000);
984 /* XXX : not implemented */
985 spr_register(env, SPR_UMMCR1, "UMMCR1",
986 &spr_read_ureg, SPR_NOACCESS,
987 &spr_read_ureg, SPR_NOACCESS,
988 0x00000000);
989 /* XXX : not implemented */
990 spr_register(env, SPR_UPMC1, "UPMC1",
991 &spr_read_ureg, SPR_NOACCESS,
992 &spr_read_ureg, SPR_NOACCESS,
993 0x00000000);
994 /* XXX : not implemented */
995 spr_register(env, SPR_UPMC2, "UPMC2",
996 &spr_read_ureg, SPR_NOACCESS,
997 &spr_read_ureg, SPR_NOACCESS,
998 0x00000000);
999 /* XXX : not implemented */
1000 spr_register(env, SPR_UPMC3, "UPMC3",
1001 &spr_read_ureg, SPR_NOACCESS,
1002 &spr_read_ureg, SPR_NOACCESS,
1003 0x00000000);
1004 /* XXX : not implemented */
1005 spr_register(env, SPR_UPMC4, "UPMC4",
1006 &spr_read_ureg, SPR_NOACCESS,
1007 &spr_read_ureg, SPR_NOACCESS,
1008 0x00000000);
1009 /* XXX : not implemented */
1010 spr_register(env, SPR_USIAR, "USIAR",
1011 &spr_read_ureg, SPR_NOACCESS,
1012 &spr_read_ureg, SPR_NOACCESS,
1013 0x00000000);
1014 /* External access control */
1015 /* XXX : not implemented */
1016 spr_register(env, SPR_EAR, "EAR",
1017 SPR_NOACCESS, SPR_NOACCESS,
1018 &spr_read_generic, &spr_write_generic,
1019 0x00000000);
1020 }
1021
1022 static void gen_spr_thrm (CPUPPCState *env)
1023 {
1024 /* Thermal management */
1025 /* XXX : not implemented */
1026 spr_register(env, SPR_THRM1, "THRM1",
1027 SPR_NOACCESS, SPR_NOACCESS,
1028 &spr_read_generic, &spr_write_generic,
1029 0x00000000);
1030 /* XXX : not implemented */
1031 spr_register(env, SPR_THRM2, "THRM2",
1032 SPR_NOACCESS, SPR_NOACCESS,
1033 &spr_read_generic, &spr_write_generic,
1034 0x00000000);
1035 /* XXX : not implemented */
1036 spr_register(env, SPR_THRM3, "THRM3",
1037 SPR_NOACCESS, SPR_NOACCESS,
1038 &spr_read_generic, &spr_write_generic,
1039 0x00000000);
1040 }
1041
1042 /* SPR specific to PowerPC 604 implementation */
1043 static void gen_spr_604 (CPUPPCState *env)
1044 {
1045 /* Processor identification */
1046 spr_register(env, SPR_PIR, "PIR",
1047 SPR_NOACCESS, SPR_NOACCESS,
1048 &spr_read_generic, &spr_write_pir,
1049 0x00000000);
1050 /* Breakpoints */
1051 /* XXX : not implemented */
1052 spr_register(env, SPR_IABR, "IABR",
1053 SPR_NOACCESS, SPR_NOACCESS,
1054 &spr_read_generic, &spr_write_generic,
1055 0x00000000);
1056 /* XXX : not implemented */
1057 spr_register(env, SPR_DABR, "DABR",
1058 SPR_NOACCESS, SPR_NOACCESS,
1059 &spr_read_generic, &spr_write_generic,
1060 0x00000000);
1061 /* Performance counters */
1062 /* XXX : not implemented */
1063 spr_register(env, SPR_MMCR0, "MMCR0",
1064 SPR_NOACCESS, SPR_NOACCESS,
1065 &spr_read_generic, &spr_write_generic,
1066 0x00000000);
1067 /* XXX : not implemented */
1068 spr_register(env, SPR_PMC1, "PMC1",
1069 SPR_NOACCESS, SPR_NOACCESS,
1070 &spr_read_generic, &spr_write_generic,
1071 0x00000000);
1072 /* XXX : not implemented */
1073 spr_register(env, SPR_PMC2, "PMC2",
1074 SPR_NOACCESS, SPR_NOACCESS,
1075 &spr_read_generic, &spr_write_generic,
1076 0x00000000);
1077 /* XXX : not implemented */
1078 spr_register(env, SPR_SIAR, "SIAR",
1079 SPR_NOACCESS, SPR_NOACCESS,
1080 &spr_read_generic, SPR_NOACCESS,
1081 0x00000000);
1082 /* XXX : not implemented */
1083 spr_register(env, SPR_SDA, "SDA",
1084 SPR_NOACCESS, SPR_NOACCESS,
1085 &spr_read_generic, SPR_NOACCESS,
1086 0x00000000);
1087 /* External access control */
1088 /* XXX : not implemented */
1089 spr_register(env, SPR_EAR, "EAR",
1090 SPR_NOACCESS, SPR_NOACCESS,
1091 &spr_read_generic, &spr_write_generic,
1092 0x00000000);
1093 }
1094
1095 /* SPR specific to PowerPC 603 implementation */
1096 static void gen_spr_603 (CPUPPCState *env)
1097 {
1098 /* External access control */
1099 /* XXX : not implemented */
1100 spr_register(env, SPR_EAR, "EAR",
1101 SPR_NOACCESS, SPR_NOACCESS,
1102 &spr_read_generic, &spr_write_generic,
1103 0x00000000);
1104 }
1105
1106 /* SPR specific to PowerPC G2 implementation */
1107 static void gen_spr_G2 (CPUPPCState *env)
1108 {
1109 /* Memory base address */
1110 /* MBAR */
1111 /* XXX : not implemented */
1112 spr_register(env, SPR_MBAR, "MBAR",
1113 SPR_NOACCESS, SPR_NOACCESS,
1114 &spr_read_generic, &spr_write_generic,
1115 0x00000000);
1116 /* Exception processing */
1117 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1118 SPR_NOACCESS, SPR_NOACCESS,
1119 &spr_read_generic, &spr_write_generic,
1120 0x00000000);
1121 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1122 SPR_NOACCESS, SPR_NOACCESS,
1123 &spr_read_generic, &spr_write_generic,
1124 0x00000000);
1125 /* Breakpoints */
1126 /* XXX : not implemented */
1127 spr_register(env, SPR_DABR, "DABR",
1128 SPR_NOACCESS, SPR_NOACCESS,
1129 &spr_read_generic, &spr_write_generic,
1130 0x00000000);
1131 /* XXX : not implemented */
1132 spr_register(env, SPR_DABR2, "DABR2",
1133 SPR_NOACCESS, SPR_NOACCESS,
1134 &spr_read_generic, &spr_write_generic,
1135 0x00000000);
1136 /* XXX : not implemented */
1137 spr_register(env, SPR_IABR, "IABR",
1138 SPR_NOACCESS, SPR_NOACCESS,
1139 &spr_read_generic, &spr_write_generic,
1140 0x00000000);
1141 /* XXX : not implemented */
1142 spr_register(env, SPR_IABR2, "IABR2",
1143 SPR_NOACCESS, SPR_NOACCESS,
1144 &spr_read_generic, &spr_write_generic,
1145 0x00000000);
1146 /* XXX : not implemented */
1147 spr_register(env, SPR_IBCR, "IBCR",
1148 SPR_NOACCESS, SPR_NOACCESS,
1149 &spr_read_generic, &spr_write_generic,
1150 0x00000000);
1151 /* XXX : not implemented */
1152 spr_register(env, SPR_DBCR, "DBCR",
1153 SPR_NOACCESS, SPR_NOACCESS,
1154 &spr_read_generic, &spr_write_generic,
1155 0x00000000);
1156 }
1157
1158 /* SPR specific to PowerPC 602 implementation */
1159 static void gen_spr_602 (CPUPPCState *env)
1160 {
1161 /* ESA registers */
1162 /* XXX : not implemented */
1163 spr_register(env, SPR_SER, "SER",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_generic, &spr_write_generic,
1166 0x00000000);
1167 /* XXX : not implemented */
1168 spr_register(env, SPR_SEBR, "SEBR",
1169 SPR_NOACCESS, SPR_NOACCESS,
1170 &spr_read_generic, &spr_write_generic,
1171 0x00000000);
1172 /* XXX : not implemented */
1173 spr_register(env, SPR_ESASRR, "ESASRR",
1174 SPR_NOACCESS, SPR_NOACCESS,
1175 &spr_read_generic, &spr_write_generic,
1176 0x00000000);
1177 /* Floating point status */
1178 /* XXX : not implemented */
1179 spr_register(env, SPR_SP, "SP",
1180 SPR_NOACCESS, SPR_NOACCESS,
1181 &spr_read_generic, &spr_write_generic,
1182 0x00000000);
1183 /* XXX : not implemented */
1184 spr_register(env, SPR_LT, "LT",
1185 SPR_NOACCESS, SPR_NOACCESS,
1186 &spr_read_generic, &spr_write_generic,
1187 0x00000000);
1188 /* Watchdog timer */
1189 /* XXX : not implemented */
1190 spr_register(env, SPR_TCR, "TCR",
1191 SPR_NOACCESS, SPR_NOACCESS,
1192 &spr_read_generic, &spr_write_generic,
1193 0x00000000);
1194 /* Interrupt base */
1195 spr_register(env, SPR_IBR, "IBR",
1196 SPR_NOACCESS, SPR_NOACCESS,
1197 &spr_read_generic, &spr_write_generic,
1198 0x00000000);
1199 /* XXX : not implemented */
1200 spr_register(env, SPR_IABR, "IABR",
1201 SPR_NOACCESS, SPR_NOACCESS,
1202 &spr_read_generic, &spr_write_generic,
1203 0x00000000);
1204 }
1205
1206 /* SPR specific to PowerPC 601 implementation */
1207 static void gen_spr_601 (CPUPPCState *env)
1208 {
1209 /* Multiplication/division register */
1210 /* MQ */
1211 spr_register(env, SPR_MQ, "MQ",
1212 &spr_read_generic, &spr_write_generic,
1213 &spr_read_generic, &spr_write_generic,
1214 0x00000000);
1215 /* RTC registers */
1216 spr_register(env, SPR_601_RTCU, "RTCU",
1217 SPR_NOACCESS, SPR_NOACCESS,
1218 SPR_NOACCESS, &spr_write_601_rtcu,
1219 0x00000000);
1220 spr_register(env, SPR_601_VRTCU, "RTCU",
1221 &spr_read_601_rtcu, SPR_NOACCESS,
1222 &spr_read_601_rtcu, SPR_NOACCESS,
1223 0x00000000);
1224 spr_register(env, SPR_601_RTCL, "RTCL",
1225 SPR_NOACCESS, SPR_NOACCESS,
1226 SPR_NOACCESS, &spr_write_601_rtcl,
1227 0x00000000);
1228 spr_register(env, SPR_601_VRTCL, "RTCL",
1229 &spr_read_601_rtcl, SPR_NOACCESS,
1230 &spr_read_601_rtcl, SPR_NOACCESS,
1231 0x00000000);
1232 /* Timer */
1233 #if 0 /* ? */
1234 spr_register(env, SPR_601_UDECR, "UDECR",
1235 &spr_read_decr, SPR_NOACCESS,
1236 &spr_read_decr, SPR_NOACCESS,
1237 0x00000000);
1238 #endif
1239 /* External access control */
1240 /* XXX : not implemented */
1241 spr_register(env, SPR_EAR, "EAR",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_generic, &spr_write_generic,
1244 0x00000000);
1245 /* Memory management */
1246 #if !defined(CONFIG_USER_ONLY)
1247 spr_register(env, SPR_IBAT0U, "IBAT0U",
1248 SPR_NOACCESS, SPR_NOACCESS,
1249 &spr_read_601_ubat, &spr_write_601_ubatu,
1250 0x00000000);
1251 spr_register(env, SPR_IBAT0L, "IBAT0L",
1252 SPR_NOACCESS, SPR_NOACCESS,
1253 &spr_read_601_ubat, &spr_write_601_ubatl,
1254 0x00000000);
1255 spr_register(env, SPR_IBAT1U, "IBAT1U",
1256 SPR_NOACCESS, SPR_NOACCESS,
1257 &spr_read_601_ubat, &spr_write_601_ubatu,
1258 0x00000000);
1259 spr_register(env, SPR_IBAT1L, "IBAT1L",
1260 SPR_NOACCESS, SPR_NOACCESS,
1261 &spr_read_601_ubat, &spr_write_601_ubatl,
1262 0x00000000);
1263 spr_register(env, SPR_IBAT2U, "IBAT2U",
1264 SPR_NOACCESS, SPR_NOACCESS,
1265 &spr_read_601_ubat, &spr_write_601_ubatu,
1266 0x00000000);
1267 spr_register(env, SPR_IBAT2L, "IBAT2L",
1268 SPR_NOACCESS, SPR_NOACCESS,
1269 &spr_read_601_ubat, &spr_write_601_ubatl,
1270 0x00000000);
1271 spr_register(env, SPR_IBAT3U, "IBAT3U",
1272 SPR_NOACCESS, SPR_NOACCESS,
1273 &spr_read_601_ubat, &spr_write_601_ubatu,
1274 0x00000000);
1275 spr_register(env, SPR_IBAT3L, "IBAT3L",
1276 SPR_NOACCESS, SPR_NOACCESS,
1277 &spr_read_601_ubat, &spr_write_601_ubatl,
1278 0x00000000);
1279 env->nb_BATs = 4;
1280 #endif
1281 }
1282
1283 static void gen_spr_74xx (CPUPPCState *env)
1284 {
1285 /* Processor identification */
1286 spr_register(env, SPR_PIR, "PIR",
1287 SPR_NOACCESS, SPR_NOACCESS,
1288 &spr_read_generic, &spr_write_pir,
1289 0x00000000);
1290 /* XXX : not implemented */
1291 spr_register(env, SPR_MMCR2, "MMCR2",
1292 SPR_NOACCESS, SPR_NOACCESS,
1293 &spr_read_generic, &spr_write_generic,
1294 0x00000000);
1295 /* XXX : not implemented */
1296 spr_register(env, SPR_UMMCR2, "UMMCR2",
1297 &spr_read_ureg, SPR_NOACCESS,
1298 &spr_read_ureg, SPR_NOACCESS,
1299 0x00000000);
1300 /* XXX: not implemented */
1301 spr_register(env, SPR_BAMR, "BAMR",
1302 SPR_NOACCESS, SPR_NOACCESS,
1303 &spr_read_generic, &spr_write_generic,
1304 0x00000000);
1305 /* XXX : not implemented */
1306 spr_register(env, SPR_MSSCR0, "MSSCR0",
1307 SPR_NOACCESS, SPR_NOACCESS,
1308 &spr_read_generic, &spr_write_generic,
1309 0x00000000);
1310 /* Hardware implementation registers */
1311 /* XXX : not implemented */
1312 spr_register(env, SPR_HID0, "HID0",
1313 SPR_NOACCESS, SPR_NOACCESS,
1314 &spr_read_generic, &spr_write_generic,
1315 0x00000000);
1316 /* XXX : not implemented */
1317 spr_register(env, SPR_HID1, "HID1",
1318 SPR_NOACCESS, SPR_NOACCESS,
1319 &spr_read_generic, &spr_write_generic,
1320 0x00000000);
1321 /* Altivec */
1322 spr_register(env, SPR_VRSAVE, "VRSAVE",
1323 &spr_read_generic, &spr_write_generic,
1324 &spr_read_generic, &spr_write_generic,
1325 0x00000000);
1326 /* XXX : not implemented */
1327 spr_register(env, SPR_L2CR, "L2CR",
1328 SPR_NOACCESS, SPR_NOACCESS,
1329 &spr_read_generic, &spr_write_generic,
1330 0x00000000);
1331 /* Not strictly an SPR */
1332 vscr_init(env, 0x00010000);
1333 }
1334
1335 static void gen_l3_ctrl (CPUPPCState *env)
1336 {
1337 /* L3CR */
1338 /* XXX : not implemented */
1339 spr_register(env, SPR_L3CR, "L3CR",
1340 SPR_NOACCESS, SPR_NOACCESS,
1341 &spr_read_generic, &spr_write_generic,
1342 0x00000000);
1343 /* L3ITCR0 */
1344 /* XXX : not implemented */
1345 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1346 SPR_NOACCESS, SPR_NOACCESS,
1347 &spr_read_generic, &spr_write_generic,
1348 0x00000000);
1349 /* L3PM */
1350 /* XXX : not implemented */
1351 spr_register(env, SPR_L3PM, "L3PM",
1352 SPR_NOACCESS, SPR_NOACCESS,
1353 &spr_read_generic, &spr_write_generic,
1354 0x00000000);
1355 }
1356
1357 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1358 {
1359 #if !defined(CONFIG_USER_ONLY)
1360 env->nb_tlb = nb_tlbs;
1361 env->nb_ways = nb_ways;
1362 env->id_tlbs = 1;
1363 env->tlb_type = TLB_6XX;
1364 /* XXX : not implemented */
1365 spr_register(env, SPR_PTEHI, "PTEHI",
1366 SPR_NOACCESS, SPR_NOACCESS,
1367 &spr_read_generic, &spr_write_generic,
1368 0x00000000);
1369 /* XXX : not implemented */
1370 spr_register(env, SPR_PTELO, "PTELO",
1371 SPR_NOACCESS, SPR_NOACCESS,
1372 &spr_read_generic, &spr_write_generic,
1373 0x00000000);
1374 /* XXX : not implemented */
1375 spr_register(env, SPR_TLBMISS, "TLBMISS",
1376 SPR_NOACCESS, SPR_NOACCESS,
1377 &spr_read_generic, &spr_write_generic,
1378 0x00000000);
1379 #endif
1380 }
1381
1382 #if !defined(CONFIG_USER_ONLY)
1383 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1384 {
1385 TCGv t0 = tcg_temp_new();
1386
1387 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1388 gen_store_spr(sprn, t0);
1389 tcg_temp_free(t0);
1390 }
1391
1392 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1393 {
1394 TCGv_i32 t0 = tcg_const_i32(sprn);
1395 gen_helper_booke206_tlbflush(cpu_env, t0);
1396 tcg_temp_free_i32(t0);
1397 }
1398
1399 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1400 {
1401 TCGv_i32 t0 = tcg_const_i32(sprn);
1402 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1403 tcg_temp_free_i32(t0);
1404 }
1405 #endif
1406
1407 static void gen_spr_usprgh (CPUPPCState *env)
1408 {
1409 spr_register(env, SPR_USPRG4, "USPRG4",
1410 &spr_read_ureg, SPR_NOACCESS,
1411 &spr_read_ureg, SPR_NOACCESS,
1412 0x00000000);
1413 spr_register(env, SPR_USPRG5, "USPRG5",
1414 &spr_read_ureg, SPR_NOACCESS,
1415 &spr_read_ureg, SPR_NOACCESS,
1416 0x00000000);
1417 spr_register(env, SPR_USPRG6, "USPRG6",
1418 &spr_read_ureg, SPR_NOACCESS,
1419 &spr_read_ureg, SPR_NOACCESS,
1420 0x00000000);
1421 spr_register(env, SPR_USPRG7, "USPRG7",
1422 &spr_read_ureg, SPR_NOACCESS,
1423 &spr_read_ureg, SPR_NOACCESS,
1424 0x00000000);
1425 }
1426
1427 /* PowerPC BookE SPR */
1428 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1429 {
1430 const char *ivor_names[64] = {
1431 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1432 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1433 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1434 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1435 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1436 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1437 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1438 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1439 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1440 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1441 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1442 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1443 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1444 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1445 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1446 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1447 };
1448 #define SPR_BOOKE_IVORxx (-1)
1449 int ivor_sprn[64] = {
1450 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1451 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1452 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1453 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1454 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1455 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1456 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1457 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1458 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1459 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1460 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1461 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1462 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1463 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1464 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1465 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1466 };
1467 int i;
1468
1469 /* Interrupt processing */
1470 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1471 SPR_NOACCESS, SPR_NOACCESS,
1472 &spr_read_generic, &spr_write_generic,
1473 0x00000000);
1474 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1475 SPR_NOACCESS, SPR_NOACCESS,
1476 &spr_read_generic, &spr_write_generic,
1477 0x00000000);
1478 /* Debug */
1479 /* XXX : not implemented */
1480 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1481 SPR_NOACCESS, SPR_NOACCESS,
1482 &spr_read_generic, &spr_write_generic,
1483 0x00000000);
1484 /* XXX : not implemented */
1485 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1486 SPR_NOACCESS, SPR_NOACCESS,
1487 &spr_read_generic, &spr_write_generic,
1488 0x00000000);
1489 /* XXX : not implemented */
1490 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1491 SPR_NOACCESS, SPR_NOACCESS,
1492 &spr_read_generic, &spr_write_generic,
1493 0x00000000);
1494 /* XXX : not implemented */
1495 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1496 SPR_NOACCESS, SPR_NOACCESS,
1497 &spr_read_generic, &spr_write_generic,
1498 0x00000000);
1499 /* XXX : not implemented */
1500 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1501 SPR_NOACCESS, SPR_NOACCESS,
1502 &spr_read_generic, &spr_write_40x_dbcr0,
1503 0x00000000);
1504 /* XXX : not implemented */
1505 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1506 SPR_NOACCESS, SPR_NOACCESS,
1507 &spr_read_generic, &spr_write_generic,
1508 0x00000000);
1509 /* XXX : not implemented */
1510 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1511 SPR_NOACCESS, SPR_NOACCESS,
1512 &spr_read_generic, &spr_write_generic,
1513 0x00000000);
1514 /* XXX : not implemented */
1515 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1516 SPR_NOACCESS, SPR_NOACCESS,
1517 &spr_read_generic, &spr_write_clear,
1518 0x00000000);
1519 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1520 SPR_NOACCESS, SPR_NOACCESS,
1521 &spr_read_generic, &spr_write_generic,
1522 0x00000000);
1523 spr_register(env, SPR_BOOKE_ESR, "ESR",
1524 SPR_NOACCESS, SPR_NOACCESS,
1525 &spr_read_generic, &spr_write_generic,
1526 0x00000000);
1527 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1528 SPR_NOACCESS, SPR_NOACCESS,
1529 &spr_read_generic, &spr_write_excp_prefix,
1530 0x00000000);
1531 /* Exception vectors */
1532 for (i = 0; i < 64; i++) {
1533 if (ivor_mask & (1ULL << i)) {
1534 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1535 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1536 exit(1);
1537 }
1538 spr_register(env, ivor_sprn[i], ivor_names[i],
1539 SPR_NOACCESS, SPR_NOACCESS,
1540 &spr_read_generic, &spr_write_excp_vector,
1541 0x00000000);
1542 }
1543 }
1544 spr_register(env, SPR_BOOKE_PID, "PID",
1545 SPR_NOACCESS, SPR_NOACCESS,
1546 &spr_read_generic, &spr_write_booke_pid,
1547 0x00000000);
1548 spr_register(env, SPR_BOOKE_TCR, "TCR",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_booke_tcr,
1551 0x00000000);
1552 spr_register(env, SPR_BOOKE_TSR, "TSR",
1553 SPR_NOACCESS, SPR_NOACCESS,
1554 &spr_read_generic, &spr_write_booke_tsr,
1555 0x00000000);
1556 /* Timer */
1557 spr_register(env, SPR_DECR, "DECR",
1558 SPR_NOACCESS, SPR_NOACCESS,
1559 &spr_read_decr, &spr_write_decr,
1560 0x00000000);
1561 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1562 SPR_NOACCESS, SPR_NOACCESS,
1563 SPR_NOACCESS, &spr_write_generic,
1564 0x00000000);
1565 /* SPRGs */
1566 spr_register(env, SPR_USPRG0, "USPRG0",
1567 &spr_read_generic, &spr_write_generic,
1568 &spr_read_generic, &spr_write_generic,
1569 0x00000000);
1570 spr_register(env, SPR_SPRG4, "SPRG4",
1571 SPR_NOACCESS, SPR_NOACCESS,
1572 &spr_read_generic, &spr_write_generic,
1573 0x00000000);
1574 spr_register(env, SPR_SPRG5, "SPRG5",
1575 SPR_NOACCESS, SPR_NOACCESS,
1576 &spr_read_generic, &spr_write_generic,
1577 0x00000000);
1578 spr_register(env, SPR_SPRG6, "SPRG6",
1579 SPR_NOACCESS, SPR_NOACCESS,
1580 &spr_read_generic, &spr_write_generic,
1581 0x00000000);
1582 spr_register(env, SPR_SPRG7, "SPRG7",
1583 SPR_NOACCESS, SPR_NOACCESS,
1584 &spr_read_generic, &spr_write_generic,
1585 0x00000000);
1586 }
1587
1588 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1589 uint32_t maxsize, uint32_t flags,
1590 uint32_t nentries)
1591 {
1592 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1593 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1594 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1595 flags | nentries;
1596 }
1597
1598 /* BookE 2.06 storage control registers */
1599 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1600 uint32_t *tlbncfg)
1601 {
1602 #if !defined(CONFIG_USER_ONLY)
1603 const char *mas_names[8] = {
1604 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1605 };
1606 int mas_sprn[8] = {
1607 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1608 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1609 };
1610 int i;
1611
1612 /* TLB assist registers */
1613 /* XXX : not implemented */
1614 for (i = 0; i < 8; i++) {
1615 void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1616 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1617 uea_write = &spr_write_generic;
1618 }
1619 if (mas_mask & (1 << i)) {
1620 spr_register(env, mas_sprn[i], mas_names[i],
1621 SPR_NOACCESS, SPR_NOACCESS,
1622 &spr_read_generic, uea_write,
1623 0x00000000);
1624 }
1625 }
1626 if (env->nb_pids > 1) {
1627 /* XXX : not implemented */
1628 spr_register(env, SPR_BOOKE_PID1, "PID1",
1629 SPR_NOACCESS, SPR_NOACCESS,
1630 &spr_read_generic, &spr_write_booke_pid,
1631 0x00000000);
1632 }
1633 if (env->nb_pids > 2) {
1634 /* XXX : not implemented */
1635 spr_register(env, SPR_BOOKE_PID2, "PID2",
1636 SPR_NOACCESS, SPR_NOACCESS,
1637 &spr_read_generic, &spr_write_booke_pid,
1638 0x00000000);
1639 }
1640 /* XXX : not implemented */
1641 spr_register(env, SPR_MMUCFG, "MMUCFG",
1642 SPR_NOACCESS, SPR_NOACCESS,
1643 &spr_read_generic, SPR_NOACCESS,
1644 0x00000000); /* TOFIX */
1645 switch (env->nb_ways) {
1646 case 4:
1647 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1648 SPR_NOACCESS, SPR_NOACCESS,
1649 &spr_read_generic, SPR_NOACCESS,
1650 tlbncfg[3]);
1651 /* Fallthru */
1652 case 3:
1653 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1654 SPR_NOACCESS, SPR_NOACCESS,
1655 &spr_read_generic, SPR_NOACCESS,
1656 tlbncfg[2]);
1657 /* Fallthru */
1658 case 2:
1659 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1660 SPR_NOACCESS, SPR_NOACCESS,
1661 &spr_read_generic, SPR_NOACCESS,
1662 tlbncfg[1]);
1663 /* Fallthru */
1664 case 1:
1665 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1666 SPR_NOACCESS, SPR_NOACCESS,
1667 &spr_read_generic, SPR_NOACCESS,
1668 tlbncfg[0]);
1669 /* Fallthru */
1670 case 0:
1671 default:
1672 break;
1673 }
1674 #endif
1675
1676 gen_spr_usprgh(env);
1677 }
1678
1679 /* SPR specific to PowerPC 440 implementation */
1680 static void gen_spr_440 (CPUPPCState *env)
1681 {
1682 /* Cache control */
1683 /* XXX : not implemented */
1684 spr_register(env, SPR_440_DNV0, "DNV0",
1685 SPR_NOACCESS, SPR_NOACCESS,
1686 &spr_read_generic, &spr_write_generic,
1687 0x00000000);
1688 /* XXX : not implemented */
1689 spr_register(env, SPR_440_DNV1, "DNV1",
1690 SPR_NOACCESS, SPR_NOACCESS,
1691 &spr_read_generic, &spr_write_generic,
1692 0x00000000);
1693 /* XXX : not implemented */
1694 spr_register(env, SPR_440_DNV2, "DNV2",
1695 SPR_NOACCESS, SPR_NOACCESS,
1696 &spr_read_generic, &spr_write_generic,
1697 0x00000000);
1698 /* XXX : not implemented */
1699 spr_register(env, SPR_440_DNV3, "DNV3",
1700 SPR_NOACCESS, SPR_NOACCESS,
1701 &spr_read_generic, &spr_write_generic,
1702 0x00000000);
1703 /* XXX : not implemented */
1704 spr_register(env, SPR_440_DTV0, "DTV0",
1705 SPR_NOACCESS, SPR_NOACCESS,
1706 &spr_read_generic, &spr_write_generic,
1707 0x00000000);
1708 /* XXX : not implemented */
1709 spr_register(env, SPR_440_DTV1, "DTV1",
1710 SPR_NOACCESS, SPR_NOACCESS,
1711 &spr_read_generic, &spr_write_generic,
1712 0x00000000);
1713 /* XXX : not implemented */
1714 spr_register(env, SPR_440_DTV2, "DTV2",
1715 SPR_NOACCESS, SPR_NOACCESS,
1716 &spr_read_generic, &spr_write_generic,
1717 0x00000000);
1718 /* XXX : not implemented */
1719 spr_register(env, SPR_440_DTV3, "DTV3",
1720 SPR_NOACCESS, SPR_NOACCESS,
1721 &spr_read_generic, &spr_write_generic,
1722 0x00000000);
1723 /* XXX : not implemented */
1724 spr_register(env, SPR_440_DVLIM, "DVLIM",
1725 SPR_NOACCESS, SPR_NOACCESS,
1726 &spr_read_generic, &spr_write_generic,
1727 0x00000000);
1728 /* XXX : not implemented */
1729 spr_register(env, SPR_440_INV0, "INV0",
1730 SPR_NOACCESS, SPR_NOACCESS,
1731 &spr_read_generic, &spr_write_generic,
1732 0x00000000);
1733 /* XXX : not implemented */
1734 spr_register(env, SPR_440_INV1, "INV1",
1735 SPR_NOACCESS, SPR_NOACCESS,
1736 &spr_read_generic, &spr_write_generic,
1737 0x00000000);
1738 /* XXX : not implemented */
1739 spr_register(env, SPR_440_INV2, "INV2",
1740 SPR_NOACCESS, SPR_NOACCESS,
1741 &spr_read_generic, &spr_write_generic,
1742 0x00000000);
1743 /* XXX : not implemented */
1744 spr_register(env, SPR_440_INV3, "INV3",
1745 SPR_NOACCESS, SPR_NOACCESS,
1746 &spr_read_generic, &spr_write_generic,
1747 0x00000000);
1748 /* XXX : not implemented */
1749 spr_register(env, SPR_440_ITV0, "ITV0",
1750 SPR_NOACCESS, SPR_NOACCESS,
1751 &spr_read_generic, &spr_write_generic,
1752 0x00000000);
1753 /* XXX : not implemented */
1754 spr_register(env, SPR_440_ITV1, "ITV1",
1755 SPR_NOACCESS, SPR_NOACCESS,
1756 &spr_read_generic, &spr_write_generic,
1757 0x00000000);
1758 /* XXX : not implemented */
1759 spr_register(env, SPR_440_ITV2, "ITV2",
1760 SPR_NOACCESS, SPR_NOACCESS,
1761 &spr_read_generic, &spr_write_generic,
1762 0x00000000);
1763 /* XXX : not implemented */
1764 spr_register(env, SPR_440_ITV3, "ITV3",
1765 SPR_NOACCESS, SPR_NOACCESS,
1766 &spr_read_generic, &spr_write_generic,
1767 0x00000000);
1768 /* XXX : not implemented */
1769 spr_register(env, SPR_440_IVLIM, "IVLIM",
1770 SPR_NOACCESS, SPR_NOACCESS,
1771 &spr_read_generic, &spr_write_generic,
1772 0x00000000);
1773 /* Cache debug */
1774 /* XXX : not implemented */
1775 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1776 SPR_NOACCESS, SPR_NOACCESS,
1777 &spr_read_generic, SPR_NOACCESS,
1778 0x00000000);
1779 /* XXX : not implemented */
1780 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1781 SPR_NOACCESS, SPR_NOACCESS,
1782 &spr_read_generic, SPR_NOACCESS,
1783 0x00000000);
1784 /* XXX : not implemented */
1785 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1786 SPR_NOACCESS, SPR_NOACCESS,
1787 &spr_read_generic, SPR_NOACCESS,
1788 0x00000000);
1789 /* XXX : not implemented */
1790 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1791 SPR_NOACCESS, SPR_NOACCESS,
1792 &spr_read_generic, SPR_NOACCESS,
1793 0x00000000);
1794 /* XXX : not implemented */
1795 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1796 SPR_NOACCESS, SPR_NOACCESS,
1797 &spr_read_generic, SPR_NOACCESS,
1798 0x00000000);
1799 /* XXX : not implemented */
1800 spr_register(env, SPR_440_DBDR, "DBDR",
1801 SPR_NOACCESS, SPR_NOACCESS,
1802 &spr_read_generic, &spr_write_generic,
1803 0x00000000);
1804 /* Processor control */
1805 spr_register(env, SPR_4xx_CCR0, "CCR0",
1806 SPR_NOACCESS, SPR_NOACCESS,
1807 &spr_read_generic, &spr_write_generic,
1808 0x00000000);
1809 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1810 SPR_NOACCESS, SPR_NOACCESS,
1811 &spr_read_generic, SPR_NOACCESS,
1812 0x00000000);
1813 /* Storage control */
1814 spr_register(env, SPR_440_MMUCR, "MMUCR",
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_generic, &spr_write_generic,
1817 0x00000000);
1818 }
1819
1820 /* SPR shared between PowerPC 40x implementations */
1821 static void gen_spr_40x (CPUPPCState *env)
1822 {
1823 /* Cache */
1824 /* not emulated, as QEMU do not emulate caches */
1825 spr_register(env, SPR_40x_DCCR, "DCCR",
1826 SPR_NOACCESS, SPR_NOACCESS,
1827 &spr_read_generic, &spr_write_generic,
1828 0x00000000);
1829 /* not emulated, as QEMU do not emulate caches */
1830 spr_register(env, SPR_40x_ICCR, "ICCR",
1831 SPR_NOACCESS, SPR_NOACCESS,
1832 &spr_read_generic, &spr_write_generic,
1833 0x00000000);
1834 /* not emulated, as QEMU do not emulate caches */
1835 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1836 SPR_NOACCESS, SPR_NOACCESS,
1837 &spr_read_generic, SPR_NOACCESS,
1838 0x00000000);
1839 /* Exception */
1840 spr_register(env, SPR_40x_DEAR, "DEAR",
1841 SPR_NOACCESS, SPR_NOACCESS,
1842 &spr_read_generic, &spr_write_generic,
1843 0x00000000);
1844 spr_register(env, SPR_40x_ESR, "ESR",
1845 SPR_NOACCESS, SPR_NOACCESS,
1846 &spr_read_generic, &spr_write_generic,
1847 0x00000000);
1848 spr_register(env, SPR_40x_EVPR, "EVPR",
1849 SPR_NOACCESS, SPR_NOACCESS,
1850 &spr_read_generic, &spr_write_excp_prefix,
1851 0x00000000);
1852 spr_register(env, SPR_40x_SRR2, "SRR2",
1853 &spr_read_generic, &spr_write_generic,
1854 &spr_read_generic, &spr_write_generic,
1855 0x00000000);
1856 spr_register(env, SPR_40x_SRR3, "SRR3",
1857 &spr_read_generic, &spr_write_generic,
1858 &spr_read_generic, &spr_write_generic,
1859 0x00000000);
1860 /* Timers */
1861 spr_register(env, SPR_40x_PIT, "PIT",
1862 SPR_NOACCESS, SPR_NOACCESS,
1863 &spr_read_40x_pit, &spr_write_40x_pit,
1864 0x00000000);
1865 spr_register(env, SPR_40x_TCR, "TCR",
1866 SPR_NOACCESS, SPR_NOACCESS,
1867 &spr_read_generic, &spr_write_booke_tcr,
1868 0x00000000);
1869 spr_register(env, SPR_40x_TSR, "TSR",
1870 SPR_NOACCESS, SPR_NOACCESS,
1871 &spr_read_generic, &spr_write_booke_tsr,
1872 0x00000000);
1873 }
1874
1875 /* SPR specific to PowerPC 405 implementation */
1876 static void gen_spr_405 (CPUPPCState *env)
1877 {
1878 /* MMU */
1879 spr_register(env, SPR_40x_PID, "PID",
1880 SPR_NOACCESS, SPR_NOACCESS,
1881 &spr_read_generic, &spr_write_generic,
1882 0x00000000);
1883 spr_register(env, SPR_4xx_CCR0, "CCR0",
1884 SPR_NOACCESS, SPR_NOACCESS,
1885 &spr_read_generic, &spr_write_generic,
1886 0x00700000);
1887 /* Debug interface */
1888 /* XXX : not implemented */
1889 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1890 SPR_NOACCESS, SPR_NOACCESS,
1891 &spr_read_generic, &spr_write_40x_dbcr0,
1892 0x00000000);
1893 /* XXX : not implemented */
1894 spr_register(env, SPR_405_DBCR1, "DBCR1",
1895 SPR_NOACCESS, SPR_NOACCESS,
1896 &spr_read_generic, &spr_write_generic,
1897 0x00000000);
1898 /* XXX : not implemented */
1899 spr_register(env, SPR_40x_DBSR, "DBSR",
1900 SPR_NOACCESS, SPR_NOACCESS,
1901 &spr_read_generic, &spr_write_clear,
1902 /* Last reset was system reset */
1903 0x00000300);
1904 /* XXX : not implemented */
1905 spr_register(env, SPR_40x_DAC1, "DAC1",
1906 SPR_NOACCESS, SPR_NOACCESS,
1907 &spr_read_generic, &spr_write_generic,
1908 0x00000000);
1909 spr_register(env, SPR_40x_DAC2, "DAC2",
1910 SPR_NOACCESS, SPR_NOACCESS,
1911 &spr_read_generic, &spr_write_generic,
1912 0x00000000);
1913 /* XXX : not implemented */
1914 spr_register(env, SPR_405_DVC1, "DVC1",
1915 SPR_NOACCESS, SPR_NOACCESS,
1916 &spr_read_generic, &spr_write_generic,
1917 0x00000000);
1918 /* XXX : not implemented */
1919 spr_register(env, SPR_405_DVC2, "DVC2",
1920 SPR_NOACCESS, SPR_NOACCESS,
1921 &spr_read_generic, &spr_write_generic,
1922 0x00000000);
1923 /* XXX : not implemented */
1924 spr_register(env, SPR_40x_IAC1, "IAC1",
1925 SPR_NOACCESS, SPR_NOACCESS,
1926 &spr_read_generic, &spr_write_generic,
1927 0x00000000);
1928 spr_register(env, SPR_40x_IAC2, "IAC2",
1929 SPR_NOACCESS, SPR_NOACCESS,
1930 &spr_read_generic, &spr_write_generic,
1931 0x00000000);
1932 /* XXX : not implemented */
1933 spr_register(env, SPR_405_IAC3, "IAC3",
1934 SPR_NOACCESS, SPR_NOACCESS,
1935 &spr_read_generic, &spr_write_generic,
1936 0x00000000);
1937 /* XXX : not implemented */
1938 spr_register(env, SPR_405_IAC4, "IAC4",
1939 SPR_NOACCESS, SPR_NOACCESS,
1940 &spr_read_generic, &spr_write_generic,
1941 0x00000000);
1942 /* Storage control */
1943 /* XXX: TODO: not implemented */
1944 spr_register(env, SPR_405_SLER, "SLER",
1945 SPR_NOACCESS, SPR_NOACCESS,
1946 &spr_read_generic, &spr_write_40x_sler,
1947 0x00000000);
1948 spr_register(env, SPR_40x_ZPR, "ZPR",
1949 SPR_NOACCESS, SPR_NOACCESS,
1950 &spr_read_generic, &spr_write_generic,
1951 0x00000000);
1952 /* XXX : not implemented */
1953 spr_register(env, SPR_405_SU0R, "SU0R",
1954 SPR_NOACCESS, SPR_NOACCESS,
1955 &spr_read_generic, &spr_write_generic,
1956 0x00000000);
1957 /* SPRG */
1958 spr_register(env, SPR_USPRG0, "USPRG0",
1959 &spr_read_ureg, SPR_NOACCESS,
1960 &spr_read_ureg, SPR_NOACCESS,
1961 0x00000000);
1962 spr_register(env, SPR_SPRG4, "SPRG4",
1963 SPR_NOACCESS, SPR_NOACCESS,
1964 &spr_read_generic, &spr_write_generic,
1965 0x00000000);
1966 spr_register(env, SPR_SPRG5, "SPRG5",
1967 SPR_NOACCESS, SPR_NOACCESS,
1968 spr_read_generic, &spr_write_generic,
1969 0x00000000);
1970 spr_register(env, SPR_SPRG6, "SPRG6",
1971 SPR_NOACCESS, SPR_NOACCESS,
1972 spr_read_generic, &spr_write_generic,
1973 0x00000000);
1974 spr_register(env, SPR_SPRG7, "SPRG7",
1975 SPR_NOACCESS, SPR_NOACCESS,
1976 spr_read_generic, &spr_write_generic,
1977 0x00000000);
1978 gen_spr_usprgh(env);
1979 }
1980
1981 /* SPR shared between PowerPC 401 & 403 implementations */
1982 static void gen_spr_401_403 (CPUPPCState *env)
1983 {
1984 /* Time base */
1985 spr_register(env, SPR_403_VTBL, "TBL",
1986 &spr_read_tbl, SPR_NOACCESS,
1987 &spr_read_tbl, SPR_NOACCESS,
1988 0x00000000);
1989 spr_register(env, SPR_403_TBL, "TBL",
1990 SPR_NOACCESS, SPR_NOACCESS,
1991 SPR_NOACCESS, &spr_write_tbl,
1992 0x00000000);
1993 spr_register(env, SPR_403_VTBU, "TBU",
1994 &spr_read_tbu, SPR_NOACCESS,
1995 &spr_read_tbu, SPR_NOACCESS,
1996 0x00000000);
1997 spr_register(env, SPR_403_TBU, "TBU",
1998 SPR_NOACCESS, SPR_NOACCESS,
1999 SPR_NOACCESS, &spr_write_tbu,
2000 0x00000000);
2001 /* Debug */
2002 /* not emulated, as QEMU do not emulate caches */
2003 spr_register(env, SPR_403_CDBCR, "CDBCR",
2004 SPR_NOACCESS, SPR_NOACCESS,
2005 &spr_read_generic, &spr_write_generic,
2006 0x00000000);
2007 }
2008
2009 /* SPR specific to PowerPC 401 implementation */
2010 static void gen_spr_401 (CPUPPCState *env)
2011 {
2012 /* Debug interface */
2013 /* XXX : not implemented */
2014 spr_register(env, SPR_40x_DBCR0, "DBCR",
2015 SPR_NOACCESS, SPR_NOACCESS,
2016 &spr_read_generic, &spr_write_40x_dbcr0,
2017 0x00000000);
2018 /* XXX : not implemented */
2019 spr_register(env, SPR_40x_DBSR, "DBSR",
2020 SPR_NOACCESS, SPR_NOACCESS,
2021 &spr_read_generic, &spr_write_clear,
2022 /* Last reset was system reset */
2023 0x00000300);
2024 /* XXX : not implemented */
2025 spr_register(env, SPR_40x_DAC1, "DAC",
2026 SPR_NOACCESS, SPR_NOACCESS,
2027 &spr_read_generic, &spr_write_generic,
2028 0x00000000);
2029 /* XXX : not implemented */
2030 spr_register(env, SPR_40x_IAC1, "IAC",
2031 SPR_NOACCESS, SPR_NOACCESS,
2032 &spr_read_generic, &spr_write_generic,
2033 0x00000000);
2034 /* Storage control */
2035 /* XXX: TODO: not implemented */
2036 spr_register(env, SPR_405_SLER, "SLER",
2037 SPR_NOACCESS, SPR_NOACCESS,
2038 &spr_read_generic, &spr_write_40x_sler,
2039 0x00000000);
2040 /* not emulated, as QEMU never does speculative access */
2041 spr_register(env, SPR_40x_SGR, "SGR",
2042 SPR_NOACCESS, SPR_NOACCESS,
2043 &spr_read_generic, &spr_write_generic,
2044 0xFFFFFFFF);
2045 /* not emulated, as QEMU do not emulate caches */
2046 spr_register(env, SPR_40x_DCWR, "DCWR",
2047 SPR_NOACCESS, SPR_NOACCESS,
2048 &spr_read_generic, &spr_write_generic,
2049 0x00000000);
2050 }
2051
2052 static void gen_spr_401x2 (CPUPPCState *env)
2053 {
2054 gen_spr_401(env);
2055 spr_register(env, SPR_40x_PID, "PID",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_generic, &spr_write_generic,
2058 0x00000000);
2059 spr_register(env, SPR_40x_ZPR, "ZPR",
2060 SPR_NOACCESS, SPR_NOACCESS,
2061 &spr_read_generic, &spr_write_generic,
2062 0x00000000);
2063 }
2064
2065 /* SPR specific to PowerPC 403 implementation */
2066 static void gen_spr_403 (CPUPPCState *env)
2067 {
2068 /* Debug interface */
2069 /* XXX : not implemented */
2070 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2071 SPR_NOACCESS, SPR_NOACCESS,
2072 &spr_read_generic, &spr_write_40x_dbcr0,
2073 0x00000000);
2074 /* XXX : not implemented */
2075 spr_register(env, SPR_40x_DBSR, "DBSR",
2076 SPR_NOACCESS, SPR_NOACCESS,
2077 &spr_read_generic, &spr_write_clear,
2078 /* Last reset was system reset */
2079 0x00000300);
2080 /* XXX : not implemented */
2081 spr_register(env, SPR_40x_DAC1, "DAC1",
2082 SPR_NOACCESS, SPR_NOACCESS,
2083 &spr_read_generic, &spr_write_generic,
2084 0x00000000);
2085 /* XXX : not implemented */
2086 spr_register(env, SPR_40x_DAC2, "DAC2",
2087 SPR_NOACCESS, SPR_NOACCESS,
2088 &spr_read_generic, &spr_write_generic,
2089 0x00000000);
2090 /* XXX : not implemented */
2091 spr_register(env, SPR_40x_IAC1, "IAC1",
2092 SPR_NOACCESS, SPR_NOACCESS,
2093 &spr_read_generic, &spr_write_generic,
2094 0x00000000);
2095 /* XXX : not implemented */
2096 spr_register(env, SPR_40x_IAC2, "IAC2",
2097 SPR_NOACCESS, SPR_NOACCESS,
2098 &spr_read_generic, &spr_write_generic,
2099 0x00000000);
2100 }
2101
2102 static void gen_spr_403_real (CPUPPCState *env)
2103 {
2104 spr_register(env, SPR_403_PBL1, "PBL1",
2105 SPR_NOACCESS, SPR_NOACCESS,
2106 &spr_read_403_pbr, &spr_write_403_pbr,
2107 0x00000000);
2108 spr_register(env, SPR_403_PBU1, "PBU1",
2109 SPR_NOACCESS, SPR_NOACCESS,
2110 &spr_read_403_pbr, &spr_write_403_pbr,
2111 0x00000000);
2112 spr_register(env, SPR_403_PBL2, "PBL2",
2113 SPR_NOACCESS, SPR_NOACCESS,
2114 &spr_read_403_pbr, &spr_write_403_pbr,
2115 0x00000000);
2116 spr_register(env, SPR_403_PBU2, "PBU2",
2117 SPR_NOACCESS, SPR_NOACCESS,
2118 &spr_read_403_pbr, &spr_write_403_pbr,
2119 0x00000000);
2120 }
2121
2122 static void gen_spr_403_mmu (CPUPPCState *env)
2123 {
2124 /* MMU */
2125 spr_register(env, SPR_40x_PID, "PID",
2126 SPR_NOACCESS, SPR_NOACCESS,
2127 &spr_read_generic, &spr_write_generic,
2128 0x00000000);
2129 spr_register(env, SPR_40x_ZPR, "ZPR",
2130 SPR_NOACCESS, SPR_NOACCESS,
2131 &spr_read_generic, &spr_write_generic,
2132 0x00000000);
2133 }
2134
2135 /* SPR specific to PowerPC compression coprocessor extension */
2136 static void gen_spr_compress (CPUPPCState *env)
2137 {
2138 /* XXX : not implemented */
2139 spr_register(env, SPR_401_SKR, "SKR",
2140 SPR_NOACCESS, SPR_NOACCESS,
2141 &spr_read_generic, &spr_write_generic,
2142 0x00000000);
2143 }
2144
2145 #if defined (TARGET_PPC64)
2146 /* SPR specific to PowerPC 620 */
2147 static void gen_spr_620 (CPUPPCState *env)
2148 {
2149 /* Processor identification */
2150 spr_register(env, SPR_PIR, "PIR",
2151 SPR_NOACCESS, SPR_NOACCESS,
2152 &spr_read_generic, &spr_write_pir,
2153 0x00000000);
2154 spr_register(env, SPR_ASR, "ASR",
2155 SPR_NOACCESS, SPR_NOACCESS,
2156 &spr_read_asr, &spr_write_asr,
2157 0x00000000);
2158 /* Breakpoints */
2159 /* XXX : not implemented */
2160 spr_register(env, SPR_IABR, "IABR",
2161 SPR_NOACCESS, SPR_NOACCESS,
2162 &spr_read_generic, &spr_write_generic,
2163 0x00000000);
2164 /* XXX : not implemented */
2165 spr_register(env, SPR_DABR, "DABR",
2166 SPR_NOACCESS, SPR_NOACCESS,
2167 &spr_read_generic, &spr_write_generic,
2168 0x00000000);
2169 /* XXX : not implemented */
2170 spr_register(env, SPR_SIAR, "SIAR",
2171 SPR_NOACCESS, SPR_NOACCESS,
2172 &spr_read_generic, SPR_NOACCESS,
2173 0x00000000);
2174 /* XXX : not implemented */
2175 spr_register(env, SPR_SDA, "SDA",
2176 SPR_NOACCESS, SPR_NOACCESS,
2177 &spr_read_generic, SPR_NOACCESS,
2178 0x00000000);
2179 /* XXX : not implemented */
2180 spr_register(env, SPR_620_PMC1R, "PMC1",
2181 SPR_NOACCESS, SPR_NOACCESS,
2182 &spr_read_generic, SPR_NOACCESS,
2183 0x00000000);
2184 spr_register(env, SPR_620_PMC1W, "PMC1",
2185 SPR_NOACCESS, SPR_NOACCESS,
2186 SPR_NOACCESS, &spr_write_generic,
2187 0x00000000);
2188 /* XXX : not implemented */
2189 spr_register(env, SPR_620_PMC2R, "PMC2",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 &spr_read_generic, SPR_NOACCESS,
2192 0x00000000);
2193 spr_register(env, SPR_620_PMC2W, "PMC2",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 SPR_NOACCESS, &spr_write_generic,
2196 0x00000000);
2197 /* XXX : not implemented */
2198 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2199 SPR_NOACCESS, SPR_NOACCESS,
2200 &spr_read_generic, SPR_NOACCESS,
2201 0x00000000);
2202 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2203 SPR_NOACCESS, SPR_NOACCESS,
2204 SPR_NOACCESS, &spr_write_generic,
2205 0x00000000);
2206 /* External access control */
2207 /* XXX : not implemented */
2208 spr_register(env, SPR_EAR, "EAR",
2209 SPR_NOACCESS, SPR_NOACCESS,
2210 &spr_read_generic, &spr_write_generic,
2211 0x00000000);
2212 #if 0 // XXX: check this
2213 /* XXX : not implemented */
2214 spr_register(env, SPR_620_PMR0, "PMR0",
2215 SPR_NOACCESS, SPR_NOACCESS,
2216 &spr_read_generic, &spr_write_generic,
2217 0x00000000);
2218 /* XXX : not implemented */
2219 spr_register(env, SPR_620_PMR1, "PMR1",
2220 SPR_NOACCESS, SPR_NOACCESS,
2221 &spr_read_generic, &spr_write_generic,
2222 0x00000000);
2223 /* XXX : not implemented */
2224 spr_register(env, SPR_620_PMR2, "PMR2",
2225 SPR_NOACCESS, SPR_NOACCESS,
2226 &spr_read_generic, &spr_write_generic,
2227 0x00000000);
2228 /* XXX : not implemented */
2229 spr_register(env, SPR_620_PMR3, "PMR3",
2230 SPR_NOACCESS, SPR_NOACCESS,
2231 &spr_read_generic, &spr_write_generic,
2232 0x00000000);
2233 /* XXX : not implemented */
2234 spr_register(env, SPR_620_PMR4, "PMR4",
2235 SPR_NOACCESS, SPR_NOACCESS,
2236 &spr_read_generic, &spr_write_generic,
2237 0x00000000);
2238 /* XXX : not implemented */
2239 spr_register(env, SPR_620_PMR5, "PMR5",
2240 SPR_NOACCESS, SPR_NOACCESS,
2241 &spr_read_generic, &spr_write_generic,
2242 0x00000000);
2243 /* XXX : not implemented */
2244 spr_register(env, SPR_620_PMR6, "PMR6",
2245 SPR_NOACCESS, SPR_NOACCESS,
2246 &spr_read_generic, &spr_write_generic,
2247 0x00000000);
2248 /* XXX : not implemented */
2249 spr_register(env, SPR_620_PMR7, "PMR7",
2250 SPR_NOACCESS, SPR_NOACCESS,
2251 &spr_read_generic, &spr_write_generic,
2252 0x00000000);
2253 /* XXX : not implemented */
2254 spr_register(env, SPR_620_PMR8, "PMR8",
2255 SPR_NOACCESS, SPR_NOACCESS,
2256 &spr_read_generic, &spr_write_generic,
2257 0x00000000);
2258 /* XXX : not implemented */
2259 spr_register(env, SPR_620_PMR9, "PMR9",
2260 SPR_NOACCESS, SPR_NOACCESS,
2261 &spr_read_generic, &spr_write_generic,
2262 0x00000000);
2263 /* XXX : not implemented */
2264 spr_register(env, SPR_620_PMRA, "PMR10",
2265 SPR_NOACCESS, SPR_NOACCESS,
2266 &spr_read_generic, &spr_write_generic,
2267 0x00000000);
2268 /* XXX : not implemented */
2269 spr_register(env, SPR_620_PMRB, "PMR11",
2270 SPR_NOACCESS, SPR_NOACCESS,
2271 &spr_read_generic, &spr_write_generic,
2272 0x00000000);
2273 /* XXX : not implemented */
2274 spr_register(env, SPR_620_PMRC, "PMR12",
2275 SPR_NOACCESS, SPR_NOACCESS,
2276 &spr_read_generic, &spr_write_generic,
2277 0x00000000);
2278 /* XXX : not implemented */
2279 spr_register(env, SPR_620_PMRD, "PMR13",
2280 SPR_NOACCESS, SPR_NOACCESS,
2281 &spr_read_generic, &spr_write_generic,
2282 0x00000000);
2283 /* XXX : not implemented */
2284 spr_register(env, SPR_620_PMRE, "PMR14",
2285 SPR_NOACCESS, SPR_NOACCESS,
2286 &spr_read_generic, &spr_write_generic,
2287 0x00000000);
2288 /* XXX : not implemented */
2289 spr_register(env, SPR_620_PMRF, "PMR15",
2290 SPR_NOACCESS, SPR_NOACCESS,
2291 &spr_read_generic, &spr_write_generic,
2292 0x00000000);
2293 #endif
2294 /* XXX : not implemented */
2295 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2296 SPR_NOACCESS, SPR_NOACCESS,
2297 &spr_read_generic, &spr_write_generic,
2298 0x00000000);
2299 /* XXX : not implemented */
2300 spr_register(env, SPR_620_L2CR, "L2CR",
2301 SPR_NOACCESS, SPR_NOACCESS,
2302 &spr_read_generic, &spr_write_generic,
2303 0x00000000);
2304 /* XXX : not implemented */
2305 spr_register(env, SPR_620_L2SR, "L2SR",
2306 SPR_NOACCESS, SPR_NOACCESS,
2307 &spr_read_generic, &spr_write_generic,
2308 0x00000000);
2309 }
2310 #endif /* defined (TARGET_PPC64) */
2311
2312 static void gen_spr_5xx_8xx (CPUPPCState *env)
2313 {
2314 /* Exception processing */
2315 spr_register(env, SPR_DSISR, "DSISR",
2316 SPR_NOACCESS, SPR_NOACCESS,
2317 &spr_read_generic, &spr_write_generic,
2318 0x00000000);
2319 spr_register(env, SPR_DAR, "DAR",
2320 SPR_NOACCESS, SPR_NOACCESS,
2321 &spr_read_generic, &spr_write_generic,
2322 0x00000000);
2323 /* Timer */
2324 spr_register(env, SPR_DECR, "DECR",
2325 SPR_NOACCESS, SPR_NOACCESS,
2326 &spr_read_decr, &spr_write_decr,
2327 0x00000000);
2328 /* XXX : not implemented */
2329 spr_register(env, SPR_MPC_EIE, "EIE",
2330 SPR_NOACCESS, SPR_NOACCESS,
2331 &spr_read_generic, &spr_write_generic,
2332 0x00000000);
2333 /* XXX : not implemented */
2334 spr_register(env, SPR_MPC_EID, "EID",
2335 SPR_NOACCESS, SPR_NOACCESS,
2336 &spr_read_generic, &spr_write_generic,
2337 0x00000000);
2338 /* XXX : not implemented */
2339 spr_register(env, SPR_MPC_NRI, "NRI",
2340 SPR_NOACCESS, SPR_NOACCESS,
2341 &spr_read_generic, &spr_write_generic,
2342 0x00000000);
2343 /* XXX : not implemented */
2344 spr_register(env, SPR_MPC_CMPA, "CMPA",
2345 SPR_NOACCESS, SPR_NOACCESS,
2346 &spr_read_generic, &spr_write_generic,
2347 0x00000000);
2348 /* XXX : not implemented */
2349 spr_register(env, SPR_MPC_CMPB, "CMPB",
2350 SPR_NOACCESS, SPR_NOACCESS,
2351 &spr_read_generic, &spr_write_generic,
2352 0x00000000);
2353 /* XXX : not implemented */
2354 spr_register(env, SPR_MPC_CMPC, "CMPC",
2355 SPR_NOACCESS, SPR_NOACCESS,
2356 &spr_read_generic, &spr_write_generic,
2357 0x00000000);
2358 /* XXX : not implemented */
2359 spr_register(env, SPR_MPC_CMPD, "CMPD",
2360 SPR_NOACCESS, SPR_NOACCESS,
2361 &spr_read_generic, &spr_write_generic,
2362 0x00000000);
2363 /* XXX : not implemented */
2364 spr_register(env, SPR_MPC_ECR, "ECR",
2365 SPR_NOACCESS, SPR_NOACCESS,
2366 &spr_read_generic, &spr_write_generic,
2367 0x00000000);
2368 /* XXX : not implemented */
2369 spr_register(env, SPR_MPC_DER, "DER",
2370 SPR_NOACCESS, SPR_NOACCESS,
2371 &spr_read_generic, &spr_write_generic,
2372 0x00000000);
2373 /* XXX : not implemented */
2374 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2375 SPR_NOACCESS, SPR_NOACCESS,
2376 &spr_read_generic, &spr_write_generic,
2377 0x00000000);
2378 /* XXX : not implemented */
2379 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2380 SPR_NOACCESS, SPR_NOACCESS,
2381 &spr_read_generic, &spr_write_generic,
2382 0x00000000);
2383 /* XXX : not implemented */
2384 spr_register(env, SPR_MPC_CMPE, "CMPE",
2385 SPR_NOACCESS, SPR_NOACCESS,
2386 &spr_read_generic, &spr_write_generic,
2387 0x00000000);
2388 /* XXX : not implemented */
2389 spr_register(env, SPR_MPC_CMPF, "CMPF",
2390 SPR_NOACCESS, SPR_NOACCESS,
2391 &spr_read_generic, &spr_write_generic,
2392 0x00000000);
2393 /* XXX : not implemented */
2394 spr_register(env, SPR_MPC_CMPG, "CMPG",
2395 SPR_NOACCESS, SPR_NOACCESS,
2396 &spr_read_generic, &spr_write_generic,
2397 0x00000000);
2398 /* XXX : not implemented */
2399 spr_register(env, SPR_MPC_CMPH, "CMPH",
2400 SPR_NOACCESS, SPR_NOACCESS,
2401 &spr_read_generic, &spr_write_generic,
2402 0x00000000);
2403 /* XXX : not implemented */
2404 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2405 SPR_NOACCESS, SPR_NOACCESS,
2406 &spr_read_generic, &spr_write_generic,
2407 0x00000000);
2408 /* XXX : not implemented */
2409 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2410 SPR_NOACCESS, SPR_NOACCESS,
2411 &spr_read_generic, &spr_write_generic,
2412 0x00000000);
2413 /* XXX : not implemented */
2414 spr_register(env, SPR_MPC_BAR, "BAR",
2415 SPR_NOACCESS, SPR_NOACCESS,
2416 &spr_read_generic, &spr_write_generic,
2417 0x00000000);
2418 /* XXX : not implemented */
2419 spr_register(env, SPR_MPC_DPDR, "DPDR",
2420 SPR_NOACCESS, SPR_NOACCESS,
2421 &spr_read_generic, &spr_write_generic,
2422 0x00000000);
2423 /* XXX : not implemented */
2424 spr_register(env, SPR_MPC_IMMR, "IMMR",
2425 SPR_NOACCESS, SPR_NOACCESS,
2426 &spr_read_generic, &spr_write_generic,
2427 0x00000000);
2428 }
2429
2430 static void gen_spr_5xx (CPUPPCState *env)
2431 {
2432 /* XXX : not implemented */
2433 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2434 SPR_NOACCESS, SPR_NOACCESS,
2435 &spr_read_generic, &spr_write_generic,
2436 0x00000000);
2437 /* XXX : not implemented */
2438 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2439 SPR_NOACCESS, SPR_NOACCESS,
2440 &spr_read_generic, &spr_write_generic,
2441 0x00000000);
2442 /* XXX : not implemented */
2443 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2444 SPR_NOACCESS, SPR_NOACCESS,
2445 &spr_read_generic, &spr_write_generic,
2446 0x00000000);
2447 /* XXX : not implemented */
2448 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2449 SPR_NOACCESS, SPR_NOACCESS,
2450 &spr_read_generic, &spr_write_generic,
2451 0x00000000);
2452 /* XXX : not implemented */
2453 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2454 SPR_NOACCESS, SPR_NOACCESS,
2455 &spr_read_generic, &spr_write_generic,
2456 0x00000000);
2457 /* XXX : not implemented */
2458 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2459 SPR_NOACCESS, SPR_NOACCESS,
2460 &spr_read_generic, &spr_write_generic,
2461 0x00000000);
2462 /* XXX : not implemented */
2463 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2464 SPR_NOACCESS, SPR_NOACCESS,
2465 &spr_read_generic, &spr_write_generic,
2466 0x00000000);
2467 /* XXX : not implemented */
2468 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2469 SPR_NOACCESS, SPR_NOACCESS,
2470 &spr_read_generic, &spr_write_generic,
2471 0x00000000);
2472 /* XXX : not implemented */
2473 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2474 SPR_NOACCESS, SPR_NOACCESS,
2475 &spr_read_generic, &spr_write_generic,
2476 0x00000000);
2477 /* XXX : not implemented */
2478 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2479 SPR_NOACCESS, SPR_NOACCESS,
2480 &spr_read_generic, &spr_write_generic,
2481 0x00000000);
2482 /* XXX : not implemented */
2483 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2484 SPR_NOACCESS, SPR_NOACCESS,
2485 &spr_read_generic, &spr_write_generic,
2486 0x00000000);
2487 /* XXX : not implemented */
2488 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2489 SPR_NOACCESS, SPR_NOACCESS,
2490 &spr_read_generic, &spr_write_generic,
2491 0x00000000);
2492 /* XXX : not implemented */
2493 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2494 SPR_NOACCESS, SPR_NOACCESS,
2495 &spr_read_generic, &spr_write_generic,
2496 0x00000000);
2497 /* XXX : not implemented */
2498 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2499 SPR_NOACCESS, SPR_NOACCESS,
2500 &spr_read_generic, &spr_write_generic,
2501 0x00000000);
2502 /* XXX : not implemented */
2503 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2504 SPR_NOACCESS, SPR_NOACCESS,
2505 &spr_read_generic, &spr_write_generic,
2506 0x00000000);
2507 /* XXX : not implemented */
2508 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2509 SPR_NOACCESS, SPR_NOACCESS,
2510 &spr_read_generic, &spr_write_generic,
2511 0x00000000);
2512 /* XXX : not implemented */
2513 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2514 SPR_NOACCESS, SPR_NOACCESS,
2515 &spr_read_generic, &spr_write_generic,
2516 0x00000000);
2517 /* XXX : not implemented */
2518 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2519 SPR_NOACCESS, SPR_NOACCESS,
2520 &spr_read_generic, &spr_write_generic,
2521 0x00000000);
2522 /* XXX : not implemented */
2523 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2524 SPR_NOACCESS, SPR_NOACCESS,
2525 &spr_read_generic, &spr_write_generic,
2526 0x00000000);
2527 /* XXX : not implemented */
2528 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2529 SPR_NOACCESS, SPR_NOACCESS,
2530 &spr_read_generic, &spr_write_generic,
2531 0x00000000);
2532 /* XXX : not implemented */
2533 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2534 SPR_NOACCESS, SPR_NOACCESS,
2535 &spr_read_generic, &spr_write_generic,
2536 0x00000000);
2537 }
2538
2539 static void gen_spr_8xx (CPUPPCState *env)
2540 {
2541 /* XXX : not implemented */
2542 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2543 SPR_NOACCESS, SPR_NOACCESS,
2544 &spr_read_generic, &spr_write_generic,
2545 0x00000000);
2546 /* XXX : not implemented */
2547 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2548 SPR_NOACCESS, SPR_NOACCESS,
2549 &spr_read_generic, &spr_write_generic,
2550 0x00000000);
2551 /* XXX : not implemented */
2552 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2553 SPR_NOACCESS, SPR_NOACCESS,
2554 &spr_read_generic, &spr_write_generic,
2555 0x00000000);
2556 /* XXX : not implemented */
2557 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2558 SPR_NOACCESS, SPR_NOACCESS,
2559 &spr_read_generic, &spr_write_generic,
2560 0x00000000);
2561 /* XXX : not implemented */
2562 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2563 SPR_NOACCESS, SPR_NOACCESS,
2564 &spr_read_generic, &spr_write_generic,
2565 0x00000000);
2566 /* XXX : not implemented */
2567 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2568 SPR_NOACCESS, SPR_NOACCESS,
2569 &spr_read_generic, &spr_write_generic,
2570 0x00000000);
2571 /* XXX : not implemented */
2572 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2573 SPR_NOACCESS, SPR_NOACCESS,
2574 &spr_read_generic, &spr_write_generic,
2575 0x00000000);
2576 /* XXX : not implemented */
2577 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2578 SPR_NOACCESS, SPR_NOACCESS,
2579 &spr_read_generic, &spr_write_generic,
2580 0x00000000);
2581 /* XXX : not implemented */
2582 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2583 SPR_NOACCESS, SPR_NOACCESS,
2584 &spr_read_generic, &spr_write_generic,
2585 0x00000000);
2586 /* XXX : not implemented */
2587 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2588 SPR_NOACCESS, SPR_NOACCESS,
2589 &spr_read_generic, &spr_write_generic,
2590 0x00000000);
2591 /* XXX : not implemented */
2592 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2593 SPR_NOACCESS, SPR_NOACCESS,
2594 &spr_read_generic, &spr_write_generic,
2595 0x00000000);
2596 /* XXX : not implemented */
2597 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2598 SPR_NOACCESS, SPR_NOACCESS,
2599 &spr_read_generic, &spr_write_generic,
2600 0x00000000);
2601 /* XXX : not implemented */
2602 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2603 SPR_NOACCESS, SPR_NOACCESS,
2604 &spr_read_generic, &spr_write_generic,
2605 0x00000000);
2606 /* XXX : not implemented */
2607 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2608 SPR_NOACCESS, SPR_NOACCESS,
2609 &spr_read_generic, &spr_write_generic,
2610 0x00000000);
2611 /* XXX : not implemented */
2612 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2613 SPR_NOACCESS, SPR_NOACCESS,
2614 &spr_read_generic, &spr_write_generic,
2615 0x00000000);
2616 /* XXX : not implemented */
2617 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2618 SPR_NOACCESS, SPR_NOACCESS,
2619 &spr_read_generic, &spr_write_generic,
2620 0x00000000);
2621 /* XXX : not implemented */
2622 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2623 SPR_NOACCESS, SPR_NOACCESS,
2624 &spr_read_generic, &spr_write_generic,
2625 0x00000000);
2626 /* XXX : not implemented */
2627 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2628 SPR_NOACCESS, SPR_NOACCESS,
2629 &spr_read_generic, &spr_write_generic,
2630 0x00000000);
2631 /* XXX : not implemented */
2632 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2633 SPR_NOACCESS, SPR_NOACCESS,
2634 &spr_read_generic, &spr_write_generic,
2635 0x00000000);
2636 /* XXX : not implemented */
2637 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2638 SPR_NOACCESS, SPR_NOACCESS,
2639 &spr_read_generic, &spr_write_generic,
2640 0x00000000);
2641 /* XXX : not implemented */
2642 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2643 SPR_NOACCESS, SPR_NOACCESS,
2644 &spr_read_generic, &spr_write_generic,
2645 0x00000000);
2646 /* XXX : not implemented */
2647 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2648 SPR_NOACCESS, SPR_NOACCESS,
2649 &spr_read_generic, &spr_write_generic,
2650 0x00000000);
2651 /* XXX : not implemented */
2652 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2653 SPR_NOACCESS, SPR_NOACCESS,
2654 &spr_read_generic, &spr_write_generic,
2655 0x00000000);
2656 /* XXX : not implemented */
2657 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2658 SPR_NOACCESS, SPR_NOACCESS,
2659 &spr_read_generic, &spr_write_generic,
2660 0x00000000);
2661 /* XXX : not implemented */
2662 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2663 SPR_NOACCESS, SPR_NOACCESS,
2664 &spr_read_generic, &spr_write_generic,
2665 0x00000000);
2666 }
2667
2668 // XXX: TODO
2669 /*
2670 * AMR => SPR 29 (Power 2.04)
2671 * CTRL => SPR 136 (Power 2.04)
2672 * CTRL => SPR 152 (Power 2.04)
2673 * SCOMC => SPR 276 (64 bits ?)
2674 * SCOMD => SPR 277 (64 bits ?)
2675 * TBU40 => SPR 286 (Power 2.04 hypv)
2676 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2677 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2678 * HDSISR => SPR 306 (Power 2.04 hypv)
2679 * HDAR => SPR 307 (Power 2.04 hypv)
2680 * PURR => SPR 309 (Power 2.04 hypv)
2681 * HDEC => SPR 310 (Power 2.04 hypv)
2682 * HIOR => SPR 311 (hypv)
2683 * RMOR => SPR 312 (970)
2684 * HRMOR => SPR 313 (Power 2.04 hypv)
2685 * HSRR0 => SPR 314 (Power 2.04 hypv)
2686 * HSRR1 => SPR 315 (Power 2.04 hypv)
2687 * LPCR => SPR 316 (970)
2688 * LPIDR => SPR 317 (970)
2689 * EPR => SPR 702 (Power 2.04 emb)
2690 * perf => 768-783 (Power 2.04)
2691 * perf => 784-799 (Power 2.04)
2692 * PPR => SPR 896 (Power 2.04)
2693 * EPLC => SPR 947 (Power 2.04 emb)
2694 * EPSC => SPR 948 (Power 2.04 emb)
2695 * DABRX => 1015 (Power 2.04 hypv)
2696 * FPECR => SPR 1022 (?)
2697 * ... and more (thermal management, performance counters, ...)
2698 */
2699
2700 /*****************************************************************************/
2701 /* Exception vectors models */
2702 static void init_excp_4xx_real (CPUPPCState *env)
2703 {
2704 #if !defined(CONFIG_USER_ONLY)
2705 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2706 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2707 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2708 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2709 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2710 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2711 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2712 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2713 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2714 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2715 env->hreset_excp_prefix = 0x00000000UL;
2716 env->ivor_mask = 0x0000FFF0UL;
2717 env->ivpr_mask = 0xFFFF0000UL;
2718 /* Hardware reset vector */
2719 env->hreset_vector = 0xFFFFFFFCUL;
2720 #endif
2721 }
2722
2723 static void init_excp_4xx_softmmu (CPUPPCState *env)
2724 {
2725 #if !defined(CONFIG_USER_ONLY)
2726 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2727 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2728 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2729 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2730 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2731 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2732 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2733 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2734 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2735 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2736 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2737 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2738 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2739 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2740 env->hreset_excp_prefix = 0x00000000UL;
2741 env->ivor_mask = 0x0000FFF0UL;
2742 env->ivpr_mask = 0xFFFF0000UL;
2743 /* Hardware reset vector */
2744 env->hreset_vector = 0xFFFFFFFCUL;
2745 #endif
2746 }
2747
2748 static void init_excp_MPC5xx (CPUPPCState *env)
2749 {
2750 #if !defined(CONFIG_USER_ONLY)
2751 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2752 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2753 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2754 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2755 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2756 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2757 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2758 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2759 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2760 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2761 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2762 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2763 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2764 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2765 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2766 env->hreset_excp_prefix = 0x00000000UL;
2767 env->ivor_mask = 0x0000FFF0UL;
2768 env->ivpr_mask = 0xFFFF0000UL;
2769 /* Hardware reset vector */
2770 env->hreset_vector = 0xFFFFFFFCUL;
2771 #endif
2772 }
2773
2774 static void init_excp_MPC8xx (CPUPPCState *env)
2775 {
2776 #if !defined(CONFIG_USER_ONLY)
2777 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2778 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2779 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2780 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2781 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2782 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2783 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2784 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2785 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2786 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2787 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2788 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2789 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2790 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2791 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2792 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2793 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2794 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2795 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2796 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2797 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2798 env->hreset_excp_prefix = 0x00000000UL;
2799 env->ivor_mask = 0x0000FFF0UL;
2800 env->ivpr_mask = 0xFFFF0000UL;
2801 /* Hardware reset vector */
2802 env->hreset_vector = 0xFFFFFFFCUL;
2803 #endif
2804 }
2805
2806 static void init_excp_G2 (CPUPPCState *env)
2807 {
2808 #if !defined(CONFIG_USER_ONLY)
2809 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2810 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2811 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2812 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2813 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2814 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2815 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2816 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2817 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2818 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2819 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2820 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2821 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2822 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2823 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2824 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2825 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2826 env->hreset_excp_prefix = 0x00000000UL;
2827 /* Hardware reset vector */
2828 env->hreset_vector = 0xFFFFFFFCUL;
2829 #endif
2830 }
2831
2832 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2833 {
2834 #if !defined(CONFIG_USER_ONLY)
2835 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2836 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2837 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2838 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2839 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2840 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2841 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2842 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2843 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2844 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2845 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2846 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2847 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2848 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2849 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2850 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2851 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2852 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2853 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2854 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2855 env->hreset_excp_prefix = 0x00000000UL;
2856 env->ivor_mask = 0x0000FFF7UL;
2857 env->ivpr_mask = ivpr_mask;
2858 /* Hardware reset vector */
2859 env->hreset_vector = 0xFFFFFFFCUL;
2860 #endif
2861 }
2862
2863 static void init_excp_BookE (CPUPPCState *env)
2864 {
2865 #if !defined(CONFIG_USER_ONLY)
2866 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2867 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2868 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2869 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2870 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2871 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2872 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2873 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2874 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2875 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2876 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2877 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2878 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2879 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2880 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2881 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2882 env->hreset_excp_prefix = 0x00000000UL;
2883 env->ivor_mask = 0x0000FFE0UL;
2884 env->ivpr_mask = 0xFFFF0000UL;
2885 /* Hardware reset vector */
2886 env->hreset_vector = 0xFFFFFFFCUL;
2887 #endif
2888 }
2889
2890 static void init_excp_601 (CPUPPCState *env)
2891 {
2892 #if !defined(CONFIG_USER_ONLY)
2893 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2894 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2895 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2896 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2897 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2898 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2899 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2900 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2901 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2902 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2903 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2904 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2905 env->hreset_excp_prefix = 0xFFF00000UL;
2906 /* Hardware reset vector */
2907 env->hreset_vector = 0x00000100UL;
2908 #endif
2909 }
2910
2911 static void init_excp_602 (CPUPPCState *env)
2912 {
2913 #if !defined(CONFIG_USER_ONLY)
2914 /* XXX: exception prefix has a special behavior on 602 */
2915 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2916 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2917 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2918 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2919 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2920 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2921 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2922 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2923 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2924 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2925 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2926 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2927 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2928 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2929 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2930 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2931 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2932 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2933 env->hreset_excp_prefix = 0xFFF00000UL;
2934 /* Hardware reset vector */
2935 env->hreset_vector = 0xFFFFFFFCUL;
2936 #endif
2937 }
2938
2939 static void init_excp_603 (CPUPPCState *env)
2940 {
2941 #if !defined(CONFIG_USER_ONLY)
2942 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2943 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2944 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2945 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2946 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2947 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2948 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2949 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2950 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2951 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2952 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2953 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2954 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2955 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2956 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2957 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2958 env->hreset_excp_prefix = 0x00000000UL;
2959 /* Hardware reset vector */
2960 env->hreset_vector = 0xFFFFFFFCUL;
2961 #endif
2962 }
2963
2964 static void init_excp_604 (CPUPPCState *env)
2965 {
2966 #if !defined(CONFIG_USER_ONLY)
2967 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2968 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2969 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2970 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2971 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2972 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2973 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2974 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2975 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2976 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2977 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2978 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2979 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2980 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2981 env->hreset_excp_prefix = 0xFFF00000UL;
2982 /* Hardware reset vector */
2983 env->hreset_vector = 0x00000100UL;
2984 #endif
2985 }
2986
2987 #if defined(TARGET_PPC64)
2988 static void init_excp_620 (CPUPPCState *env)
2989 {
2990 #if !defined(CONFIG_USER_ONLY)
2991 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2992 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2993 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2994 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2995 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2996 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2997 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2998 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2999 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3000 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3001 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3002 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3003 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3004 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3005 env->hreset_excp_prefix = 0xFFF00000UL;
3006 /* Hardware reset vector */
3007 env->hreset_vector = 0x0000000000000100ULL;
3008 #endif
3009 }
3010 #endif /* defined(TARGET_PPC64) */
3011
3012 static void init_excp_7x0 (CPUPPCState *env)
3013 {
3014 #if !defined(CONFIG_USER_ONLY)
3015 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3016 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3017 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3018 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3019 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3020 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3021 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3022 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3023 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3024 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3025 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3026 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3027 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3028 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3029 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3030 env->hreset_excp_prefix = 0x00000000UL;
3031 /* Hardware reset vector */
3032 env->hreset_vector = 0xFFFFFFFCUL;
3033 #endif
3034 }
3035
3036 static void init_excp_750cl (CPUPPCState *env)
3037 {
3038 #if !defined(CONFIG_USER_ONLY)
3039 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3040 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3041 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3042 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3043 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3044 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3045 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3046 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3047 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3048 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3049 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3050 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3051 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3052 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3053 env->hreset_excp_prefix = 0x00000000UL;
3054 /* Hardware reset vector */
3055 env->hreset_vector = 0xFFFFFFFCUL;
3056 #endif
3057 }
3058
3059 static void init_excp_750cx (CPUPPCState *env)
3060 {
3061 #if !defined(CONFIG_USER_ONLY)
3062 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3063 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3064 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3065 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3066 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3067 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3068 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3069 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3070 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3071 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3072 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3073 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3074 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3075 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3076 env->hreset_excp_prefix = 0x00000000UL;
3077 /* Hardware reset vector */
3078 env->hreset_vector = 0xFFFFFFFCUL;
3079 #endif
3080 }
3081
3082 /* XXX: Check if this is correct */
3083 static void init_excp_7x5 (CPUPPCState *env)
3084 {
3085 #if !defined(CONFIG_USER_ONLY)
3086 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3087 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3088 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3089 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3090 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3091 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3092 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3093 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3094 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3095 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3096 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3097 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3098 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3099 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3100 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3101 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3102 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3103 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3104 env->hreset_excp_prefix = 0x00000000UL;
3105 /* Hardware reset vector */
3106 env->hreset_vector = 0xFFFFFFFCUL;
3107 #endif
3108 }
3109
3110 static void init_excp_7400 (CPUPPCState *env)
3111 {
3112 #if !defined(CONFIG_USER_ONLY)
3113 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3114 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3115 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3116 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3117 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3118 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3119 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3120 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3121 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3122 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3123 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3124 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3125 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3126 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3127 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3128 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3129 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3130 env->hreset_excp_prefix = 0x00000000UL;
3131 /* Hardware reset vector */
3132 env->hreset_vector = 0xFFFFFFFCUL;
3133 #endif
3134 }
3135
3136 static void init_excp_7450 (CPUPPCState *env)
3137 {
3138 #if !defined(CONFIG_USER_ONLY)
3139 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3140 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3141 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3142 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3143 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3144 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3145 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3146 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3147 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3148 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3149 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3150 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3151 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3152 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3153 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3154 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3155 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3156 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3157 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3158 env->hreset_excp_prefix = 0x00000000UL;
3159 /* Hardware reset vector */
3160 env->hreset_vector = 0xFFFFFFFCUL;
3161 #endif
3162 }
3163
3164 #if defined (TARGET_PPC64)
3165 static void init_excp_970 (CPUPPCState *env)
3166 {
3167 #if !defined(CONFIG_USER_ONLY)
3168 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3169 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3170 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3171 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3172 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3173 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3174 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3175 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3176 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3177 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3178 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3179 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3180 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3181 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3182 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3183 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3184 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3185 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3186 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3187 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3188 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
3189 /* Hardware reset vector */
3190 env->hreset_vector = 0x0000000000000100ULL;
3191 #endif
3192 }
3193
3194 static void init_excp_POWER7 (CPUPPCState *env)
3195 {
3196 #if !defined(CONFIG_USER_ONLY)
3197 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3198 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3199 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3200 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3201 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3202 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3203 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3204 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3205 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3206 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3207 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3208 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3209 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3210 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3211 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3212 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3213 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3214 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3215 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3216 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3217 env->hreset_excp_prefix = 0;
3218 /* Hardware reset vector */
3219 env->hreset_vector = 0x0000000000000100ULL;
3220 #endif
3221 }
3222 #endif
3223
3224 /*****************************************************************************/
3225 /* Power management enable checks */
3226 static int check_pow_none (CPUPPCState *env)
3227 {
3228 return 0;
3229 }
3230
3231 static int check_pow_nocheck (CPUPPCState *env)
3232 {
3233 return 1;
3234 }
3235
3236 static int check_pow_hid0 (CPUPPCState *env)
3237 {
3238 if (env->spr[SPR_HID0] & 0x00E00000)
3239 return 1;
3240
3241 return 0;
3242 }
3243
3244 static int check_pow_hid0_74xx (CPUPPCState *env)
3245 {
3246 if (env->spr[SPR_HID0] & 0x00600000)
3247 return 1;
3248
3249 return 0;
3250 }
3251
3252 /*****************************************************************************/
3253 /* PowerPC implementations definitions */
3254
3255 #define POWERPC_FAMILY(_name) \
3256 static void \
3257 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3258 \
3259 static const TypeInfo \
3260 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3261 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3262 .parent = TYPE_POWERPC_CPU, \
3263 .abstract = true, \
3264 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3265 }; \
3266 \
3267 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3268 { \
3269 type_register_static( \
3270 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3271 } \
3272 \
3273 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3274 \
3275 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3276
3277 static void init_proc_401 (CPUPPCState *env)
3278 {
3279 gen_spr_40x(env);
3280 gen_spr_401_403(env);
3281 gen_spr_401(env);
3282 init_excp_4xx_real(env);
3283 env->dcache_line_size = 32;
3284 env->icache_line_size = 32;
3285 /* Allocate hardware IRQ controller */
3286 ppc40x_irq_init(env);
3287
3288 SET_FIT_PERIOD(12, 16, 20, 24);
3289 SET_WDT_PERIOD(16, 20, 24, 28);
3290 }
3291
3292 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3293 {
3294 DeviceClass *dc = DEVICE_CLASS(oc);
3295 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3296
3297 dc->desc = "PowerPC 401";
3298 pcc->init_proc = init_proc_401;
3299 pcc->check_pow = check_pow_nocheck;
3300 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3301 PPC_WRTEE | PPC_DCR |
3302 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3303 PPC_CACHE_DCBZ |
3304 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3305 PPC_4xx_COMMON | PPC_40x_EXCP;
3306 pcc->insns_flags2 = PPC_NONE;
3307 pcc->msr_mask = 0x00000000000FD201ULL;
3308 pcc->mmu_model = POWERPC_MMU_REAL;
3309 pcc->excp_model = POWERPC_EXCP_40x;
3310 pcc->bus_model = PPC_FLAGS_INPUT_401;
3311 pcc->bfd_mach = bfd_mach_ppc_403;
3312 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3313 POWERPC_FLAG_BUS_CLK;
3314 }
3315
3316 static void init_proc_401x2 (CPUPPCState *env)
3317 {
3318 gen_spr_40x(env);
3319 gen_spr_401_403(env);
3320 gen_spr_401x2(env);
3321 gen_spr_compress(env);
3322 /* Memory management */
3323 #if !defined(CONFIG_USER_ONLY)
3324 env->nb_tlb = 64;
3325 env->nb_ways = 1;
3326 env->id_tlbs = 0;
3327 env->tlb_type = TLB_EMB;
3328 #endif
3329 init_excp_4xx_softmmu(env);
3330 env->dcache_line_size = 32;
3331 env->icache_line_size = 32;
3332 /* Allocate hardware IRQ controller */
3333 ppc40x_irq_init(env);
3334
3335 SET_FIT_PERIOD(12, 16, 20, 24);
3336 SET_WDT_PERIOD(16, 20, 24, 28);
3337 }
3338
3339 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3340 {
3341 DeviceClass *dc = DEVICE_CLASS(oc);
3342 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3343
3344 dc->desc = "PowerPC 401x2";
3345 pcc->init_proc = init_proc_401x2;
3346 pcc->check_pow = check_pow_nocheck;
3347 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3348 PPC_DCR | PPC_WRTEE |
3349 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3350 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3351 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3352 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3353 PPC_4xx_COMMON | PPC_40x_EXCP;
3354 pcc->insns_flags2 = PPC_NONE;
3355 pcc->msr_mask = 0x00000000001FD231ULL;
3356 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3357 pcc->excp_model = POWERPC_EXCP_40x;
3358 pcc->bus_model = PPC_FLAGS_INPUT_401;
3359 pcc->bfd_mach = bfd_mach_ppc_403;
3360 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3361 POWERPC_FLAG_BUS_CLK;
3362 }
3363
3364 static void init_proc_401x3 (CPUPPCState *env)
3365 {
3366 gen_spr_40x(env);
3367 gen_spr_401_403(env);
3368 gen_spr_401(env);
3369 gen_spr_401x2(env);
3370 gen_spr_compress(env);
3371 init_excp_4xx_softmmu(env);
3372 env->dcache_line_size = 32;
3373 env->icache_line_size = 32;
3374 /* Allocate hardware IRQ controller */
3375 ppc40x_irq_init(env);
3376
3377 SET_FIT_PERIOD(12, 16, 20, 24);
3378 SET_WDT_PERIOD(16, 20, 24, 28);
3379 }
3380
3381 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3382 {
3383 DeviceClass *dc = DEVICE_CLASS(oc);
3384 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3385
3386 dc->desc = "PowerPC 401x3";
3387 pcc->init_proc = init_proc_401x3;
3388 pcc->check_pow = check_pow_nocheck;
3389 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3390 PPC_DCR | PPC_WRTEE |
3391 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3392 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3393 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3394 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3395 PPC_4xx_COMMON | PPC_40x_EXCP;
3396 pcc->insns_flags2 = PPC_NONE;
3397 pcc->msr_mask = 0x00000000001FD631ULL;
3398 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3399 pcc->excp_model = POWERPC_EXCP_40x;
3400 pcc->bus_model = PPC_FLAGS_INPUT_401;
3401 pcc->bfd_mach = bfd_mach_ppc_403;
3402 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3403 POWERPC_FLAG_BUS_CLK;
3404 }
3405
3406 static void init_proc_IOP480 (CPUPPCState *env)
3407 {
3408 gen_spr_40x(env);
3409 gen_spr_401_403(env);
3410 gen_spr_401x2(env);
3411 gen_spr_compress(env);
3412 /* Memory management */
3413 #if !defined(CONFIG_USER_ONLY)
3414 env->nb_tlb = 64;
3415 env->nb_ways = 1;
3416 env->id_tlbs = 0;
3417 env->tlb_type = TLB_EMB;
3418 #endif
3419 init_excp_4xx_softmmu(env);
3420 env->dcache_line_size = 32;
3421 env->icache_line_size = 32;
3422 /* Allocate hardware IRQ controller */
3423 ppc40x_irq_init(env);
3424
3425 SET_FIT_PERIOD(8, 12, 16, 20);
3426 SET_WDT_PERIOD(16, 20, 24, 28);
3427 }
3428
3429 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3430 {
3431 DeviceClass *dc = DEVICE_CLASS(oc);
3432 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3433
3434 dc->desc = "IOP480";
3435 pcc->init_proc = init_proc_IOP480;
3436 pcc->check_pow = check_pow_nocheck;
3437 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3438 PPC_DCR | PPC_WRTEE |
3439 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3440 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3441 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3442 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3443 PPC_4xx_COMMON | PPC_40x_EXCP;
3444 pcc->insns_flags2 = PPC_NONE;
3445 pcc->msr_mask = 0x00000000001FD231ULL;
3446 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3447 pcc->excp_model = POWERPC_EXCP_40x;
3448 pcc->bus_model = PPC_FLAGS_INPUT_401;
3449 pcc->bfd_mach = bfd_mach_ppc_403;
3450 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3451 POWERPC_FLAG_BUS_CLK;
3452 }
3453
3454 static void init_proc_403 (CPUPPCState *env)
3455 {
3456 gen_spr_40x(env);
3457 gen_spr_401_403(env);
3458 gen_spr_403(env);
3459 gen_spr_403_real(env);
3460 init_excp_4xx_real(env);
3461 env->dcache_line_size = 32;
3462 env->icache_line_size = 32;
3463 /* Allocate hardware IRQ controller */
3464 ppc40x_irq_init(env);
3465
3466 SET_FIT_PERIOD(8, 12, 16, 20);
3467 SET_WDT_PERIOD(16, 20, 24, 28);
3468 }
3469
3470 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3471 {
3472 DeviceClass *dc = DEVICE_CLASS(oc);
3473 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3474
3475 dc->desc = "PowerPC 403";
3476 pcc->init_proc = init_proc_403;
3477 pcc->check_pow = check_pow_nocheck;
3478 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3479 PPC_DCR | PPC_WRTEE |
3480 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3481 PPC_CACHE_DCBZ |
3482 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3483 PPC_4xx_COMMON | PPC_40x_EXCP;
3484 pcc->insns_flags2 = PPC_NONE;
3485 pcc->msr_mask = 0x000000000007D00DULL;
3486 pcc->mmu_model = POWERPC_MMU_REAL;
3487 pcc->excp_model = POWERPC_EXCP_40x;
3488 pcc->bus_model = PPC_FLAGS_INPUT_401;
3489 pcc->bfd_mach = bfd_mach_ppc_403;
3490 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3491 POWERPC_FLAG_BUS_CLK;
3492 }
3493
3494 static void init_proc_403GCX (CPUPPCState *env)
3495 {
3496 gen_spr_40x(env);
3497 gen_spr_401_403(env);
3498 gen_spr_403(env);
3499 gen_spr_403_real(env);
3500 gen_spr_403_mmu(env);
3501 /* Bus access control */
3502 /* not emulated, as QEMU never does speculative access */
3503 spr_register(env, SPR_40x_SGR, "SGR",
3504 SPR_NOACCESS, SPR_NOACCESS,
3505 &spr_read_generic, &spr_write_generic,
3506 0xFFFFFFFF);
3507 /* not emulated, as QEMU do not emulate caches */
3508 spr_register(env, SPR_40x_DCWR, "DCWR",
3509 SPR_NOACCESS, SPR_NOACCESS,
3510 &spr_read_generic, &spr_write_generic,
3511 0x00000000);
3512 /* Memory management */
3513 #if !defined(CONFIG_USER_ONLY)
3514 env->nb_tlb = 64;
3515 env->nb_ways = 1;
3516 env->id_tlbs = 0;
3517 env->tlb_type = TLB_EMB;
3518 #endif
3519 init_excp_4xx_softmmu(env);
3520 env->dcache_line_size = 32;
3521 env->icache_line_size = 32;
3522 /* Allocate hardware IRQ controller */
3523 ppc40x_irq_init(env);
3524
3525 SET_FIT_PERIOD(8, 12, 16, 20);
3526 SET_WDT_PERIOD(16, 20, 24, 28);
3527 }
3528
3529 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3530 {
3531 DeviceClass *dc = DEVICE_CLASS(oc);
3532 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3533
3534 dc->desc = "PowerPC 403 GCX";
3535 pcc->init_proc = init_proc_403GCX;
3536 pcc->check_pow = check_pow_nocheck;
3537 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3538 PPC_DCR | PPC_WRTEE |
3539 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3540 PPC_CACHE_DCBZ |
3541 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3542 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3543 PPC_4xx_COMMON | PPC_40x_EXCP;
3544 pcc->insns_flags2 = PPC_NONE;
3545 pcc->msr_mask = 0x000000000007D00DULL;
3546 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3547 pcc->excp_model = POWERPC_EXCP_40x;
3548 pcc->bus_model = PPC_FLAGS_INPUT_401;
3549 pcc->bfd_mach = bfd_mach_ppc_403;
3550 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3551 POWERPC_FLAG_BUS_CLK;
3552 }
3553
3554 static void init_proc_405 (CPUPPCState *env)
3555 {
3556 /* Time base */
3557 gen_tbl(env);
3558 gen_spr_40x(env);
3559 gen_spr_405(env);
3560 /* Bus access control */
3561 /* not emulated, as QEMU never does speculative access */
3562 spr_register(env, SPR_40x_SGR, "SGR",
3563 SPR_NOACCESS, SPR_NOACCESS,
3564 &spr_read_generic, &spr_write_generic,
3565 0xFFFFFFFF);
3566 /* not emulated, as QEMU do not emulate caches */
3567 spr_register(env, SPR_40x_DCWR, "DCWR",
3568 SPR_NOACCESS, SPR_NOACCESS,
3569 &spr_read_generic, &spr_write_generic,
3570 0x00000000);
3571 /* Memory management */
3572 #if !defined(CONFIG_USER_ONLY)
3573 env->nb_tlb = 64;
3574 env->nb_ways = 1;
3575 env->id_tlbs = 0;
3576 env->tlb_type = TLB_EMB;
3577 #endif
3578 init_excp_4xx_softmmu(env);
3579 env->dcache_line_size = 32;
3580 env->icache_line_size = 32;
3581 /* Allocate hardware IRQ controller */
3582 ppc40x_irq_init(env);
3583
3584 SET_FIT_PERIOD(8, 12, 16, 20);
3585 SET_WDT_PERIOD(16, 20, 24, 28);
3586 }
3587
3588 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3589 {
3590 DeviceClass *dc = DEVICE_CLASS(oc);
3591 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3592
3593 dc->desc = "PowerPC 405";
3594 pcc->init_proc = init_proc_405;
3595 pcc->check_pow = check_pow_nocheck;
3596 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3597 PPC_DCR | PPC_WRTEE |
3598 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3599 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3600 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3601 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3602 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3603 pcc->insns_flags2 = PPC_NONE;
3604 pcc->msr_mask = 0x000000000006E630ULL;
3605 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3606 pcc->excp_model = POWERPC_EXCP_40x;
3607 pcc->bus_model = PPC_FLAGS_INPUT_405;
3608 pcc->bfd_mach = bfd_mach_ppc_403;
3609 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3610 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3611 }
3612
3613 static void init_proc_440EP (CPUPPCState *env)
3614 {
3615 /* Time base */
3616 gen_tbl(env);
3617 gen_spr_BookE(env, 0x000000000000FFFFULL);
3618 gen_spr_440(env);
3619 gen_spr_usprgh(env);
3620 /* Processor identification */
3621 spr_register(env, SPR_BOOKE_PIR, "PIR",
3622 SPR_NOACCESS, SPR_NOACCESS,
3623 &spr_read_generic, &spr_write_pir,
3624 0x00000000);
3625 /* XXX : not implemented */
3626 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3627 SPR_NOACCESS, SPR_NOACCESS,
3628 &spr_read_generic, &spr_write_generic,
3629 0x00000000);
3630 /* XXX : not implemented */
3631 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3632 SPR_NOACCESS, SPR_NOACCESS,
3633 &spr_read_generic, &spr_write_generic,
3634 0x00000000);
3635 /* XXX : not implemented */
3636 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3637 SPR_NOACCESS, SPR_NOACCESS,
3638 &spr_read_generic, &spr_write_generic,
3639 0x00000000);
3640 /* XXX : not implemented */
3641 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3642 SPR_NOACCESS, SPR_NOACCESS,
3643 &spr_read_generic, &spr_write_generic,
3644 0x00000000);
3645 /* XXX : not implemented */
3646 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3647 SPR_NOACCESS, SPR_NOACCESS,
3648 &spr_read_generic, &spr_write_generic,
3649 0x00000000);
3650 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3651 SPR_NOACCESS, SPR_NOACCESS,
3652 &spr_read_generic, &spr_write_generic,
3653 0x00000000);
3654 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3655 SPR_NOACCESS, SPR_NOACCESS,
3656 &spr_read_generic, &spr_write_generic,
3657 0x00000000);
3658 /* XXX : not implemented */
3659 spr_register(env, SPR_440_CCR1, "CCR1",
3660 SPR_NOACCESS, SPR_NOACCESS,
3661 &spr_read_generic, &spr_write_generic,
3662 0x00000000);
3663 /* Memory management */
3664 #if !defined(CONFIG_USER_ONLY)
3665 env->nb_tlb = 64;
3666 env->nb_ways = 1;
3667 env->id_tlbs = 0;
3668 env->tlb_type = TLB_EMB;
3669 #endif
3670 init_excp_BookE(env);
3671 env->dcache_line_size = 32;
3672 env->icache_line_size = 32;
3673 ppc40x_irq_init(env);
3674
3675 SET_FIT_PERIOD(12, 16, 20, 24);
3676 SET_WDT_PERIOD(20, 24, 28, 32);
3677 }
3678
3679 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3680 {
3681 DeviceClass *dc = DEVICE_CLASS(oc);
3682 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3683
3684 dc->desc = "PowerPC 440 EP";
3685 pcc->init_proc = init_proc_440EP;
3686 pcc->check_pow = check_pow_nocheck;
3687 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3688 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3689 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3690 PPC_FLOAT_STFIWX |
3691 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3692 PPC_CACHE | PPC_CACHE_ICBI |
3693 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3694 PPC_MEM_TLBSYNC | PPC_MFTB |
3695 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3696 PPC_440_SPEC;
3697 pcc->insns_flags2 = PPC_NONE;
3698 pcc->msr_mask = 0x000000000006FF30ULL;
3699 pcc->mmu_model = POWERPC_MMU_BOOKE;
3700 pcc->excp_model = POWERPC_EXCP_BOOKE;
3701 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3702 pcc->bfd_mach = bfd_mach_ppc_403;
3703 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3704 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3705 }
3706
3707 static void init_proc_440GP (CPUPPCState *env)
3708 {
3709 /* Time base */
3710 gen_tbl(env);
3711 gen_spr_BookE(env, 0x000000000000FFFFULL);
3712 gen_spr_440(env);
3713 gen_spr_usprgh(env);
3714 /* Processor identification */
3715 spr_register(env, SPR_BOOKE_PIR, "PIR",
3716 SPR_NOACCESS, SPR_NOACCESS,
3717 &spr_read_generic, &spr_write_pir,
3718 0x00000000);
3719 /* XXX : not implemented */
3720 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3721 SPR_NOACCESS, SPR_NOACCESS,
3722 &spr_read_generic, &spr_write_generic,
3723 0x00000000);
3724 /* XXX : not implemented */
3725 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3726 SPR_NOACCESS, SPR_NOACCESS,
3727 &spr_read_generic, &spr_write_generic,
3728 0x00000000);
3729 /* XXX : not implemented */
3730 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3731 SPR_NOACCESS, SPR_NOACCESS,
3732 &spr_read_generic, &spr_write_generic,
3733 0x00000000);
3734 /* XXX : not implemented */
3735 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3736 SPR_NOACCESS, SPR_NOACCESS,
3737 &spr_read_generic, &spr_write_generic,
3738 0x00000000);
3739 /* Memory management */
3740 #if !defined(CONFIG_USER_ONLY)
3741 env->nb_tlb = 64;
3742 env->nb_ways = 1;
3743 env->id_tlbs = 0;
3744 env->tlb_type = TLB_EMB;
3745 #endif
3746 init_excp_BookE(env);
3747 env->dcache_line_size = 32;
3748 env->icache_line_size = 32;
3749 /* XXX: TODO: allocate internal IRQ controller */
3750
3751 SET_FIT_PERIOD(12, 16, 20, 24);
3752 SET_WDT_PERIOD(20, 24, 28, 32);
3753 }
3754
3755 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3756 {
3757 DeviceClass *dc = DEVICE_CLASS(oc);
3758 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3759
3760 dc->desc = "PowerPC 440 GP";
3761 pcc->init_proc = init_proc_440GP;
3762 pcc->check_pow = check_pow_nocheck;
3763 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3764 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3765 PPC_CACHE | PPC_CACHE_ICBI |
3766 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3767 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3768 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3769 PPC_440_SPEC;
3770 pcc->insns_flags2 = PPC_NONE;
3771 pcc->msr_mask = 0x000000000006FF30ULL;
3772 pcc->mmu_model = POWERPC_MMU_BOOKE;
3773 pcc->excp_model = POWERPC_EXCP_BOOKE;
3774 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3775 pcc->bfd_mach = bfd_mach_ppc_403;
3776 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3777 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3778 }
3779
3780 static void init_proc_440x4 (CPUPPCState *env)
3781 {
3782 /* Time base */
3783 gen_tbl(env);
3784 gen_spr_BookE(env, 0x000000000000FFFFULL);
3785 gen_spr_440(env);
3786 gen_spr_usprgh(env);
3787 /* Processor identification */
3788 spr_register(env, SPR_BOOKE_PIR, "PIR",
3789 SPR_NOACCESS, SPR_NOACCESS,
3790 &spr_read_generic, &spr_write_pir,
3791 0x00000000);
3792 /* XXX : not implemented */
3793 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3794 SPR_NOACCESS, SPR_NOACCESS,
3795 &spr_read_generic, &spr_write_generic,
3796 0x00000000);
3797 /* XXX : not implemented */
3798 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3799 SPR_NOACCESS, SPR_NOACCESS,
3800 &spr_read_generic, &spr_write_generic,
3801 0x00000000);
3802 /* XXX : not implemented */
3803 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3804 SPR_NOACCESS, SPR_NOACCESS,
3805 &spr_read_generic, &spr_write_generic,
3806 0x00000000);
3807 /* XXX : not implemented */
3808 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3809 SPR_NOACCESS, SPR_NOACCESS,
3810 &spr_read_generic, &spr_write_generic,
3811 0x00000000);
3812 /* Memory management */
3813 #if !defined(CONFIG_USER_ONLY)
3814 env->nb_tlb = 64;
3815 env->nb_ways = 1;
3816 env->id_tlbs = 0;
3817 env->tlb_type = TLB_EMB;
3818 #endif
3819 init_excp_BookE(env);
3820 env->dcache_line_size = 32;
3821 env->icache_line_size = 32;
3822 /* XXX: TODO: allocate internal IRQ controller */
3823
3824 SET_FIT_PERIOD(12, 16, 20, 24);
3825 SET_WDT_PERIOD(20, 24, 28, 32);
3826 }
3827
3828 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3829 {
3830 DeviceClass *dc = DEVICE_CLASS(oc);
3831 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3832
3833 dc->desc = "PowerPC 440x4";
3834 pcc->init_proc = init_proc_440x4;
3835 pcc->check_pow = check_pow_nocheck;
3836 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3837 PPC_DCR | PPC_WRTEE |
3838 PPC_CACHE | PPC_CACHE_ICBI |
3839 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3840 PPC_MEM_TLBSYNC | PPC_MFTB |
3841 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3842 PPC_440_SPEC;
3843 pcc->insns_flags2 = PPC_NONE;
3844 pcc->msr_mask = 0x000000000006FF30ULL;
3845 pcc->mmu_model = POWERPC_MMU_BOOKE;
3846 pcc->excp_model = POWERPC_EXCP_BOOKE;
3847 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3848 pcc->bfd_mach = bfd_mach_ppc_403;
3849 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3850 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3851 }
3852
3853 static void init_proc_440x5 (CPUPPCState *env)
3854 {
3855 /* Time base */
3856 gen_tbl(env);
3857 gen_spr_BookE(env, 0x000000000000FFFFULL);
3858 gen_spr_440(env);
3859 gen_spr_usprgh(env);
3860 /* Processor identification */
3861 spr_register(env, SPR_BOOKE_PIR, "PIR",
3862 SPR_NOACCESS, SPR_NOACCESS,
3863 &spr_read_generic, &spr_write_pir,
3864 0x00000000);
3865 /* XXX : not implemented */
3866 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3867 SPR_NOACCESS, SPR_NOACCESS,
3868 &spr_read_generic, &spr_write_generic,
3869 0x00000000);
3870 /* XXX : not implemented */
3871 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3872 SPR_NOACCESS, SPR_NOACCESS,
3873 &spr_read_generic, &spr_write_generic,
3874 0x00000000);
3875 /* XXX : not implemented */
3876 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3877 SPR_NOACCESS, SPR_NOACCESS,
3878 &spr_read_generic, &spr_write_generic,
3879 0x00000000);
3880 /* XXX : not implemented */
3881 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3882 SPR_NOACCESS, SPR_NOACCESS,
3883 &spr_read_generic, &spr_write_generic,
3884 0x00000000);
3885 /* XXX : not implemented */
3886 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3887 SPR_NOACCESS, SPR_NOACCESS,
3888 &spr_read_generic, &spr_write_generic,
3889 0x00000000);
3890 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3891 SPR_NOACCESS, SPR_NOACCESS,
3892 &spr_read_generic, &spr_write_generic,
3893 0x00000000);
3894 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3895 SPR_NOACCESS, SPR_NOACCESS,
3896 &spr_read_generic, &spr_write_generic,
3897 0x00000000);
3898 /* XXX : not implemented */
3899 spr_register(env, SPR_440_CCR1, "CCR1",
3900 SPR_NOACCESS, SPR_NOACCESS,
3901 &spr_read_generic, &spr_write_generic,
3902 0x00000000);
3903 /* Memory management */
3904 #if !defined(CONFIG_USER_ONLY)
3905 env->nb_tlb = 64;
3906 env->nb_ways = 1;
3907 env->id_tlbs = 0;
3908 env->tlb_type = TLB_EMB;
3909 #endif
3910 init_excp_BookE(env);
3911 env->dcache_line_size = 32;
3912 env->icache_line_size = 32;
3913 ppc40x_irq_init(env);
3914
3915 SET_FIT_PERIOD(12, 16, 20, 24);
3916 SET_WDT_PERIOD(20, 24, 28, 32);
3917 }
3918
3919 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3920 {
3921 DeviceClass *dc = DEVICE_CLASS(oc);
3922 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3923
3924 dc->desc = "PowerPC 440x5";
3925 pcc->init_proc = init_proc_440x5;
3926 pcc->check_pow = check_pow_nocheck;
3927 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3928 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3929 PPC_CACHE | PPC_CACHE_ICBI |
3930 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3931 PPC_MEM_TLBSYNC | PPC_MFTB |
3932 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3933 PPC_440_SPEC;
3934 pcc->insns_flags2 = PPC_NONE;
3935 pcc->msr_mask = 0x000000000006FF30ULL;
3936 pcc->mmu_model = POWERPC_MMU_BOOKE;
3937 pcc->excp_model = POWERPC_EXCP_BOOKE;
3938 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3939 pcc->bfd_mach = bfd_mach_ppc_403;
3940 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3941 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3942 }
3943
3944 static void init_proc_460 (CPUPPCState *env)
3945 {
3946 /* Time base */
3947 gen_tbl(env);
3948 gen_spr_BookE(env, 0x000000000000FFFFULL);
3949 gen_spr_440(env);
3950 gen_spr_usprgh(env);
3951 /* Processor identification */
3952 spr_register(env, SPR_BOOKE_PIR, "PIR",
3953 SPR_NOACCESS, SPR_NOACCESS,
3954 &spr_read_generic, &spr_write_pir,
3955 0x00000000);
3956 /* XXX : not implemented */
3957 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3958 SPR_NOACCESS, SPR_NOACCESS,
3959 &spr_read_generic, &spr_write_generic,
3960 0x00000000);
3961 /* XXX : not implemented */
3962 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3963 SPR_NOACCESS, SPR_NOACCESS,
3964 &spr_read_generic, &spr_write_generic,
3965 0x00000000);
3966 /* XXX : not implemented */
3967 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3968 SPR_NOACCESS, SPR_NOACCESS,
3969 &spr_read_generic, &spr_write_generic,
3970 0x00000000);
3971 /* XXX : not implemented */
3972 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3973 SPR_NOACCESS, SPR_NOACCESS,
3974 &spr_read_generic, &spr_write_generic,
3975 0x00000000);
3976 /* XXX : not implemented */
3977 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3978 SPR_NOACCESS, SPR_NOACCESS,
3979 &spr_read_generic, &spr_write_generic,
3980 0x00000000);
3981 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3982 SPR_NOACCESS, SPR_NOACCESS,
3983 &spr_read_generic, &spr_write_generic,
3984 0x00000000);
3985 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3986 SPR_NOACCESS, SPR_NOACCESS,
3987 &spr_read_generic, &spr_write_generic,
3988 0x00000000);
3989 /* XXX : not implemented */
3990 spr_register(env, SPR_440_CCR1, "CCR1",
3991 SPR_NOACCESS, SPR_NOACCESS,
3992 &spr_read_generic, &spr_write_generic,
3993 0x00000000);
3994 /* XXX : not implemented */
3995 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3996 &spr_read_generic, &spr_write_generic,
3997 &spr_read_generic, &spr_write_generic,
3998 0x00000000);
3999 /* Memory management */
4000 #if !defined(CONFIG_USER_ONLY)
4001 env->nb_tlb = 64;
4002 env->nb_ways = 1;
4003 env->id_tlbs = 0;
4004 env->tlb_type = TLB_EMB;
4005 #endif
4006 init_excp_BookE(env);
4007 env->dcache_line_size = 32;
4008 env->icache_line_size = 32;
4009 /* XXX: TODO: allocate internal IRQ controller */
4010
4011 SET_FIT_PERIOD(12, 16, 20, 24);
4012 SET_WDT_PERIOD(20, 24, 28, 32);
4013 }
4014
4015 POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
4016 {
4017 DeviceClass *dc = DEVICE_CLASS(oc);
4018 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4019
4020 dc->desc = "PowerPC 460 (guessed)";
4021 pcc->init_proc = init_proc_460;
4022 pcc->check_pow = check_pow_nocheck;
4023 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4024 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4025 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
4026 PPC_CACHE | PPC_CACHE_ICBI |
4027 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4028 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4029 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4030 PPC_440_SPEC;
4031 pcc->insns_flags2 = PPC_NONE;
4032 pcc->msr_mask = 0x000000000006FF30ULL;
4033 pcc->mmu_model = POWERPC_MMU_BOOKE;
4034 pcc->excp_model = POWERPC_EXCP_BOOKE;
4035 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4036 pcc->bfd_mach = bfd_mach_ppc_403;
4037 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4038 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4039 }
4040
4041 static void init_proc_460F (CPUPPCState *env)
4042 {
4043 /* Time base */
4044 gen_tbl(env);
4045 gen_spr_BookE(env, 0x000000000000FFFFULL);
4046 gen_spr_440(env);
4047 gen_spr_usprgh(env);
4048 /* Processor identification */
4049 spr_register(env, SPR_BOOKE_PIR, "PIR",
4050 SPR_NOACCESS, SPR_NOACCESS,
4051 &spr_read_generic, &spr_write_pir,
4052 0x00000000);
4053 /* XXX : not implemented */
4054 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4055 SPR_NOACCESS, SPR_NOACCESS,
4056 &spr_read_generic, &spr_write_generic,
4057 0x00000000);
4058 /* XXX : not implemented */
4059 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4060 SPR_NOACCESS, SPR_NOACCESS,
4061 &spr_read_generic, &spr_write_generic,
4062 0x00000000);
4063 /* XXX : not implemented */
4064 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4065 SPR_NOACCESS, SPR_NOACCESS,
4066 &spr_read_generic, &spr_write_generic,
4067 0x00000000);
4068 /* XXX : not implemented */
4069 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4070 SPR_NOACCESS, SPR_NOACCESS,
4071 &spr_read_generic, &spr_write_generic,
4072 0x00000000);
4073 /* XXX : not implemented */
4074 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4075 SPR_NOACCESS, SPR_NOACCESS,
4076 &spr_read_generic, &spr_write_generic,
4077 0x00000000);
4078 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4079 SPR_NOACCESS, SPR_NOACCESS,
4080 &spr_read_generic, &spr_write_generic,
4081 0x00000000);
4082 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4083 SPR_NOACCESS, SPR_NOACCESS,
4084 &spr_read_generic, &spr_write_generic,
4085 0x00000000);
4086 /* XXX : not implemented */
4087 spr_register(env, SPR_440_CCR1, "CCR1",
4088 SPR_NOACCESS, SPR_NOACCESS,
4089 &spr_read_generic, &spr_write_generic,
4090 0x00000000);
4091 /* XXX : not implemented */
4092 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4093 &spr_read_generic, &spr_write_generic,
4094 &spr_read_generic, &spr_write_generic,
4095 0x00000000);
4096 /* Memory management */
4097 #if !defined(CONFIG_USER_ONLY)
4098 env->nb_tlb = 64;
4099 env->nb_ways = 1;
4100 env->id_tlbs = 0;
4101 env->tlb_type = TLB_EMB;
4102 #endif
4103 init_excp_BookE(env);
4104 env->dcache_line_size = 32;
4105 env->icache_line_size = 32;
4106 /* XXX: TODO: allocate internal IRQ controller */
4107
4108 SET_FIT_PERIOD(12, 16, 20, 24);
4109 SET_WDT_PERIOD(20, 24, 28, 32);
4110 }
4111
4112 POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
4113 {
4114 DeviceClass *dc = DEVICE_CLASS(oc);
4115 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4116
4117 dc->desc = "PowerPC 460F (guessed)";
4118 pcc->init_proc = init_proc_460F;
4119 pcc->check_pow = check_pow_nocheck;
4120 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4121 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
4122 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4123 PPC_FLOAT_STFIWX | PPC_MFTB |
4124 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4125 PPC_WRTEE | PPC_MFAPIDI |
4126 PPC_CACHE | PPC_CACHE_ICBI |
4127 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4128 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4129 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4130 PPC_440_SPEC;
4131 pcc->insns_flags2 = PPC_NONE;
4132 pcc->msr_mask = 0x000000000006FF30ULL;
4133 pcc->mmu_model = POWERPC_MMU_BOOKE;
4134 pcc->excp_model = POWERPC_EXCP_BOOKE;
4135 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4136 pcc->bfd_mach = bfd_mach_ppc_403;
4137 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4138 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4139 }
4140
4141 static void init_proc_MPC5xx (CPUPPCState *env)
4142 {
4143 /* Time base */
4144 gen_tbl(env);
4145 gen_spr_5xx_8xx(env);
4146 gen_spr_5xx(env);
4147 init_excp_MPC5xx(env);
4148 env->dcache_line_size = 32;
4149 env->icache_line_size = 32;
4150 /* XXX: TODO: allocate internal IRQ controller */
4151 }
4152
4153 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4154 {
4155 DeviceClass *dc = DEVICE_CLASS(oc);
4156 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4157
4158 dc->desc = "Freescale 5xx cores (aka RCPU)";
4159 pcc->init_proc = init_proc_MPC5xx;
4160 pcc->check_pow = check_pow_none;
4161 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4162 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4163 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4164 PPC_MFTB;
4165 pcc->insns_flags2 = PPC_NONE;
4166 pcc->msr_mask = 0x000000000001FF43ULL;
4167 pcc->mmu_model = POWERPC_MMU_REAL;
4168 pcc->excp_model = POWERPC_EXCP_603;
4169 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4170 pcc->bfd_mach = bfd_mach_ppc_505;
4171 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4172 POWERPC_FLAG_BUS_CLK;
4173 }
4174
4175 static void init_proc_MPC8xx (CPUPPCState *env)
4176 {
4177 /* Time base */
4178 gen_tbl(env);
4179 gen_spr_5xx_8xx(env);
4180 gen_spr_8xx(env);
4181 init_excp_MPC8xx(env);
4182 env->dcache_line_size = 32;
4183 env->icache_line_size = 32;
4184 /* XXX: TODO: allocate internal IRQ controller */
4185 }
4186
4187 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4188 {
4189 DeviceClass *dc = DEVICE_CLASS(oc);
4190 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4191
4192 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4193 pcc->init_proc = init_proc_MPC8xx;
4194 pcc->check_pow = check_pow_none;
4195 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4196 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4197 PPC_CACHE_ICBI | PPC_MFTB;
4198 pcc->insns_flags2 = PPC_NONE;
4199 pcc->msr_mask = 0x000000000001F673ULL;
4200 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4201 pcc->excp_model = POWERPC_EXCP_603;
4202 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4203 pcc->bfd_mach = bfd_mach_ppc_860;
4204 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4205 POWERPC_FLAG_BUS_CLK;
4206 }
4207
4208 /* Freescale 82xx cores (aka PowerQUICC-II) */
4209
4210 static void init_proc_G2 (CPUPPCState *env)
4211 {
4212 gen_spr_ne_601(env);
4213 gen_spr_G2_755(env);
4214 gen_spr_G2(env);
4215 /* Time base */
4216 gen_tbl(env);
4217 /* External access control */
4218 /* XXX : not implemented */
4219 spr_register(env, SPR_EAR, "EAR",
4220 SPR_NOACCESS, SPR_NOACCESS,
4221 &spr_read_generic, &spr_write_generic,
4222 0x00000000);
4223 /* Hardware implementation register */
4224 /* XXX : not implemented */
4225 spr_register(env, SPR_HID0, "HID0",
4226 SPR_NOACCESS, SPR_NOACCESS,
4227 &spr_read_generic, &spr_write_generic,
4228 0x00000000);
4229 /* XXX : not implemented */
4230 spr_register(env, SPR_HID1, "HID1",
4231 SPR_NOACCESS, SPR_NOACCESS,
4232 &spr_read_generic, &spr_write_generic,
4233 0x00000000);
4234 /* XXX : not implemented */
4235 spr_register(env, SPR_HID2, "HID2",
4236 SPR_NOACCESS, SPR_NOACCESS,
4237 &spr_read_generic, &spr_write_generic,
4238 0x00000000);
4239 /* Memory management */
4240 gen_low_BATs(env);
4241 gen_high_BATs(env);
4242 gen_6xx_7xx_soft_tlb(env, 64, 2);
4243 init_excp_G2(env);
4244 env->dcache_line_size = 32;
4245 env->icache_line_size = 32;
4246 /* Allocate hardware IRQ controller */
4247 ppc6xx_irq_init(env);
4248 }
4249
4250 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4251 {
4252 DeviceClass *dc = DEVICE_CLASS(oc);
4253 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4254
4255 dc->desc = "PowerPC G2";
4256 pcc->init_proc = init_proc_G2;
4257 pcc->check_pow = check_pow_hid0;
4258 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4259 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4260 PPC_FLOAT_STFIWX |
4261 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4262 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4263 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4264 PPC_SEGMENT | PPC_EXTERN;
4265 pcc->insns_flags2 = PPC_NONE;
4266 pcc->msr_mask = 0x000000000006FFF2ULL;
4267 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4268 pcc->excp_model = POWERPC_EXCP_G2;
4269 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4270 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4271 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4272 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4273 }
4274
4275 static void init_proc_G2LE (CPUPPCState *env)
4276 {
4277 gen_spr_ne_601(env);
4278 gen_spr_G2_755(env);
4279 gen_spr_G2(env);
4280 /* Time base */
4281 gen_tbl(env);
4282 /* External access control */
4283 /* XXX : not implemented */
4284 spr_register(env, SPR_EAR, "EAR",
4285 SPR_NOACCESS, SPR_NOACCESS,
4286 &spr_read_generic, &spr_write_generic,
4287 0x00000000);
4288 /* Hardware implementation register */
4289 /* XXX : not implemented */
4290 spr_register(env, SPR_HID0, "HID0",
4291 SPR_NOACCESS, SPR_NOACCESS,
4292 &spr_read_generic, &spr_write_generic,
4293 0x00000000);
4294 /* XXX : not implemented */
4295 spr_register(env, SPR_HID1, "HID1",
4296 SPR_NOACCESS, SPR_NOACCESS,
4297 &spr_read_generic, &spr_write_generic,
4298 0x00000000);
4299 /* XXX : not implemented */
4300 spr_register(env, SPR_HID2, "HID2",
4301 SPR_NOACCESS, SPR_NOACCESS,
4302 &spr_read_generic, &spr_write_generic,
4303 0x00000000);
4304 /* Memory management */
4305 gen_low_BATs(env);
4306 gen_high_BATs(env);
4307 gen_6xx_7xx_soft_tlb(env, 64, 2);
4308 init_excp_G2(env);
4309 env->dcache_line_size = 32;
4310 env->icache_line_size = 32;
4311 /* Allocate hardware IRQ controller */
4312 ppc6xx_irq_init(env);
4313 }
4314
4315 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4316 {
4317 DeviceClass *dc = DEVICE_CLASS(oc);
4318 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4319
4320 dc->desc = "PowerPC G2LE";
4321 pcc->init_proc = init_proc_G2LE;
4322 pcc->check_pow = check_pow_hid0;
4323 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4324 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4325 PPC_FLOAT_STFIWX |
4326 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4327 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4328 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4329 PPC_SEGMENT | PPC_EXTERN;
4330 pcc->insns_flags2 = PPC_NONE;
4331 pcc->msr_mask = 0x000000000007FFF3ULL;
4332 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4333 pcc->excp_model = POWERPC_EXCP_G2;
4334 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4335 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4336 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4337 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4338 }
4339
4340 static void init_proc_e200 (CPUPPCState *env)
4341 {
4342 /* Time base */
4343 gen_tbl(env);
4344 gen_spr_BookE(env, 0x000000070000FFFFULL);
4345 /* XXX : not implemented */
4346 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4347 &spr_read_spefscr, &spr_write_spefscr,
4348 &spr_read_spefscr, &spr_write_spefscr,
4349 0x00000000);
4350 /* Memory management */
4351 gen_spr_BookE206(env, 0x0000005D, NULL);
4352 /* XXX : not implemented */
4353 spr_register(env, SPR_HID0, "HID0",
4354 SPR_NOACCESS, SPR_NOACCESS,
4355 &spr_read_generic, &spr_write_generic,
4356 0x00000000);
4357 /* XXX : not implemented */
4358 spr_register(env, SPR_HID1, "HID1",
4359 SPR_NOACCESS, SPR_NOACCESS,
4360 &spr_read_generic, &spr_write_generic,
4361 0x00000000);
4362 /* XXX : not implemented */
4363 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4364 SPR_NOACCESS, SPR_NOACCESS,
4365 &spr_read_generic, &spr_write_generic,
4366 0x00000000);
4367 /* XXX : not implemented */
4368 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4369 SPR_NOACCESS, SPR_NOACCESS,
4370 &spr_read_generic, &spr_write_generic,
4371 0x00000000);
4372 /* XXX : not implemented */
4373 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4374 SPR_NOACCESS, SPR_NOACCESS,
4375 &spr_read_generic, &spr_write_generic,
4376 0x00000000);
4377 /* XXX : not implemented */
4378 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4379 SPR_NOACCESS, SPR_NOACCESS,
4380 &spr_read_generic, &spr_write_generic,
4381 0x00000000);
4382 /* XXX : not implemented */
4383 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4384 SPR_NOACCESS, SPR_NOACCESS,
4385 &spr_read_generic, &spr_write_generic,
4386 0x00000000);
4387 /* XXX : not implemented */
4388 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4389 SPR_NOACCESS, SPR_NOACCESS,
4390 &spr_read_generic, &spr_write_generic,
4391 0x00000000);
4392 /* XXX : not implemented */
4393 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4394 SPR_NOACCESS, SPR_NOACCESS,
4395 &spr_read_generic, &spr_write_generic,
4396 0x00000000);
4397 /* XXX : not implemented */
4398 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4399 SPR_NOACCESS, SPR_NOACCESS,
4400 &spr_read_generic, &spr_write_generic,
4401 0x00000000);
4402 /* XXX : not implemented */
4403 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4404 SPR_NOACCESS, SPR_NOACCESS,
4405 &spr_read_generic, &spr_write_generic,
4406 0x00000000);
4407 /* XXX : not implemented */
4408 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4409 SPR_NOACCESS, SPR_NOACCESS,
4410 &spr_read_generic, &spr_write_generic,
4411 0x00000000);
4412 /* XXX : not implemented */
4413 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4414 SPR_NOACCESS, SPR_NOACCESS,
4415 &spr_read_generic, &spr_write_generic,
4416 0x00000000);
4417 /* XXX : not implemented */
4418 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4419 SPR_NOACCESS, SPR_NOACCESS,
4420 &spr_read_generic, &spr_write_generic,
4421 0x00000000);
4422 /* XXX : not implemented */
4423 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4424 SPR_NOACCESS, SPR_NOACCESS,
4425 &spr_read_generic, &spr_write_generic,
4426 0x00000000); /* TOFIX */
4427 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4428 SPR_NOACCESS, SPR_NOACCESS,
4429 &spr_read_generic, &spr_write_generic,
4430 0x00000000);
4431 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4432 SPR_NOACCESS, SPR_NOACCESS,
4433 &spr_read_generic, &spr_write_generic,
4434 0x00000000);
4435 #if !defined(CONFIG_USER_ONLY)
4436 env->nb_tlb = 64;
4437 env->nb_ways = 1;
4438 env->id_tlbs = 0;
4439 env->tlb_type = TLB_EMB;
4440 #endif
4441 init_excp_e200(env, 0xFFFF0000UL);
4442 env->dcache_line_size = 32;
4443 env->icache_line_size = 32;
4444 /* XXX: TODO: allocate internal IRQ controller */
4445 }
4446
4447 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4448 {
4449 DeviceClass *dc = DEVICE_CLASS(oc);
4450 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4451
4452 dc->desc = "e200 core";
4453 pcc->init_proc = init_proc_e200;
4454 pcc->check_pow = check_pow_hid0;
4455 /* XXX: unimplemented instructions:
4456 * dcblc
4457 * dcbtlst
4458 * dcbtstls
4459 * icblc
4460 * icbtls
4461 * tlbivax
4462 * all SPE multiply-accumulate instructions
4463 */
4464 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4465 PPC_SPE | PPC_SPE_SINGLE |
4466 PPC_WRTEE | PPC_RFDI |
4467 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4468 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4469 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4470 PPC_BOOKE;
4471 pcc->insns_flags2 = PPC_NONE;
4472 pcc->msr_mask = 0x000000000606FF30ULL;
4473 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4474 pcc->excp_model = POWERPC_EXCP_BOOKE;
4475 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4476 pcc->bfd_mach = bfd_mach_ppc_860;
4477 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4478 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4479 POWERPC_FLAG_BUS_CLK;
4480 }
4481
4482 static void init_proc_e300 (CPUPPCState *env)
4483 {
4484 gen_spr_ne_601(env);
4485 gen_spr_603(env);
4486 /* Time base */
4487 gen_tbl(env);
4488 /* hardware implementation registers */
4489 /* XXX : not implemented */
4490 spr_register(env, SPR_HID0, "HID0",
4491 SPR_NOACCESS, SPR_NOACCESS,
4492 &spr_read_generic, &spr_write_generic,
4493 0x00000000);
4494 /* XXX : not implemented */
4495 spr_register(env, SPR_HID1, "HID1",
4496 SPR_NOACCESS, SPR_NOACCESS,
4497 &spr_read_generic, &spr_write_generic,
4498 0x00000000);
4499 /* XXX : not implemented */
4500 spr_register(env, SPR_HID2, "HID2",
4501 SPR_NOACCESS, SPR_NOACCESS,
4502 &spr_read_generic, &spr_write_generic,
4503 0x00000000);
4504 /* Memory management */
4505 gen_low_BATs(env);
4506 gen_high_BATs(env);
4507 gen_6xx_7xx_soft_tlb(env, 64, 2);
4508 init_excp_603(env);
4509 env->dcache_line_size = 32;
4510 env->icache_line_size = 32;
4511 /* Allocate hardware IRQ controller */
4512 ppc6xx_irq_init(env);
4513 }
4514
4515 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4516 {
4517 DeviceClass *dc = DEVICE_CLASS(oc);
4518 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4519
4520 dc->desc = "e300 core";
4521 pcc->init_proc = init_proc_e300;
4522 pcc->check_pow = check_pow_hid0;
4523 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4524 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4525 PPC_FLOAT_STFIWX |
4526 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4527 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4528 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4529 PPC_SEGMENT | PPC_EXTERN;
4530 pcc->insns_flags2 = PPC_NONE;
4531 pcc->msr_mask = 0x000000000007FFF3ULL;
4532 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4533 pcc->excp_model = POWERPC_EXCP_603;
4534 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4535 pcc->bfd_mach = bfd_mach_ppc_603;
4536 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4537 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4538 }
4539
4540 #if !defined(CONFIG_USER_ONLY)
4541 static void spr_write_mas73(void *opaque, int sprn, int gprn)
4542 {
4543 TCGv val = tcg_temp_new();
4544 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4545 gen_store_spr(SPR_BOOKE_MAS3, val);
4546 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4547 gen_store_spr(SPR_BOOKE_MAS7, val);
4548 tcg_temp_free(val);
4549 }
4550
4551 static void spr_read_mas73(void *opaque, int gprn, int sprn)
4552 {
4553 TCGv mas7 = tcg_temp_new();
4554 TCGv mas3 = tcg_temp_new();
4555 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4556 tcg_gen_shli_tl(mas7, mas7, 32);
4557 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4558 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4559 tcg_temp_free(mas3);
4560 tcg_temp_free(mas7);
4561 }
4562
4563 #endif
4564
4565 enum fsl_e500_version {
4566 fsl_e500v1,
4567 fsl_e500v2,
4568 fsl_e500mc,
4569 fsl_e5500,
4570 };
4571
4572 static void init_proc_e500 (CPUPPCState *env, int version)
4573 {
4574 uint32_t tlbncfg[2];
4575 uint64_t ivor_mask;
4576 uint64_t ivpr_mask = 0xFFFF0000ULL;
4577 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4578 | 0x0020; /* 32 kb */
4579 #if !defined(CONFIG_USER_ONLY)
4580 int i;
4581 #endif
4582
4583 /* Time base */
4584 gen_tbl(env);
4585 /*
4586 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4587 * complain when accessing them.
4588 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4589 */
4590 switch (version) {
4591 case fsl_e500v1:
4592 case fsl_e500v2:
4593 default:
4594 ivor_mask = 0x0000000F0000FFFFULL;
4595 break;
4596 case fsl_e500mc:
4597 case fsl_e5500:
4598 ivor_mask = 0x000003FE0000FFFFULL;
4599 break;
4600 }
4601 gen_spr_BookE(env, ivor_mask);
4602 /* Processor identification */
4603 spr_register(env, SPR_BOOKE_PIR, "PIR",
4604 SPR_NOACCESS, SPR_NOACCESS,
4605 &spr_read_generic, &spr_write_pir,
4606 0x00000000);
4607 /* XXX : not implemented */
4608 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4609 &spr_read_spefscr, &spr_write_spefscr,
4610 &spr_read_spefscr, &spr_write_spefscr,
4611 0x00000000);
4612 #if !defined(CONFIG_USER_ONLY)
4613 /* Memory management */
4614 env->nb_pids = 3;
4615 env->nb_ways = 2;
4616 env->id_tlbs = 0;
4617 switch (version) {
4618 case fsl_e500v1:
4619 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4620 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4621 break;
4622 case fsl_e500v2:
4623 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4624 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4625 break;
4626 case fsl_e500mc:
4627 case fsl_e5500:
4628 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4629 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4630 break;
4631 default:
4632 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4633 }
4634 #endif
4635 /* Cache sizes */
4636 switch (version) {
4637 case fsl_e500v1:
4638 case fsl_e500v2:
4639 env->dcache_line_size = 32;
4640 env->icache_line_size = 32;
4641 break;
4642 case fsl_e500mc:
4643 case fsl_e5500:
4644 env->dcache_line_size = 64;
4645 env->icache_line_size = 64;
4646 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4647 break;
4648 default:
4649 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4650 }
4651 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4652 /* XXX : not implemented */
4653 spr_register(env, SPR_HID0, "HID0",
4654 SPR_NOACCESS, SPR_NOACCESS,
4655 &spr_read_generic, &spr_write_generic,
4656 0x00000000);
4657 /* XXX : not implemented */
4658 spr_register(env, SPR_HID1, "HID1",
4659 SPR_NOACCESS, SPR_NOACCESS,
4660 &spr_read_generic, &spr_write_generic,
4661 0x00000000);
4662 /* XXX : not implemented */
4663 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4664 SPR_NOACCESS, SPR_NOACCESS,
4665 &spr_read_generic, &spr_write_generic,
4666 0x00000000);
4667 /* XXX : not implemented */
4668 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4669 SPR_NOACCESS, SPR_NOACCESS,
4670 &spr_read_generic, &spr_write_generic,
4671 0x00000000);
4672 /* XXX : not implemented */
4673 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4674 SPR_NOACCESS, SPR_NOACCESS,
4675 &spr_read_generic, &spr_write_generic,
4676 0x00000000);
4677 /* XXX : not implemented */
4678 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4679 SPR_NOACCESS, SPR_NOACCESS,
4680 &spr_read_generic, &spr_write_generic,
4681 0x00000000);
4682 /* XXX : not implemented */
4683 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4684 SPR_NOACCESS, SPR_NOACCESS,
4685 &spr_read_generic, &spr_write_generic,
4686 0x00000000);
4687 /* XXX : not implemented */
4688 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4689 SPR_NOACCESS, SPR_NOACCESS,
4690 &spr_read_generic, &spr_write_generic,
4691 0x00000000);
4692 /* XXX : not implemented */
4693 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4694 SPR_NOACCESS, SPR_NOACCESS,
4695 &spr_read_generic, &spr_write_generic,
4696 l1cfg0);
4697 /* XXX : not implemented */
4698 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4699 SPR_NOACCESS, SPR_NOACCESS,
4700 &spr_read_generic, &spr_write_e500_l1csr0,
4701 0x00000000);
4702 /* XXX : not implemented */
4703 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4704 SPR_NOACCESS, SPR_NOACCESS,
4705 &spr_read_generic, &spr_write_generic,
4706 0x00000000);
4707 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4708 SPR_NOACCESS, SPR_NOACCESS,
4709 &spr_read_generic, &spr_write_generic,
4710 0x00000000);
4711 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4712 SPR_NOACCESS, SPR_NOACCESS,
4713 &spr_read_generic, &spr_write_generic,
4714 0x00000000);
4715 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4716 SPR_NOACCESS, SPR_NOACCESS,
4717 &spr_read_generic, &spr_write_booke206_mmucsr0,
4718 0x00000000);
4719 spr_register(env, SPR_BOOKE_EPR, "EPR",
4720 SPR_NOACCESS, SPR_NOACCESS,
4721 &spr_read_generic, SPR_NOACCESS,
4722 0x00000000);
4723 /* XXX better abstract into Emb.xxx features */
4724 if (version == fsl_e5500) {
4725 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4726 SPR_NOACCESS, SPR_NOACCESS,
4727 &spr_read_generic, &spr_write_generic,
4728 0x00000000);
4729 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4730 SPR_NOACCESS, SPR_NOACCESS,
4731 &spr_read_mas73, &spr_write_mas73,
4732 0x00000000);
4733 ivpr_mask = (target_ulong)~0xFFFFULL;
4734 }
4735
4736 #if !defined(CONFIG_USER_ONLY)
4737 env->nb_tlb = 0;
4738 env->tlb_type = TLB_MAS;
4739 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4740 env->nb_tlb += booke206_tlb_size(env, i);
4741 }
4742 #endif
4743
4744 init_excp_e200(env, ivpr_mask);
4745 /* Allocate hardware IRQ controller */
4746 ppce500_irq_init(env);
4747 }
4748
4749 static void init_proc_e500v1(CPUPPCState *env)
4750 {
4751 init_proc_e500(env, fsl_e500v1);
4752 }
4753
4754 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4755 {
4756 DeviceClass *dc = DEVICE_CLASS(oc);
4757 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4758
4759 dc->desc = "e500v1 core";
4760 pcc->init_proc = init_proc_e500v1;
4761 pcc->check_pow = check_pow_hid0;
4762 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4763 PPC_SPE | PPC_SPE_SINGLE |
4764 PPC_WRTEE | PPC_RFDI |
4765 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4766 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4767 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4768 pcc->insns_flags2 = PPC2_BOOKE206;
4769 pcc->msr_mask = 0x000000000606FF30ULL;
4770 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4771 pcc->excp_model = POWERPC_EXCP_BOOKE;
4772 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4773 pcc->bfd_mach = bfd_mach_ppc_860;
4774 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4775 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4776 POWERPC_FLAG_BUS_CLK;
4777 }
4778
4779 static void init_proc_e500v2(CPUPPCState *env)
4780 {
4781 init_proc_e500(env, fsl_e500v2);
4782 }
4783
4784 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4785 {
4786 DeviceClass *dc = DEVICE_CLASS(oc);
4787 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4788
4789 dc->desc = "e500v2 core";
4790 pcc->init_proc = init_proc_e500v2;
4791 pcc->check_pow = check_pow_hid0;
4792 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4793 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4794 PPC_WRTEE | PPC_RFDI |
4795 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4796 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4797 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4798 pcc->insns_flags2 = PPC2_BOOKE206;
4799 pcc->msr_mask = 0x000000000606FF30ULL;
4800 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4801 pcc->excp_model = POWERPC_EXCP_BOOKE;
4802 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4803 pcc->bfd_mach = bfd_mach_ppc_860;
4804 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4805 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4806 POWERPC_FLAG_BUS_CLK;
4807 }
4808
4809 static void init_proc_e500mc(CPUPPCState *env)
4810 {
4811 init_proc_e500(env, fsl_e500mc);
4812 }
4813
4814 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4815 {
4816 DeviceClass *dc = DEVICE_CLASS(oc);
4817 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4818
4819 dc->desc = "e500mc core";
4820 pcc->init_proc = init_proc_e500mc;
4821 pcc->check_pow = check_pow_none;
4822 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4823 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4824 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4825 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4826 PPC_FLOAT | PPC_FLOAT_FRES |
4827 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4828 PPC_FLOAT_STFIWX | PPC_WAIT |
4829 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4830 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4831 pcc->msr_mask = 0x000000001402FB36ULL;
4832 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4833 pcc->excp_model = POWERPC_EXCP_BOOKE;
4834 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4835 /* FIXME: figure out the correct flag for e500mc */
4836 pcc->bfd_mach = bfd_mach_ppc_e500;
4837 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4838 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4839 }
4840
4841 #ifdef TARGET_PPC64
4842 static void init_proc_e5500(CPUPPCState *env)
4843 {
4844 init_proc_e500(env, fsl_e5500);
4845 }
4846
4847 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
4848 {
4849 DeviceClass *dc = DEVICE_CLASS(oc);
4850 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4851
4852 dc->desc = "e5500 core";
4853 pcc->init_proc = init_proc_e5500;
4854 pcc->check_pow = check_pow_none;
4855 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4856 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4857 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4858 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4859 PPC_FLOAT | PPC_FLOAT_FRES |
4860 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4861 PPC_FLOAT_STFIWX | PPC_WAIT |
4862 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4863 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
4864 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4865 pcc->msr_mask = 0x000000009402FB36ULL;
4866 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4867 pcc->excp_model = POWERPC_EXCP_BOOKE;
4868 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4869 /* FIXME: figure out the correct flag for e5500 */
4870 pcc->bfd_mach = bfd_mach_ppc_e500;
4871 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4872 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4873 }
4874 #endif
4875
4876 /* Non-embedded PowerPC */
4877
4878 /* POWER : same as 601, without mfmsr, mfsr */
4879 #if defined(TODO)
4880 POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
4881 {
4882 DeviceClass *dc = DEVICE_CLASS(oc);
4883 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4884
4885 dc->desc = "POWER";
4886 pcc->insns_flags = XXX_TODO;
4887 /* POWER RSC (from RAD6000) */
4888 pcc->msr_mask = 0x00000000FEF0ULL;
4889 }
4890 #endif /* TODO */
4891
4892 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4893
4894 static void init_proc_601 (CPUPPCState *env)
4895 {
4896 gen_spr_ne_601(env);
4897 gen_spr_601(env);
4898 /* Hardware implementation registers */
4899 /* XXX : not implemented */
4900 spr_register(env, SPR_HID0, "HID0",
4901 SPR_NOACCESS, SPR_NOACCESS,
4902 &spr_read_generic, &spr_write_hid0_601,
4903 0x80010080);
4904 /* XXX : not implemented */
4905 spr_register(env, SPR_HID1, "HID1",
4906 SPR_NOACCESS, SPR_NOACCESS,
4907 &spr_read_generic, &spr_write_generic,
4908 0x00000000);
4909 /* XXX : not implemented */
4910 spr_register(env, SPR_601_HID2, "HID2",
4911 SPR_NOACCESS, SPR_NOACCESS,
4912 &spr_read_generic, &spr_write_generic,
4913 0x00000000);
4914 /* XXX : not implemented */
4915 spr_register(env, SPR_601_HID5, "HID5",
4916 SPR_NOACCESS, SPR_NOACCESS,
4917 &spr_read_generic, &spr_write_generic,
4918 0x00000000);
4919 /* Memory management */
4920 init_excp_601(env);
4921 /* XXX: beware that dcache line size is 64
4922 * but dcbz uses 32 bytes "sectors"
4923 * XXX: this breaks clcs instruction !
4924 */
4925 env->dcache_line_size = 32;
4926 env->icache_line_size = 64;
4927 /* Allocate hardware IRQ controller */
4928 ppc6xx_irq_init(env);
4929 }
4930
4931 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
4932 {
4933 DeviceClass *dc = DEVICE_CLASS(oc);
4934 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4935
4936 dc->desc = "PowerPC 601";
4937 pcc->init_proc = init_proc_601;
4938 pcc->check_pow = check_pow_none;
4939 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4940 PPC_FLOAT |
4941 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4942 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4943 PPC_SEGMENT | PPC_EXTERN;
4944 pcc->insns_flags2 = PPC_NONE;
4945 pcc->msr_mask = 0x000000000000FD70ULL;
4946 pcc->mmu_model = POWERPC_MMU_601;
4947 pcc->excp_model = POWERPC_EXCP_601;
4948 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4949 pcc->bfd_mach = bfd_mach_ppc_601;
4950 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
4951 }
4952
4953 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4954
4955 static void init_proc_601v (CPUPPCState *env)
4956 {
4957 init_proc_601(env);
4958 /* XXX : not implemented */
4959 spr_register(env, SPR_601_HID15, "HID15",
4960 SPR_NOACCESS, SPR_NOACCESS,
4961 &spr_read_generic, &spr_write_generic,
4962 0x00000000);
4963 }
4964
4965 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
4966 {
4967 DeviceClass *dc = DEVICE_CLASS(oc);
4968 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4969
4970 dc->desc = "PowerPC 601v";
4971 pcc->init_proc = init_proc_601v;
4972 pcc->check_pow = check_pow_none;
4973 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4974 PPC_FLOAT |
4975 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4976 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4977 PPC_SEGMENT | PPC_EXTERN;
4978 pcc->insns_flags2 = PPC_NONE;
4979 pcc->msr_mask = 0x000000000000FD70ULL;
4980 pcc->mmu_model = POWERPC_MMU_601;
4981 pcc->excp_model = POWERPC_EXCP_601;
4982 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4983 pcc->bfd_mach = bfd_mach_ppc_601;
4984 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
4985 }
4986
4987 static void init_proc_602 (CPUPPCState *env)
4988 {
4989 gen_spr_ne_601(env);
4990 gen_spr_602(env);
4991 /* Time base */
4992 gen_tbl(env);
4993 /* hardware implementation registers */
4994 /* XXX : not implemented */
4995 spr_register(env, SPR_HID0, "HID0",
4996 SPR_NOACCESS, SPR_NOACCESS,
4997 &spr_read_generic, &spr_write_generic,
4998 0x00000000);
4999 /* XXX : not implemented */
5000 spr_register(env, SPR_HID1, "HID1",
5001 SPR_NOACCESS, SPR_NOACCESS,
5002 &spr_read_generic, &spr_write_generic,
5003 0x00000000);
5004 /* Memory management */
5005 gen_low_BATs(env);
5006 gen_6xx_7xx_soft_tlb(env, 64, 2);
5007 init_excp_602(env);
5008 env->dcache_line_size = 32;
5009 env->icache_line_size = 32;
5010 /* Allocate hardware IRQ controller */
5011 ppc6xx_irq_init(env);
5012 }
5013
5014 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
5015 {
5016 DeviceClass *dc = DEVICE_CLASS(oc);
5017 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5018
5019 dc->desc = "PowerPC 602";
5020 pcc->init_proc = init_proc_602;
5021 pcc->check_pow = check_pow_hid0;
5022 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5023 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5024 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5025 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5026 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5027 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
5028 PPC_SEGMENT | PPC_602_SPEC;
5029 pcc->insns_flags2 = PPC_NONE;
5030 pcc->msr_mask = 0x0000000000C7FF73ULL;
5031 /* XXX: 602 MMU is quite specific. Should add a special case */
5032 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5033 pcc->excp_model = POWERPC_EXCP_602;
5034 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5035 pcc->bfd_mach = bfd_mach_ppc_602;
5036 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5037 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5038 }
5039
5040 static void init_proc_603 (CPUPPCState *env)
5041 {
5042 gen_spr_ne_601(env);
5043 gen_spr_603(env);
5044 /* Time base */
5045 gen_tbl(env);
5046 /* hardware implementation registers */
5047 /* XXX : not implemented */
5048 spr_register(env, SPR_HID0, "HID0",
5049 SPR_NOACCESS, SPR_NOACCESS,
5050 &spr_read_generic, &spr_write_generic,
5051 0x00000000);
5052 /* XXX : not implemented */
5053 spr_register(env, SPR_HID1, "HID1",
5054 SPR_NOACCESS, SPR_NOACCESS,
5055 &spr_read_generic, &spr_write_generic,
5056 0x00000000);
5057 /* Memory management */
5058 gen_low_BATs(env);
5059 gen_6xx_7xx_soft_tlb(env, 64, 2);
5060 init_excp_603(env);
5061 env->dcache_line_size = 32;
5062 env->icache_line_size = 32;
5063 /* Allocate hardware IRQ controller */
5064 ppc6xx_irq_init(env);
5065 }
5066
5067 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
5068 {
5069 DeviceClass *dc = DEVICE_CLASS(oc);
5070 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5071
5072 dc->desc = "PowerPC 603";
5073 pcc->init_proc = init_proc_603;
5074 pcc->check_pow = check_pow_hid0;
5075 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5076 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5077 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5078 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5079 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5080 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5081 PPC_SEGMENT | PPC_EXTERN;
5082 pcc->insns_flags2 = PPC_NONE;
5083 pcc->msr_mask = 0x000000000007FF73ULL;
5084 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5085 pcc->excp_model = POWERPC_EXCP_603;
5086 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5087 pcc->bfd_mach = bfd_mach_ppc_603;
5088 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5089 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5090 }
5091
5092 static void init_proc_603E (CPUPPCState *env)
5093 {
5094 gen_spr_ne_601(env);
5095 gen_spr_603(env);
5096 /* Time base */
5097 gen_tbl(env);
5098 /* hardware implementation registers */
5099 /* XXX : not implemented */
5100 spr_register(env, SPR_HID0, "HID0",
5101 SPR_NOACCESS, SPR_NOACCESS,
5102 &spr_read_generic, &spr_write_generic,
5103 0x00000000);
5104 /* XXX : not implemented */
5105 spr_register(env, SPR_HID1, "HID1",
5106 SPR_NOACCESS, SPR_NOACCESS,
5107 &spr_read_generic, &spr_write_generic,
5108 0x00000000);
5109 /* XXX : not implemented */
5110 spr_register(env, SPR_IABR, "IABR",
5111 SPR_NOACCESS, SPR_NOACCESS,
5112 &spr_read_generic, &spr_write_generic,
5113 0x00000000);
5114 /* Memory management */
5115 gen_low_BATs(env);
5116 gen_6xx_7xx_soft_tlb(env, 64, 2);
5117 init_excp_603(env);
5118 env->dcache_line_size = 32;
5119 env->icache_line_size = 32;
5120 /* Allocate hardware IRQ controller */
5121 ppc6xx_irq_init(env);
5122 }
5123
5124 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
5125 {
5126 DeviceClass *dc = DEVICE_CLASS(oc);
5127 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5128
5129 dc->desc = "PowerPC 603e";
5130 pcc->init_proc = init_proc_603E;
5131 pcc->check_pow = check_pow_hid0;
5132 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5133 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5134 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5135 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5136 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5137 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5138 PPC_SEGMENT | PPC_EXTERN;
5139 pcc->insns_flags2 = PPC_NONE;
5140 pcc->msr_mask = 0x000000000007FF73ULL;
5141 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5142 pcc->excp_model = POWERPC_EXCP_603E;
5143 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5144 pcc->bfd_mach = bfd_mach_ppc_ec603e;
5145 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5146 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5147 }
5148
5149 static void init_proc_604 (CPUPPCState *env)
5150 {
5151 gen_spr_ne_601(env);
5152 gen_spr_604(env);
5153 /* Time base */
5154 gen_tbl(env);
5155 /* Hardware implementation registers */
5156 /* XXX : not implemented */
5157 spr_register(env, SPR_HID0, "HID0",
5158 SPR_NOACCESS, SPR_NOACCESS,
5159 &spr_read_generic, &spr_write_generic,
5160 0x00000000);
5161 /* Memory management */
5162 gen_low_BATs(env);
5163 init_excp_604(env);
5164 env->dcache_line_size = 32;
5165 env->icache_line_size = 32;
5166 /* Allocate hardware IRQ controller */
5167 ppc6xx_irq_init(env);
5168 }
5169
5170 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5171 {
5172 DeviceClass *dc = DEVICE_CLASS(oc);
5173 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5174
5175 dc->desc = "PowerPC 604";
5176 pcc->init_proc = init_proc_604;
5177 pcc->check_pow = check_pow_nocheck;
5178 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5179 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5180 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5181 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5182 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5183 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5184 PPC_SEGMENT | PPC_EXTERN;
5185 pcc->insns_flags2 = PPC_NONE;
5186 pcc->msr_mask = 0x000000000005FF77ULL;
5187 pcc->mmu_model = POWERPC_MMU_32B;
5188 pcc->excp_model = POWERPC_EXCP_604;
5189 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5190 pcc->bfd_mach = bfd_mach_ppc_604;
5191 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5192 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5193 }
5194
5195 static void init_proc_604E (CPUPPCState *env)
5196 {
5197 gen_spr_ne_601(env);
5198 gen_spr_604(env);
5199 /* XXX : not implemented */
5200 spr_register(env, SPR_MMCR1, "MMCR1",
5201 SPR_NOACCESS, SPR_NOACCESS,
5202 &spr_read_generic, &spr_write_generic,
5203 0x00000000);
5204 /* XXX : not implemented */
5205 spr_register(env, SPR_PMC3, "PMC3",
5206 SPR_NOACCESS, SPR_NOACCESS,
5207 &spr_read_generic, &spr_write_generic,
5208 0x00000000);
5209 /* XXX : not implemented */
5210 spr_register(env, SPR_PMC4, "PMC4",
5211 SPR_NOACCESS, SPR_NOACCESS,
5212 &spr_read_generic, &spr_write_generic,
5213 0x00000000);
5214 /* Time base */
5215 gen_tbl(env);
5216 /* Hardware implementation registers */
5217 /* XXX : not implemented */
5218 spr_register(env, SPR_HID0, "HID0",
5219 SPR_NOACCESS, SPR_NOACCESS,
5220 &spr_read_generic, &spr_write_generic,
5221 0x00000000);
5222 /* XXX : not implemented */
5223 spr_register(env, SPR_HID1, "HID1",
5224 SPR_NOACCESS, SPR_NOACCESS,
5225 &spr_read_generic, &spr_write_generic,
5226 0x00000000);
5227 /* Memory management */
5228 gen_low_BATs(env);
5229 init_excp_604(env);
5230 env->dcache_line_size = 32;
5231 env->icache_line_size = 32;
5232 /* Allocate hardware IRQ controller */
5233 ppc6xx_irq_init(env);
5234 }
5235
5236 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5237 {
5238 DeviceClass *dc = DEVICE_CLASS(oc);
5239 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5240
5241 dc->desc = "PowerPC 604E";
5242 pcc->init_proc = init_proc_604E;
5243 pcc->check_pow = check_pow_nocheck;
5244 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5245 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5246 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5247 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5248 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5249 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5250 PPC_SEGMENT | PPC_EXTERN;
5251 pcc->insns_flags2 = PPC_NONE;
5252 pcc->msr_mask = 0x000000000005FF77ULL;
5253 pcc->mmu_model = POWERPC_MMU_32B;
5254 pcc->excp_model = POWERPC_EXCP_604;
5255 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5256 pcc->bfd_mach = bfd_mach_ppc_604;
5257 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5258 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5259 }
5260
5261 static void init_proc_740 (CPUPPCState *env)
5262 {
5263 gen_spr_ne_601(env);
5264 gen_spr_7xx(env);
5265 /* Time base */
5266 gen_tbl(env);
5267 /* Thermal management */
5268 gen_spr_thrm(env);
5269 /* Hardware implementation registers */
5270 /* XXX : not implemented */
5271 spr_register(env, SPR_HID0, "HID0",
5272 SPR_NOACCESS, SPR_NOACCESS,
5273 &spr_read_generic, &spr_write_generic,
5274 0x00000000);
5275 /* XXX : not implemented */
5276 spr_register(env, SPR_HID1, "HID1",
5277 SPR_NOACCESS, SPR_NOACCESS,
5278 &spr_read_generic, &spr_write_generic,
5279 0x00000000);
5280 /* Memory management */
5281 gen_low_BATs(env);
5282 init_excp_7x0(env);
5283 env->dcache_line_size = 32;
5284 env->icache_line_size = 32;
5285 /* Allocate hardware IRQ controller */
5286 ppc6xx_irq_init(env);
5287 }
5288
5289 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5290 {
5291 DeviceClass *dc = DEVICE_CLASS(oc);
5292 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5293
5294 dc->desc = "PowerPC 740";
5295 pcc->init_proc = init_proc_740;
5296 pcc->check_pow = check_pow_hid0;
5297 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5298 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5299 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5300 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5301 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5302 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5303 PPC_SEGMENT | PPC_EXTERN;
5304 pcc->insns_flags2 = PPC_NONE;
5305 pcc->msr_mask = 0x000000000005FF77ULL;
5306 pcc->mmu_model = POWERPC_MMU_32B;
5307 pcc->excp_model = POWERPC_EXCP_7x0;
5308 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5309 pcc->bfd_mach = bfd_mach_ppc_750;
5310 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5311 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5312 }
5313
5314 static void init_proc_750 (CPUPPCState *env)
5315 {
5316 gen_spr_ne_601(env);
5317 gen_spr_7xx(env);
5318 /* XXX : not implemented */
5319 spr_register(env, SPR_L2CR, "L2CR",
5320 SPR_NOACCESS, SPR_NOACCESS,
5321 &spr_read_generic, &spr_write_generic,
5322 0x00000000);
5323 /* Time base */
5324 gen_tbl(env);
5325 /* Thermal management */
5326 gen_spr_thrm(env);
5327 /* Hardware implementation registers */
5328 /* XXX : not implemented */
5329 spr_register(env, SPR_HID0, "HID0",
5330 SPR_NOACCESS, SPR_NOACCESS,
5331 &spr_read_generic, &spr_write_generic,
5332 0x00000000);
5333 /* XXX : not implemented */
5334 spr_register(env, SPR_HID1, "HID1",
5335 SPR_NOACCESS, SPR_NOACCESS,
5336 &spr_read_generic, &spr_write_generic,
5337 0x00000000);
5338 /* Memory management */
5339 gen_low_BATs(env);
5340 /* XXX: high BATs are also present but are known to be bugged on
5341 * die version 1.x
5342 */
5343 init_excp_7x0(env);
5344 env->dcache_line_size = 32;
5345 env->icache_line_size = 32;
5346 /* Allocate hardware IRQ controller */
5347 ppc6xx_irq_init(env);
5348 }
5349
5350 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5351 {
5352 DeviceClass *dc = DEVICE_CLASS(oc);
5353 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5354
5355 dc->desc = "PowerPC 750";
5356 pcc->init_proc = init_proc_750;
5357 pcc->check_pow = check_pow_hid0;
5358 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5359 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5360 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5361 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5362 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5363 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5364 PPC_SEGMENT | PPC_EXTERN;
5365 pcc->insns_flags2 = PPC_NONE;
5366 pcc->msr_mask = 0x000000000005FF77ULL;
5367 pcc->mmu_model = POWERPC_MMU_32B;
5368 pcc->excp_model = POWERPC_EXCP_7x0;
5369 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5370 pcc->bfd_mach = bfd_mach_ppc_750;
5371 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5372 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5373 }
5374
5375 static void init_proc_750cl (CPUPPCState *env)
5376 {
5377 gen_spr_ne_601(env);
5378 gen_spr_7xx(env);
5379 /* XXX : not implemented */
5380 spr_register(env, SPR_L2CR, "L2CR",
5381 SPR_NOACCESS, SPR_NOACCESS,
5382 &spr_read_generic, &spr_write_generic,
5383 0x00000000);
5384 /* Time base */
5385 gen_tbl(env);
5386 /* Thermal management */
5387 /* Those registers are fake on 750CL */
5388 spr_register(env, SPR_THRM1, "THRM1",
5389 SPR_NOACCESS, SPR_NOACCESS,
5390 &spr_read_generic, &spr_write_generic,
5391 0x00000000);
5392 spr_register(env, SPR_THRM2, "THRM2",
5393 SPR_NOACCESS, SPR_NOACCESS,
5394 &spr_read_generic, &spr_write_generic,
5395 0x00000000);
5396 spr_register(env, SPR_THRM3, "THRM3",
5397 SPR_NOACCESS, SPR_NOACCESS,
5398 &spr_read_generic, &spr_write_generic,
5399 0x00000000);
5400 /* XXX: not implemented */
5401 spr_register(env, SPR_750_TDCL, "TDCL",
5402 SPR_NOACCESS, SPR_NOACCESS,
5403 &spr_read_generic, &spr_write_generic,
5404 0x00000000);
5405 spr_register(env, SPR_750_TDCH, "TDCH",
5406 SPR_NOACCESS, SPR_NOACCESS,
5407 &spr_read_generic, &spr_write_generic,
5408 0x00000000);
5409 /* DMA */
5410 /* XXX : not implemented */
5411 spr_register(env, SPR_750_WPAR, "WPAR",
5412 SPR_NOACCESS, SPR_NOACCESS,
5413 &spr_read_generic, &spr_write_generic,
5414 0x00000000);
5415 spr_register(env, SPR_750_DMAL, "DMAL",
5416 SPR_NOACCESS, SPR_NOACCESS,
5417 &spr_read_generic, &spr_write_generic,
5418 0x00000000);
5419 spr_register(env, SPR_750_DMAU, "DMAU",
5420 SPR_NOACCESS, SPR_NOACCESS,
5421 &spr_read_generic, &spr_write_generic,
5422 0x00000000);
5423 /* Hardware implementation registers */
5424 /* XXX : not implemented */
5425 spr_register(env, SPR_HID0, "HID0",
5426 SPR_NOACCESS, SPR_NOACCESS,
5427 &spr_read_generic, &spr_write_generic,
5428 0x00000000);
5429 /* XXX : not implemented */
5430 spr_register(env, SPR_HID1, "HID1",
5431 SPR_NOACCESS, SPR_NOACCESS,
5432 &spr_read_generic, &spr_write_generic,
5433 0x00000000);
5434 /* XXX : not implemented */
5435 spr_register(env, SPR_750CL_HID2, "HID2",
5436 SPR_NOACCESS, SPR_NOACCESS,
5437 &spr_read_generic, &spr_write_generic,
5438 0x00000000);
5439 /* XXX : not implemented */
5440 spr_register(env, SPR_750CL_HID4, "HID4",
5441 SPR_NOACCESS, SPR_NOACCESS,
5442 &spr_read_generic, &spr_write_generic,
5443 0x00000000);
5444 /* Quantization registers */
5445 /* XXX : not implemented */
5446 spr_register(env, SPR_750_GQR0, "GQR0",
5447 SPR_NOACCESS, SPR_NOACCESS,
5448 &spr_read_generic, &spr_write_generic,
5449 0x00000000);
5450 /* XXX : not implemented */
5451 spr_register(env, SPR_750_GQR1, "GQR1",
5452 SPR_NOACCESS, SPR_NOACCESS,
5453 &spr_read_generic, &spr_write_generic,
5454 0x00000000);
5455 /* XXX : not implemented */
5456 spr_register(env, SPR_750_GQR2, "GQR2",
5457 SPR_NOACCESS, SPR_NOACCESS,
5458 &spr_read_generic, &spr_write_generic,
5459 0x00000000);
5460 /* XXX : not implemented */
5461 spr_register(env, SPR_750_GQR3, "GQR3",
5462 SPR_NOACCESS, SPR_NOACCESS,
5463 &spr_read_generic, &spr_write_generic,
5464 0x00000000);
5465 /* XXX : not implemented */
5466 spr_register(env, SPR_750_GQR4, "GQR4",
5467 SPR_NOACCESS, SPR_NOACCESS,
5468 &spr_read_generic, &spr_write_generic,
5469 0x00000000);
5470 /* XXX : not implemented */
5471 spr_register(env, SPR_750_GQR5, "GQR5",
5472 SPR_NOACCESS, SPR_NOACCESS,
5473 &spr_read_generic, &spr_write_generic,
5474 0x00000000);
5475 /* XXX : not implemented */
5476 spr_register(env, SPR_750_GQR6, "GQR6",
5477 SPR_NOACCESS, SPR_NOACCESS,
5478 &spr_read_generic, &spr_write_generic,
5479 0x00000000);
5480 /* XXX : not implemented */
5481 spr_register(env, SPR_750_GQR7, "GQR7",
5482 SPR_NOACCESS, SPR_NOACCESS,
5483 &spr_read_generic, &spr_write_generic,
5484 0x00000000);
5485 /* Memory management */
5486 gen_low_BATs(env);
5487 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5488 gen_high_BATs(env);
5489 init_excp_750cl(env);
5490 env->dcache_line_size = 32;
5491 env->icache_line_size = 32;
5492 /* Allocate hardware IRQ controller */
5493 ppc6xx_irq_init(env);
5494 }
5495
5496 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5497 {
5498 DeviceClass *dc = DEVICE_CLASS(oc);
5499 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5500
5501 dc->desc = "PowerPC 750 CL";
5502 pcc->init_proc = init_proc_750cl;
5503 pcc->check_pow = check_pow_hid0;
5504 /* XXX: not implemented:
5505 * cache lock instructions:
5506 * dcbz_l
5507 * floating point paired instructions
5508 * psq_lux
5509 * psq_lx
5510 * psq_stux
5511 * psq_stx
5512 * ps_abs
5513 * ps_add
5514 * ps_cmpo0
5515 * ps_cmpo1
5516 * ps_cmpu0
5517 * ps_cmpu1
5518 * ps_div
5519 * ps_madd
5520 * ps_madds0
5521 * ps_madds1
5522 * ps_merge00
5523 * ps_merge01
5524 * ps_merge10
5525 * ps_merge11
5526 * ps_mr
5527 * ps_msub
5528 * ps_mul
5529 * ps_muls0
5530 * ps_muls1
5531 * ps_nabs
5532 * ps_neg
5533 * ps_nmadd
5534 * ps_nmsub
5535 * ps_res
5536 * ps_rsqrte
5537 * ps_sel
5538 * ps_sub
5539 * ps_sum0
5540 * ps_sum1
5541 */
5542 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5543 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5544 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5545 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5546 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5547 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5548 PPC_SEGMENT | PPC_EXTERN;
5549 pcc->insns_flags2 = PPC_NONE;
5550 pcc->msr_mask = 0x000000000005FF77ULL;
5551 pcc->mmu_model = POWERPC_MMU_32B;
5552 pcc->excp_model = POWERPC_EXCP_7x0;
5553 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5554 pcc->bfd_mach = bfd_mach_ppc_750;
5555 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5556 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5557 }
5558
5559 static void init_proc_750cx (CPUPPCState *env)
5560 {
5561 gen_spr_ne_601(env);
5562 gen_spr_7xx(env);
5563 /* XXX : not implemented */
5564 spr_register(env, SPR_L2CR, "L2CR",
5565 SPR_NOACCESS, SPR_NOACCESS,
5566 &spr_read_generic, &spr_write_generic,
5567 0x00000000);
5568 /* Time base */
5569 gen_tbl(env);
5570 /* Thermal management */
5571 gen_spr_thrm(env);
5572 /* This register is not implemented but is present for compatibility */
5573 spr_register(env, SPR_SDA, "SDA",
5574 SPR_NOACCESS, SPR_NOACCESS,
5575 &spr_read_generic, &spr_write_generic,
5576 0x00000000);
5577 /* Hardware implementation registers */
5578 /* XXX : not implemented */
5579 spr_register(env, SPR_HID0, "HID0",
5580 SPR_NOACCESS, SPR_NOACCESS,
5581 &spr_read_generic, &spr_write_generic,
5582 0x00000000);
5583 /* XXX : not implemented */
5584 spr_register(env, SPR_HID1, "HID1",
5585 SPR_NOACCESS, SPR_NOACCESS,
5586 &spr_read_generic, &spr_write_generic,
5587 0x00000000);
5588 /* Memory management */
5589 gen_low_BATs(env);
5590 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5591 gen_high_BATs(env);
5592 init_excp_750cx(env);
5593 env->dcache_line_size = 32;
5594 env->icache_line_size = 32;
5595 /* Allocate hardware IRQ controller */
5596 ppc6xx_irq_init(env);
5597 }
5598
5599 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
5600 {
5601 DeviceClass *dc = DEVICE_CLASS(oc);
5602 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5603
5604 dc->desc = "PowerPC 750CX";
5605 pcc->init_proc = init_proc_750cx;
5606 pcc->check_pow = check_pow_hid0;
5607 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5608 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5609 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5610 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5611 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5612 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5613 PPC_SEGMENT | PPC_EXTERN;
5614 pcc->insns_flags2 = PPC_NONE;
5615 pcc->msr_mask = 0x000000000005FF77ULL;
5616 pcc->mmu_model = POWERPC_MMU_32B;
5617 pcc->excp_model = POWERPC_EXCP_7x0;
5618 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5619 pcc->bfd_mach = bfd_mach_ppc_750;
5620 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5621 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5622 }
5623
5624 static void init_proc_750fx (CPUPPCState *env)
5625 {
5626 gen_spr_ne_601(env);
5627 gen_spr_7xx(env);
5628 /* XXX : not implemented */
5629 spr_register(env, SPR_L2CR, "L2CR",
5630 SPR_NOACCESS, SPR_NOACCESS,
5631 &spr_read_generic, &spr_write_generic,
5632 0x00000000);
5633 /* Time base */
5634 gen_tbl(env);
5635 /* Thermal management */
5636 gen_spr_thrm(env);
5637 /* XXX : not implemented */
5638 spr_register(env, SPR_750_THRM4, "THRM4",
5639 SPR_NOACCESS, SPR_NOACCESS,
5640 &spr_read_generic, &spr_write_generic,
5641 0x00000000);
5642 /* Hardware implementation registers */
5643 /* XXX : not implemented */
5644 spr_register(env, SPR_HID0, "HID0",
5645 SPR_NOACCESS, SPR_NOACCESS,
5646 &spr_read_generic, &spr_write_generic,
5647 0x00000000);
5648 /* XXX : not implemented */
5649 spr_register(env, SPR_HID1, "HID1",
5650 SPR_NOACCESS, SPR_NOACCESS,
5651 &spr_read_generic, &spr_write_generic,
5652 0x00000000);
5653 /* XXX : not implemented */
5654 spr_register(env, SPR_750FX_HID2, "HID2",
5655 SPR_NOACCESS, SPR_NOACCESS,
5656 &spr_read_generic, &spr_write_generic,
5657 0x00000000);
5658 /* Memory management */
5659 gen_low_BATs(env);
5660 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5661 gen_high_BATs(env);
5662 init_excp_7x0(env);
5663 env->dcache_line_size = 32;
5664 env->icache_line_size = 32;
5665 /* Allocate hardware IRQ controller */
5666 ppc6xx_irq_init(env);
5667 }
5668
5669 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
5670 {
5671 DeviceClass *dc = DEVICE_CLASS(oc);
5672 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5673
5674 dc->desc = "PowerPC 750FX";
5675 pcc->init_proc = init_proc_750fx;
5676 pcc->check_pow = check_pow_hid0;
5677 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5678 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5679 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5680 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5681 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5682 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5683 PPC_SEGMENT | PPC_EXTERN;
5684 pcc->insns_flags2 = PPC_NONE;
5685 pcc->msr_mask = 0x000000000005FF77ULL;
5686 pcc->mmu_model = POWERPC_MMU_32B;
5687 pcc->excp_model = POWERPC_EXCP_7x0;
5688 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5689 pcc->bfd_mach = bfd_mach_ppc_750;
5690 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5691 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5692 }
5693
5694 static void init_proc_750gx (CPUPPCState *env)
5695 {
5696 gen_spr_ne_601(env);
5697 gen_spr_7xx(env);
5698 /* XXX : not implemented (XXX: different from 750fx) */
5699 spr_register(env, SPR_L2CR, "L2CR",
5700 SPR_NOACCESS, SPR_NOACCESS,
5701 &spr_read_generic, &spr_write_generic,
5702 0x00000000);
5703 /* Time base */
5704 gen_tbl(env);
5705 /* Thermal management */
5706 gen_spr_thrm(env);
5707 /* XXX : not implemented */
5708 spr_register(env, SPR_750_THRM4, "THRM4",
5709 SPR_NOACCESS, SPR_NOACCESS,
5710 &spr_read_generic, &spr_write_generic,
5711 0x00000000);
5712 /* Hardware implementation registers */
5713 /* XXX : not implemented (XXX: different from 750fx) */
5714 spr_register(env, SPR_HID0, "HID0",
5715 SPR_NOACCESS, SPR_NOACCESS,
5716 &spr_read_generic, &spr_write_generic,
5717 0x00000000);
5718 /* XXX : not implemented */
5719 spr_register(env, SPR_HID1, "HID1",
5720 SPR_NOACCESS, SPR_NOACCESS,
5721 &spr_read_generic, &spr_write_generic,
5722 0x00000000);
5723 /* XXX : not implemented (XXX: different from 750fx) */
5724 spr_register(env, SPR_750FX_HID2, "HID2",
5725 SPR_NOACCESS, SPR_NOACCESS,
5726 &spr_read_generic, &spr_write_generic,
5727 0x00000000);
5728 /* Memory management */
5729 gen_low_BATs(env);
5730 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5731 gen_high_BATs(env);
5732 init_excp_7x0(env);
5733 env->dcache_line_size = 32;
5734 env->icache_line_size = 32;
5735 /* Allocate hardware IRQ controller */
5736 ppc6xx_irq_init(env);
5737 }
5738
5739 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
5740 {
5741 DeviceClass *dc = DEVICE_CLASS(oc);
5742 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5743
5744 dc->desc = "PowerPC 750GX";
5745 pcc->init_proc = init_proc_750gx;
5746 pcc->check_pow = check_pow_hid0;
5747 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5748 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5749 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5750 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5751 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5752 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5753 PPC_SEGMENT | PPC_EXTERN;
5754 pcc->insns_flags2 = PPC_NONE;
5755 pcc->msr_mask = 0x000000000005FF77ULL;
5756 pcc->mmu_model = POWERPC_MMU_32B;
5757 pcc->excp_model = POWERPC_EXCP_7x0;
5758 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5759 pcc->bfd_mach = bfd_mach_ppc_750;
5760 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5761 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5762 }
5763
5764 static void init_proc_745 (CPUPPCState *env)
5765 {
5766 gen_spr_ne_601(env);
5767 gen_spr_7xx(env);
5768 gen_spr_G2_755(env);
5769 /* Time base */
5770 gen_tbl(env);
5771 /* Thermal management */
5772 gen_spr_thrm(env);
5773 /* Hardware implementation registers */
5774 /* XXX : not implemented */
5775 spr_register(env, SPR_HID0, "HID0",
5776 SPR_NOACCESS, SPR_NOACCESS,
5777 &spr_read_generic, &spr_write_generic,
5778 0x00000000);
5779 /* XXX : not implemented */
5780 spr_register(env, SPR_HID1, "HID1",
5781 SPR_NOACCESS, SPR_NOACCESS,
5782 &spr_read_generic, &spr_write_generic,
5783 0x00000000);
5784 /* XXX : not implemented */
5785 spr_register(env, SPR_HID2, "HID2",
5786 SPR_NOACCESS, SPR_NOACCESS,
5787 &spr_read_generic, &spr_write_generic,
5788 0x00000000);
5789 /* Memory management */
5790 gen_low_BATs(env);
5791 gen_high_BATs(env);
5792 gen_6xx_7xx_soft_tlb(env, 64, 2);
5793 init_excp_7x5(env);
5794 env->dcache_line_size = 32;
5795 env->icache_line_size = 32;
5796 /* Allocate hardware IRQ controller */
5797 ppc6xx_irq_init(env);
5798 }
5799
5800 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
5801 {
5802 DeviceClass *dc = DEVICE_CLASS(oc);
5803 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5804
5805 dc->desc = "PowerPC 745";
5806 pcc->init_proc = init_proc_745;
5807 pcc->check_pow = check_pow_hid0;
5808 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5809 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5810 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5811 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5812 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5813 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5814 PPC_SEGMENT | PPC_EXTERN;
5815 pcc->insns_flags2 = PPC_NONE;
5816 pcc->msr_mask = 0x000000000005FF77ULL;
5817 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5818 pcc->excp_model = POWERPC_EXCP_7x5;
5819 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5820 pcc->bfd_mach = bfd_mach_ppc_750;
5821 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5822 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5823 }
5824
5825 static void init_proc_755 (CPUPPCState *env)
5826 {
5827 gen_spr_ne_601(env);
5828 gen_spr_7xx(env);
5829 gen_spr_G2_755(env);
5830 /* Time base */
5831 gen_tbl(env);
5832 /* L2 cache control */
5833 /* XXX : not implemented */
5834 spr_register(env, SPR_L2CR, "L2CR",
5835 SPR_NOACCESS, SPR_NOACCESS,
5836 &spr_read_generic, &spr_write_generic,
5837 0x00000000);
5838 /* XXX : not implemented */
5839 spr_register(env, SPR_L2PMCR, "L2PMCR",
5840 SPR_NOACCESS, SPR_NOACCESS,
5841 &spr_read_generic, &spr_write_generic,
5842 0x00000000);
5843 /* Thermal management */
5844 gen_spr_thrm(env);
5845 /* Hardware implementation registers */
5846 /* XXX : not implemented */
5847 spr_register(env, SPR_HID0, "HID0",
5848 SPR_NOACCESS, SPR_NOACCESS,
5849 &spr_read_generic, &spr_write_generic,
5850 0x00000000);
5851 /* XXX : not implemented */
5852 spr_register(env, SPR_HID1, "HID1",
5853 SPR_NOACCESS, SPR_NOACCESS,
5854 &spr_read_generic, &spr_write_generic,
5855 0x00000000);
5856 /* XXX : not implemented */
5857 spr_register(env, SPR_HID2, "HID2",
5858 SPR_NOACCESS, SPR_NOACCESS,
5859 &spr_read_generic, &spr_write_generic,
5860 0x00000000);
5861 /* Memory management */
5862 gen_low_BATs(env);
5863 gen_high_BATs(env);
5864 gen_6xx_7xx_soft_tlb(env, 64, 2);
5865 init_excp_7x5(env);
5866 env->dcache_line_size = 32;
5867 env->icache_line_size = 32;
5868 /* Allocate hardware IRQ controller */
5869 ppc6xx_irq_init(env);
5870 }
5871
5872 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
5873 {
5874 DeviceClass *dc = DEVICE_CLASS(oc);
5875 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5876
5877 dc->desc = "PowerPC 755";
5878 pcc->init_proc = init_proc_755;
5879 pcc->check_pow = check_pow_hid0;
5880 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5881 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5882 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5883 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5884 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5885 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5886 PPC_SEGMENT | PPC_EXTERN;
5887 pcc->insns_flags2 = PPC_NONE;
5888 pcc->msr_mask = 0x000000000005FF77ULL;
5889 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5890 pcc->excp_model = POWERPC_EXCP_7x5;
5891 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5892 pcc->bfd_mach = bfd_mach_ppc_750;
5893 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5894 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5895 }
5896
5897 static void init_proc_7400 (CPUPPCState *env)
5898 {
5899 gen_spr_ne_601(env);
5900 gen_spr_7xx(env);
5901 /* Time base */
5902 gen_tbl(env);
5903 /* 74xx specific SPR */
5904 gen_spr_74xx(env);
5905 /* XXX : not implemented */
5906 spr_register(env, SPR_UBAMR, "UBAMR",
5907 &spr_read_ureg, SPR_NOACCESS,
5908 &spr_read_ureg, SPR_NOACCESS,
5909 0x00000000);
5910 /* XXX: this seems not implemented on all revisions. */
5911 /* XXX : not implemented */
5912 spr_register(env, SPR_MSSCR1, "MSSCR1",
5913 SPR_NOACCESS, SPR_NOACCESS,
5914 &spr_read_generic, &spr_write_generic,
5915 0x00000000);
5916 /* Thermal management */
5917 gen_spr_thrm(env);
5918 /* Memory management */
5919 gen_low_BATs(env);
5920 init_excp_7400(env);
5921 env->dcache_line_size = 32;
5922 env->icache_line_size = 32;
5923 /* Allocate hardware IRQ controller */
5924 ppc6xx_irq_init(env);
5925 }
5926
5927 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
5928 {
5929 DeviceClass *dc = DEVICE_CLASS(oc);
5930 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5931
5932 dc->desc = "PowerPC 7400 (aka G4)";
5933 pcc->init_proc = init_proc_7400;
5934 pcc->check_pow = check_pow_hid0;
5935 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5936 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5937 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5938 PPC_FLOAT_STFIWX |
5939 PPC_CACHE | PPC_CACHE_ICBI |
5940 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5941 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5942 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5943 PPC_MEM_TLBIA |
5944 PPC_SEGMENT | PPC_EXTERN |
5945 PPC_ALTIVEC;
5946 pcc->insns_flags2 = PPC_NONE;
5947 pcc->msr_mask = 0x000000000205FF77ULL;
5948 pcc->mmu_model = POWERPC_MMU_32B;
5949 pcc->excp_model = POWERPC_EXCP_74xx;
5950 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5951 pcc->bfd_mach = bfd_mach_ppc_7400;
5952 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5953 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5954 POWERPC_FLAG_BUS_CLK;
5955 }
5956
5957 static void init_proc_7410 (CPUPPCState *env)
5958 {
5959 gen_spr_ne_601(env);
5960 gen_spr_7xx(env);
5961 /* Time base */
5962 gen_tbl(env);
5963 /* 74xx specific SPR */
5964 gen_spr_74xx(env);
5965 /* XXX : not implemented */
5966 spr_register(env, SPR_UBAMR, "UBAMR",
5967 &spr_read_ureg, SPR_NOACCESS,
5968 &spr_read_ureg, SPR_NOACCESS,
5969 0x00000000);
5970 /* Thermal management */
5971 gen_spr_thrm(env);
5972 /* L2PMCR */
5973 /* XXX : not implemented */
5974 spr_register(env, SPR_L2PMCR, "L2PMCR",
5975 SPR_NOACCESS, SPR_NOACCESS,
5976 &spr_read_generic, &spr_write_generic,
5977 0x00000000);
5978 /* LDSTDB */
5979 /* XXX : not implemented */
5980 spr_register(env, SPR_LDSTDB, "LDSTDB",
5981 SPR_NOACCESS, SPR_NOACCESS,
5982 &spr_read_generic, &spr_write_generic,
5983 0x00000000);
5984 /* Memory management */
5985 gen_low_BATs(env);
5986 init_excp_7400(env);
5987 env->dcache_line_size = 32;
5988 env->icache_line_size = 32;
5989 /* Allocate hardware IRQ controller */
5990 ppc6xx_irq_init(env);
5991 }
5992
5993 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
5994 {
5995 DeviceClass *dc = DEVICE_CLASS(oc);
5996 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5997
5998 dc->desc = "PowerPC 7410 (aka G4)";
5999 pcc->init_proc = init_proc_7410;
6000 pcc->check_pow = check_pow_hid0;
6001 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6002 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6003 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6004 PPC_FLOAT_STFIWX |
6005 PPC_CACHE | PPC_CACHE_ICBI |
6006 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6007 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6008 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6009 PPC_MEM_TLBIA |
6010 PPC_SEGMENT | PPC_EXTERN |
6011 PPC_ALTIVEC;
6012 pcc->insns_flags2 = PPC_NONE;
6013 pcc->msr_mask = 0x000000000205FF77ULL;
6014 pcc->mmu_model = POWERPC_MMU_32B;
6015 pcc->excp_model = POWERPC_EXCP_74xx;
6016 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6017 pcc->bfd_mach = bfd_mach_ppc_7400;
6018 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6019 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6020 POWERPC_FLAG_BUS_CLK;
6021 }
6022
6023 static void init_proc_7440 (CPUPPCState *env)
6024 {
6025 gen_spr_ne_601(env);
6026 gen_spr_7xx(env);
6027 /* Time base */
6028 gen_tbl(env);
6029 /* 74xx specific SPR */
6030 gen_spr_74xx(env);
6031 /* XXX : not implemented */
6032 spr_register(env, SPR_UBAMR, "UBAMR",
6033 &spr_read_ureg, SPR_NOACCESS,
6034 &spr_read_ureg, SPR_NOACCESS,
6035 0x00000000);
6036 /* LDSTCR */
6037 /* XXX : not implemented */
6038 spr_register(env, SPR_LDSTCR, "LDSTCR",
6039 SPR_NOACCESS, SPR_NOACCESS,
6040 &spr_read_generic, &spr_write_generic,
6041 0x00000000);
6042 /* ICTRL */
6043 /* XXX : not implemented */
6044 spr_register(env, SPR_ICTRL, "ICTRL",
6045 SPR_NOACCESS, SPR_NOACCESS,
6046 &spr_read_generic, &spr_write_generic,
6047 0x00000000);
6048 /* MSSSR0 */
6049 /* XXX : not implemented */
6050 spr_register(env, SPR_MSSSR0, "MSSSR0",
6051 SPR_NOACCESS, SPR_NOACCESS,
6052 &spr_read_generic, &spr_write_generic,
6053 0x00000000);
6054 /* PMC */
6055 /* XXX : not implemented */
6056 spr_register(env, SPR_PMC5, "PMC5",
6057 SPR_NOACCESS, SPR_NOACCESS,
6058 &spr_read_generic, &spr_write_generic,
6059 0x00000000);
6060 /* XXX : not implemented */
6061 spr_register(env, SPR_UPMC5, "UPMC5",
6062 &spr_read_ureg, SPR_NOACCESS,
6063 &spr_read_ureg, SPR_NOACCESS,
6064 0x00000000);
6065 /* XXX : not implemented */
6066 spr_register(env, SPR_PMC6, "PMC6",
6067 SPR_NOACCESS, SPR_NOACCESS,
6068 &spr_read_generic, &spr_write_generic,
6069 0x00000000);
6070 /* XXX : not implemented */
6071 spr_register(env, SPR_UPMC6, "UPMC6",
6072 &spr_read_ureg, SPR_NOACCESS,
6073 &spr_read_ureg, SPR_NOACCESS,
6074 0x00000000);
6075 /* Memory management */
6076 gen_low_BATs(env);
6077 gen_74xx_soft_tlb(env, 128, 2);
6078 init_excp_7450(env);
6079 env->dcache_line_size = 32;
6080 env->icache_line_size = 32;
6081 /* Allocate hardware IRQ controller */
6082 ppc6xx_irq_init(env);
6083 }
6084
6085 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
6086 {
6087 DeviceClass *dc = DEVICE_CLASS(oc);
6088 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6089
6090 dc->desc = "PowerPC 7440 (aka G4)";
6091 pcc->init_proc = init_proc_7440;
6092 pcc->check_pow = check_pow_hid0_74xx;
6093 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6094 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6095 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6096 PPC_FLOAT_STFIWX |
6097 PPC_CACHE | PPC_CACHE_ICBI |
6098 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6099 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6100 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6101 PPC_MEM_TLBIA | PPC_74xx_TLB |
6102 PPC_SEGMENT | PPC_EXTERN |
6103 PPC_ALTIVEC;
6104 pcc->insns_flags2 = PPC_NONE;
6105 pcc->msr_mask = 0x000000000205FF77ULL;
6106 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6107 pcc->excp_model = POWERPC_EXCP_74xx;
6108 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6109 pcc->bfd_mach = bfd_mach_ppc_7400;
6110 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6111 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6112 POWERPC_FLAG_BUS_CLK;
6113 }
6114
6115 static void init_proc_7450 (CPUPPCState *env)
6116 {
6117 gen_spr_ne_601(env);
6118 gen_spr_7xx(env);
6119 /* Time base */
6120 gen_tbl(env);
6121 /* 74xx specific SPR */
6122 gen_spr_74xx(env);
6123 /* Level 3 cache control */
6124 gen_l3_ctrl(env);
6125 /* L3ITCR1 */
6126 /* XXX : not implemented */
6127 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6128 SPR_NOACCESS, SPR_NOACCESS,
6129 &spr_read_generic, &spr_write_generic,
6130 0x00000000);
6131 /* L3ITCR2 */
6132 /* XXX : not implemented */
6133 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6134 SPR_NOACCESS, SPR_NOACCESS,
6135 &spr_read_generic, &spr_write_generic,
6136 0x00000000);
6137 /* L3ITCR3 */
6138 /* XXX : not implemented */
6139 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6140 SPR_NOACCESS, SPR_NOACCESS,
6141 &spr_read_generic, &spr_write_generic,
6142 0x00000000);
6143 /* L3OHCR */
6144 /* XXX : not implemented */
6145 spr_register(env, SPR_L3OHCR, "L3OHCR",
6146 SPR_NOACCESS, SPR_NOACCESS,
6147 &spr_read_generic, &spr_write_generic,
6148 0x00000000);
6149 /* XXX : not implemented */
6150 spr_register(env, SPR_UBAMR, "UBAMR",
6151 &spr_read_ureg, SPR_NOACCESS,
6152 &spr_read_ureg, SPR_NOACCESS,
6153 0x00000000);
6154 /* LDSTCR */
6155 /* XXX : not implemented */
6156 spr_register(env, SPR_LDSTCR, "LDSTCR",
6157 SPR_NOACCESS, SPR_NOACCESS,
6158 &spr_read_generic, &spr_write_generic,
6159 0x00000000);
6160 /* ICTRL */
6161 /* XXX : not implemented */
6162 spr_register(env, SPR_ICTRL, "ICTRL",
6163 SPR_NOACCESS, SPR_NOACCESS,
6164 &spr_read_generic, &spr_write_generic,
6165 0x00000000);
6166 /* MSSSR0 */
6167 /* XXX : not implemented */
6168 spr_register(env, SPR_MSSSR0, "MSSSR0",
6169 SPR_NOACCESS, SPR_NOACCESS,
6170 &spr_read_generic, &spr_write_generic,
6171 0x00000000);
6172 /* PMC */
6173 /* XXX : not implemented */
6174 spr_register(env, SPR_PMC5, "PMC5",
6175 SPR_NOACCESS, SPR_NOACCESS,
6176 &spr_read_generic, &spr_write_generic,
6177 0x00000000);
6178 /* XXX : not implemented */
6179 spr_register(env, SPR_UPMC5, "UPMC5",
6180 &spr_read_ureg, SPR_NOACCESS,
6181 &spr_read_ureg, SPR_NOACCESS,
6182 0x00000000);
6183 /* XXX : not implemented */
6184 spr_register(env, SPR_PMC6, "PMC6",
6185 SPR_NOACCESS, SPR_NOACCESS,
6186 &spr_read_generic, &spr_write_generic,
6187 0x00000000);
6188 /* XXX : not implemented */
6189 spr_register(env, SPR_UPMC6, "UPMC6",
6190 &spr_read_ureg, SPR_NOACCESS,
6191 &spr_read_ureg, SPR_NOACCESS,
6192 0x00000000);
6193 /* Memory management */
6194 gen_low_BATs(env);
6195 gen_74xx_soft_tlb(env, 128, 2);
6196 init_excp_7450(env);
6197 env->dcache_line_size = 32;
6198 env->icache_line_size = 32;
6199 /* Allocate hardware IRQ controller */
6200 ppc6xx_irq_init(env);
6201 }
6202
6203 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6204 {
6205 DeviceClass *dc = DEVICE_CLASS(oc);
6206 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6207
6208 dc->desc = "PowerPC 7450 (aka G4)";
6209 pcc->init_proc = init_proc_7450;
6210 pcc->check_pow = check_pow_hid0_74xx;
6211 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6212 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6213 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6214 PPC_FLOAT_STFIWX |
6215 PPC_CACHE | PPC_CACHE_ICBI |
6216 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6217 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6218 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6219 PPC_MEM_TLBIA | PPC_74xx_TLB |
6220 PPC_SEGMENT | PPC_EXTERN |
6221 PPC_ALTIVEC;
6222 pcc->insns_flags2 = PPC_NONE;
6223 pcc->msr_mask = 0x000000000205FF77ULL;
6224 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6225 pcc->excp_model = POWERPC_EXCP_74xx;
6226 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6227 pcc->bfd_mach = bfd_mach_ppc_7400;
6228 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6229 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6230 POWERPC_FLAG_BUS_CLK;
6231 }
6232
6233 static void init_proc_7445 (CPUPPCState *env)
6234 {
6235 gen_spr_ne_601(env);
6236 gen_spr_7xx(env);
6237 /* Time base */
6238 gen_tbl(env);
6239 /* 74xx specific SPR */
6240 gen_spr_74xx(env);
6241 /* LDSTCR */
6242 /* XXX : not implemented */
6243 spr_register(env, SPR_LDSTCR, "LDSTCR",
6244 SPR_NOACCESS, SPR_NOACCESS,
6245 &spr_read_generic, &spr_write_generic,
6246 0x00000000);
6247 /* ICTRL */
6248 /* XXX : not implemented */
6249 spr_register(env, SPR_ICTRL, "ICTRL",
6250 SPR_NOACCESS, SPR_NOACCESS,
6251 &spr_read_generic, &spr_write_generic,
6252 0x00000000);
6253 /* MSSSR0 */
6254 /* XXX : not implemented */
6255 spr_register(env, SPR_MSSSR0, "MSSSR0",
6256 SPR_NOACCESS, SPR_NOACCESS,
6257 &spr_read_generic, &spr_write_generic,
6258 0x00000000);
6259 /* PMC */
6260 /* XXX : not implemented */
6261 spr_register(env, SPR_PMC5, "PMC5",
6262 SPR_NOACCESS, SPR_NOACCESS,
6263 &spr_read_generic, &spr_write_generic,
6264 0x00000000);
6265 /* XXX : not implemented */
6266 spr_register(env, SPR_UPMC5, "UPMC5",
6267 &spr_read_ureg, SPR_NOACCESS,
6268 &spr_read_ureg, SPR_NOACCESS,
6269 0x00000000);
6270 /* XXX : not implemented */
6271 spr_register(env, SPR_PMC6, "PMC6",
6272 SPR_NOACCESS, SPR_NOACCESS,
6273 &spr_read_generic, &spr_write_generic,
6274 0x00000000);
6275 /* XXX : not implemented */
6276 spr_register(env, SPR_UPMC6, "UPMC6",
6277 &spr_read_ureg, SPR_NOACCESS,
6278 &spr_read_ureg, SPR_NOACCESS,
6279 0x00000000);
6280 /* SPRGs */
6281 spr_register(env, SPR_SPRG4, "SPRG4",
6282 SPR_NOACCESS, SPR_NOACCESS,
6283 &spr_read_generic, &spr_write_generic,
6284 0x00000000);
6285 spr_register(env, SPR_USPRG4, "USPRG4",
6286 &spr_read_ureg, SPR_NOACCESS,
6287 &spr_read_ureg, SPR_NOACCESS,
6288 0x00000000);
6289 spr_register(env, SPR_SPRG5, "SPRG5",
6290 SPR_NOACCESS, SPR_NOACCESS,
6291 &spr_read_generic, &spr_write_generic,
6292 0x00000000);
6293 spr_register(env, SPR_USPRG5, "USPRG5",
6294 &spr_read_ureg, SPR_NOACCESS,
6295 &spr_read_ureg, SPR_NOACCESS,
6296 0x00000000);
6297 spr_register(env, SPR_SPRG6, "SPRG6",
6298 SPR_NOACCESS, SPR_NOACCESS,
6299 &spr_read_generic, &spr_write_generic,
6300 0x00000000);
6301 spr_register(env, SPR_USPRG6, "USPRG6",
6302 &spr_read_ureg, SPR_NOACCESS,
6303 &spr_read_ureg, SPR_NOACCESS,
6304 0x00000000);
6305 spr_register(env, SPR_SPRG7, "SPRG7",
6306 SPR_NOACCESS, SPR_NOACCESS,
6307 &spr_read_generic, &spr_write_generic,
6308 0x00000000);
6309 spr_register(env, SPR_USPRG7, "USPRG7",
6310 &spr_read_ureg, SPR_NOACCESS,
6311 &spr_read_ureg, SPR_NOACCESS,
6312 0x00000000);
6313 /* Memory management */
6314 gen_low_BATs(env);
6315 gen_high_BATs(env);
6316 gen_74xx_soft_tlb(env, 128, 2);
6317 init_excp_7450(env);
6318 env->dcache_line_size = 32;
6319 env->icache_line_size = 32;
6320 /* Allocate hardware IRQ controller */
6321 ppc6xx_irq_init(env);
6322 }
6323
6324 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6325 {
6326 DeviceClass *dc = DEVICE_CLASS(oc);
6327 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6328
6329 dc->desc = "PowerPC 7445 (aka G4)";
6330 pcc->init_proc = init_proc_7445;
6331 pcc->check_pow = check_pow_hid0_74xx;
6332 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6333 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6334 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6335 PPC_FLOAT_STFIWX |
6336 PPC_CACHE | PPC_CACHE_ICBI |
6337 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6338 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6339 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6340 PPC_MEM_TLBIA | PPC_74xx_TLB |
6341 PPC_SEGMENT | PPC_EXTERN |
6342 PPC_ALTIVEC;
6343 pcc->insns_flags2 = PPC_NONE;
6344 pcc->msr_mask = 0x000000000205FF77ULL;
6345 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6346 pcc->excp_model = POWERPC_EXCP_74xx;
6347 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6348 pcc->bfd_mach = bfd_mach_ppc_7400;
6349 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6350 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6351 POWERPC_FLAG_BUS_CLK;
6352 }
6353
6354 static void init_proc_7455 (CPUPPCState *env)
6355 {
6356 gen_spr_ne_601(env);
6357 gen_spr_7xx(env);
6358 /* Time base */
6359 gen_tbl(env);
6360 /* 74xx specific SPR */
6361 gen_spr_74xx(env);
6362 /* Level 3 cache control */
6363 gen_l3_ctrl(env);
6364 /* LDSTCR */
6365 /* XXX : not implemented */
6366 spr_register(env, SPR_LDSTCR, "LDSTCR",
6367 SPR_NOACCESS, SPR_NOACCESS,
6368 &spr_read_generic, &spr_write_generic,
6369 0x00000000);
6370 /* ICTRL */
6371 /* XXX : not implemented */
6372 spr_register(env, SPR_ICTRL, "ICTRL",
6373 SPR_NOACCESS, SPR_NOACCESS,
6374 &spr_read_generic, &spr_write_generic,
6375 0x00000000);
6376 /* MSSSR0 */
6377 /* XXX : not implemented */
6378 spr_register(env, SPR_MSSSR0, "MSSSR0",
6379 SPR_NOACCESS, SPR_NOACCESS,
6380 &spr_read_generic, &spr_write_generic,
6381 0x00000000);
6382 /* PMC */
6383 /* XXX : not implemented */
6384 spr_register(env, SPR_PMC5, "PMC5",
6385 SPR_NOACCESS, SPR_NOACCESS,
6386 &spr_read_generic, &spr_write_generic,
6387 0x00000000);
6388 /* XXX : not implemented */
6389 spr_register(env, SPR_UPMC5, "UPMC5",
6390 &spr_read_ureg, SPR_NOACCESS,
6391 &spr_read_ureg, SPR_NOACCESS,
6392 0x00000000);
6393 /* XXX : not implemented */
6394 spr_register(env, SPR_PMC6, "PMC6",
6395 SPR_NOACCESS, SPR_NOACCESS,
6396 &spr_read_generic, &spr_write_generic,
6397 0x00000000);
6398 /* XXX : not implemented */
6399 spr_register(env, SPR_UPMC6, "UPMC6",
6400 &spr_read_ureg, SPR_NOACCESS,
6401 &spr_read_ureg, SPR_NOACCESS,
6402 0x00000000);
6403 /* SPRGs */
6404 spr_register(env, SPR_SPRG4, "SPRG4",
6405 SPR_NOACCESS, SPR_NOACCESS,
6406 &spr_read_generic, &spr_write_generic,
6407 0x00000000);
6408 spr_register(env, SPR_USPRG4, "USPRG4",
6409 &spr_read_ureg, SPR_NOACCESS,
6410 &spr_read_ureg, SPR_NOACCESS,
6411 0x00000000);
6412 spr_register(env, SPR_SPRG5, "SPRG5",
6413 SPR_NOACCESS, SPR_NOACCESS,
6414 &spr_read_generic, &spr_write_generic,
6415 0x00000000);
6416 spr_register(env, SPR_USPRG5, "USPRG5",
6417 &spr_read_ureg, SPR_NOACCESS,
6418 &spr_read_ureg, SPR_NOACCESS,
6419 0x00000000);
6420 spr_register(env, SPR_SPRG6, "SPRG6",
6421 SPR_NOACCESS, SPR_NOACCESS,
6422 &spr_read_generic, &spr_write_generic,
6423 0x00000000);
6424 spr_register(env, SPR_USPRG6, "USPRG6",
6425 &spr_read_ureg, SPR_NOACCESS,
6426 &spr_read_ureg, SPR_NOACCESS,
6427 0x00000000);
6428 spr_register(env, SPR_SPRG7, "SPRG7",
6429 SPR_NOACCESS, SPR_NOACCESS,
6430 &spr_read_generic, &spr_write_generic,
6431 0x00000000);
6432 spr_register(env, SPR_USPRG7, "USPRG7",
6433 &spr_read_ureg, SPR_NOACCESS,
6434 &spr_read_ureg, SPR_NOACCESS,
6435 0x00000000);
6436 /* Memory management */
6437 gen_low_BATs(env);
6438 gen_high_BATs(env);
6439 gen_74xx_soft_tlb(env, 128, 2);
6440 init_excp_7450(env);
6441 env->dcache_line_size = 32;
6442 env->icache_line_size = 32;
6443 /* Allocate hardware IRQ controller */
6444 ppc6xx_irq_init(env);
6445 }
6446
6447 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
6448 {
6449 DeviceClass *dc = DEVICE_CLASS(oc);
6450 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6451
6452 dc->desc = "PowerPC 7455 (aka G4)";
6453 pcc->init_proc = init_proc_7455;
6454 pcc->check_pow = check_pow_hid0_74xx;
6455 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6456 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6457 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6458 PPC_FLOAT_STFIWX |
6459 PPC_CACHE | PPC_CACHE_ICBI |
6460 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6461 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6462 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6463 PPC_MEM_TLBIA | PPC_74xx_TLB |
6464 PPC_SEGMENT | PPC_EXTERN |
6465 PPC_ALTIVEC;
6466 pcc->insns_flags2 = PPC_NONE;
6467 pcc->msr_mask = 0x000000000205FF77ULL;
6468 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6469 pcc->excp_model = POWERPC_EXCP_74xx;
6470 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6471 pcc->bfd_mach = bfd_mach_ppc_7400;
6472 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6473 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6474 POWERPC_FLAG_BUS_CLK;
6475 }
6476
6477 static void init_proc_7457 (CPUPPCState *env)
6478 {
6479 gen_spr_ne_601(env);
6480 gen_spr_7xx(env);
6481 /* Time base */
6482 gen_tbl(env);
6483 /* 74xx specific SPR */
6484 gen_spr_74xx(env);
6485 /* Level 3 cache control */
6486 gen_l3_ctrl(env);
6487 /* L3ITCR1 */
6488 /* XXX : not implemented */
6489 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6490 SPR_NOACCESS, SPR_NOACCESS,
6491 &spr_read_generic, &spr_write_generic,
6492 0x00000000);
6493 /* L3ITCR2 */
6494 /* XXX : not implemented */
6495 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6496 SPR_NOACCESS, SPR_NOACCESS,
6497 &spr_read_generic, &spr_write_generic,
6498 0x00000000);
6499 /* L3ITCR3 */
6500 /* XXX : not implemented */
6501 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6502 SPR_NOACCESS, SPR_NOACCESS,
6503 &spr_read_generic, &spr_write_generic,
6504 0x00000000);
6505 /* L3OHCR */
6506 /* XXX : not implemented */
6507 spr_register(env, SPR_L3OHCR, "L3OHCR",
6508 SPR_NOACCESS, SPR_NOACCESS,
6509 &spr_read_generic, &spr_write_generic,
6510 0x00000000);
6511 /* LDSTCR */
6512 /* XXX : not implemented */
6513 spr_register(env, SPR_LDSTCR, "LDSTCR",
6514 SPR_NOACCESS, SPR_NOACCESS,
6515 &spr_read_generic, &spr_write_generic,
6516 0x00000000);
6517 /* ICTRL */
6518 /* XXX : not implemented */
6519 spr_register(env, SPR_ICTRL, "ICTRL",
6520 SPR_NOACCESS, SPR_NOACCESS,
6521 &spr_read_generic, &spr_write_generic,
6522 0x00000000);
6523 /* MSSSR0 */
6524 /* XXX : not implemented */
6525 spr_register(env, SPR_MSSSR0, "MSSSR0",
6526 SPR_NOACCESS, SPR_NOACCESS,
6527 &spr_read_generic, &spr_write_generic,
6528 0x00000000);
6529 /* PMC */
6530 /* XXX : not implemented */
6531 spr_register(env, SPR_PMC5, "PMC5",
6532 SPR_NOACCESS, SPR_NOACCESS,
6533 &spr_read_generic, &spr_write_generic,
6534 0x00000000);
6535 /* XXX : not implemented */
6536 spr_register(env, SPR_UPMC5, "UPMC5",
6537 &spr_read_ureg, SPR_NOACCESS,
6538 &spr_read_ureg, SPR_NOACCESS,
6539 0x00000000);
6540 /* XXX : not implemented */
6541 spr_register(env, SPR_PMC6, "PMC6",
6542 SPR_NOACCESS, SPR_NOACCESS,
6543 &spr_read_generic, &spr_write_generic,
6544 0x00000000);
6545 /* XXX : not implemented */
6546 spr_register(env, SPR_UPMC6, "UPMC6",
6547 &spr_read_ureg, SPR_NOACCESS,
6548 &spr_read_ureg, SPR_NOACCESS,
6549 0x00000000);
6550 /* SPRGs */
6551 spr_register(env, SPR_SPRG4, "SPRG4",
6552 SPR_NOACCESS, SPR_NOACCESS,
6553 &spr_read_generic, &spr_write_generic,
6554 0x00000000);
6555 spr_register(env, SPR_USPRG4, "USPRG4",
6556 &spr_read_ureg, SPR_NOACCESS,
6557 &spr_read_ureg, SPR_NOACCESS,
6558 0x00000000);
6559 spr_register(env, SPR_SPRG5, "SPRG5",
6560 SPR_NOACCESS, SPR_NOACCESS,
6561 &spr_read_generic, &spr_write_generic,
6562 0x00000000);
6563 spr_register(env, SPR_USPRG5, "USPRG5",
6564 &spr_read_ureg, SPR_NOACCESS,
6565 &spr_read_ureg, SPR_NOACCESS,
6566 0x00000000);
6567 spr_register(env, SPR_SPRG6, "SPRG6",
6568 SPR_NOACCESS, SPR_NOACCESS,
6569 &spr_read_generic, &spr_write_generic,
6570 0x00000000);
6571 spr_register(env, SPR_USPRG6, "USPRG6",
6572 &spr_read_ureg, SPR_NOACCESS,
6573 &spr_read_ureg, SPR_NOACCESS,
6574 0x00000000);
6575 spr_register(env, SPR_SPRG7, "SPRG7",
6576 SPR_NOACCESS, SPR_NOACCESS,
6577 &spr_read_generic, &spr_write_generic,
6578 0x00000000);
6579 spr_register(env, SPR_USPRG7, "USPRG7",
6580 &spr_read_ureg, SPR_NOACCESS,
6581 &spr_read_ureg, SPR_NOACCESS,
6582 0x00000000);
6583 /* Memory management */
6584 gen_low_BATs(env);
6585 gen_high_BATs(env);
6586 gen_74xx_soft_tlb(env, 128, 2);
6587 init_excp_7450(env);
6588 env->dcache_line_size = 32;
6589 env->icache_line_size = 32;
6590 /* Allocate hardware IRQ controller */
6591 ppc6xx_irq_init(env);
6592 }
6593
6594 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
6595 {
6596 DeviceClass *dc = DEVICE_CLASS(oc);
6597 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6598
6599 dc->desc = "PowerPC 7457 (aka G4)";
6600 pcc->init_proc = init_proc_7457;
6601 pcc->check_pow = check_pow_hid0_74xx;
6602 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6603 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6604 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6605 PPC_FLOAT_STFIWX |
6606 PPC_CACHE | PPC_CACHE_ICBI |
6607 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6608 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6609 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6610 PPC_MEM_TLBIA | PPC_74xx_TLB |
6611 PPC_SEGMENT | PPC_EXTERN |
6612 PPC_ALTIVEC;
6613 pcc->insns_flags2 = PPC_NONE;
6614 pcc->msr_mask = 0x000000000205FF77ULL;
6615 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6616 pcc->excp_model = POWERPC_EXCP_74xx;
6617 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6618 pcc->bfd_mach = bfd_mach_ppc_7400;
6619 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6620 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6621 POWERPC_FLAG_BUS_CLK;
6622 }
6623
6624 #if defined (TARGET_PPC64)
6625 #if defined(CONFIG_USER_ONLY)
6626 #define POWERPC970_HID5_INIT 0x00000080
6627 #else
6628 #define POWERPC970_HID5_INIT 0x00000000
6629 #endif
6630
6631 static int check_pow_970 (CPUPPCState *env)
6632 {
6633 if (env->spr[SPR_HID0] & 0x00600000)
6634 return 1;
6635
6636 return 0;
6637 }
6638
6639 static void init_proc_970 (CPUPPCState *env)
6640 {
6641 gen_spr_ne_601(env);
6642 gen_spr_7xx(env);
6643 /* Time base */
6644 gen_tbl(env);
6645 /* Hardware implementation registers */
6646 /* XXX : not implemented */
6647 spr_register(env, SPR_HID0, "HID0",
6648 SPR_NOACCESS, SPR_NOACCESS,
6649 &spr_read_generic, &spr_write_clear,
6650 0x60000000);
6651 /* XXX : not implemented */
6652 spr_register(env, SPR_HID1, "HID1",
6653 SPR_NOACCESS, SPR_NOACCESS,
6654 &spr_read_generic, &spr_write_generic,
6655 0x00000000);
6656 /* XXX : not implemented */
6657 spr_register(env, SPR_750FX_HID2, "HID2",
6658 SPR_NOACCESS, SPR_NOACCESS,
6659 &spr_read_generic, &spr_write_generic,
6660 0x00000000);
6661 /* XXX : not implemented */
6662 spr_register(env, SPR_970_HID5, "HID5",
6663 SPR_NOACCESS, SPR_NOACCESS,
6664 &spr_read_generic, &spr_write_generic,
6665 POWERPC970_HID5_INIT);
6666 /* XXX : not implemented */
6667 spr_register(env, SPR_L2CR, "L2CR",
6668 SPR_NOACCESS, SPR_NOACCESS,
6669 &spr_read_generic, &spr_write_generic,
6670 0x00000000);
6671 /* Memory management */
6672 /* XXX: not correct */
6673 gen_low_BATs(env);
6674 /* XXX : not implemented */
6675 spr_register(env, SPR_MMUCFG, "MMUCFG",
6676 SPR_NOACCESS, SPR_NOACCESS,
6677 &spr_read_generic, SPR_NOACCESS,
6678 0x00000000); /* TOFIX */
6679 /* XXX : not implemented */
6680 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6681 SPR_NOACCESS, SPR_NOACCESS,
6682 &spr_read_generic, &spr_write_generic,
6683 0x00000000); /* TOFIX */
6684 spr_register(env, SPR_HIOR, "SPR_HIOR",
6685 SPR_NOACCESS, SPR_NOACCESS,
6686 &spr_read_hior, &spr_write_hior,
6687 0x00000000);
6688 #if !defined(CONFIG_USER_ONLY)
6689 env->slb_nr = 32;
6690 #endif
6691 init_excp_970(env);
6692 env->dcache_line_size = 128;
6693 env->icache_line_size = 128;
6694 /* Allocate hardware IRQ controller */
6695 ppc970_irq_init(env);
6696 /* Can't find information on what this should be on reset. This
6697 * value is the one used by 74xx processors. */
6698 vscr_init(env, 0x00010000);
6699 }
6700
6701 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
6702 {
6703 DeviceClass *dc = DEVICE_CLASS(oc);
6704 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6705
6706 dc->desc = "PowerPC 970";
6707 pcc->init_proc = init_proc_970;
6708 pcc->check_pow = check_pow_970;
6709 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6710 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6711 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6712 PPC_FLOAT_STFIWX |
6713 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6714 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6715 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6716 PPC_64B | PPC_ALTIVEC |
6717 PPC_SEGMENT_64B | PPC_SLBI;
6718 pcc->insns_flags2 = PPC_NONE;
6719 pcc->msr_mask = 0x900000000204FF36ULL;
6720 pcc->mmu_model = POWERPC_MMU_64B;
6721 pcc->excp_model = POWERPC_EXCP_970;
6722 pcc->bus_model = PPC_FLAGS_INPUT_970;
6723 pcc->bfd_mach = bfd_mach_ppc64;
6724 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6725 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6726 POWERPC_FLAG_BUS_CLK;
6727 }
6728
6729 static int check_pow_970FX (CPUPPCState *env)
6730 {
6731 if (env->spr[SPR_HID0] & 0x00600000)
6732 return 1;
6733
6734 return 0;
6735 }
6736
6737 static void init_proc_970FX (CPUPPCState *env)
6738 {
6739 gen_spr_ne_601(env);
6740 gen_spr_7xx(env);
6741 /* Time base */
6742 gen_tbl(env);
6743 /* Hardware implementation registers */
6744 /* XXX : not implemented */
6745 spr_register(env, SPR_HID0, "HID0",
6746 SPR_NOACCESS, SPR_NOACCESS,
6747 &spr_read_generic, &spr_write_clear,
6748 0x60000000);
6749 /* XXX : not implemented */
6750 spr_register(env, SPR_HID1, "HID1",
6751 SPR_NOACCESS, SPR_NOACCESS,
6752 &spr_read_generic, &spr_write_generic,
6753 0x00000000);
6754 /* XXX : not implemented */
6755 spr_register(env, SPR_750FX_HID2, "HID2",
6756 SPR_NOACCESS, SPR_NOACCESS,
6757 &spr_read_generic, &spr_write_generic,
6758 0x00000000);
6759 /* XXX : not implemented */
6760 spr_register(env, SPR_970_HID5, "HID5",
6761 SPR_NOACCESS, SPR_NOACCESS,
6762 &spr_read_generic, &spr_write_generic,
6763 POWERPC970_HID5_INIT);
6764 /* XXX : not implemented */
6765 spr_register(env, SPR_L2CR, "L2CR",
6766 SPR_NOACCESS, SPR_NOACCESS,
6767 &spr_read_generic, &spr_write_generic,
6768 0x00000000);
6769 /* Memory management */
6770 /* XXX: not correct */
6771 gen_low_BATs(env);
6772 /* XXX : not implemented */
6773 spr_register(env, SPR_MMUCFG, "MMUCFG",
6774 SPR_NOACCESS, SPR_NOACCESS,
6775 &spr_read_generic, SPR_NOACCESS,
6776 0x00000000); /* TOFIX */
6777 /* XXX : not implemented */
6778 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6779 SPR_NOACCESS, SPR_NOACCESS,
6780 &spr_read_generic, &spr_write_generic,
6781 0x00000000); /* TOFIX */
6782 spr_register(env, SPR_HIOR, "SPR_HIOR",
6783 SPR_NOACCESS, SPR_NOACCESS,
6784 &spr_read_hior, &spr_write_hior,
6785 0x00000000);
6786 spr_register(env, SPR_CTRL, "SPR_CTRL",
6787 SPR_NOACCESS, SPR_NOACCESS,
6788 &spr_read_generic, &spr_write_generic,
6789 0x00000000);
6790 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6791 SPR_NOACCESS, SPR_NOACCESS,
6792 &spr_read_generic, &spr_write_generic,
6793 0x00000000);
6794 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6795 &spr_read_generic, &spr_write_generic,
6796 &spr_read_generic, &spr_write_generic,
6797 0x00000000);
6798 #if !defined(CONFIG_USER_ONLY)
6799 env->slb_nr = 64;
6800 #endif
6801 init_excp_970(env);
6802 env->dcache_line_size = 128;
6803 env->icache_line_size = 128;
6804 /* Allocate hardware IRQ controller */
6805 ppc970_irq_init(env);
6806 /* Can't find information on what this should be on reset. This
6807 * value is the one used by 74xx processors. */
6808 vscr_init(env, 0x00010000);
6809 }
6810
6811 POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
6812 {
6813 DeviceClass *dc = DEVICE_CLASS(oc);
6814 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6815
6816 dc->desc = "PowerPC 970FX (aka G5)";
6817 pcc->init_proc = init_proc_970FX;
6818 pcc->check_pow = check_pow_970FX;
6819 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6820 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6821 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6822 PPC_FLOAT_STFIWX |
6823 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6824 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6825 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6826 PPC_64B | PPC_ALTIVEC |
6827 PPC_SEGMENT_64B | PPC_SLBI;
6828 pcc->insns_flags2 = PPC_NONE;
6829 pcc->msr_mask = 0x800000000204FF36ULL;
6830 pcc->mmu_model = POWERPC_MMU_64B;
6831 pcc->excp_model = POWERPC_EXCP_970;
6832 pcc->bus_model = PPC_FLAGS_INPUT_970;
6833 pcc->bfd_mach = bfd_mach_ppc64;
6834 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6835 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6836 POWERPC_FLAG_BUS_CLK;
6837 }
6838
6839 static int check_pow_970GX (CPUPPCState *env)
6840 {
6841 if (env->spr[SPR_HID0] & 0x00600000)
6842 return 1;
6843
6844 return 0;
6845 }
6846
6847 static void init_proc_970GX (CPUPPCState *env)
6848 {
6849 gen_spr_ne_601(env);
6850 gen_spr_7xx(env);
6851 /* Time base */
6852 gen_tbl(env);
6853 /* Hardware implementation registers */
6854 /* XXX : not implemented */
6855 spr_register(env, SPR_HID0, "HID0",
6856 SPR_NOACCESS, SPR_NOACCESS,
6857 &spr_read_generic, &spr_write_clear,
6858 0x60000000);
6859 /* XXX : not implemented */
6860 spr_register(env, SPR_HID1, "HID1",
6861 SPR_NOACCESS, SPR_NOACCESS,
6862 &spr_read_generic, &spr_write_generic,
6863 0x00000000);
6864 /* XXX : not implemented */
6865 spr_register(env, SPR_750FX_HID2, "HID2",
6866 SPR_NOACCESS, SPR_NOACCESS,
6867 &spr_read_generic, &spr_write_generic,
6868 0x00000000);
6869 /* XXX : not implemented */
6870 spr_register(env, SPR_970_HID5, "HID5",
6871 SPR_NOACCESS, SPR_NOACCESS,
6872 &spr_read_generic, &spr_write_generic,
6873 POWERPC970_HID5_INIT);
6874 /* XXX : not implemented */
6875 spr_register(env, SPR_L2CR, "L2CR",
6876 SPR_NOACCESS, SPR_NOACCESS,
6877 &spr_read_generic, &spr_write_generic,
6878 0x00000000);
6879 /* Memory management */
6880 /* XXX: not correct */
6881 gen_low_BATs(env);
6882 /* XXX : not implemented */
6883 spr_register(env, SPR_MMUCFG, "MMUCFG",
6884 SPR_NOACCESS, SPR_NOACCESS,
6885 &spr_read_generic, SPR_NOACCESS,
6886 0x00000000); /* TOFIX */
6887 /* XXX : not implemented */
6888 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6889 SPR_NOACCESS, SPR_NOACCESS,
6890 &spr_read_generic, &spr_write_generic,
6891 0x00000000); /* TOFIX */
6892 spr_register(env, SPR_HIOR, "SPR_HIOR",
6893 SPR_NOACCESS, SPR_NOACCESS,
6894 &spr_read_hior, &spr_write_hior,
6895 0x00000000);
6896 #if !defined(CONFIG_USER_ONLY)
6897 env->slb_nr = 32;
6898 #endif
6899 init_excp_970(env);
6900 env->dcache_line_size = 128;
6901 env->icache_line_size = 128;
6902 /* Allocate hardware IRQ controller */
6903 ppc970_irq_init(env);
6904 /* Can't find information on what this should be on reset. This
6905 * value is the one used by 74xx processors. */
6906 vscr_init(env, 0x00010000);
6907 }
6908
6909 POWERPC_FAMILY(970GX)(ObjectClass *oc, void *data)
6910 {
6911 DeviceClass *dc = DEVICE_CLASS(oc);
6912 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6913
6914 dc->desc = "PowerPC 970 GX";
6915 pcc->init_proc = init_proc_970GX;
6916 pcc->check_pow = check_pow_970GX;
6917 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6918 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6919 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6920 PPC_FLOAT_STFIWX |
6921 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6922 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6923 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6924 PPC_64B | PPC_ALTIVEC |
6925 PPC_SEGMENT_64B | PPC_SLBI;
6926 pcc->insns_flags2 = PPC_NONE;
6927 pcc->msr_mask = 0x800000000204FF36ULL;
6928 pcc->mmu_model = POWERPC_MMU_64B;
6929 pcc->excp_model = POWERPC_EXCP_970;
6930 pcc->bus_model = PPC_FLAGS_INPUT_970;
6931 pcc->bfd_mach = bfd_mach_ppc64;
6932 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6933 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6934 POWERPC_FLAG_BUS_CLK;
6935 }
6936
6937 static int check_pow_970MP (CPUPPCState *env)
6938 {
6939 if (env->spr[SPR_HID0] & 0x01C00000)
6940 return 1;
6941
6942 return 0;
6943 }
6944
6945 static void init_proc_970MP (CPUPPCState *env)
6946 {
6947 gen_spr_ne_601(env);
6948 gen_spr_7xx(env);
6949 /* Time base */
6950 gen_tbl(env);
6951 /* Hardware implementation registers */
6952 /* XXX : not implemented */
6953 spr_register(env, SPR_HID0, "HID0",
6954 SPR_NOACCESS, SPR_NOACCESS,
6955 &spr_read_generic, &spr_write_clear,
6956 0x60000000);
6957 /* XXX : not implemented */
6958 spr_register(env, SPR_HID1, "HID1",
6959 SPR_NOACCESS, SPR_NOACCESS,
6960 &spr_read_generic, &spr_write_generic,
6961 0x00000000);
6962 /* XXX : not implemented */
6963 spr_register(env, SPR_750FX_HID2, "HID2",
6964 SPR_NOACCESS, SPR_NOACCESS,
6965 &spr_read_generic, &spr_write_generic,
6966 0x00000000);
6967 /* XXX : not implemented */
6968 spr_register(env, SPR_970_HID5, "HID5",
6969 SPR_NOACCESS, SPR_NOACCESS,
6970 &spr_read_generic, &spr_write_generic,
6971 POWERPC970_HID5_INIT);
6972 /* XXX : not implemented */
6973 spr_register(env, SPR_L2CR, "L2CR",
6974 SPR_NOACCESS, SPR_NOACCESS,
6975 &spr_read_generic, &spr_write_generic,
6976 0x00000000);
6977 /* Memory management */
6978 /* XXX: not correct */
6979 gen_low_BATs(env);
6980 /* XXX : not implemented */
6981 spr_register(env, SPR_MMUCFG, "MMUCFG",
6982 SPR_NOACCESS, SPR_NOACCESS,
6983 &spr_read_generic, SPR_NOACCESS,
6984 0x00000000); /* TOFIX */
6985 /* XXX : not implemented */
6986 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6987 SPR_NOACCESS, SPR_NOACCESS,
6988 &spr_read_generic, &spr_write_generic,
6989 0x00000000); /* TOFIX */
6990 spr_register(env, SPR_HIOR, "SPR_HIOR",
6991 SPR_NOACCESS, SPR_NOACCESS,
6992 &spr_read_hior, &spr_write_hior,
6993 0x00000000);
6994 #if !defined(CONFIG_USER_ONLY)
6995 env->slb_nr = 32;
6996 #endif
6997 init_excp_970(env);
6998 env->dcache_line_size = 128;
6999 env->icache_line_size = 128;
7000 /* Allocate hardware IRQ controller */
7001 ppc970_irq_init(env);
7002 /* Can't find information on what this should be on reset. This
7003 * value is the one used by 74xx processors. */
7004 vscr_init(env, 0x00010000);
7005 }
7006
7007 POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
7008 {
7009 DeviceClass *dc = DEVICE_CLASS(oc);
7010 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7011
7012 dc->desc = "PowerPC 970 MP";
7013 pcc->init_proc = init_proc_970MP;
7014 pcc->check_pow = check_pow_970MP;
7015 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7016 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7017 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7018 PPC_FLOAT_STFIWX |
7019 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7020 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7021 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7022 PPC_64B | PPC_ALTIVEC |
7023 PPC_SEGMENT_64B | PPC_SLBI;
7024 pcc->insns_flags2 = PPC_NONE;
7025 pcc->msr_mask = 0x900000000204FF36ULL;
7026 pcc->mmu_model = POWERPC_MMU_64B;
7027 pcc->excp_model = POWERPC_EXCP_970;
7028 pcc->bus_model = PPC_FLAGS_INPUT_970;
7029 pcc->bfd_mach = bfd_mach_ppc64;
7030 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7031 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7032 POWERPC_FLAG_BUS_CLK;
7033 }
7034
7035 static void init_proc_POWER7 (CPUPPCState *env)
7036 {
7037 gen_spr_ne_601(env);
7038 gen_spr_7xx(env);
7039 /* Time base */
7040 gen_tbl(env);
7041 /* Processor identification */
7042 spr_register(env, SPR_PIR, "PIR",
7043 SPR_NOACCESS, SPR_NOACCESS,
7044 &spr_read_generic, &spr_write_pir,
7045 0x00000000);
7046 #if !defined(CONFIG_USER_ONLY)
7047 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
7048 spr_register(env, SPR_PURR, "PURR",
7049 &spr_read_purr, SPR_NOACCESS,
7050 &spr_read_purr, SPR_NOACCESS,
7051 0x00000000);
7052 spr_register(env, SPR_SPURR, "SPURR",
7053 &spr_read_purr, SPR_NOACCESS,
7054 &spr_read_purr, SPR_NOACCESS,
7055 0x00000000);
7056 spr_register(env, SPR_CFAR, "SPR_CFAR",
7057 SPR_NOACCESS, SPR_NOACCESS,
7058 &spr_read_cfar, &spr_write_cfar,
7059 0x00000000);
7060 spr_register(env, SPR_DSCR, "SPR_DSCR",
7061 SPR_NOACCESS, SPR_NOACCESS,
7062 &spr_read_generic, &spr_write_generic,
7063 0x00000000);
7064 #endif /* !CONFIG_USER_ONLY */
7065 /* Memory management */
7066 /* XXX : not implemented */
7067 spr_register(env, SPR_MMUCFG, "MMUCFG",
7068 SPR_NOACCESS, SPR_NOACCESS,
7069 &spr_read_generic, SPR_NOACCESS,
7070 0x00000000); /* TOFIX */
7071 /* XXX : not implemented */
7072 spr_register(env, SPR_CTRL, "SPR_CTRLT",
7073 SPR_NOACCESS, SPR_NOACCESS,
7074 &spr_read_generic, &spr_write_generic,
7075 0x80800000);
7076 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
7077 SPR_NOACCESS, SPR_NOACCESS,
7078 &spr_read_generic, &spr_write_generic,
7079 0x80800000);
7080 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
7081 &spr_read_generic, &spr_write_generic,
7082 &spr_read_generic, &spr_write_generic,
7083 0x00000000);
7084 #if !defined(CONFIG_USER_ONLY)
7085 env->slb_nr = 32;
7086 #endif
7087 init_excp_POWER7(env);
7088 env->dcache_line_size = 128;
7089 env->icache_line_size = 128;
7090 /* Allocate hardware IRQ controller */
7091 ppcPOWER7_irq_init(env);
7092 /* Can't find information on what this should be on reset. This
7093 * value is the one used by 74xx processors. */
7094 vscr_init(env, 0x00010000);
7095 }
7096
7097 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
7098 {
7099 DeviceClass *dc = DEVICE_CLASS(oc);
7100 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7101
7102 dc->desc = "POWER7";
7103 pcc->init_proc = init_proc_POWER7;
7104 pcc->check_pow = check_pow_nocheck;
7105 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7106 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7107 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7108 PPC_FLOAT_STFIWX |
7109 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7110 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7111 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7112 PPC_64B | PPC_ALTIVEC |
7113 PPC_SEGMENT_64B | PPC_SLBI |
7114 PPC_POPCNTB | PPC_POPCNTWD;
7115 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX;
7116 pcc->msr_mask = 0x800000000204FF36ULL;
7117 pcc->mmu_model = POWERPC_MMU_2_06;
7118 pcc->excp_model = POWERPC_EXCP_POWER7;
7119 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7120 pcc->bfd_mach = bfd_mach_ppc64;
7121 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7122 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7123 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR;
7124 }
7125
7126 static void init_proc_620 (CPUPPCState *env)
7127 {
7128 gen_spr_ne_601(env);
7129 gen_spr_620(env);
7130 /* Time base */
7131 gen_tbl(env);
7132 /* Hardware implementation registers */
7133 /* XXX : not implemented */
7134 spr_register(env, SPR_HID0, "HID0",
7135 SPR_NOACCESS, SPR_NOACCESS,
7136 &spr_read_generic, &spr_write_generic,
7137 0x00000000);
7138 /* Memory management */
7139 gen_low_BATs(env);
7140 init_excp_620(env);
7141 env->dcache_line_size = 64;
7142 env->icache_line_size = 64;
7143 /* Allocate hardware IRQ controller */
7144 ppc6xx_irq_init(env);
7145 }
7146
7147 POWERPC_FAMILY(620)(ObjectClass *oc, void *data)
7148 {
7149 DeviceClass *dc = DEVICE_CLASS(oc);
7150 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7151
7152 dc->desc = "PowerPC 620";
7153 pcc->init_proc = init_proc_620;
7154 pcc->check_pow = check_pow_nocheck; /* Check this */
7155 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7156 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7157 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7158 PPC_FLOAT_STFIWX |
7159 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7160 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7161 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7162 PPC_SEGMENT | PPC_EXTERN |
7163 PPC_64B | PPC_SLBI;
7164 pcc->insns_flags2 = PPC_NONE;
7165 pcc->msr_mask = 0x800000000005FF77ULL;
7166 pcc->mmu_model = POWERPC_MMU_620;
7167 pcc->excp_model = POWERPC_EXCP_970;
7168 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7169 pcc->bfd_mach = bfd_mach_ppc64;
7170 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
7171 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7172 }
7173
7174 #endif /* defined (TARGET_PPC64) */
7175
7176 /*****************************************************************************/
7177 /* PVR definitions for most known PowerPC */
7178 enum {
7179 /* PowerPC 401 family */
7180 /* Generic PowerPC 401 */
7181 #define CPU_POWERPC_401 CPU_POWERPC_401G2
7182 /* PowerPC 401 cores */
7183 CPU_POWERPC_401A1 = 0x00210000,
7184 CPU_POWERPC_401B2 = 0x00220000,
7185 #if 0
7186 CPU_POWERPC_401B3 = xxx,
7187 #endif
7188 CPU_POWERPC_401C2 = 0x00230000,
7189 CPU_POWERPC_401D2 = 0x00240000,
7190 CPU_POWERPC_401E2 = 0x00250000,
7191 CPU_POWERPC_401F2 = 0x00260000,
7192 CPU_POWERPC_401G2 = 0x00270000,
7193 /* PowerPC 401 microcontrolers */
7194 #if 0
7195 CPU_POWERPC_401GF = xxx,
7196 #endif
7197 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
7198 /* IBM Processor for Network Resources */
7199 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
7200 #if 0
7201 CPU_POWERPC_XIPCHIP = xxx,
7202 #endif
7203 /* PowerPC 403 family */
7204 /* PowerPC 403 microcontrollers */
7205 CPU_POWERPC_403GA = 0x00200011,
7206 CPU_POWERPC_403GB = 0x00200100,
7207 CPU_POWERPC_403GC = 0x00200200,
7208 CPU_POWERPC_403GCX = 0x00201400,
7209 #if 0
7210 CPU_POWERPC_403GP = xxx,
7211 #endif
7212 /* PowerPC 405 family */
7213 /* PowerPC 405 cores */
7214 #if 0
7215 CPU_POWERPC_405A3 = xxx,
7216 #endif
7217 #if 0
7218 CPU_POWERPC_405A4 = xxx,
7219 #endif
7220 #if 0
7221 CPU_POWERPC_405B3 = xxx,
7222 #endif
7223 #if 0
7224 CPU_POWERPC_405B4 = xxx,
7225 #endif
7226 #if 0
7227 CPU_POWERPC_405C3 = xxx,
7228 #endif
7229 #if 0
7230 CPU_POWERPC_405C4 = xxx,
7231 #endif
7232 CPU_POWERPC_405D2 = 0x20010000,
7233 #if 0
7234 CPU_POWERPC_405D3 = xxx,
7235 #endif
7236 CPU_POWERPC_405D4 = 0x41810000,
7237 #if 0
7238 CPU_POWERPC_405D5 = xxx,
7239 #endif
7240 #if 0
7241 CPU_POWERPC_405E4 = xxx,
7242 #endif
7243 #if 0
7244 CPU_POWERPC_405F4 = xxx,
7245 #endif
7246 #if 0
7247 CPU_POWERPC_405F5 = xxx,
7248 #endif
7249 #if 0
7250 CPU_POWERPC_405F6 = xxx,
7251 #endif
7252 /* PowerPC 405 microcontrolers */
7253 /* XXX: missing 0x200108a0 */
7254 CPU_POWERPC_405CRa = 0x40110041,
7255 CPU_POWERPC_405CRb = 0x401100C5,
7256 CPU_POWERPC_405CRc = 0x40110145,
7257 CPU_POWERPC_405EP = 0x51210950,
7258 #if 0
7259 CPU_POWERPC_405EXr = xxx,
7260 #endif
7261 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
7262 #if 0
7263 CPU_POWERPC_405FX = xxx,
7264 #endif
7265 CPU_POWERPC_405GPa = 0x40110000,
7266 CPU_POWERPC_405GPb = 0x40110040,
7267 CPU_POWERPC_405GPc = 0x40110082,
7268 CPU_POWERPC_405GPd = 0x401100C4,
7269 CPU_POWERPC_405GPR = 0x50910951,
7270 #if 0
7271 CPU_POWERPC_405H = xxx,
7272 #endif
7273 #if 0
7274 CPU_POWERPC_405L = xxx,
7275 #endif
7276 CPU_POWERPC_405LP = 0x41F10000,
7277 #if 0
7278 CPU_POWERPC_405PM = xxx,
7279 #endif
7280 #if 0
7281 CPU_POWERPC_405PS = xxx,
7282 #endif
7283 #if 0
7284 CPU_POWERPC_405S = xxx,
7285 #endif
7286 /* IBM network processors */
7287 CPU_POWERPC_NPE405H = 0x414100C0,
7288 CPU_POWERPC_NPE405H2 = 0x41410140,
7289 CPU_POWERPC_NPE405L = 0x416100C0,
7290 CPU_POWERPC_NPE4GS3 = 0x40B10000,
7291 #if 0
7292 CPU_POWERPC_NPCxx1 = xxx,
7293 #endif
7294 #if 0
7295 CPU_POWERPC_NPR161 = xxx,
7296 #endif
7297 #if 0
7298 CPU_POWERPC_LC77700 = xxx,
7299 #endif
7300 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
7301 #if 0
7302 CPU_POWERPC_STB01000 = xxx,
7303 #endif
7304 #if 0
7305 CPU_POWERPC_STB01010 = xxx,
7306 #endif
7307 #if 0
7308 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
7309 #endif
7310 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
7311 #if 0
7312 CPU_POWERPC_STB043 = xxx,
7313 #endif
7314 #if 0
7315 CPU_POWERPC_STB045 = xxx,
7316 #endif
7317 CPU_POWERPC_STB04 = 0x41810000,
7318 CPU_POWERPC_STB25 = 0x51510950,
7319 #if 0
7320 CPU_POWERPC_STB130 = xxx,
7321 #endif
7322 /* Xilinx cores */
7323 CPU_POWERPC_X2VP4 = 0x20010820,
7324 CPU_POWERPC_X2VP20 = 0x20010860,
7325 #if 0
7326 CPU_POWERPC_ZL10310 = xxx,
7327 #endif
7328 #if 0
7329 CPU_POWERPC_ZL10311 = xxx,
7330 #endif
7331 #if 0
7332 CPU_POWERPC_ZL10320 = xxx,
7333 #endif
7334 #if 0
7335 CPU_POWERPC_ZL10321 = xxx,
7336 #endif
7337 /* PowerPC 440 family */
7338 /* Generic PowerPC 440 */
7339 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
7340 /* PowerPC 440 cores */
7341 #if 0
7342 CPU_POWERPC_440A4 = xxx,
7343 #endif
7344 CPU_POWERPC_440_XILINX = 0x7ff21910,
7345 #if 0
7346 CPU_POWERPC_440A5 = xxx,
7347 #endif
7348 #if 0
7349 CPU_POWERPC_440B4 = xxx,
7350 #endif
7351 #if 0
7352 CPU_POWERPC_440F5 = xxx,
7353 #endif
7354 #if 0
7355 CPU_POWERPC_440G5 = xxx,
7356 #endif
7357 #if 0
7358 CPU_POWERPC_440H4 = xxx,
7359 #endif
7360 #if 0
7361 CPU_POWERPC_440H6 = xxx,
7362 #endif
7363 /* PowerPC 440 microcontrolers */
7364 CPU_POWERPC_440EPa = 0x42221850,
7365 CPU_POWERPC_440EPb = 0x422218D3,
7366 CPU_POWERPC_440GPb = 0x40120440,
7367 CPU_POWERPC_440GPc = 0x40120481,
7368 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
7369 CPU_POWERPC_440GRX = 0x200008D0,
7370 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
7371 CPU_POWERPC_440GXa = 0x51B21850,
7372 CPU_POWERPC_440GXb = 0x51B21851,
7373 CPU_POWERPC_440GXc = 0x51B21892,
7374 CPU_POWERPC_440GXf = 0x51B21894,
7375 #if 0
7376 CPU_POWERPC_440S = xxx,
7377 #endif
7378 CPU_POWERPC_440SP = 0x53221850,
7379 CPU_POWERPC_440SP2 = 0x53221891,
7380 CPU_POWERPC_440SPE = 0x53421890,
7381 /* PowerPC 460 family */
7382 #if 0
7383 /* Generic PowerPC 464 */
7384 #define CPU_POWERPC_464 CPU_POWERPC_464H90
7385 #endif
7386 /* PowerPC 464 microcontrolers */
7387 #if 0
7388 CPU_POWERPC_464H90 = xxx,
7389 #endif
7390 #if 0
7391 CPU_POWERPC_464H90FP = xxx,
7392 #endif
7393 /* Freescale embedded PowerPC cores */
7394 /* PowerPC MPC 5xx cores (aka RCPU) */
7395 CPU_POWERPC_MPC5xx = 0x00020020,
7396 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
7397 CPU_POWERPC_MPC8xx = 0x00500000,
7398 /* G2 cores (aka PowerQUICC-II) */
7399 CPU_POWERPC_G2 = 0x00810011,
7400 CPU_POWERPC_G2H4 = 0x80811010,
7401 CPU_POWERPC_G2gp = 0x80821010,
7402 CPU_POWERPC_G2ls = 0x90810010,
7403 CPU_POWERPC_MPC603 = 0x00810100,
7404 CPU_POWERPC_G2_HIP3 = 0x00810101,
7405 CPU_POWERPC_G2_HIP4 = 0x80811014,
7406 /* G2_LE core (aka PowerQUICC-II) */
7407 CPU_POWERPC_G2LE = 0x80820010,
7408 CPU_POWERPC_G2LEgp = 0x80822010,
7409 CPU_POWERPC_G2LEls = 0xA0822010,
7410 CPU_POWERPC_G2LEgp1 = 0x80822011,
7411 CPU_POWERPC_G2LEgp3 = 0x80822013,
7412 /* MPC52xx microcontrollers */
7413 /* XXX: MPC 5121 ? */
7414 #define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
7415 #define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
7416 #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
7417 #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
7418 #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
7419 /* e200 family */
7420 /* e200 cores */
7421 #if 0
7422 CPU_POWERPC_e200z0 = xxx,
7423 #endif
7424 #if 0
7425 CPU_POWERPC_e200z1 = xxx,
7426 #endif
7427 #if 0 /* ? */
7428 CPU_POWERPC_e200z3 = 0x81120000,
7429 #endif
7430 CPU_POWERPC_e200z5 = 0x81000000,
7431 CPU_POWERPC_e200z6 = 0x81120000,
7432 /* MPC55xx microcontrollers */
7433 #define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
7434 #if 0
7435 #define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
7436 #define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
7437 #define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
7438 #define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
7439 #define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
7440 #define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
7441 #define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
7442 #define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
7443 #define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
7444 #define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
7445 #define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
7446 #define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
7447 #define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
7448 #define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
7449 #endif
7450 #if 0
7451 #define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
7452 #define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
7453 #endif
7454 #define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
7455 #define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
7456 #define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
7457 #define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
7458 #define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
7459 #define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
7460 /* e300 family */
7461 /* e300 cores */
7462 CPU_POWERPC_e300c1 = 0x00830010,
7463 CPU_POWERPC_e300c2 = 0x00840010,
7464 CPU_POWERPC_e300c3 = 0x00850010,
7465 CPU_POWERPC_e300c4 = 0x00860010,
7466 /* MPC83xx microcontrollers */
7467 #define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
7468 #define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
7469 #define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
7470 #define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
7471 #define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
7472 #define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
7473 /* e500 family */
7474 /* e500 cores */
7475 #define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
7476 CPU_POWERPC_e500v1_v10 = 0x80200010,
7477 CPU_POWERPC_e500v1_v20 = 0x80200020,
7478 CPU_POWERPC_e500v2_v10 = 0x80210010,
7479 CPU_POWERPC_e500v2_v11 = 0x80210011,
7480 CPU_POWERPC_e500v2_v20 = 0x80210020,
7481 CPU_POWERPC_e500v2_v21 = 0x80210021,
7482 CPU_POWERPC_e500v2_v22 = 0x80210022,
7483 CPU_POWERPC_e500v2_v30 = 0x80210030,
7484 CPU_POWERPC_e500mc = 0x80230020,
7485 CPU_POWERPC_e5500 = 0x80240020,
7486 /* MPC85xx microcontrollers */
7487 #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
7488 #define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
7489 #define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
7490 #define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
7491 #define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
7492 #define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
7493 #define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
7494 #define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
7495 #define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
7496 #define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
7497 #define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
7498 #define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
7499 #define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
7500 #define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
7501 #define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
7502 #define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
7503 #define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
7504 #define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
7505 #define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
7506 #define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
7507 #define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
7508 #define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
7509 #define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
7510 #define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
7511 #define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
7512 #define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
7513 #define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
7514 #define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
7515 #define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
7516 #define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
7517 #define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
7518 #define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
7519 #define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
7520 #define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
7521 #define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
7522 #define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
7523 #define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
7524 #define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
7525 #define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
7526 #define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
7527 #define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
7528 #define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
7529 #define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
7530 #define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
7531 #define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
7532 #define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
7533 #define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
7534 #define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
7535 #define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
7536 #define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
7537 #define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
7538 #define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
7539 #define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
7540 /* e600 family */
7541 /* e600 cores */
7542 CPU_POWERPC_e600 = 0x80040010,
7543 /* MPC86xx microcontrollers */
7544 #define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
7545 #define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
7546 #define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
7547 /* PowerPC 6xx cores */
7548 CPU_POWERPC_601_v0 = 0x00010001,
7549 CPU_POWERPC_601_v1 = 0x00010001,
7550 CPU_POWERPC_601_v2 = 0x00010002,
7551 CPU_POWERPC_602 = 0x00050100,
7552 CPU_POWERPC_603 = 0x00030100,
7553 CPU_POWERPC_603E_v11 = 0x00060101,
7554 CPU_POWERPC_603E_v12 = 0x00060102,
7555 CPU_POWERPC_603E_v13 = 0x00060103,
7556 CPU_POWERPC_603E_v14 = 0x00060104,
7557 CPU_POWERPC_603E_v22 = 0x00060202,
7558 CPU_POWERPC_603E_v3 = 0x00060300,
7559 CPU_POWERPC_603E_v4 = 0x00060400,
7560 CPU_POWERPC_603E_v41 = 0x00060401,
7561 CPU_POWERPC_603E7t = 0x00071201,
7562 CPU_POWERPC_603E7v = 0x00070100,
7563 CPU_POWERPC_603E7v1 = 0x00070101,
7564 CPU_POWERPC_603E7v2 = 0x00070201,
7565 CPU_POWERPC_603E7 = 0x00070200,
7566 CPU_POWERPC_603P = 0x00070000,
7567 /* XXX: missing 0x00040303 (604) */
7568 CPU_POWERPC_604 = 0x00040103,
7569 /* XXX: missing 0x00091203 */
7570 /* XXX: missing 0x00092110 */
7571 /* XXX: missing 0x00092120 */
7572 CPU_POWERPC_604E_v10 = 0x00090100,
7573 CPU_POWERPC_604E_v22 = 0x00090202,
7574 CPU_POWERPC_604E_v24 = 0x00090204,
7575 /* XXX: missing 0x000a0100 */
7576 /* XXX: missing 0x00093102 */
7577 CPU_POWERPC_604R = 0x000a0101,
7578 #if 0
7579 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
7580 #endif
7581 /* PowerPC 740/750 cores (aka G3) */
7582 /* XXX: missing 0x00084202 */
7583 CPU_POWERPC_7x0_v10 = 0x00080100,
7584 CPU_POWERPC_7x0_v20 = 0x00080200,
7585 CPU_POWERPC_7x0_v21 = 0x00080201,
7586 CPU_POWERPC_7x0_v22 = 0x00080202,
7587 CPU_POWERPC_7x0_v30 = 0x00080300,
7588 CPU_POWERPC_7x0_v31 = 0x00080301,
7589 CPU_POWERPC_740E = 0x00080100,
7590 CPU_POWERPC_750E = 0x00080200,
7591 CPU_POWERPC_7x0P = 0x10080000,
7592 /* XXX: missing 0x00087010 (CL ?) */
7593 CPU_POWERPC_750CL_v10 = 0x00087200,
7594 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
7595 CPU_POWERPC_750CX_v10 = 0x00082100,
7596 CPU_POWERPC_750CX_v20 = 0x00082200,
7597 CPU_POWERPC_750CX_v21 = 0x00082201,
7598 CPU_POWERPC_750CX_v22 = 0x00082202,
7599 CPU_POWERPC_750CXE_v21 = 0x00082211,
7600 CPU_POWERPC_750CXE_v22 = 0x00082212,
7601 CPU_POWERPC_750CXE_v23 = 0x00082213,
7602 CPU_POWERPC_750CXE_v24 = 0x00082214,
7603 CPU_POWERPC_750CXE_v24b = 0x00083214,
7604 CPU_POWERPC_750CXE_v30 = 0x00082310,
7605 CPU_POWERPC_750CXE_v31 = 0x00082311,
7606 CPU_POWERPC_750CXE_v31b = 0x00083311,
7607 CPU_POWERPC_750CXR = 0x00083410,
7608 CPU_POWERPC_750FL = 0x70000203,
7609 CPU_POWERPC_750FX_v10 = 0x70000100,
7610 CPU_POWERPC_750FX_v20 = 0x70000200,
7611 CPU_POWERPC_750FX_v21 = 0x70000201,
7612 CPU_POWERPC_750FX_v22 = 0x70000202,
7613 CPU_POWERPC_750FX_v23 = 0x70000203,
7614 CPU_POWERPC_750GL = 0x70020102,
7615 CPU_POWERPC_750GX_v10 = 0x70020100,
7616 CPU_POWERPC_750GX_v11 = 0x70020101,
7617 CPU_POWERPC_750GX_v12 = 0x70020102,
7618 CPU_POWERPC_750L_v20 = 0x00088200,
7619 CPU_POWERPC_750L_v21 = 0x00088201,
7620 CPU_POWERPC_750L_v22 = 0x00088202,
7621 CPU_POWERPC_750L_v30 = 0x00088300,
7622 CPU_POWERPC_750L_v32 = 0x00088302,
7623 /* PowerPC 745/755 cores */
7624 CPU_POWERPC_7x5_v10 = 0x00083100,
7625 CPU_POWERPC_7x5_v11 = 0x00083101,
7626 CPU_POWERPC_7x5_v20 = 0x00083200,
7627 CPU_POWERPC_7x5_v21 = 0x00083201,
7628 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
7629 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
7630 CPU_POWERPC_7x5_v24 = 0x00083204,
7631 CPU_POWERPC_7x5_v25 = 0x00083205,
7632 CPU_POWERPC_7x5_v26 = 0x00083206,
7633 CPU_POWERPC_7x5_v27 = 0x00083207,
7634 CPU_POWERPC_7x5_v28 = 0x00083208,
7635 #if 0
7636 CPU_POWERPC_7x5P = xxx,
7637 #endif
7638 /* PowerPC 74xx cores (aka G4) */
7639 /* XXX: missing 0x000C1101 */
7640 CPU_POWERPC_7400_v10 = 0x000C0100,
7641 CPU_POWERPC_7400_v11 = 0x000C0101,
7642 CPU_POWERPC_7400_v20 = 0x000C0200,
7643 CPU_POWERPC_7400_v21 = 0x000C0201,
7644 CPU_POWERPC_7400_v22 = 0x000C0202,
7645 CPU_POWERPC_7400_v26 = 0x000C0206,
7646 CPU_POWERPC_7400_v27 = 0x000C0207,
7647 CPU_POWERPC_7400_v28 = 0x000C0208,
7648 CPU_POWERPC_7400_v29 = 0x000C0209,
7649 CPU_POWERPC_7410_v10 = 0x800C1100,
7650 CPU_POWERPC_7410_v11 = 0x800C1101,
7651 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
7652 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
7653 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
7654 CPU_POWERPC_7448_v10 = 0x80040100,
7655 CPU_POWERPC_7448_v11 = 0x80040101,
7656 CPU_POWERPC_7448_v20 = 0x80040200,
7657 CPU_POWERPC_7448_v21 = 0x80040201,
7658 CPU_POWERPC_7450_v10 = 0x80000100,
7659 CPU_POWERPC_7450_v11 = 0x80000101,
7660 CPU_POWERPC_7450_v12 = 0x80000102,
7661 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
7662 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
7663 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
7664 /* XXX: this entry might be a bug in some documentation */
7665 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
7666 CPU_POWERPC_74x5_v10 = 0x80010100,
7667 /* XXX: missing 0x80010200 */
7668 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
7669 CPU_POWERPC_74x5_v32 = 0x80010302,
7670 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
7671 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
7672 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
7673 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
7674 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
7675 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
7676 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
7677 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
7678 /* 64 bits PowerPC */
7679 #if defined(TARGET_PPC64)
7680 CPU_POWERPC_620 = 0x00140000,
7681 CPU_POWERPC_630 = 0x00400000,
7682 CPU_POWERPC_631 = 0x00410104,
7683 CPU_POWERPC_POWER4 = 0x00350000,
7684 CPU_POWERPC_POWER4P = 0x00380000,
7685 /* XXX: missing 0x003A0201 */
7686 CPU_POWERPC_POWER5 = 0x003A0203,
7687 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
7688 CPU_POWERPC_POWER5P = 0x003B0000,
7689 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
7690 CPU_POWERPC_POWER6 = 0x003E0000,
7691 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
7692 CPU_POWERPC_POWER6A = 0x0F000002,
7693 CPU_POWERPC_POWER7_v20 = 0x003F0200,
7694 CPU_POWERPC_POWER7_v21 = 0x003F0201,
7695 CPU_POWERPC_POWER7_v23 = 0x003F0203,
7696 CPU_POWERPC_970 = 0x00390202,
7697 CPU_POWERPC_970FX_v10 = 0x00391100,
7698 CPU_POWERPC_970FX_v20 = 0x003C0200,
7699 CPU_POWERPC_970FX_v21 = 0x003C0201,
7700 CPU_POWERPC_970FX_v30 = 0x003C0300,
7701 CPU_POWERPC_970FX_v31 = 0x003C0301,
7702 CPU_POWERPC_970GX = 0x00450000,
7703 CPU_POWERPC_970MP_v10 = 0x00440100,
7704 CPU_POWERPC_970MP_v11 = 0x00440101,
7705 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
7706 CPU_POWERPC_CELL_v10 = 0x00700100,
7707 CPU_POWERPC_CELL_v20 = 0x00700400,
7708 CPU_POWERPC_CELL_v30 = 0x00700500,
7709 CPU_POWERPC_CELL_v31 = 0x00700501,
7710 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
7711 CPU_POWERPC_RS64 = 0x00330000,
7712 CPU_POWERPC_RS64II = 0x00340000,
7713 CPU_POWERPC_RS64III = 0x00360000,
7714 CPU_POWERPC_RS64IV = 0x00370000,
7715 #endif /* defined(TARGET_PPC64) */
7716 /* Original POWER */
7717 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7718 * POWER2 (RIOS2) & RSC2 (P2SC) here
7719 */
7720 #if 0
7721 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
7722 #endif
7723 #if 0
7724 CPU_POWER2 = xxx, /* 0x40000 ? */
7725 #endif
7726 /* PA Semi core */
7727 CPU_POWERPC_PA6T = 0x00900000,
7728 };
7729
7730 /* System version register (used on MPC 8xxx) */
7731 enum {
7732 POWERPC_SVR_NONE = 0x00000000,
7733 POWERPC_SVR_5200_v10 = 0x80110010,
7734 POWERPC_SVR_5200_v11 = 0x80110011,
7735 POWERPC_SVR_5200_v12 = 0x80110012,
7736 POWERPC_SVR_5200B_v20 = 0x80110020,
7737 POWERPC_SVR_5200B_v21 = 0x80110021,
7738 #define POWERPC_SVR_55xx POWERPC_SVR_5567
7739 #if 0
7740 POWERPC_SVR_5533 = xxx,
7741 #endif
7742 #if 0
7743 POWERPC_SVR_5534 = xxx,
7744 #endif
7745 #if 0
7746 POWERPC_SVR_5553 = xxx,
7747 #endif
7748 #if 0
7749 POWERPC_SVR_5554 = xxx,
7750 #endif
7751 #if 0
7752 POWERPC_SVR_5561 = xxx,
7753 #endif
7754 #if 0
7755 POWERPC_SVR_5565 = xxx,
7756 #endif
7757 #if 0
7758 POWERPC_SVR_5566 = xxx,
7759 #endif
7760 #if 0
7761 POWERPC_SVR_5567 = xxx,
7762 #endif
7763 #if 0
7764 POWERPC_SVR_8313 = xxx,
7765 #endif
7766 #if 0
7767 POWERPC_SVR_8313E = xxx,
7768 #endif
7769 #if 0
7770 POWERPC_SVR_8314 = xxx,
7771 #endif
7772 #if 0
7773 POWERPC_SVR_8314E = xxx,
7774 #endif
7775 #if 0
7776 POWERPC_SVR_8315 = xxx,
7777 #endif
7778 #if 0
7779 POWERPC_SVR_8315E = xxx,
7780 #endif
7781 #if 0
7782 POWERPC_SVR_8321 = xxx,
7783 #endif
7784 #if 0
7785 POWERPC_SVR_8321E = xxx,
7786 #endif
7787 #if 0
7788 POWERPC_SVR_8323 = xxx,
7789 #endif
7790 #if 0
7791 POWERPC_SVR_8323E = xxx,
7792 #endif
7793 POWERPC_SVR_8343 = 0x80570010,
7794 POWERPC_SVR_8343A = 0x80570030,
7795 POWERPC_SVR_8343E = 0x80560010,
7796 POWERPC_SVR_8343EA = 0x80560030,
7797 POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
7798 POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
7799 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7800 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
7801 POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
7802 POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
7803 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7804 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7805 POWERPC_SVR_8349 = 0x80510010,
7806 POWERPC_SVR_8349A = 0x80510030,
7807 POWERPC_SVR_8349E = 0x80500010,
7808 POWERPC_SVR_8349EA = 0x80500030,
7809 #if 0
7810 POWERPC_SVR_8358E = xxx,
7811 #endif
7812 #if 0
7813 POWERPC_SVR_8360E = xxx,
7814 #endif
7815 #define POWERPC_SVR_E500 0x40000000
7816 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7817 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7818 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7819 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7820 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7821 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7822 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7823 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7824 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7825 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7826 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7827 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7828 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7829 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7830 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7831 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7832 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7833 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7834 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7835 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7836 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7837 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7838 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7839 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7840 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7841 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7842 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7843 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7844 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7845 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7846 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7847 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7848 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7849 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7850 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7851 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7852 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7853 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7854 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7855 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7856 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7857 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7858 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7859 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7860 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7861 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7862 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7863 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7864 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7865 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7866 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7867 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7868 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7869 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7870 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7871 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
7872 #if 0
7873 POWERPC_SVR_8610 = xxx,
7874 #endif
7875 POWERPC_SVR_8641 = 0x80900021,
7876 POWERPC_SVR_8641D = 0x80900121,
7877 };
7878
7879 /*****************************************************************************/
7880 /* PowerPC CPU definitions */
7881 #define POWERPC_DEF_PREFIX(pvr, svr, type) \
7882 glue(glue(glue(glue(pvr, _), svr), _), type)
7883 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
7884 static void \
7885 glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init) \
7886 (ObjectClass *oc, void *data) \
7887 { \
7888 DeviceClass *dc = DEVICE_CLASS(oc); \
7889 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); \
7890 \
7891 pcc->pvr = _pvr; \
7892 pcc->svr = _svr; \
7893 dc->desc = NULL; \
7894 } \
7895 \
7896 static const TypeInfo \
7897 glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_type_info) = { \
7898 .name = _name "-" TYPE_POWERPC_CPU, \
7899 .parent = stringify(_type) "-family-" TYPE_POWERPC_CPU, \
7900 .class_init = \
7901 glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init), \
7902 }; \
7903 \
7904 static void \
7905 glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_register_types)(void) \
7906 { \
7907 type_register_static( \
7908 &glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_type_info)); \
7909 } \
7910 \
7911 type_init( \
7912 glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_register_types))
7913
7914 #define POWERPC_DEF(_name, _pvr, _type) \
7915 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
7916
7917 /* Embedded PowerPC */
7918 /* PowerPC 401 family */
7919 /* Generic PowerPC 401 */
7920 POWERPC_DEF("401", CPU_POWERPC_401, 401)
7921 /* PowerPC 401 cores */
7922 /* PowerPC 401A1 */
7923 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401)
7924 /* PowerPC 401B2 */
7925 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2)
7926 #if defined (TODO)
7927 /* PowerPC 401B3 */
7928 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3)
7929 #endif
7930 /* PowerPC 401C2 */
7931 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2)
7932 /* PowerPC 401D2 */
7933 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2)
7934 /* PowerPC 401E2 */
7935 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2)
7936 /* PowerPC 401F2 */
7937 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2)
7938 /* PowerPC 401G2 */
7939 /* XXX: to be checked */
7940 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2)
7941 /* PowerPC 401 microcontrolers */
7942 #if defined (TODO)
7943 /* PowerPC 401GF */
7944 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401)
7945 #endif
7946 /* IOP480 (401 microcontroler) */
7947 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480)
7948 /* IBM Processor for Network Resources */
7949 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401)
7950 #if defined (TODO)
7951 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401)
7952 #endif
7953 /* PowerPC 403 family */
7954 /* PowerPC 403 microcontrolers */
7955 /* PowerPC 403 GA */
7956 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403)
7957 /* PowerPC 403 GB */
7958 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403)
7959 /* PowerPC 403 GC */
7960 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403)
7961 /* PowerPC 403 GCX */
7962 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX)
7963 #if defined (TODO)
7964 /* PowerPC 403 GP */
7965 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403)
7966 #endif
7967 /* PowerPC 405 family */
7968 /* PowerPC 405 cores */
7969 #if defined (TODO)
7970 /* PowerPC 405 A3 */
7971 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405)
7972 #endif
7973 #if defined (TODO)
7974 /* PowerPC 405 A4 */
7975 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405)
7976 #endif
7977 #if defined (TODO)
7978 /* PowerPC 405 B3 */
7979 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405)
7980 #endif
7981 #if defined (TODO)
7982 /* PowerPC 405 B4 */
7983 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405)
7984 #endif
7985 #if defined (TODO)
7986 /* PowerPC 405 C3 */
7987 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405)
7988 #endif
7989 #if defined (TODO)
7990 /* PowerPC 405 C4 */
7991 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405)
7992 #endif
7993 /* PowerPC 405 D2 */
7994 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405)
7995 #if defined (TODO)
7996 /* PowerPC 405 D3 */
7997 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405)
7998 #endif
7999 /* PowerPC 405 D4 */
8000 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405)
8001 #if defined (TODO)
8002 /* PowerPC 405 D5 */
8003 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405)
8004 #endif
8005 #if defined (TODO)
8006 /* PowerPC 405 E4 */
8007 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405)
8008 #endif
8009 #if defined (TODO)
8010 /* PowerPC 405 F4 */
8011 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405)
8012 #endif
8013 #if defined (TODO)
8014 /* PowerPC 405 F5 */
8015 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405)
8016 #endif
8017 #if defined (TODO)
8018 /* PowerPC 405 F6 */
8019 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405)
8020 #endif
8021 /* PowerPC 405 microcontrolers */
8022 /* PowerPC 405 CRa */
8023 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405)
8024 /* PowerPC 405 CRb */
8025 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405)
8026 /* PowerPC 405 CRc */
8027 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405)
8028 /* PowerPC 405 EP */
8029 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405)
8030 #if defined(TODO)
8031 /* PowerPC 405 EXr */
8032 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405)
8033 #endif
8034 /* PowerPC 405 EZ */
8035 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405)
8036 #if defined(TODO)
8037 /* PowerPC 405 FX */
8038 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405)
8039 #endif
8040 /* PowerPC 405 GPa */
8041 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405)
8042 /* PowerPC 405 GPb */
8043 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405)
8044 /* PowerPC 405 GPc */
8045 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405)
8046 /* PowerPC 405 GPd */
8047 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405)
8048 /* PowerPC 405 GPR */
8049 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405)
8050 #if defined(TODO)
8051 /* PowerPC 405 H */
8052 POWERPC_DEF("405H", CPU_POWERPC_405H, 405)
8053 #endif
8054 #if defined(TODO)
8055 /* PowerPC 405 L */
8056 POWERPC_DEF("405L", CPU_POWERPC_405L, 405)
8057 #endif
8058 /* PowerPC 405 LP */
8059 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405)
8060 #if defined(TODO)
8061 /* PowerPC 405 PM */
8062 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405)
8063 #endif
8064 #if defined(TODO)
8065 /* PowerPC 405 PS */
8066 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405)
8067 #endif
8068 #if defined(TODO)
8069 /* PowerPC 405 S */
8070 POWERPC_DEF("405S", CPU_POWERPC_405S, 405)
8071 #endif
8072 /* Npe405 H */
8073 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405)
8074 /* Npe405 H2 */
8075 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405)
8076 /* Npe405 L */
8077 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405)
8078 /* Npe4GS3 */
8079 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405)
8080 #if defined (TODO)
8081 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405)
8082 #endif
8083 #if defined (TODO)
8084 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405)
8085 #endif
8086 #if defined (TODO)
8087 /* PowerPC LC77700 (Sanyo) */
8088 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405)
8089 #endif
8090 /* PowerPC 401/403/405 based set-top-box microcontrolers */
8091 #if defined (TODO)
8092 /* STB010000 */
8093 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2)
8094 #endif
8095 #if defined (TODO)
8096 /* STB01010 */
8097 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2)
8098 #endif
8099 #if defined (TODO)
8100 /* STB0210 */
8101 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3)
8102 #endif
8103 /* STB03xx */
8104 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405)
8105 #if defined (TODO)
8106 /* STB043x */
8107 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405)
8108 #endif
8109 #if defined (TODO)
8110 /* STB045x */
8111 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405)
8112 #endif
8113 /* STB04xx */
8114 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405)
8115 /* STB25xx */
8116 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405)
8117 #if defined (TODO)
8118 /* STB130 */
8119 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405)
8120 #endif
8121 /* Xilinx PowerPC 405 cores */
8122 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405)
8123 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405)
8124 #if defined (TODO)
8125 /* Zarlink ZL10310 */
8126 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405)
8127 #endif
8128 #if defined (TODO)
8129 /* Zarlink ZL10311 */
8130 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405)
8131 #endif
8132 #if defined (TODO)
8133 /* Zarlink ZL10320 */
8134 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405)
8135 #endif
8136 #if defined (TODO)
8137 /* Zarlink ZL10321 */
8138 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405)
8139 #endif
8140 /* PowerPC 440 family */
8141 #if defined(TODO_USER_ONLY)
8142 /* Generic PowerPC 440 */
8143 POWERPC_DEF("440", CPU_POWERPC_440, 440GP)
8144 #endif
8145 /* PowerPC 440 cores */
8146 #if defined (TODO)
8147 /* PowerPC 440 A4 */
8148 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4)
8149 #endif
8150 /* PowerPC 440 Xilinx 5 */
8151 POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5)
8152 #if defined (TODO)
8153 /* PowerPC 440 A5 */
8154 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5)
8155 #endif
8156 #if defined (TODO)
8157 /* PowerPC 440 B4 */
8158 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4)
8159 #endif
8160 #if defined (TODO)
8161 /* PowerPC 440 G4 */
8162 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4)
8163 #endif
8164 #if defined (TODO)
8165 /* PowerPC 440 F5 */
8166 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5)
8167 #endif
8168 #if defined (TODO)
8169 /* PowerPC 440 G5 */
8170 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5)
8171 #endif
8172 #if defined (TODO)
8173 /* PowerPC 440H4 */
8174 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4)
8175 #endif
8176 #if defined (TODO)
8177 /* PowerPC 440H6 */
8178 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5)
8179 #endif
8180 /* PowerPC 440 microcontrolers */
8181 /* PowerPC 440 EPa */
8182 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP)
8183 /* PowerPC 440 EPb */
8184 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP)
8185 /* PowerPC 440 EPX */
8186 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP)
8187 #if defined(TODO_USER_ONLY)
8188 /* PowerPC 440 GPb */
8189 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP)
8190 #endif
8191 #if defined(TODO_USER_ONLY)
8192 /* PowerPC 440 GPc */
8193 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP)
8194 #endif
8195 #if defined(TODO_USER_ONLY)
8196 /* PowerPC 440 GRa */
8197 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5)
8198 #endif
8199 #if defined(TODO_USER_ONLY)
8200 /* PowerPC 440 GRX */
8201 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5)
8202 #endif
8203 #if defined(TODO_USER_ONLY)
8204 /* PowerPC 440 GXa */
8205 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP)
8206 #endif
8207 #if defined(TODO_USER_ONLY)
8208 /* PowerPC 440 GXb */
8209 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP)
8210 #endif
8211 #if defined(TODO_USER_ONLY)
8212 /* PowerPC 440 GXc */
8213 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP)
8214 #endif
8215 #if defined(TODO_USER_ONLY)
8216 /* PowerPC 440 GXf */
8217 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP)
8218 #endif
8219 #if defined(TODO)
8220 /* PowerPC 440 S */
8221 POWERPC_DEF("440S", CPU_POWERPC_440S, 440)
8222 #endif
8223 #if defined(TODO_USER_ONLY)
8224 /* PowerPC 440 SP */
8225 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP)
8226 #endif
8227 #if defined(TODO_USER_ONLY)
8228 /* PowerPC 440 SP2 */
8229 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP)
8230 #endif
8231 #if defined(TODO_USER_ONLY)
8232 /* PowerPC 440 SPE */
8233 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP)
8234 #endif
8235 /* PowerPC 460 family */
8236 #if defined (TODO)
8237 /* Generic PowerPC 464 */
8238 POWERPC_DEF("464", CPU_POWERPC_464, 460)
8239 #endif
8240 /* PowerPC 464 microcontrolers */
8241 #if defined (TODO)
8242 /* PowerPC 464H90 */
8243 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460)
8244 #endif
8245 #if defined (TODO)
8246 /* PowerPC 464H90F */
8247 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F)
8248 #endif
8249 /* Freescale embedded PowerPC cores */
8250 /* MPC5xx family (aka RCPU) */
8251 #if defined(TODO_USER_ONLY)
8252 /* Generic MPC5xx core */
8253 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx)
8254 #endif
8255 /* MPC8xx family (aka PowerQUICC) */
8256 #if defined(TODO_USER_ONLY)
8257 /* Generic MPC8xx core */
8258 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx)
8259 #endif
8260 /* MPC82xx family (aka PowerQUICC-II) */
8261 /* PowerPC G2 core */
8262 POWERPC_DEF("G2", CPU_POWERPC_G2, G2)
8263 /* PowerPC G2 H4 core */
8264 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2)
8265 /* PowerPC G2 GP core */
8266 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2)
8267 /* PowerPC G2 LS core */
8268 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2)
8269 /* PowerPC G2 HiP3 core */
8270 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2)
8271 /* PowerPC G2 HiP4 core */
8272 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2)
8273 /* PowerPC MPC603 core */
8274 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E)
8275 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
8276 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE)
8277 /* PowerPC G2LE GP core */
8278 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE)
8279 /* PowerPC G2LE LS core */
8280 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE)
8281 /* PowerPC G2LE GP1 core */
8282 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE)
8283 /* PowerPC G2LE GP3 core */
8284 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp3, G2LE)
8285 /* PowerPC G2 microcontrollers */
8286 #if defined(TODO)
8287 /* MPC5121 */
8288 POWERPC_DEF_SVR("MPC5121",
8289 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE)
8290 #endif
8291 /* MPC5200 v1.0 */
8292 POWERPC_DEF_SVR("MPC5200_v10",
8293 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE)
8294 /* MPC5200 v1.1 */
8295 POWERPC_DEF_SVR("MPC5200_v11",
8296 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE)
8297 /* MPC5200 v1.2 */
8298 POWERPC_DEF_SVR("MPC5200_v12",
8299 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE)
8300 /* MPC5200B v2.0 */
8301 POWERPC_DEF_SVR("MPC5200B_v20",
8302 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE)
8303 /* MPC5200B v2.1 */
8304 POWERPC_DEF_SVR("MPC5200B_v21",
8305 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE)
8306 /* e200 family */
8307 /* Generic MPC55xx core */
8308 #if defined (TODO)
8309 POWERPC_DEF_SVR("MPC55xx",
8310 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200)
8311 #endif
8312 #if defined (TODO)
8313 /* PowerPC e200z0 core */
8314 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200)
8315 #endif
8316 #if defined (TODO)
8317 /* PowerPC e200z1 core */
8318 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200)
8319 #endif
8320 #if defined (TODO)
8321 /* PowerPC e200z3 core */
8322 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200)
8323 #endif
8324 /* PowerPC e200z5 core */
8325 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200)
8326 /* PowerPC e200z6 core */
8327 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200)
8328 /* PowerPC e200 microcontrollers */
8329 #if defined (TODO)
8330 /* MPC5514E */
8331 POWERPC_DEF_SVR("MPC5514E",
8332 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200)
8333 #endif
8334 #if defined (TODO)
8335 /* MPC5514E v0 */
8336 POWERPC_DEF_SVR("MPC5514E_v0",
8337 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200)
8338 #endif
8339 #if defined (TODO)
8340 /* MPC5514E v1 */
8341 POWERPC_DEF_SVR("MPC5514E_v1",
8342 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200)
8343 #endif
8344 #if defined (TODO)
8345 /* MPC5514G */
8346 POWERPC_DEF_SVR("MPC5514G",
8347 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200)
8348 #endif
8349 #if defined (TODO)
8350 /* MPC5514G v0 */
8351 POWERPC_DEF_SVR("MPC5514G_v0",
8352 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200)
8353 #endif
8354 #if defined (TODO)
8355 /* MPC5514G v1 */
8356 POWERPC_DEF_SVR("MPC5514G_v1",
8357 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200)
8358 #endif
8359 #if defined (TODO)
8360 /* MPC5515S */
8361 POWERPC_DEF_SVR("MPC5515S",
8362 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200)
8363 #endif
8364 #if defined (TODO)
8365 /* MPC5516E */
8366 POWERPC_DEF_SVR("MPC5516E",
8367 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200)
8368 #endif
8369 #if defined (TODO)
8370 /* MPC5516E v0 */
8371 POWERPC_DEF_SVR("MPC5516E_v0",
8372 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200)
8373 #endif
8374 #if defined (TODO)
8375 /* MPC5516E v1 */
8376 POWERPC_DEF_SVR("MPC5516E_v1",
8377 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200)
8378 #endif
8379 #if defined (TODO)
8380 /* MPC5516G */
8381 POWERPC_DEF_SVR("MPC5516G",
8382 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200)
8383 #endif
8384 #if defined (TODO)
8385 /* MPC5516G v0 */
8386 POWERPC_DEF_SVR("MPC5516G_v0",
8387 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200)
8388 #endif
8389 #if defined (TODO)
8390 /* MPC5516G v1 */
8391 POWERPC_DEF_SVR("MPC5516G_v1",
8392 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200)
8393 #endif
8394 #if defined (TODO)
8395 /* MPC5516S */
8396 POWERPC_DEF_SVR("MPC5516S",
8397 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200)
8398 #endif
8399 #if defined (TODO)
8400 /* MPC5533 */
8401 POWERPC_DEF_SVR("MPC5533",
8402 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200)
8403 #endif
8404 #if defined (TODO)
8405 /* MPC5534 */
8406 POWERPC_DEF_SVR("MPC5534",
8407 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200)
8408 #endif
8409 #if defined (TODO)
8410 /* MPC5553 */
8411 POWERPC_DEF_SVR("MPC5553",
8412 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200)
8413 #endif
8414 #if defined (TODO)
8415 /* MPC5554 */
8416 POWERPC_DEF_SVR("MPC5554",
8417 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200)
8418 #endif
8419 #if defined (TODO)
8420 /* MPC5561 */
8421 POWERPC_DEF_SVR("MPC5561",
8422 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200)
8423 #endif
8424 #if defined (TODO)
8425 /* MPC5565 */
8426 POWERPC_DEF_SVR("MPC5565",
8427 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200)
8428 #endif
8429 #if defined (TODO)
8430 /* MPC5566 */
8431 POWERPC_DEF_SVR("MPC5566",
8432 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200)
8433 #endif
8434 #if defined (TODO)
8435 /* MPC5567 */
8436 POWERPC_DEF_SVR("MPC5567",
8437 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200)
8438 #endif
8439 /* e300 family */
8440 /* PowerPC e300c1 core */
8441 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300)
8442 /* PowerPC e300c2 core */
8443 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300)
8444 /* PowerPC e300c3 core */
8445 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300)
8446 /* PowerPC e300c4 core */
8447 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300)
8448 /* PowerPC e300 microcontrollers */
8449 #if defined (TODO)
8450 /* MPC8313 */
8451 POWERPC_DEF_SVR("MPC8313",
8452 CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300)
8453 #endif
8454 #if defined (TODO)
8455 /* MPC8313E */
8456 POWERPC_DEF_SVR("MPC8313E",
8457 CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300)
8458 #endif
8459 #if defined (TODO)
8460 /* MPC8314 */
8461 POWERPC_DEF_SVR("MPC8314",
8462 CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300)
8463 #endif
8464 #if defined (TODO)
8465 /* MPC8314E */
8466 POWERPC_DEF_SVR("MPC8314E",
8467 CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300)
8468 #endif
8469 #if defined (TODO)
8470 /* MPC8315 */
8471 POWERPC_DEF_SVR("MPC8315",
8472 CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300)
8473 #endif
8474 #if defined (TODO)
8475 /* MPC8315E */
8476 POWERPC_DEF_SVR("MPC8315E",
8477 CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300)
8478 #endif
8479 #if defined (TODO)
8480 /* MPC8321 */
8481 POWERPC_DEF_SVR("MPC8321",
8482 CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300)
8483 #endif
8484 #if defined (TODO)
8485 /* MPC8321E */
8486 POWERPC_DEF_SVR("MPC8321E",
8487 CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300)
8488 #endif
8489 #if defined (TODO)
8490 /* MPC8323 */
8491 POWERPC_DEF_SVR("MPC8323",
8492 CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300)
8493 #endif
8494 #if defined (TODO)
8495 /* MPC8323E */
8496 POWERPC_DEF_SVR("MPC8323E",
8497 CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300)
8498 #endif
8499 /* MPC8343 */
8500 POWERPC_DEF_SVR("MPC8343",
8501 CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300)
8502 /* MPC8343A */
8503 POWERPC_DEF_SVR("MPC8343A",
8504 CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300)
8505 /* MPC8343E */
8506 POWERPC_DEF_SVR("MPC8343E",
8507 CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300)
8508 /* MPC8343EA */
8509 POWERPC_DEF_SVR("MPC8343EA",
8510 CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300)
8511 /* MPC8347T */
8512 POWERPC_DEF_SVR("MPC8347T",
8513 CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300)
8514 /* MPC8347P */
8515 POWERPC_DEF_SVR("MPC8347P",
8516 CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300)
8517 /* MPC8347AT */
8518 POWERPC_DEF_SVR("MPC8347AT",
8519 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300)
8520 /* MPC8347AP */
8521 POWERPC_DEF_SVR("MPC8347AP",
8522 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300)
8523 /* MPC8347ET */
8524 POWERPC_DEF_SVR("MPC8347ET",
8525 CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300)
8526 /* MPC8343EP */
8527 POWERPC_DEF_SVR("MPC8347EP",
8528 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300)
8529 /* MPC8347EAT */
8530 POWERPC_DEF_SVR("MPC8347EAT",
8531 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300)
8532 /* MPC8343EAP */
8533 POWERPC_DEF_SVR("MPC8347EAP",
8534 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300)
8535 /* MPC8349 */
8536 POWERPC_DEF_SVR("MPC8349",
8537 CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300)
8538 /* MPC8349A */
8539 POWERPC_DEF_SVR("MPC8349A",
8540 CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300)
8541 /* MPC8349E */
8542 POWERPC_DEF_SVR("MPC8349E",
8543 CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300)
8544 /* MPC8349EA */
8545 POWERPC_DEF_SVR("MPC8349EA",
8546 CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300)
8547 #if defined (TODO)
8548 /* MPC8358E */
8549 POWERPC_DEF_SVR("MPC8358E",
8550 CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300)
8551 #endif
8552 #if defined (TODO)
8553 /* MPC8360E */
8554 POWERPC_DEF_SVR("MPC8360E",
8555 CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300)
8556 #endif
8557 /* MPC8377 */
8558 POWERPC_DEF_SVR("MPC8377",
8559 CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300)
8560 /* MPC8377E */
8561 POWERPC_DEF_SVR("MPC8377E",
8562 CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300)
8563 /* MPC8378 */
8564 POWERPC_DEF_SVR("MPC8378",
8565 CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300)
8566 /* MPC8378E */
8567 POWERPC_DEF_SVR("MPC8378E",
8568 CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300)
8569 /* MPC8379 */
8570 POWERPC_DEF_SVR("MPC8379",
8571 CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300)
8572 /* MPC8379E */
8573 POWERPC_DEF_SVR("MPC8379E",
8574 CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300)
8575 /* e500 family */
8576 /* PowerPC e500 v1.0 core */
8577 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1)
8578 /* PowerPC e500 v2.0 core */
8579 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1)
8580 /* PowerPC e500v2 v1.0 core */
8581 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2)
8582 /* PowerPC e500v2 v2.0 core */
8583 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2)
8584 /* PowerPC e500v2 v2.1 core */
8585 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2)
8586 /* PowerPC e500v2 v2.2 core */
8587 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2)
8588 /* PowerPC e500v2 v3.0 core */
8589 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2)
8590 POWERPC_DEF_SVR("e500mc", CPU_POWERPC_e500mc, POWERPC_SVR_E500, e500mc)
8591 #ifdef TARGET_PPC64
8592 POWERPC_DEF_SVR("e5500", CPU_POWERPC_e5500, POWERPC_SVR_E500, e5500)
8593 #endif
8594 /* PowerPC e500 microcontrollers */
8595 /* MPC8533 v1.0 */
8596 POWERPC_DEF_SVR("MPC8533_v10",
8597 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2)
8598 /* MPC8533 v1.1 */
8599 POWERPC_DEF_SVR("MPC8533_v11",
8600 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2)
8601 /* MPC8533E v1.0 */
8602 POWERPC_DEF_SVR("MPC8533E_v10",
8603 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2)
8604 POWERPC_DEF_SVR("MPC8533E_v11",
8605 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2)
8606 /* MPC8540 v1.0 */
8607 POWERPC_DEF_SVR("MPC8540_v10",
8608 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1)
8609 /* MPC8540 v2.0 */
8610 POWERPC_DEF_SVR("MPC8540_v20",
8611 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1)
8612 /* MPC8540 v2.1 */
8613 POWERPC_DEF_SVR("MPC8540_v21",
8614 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1)
8615 /* MPC8541 v1.0 */
8616 POWERPC_DEF_SVR("MPC8541_v10",
8617 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1)
8618 /* MPC8541 v1.1 */
8619 POWERPC_DEF_SVR("MPC8541_v11",
8620 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1)
8621 /* MPC8541E v1.0 */
8622 POWERPC_DEF_SVR("MPC8541E_v10",
8623 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1)
8624 /* MPC8541E v1.1 */
8625 POWERPC_DEF_SVR("MPC8541E_v11",
8626 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1)
8627 /* MPC8543 v1.0 */
8628 POWERPC_DEF_SVR("MPC8543_v10",
8629 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2)
8630 /* MPC8543 v1.1 */
8631 POWERPC_DEF_SVR("MPC8543_v11",
8632 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2)
8633 /* MPC8543 v2.0 */
8634 POWERPC_DEF_SVR("MPC8543_v20",
8635 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2)
8636 /* MPC8543 v2.1 */
8637 POWERPC_DEF_SVR("MPC8543_v21",
8638 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2)
8639 /* MPC8543E v1.0 */
8640 POWERPC_DEF_SVR("MPC8543E_v10",
8641 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2)
8642 /* MPC8543E v1.1 */
8643 POWERPC_DEF_SVR("MPC8543E_v11",
8644 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2)
8645 /* MPC8543E v2.0 */
8646 POWERPC_DEF_SVR("MPC8543E_v20",
8647 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2)
8648 /* MPC8543E v2.1 */
8649 POWERPC_DEF_SVR("MPC8543E_v21",
8650 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2)
8651 /* MPC8544 v1.0 */
8652 POWERPC_DEF_SVR("MPC8544_v10",
8653 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2)
8654 /* MPC8544 v1.1 */
8655 POWERPC_DEF_SVR("MPC8544_v11",
8656 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2)
8657 /* MPC8544E v1.0 */
8658 POWERPC_DEF_SVR("MPC8544E_v10",
8659 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2)
8660 /* MPC8544E v1.1 */
8661 POWERPC_DEF_SVR("MPC8544E_v11",
8662 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2)
8663 /* MPC8545 v2.0 */
8664 POWERPC_DEF_SVR("MPC8545_v20",
8665 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2)
8666 /* MPC8545 v2.1 */
8667 POWERPC_DEF_SVR("MPC8545_v21",
8668 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2)
8669 /* MPC8545E v2.0 */
8670 POWERPC_DEF_SVR("MPC8545E_v20",
8671 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2)
8672 /* MPC8545E v2.1 */
8673 POWERPC_DEF_SVR("MPC8545E_v21",
8674 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2)
8675 /* MPC8547E v2.0 */
8676 POWERPC_DEF_SVR("MPC8547E_v20",
8677 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2)
8678 /* MPC8547E v2.1 */
8679 POWERPC_DEF_SVR("MPC8547E_v21",
8680 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2)
8681 /* MPC8548 v1.0 */
8682 POWERPC_DEF_SVR("MPC8548_v10",
8683 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2)
8684 /* MPC8548 v1.1 */
8685 POWERPC_DEF_SVR("MPC8548_v11",
8686 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2)
8687 /* MPC8548 v2.0 */
8688 POWERPC_DEF_SVR("MPC8548_v20",
8689 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2)
8690 /* MPC8548 v2.1 */
8691 POWERPC_DEF_SVR("MPC8548_v21",
8692 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2)
8693 /* MPC8548E v1.0 */
8694 POWERPC_DEF_SVR("MPC8548E_v10",
8695 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2)
8696 /* MPC8548E v1.1 */
8697 POWERPC_DEF_SVR("MPC8548E_v11",
8698 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2)
8699 /* MPC8548E v2.0 */
8700 POWERPC_DEF_SVR("MPC8548E_v20",
8701 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2)
8702 /* MPC8548E v2.1 */
8703 POWERPC_DEF_SVR("MPC8548E_v21",
8704 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2)
8705 /* MPC8555 v1.0 */
8706 POWERPC_DEF_SVR("MPC8555_v10",
8707 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2)
8708 /* MPC8555 v1.1 */
8709 POWERPC_DEF_SVR("MPC8555_v11",
8710 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2)
8711 /* MPC8555E v1.0 */
8712 POWERPC_DEF_SVR("MPC8555E_v10",
8713 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2)
8714 /* MPC8555E v1.1 */
8715 POWERPC_DEF_SVR("MPC8555E_v11",
8716 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2)
8717 /* MPC8560 v1.0 */
8718 POWERPC_DEF_SVR("MPC8560_v10",
8719 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2)
8720 /* MPC8560 v2.0 */
8721 POWERPC_DEF_SVR("MPC8560_v20",
8722 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2)
8723 /* MPC8560 v2.1 */
8724 POWERPC_DEF_SVR("MPC8560_v21",
8725 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2)
8726 /* MPC8567 */
8727 POWERPC_DEF_SVR("MPC8567",
8728 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2)
8729 /* MPC8567E */
8730 POWERPC_DEF_SVR("MPC8567E",
8731 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2)
8732 /* MPC8568 */
8733 POWERPC_DEF_SVR("MPC8568",
8734 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2)
8735 /* MPC8568E */
8736 POWERPC_DEF_SVR("MPC8568E",
8737 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2)
8738 /* MPC8572 */
8739 POWERPC_DEF_SVR("MPC8572",
8740 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2)
8741 /* MPC8572E */
8742 POWERPC_DEF_SVR("MPC8572E",
8743 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2)
8744 /* e600 family */
8745 /* PowerPC e600 core */
8746 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400)
8747 /* PowerPC e600 microcontrollers */
8748 #if defined (TODO)
8749 /* MPC8610 */
8750 POWERPC_DEF_SVR("MPC8610",
8751 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400)
8752 #endif
8753 /* MPC8641 */
8754 POWERPC_DEF_SVR("MPC8641",
8755 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400)
8756 /* MPC8641D */
8757 POWERPC_DEF_SVR("MPC8641D",
8758 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400)
8759 /* 32 bits "classic" PowerPC */
8760 /* PowerPC 6xx family */
8761 /* PowerPC 601v0 */
8762 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601)
8763 /* PowerPC 601v1 */
8764 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601)
8765 /* PowerPC 601v2 */
8766 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v)
8767 /* PowerPC 602 */
8768 POWERPC_DEF("602", CPU_POWERPC_602, 602)
8769 /* PowerPC 603 */
8770 POWERPC_DEF("603", CPU_POWERPC_603, 603)
8771 /* PowerPC 603e v1.1 */
8772 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E)
8773 /* PowerPC 603e v1.2 */
8774 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E)
8775 /* PowerPC 603e v1.3 */
8776 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E)
8777 /* PowerPC 603e v1.4 */
8778 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E)
8779 /* PowerPC 603e v2.2 */
8780 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E)
8781 /* PowerPC 603e v3 */
8782 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E)
8783 /* PowerPC 603e v4 */
8784 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E)
8785 /* PowerPC 603e v4.1 */
8786 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E)
8787 /* PowerPC 603e (aka PID7) */
8788 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E)
8789 /* PowerPC 603e7t */
8790 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E)
8791 /* PowerPC 603e7v */
8792 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E)
8793 /* PowerPC 603e7v1 */
8794 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E)
8795 /* PowerPC 603e7v2 */
8796 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E)
8797 /* PowerPC 603p (aka PID7v) */
8798 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E)
8799 /* PowerPC 604 */
8800 POWERPC_DEF("604", CPU_POWERPC_604, 604)
8801 /* PowerPC 604e v1.0 */
8802 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E)
8803 /* PowerPC 604e v2.2 */
8804 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E)
8805 /* PowerPC 604e v2.4 */
8806 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E)
8807 /* PowerPC 604r (aka PIDA) */
8808 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E)
8809 #if defined(TODO)
8810 /* PowerPC 604ev */
8811 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E)
8812 #endif
8813 /* PowerPC 7xx family */
8814 /* PowerPC 740 v1.0 (G3) */
8815 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740)
8816 /* PowerPC 750 v1.0 (G3) */
8817 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750)
8818 /* PowerPC 740 v2.0 (G3) */
8819 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740)
8820 /* PowerPC 750 v2.0 (G3) */
8821 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750)
8822 /* PowerPC 740 v2.1 (G3) */
8823 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740)
8824 /* PowerPC 750 v2.1 (G3) */
8825 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750)
8826 /* PowerPC 740 v2.2 (G3) */
8827 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740)
8828 /* PowerPC 750 v2.2 (G3) */
8829 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750)
8830 /* PowerPC 740 v3.0 (G3) */
8831 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740)
8832 /* PowerPC 750 v3.0 (G3) */
8833 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750)
8834 /* PowerPC 740 v3.1 (G3) */
8835 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740)
8836 /* PowerPC 750 v3.1 (G3) */
8837 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750)
8838 /* PowerPC 740E (G3) */
8839 POWERPC_DEF("740e", CPU_POWERPC_740E, 740)
8840 /* PowerPC 750E (G3) */
8841 POWERPC_DEF("750e", CPU_POWERPC_750E, 750)
8842 /* PowerPC 740P (G3) */
8843 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740)
8844 /* PowerPC 750P (G3) */
8845 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750)
8846 /* PowerPC 750CL v1.0 */
8847 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl)
8848 /* PowerPC 750CL v2.0 */
8849 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl)
8850 /* PowerPC 750CX v1.0 (G3 embedded) */
8851 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx)
8852 /* PowerPC 750CX v2.1 (G3 embedded) */
8853 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx)
8854 /* PowerPC 750CX v2.1 (G3 embedded) */
8855 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx)
8856 /* PowerPC 750CX v2.2 (G3 embedded) */
8857 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx)
8858 /* PowerPC 750CXe v2.1 (G3 embedded) */
8859 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx)
8860 /* PowerPC 750CXe v2.2 (G3 embedded) */
8861 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx)
8862 /* PowerPC 750CXe v2.3 (G3 embedded) */
8863 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx)
8864 /* PowerPC 750CXe v2.4 (G3 embedded) */
8865 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx)
8866 /* PowerPC 750CXe v2.4b (G3 embedded) */
8867 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx)
8868 /* PowerPC 750CXe v3.0 (G3 embedded) */
8869 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx)
8870 /* PowerPC 750CXe v3.1 (G3 embedded) */
8871 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx)
8872 /* PowerPC 750CXe v3.1b (G3 embedded) */
8873 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx)
8874 /* PowerPC 750CXr (G3 embedded) */
8875 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx)
8876 /* PowerPC 750FL (G3 embedded) */
8877 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx)
8878 /* PowerPC 750FX v1.0 (G3 embedded) */
8879 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx)
8880 /* PowerPC 750FX v2.0 (G3 embedded) */
8881 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx)
8882 /* PowerPC 750FX v2.1 (G3 embedded) */
8883 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx)
8884 /* PowerPC 750FX v2.2 (G3 embedded) */
8885 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx)
8886 /* PowerPC 750FX v2.3 (G3 embedded) */
8887 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx)
8888 /* PowerPC 750GL (G3 embedded) */
8889 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx)
8890 /* PowerPC 750GX v1.0 (G3 embedded) */
8891 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx)
8892 /* PowerPC 750GX v1.1 (G3 embedded) */
8893 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx)
8894 /* PowerPC 750GX v1.2 (G3 embedded) */
8895 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx)
8896 /* PowerPC 750L v2.0 (G3 embedded) */
8897 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750)
8898 /* PowerPC 750L v2.1 (G3 embedded) */
8899 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750)
8900 /* PowerPC 750L v2.2 (G3 embedded) */
8901 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750)
8902 /* PowerPC 750L v3.0 (G3 embedded) */
8903 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750)
8904 /* PowerPC 750L v3.2 (G3 embedded) */
8905 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750)
8906 /* PowerPC 745 v1.0 */
8907 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745)
8908 /* PowerPC 755 v1.0 */
8909 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755)
8910 /* PowerPC 745 v1.1 */
8911 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745)
8912 /* PowerPC 755 v1.1 */
8913 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755)
8914 /* PowerPC 745 v2.0 */
8915 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745)
8916 /* PowerPC 755 v2.0 */
8917 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755)
8918 /* PowerPC 745 v2.1 */
8919 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745)
8920 /* PowerPC 755 v2.1 */
8921 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755)
8922 /* PowerPC 745 v2.2 */
8923 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745)
8924 /* PowerPC 755 v2.2 */
8925 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755)
8926 /* PowerPC 745 v2.3 */
8927 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745)
8928 /* PowerPC 755 v2.3 */
8929 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755)
8930 /* PowerPC 745 v2.4 */
8931 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745)
8932 /* PowerPC 755 v2.4 */
8933 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755)
8934 /* PowerPC 745 v2.5 */
8935 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745)
8936 /* PowerPC 755 v2.5 */
8937 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755)
8938 /* PowerPC 745 v2.6 */
8939 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745)
8940 /* PowerPC 755 v2.6 */
8941 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755)
8942 /* PowerPC 745 v2.7 */
8943 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745)
8944 /* PowerPC 755 v2.7 */
8945 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755)
8946 /* PowerPC 745 v2.8 */
8947 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745)
8948 /* PowerPC 755 v2.8 */
8949 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755)
8950 #if defined (TODO)
8951 /* PowerPC 745P (G3) */
8952 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745)
8953 /* PowerPC 755P (G3) */
8954 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755)
8955 #endif
8956 /* PowerPC 74xx family */
8957 /* PowerPC 7400 v1.0 (G4) */
8958 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400)
8959 /* PowerPC 7400 v1.1 (G4) */
8960 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400)
8961 /* PowerPC 7400 v2.0 (G4) */
8962 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400)
8963 /* PowerPC 7400 v2.1 (G4) */
8964 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400)
8965 /* PowerPC 7400 v2.2 (G4) */
8966 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400)
8967 /* PowerPC 7400 v2.6 (G4) */
8968 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400)
8969 /* PowerPC 7400 v2.7 (G4) */
8970 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400)
8971 /* PowerPC 7400 v2.8 (G4) */
8972 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400)
8973 /* PowerPC 7400 v2.9 (G4) */
8974 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400)
8975 /* PowerPC 7410 v1.0 (G4) */
8976 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410)
8977 /* PowerPC 7410 v1.1 (G4) */
8978 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410)
8979 /* PowerPC 7410 v1.2 (G4) */
8980 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410)
8981 /* PowerPC 7410 v1.3 (G4) */
8982 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410)
8983 /* PowerPC 7410 v1.4 (G4) */
8984 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410)
8985 /* PowerPC 7448 v1.0 (G4) */
8986 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400)
8987 /* PowerPC 7448 v1.1 (G4) */
8988 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400)
8989 /* PowerPC 7448 v2.0 (G4) */
8990 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400)
8991 /* PowerPC 7448 v2.1 (G4) */
8992 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400)
8993 /* PowerPC 7450 v1.0 (G4) */
8994 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450)
8995 /* PowerPC 7450 v1.1 (G4) */
8996 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450)
8997 /* PowerPC 7450 v1.2 (G4) */
8998 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450)
8999 /* PowerPC 7450 v2.0 (G4) */
9000 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450)
9001 /* PowerPC 7450 v2.1 (G4) */
9002 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450)
9003 /* PowerPC 7441 v2.1 (G4) */
9004 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440)
9005 /* PowerPC 7441 v2.3 (G4) */
9006 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440)
9007 /* PowerPC 7451 v2.3 (G4) */
9008 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450)
9009 /* PowerPC 7441 v2.10 (G4) */
9010 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440)
9011 /* PowerPC 7451 v2.10 (G4) */
9012 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450)
9013 /* PowerPC 7445 v1.0 (G4) */
9014 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445)
9015 /* PowerPC 7455 v1.0 (G4) */
9016 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455)
9017 /* PowerPC 7445 v2.1 (G4) */
9018 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445)
9019 /* PowerPC 7455 v2.1 (G4) */
9020 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455)
9021 /* PowerPC 7445 v3.2 (G4) */
9022 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445)
9023 /* PowerPC 7455 v3.2 (G4) */
9024 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455)
9025 /* PowerPC 7445 v3.3 (G4) */
9026 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445)
9027 /* PowerPC 7455 v3.3 (G4) */
9028 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455)
9029 /* PowerPC 7445 v3.4 (G4) */
9030 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445)
9031 /* PowerPC 7455 v3.4 (G4) */
9032 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455)
9033 /* PowerPC 7447 v1.0 (G4) */
9034 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445)
9035 /* PowerPC 7457 v1.0 (G4) */
9036 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455)
9037 /* PowerPC 7447 v1.1 (G4) */
9038 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445)
9039 /* PowerPC 7457 v1.1 (G4) */
9040 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455)
9041 /* PowerPC 7457 v1.2 (G4) */
9042 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455)
9043 /* PowerPC 7447A v1.0 (G4) */
9044 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445)
9045 /* PowerPC 7457A v1.0 (G4) */
9046 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455)
9047 /* PowerPC 7447A v1.1 (G4) */
9048 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445)
9049 /* PowerPC 7457A v1.1 (G4) */
9050 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455)
9051 /* PowerPC 7447A v1.2 (G4) */
9052 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445)
9053 /* PowerPC 7457A v1.2 (G4) */
9054 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455)
9055 /* 64 bits PowerPC */
9056 #if defined (TARGET_PPC64)
9057 /* PowerPC 620 */
9058 POWERPC_DEF("620", CPU_POWERPC_620, 620)
9059 #if defined (TODO)
9060 /* PowerPC 630 (POWER3) */
9061 POWERPC_DEF("630", CPU_POWERPC_630, 630)
9062 #endif
9063 #if defined (TODO)
9064 /* PowerPC 631 (Power 3+) */
9065 POWERPC_DEF("631", CPU_POWERPC_631, 631)
9066 #endif
9067 #if defined (TODO)
9068 /* POWER4 */
9069 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4)
9070 #endif
9071 #if defined (TODO)
9072 /* POWER4p */
9073 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P)
9074 #endif
9075 #if defined (TODO)
9076 /* POWER5 */
9077 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5)
9078 /* POWER5GR */
9079 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5)
9080 #endif
9081 #if defined (TODO)
9082 /* POWER5+ */
9083 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P)
9084 /* POWER5GS */
9085 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P)
9086 #endif
9087 #if defined (TODO)
9088 /* POWER6 */
9089 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6)
9090 /* POWER6 running in POWER5 mode */
9091 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5)
9092 /* POWER6A */
9093 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6)
9094 #endif
9095 /* POWER7 */
9096 POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7)
9097 POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POWER7)
9098 POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7)
9099 /* PowerPC 970 */
9100 POWERPC_DEF("970", CPU_POWERPC_970, 970)
9101 /* PowerPC 970FX v1.0 (G5) */
9102 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX)
9103 /* PowerPC 970FX v2.0 (G5) */
9104 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX)
9105 /* PowerPC 970FX v2.1 (G5) */
9106 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX)
9107 /* PowerPC 970FX v3.0 (G5) */
9108 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX)
9109 /* PowerPC 970FX v3.1 (G5) */
9110 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX)
9111 /* PowerPC 970GX (G5) */
9112 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX)
9113 /* PowerPC 970MP v1.0 */
9114 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP)
9115 /* PowerPC 970MP v1.1 */
9116 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP)
9117 #if defined (TODO)
9118 /* PowerPC Cell */
9119 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970)
9120 #endif
9121 #if defined (TODO)
9122 /* PowerPC Cell v1.0 */
9123 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970)
9124 #endif
9125 #if defined (TODO)
9126 /* PowerPC Cell v2.0 */
9127 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970)
9128 #endif
9129 #if defined (TODO)
9130 /* PowerPC Cell v3.0 */
9131 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970)
9132 #endif
9133 #if defined (TODO)
9134 /* PowerPC Cell v3.1 */
9135 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970)
9136 #endif
9137 #if defined (TODO)
9138 /* PowerPC Cell v3.2 */
9139 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970)
9140 #endif
9141 #if defined (TODO)
9142 /* RS64 (Apache/A35) */
9143 /* This one seems to support the whole POWER2 instruction set
9144 * and the PowerPC 64 one.
9145 */
9146 /* What about A10 & A30 ? */
9147 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64)
9148 #endif
9149 #if defined (TODO)
9150 /* RS64-II (NorthStar/A50) */
9151 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64)
9152 #endif
9153 #if defined (TODO)
9154 /* RS64-III (Pulsar) */
9155 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64)
9156 #endif
9157 #if defined (TODO)
9158 /* RS64-IV (IceStar/IStar/SStar) */
9159 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64)
9160 #endif
9161 #endif /* defined (TARGET_PPC64) */
9162 /* POWER */
9163 #if defined (TODO)
9164 /* Original POWER */
9165 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER)
9166 #endif
9167 #if defined (TODO)
9168 /* POWER2 */
9169 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER)
9170 #endif
9171 /* PA semi cores */
9172 #if defined (TODO)
9173 /* PA PA6T */
9174 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T)
9175 #endif
9176
9177 typedef struct PowerPCCPUAlias {
9178 const char *alias;
9179 const char *model;
9180 } PowerPCCPUAlias;
9181
9182 static const PowerPCCPUAlias ppc_cpu_aliases[] = {
9183 { "403", "403GC" },
9184 { "405", "405D4" },
9185 { "405CR", "405CRc" },
9186 { "405GP", "405GPd" },
9187 { "405GPe", "405CRc" },
9188 { "x2vp7", "x2vp4" },
9189 { "x2vp50", "x2vp20" },
9190
9191 { "440EP", "440EPb" },
9192 { "440GP", "440GPc" },
9193 { "440GR", "440GRa" },
9194 { "440GX", "440GXf" },
9195
9196 { "RCPU", "MPC5xx" },
9197 /* MPC5xx microcontrollers */
9198 { "MGT560", "MPC5xx" },
9199 { "MPC509", "MPC5xx" },
9200 { "MPC533", "MPC5xx" },
9201 { "MPC534", "MPC5xx" },
9202 { "MPC555", "MPC5xx" },
9203 { "MPC556", "MPC5xx" },
9204 { "MPC560", "MPC5xx" },
9205 { "MPC561", "MPC5xx" },
9206 { "MPC562", "MPC5xx" },
9207 { "MPC563", "MPC5xx" },
9208 { "MPC564", "MPC5xx" },
9209 { "MPC565", "MPC5xx" },
9210 { "MPC566", "MPC5xx" },
9211
9212 { "PowerQUICC", "MPC8xx" },
9213 /* MPC8xx microcontrollers */
9214 { "MGT823", "MPC8xx" },
9215 { "MPC821", "MPC8xx" },
9216 { "MPC823", "MPC8xx" },
9217 { "MPC850", "MPC8xx" },
9218 { "MPC852T", "MPC8xx" },
9219 { "MPC855T", "MPC8xx" },
9220 { "MPC857", "MPC8xx" },
9221 { "MPC859", "MPC8xx" },
9222 { "MPC860", "MPC8xx" },
9223 { "MPC862", "MPC8xx" },
9224 { "MPC866", "MPC8xx" },
9225 { "MPC870", "MPC8xx" },
9226 { "MPC875", "MPC8xx" },
9227 { "MPC880", "MPC8xx" },
9228 { "MPC885", "MPC8xx" },
9229
9230 /* PowerPC MPC603 microcontrollers */
9231 { "MPC8240", "603" },
9232
9233 { "MPC52xx", "MPC5200" },
9234 { "MPC5200", "MPC5200_v12" },
9235 { "MPC5200B", "MPC5200B_v21" },
9236
9237 { "MPC82xx", "MPC8280" },
9238 { "PowerQUICC-II", "MPC82xx" },
9239 { "MPC8241", "G2HiP4" },
9240 { "MPC8245", "G2HiP4" },
9241 { "MPC8247", "G2leGP3" },
9242 { "MPC8248", "G2leGP3" },
9243 { "MPC8250", "MPC8250_HiP4" },
9244 { "MPC8250_HiP3", "G2HiP3" },
9245 { "MPC8250_HiP4", "G2HiP4" },
9246 { "MPC8255", "MPC8255_HiP4" },
9247 { "MPC8255_HiP3", "G2HiP3" },
9248 { "MPC8255_HiP4", "G2HiP4" },
9249 { "MPC8260", "MPC8260_HiP4" },
9250 { "MPC8260_HiP3", "G2HiP3" },
9251 { "MPC8260_HiP4", "G2HiP4" },
9252 { "MPC8264", "MPC8264_HiP4" },
9253 { "MPC8264_HiP3", "G2HiP3" },
9254 { "MPC8264_HiP4", "G2HiP4" },
9255 { "MPC8265", "MPC8265_HiP4" },
9256 { "MPC8265_HiP3", "G2HiP3" },
9257 { "MPC8265_HiP4", "G2HiP4" },
9258 { "MPC8266", "MPC8266_HiP4" },
9259 { "MPC8266_HiP3", "G2HiP3" },
9260 { "MPC8266_HiP4", "G2HiP4" },
9261 { "MPC8270", "G2leGP3" },
9262 { "MPC8271", "G2leGP3" },
9263 { "MPC8272", "G2leGP3" },
9264 { "MPC8275", "G2leGP3" },
9265 { "MPC8280", "G2leGP3" },
9266 { "e200", "e200z6" },
9267 { "e300", "e300c3" },
9268 { "MPC8347", "MPC8347T" },
9269 { "MPC8347A", "MPC8347AT" },
9270 { "MPC8347E", "MPC8347ET" },
9271 { "MPC8347EA", "MPC8347EAT" },
9272 { "e500", "e500v2_v22" },
9273 { "e500v1", "e500_v20" },
9274 { "e500v2", "e500v2_v22" },
9275 { "MPC8533", "MPC8533_v11" },
9276 { "MPC8533E", "MPC8533E_v11" },
9277 { "MPC8540", "MPC8540_v21" },
9278 { "MPC8541", "MPC8541_v11" },
9279 { "MPC8541E", "MPC8541E_v11" },
9280 { "MPC8543", "MPC8543_v21" },
9281 { "MPC8543E", "MPC8543E_v21" },
9282 { "MPC8544", "MPC8544_v11" },
9283 { "MPC8544E", "MPC8544E_v11" },
9284 { "MPC8545", "MPC8545_v21" },
9285 { "MPC8545E", "MPC8545E_v21" },
9286 { "MPC8547E", "MPC8547E_v21" },
9287 { "MPC8548", "MPC8548_v21" },
9288 { "MPC8548E", "MPC8548E_v21" },
9289 { "MPC8555", "MPC8555_v11" },
9290 { "MPC8555E", "MPC8555E_v11" },
9291 { "MPC8560", "MPC8560_v21" },
9292 { "601", "601_v2" },
9293 { "601v", "601_v2" },
9294 { "Vanilla", "603" },
9295 { "603e", "603e_v4.1" },
9296 { "Stretch", "603e" },
9297 { "Vaillant", "603e7v" },
9298 { "603r", "603e7t" },
9299 { "Goldeneye", "603r" },
9300 { "604e", "604e_v2.4" },
9301 { "Sirocco", "604e" },
9302 { "Mach5", "604r" },
9303 { "740", "740_v3.1" },
9304 { "Arthur", "740" },
9305 { "750", "750_v3.1" },
9306 { "Typhoon", "750" },
9307 { "G3", "750" },
9308 { "Conan/Doyle", "750p" },
9309 { "750cl", "750cl_v2.0" },
9310 { "750cx", "750cx_v2.2" },
9311 { "750cxe", "750cxe_v3.1b" },
9312 { "750fx", "750fx_v2.3" },
9313 { "750gx", "750gx_v1.2" },
9314 { "750l", "750l_v3.2" },
9315 { "LoneStar", "750l" },
9316 { "745", "745_v2.8" },
9317 { "755", "755_v2.8" },
9318 { "Goldfinger", "755" },
9319 { "7400", "7400_v2.9" },
9320 { "Max", "7400" },
9321 { "G4", "7400" },
9322 { "7410", "7410_v1.4" },
9323 { "Nitro", "7410" },
9324 { "7448", "7448_v2.1" },
9325 { "7450", "7450_v2.1" },
9326 { "Vger", "7450" },
9327 { "7441", "7441_v2.3" },
9328 { "7451", "7451_v2.3" },
9329 { "7445", "7445_v3.2" },
9330 { "7455", "7455_v3.2" },
9331 { "Apollo6", "7455" },
9332 { "7447", "7447_v1.2" },
9333 { "7457", "7457_v1.2" },
9334 { "Apollo7", "7457" },
9335 { "7447A", "7447A_v1.2" },
9336 { "7457A", "7457A_v1.2" },
9337 { "Apollo7PM", "7457A_v1.0" },
9338 #if defined(TARGET_PPC64)
9339 { "Trident", "620" },
9340 { "POWER3", "630" },
9341 { "Boxer", "POWER3" },
9342 { "Dino", "POWER3" },
9343 { "POWER3+", "631" },
9344 { "POWER7", "POWER7_v2.0" },
9345 { "970fx", "970fx_v3.1" },
9346 { "970mp", "970mp_v1.1" },
9347 { "Apache", "RS64" },
9348 { "A35", "RS64" },
9349 { "NorthStar", "RS64-II" },
9350 { "A50", "RS64-II" },
9351 { "Pulsar", "RS64-III" },
9352 { "IceStar", "RS64-IV" },
9353 { "IStar", "RS64-IV" },
9354 { "SStar", "RS64-IV" },
9355 #endif
9356 { "RIOS", "POWER" },
9357 { "RSC", "POWER" },
9358 { "RSC3308", "POWER" },
9359 { "RSC4608", "POWER" },
9360 { "RSC2", "POWER2" },
9361 { "P2SC", "POWER2" },
9362
9363 /* Generic PowerPCs */
9364 #if defined(TARGET_PPC64)
9365 { "ppc64", "970fx" },
9366 #endif
9367 { "ppc32", "604" },
9368 { "ppc", "ppc32" },
9369 { "default", "ppc" },
9370 };
9371
9372 /*****************************************************************************/
9373 /* Generic CPU instantiation routine */
9374 static void init_ppc_proc(PowerPCCPU *cpu)
9375 {
9376 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9377 CPUPPCState *env = &cpu->env;
9378 #if !defined(CONFIG_USER_ONLY)
9379 int i;
9380
9381 env->irq_inputs = NULL;
9382 /* Set all exception vectors to an invalid address */
9383 for (i = 0; i < POWERPC_EXCP_NB; i++)
9384 env->excp_vectors[i] = (target_ulong)(-1ULL);
9385 env->hreset_excp_prefix = 0x00000000;
9386 env->ivor_mask = 0x00000000;
9387 env->ivpr_mask = 0x00000000;
9388 /* Default MMU definitions */
9389 env->nb_BATs = 0;
9390 env->nb_tlb = 0;
9391 env->nb_ways = 0;
9392 env->tlb_type = TLB_NONE;
9393 #endif
9394 /* Register SPR common to all PowerPC implementations */
9395 gen_spr_generic(env);
9396 spr_register(env, SPR_PVR, "PVR",
9397 /* Linux permits userspace to read PVR */
9398 #if defined(CONFIG_LINUX_USER)
9399 &spr_read_generic,
9400 #else
9401 SPR_NOACCESS,
9402 #endif
9403 SPR_NOACCESS,
9404 &spr_read_generic, SPR_NOACCESS,
9405 pcc->pvr);
9406 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9407 if (pcc->svr != POWERPC_SVR_NONE) {
9408 if (pcc->svr & POWERPC_SVR_E500) {
9409 spr_register(env, SPR_E500_SVR, "SVR",
9410 SPR_NOACCESS, SPR_NOACCESS,
9411 &spr_read_generic, SPR_NOACCESS,
9412 pcc->svr & ~POWERPC_SVR_E500);
9413 } else {
9414 spr_register(env, SPR_SVR, "SVR",
9415 SPR_NOACCESS, SPR_NOACCESS,
9416 &spr_read_generic, SPR_NOACCESS,
9417 pcc->svr);
9418 }
9419 }
9420 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9421 (*pcc->init_proc)(env);
9422 #if !defined(CONFIG_USER_ONLY)
9423 env->excp_prefix = env->hreset_excp_prefix;
9424 #endif
9425 /* MSR bits & flags consistency checks */
9426 if (env->msr_mask & (1 << 25)) {
9427 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9428 case POWERPC_FLAG_SPE:
9429 case POWERPC_FLAG_VRE:
9430 break;
9431 default:
9432 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9433 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9434 exit(1);
9435 }
9436 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9437 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9438 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9439 exit(1);
9440 }
9441 if (env->msr_mask & (1 << 17)) {
9442 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9443 case POWERPC_FLAG_TGPR:
9444 case POWERPC_FLAG_CE:
9445 break;
9446 default:
9447 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9448 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9449 exit(1);
9450 }
9451 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9452 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9453 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9454 exit(1);
9455 }
9456 if (env->msr_mask & (1 << 10)) {
9457 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9458 POWERPC_FLAG_UBLE)) {
9459 case POWERPC_FLAG_SE:
9460 case POWERPC_FLAG_DWE:
9461 case POWERPC_FLAG_UBLE:
9462 break;
9463 default:
9464 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9465 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9466 "POWERPC_FLAG_UBLE\n");
9467 exit(1);
9468 }
9469 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9470 POWERPC_FLAG_UBLE)) {
9471 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9472 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9473 "POWERPC_FLAG_UBLE\n");
9474 exit(1);
9475 }
9476 if (env->msr_mask & (1 << 9)) {
9477 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9478 case POWERPC_FLAG_BE:
9479 case POWERPC_FLAG_DE:
9480 break;
9481 default:
9482 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9483 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9484 exit(1);
9485 }
9486 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9487 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9488 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9489 exit(1);
9490 }
9491 if (env->msr_mask & (1 << 2)) {
9492 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9493 case POWERPC_FLAG_PX:
9494 case POWERPC_FLAG_PMM:
9495 break;
9496 default:
9497 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9498 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9499 exit(1);
9500 }
9501 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9502 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9503 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9504 exit(1);
9505 }
9506 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9507 fprintf(stderr, "PowerPC flags inconsistency\n"
9508 "Should define the time-base and decrementer clock source\n");
9509 exit(1);
9510 }
9511 /* Allocate TLBs buffer when needed */
9512 #if !defined(CONFIG_USER_ONLY)
9513 if (env->nb_tlb != 0) {
9514 int nb_tlb = env->nb_tlb;
9515 if (env->id_tlbs != 0)
9516 nb_tlb *= 2;
9517 switch (env->tlb_type) {
9518 case TLB_6XX:
9519 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
9520 break;
9521 case TLB_EMB:
9522 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
9523 break;
9524 case TLB_MAS:
9525 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
9526 break;
9527 }
9528 /* Pre-compute some useful values */
9529 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9530 }
9531 if (env->irq_inputs == NULL) {
9532 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
9533 " Attempt QEMU to crash very soon !\n");
9534 }
9535 #endif
9536 if (env->check_pow == NULL) {
9537 fprintf(stderr, "WARNING: no power management check handler "
9538 "registered.\n"
9539 " Attempt QEMU to crash very soon !\n");
9540 }
9541 }
9542
9543 #if defined(PPC_DUMP_CPU)
9544 static void dump_ppc_sprs (CPUPPCState *env)
9545 {
9546 ppc_spr_t *spr;
9547 #if !defined(CONFIG_USER_ONLY)
9548 uint32_t sr, sw;
9549 #endif
9550 uint32_t ur, uw;
9551 int i, j, n;
9552
9553 printf("Special purpose registers:\n");
9554 for (i = 0; i < 32; i++) {
9555 for (j = 0; j < 32; j++) {
9556 n = (i << 5) | j;
9557 spr = &env->spr_cb[n];
9558 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9559 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9560 #if !defined(CONFIG_USER_ONLY)
9561 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9562 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9563 if (sw || sr || uw || ur) {
9564 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9565 (i << 5) | j, (i << 5) | j, spr->name,
9566 sw ? 'w' : '-', sr ? 'r' : '-',
9567 uw ? 'w' : '-', ur ? 'r' : '-');
9568 }
9569 #else
9570 if (uw || ur) {
9571 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9572 (i << 5) | j, (i << 5) | j, spr->name,
9573 uw ? 'w' : '-', ur ? 'r' : '-');
9574 }
9575 #endif
9576 }
9577 }
9578 fflush(stdout);
9579 fflush(stderr);
9580 }
9581 #endif
9582
9583 /*****************************************************************************/
9584 #include <stdlib.h>
9585 #include <string.h>
9586
9587 /* Opcode types */
9588 enum {
9589 PPC_DIRECT = 0, /* Opcode routine */
9590 PPC_INDIRECT = 1, /* Indirect opcode table */
9591 };
9592
9593 static inline int is_indirect_opcode (void *handler)
9594 {
9595 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
9596 }
9597
9598 static inline opc_handler_t **ind_table(void *handler)
9599 {
9600 return (opc_handler_t **)((uintptr_t)handler & ~3);
9601 }
9602
9603 /* Instruction table creation */
9604 /* Opcodes tables creation */
9605 static void fill_new_table (opc_handler_t **table, int len)
9606 {
9607 int i;
9608
9609 for (i = 0; i < len; i++)
9610 table[i] = &invalid_handler;
9611 }
9612
9613 static int create_new_table (opc_handler_t **table, unsigned char idx)
9614 {
9615 opc_handler_t **tmp;
9616
9617 tmp = malloc(0x20 * sizeof(opc_handler_t));
9618 fill_new_table(tmp, 0x20);
9619 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
9620
9621 return 0;
9622 }
9623
9624 static int insert_in_table (opc_handler_t **table, unsigned char idx,
9625 opc_handler_t *handler)
9626 {
9627 if (table[idx] != &invalid_handler)
9628 return -1;
9629 table[idx] = handler;
9630
9631 return 0;
9632 }
9633
9634 static int register_direct_insn (opc_handler_t **ppc_opcodes,
9635 unsigned char idx, opc_handler_t *handler)
9636 {
9637 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9638 printf("*** ERROR: opcode %02x already assigned in main "
9639 "opcode table\n", idx);
9640 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9641 printf(" Registered handler '%s' - new handler '%s'\n",
9642 ppc_opcodes[idx]->oname, handler->oname);
9643 #endif
9644 return -1;
9645 }
9646
9647 return 0;
9648 }
9649
9650 static int register_ind_in_table (opc_handler_t **table,
9651 unsigned char idx1, unsigned char idx2,
9652 opc_handler_t *handler)
9653 {
9654 if (table[idx1] == &invalid_handler) {
9655 if (create_new_table(table, idx1) < 0) {
9656 printf("*** ERROR: unable to create indirect table "
9657 "idx=%02x\n", idx1);
9658 return -1;
9659 }
9660 } else {
9661 if (!is_indirect_opcode(table[idx1])) {
9662 printf("*** ERROR: idx %02x already assigned to a direct "
9663 "opcode\n", idx1);
9664 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9665 printf(" Registered handler '%s' - new handler '%s'\n",
9666 ind_table(table[idx1])[idx2]->oname, handler->oname);
9667 #endif
9668 return -1;
9669 }
9670 }
9671 if (handler != NULL &&
9672 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9673 printf("*** ERROR: opcode %02x already assigned in "
9674 "opcode table %02x\n", idx2, idx1);
9675 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9676 printf(" Registered handler '%s' - new handler '%s'\n",
9677 ind_table(table[idx1])[idx2]->oname, handler->oname);
9678 #endif
9679 return -1;
9680 }
9681
9682 return 0;
9683 }
9684
9685 static int register_ind_insn (opc_handler_t **ppc_opcodes,
9686 unsigned char idx1, unsigned char idx2,
9687 opc_handler_t *handler)
9688 {
9689 int ret;
9690
9691 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9692
9693 return ret;
9694 }
9695
9696 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9697 unsigned char idx1, unsigned char idx2,
9698 unsigned char idx3, opc_handler_t *handler)
9699 {
9700 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9701 printf("*** ERROR: unable to join indirect table idx "
9702 "[%02x-%02x]\n", idx1, idx2);
9703 return -1;
9704 }
9705 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9706 handler) < 0) {
9707 printf("*** ERROR: unable to insert opcode "
9708 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9709 return -1;
9710 }
9711
9712 return 0;
9713 }
9714
9715 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9716 {
9717 if (insn->opc2 != 0xFF) {
9718 if (insn->opc3 != 0xFF) {
9719 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9720 insn->opc3, &insn->handler) < 0)
9721 return -1;
9722 } else {
9723 if (register_ind_insn(ppc_opcodes, insn->opc1,
9724 insn->opc2, &insn->handler) < 0)
9725 return -1;
9726 }
9727 } else {
9728 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9729 return -1;
9730 }
9731
9732 return 0;
9733 }
9734
9735 static int test_opcode_table (opc_handler_t **table, int len)
9736 {
9737 int i, count, tmp;
9738
9739 for (i = 0, count = 0; i < len; i++) {
9740 /* Consistency fixup */
9741 if (table[i] == NULL)
9742 table[i] = &invalid_handler;
9743 if (table[i] != &invalid_handler) {
9744 if (is_indirect_opcode(table[i])) {
9745 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9746 if (tmp == 0) {
9747 free(table[i]);
9748 table[i] = &invalid_handler;
9749 } else {
9750 count++;
9751 }
9752 } else {
9753 count++;
9754 }
9755 }
9756 }
9757
9758 return count;
9759 }
9760
9761 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9762 {
9763 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9764 printf("*** WARNING: no opcode defined !\n");
9765 }
9766
9767 /*****************************************************************************/
9768 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
9769 {
9770 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9771 CPUPPCState *env = &cpu->env;
9772 opcode_t *opc;
9773
9774 fill_new_table(env->opcodes, 0x40);
9775 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9776 if (((opc->handler.type & pcc->insns_flags) != 0) ||
9777 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
9778 if (register_insn(env->opcodes, opc) < 0) {
9779 error_setg(errp, "ERROR initializing PowerPC instruction "
9780 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
9781 opc->opc3);
9782 return;
9783 }
9784 }
9785 }
9786 fix_opcode_tables(env->opcodes);
9787 fflush(stdout);
9788 fflush(stderr);
9789 }
9790
9791 #if defined(PPC_DUMP_CPU)
9792 static void dump_ppc_insns (CPUPPCState *env)
9793 {
9794 opc_handler_t **table, *handler;
9795 const char *p, *q;
9796 uint8_t opc1, opc2, opc3;
9797
9798 printf("Instructions set:\n");
9799 /* opc1 is 6 bits long */
9800 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9801 table = env->opcodes;
9802 handler = table[opc1];
9803 if (is_indirect_opcode(handler)) {
9804 /* opc2 is 5 bits long */
9805 for (opc2 = 0; opc2 < 0x20; opc2++) {
9806 table = env->opcodes;
9807 handler = env->opcodes[opc1];
9808 table = ind_table(handler);
9809 handler = table[opc2];
9810 if (is_indirect_opcode(handler)) {
9811 table = ind_table(handler);
9812 /* opc3 is 5 bits long */
9813 for (opc3 = 0; opc3 < 0x20; opc3++) {
9814 handler = table[opc3];
9815 if (handler->handler != &gen_invalid) {
9816 /* Special hack to properly dump SPE insns */
9817 p = strchr(handler->oname, '_');
9818 if (p == NULL) {
9819 printf("INSN: %02x %02x %02x (%02d %04d) : "
9820 "%s\n",
9821 opc1, opc2, opc3, opc1,
9822 (opc3 << 5) | opc2,
9823 handler->oname);
9824 } else {
9825 q = "speundef";
9826 if ((p - handler->oname) != strlen(q) ||
9827 memcmp(handler->oname, q, strlen(q)) != 0) {
9828 /* First instruction */
9829 printf("INSN: %02x %02x %02x (%02d %04d) : "
9830 "%.*s\n",
9831 opc1, opc2 << 1, opc3, opc1,
9832 (opc3 << 6) | (opc2 << 1),
9833 (int)(p - handler->oname),
9834 handler->oname);
9835 }
9836 if (strcmp(p + 1, q) != 0) {
9837 /* Second instruction */
9838 printf("INSN: %02x %02x %02x (%02d %04d) : "
9839 "%s\n",
9840 opc1, (opc2 << 1) | 1, opc3, opc1,
9841 (opc3 << 6) | (opc2 << 1) | 1,
9842 p + 1);
9843 }
9844 }
9845 }
9846 }
9847 } else {
9848 if (handler->handler != &gen_invalid) {
9849 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9850 opc1, opc2, opc1, opc2, handler->oname);
9851 }
9852 }
9853 }
9854 } else {
9855 if (handler->handler != &gen_invalid) {
9856 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9857 opc1, opc1, handler->oname);
9858 }
9859 }
9860 }
9861 }
9862 #endif
9863
9864 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9865 {
9866 if (n < 32) {
9867 stfq_p(mem_buf, env->fpr[n]);
9868 return 8;
9869 }
9870 if (n == 32) {
9871 stl_p(mem_buf, env->fpscr);
9872 return 4;
9873 }
9874 return 0;
9875 }
9876
9877 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9878 {
9879 if (n < 32) {
9880 env->fpr[n] = ldfq_p(mem_buf);
9881 return 8;
9882 }
9883 if (n == 32) {
9884 /* FPSCR not implemented */
9885 return 4;
9886 }
9887 return 0;
9888 }
9889
9890 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9891 {
9892 if (n < 32) {
9893 #ifdef HOST_WORDS_BIGENDIAN
9894 stq_p(mem_buf, env->avr[n].u64[0]);
9895 stq_p(mem_buf+8, env->avr[n].u64[1]);
9896 #else
9897 stq_p(mem_buf, env->avr[n].u64[1]);
9898 stq_p(mem_buf+8, env->avr[n].u64[0]);
9899 #endif
9900 return 16;
9901 }
9902 if (n == 32) {
9903 stl_p(mem_buf, env->vscr);
9904 return 4;
9905 }
9906 if (n == 33) {
9907 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9908 return 4;
9909 }
9910 return 0;
9911 }
9912
9913 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9914 {
9915 if (n < 32) {
9916 #ifdef HOST_WORDS_BIGENDIAN
9917 env->avr[n].u64[0] = ldq_p(mem_buf);
9918 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9919 #else
9920 env->avr[n].u64[1] = ldq_p(mem_buf);
9921 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9922 #endif
9923 return 16;
9924 }
9925 if (n == 32) {
9926 env->vscr = ldl_p(mem_buf);
9927 return 4;
9928 }
9929 if (n == 33) {
9930 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9931 return 4;
9932 }
9933 return 0;
9934 }
9935
9936 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9937 {
9938 if (n < 32) {
9939 #if defined(TARGET_PPC64)
9940 stl_p(mem_buf, env->gpr[n] >> 32);
9941 #else
9942 stl_p(mem_buf, env->gprh[n]);
9943 #endif
9944 return 4;
9945 }
9946 if (n == 32) {
9947 stq_p(mem_buf, env->spe_acc);
9948 return 8;
9949 }
9950 if (n == 33) {
9951 stl_p(mem_buf, env->spe_fscr);
9952 return 4;
9953 }
9954 return 0;
9955 }
9956
9957 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9958 {
9959 if (n < 32) {
9960 #if defined(TARGET_PPC64)
9961 target_ulong lo = (uint32_t)env->gpr[n];
9962 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9963 env->gpr[n] = lo | hi;
9964 #else
9965 env->gprh[n] = ldl_p(mem_buf);
9966 #endif
9967 return 4;
9968 }
9969 if (n == 32) {
9970 env->spe_acc = ldq_p(mem_buf);
9971 return 8;
9972 }
9973 if (n == 33) {
9974 env->spe_fscr = ldl_p(mem_buf);
9975 return 4;
9976 }
9977 return 0;
9978 }
9979
9980 static int ppc_fixup_cpu(PowerPCCPU *cpu)
9981 {
9982 CPUPPCState *env = &cpu->env;
9983
9984 /* TCG doesn't (yet) emulate some groups of instructions that
9985 * are implemented on some otherwise supported CPUs (e.g. VSX
9986 * and decimal floating point instructions on POWER7). We
9987 * remove unsupported instruction groups from the cpu state's
9988 * instruction masks and hope the guest can cope. For at
9989 * least the pseries machine, the unavailability of these
9990 * instructions can be advertised to the guest via the device
9991 * tree. */
9992 if ((env->insns_flags & ~PPC_TCG_INSNS)
9993 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
9994 fprintf(stderr, "Warning: Disabling some instructions which are not "
9995 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
9996 env->insns_flags & ~PPC_TCG_INSNS,
9997 env->insns_flags2 & ~PPC_TCG_INSNS2);
9998 }
9999 env->insns_flags &= PPC_TCG_INSNS;
10000 env->insns_flags2 &= PPC_TCG_INSNS2;
10001 return 0;
10002 }
10003
10004 static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
10005 {
10006 PowerPCCPU *cpu = POWERPC_CPU(dev);
10007 CPUPPCState *env = &cpu->env;
10008 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10009 Error *local_err = NULL;
10010 #if !defined(CONFIG_USER_ONLY)
10011 int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
10012 #endif
10013
10014 #if !defined(CONFIG_USER_ONLY)
10015 if (smp_threads > max_smt) {
10016 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
10017 max_smt, kvm_enabled() ? "KVM" : "TCG");
10018 return;
10019 }
10020 #endif
10021
10022 if (kvm_enabled()) {
10023 if (kvmppc_fixup_cpu(cpu) != 0) {
10024 error_setg(errp, "Unable to virtualize selected CPU with KVM");
10025 return;
10026 }
10027 } else {
10028 if (ppc_fixup_cpu(cpu) != 0) {
10029 error_setg(errp, "Unable to emulate selected CPU with TCG");
10030 return;
10031 }
10032 }
10033
10034 #if defined(TARGET_PPCEMB)
10035 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
10036 error_setg(errp, "CPU does not possess a BookE MMU. "
10037 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
10038 "or choose another CPU model.");
10039 return;
10040 }
10041 #endif
10042
10043 create_ppc_opcodes(cpu, &local_err);
10044 if (local_err != NULL) {
10045 error_propagate(errp, local_err);
10046 return;
10047 }
10048 init_ppc_proc(cpu);
10049
10050 if (pcc->insns_flags & PPC_FLOAT) {
10051 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
10052 33, "power-fpu.xml", 0);
10053 }
10054 if (pcc->insns_flags & PPC_ALTIVEC) {
10055 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
10056 34, "power-altivec.xml", 0);
10057 }
10058 if (pcc->insns_flags & PPC_SPE) {
10059 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
10060 34, "power-spe.xml", 0);
10061 }
10062
10063 qemu_init_vcpu(env);
10064
10065 pcc->parent_realize(dev, errp);
10066
10067 #if defined(PPC_DUMP_CPU)
10068 {
10069 const char *mmu_model, *excp_model, *bus_model;
10070 switch (env->mmu_model) {
10071 case POWERPC_MMU_32B:
10072 mmu_model = "PowerPC 32";
10073 break;
10074 case POWERPC_MMU_SOFT_6xx:
10075 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
10076 break;
10077 case POWERPC_MMU_SOFT_74xx:
10078 mmu_model = "PowerPC 74xx with software driven TLBs";
10079 break;
10080 case POWERPC_MMU_SOFT_4xx:
10081 mmu_model = "PowerPC 4xx with software driven TLBs";
10082 break;
10083 case POWERPC_MMU_SOFT_4xx_Z:
10084 mmu_model = "PowerPC 4xx with software driven TLBs "
10085 "and zones protections";
10086 break;
10087 case POWERPC_MMU_REAL:
10088 mmu_model = "PowerPC real mode only";
10089 break;
10090 case POWERPC_MMU_MPC8xx:
10091 mmu_model = "PowerPC MPC8xx";
10092 break;
10093 case POWERPC_MMU_BOOKE:
10094 mmu_model = "PowerPC BookE";
10095 break;
10096 case POWERPC_MMU_BOOKE206:
10097 mmu_model = "PowerPC BookE 2.06";
10098 break;
10099 case POWERPC_MMU_601:
10100 mmu_model = "PowerPC 601";
10101 break;
10102 #if defined (TARGET_PPC64)
10103 case POWERPC_MMU_64B:
10104 mmu_model = "PowerPC 64";
10105 break;
10106 case POWERPC_MMU_620:
10107 mmu_model = "PowerPC 620";
10108 break;
10109 #endif
10110 default:
10111 mmu_model = "Unknown or invalid";
10112 break;
10113 }
10114 switch (env->excp_model) {
10115 case POWERPC_EXCP_STD:
10116 excp_model = "PowerPC";
10117 break;
10118 case POWERPC_EXCP_40x:
10119 excp_model = "PowerPC 40x";
10120 break;
10121 case POWERPC_EXCP_601:
10122 excp_model = "PowerPC 601";
10123 break;
10124 case POWERPC_EXCP_602:
10125 excp_model = "PowerPC 602";
10126 break;
10127 case POWERPC_EXCP_603:
10128 excp_model = "PowerPC 603";
10129 break;
10130 case POWERPC_EXCP_603E:
10131 excp_model = "PowerPC 603e";
10132 break;
10133 case POWERPC_EXCP_604:
10134 excp_model = "PowerPC 604";
10135 break;
10136 case POWERPC_EXCP_7x0:
10137 excp_model = "PowerPC 740/750";
10138 break;
10139 case POWERPC_EXCP_7x5:
10140 excp_model = "PowerPC 745/755";
10141 break;
10142 case POWERPC_EXCP_74xx:
10143 excp_model = "PowerPC 74xx";
10144 break;
10145 case POWERPC_EXCP_BOOKE:
10146 excp_model = "PowerPC BookE";
10147 break;
10148 #if defined (TARGET_PPC64)
10149 case POWERPC_EXCP_970:
10150 excp_model = "PowerPC 970";
10151 break;
10152 #endif
10153 default:
10154 excp_model = "Unknown or invalid";
10155 break;
10156 }
10157 switch (env->bus_model) {
10158 case PPC_FLAGS_INPUT_6xx:
10159 bus_model = "PowerPC 6xx";
10160 break;
10161 case PPC_FLAGS_INPUT_BookE:
10162 bus_model = "PowerPC BookE";
10163 break;
10164 case PPC_FLAGS_INPUT_405:
10165 bus_model = "PowerPC 405";
10166 break;
10167 case PPC_FLAGS_INPUT_401:
10168 bus_model = "PowerPC 401/403";
10169 break;
10170 case PPC_FLAGS_INPUT_RCPU:
10171 bus_model = "RCPU / MPC8xx";
10172 break;
10173 #if defined (TARGET_PPC64)
10174 case PPC_FLAGS_INPUT_970:
10175 bus_model = "PowerPC 970";
10176 break;
10177 #endif
10178 default:
10179 bus_model = "Unknown or invalid";
10180 break;
10181 }
10182 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
10183 " MMU model : %s\n",
10184 pcc->name, pcc->pvr, pcc->msr_mask, mmu_model);
10185 #if !defined(CONFIG_USER_ONLY)
10186 if (env->tlb != NULL) {
10187 printf(" %d %s TLB in %d ways\n",
10188 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
10189 env->nb_ways);
10190 }
10191 #endif
10192 printf(" Exceptions model : %s\n"
10193 " Bus model : %s\n",
10194 excp_model, bus_model);
10195 printf(" MSR features :\n");
10196 if (env->flags & POWERPC_FLAG_SPE)
10197 printf(" signal processing engine enable"
10198 "\n");
10199 else if (env->flags & POWERPC_FLAG_VRE)
10200 printf(" vector processor enable\n");
10201 if (env->flags & POWERPC_FLAG_TGPR)
10202 printf(" temporary GPRs\n");
10203 else if (env->flags & POWERPC_FLAG_CE)
10204 printf(" critical input enable\n");
10205 if (env->flags & POWERPC_FLAG_SE)
10206 printf(" single-step trace mode\n");
10207 else if (env->flags & POWERPC_FLAG_DWE)
10208 printf(" debug wait enable\n");
10209 else if (env->flags & POWERPC_FLAG_UBLE)
10210 printf(" user BTB lock enable\n");
10211 if (env->flags & POWERPC_FLAG_BE)
10212 printf(" branch-step trace mode\n");
10213 else if (env->flags & POWERPC_FLAG_DE)
10214 printf(" debug interrupt enable\n");
10215 if (env->flags & POWERPC_FLAG_PX)
10216 printf(" inclusive protection\n");
10217 else if (env->flags & POWERPC_FLAG_PMM)
10218 printf(" performance monitor mark\n");
10219 if (env->flags == POWERPC_FLAG_NONE)
10220 printf(" none\n");
10221 printf(" Time-base/decrementer clock source: %s\n",
10222 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
10223 }
10224 dump_ppc_insns(env);
10225 dump_ppc_sprs(env);
10226 fflush(stdout);
10227 #endif
10228 }
10229
10230 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
10231 {
10232 ObjectClass *oc = (ObjectClass *)a;
10233 uint32_t pvr = *(uint32_t *)b;
10234 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
10235
10236 /* -cpu host does a PVR lookup during construction */
10237 if (unlikely(strcmp(object_class_get_name(oc),
10238 TYPE_HOST_POWERPC_CPU) == 0)) {
10239 return -1;
10240 }
10241
10242 #if defined(TARGET_PPCEMB)
10243 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
10244 return -1;
10245 }
10246 #endif
10247
10248 return pcc->pvr == pvr ? 0 : -1;
10249 }
10250
10251 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
10252 {
10253 GSList *list, *item;
10254 PowerPCCPUClass *pcc = NULL;
10255
10256 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10257 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
10258 if (item != NULL) {
10259 pcc = POWERPC_CPU_CLASS(item->data);
10260 }
10261 g_slist_free(list);
10262
10263 return pcc;
10264 }
10265
10266 static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
10267 {
10268 ObjectClass *oc = (ObjectClass *)a;
10269 const char *name = b;
10270 #if defined(TARGET_PPCEMB)
10271 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10272 #endif
10273
10274 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
10275 #if defined(TARGET_PPCEMB)
10276 pcc->mmu_model == POWERPC_MMU_BOOKE &&
10277 #endif
10278 strcmp(object_class_get_name(oc) + strlen(name),
10279 "-" TYPE_POWERPC_CPU) == 0) {
10280 return 0;
10281 }
10282 return -1;
10283 }
10284
10285 #include <ctype.h>
10286
10287 static ObjectClass *ppc_cpu_class_by_name(const char *name)
10288 {
10289 GSList *list, *item;
10290 ObjectClass *ret = NULL;
10291 const char *p;
10292 int i, len;
10293
10294 if (strcasecmp(name, "host") == 0) {
10295 if (kvm_enabled()) {
10296 ret = object_class_by_name(TYPE_HOST_POWERPC_CPU);
10297 }
10298 return ret;
10299 }
10300
10301 /* Check if the given name is a PVR */
10302 len = strlen(name);
10303 if (len == 10 && name[0] == '0' && name[1] == 'x') {
10304 p = name + 2;
10305 goto check_pvr;
10306 } else if (len == 8) {
10307 p = name;
10308 check_pvr:
10309 for (i = 0; i < 8; i++) {
10310 if (!qemu_isxdigit(*p++))
10311 break;
10312 }
10313 if (i == 8) {
10314 ret = OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
10315 return ret;
10316 }
10317 }
10318
10319 for (i = 0; i < ARRAY_SIZE(ppc_cpu_aliases); i++) {
10320 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
10321 return ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
10322 }
10323 }
10324
10325 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10326 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
10327 if (item != NULL) {
10328 ret = OBJECT_CLASS(item->data);
10329 }
10330 g_slist_free(list);
10331
10332 return ret;
10333 }
10334
10335 PowerPCCPU *cpu_ppc_init(const char *cpu_model)
10336 {
10337 PowerPCCPU *cpu;
10338 CPUPPCState *env;
10339 ObjectClass *oc;
10340 Error *err = NULL;
10341
10342 oc = ppc_cpu_class_by_name(cpu_model);
10343 if (oc == NULL) {
10344 return NULL;
10345 }
10346
10347 cpu = POWERPC_CPU(object_new(object_class_get_name(oc)));
10348 env = &cpu->env;
10349 env->cpu_model_str = cpu_model;
10350
10351 object_property_set_bool(OBJECT(cpu), true, "realized", &err);
10352 if (err != NULL) {
10353 fprintf(stderr, "%s\n", error_get_pretty(err));
10354 error_free(err);
10355 object_unref(OBJECT(cpu));
10356 return NULL;
10357 }
10358
10359 return cpu;
10360 }
10361
10362 /* Sort by PVR, ordering special case "host" last. */
10363 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
10364 {
10365 ObjectClass *oc_a = (ObjectClass *)a;
10366 ObjectClass *oc_b = (ObjectClass *)b;
10367 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
10368 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
10369 const char *name_a = object_class_get_name(oc_a);
10370 const char *name_b = object_class_get_name(oc_b);
10371
10372 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
10373 return 1;
10374 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
10375 return -1;
10376 } else {
10377 /* Avoid an integer overflow during subtraction */
10378 if (pcc_a->pvr < pcc_b->pvr) {
10379 return -1;
10380 } else if (pcc_a->pvr > pcc_b->pvr) {
10381 return 1;
10382 } else {
10383 return 0;
10384 }
10385 }
10386 }
10387
10388 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
10389 {
10390 ObjectClass *oc = data;
10391 CPUListState *s = user_data;
10392 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10393 const char *typename = object_class_get_name(oc);
10394 char *name;
10395
10396 #if defined(TARGET_PPCEMB)
10397 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
10398 return;
10399 }
10400 #endif
10401
10402 name = g_strndup(typename,
10403 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
10404 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
10405 name, pcc->pvr);
10406 g_free(name);
10407 }
10408
10409 void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
10410 {
10411 CPUListState s = {
10412 .file = f,
10413 .cpu_fprintf = cpu_fprintf,
10414 };
10415 GSList *list;
10416 int i;
10417
10418 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10419 list = g_slist_sort(list, ppc_cpu_list_compare);
10420 g_slist_foreach(list, ppc_cpu_list_entry, &s);
10421 g_slist_free(list);
10422
10423 cpu_fprintf(f, "\n");
10424 for (i = 0; i < ARRAY_SIZE(ppc_cpu_aliases); i++) {
10425 ObjectClass *oc = ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
10426 if (oc == NULL) {
10427 /* Hide aliases that point to a TODO or TODO_USER_ONLY model */
10428 continue;
10429 }
10430 cpu_fprintf(f, "PowerPC %-16s\n",
10431 ppc_cpu_aliases[i].alias);
10432 }
10433 }
10434
10435 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
10436 {
10437 ObjectClass *oc = data;
10438 CpuDefinitionInfoList **first = user_data;
10439 const char *typename;
10440 CpuDefinitionInfoList *entry;
10441 CpuDefinitionInfo *info;
10442 #if defined(TARGET_PPCEMB)
10443 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10444
10445 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
10446 return;
10447 }
10448 #endif
10449
10450 typename = object_class_get_name(oc);
10451 info = g_malloc0(sizeof(*info));
10452 info->name = g_strndup(typename,
10453 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
10454
10455 entry = g_malloc0(sizeof(*entry));
10456 entry->value = info;
10457 entry->next = *first;
10458 *first = entry;
10459 }
10460
10461 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
10462 {
10463 CpuDefinitionInfoList *cpu_list = NULL;
10464 GSList *list;
10465
10466 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10467 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
10468 g_slist_free(list);
10469
10470 return cpu_list;
10471 }
10472
10473 /* CPUClass::reset() */
10474 static void ppc_cpu_reset(CPUState *s)
10475 {
10476 PowerPCCPU *cpu = POWERPC_CPU(s);
10477 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10478 CPUPPCState *env = &cpu->env;
10479 target_ulong msr;
10480
10481 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
10482 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
10483 log_cpu_state(env, 0);
10484 }
10485
10486 pcc->parent_reset(s);
10487
10488 msr = (target_ulong)0;
10489 if (0) {
10490 /* XXX: find a suitable condition to enable the hypervisor mode */
10491 msr |= (target_ulong)MSR_HVB;
10492 }
10493 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
10494 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
10495 msr |= (target_ulong)1 << MSR_EP;
10496 #if defined(DO_SINGLE_STEP) && 0
10497 /* Single step trace mode */
10498 msr |= (target_ulong)1 << MSR_SE;
10499 msr |= (target_ulong)1 << MSR_BE;
10500 #endif
10501 #if defined(CONFIG_USER_ONLY)
10502 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
10503 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
10504 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
10505 msr |= (target_ulong)1 << MSR_PR;
10506 #else
10507 env->excp_prefix = env->hreset_excp_prefix;
10508 env->nip = env->hreset_vector | env->excp_prefix;
10509 if (env->mmu_model != POWERPC_MMU_REAL) {
10510 ppc_tlb_invalidate_all(env);
10511 }
10512 #endif
10513 env->msr = msr & env->msr_mask;
10514 #if defined(TARGET_PPC64)
10515 if (env->mmu_model & POWERPC_MMU_64) {
10516 env->msr |= (1ULL << MSR_SF);
10517 }
10518 #endif
10519 hreg_compute_hflags(env);
10520 env->reserve_addr = (target_ulong)-1ULL;
10521 /* Be sure no exception or interrupt is pending */
10522 env->pending_interrupts = 0;
10523 env->exception_index = POWERPC_EXCP_NONE;
10524 env->error_code = 0;
10525
10526 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
10527 env->vpa_addr = 0;
10528 env->slb_shadow_addr = 0;
10529 env->slb_shadow_size = 0;
10530 env->dtl_addr = 0;
10531 env->dtl_size = 0;
10532 #endif /* TARGET_PPC64 */
10533
10534 /* Flush all TLBs */
10535 tlb_flush(env, 1);
10536 }
10537
10538 static void ppc_cpu_initfn(Object *obj)
10539 {
10540 CPUState *cs = CPU(obj);
10541 PowerPCCPU *cpu = POWERPC_CPU(obj);
10542 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10543 CPUPPCState *env = &cpu->env;
10544
10545 cs->env_ptr = env;
10546 cpu_exec_init(env);
10547
10548 env->msr_mask = pcc->msr_mask;
10549 env->mmu_model = pcc->mmu_model;
10550 env->excp_model = pcc->excp_model;
10551 env->bus_model = pcc->bus_model;
10552 env->insns_flags = pcc->insns_flags;
10553 env->insns_flags2 = pcc->insns_flags2;
10554 env->flags = pcc->flags;
10555 env->bfd_mach = pcc->bfd_mach;
10556 env->check_pow = pcc->check_pow;
10557
10558 #if defined(TARGET_PPC64)
10559 if (pcc->sps) {
10560 env->sps = *pcc->sps;
10561 } else if (env->mmu_model & POWERPC_MMU_64) {
10562 /* Use default sets of page sizes */
10563 static const struct ppc_segment_page_sizes defsps = {
10564 .sps = {
10565 { .page_shift = 12, /* 4K */
10566 .slb_enc = 0,
10567 .enc = { { .page_shift = 12, .pte_enc = 0 } }
10568 },
10569 { .page_shift = 24, /* 16M */
10570 .slb_enc = 0x100,
10571 .enc = { { .page_shift = 24, .pte_enc = 0 } }
10572 },
10573 },
10574 };
10575 env->sps = defsps;
10576 }
10577 #endif /* defined(TARGET_PPC64) */
10578
10579 if (tcg_enabled()) {
10580 ppc_translate_init();
10581 }
10582 }
10583
10584 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
10585 {
10586 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10587 CPUClass *cc = CPU_CLASS(oc);
10588 DeviceClass *dc = DEVICE_CLASS(oc);
10589
10590 pcc->parent_realize = dc->realize;
10591 dc->realize = ppc_cpu_realizefn;
10592
10593 pcc->parent_reset = cc->reset;
10594 cc->reset = ppc_cpu_reset;
10595
10596 cc->class_by_name = ppc_cpu_class_by_name;
10597 }
10598
10599 static const TypeInfo ppc_cpu_type_info = {
10600 .name = TYPE_POWERPC_CPU,
10601 .parent = TYPE_CPU,
10602 .instance_size = sizeof(PowerPCCPU),
10603 .instance_init = ppc_cpu_initfn,
10604 .abstract = true,
10605 .class_size = sizeof(PowerPCCPUClass),
10606 .class_init = ppc_cpu_class_init,
10607 };
10608
10609 static void ppc_cpu_register_types(void)
10610 {
10611 type_register_static(&ppc_cpu_type_info);
10612 }
10613
10614 type_init(ppc_cpu_register_types)
Qemu copy for testing