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Reorganize the CPUPPCState structure to group features.
[qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26 #include "dis-asm.h"
27
28 //#define PPC_DUMP_CPU
29 //#define PPC_DEBUG_SPR
30 //#define PPC_DEBUG_IRQ
31
32 struct ppc_def_t {
33 const unsigned char *name;
34 uint32_t pvr;
35 uint32_t pvr_mask;
36 uint64_t insns_flags;
37 uint64_t msr_mask;
38 uint8_t mmu_model;
39 uint8_t excp_model;
40 uint8_t bus_model;
41 uint8_t pad;
42 uint32_t flags;
43 int bfd_mach;
44 void (*init_proc)(CPUPPCState *env);
45 };
46
47 /* For user-mode emulation, we don't emulate any IRQ controller */
48 #if defined(CONFIG_USER_ONLY)
49 #define PPC_IRQ_INIT_FN(name) \
50 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
51 { \
52 }
53 #else
54 #define PPC_IRQ_INIT_FN(name) \
55 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
56 #endif
57
58 PPC_IRQ_INIT_FN(40x);
59 PPC_IRQ_INIT_FN(6xx);
60 PPC_IRQ_INIT_FN(970);
61
62 /* Generic callbacks:
63 * do nothing but store/retrieve spr value
64 */
65 #ifdef PPC_DUMP_SPR_ACCESSES
66 static void spr_read_generic (void *opaque, int sprn)
67 {
68 gen_op_load_dump_spr(sprn);
69 }
70
71 static void spr_write_generic (void *opaque, int sprn)
72 {
73 gen_op_store_dump_spr(sprn);
74 }
75 #else
76 static void spr_read_generic (void *opaque, int sprn)
77 {
78 gen_op_load_spr(sprn);
79 }
80
81 static void spr_write_generic (void *opaque, int sprn)
82 {
83 gen_op_store_spr(sprn);
84 }
85 #endif
86
87 #if !defined(CONFIG_USER_ONLY)
88 static void spr_write_clear (void *opaque, int sprn)
89 {
90 gen_op_mask_spr(sprn);
91 }
92 #endif
93
94 /* SPR common to all PowerPC */
95 /* XER */
96 static void spr_read_xer (void *opaque, int sprn)
97 {
98 gen_op_load_xer();
99 }
100
101 static void spr_write_xer (void *opaque, int sprn)
102 {
103 gen_op_store_xer();
104 }
105
106 /* LR */
107 static void spr_read_lr (void *opaque, int sprn)
108 {
109 gen_op_load_lr();
110 }
111
112 static void spr_write_lr (void *opaque, int sprn)
113 {
114 gen_op_store_lr();
115 }
116
117 /* CTR */
118 static void spr_read_ctr (void *opaque, int sprn)
119 {
120 gen_op_load_ctr();
121 }
122
123 static void spr_write_ctr (void *opaque, int sprn)
124 {
125 gen_op_store_ctr();
126 }
127
128 /* User read access to SPR */
129 /* USPRx */
130 /* UMMCRx */
131 /* UPMCx */
132 /* USIA */
133 /* UDECR */
134 static void spr_read_ureg (void *opaque, int sprn)
135 {
136 gen_op_load_spr(sprn + 0x10);
137 }
138
139 /* SPR common to all non-embedded PowerPC */
140 /* DECR */
141 #if !defined(CONFIG_USER_ONLY)
142 static void spr_read_decr (void *opaque, int sprn)
143 {
144 gen_op_load_decr();
145 }
146
147 static void spr_write_decr (void *opaque, int sprn)
148 {
149 gen_op_store_decr();
150 }
151 #endif
152
153 /* SPR common to all non-embedded PowerPC, except 601 */
154 /* Time base */
155 static void spr_read_tbl (void *opaque, int sprn)
156 {
157 gen_op_load_tbl();
158 }
159
160 static void spr_read_tbu (void *opaque, int sprn)
161 {
162 gen_op_load_tbu();
163 }
164
165 __attribute__ (( unused ))
166 static void spr_read_atbl (void *opaque, int sprn)
167 {
168 gen_op_load_atbl();
169 }
170
171 __attribute__ (( unused ))
172 static void spr_read_atbu (void *opaque, int sprn)
173 {
174 gen_op_load_atbu();
175 }
176
177 #if !defined(CONFIG_USER_ONLY)
178 static void spr_write_tbl (void *opaque, int sprn)
179 {
180 gen_op_store_tbl();
181 }
182
183 static void spr_write_tbu (void *opaque, int sprn)
184 {
185 gen_op_store_tbu();
186 }
187
188 __attribute__ (( unused ))
189 static void spr_write_atbl (void *opaque, int sprn)
190 {
191 gen_op_store_atbl();
192 }
193
194 __attribute__ (( unused ))
195 static void spr_write_atbu (void *opaque, int sprn)
196 {
197 gen_op_store_atbu();
198 }
199 #endif
200
201 #if !defined(CONFIG_USER_ONLY)
202 /* IBAT0U...IBAT0U */
203 /* IBAT0L...IBAT7L */
204 static void spr_read_ibat (void *opaque, int sprn)
205 {
206 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
207 }
208
209 static void spr_read_ibat_h (void *opaque, int sprn)
210 {
211 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
212 }
213
214 static void spr_write_ibatu (void *opaque, int sprn)
215 {
216 gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
217 }
218
219 static void spr_write_ibatu_h (void *opaque, int sprn)
220 {
221 gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
222 }
223
224 static void spr_write_ibatl (void *opaque, int sprn)
225 {
226 gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
227 }
228
229 static void spr_write_ibatl_h (void *opaque, int sprn)
230 {
231 gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
232 }
233
234 /* DBAT0U...DBAT7U */
235 /* DBAT0L...DBAT7L */
236 static void spr_read_dbat (void *opaque, int sprn)
237 {
238 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
239 }
240
241 static void spr_read_dbat_h (void *opaque, int sprn)
242 {
243 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
244 }
245
246 static void spr_write_dbatu (void *opaque, int sprn)
247 {
248 gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
249 }
250
251 static void spr_write_dbatu_h (void *opaque, int sprn)
252 {
253 gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
254 }
255
256 static void spr_write_dbatl (void *opaque, int sprn)
257 {
258 gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
259 }
260
261 static void spr_write_dbatl_h (void *opaque, int sprn)
262 {
263 gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
264 }
265
266 /* SDR1 */
267 static void spr_read_sdr1 (void *opaque, int sprn)
268 {
269 gen_op_load_sdr1();
270 }
271
272 static void spr_write_sdr1 (void *opaque, int sprn)
273 {
274 gen_op_store_sdr1();
275 }
276
277 /* 64 bits PowerPC specific SPRs */
278 /* ASR */
279 #if defined(TARGET_PPC64)
280 __attribute__ (( unused ))
281 static void spr_read_asr (void *opaque, int sprn)
282 {
283 gen_op_load_asr();
284 }
285
286 __attribute__ (( unused ))
287 static void spr_write_asr (void *opaque, int sprn)
288 {
289 gen_op_store_asr();
290 }
291 #endif
292 #endif
293
294 /* PowerPC 601 specific registers */
295 /* RTC */
296 static void spr_read_601_rtcl (void *opaque, int sprn)
297 {
298 gen_op_load_601_rtcl();
299 }
300
301 static void spr_read_601_rtcu (void *opaque, int sprn)
302 {
303 gen_op_load_601_rtcu();
304 }
305
306 #if !defined(CONFIG_USER_ONLY)
307 static void spr_write_601_rtcu (void *opaque, int sprn)
308 {
309 gen_op_store_601_rtcu();
310 }
311
312 static void spr_write_601_rtcl (void *opaque, int sprn)
313 {
314 gen_op_store_601_rtcl();
315 }
316 #endif
317
318 /* Unified bats */
319 #if !defined(CONFIG_USER_ONLY)
320 static void spr_read_601_ubat (void *opaque, int sprn)
321 {
322 gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
323 }
324
325 static void spr_write_601_ubatu (void *opaque, int sprn)
326 {
327 gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
328 }
329
330 static void spr_write_601_ubatl (void *opaque, int sprn)
331 {
332 gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
333 }
334 #endif
335
336 /* PowerPC 40x specific registers */
337 #if !defined(CONFIG_USER_ONLY)
338 static void spr_read_40x_pit (void *opaque, int sprn)
339 {
340 gen_op_load_40x_pit();
341 }
342
343 static void spr_write_40x_pit (void *opaque, int sprn)
344 {
345 gen_op_store_40x_pit();
346 }
347
348 static void spr_write_40x_dbcr0 (void *opaque, int sprn)
349 {
350 DisasContext *ctx = opaque;
351
352 gen_op_store_40x_dbcr0();
353 /* We must stop translation as we may have rebooted */
354 GEN_STOP(ctx);
355 }
356
357 static void spr_write_40x_sler (void *opaque, int sprn)
358 {
359 gen_op_store_40x_sler();
360 }
361
362 static void spr_write_booke_tcr (void *opaque, int sprn)
363 {
364 gen_op_store_booke_tcr();
365 }
366
367 static void spr_write_booke_tsr (void *opaque, int sprn)
368 {
369 gen_op_store_booke_tsr();
370 }
371 #endif
372
373 /* PowerPC 403 specific registers */
374 /* PBL1 / PBU1 / PBL2 / PBU2 */
375 #if !defined(CONFIG_USER_ONLY)
376 static void spr_read_403_pbr (void *opaque, int sprn)
377 {
378 gen_op_load_403_pb(sprn - SPR_403_PBL1);
379 }
380
381 static void spr_write_403_pbr (void *opaque, int sprn)
382 {
383 gen_op_store_403_pb(sprn - SPR_403_PBL1);
384 }
385
386 static void spr_write_pir (void *opaque, int sprn)
387 {
388 gen_op_store_pir();
389 }
390 #endif
391
392 #if !defined(CONFIG_USER_ONLY)
393 /* Callback used to write the exception vector base */
394 static void spr_write_excp_prefix (void *opaque, int sprn)
395 {
396 gen_op_store_excp_prefix();
397 gen_op_store_spr(sprn);
398 }
399
400 static void spr_write_excp_vector (void *opaque, int sprn)
401 {
402 DisasContext *ctx = opaque;
403
404 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
405 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR0);
406 gen_op_store_spr(sprn);
407 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
408 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR32 + 32);
409 gen_op_store_spr(sprn);
410 } else {
411 printf("Trying to write an unknown exception vector %d %03x\n",
412 sprn, sprn);
413 GEN_EXCP_PRIVREG(ctx);
414 }
415 }
416 #endif
417
418 #if defined(CONFIG_USER_ONLY)
419 #define spr_register(env, num, name, uea_read, uea_write, \
420 oea_read, oea_write, initial_value) \
421 do { \
422 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
423 } while (0)
424 static inline void _spr_register (CPUPPCState *env, int num,
425 const unsigned char *name,
426 void (*uea_read)(void *opaque, int sprn),
427 void (*uea_write)(void *opaque, int sprn),
428 target_ulong initial_value)
429 #else
430 static inline void spr_register (CPUPPCState *env, int num,
431 const unsigned char *name,
432 void (*uea_read)(void *opaque, int sprn),
433 void (*uea_write)(void *opaque, int sprn),
434 void (*oea_read)(void *opaque, int sprn),
435 void (*oea_write)(void *opaque, int sprn),
436 target_ulong initial_value)
437 #endif
438 {
439 ppc_spr_t *spr;
440
441 spr = &env->spr_cb[num];
442 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
443 #if !defined(CONFIG_USER_ONLY)
444 spr->oea_read != NULL || spr->oea_write != NULL ||
445 #endif
446 spr->uea_read != NULL || spr->uea_write != NULL) {
447 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
448 exit(1);
449 }
450 #if defined(PPC_DEBUG_SPR)
451 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
452 initial_value);
453 #endif
454 spr->name = name;
455 spr->uea_read = uea_read;
456 spr->uea_write = uea_write;
457 #if !defined(CONFIG_USER_ONLY)
458 spr->oea_read = oea_read;
459 spr->oea_write = oea_write;
460 #endif
461 env->spr[num] = initial_value;
462 }
463
464 /* Generic PowerPC SPRs */
465 static void gen_spr_generic (CPUPPCState *env)
466 {
467 /* Integer processing */
468 spr_register(env, SPR_XER, "XER",
469 &spr_read_xer, &spr_write_xer,
470 &spr_read_xer, &spr_write_xer,
471 0x00000000);
472 /* Branch contol */
473 spr_register(env, SPR_LR, "LR",
474 &spr_read_lr, &spr_write_lr,
475 &spr_read_lr, &spr_write_lr,
476 0x00000000);
477 spr_register(env, SPR_CTR, "CTR",
478 &spr_read_ctr, &spr_write_ctr,
479 &spr_read_ctr, &spr_write_ctr,
480 0x00000000);
481 /* Interrupt processing */
482 spr_register(env, SPR_SRR0, "SRR0",
483 SPR_NOACCESS, SPR_NOACCESS,
484 &spr_read_generic, &spr_write_generic,
485 0x00000000);
486 spr_register(env, SPR_SRR1, "SRR1",
487 SPR_NOACCESS, SPR_NOACCESS,
488 &spr_read_generic, &spr_write_generic,
489 0x00000000);
490 /* Processor control */
491 spr_register(env, SPR_SPRG0, "SPRG0",
492 SPR_NOACCESS, SPR_NOACCESS,
493 &spr_read_generic, &spr_write_generic,
494 0x00000000);
495 spr_register(env, SPR_SPRG1, "SPRG1",
496 SPR_NOACCESS, SPR_NOACCESS,
497 &spr_read_generic, &spr_write_generic,
498 0x00000000);
499 spr_register(env, SPR_SPRG2, "SPRG2",
500 SPR_NOACCESS, SPR_NOACCESS,
501 &spr_read_generic, &spr_write_generic,
502 0x00000000);
503 spr_register(env, SPR_SPRG3, "SPRG3",
504 SPR_NOACCESS, SPR_NOACCESS,
505 &spr_read_generic, &spr_write_generic,
506 0x00000000);
507 }
508
509 /* SPR common to all non-embedded PowerPC, including 601 */
510 static void gen_spr_ne_601 (CPUPPCState *env)
511 {
512 /* Exception processing */
513 spr_register(env, SPR_DSISR, "DSISR",
514 SPR_NOACCESS, SPR_NOACCESS,
515 &spr_read_generic, &spr_write_generic,
516 0x00000000);
517 spr_register(env, SPR_DAR, "DAR",
518 SPR_NOACCESS, SPR_NOACCESS,
519 &spr_read_generic, &spr_write_generic,
520 0x00000000);
521 /* Timer */
522 spr_register(env, SPR_DECR, "DECR",
523 SPR_NOACCESS, SPR_NOACCESS,
524 &spr_read_decr, &spr_write_decr,
525 0x00000000);
526 /* Memory management */
527 spr_register(env, SPR_SDR1, "SDR1",
528 SPR_NOACCESS, SPR_NOACCESS,
529 &spr_read_sdr1, &spr_write_sdr1,
530 0x00000000);
531 }
532
533 /* BATs 0-3 */
534 static void gen_low_BATs (CPUPPCState *env)
535 {
536 #if !defined(CONFIG_USER_ONLY)
537 spr_register(env, SPR_IBAT0U, "IBAT0U",
538 SPR_NOACCESS, SPR_NOACCESS,
539 &spr_read_ibat, &spr_write_ibatu,
540 0x00000000);
541 spr_register(env, SPR_IBAT0L, "IBAT0L",
542 SPR_NOACCESS, SPR_NOACCESS,
543 &spr_read_ibat, &spr_write_ibatl,
544 0x00000000);
545 spr_register(env, SPR_IBAT1U, "IBAT1U",
546 SPR_NOACCESS, SPR_NOACCESS,
547 &spr_read_ibat, &spr_write_ibatu,
548 0x00000000);
549 spr_register(env, SPR_IBAT1L, "IBAT1L",
550 SPR_NOACCESS, SPR_NOACCESS,
551 &spr_read_ibat, &spr_write_ibatl,
552 0x00000000);
553 spr_register(env, SPR_IBAT2U, "IBAT2U",
554 SPR_NOACCESS, SPR_NOACCESS,
555 &spr_read_ibat, &spr_write_ibatu,
556 0x00000000);
557 spr_register(env, SPR_IBAT2L, "IBAT2L",
558 SPR_NOACCESS, SPR_NOACCESS,
559 &spr_read_ibat, &spr_write_ibatl,
560 0x00000000);
561 spr_register(env, SPR_IBAT3U, "IBAT3U",
562 SPR_NOACCESS, SPR_NOACCESS,
563 &spr_read_ibat, &spr_write_ibatu,
564 0x00000000);
565 spr_register(env, SPR_IBAT3L, "IBAT3L",
566 SPR_NOACCESS, SPR_NOACCESS,
567 &spr_read_ibat, &spr_write_ibatl,
568 0x00000000);
569 spr_register(env, SPR_DBAT0U, "DBAT0U",
570 SPR_NOACCESS, SPR_NOACCESS,
571 &spr_read_dbat, &spr_write_dbatu,
572 0x00000000);
573 spr_register(env, SPR_DBAT0L, "DBAT0L",
574 SPR_NOACCESS, SPR_NOACCESS,
575 &spr_read_dbat, &spr_write_dbatl,
576 0x00000000);
577 spr_register(env, SPR_DBAT1U, "DBAT1U",
578 SPR_NOACCESS, SPR_NOACCESS,
579 &spr_read_dbat, &spr_write_dbatu,
580 0x00000000);
581 spr_register(env, SPR_DBAT1L, "DBAT1L",
582 SPR_NOACCESS, SPR_NOACCESS,
583 &spr_read_dbat, &spr_write_dbatl,
584 0x00000000);
585 spr_register(env, SPR_DBAT2U, "DBAT2U",
586 SPR_NOACCESS, SPR_NOACCESS,
587 &spr_read_dbat, &spr_write_dbatu,
588 0x00000000);
589 spr_register(env, SPR_DBAT2L, "DBAT2L",
590 SPR_NOACCESS, SPR_NOACCESS,
591 &spr_read_dbat, &spr_write_dbatl,
592 0x00000000);
593 spr_register(env, SPR_DBAT3U, "DBAT3U",
594 SPR_NOACCESS, SPR_NOACCESS,
595 &spr_read_dbat, &spr_write_dbatu,
596 0x00000000);
597 spr_register(env, SPR_DBAT3L, "DBAT3L",
598 SPR_NOACCESS, SPR_NOACCESS,
599 &spr_read_dbat, &spr_write_dbatl,
600 0x00000000);
601 env->nb_BATs += 4;
602 #endif
603 }
604
605 /* BATs 4-7 */
606 static void gen_high_BATs (CPUPPCState *env)
607 {
608 #if !defined(CONFIG_USER_ONLY)
609 spr_register(env, SPR_IBAT4U, "IBAT4U",
610 SPR_NOACCESS, SPR_NOACCESS,
611 &spr_read_ibat_h, &spr_write_ibatu_h,
612 0x00000000);
613 spr_register(env, SPR_IBAT4L, "IBAT4L",
614 SPR_NOACCESS, SPR_NOACCESS,
615 &spr_read_ibat_h, &spr_write_ibatl_h,
616 0x00000000);
617 spr_register(env, SPR_IBAT5U, "IBAT5U",
618 SPR_NOACCESS, SPR_NOACCESS,
619 &spr_read_ibat_h, &spr_write_ibatu_h,
620 0x00000000);
621 spr_register(env, SPR_IBAT5L, "IBAT5L",
622 SPR_NOACCESS, SPR_NOACCESS,
623 &spr_read_ibat_h, &spr_write_ibatl_h,
624 0x00000000);
625 spr_register(env, SPR_IBAT6U, "IBAT6U",
626 SPR_NOACCESS, SPR_NOACCESS,
627 &spr_read_ibat_h, &spr_write_ibatu_h,
628 0x00000000);
629 spr_register(env, SPR_IBAT6L, "IBAT6L",
630 SPR_NOACCESS, SPR_NOACCESS,
631 &spr_read_ibat_h, &spr_write_ibatl_h,
632 0x00000000);
633 spr_register(env, SPR_IBAT7U, "IBAT7U",
634 SPR_NOACCESS, SPR_NOACCESS,
635 &spr_read_ibat_h, &spr_write_ibatu_h,
636 0x00000000);
637 spr_register(env, SPR_IBAT7L, "IBAT7L",
638 SPR_NOACCESS, SPR_NOACCESS,
639 &spr_read_ibat_h, &spr_write_ibatl_h,
640 0x00000000);
641 spr_register(env, SPR_DBAT4U, "DBAT4U",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_dbat_h, &spr_write_dbatu_h,
644 0x00000000);
645 spr_register(env, SPR_DBAT4L, "DBAT4L",
646 SPR_NOACCESS, SPR_NOACCESS,
647 &spr_read_dbat_h, &spr_write_dbatl_h,
648 0x00000000);
649 spr_register(env, SPR_DBAT5U, "DBAT5U",
650 SPR_NOACCESS, SPR_NOACCESS,
651 &spr_read_dbat_h, &spr_write_dbatu_h,
652 0x00000000);
653 spr_register(env, SPR_DBAT5L, "DBAT5L",
654 SPR_NOACCESS, SPR_NOACCESS,
655 &spr_read_dbat_h, &spr_write_dbatl_h,
656 0x00000000);
657 spr_register(env, SPR_DBAT6U, "DBAT6U",
658 SPR_NOACCESS, SPR_NOACCESS,
659 &spr_read_dbat_h, &spr_write_dbatu_h,
660 0x00000000);
661 spr_register(env, SPR_DBAT6L, "DBAT6L",
662 SPR_NOACCESS, SPR_NOACCESS,
663 &spr_read_dbat_h, &spr_write_dbatl_h,
664 0x00000000);
665 spr_register(env, SPR_DBAT7U, "DBAT7U",
666 SPR_NOACCESS, SPR_NOACCESS,
667 &spr_read_dbat_h, &spr_write_dbatu_h,
668 0x00000000);
669 spr_register(env, SPR_DBAT7L, "DBAT7L",
670 SPR_NOACCESS, SPR_NOACCESS,
671 &spr_read_dbat_h, &spr_write_dbatl_h,
672 0x00000000);
673 env->nb_BATs += 4;
674 #endif
675 }
676
677 /* Generic PowerPC time base */
678 static void gen_tbl (CPUPPCState *env)
679 {
680 spr_register(env, SPR_VTBL, "TBL",
681 &spr_read_tbl, SPR_NOACCESS,
682 &spr_read_tbl, SPR_NOACCESS,
683 0x00000000);
684 spr_register(env, SPR_TBL, "TBL",
685 SPR_NOACCESS, SPR_NOACCESS,
686 SPR_NOACCESS, &spr_write_tbl,
687 0x00000000);
688 spr_register(env, SPR_VTBU, "TBU",
689 &spr_read_tbu, SPR_NOACCESS,
690 &spr_read_tbu, SPR_NOACCESS,
691 0x00000000);
692 spr_register(env, SPR_TBU, "TBU",
693 SPR_NOACCESS, SPR_NOACCESS,
694 SPR_NOACCESS, &spr_write_tbu,
695 0x00000000);
696 }
697
698 /* Softare table search registers */
699 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
700 {
701 #if !defined(CONFIG_USER_ONLY)
702 env->nb_tlb = nb_tlbs;
703 env->nb_ways = nb_ways;
704 env->id_tlbs = 1;
705 spr_register(env, SPR_DMISS, "DMISS",
706 SPR_NOACCESS, SPR_NOACCESS,
707 &spr_read_generic, SPR_NOACCESS,
708 0x00000000);
709 spr_register(env, SPR_DCMP, "DCMP",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_generic, SPR_NOACCESS,
712 0x00000000);
713 spr_register(env, SPR_HASH1, "HASH1",
714 SPR_NOACCESS, SPR_NOACCESS,
715 &spr_read_generic, SPR_NOACCESS,
716 0x00000000);
717 spr_register(env, SPR_HASH2, "HASH2",
718 SPR_NOACCESS, SPR_NOACCESS,
719 &spr_read_generic, SPR_NOACCESS,
720 0x00000000);
721 spr_register(env, SPR_IMISS, "IMISS",
722 SPR_NOACCESS, SPR_NOACCESS,
723 &spr_read_generic, SPR_NOACCESS,
724 0x00000000);
725 spr_register(env, SPR_ICMP, "ICMP",
726 SPR_NOACCESS, SPR_NOACCESS,
727 &spr_read_generic, SPR_NOACCESS,
728 0x00000000);
729 spr_register(env, SPR_RPA, "RPA",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_generic, &spr_write_generic,
732 0x00000000);
733 #endif
734 }
735
736 /* SPR common to MPC755 and G2 */
737 static void gen_spr_G2_755 (CPUPPCState *env)
738 {
739 /* SGPRs */
740 spr_register(env, SPR_SPRG4, "SPRG4",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_generic, &spr_write_generic,
743 0x00000000);
744 spr_register(env, SPR_SPRG5, "SPRG5",
745 SPR_NOACCESS, SPR_NOACCESS,
746 &spr_read_generic, &spr_write_generic,
747 0x00000000);
748 spr_register(env, SPR_SPRG6, "SPRG6",
749 SPR_NOACCESS, SPR_NOACCESS,
750 &spr_read_generic, &spr_write_generic,
751 0x00000000);
752 spr_register(env, SPR_SPRG7, "SPRG7",
753 SPR_NOACCESS, SPR_NOACCESS,
754 &spr_read_generic, &spr_write_generic,
755 0x00000000);
756 /* External access control */
757 /* XXX : not implemented */
758 spr_register(env, SPR_EAR, "EAR",
759 SPR_NOACCESS, SPR_NOACCESS,
760 &spr_read_generic, &spr_write_generic,
761 0x00000000);
762 }
763
764 /* SPR common to all 7xx PowerPC implementations */
765 static void gen_spr_7xx (CPUPPCState *env)
766 {
767 /* Breakpoints */
768 /* XXX : not implemented */
769 spr_register(env, SPR_DABR, "DABR",
770 SPR_NOACCESS, SPR_NOACCESS,
771 &spr_read_generic, &spr_write_generic,
772 0x00000000);
773 /* XXX : not implemented */
774 spr_register(env, SPR_IABR, "IABR",
775 SPR_NOACCESS, SPR_NOACCESS,
776 &spr_read_generic, &spr_write_generic,
777 0x00000000);
778 /* Cache management */
779 /* XXX : not implemented */
780 spr_register(env, SPR_ICTC, "ICTC",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_generic, &spr_write_generic,
783 0x00000000);
784 /* XXX : not implemented */
785 spr_register(env, SPR_L2CR, "L2CR",
786 SPR_NOACCESS, SPR_NOACCESS,
787 &spr_read_generic, &spr_write_generic,
788 0x00000000);
789 /* Performance monitors */
790 /* XXX : not implemented */
791 spr_register(env, SPR_MMCR0, "MMCR0",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_generic, &spr_write_generic,
794 0x00000000);
795 /* XXX : not implemented */
796 spr_register(env, SPR_MMCR1, "MMCR1",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_generic, &spr_write_generic,
799 0x00000000);
800 /* XXX : not implemented */
801 spr_register(env, SPR_PMC1, "PMC1",
802 SPR_NOACCESS, SPR_NOACCESS,
803 &spr_read_generic, &spr_write_generic,
804 0x00000000);
805 /* XXX : not implemented */
806 spr_register(env, SPR_PMC2, "PMC2",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_generic, &spr_write_generic,
809 0x00000000);
810 /* XXX : not implemented */
811 spr_register(env, SPR_PMC3, "PMC3",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_generic, &spr_write_generic,
814 0x00000000);
815 /* XXX : not implemented */
816 spr_register(env, SPR_PMC4, "PMC4",
817 SPR_NOACCESS, SPR_NOACCESS,
818 &spr_read_generic, &spr_write_generic,
819 0x00000000);
820 /* XXX : not implemented */
821 spr_register(env, SPR_SIAR, "SIAR",
822 SPR_NOACCESS, SPR_NOACCESS,
823 &spr_read_generic, SPR_NOACCESS,
824 0x00000000);
825 /* XXX : not implemented */
826 spr_register(env, SPR_UMMCR0, "UMMCR0",
827 &spr_read_ureg, SPR_NOACCESS,
828 &spr_read_ureg, SPR_NOACCESS,
829 0x00000000);
830 /* XXX : not implemented */
831 spr_register(env, SPR_UMMCR1, "UMMCR1",
832 &spr_read_ureg, SPR_NOACCESS,
833 &spr_read_ureg, SPR_NOACCESS,
834 0x00000000);
835 /* XXX : not implemented */
836 spr_register(env, SPR_UPMC1, "UPMC1",
837 &spr_read_ureg, SPR_NOACCESS,
838 &spr_read_ureg, SPR_NOACCESS,
839 0x00000000);
840 /* XXX : not implemented */
841 spr_register(env, SPR_UPMC2, "UPMC2",
842 &spr_read_ureg, SPR_NOACCESS,
843 &spr_read_ureg, SPR_NOACCESS,
844 0x00000000);
845 /* XXX : not implemented */
846 spr_register(env, SPR_UPMC3, "UPMC3",
847 &spr_read_ureg, SPR_NOACCESS,
848 &spr_read_ureg, SPR_NOACCESS,
849 0x00000000);
850 /* XXX : not implemented */
851 spr_register(env, SPR_UPMC4, "UPMC4",
852 &spr_read_ureg, SPR_NOACCESS,
853 &spr_read_ureg, SPR_NOACCESS,
854 0x00000000);
855 /* XXX : not implemented */
856 spr_register(env, SPR_USIAR, "USIAR",
857 &spr_read_ureg, SPR_NOACCESS,
858 &spr_read_ureg, SPR_NOACCESS,
859 0x00000000);
860 /* External access control */
861 /* XXX : not implemented */
862 spr_register(env, SPR_EAR, "EAR",
863 SPR_NOACCESS, SPR_NOACCESS,
864 &spr_read_generic, &spr_write_generic,
865 0x00000000);
866 }
867
868 static void gen_spr_thrm (CPUPPCState *env)
869 {
870 /* Thermal management */
871 /* XXX : not implemented */
872 spr_register(env, SPR_THRM1, "THRM1",
873 SPR_NOACCESS, SPR_NOACCESS,
874 &spr_read_generic, &spr_write_generic,
875 0x00000000);
876 /* XXX : not implemented */
877 spr_register(env, SPR_THRM2, "THRM2",
878 SPR_NOACCESS, SPR_NOACCESS,
879 &spr_read_generic, &spr_write_generic,
880 0x00000000);
881 /* XXX : not implemented */
882 spr_register(env, SPR_THRM3, "THRM3",
883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_generic, &spr_write_generic,
885 0x00000000);
886 }
887
888 /* SPR specific to PowerPC 604 implementation */
889 static void gen_spr_604 (CPUPPCState *env)
890 {
891 /* Processor identification */
892 spr_register(env, SPR_PIR, "PIR",
893 SPR_NOACCESS, SPR_NOACCESS,
894 &spr_read_generic, &spr_write_pir,
895 0x00000000);
896 /* Breakpoints */
897 /* XXX : not implemented */
898 spr_register(env, SPR_IABR, "IABR",
899 SPR_NOACCESS, SPR_NOACCESS,
900 &spr_read_generic, &spr_write_generic,
901 0x00000000);
902 /* XXX : not implemented */
903 spr_register(env, SPR_DABR, "DABR",
904 SPR_NOACCESS, SPR_NOACCESS,
905 &spr_read_generic, &spr_write_generic,
906 0x00000000);
907 /* Performance counters */
908 /* XXX : not implemented */
909 spr_register(env, SPR_MMCR0, "MMCR0",
910 SPR_NOACCESS, SPR_NOACCESS,
911 &spr_read_generic, &spr_write_generic,
912 0x00000000);
913 /* XXX : not implemented */
914 spr_register(env, SPR_MMCR1, "MMCR1",
915 SPR_NOACCESS, SPR_NOACCESS,
916 &spr_read_generic, &spr_write_generic,
917 0x00000000);
918 /* XXX : not implemented */
919 spr_register(env, SPR_PMC1, "PMC1",
920 SPR_NOACCESS, SPR_NOACCESS,
921 &spr_read_generic, &spr_write_generic,
922 0x00000000);
923 /* XXX : not implemented */
924 spr_register(env, SPR_PMC2, "PMC2",
925 SPR_NOACCESS, SPR_NOACCESS,
926 &spr_read_generic, &spr_write_generic,
927 0x00000000);
928 /* XXX : not implemented */
929 spr_register(env, SPR_PMC3, "PMC3",
930 SPR_NOACCESS, SPR_NOACCESS,
931 &spr_read_generic, &spr_write_generic,
932 0x00000000);
933 /* XXX : not implemented */
934 spr_register(env, SPR_PMC4, "PMC4",
935 SPR_NOACCESS, SPR_NOACCESS,
936 &spr_read_generic, &spr_write_generic,
937 0x00000000);
938 /* XXX : not implemented */
939 spr_register(env, SPR_SIAR, "SIAR",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, SPR_NOACCESS,
942 0x00000000);
943 /* XXX : not implemented */
944 spr_register(env, SPR_SDA, "SDA",
945 SPR_NOACCESS, SPR_NOACCESS,
946 &spr_read_generic, SPR_NOACCESS,
947 0x00000000);
948 /* External access control */
949 /* XXX : not implemented */
950 spr_register(env, SPR_EAR, "EAR",
951 SPR_NOACCESS, SPR_NOACCESS,
952 &spr_read_generic, &spr_write_generic,
953 0x00000000);
954 }
955
956 /* SPR specific to PowerPC 603 implementation */
957 static void gen_spr_603 (CPUPPCState *env)
958 {
959 /* External access control */
960 /* XXX : not implemented */
961 spr_register(env, SPR_EAR, "EAR",
962 SPR_NOACCESS, SPR_NOACCESS,
963 &spr_read_generic, &spr_write_generic,
964 0x00000000);
965 }
966
967 /* SPR specific to PowerPC G2 implementation */
968 static void gen_spr_G2 (CPUPPCState *env)
969 {
970 /* Memory base address */
971 /* MBAR */
972 /* XXX : not implemented */
973 spr_register(env, SPR_MBAR, "MBAR",
974 SPR_NOACCESS, SPR_NOACCESS,
975 &spr_read_generic, &spr_write_generic,
976 0x00000000);
977 /* System version register */
978 /* SVR */
979 /* XXX : TODO: initialize it to an appropriate value */
980 spr_register(env, SPR_SVR, "SVR",
981 SPR_NOACCESS, SPR_NOACCESS,
982 &spr_read_generic, SPR_NOACCESS,
983 0x00000000);
984 /* Exception processing */
985 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
986 SPR_NOACCESS, SPR_NOACCESS,
987 &spr_read_generic, &spr_write_generic,
988 0x00000000);
989 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
990 SPR_NOACCESS, SPR_NOACCESS,
991 &spr_read_generic, &spr_write_generic,
992 0x00000000);
993 /* Breakpoints */
994 /* XXX : not implemented */
995 spr_register(env, SPR_DABR, "DABR",
996 SPR_NOACCESS, SPR_NOACCESS,
997 &spr_read_generic, &spr_write_generic,
998 0x00000000);
999 /* XXX : not implemented */
1000 spr_register(env, SPR_DABR2, "DABR2",
1001 SPR_NOACCESS, SPR_NOACCESS,
1002 &spr_read_generic, &spr_write_generic,
1003 0x00000000);
1004 /* XXX : not implemented */
1005 spr_register(env, SPR_IABR, "IABR",
1006 SPR_NOACCESS, SPR_NOACCESS,
1007 &spr_read_generic, &spr_write_generic,
1008 0x00000000);
1009 /* XXX : not implemented */
1010 spr_register(env, SPR_IABR2, "IABR2",
1011 SPR_NOACCESS, SPR_NOACCESS,
1012 &spr_read_generic, &spr_write_generic,
1013 0x00000000);
1014 /* XXX : not implemented */
1015 spr_register(env, SPR_IBCR, "IBCR",
1016 SPR_NOACCESS, SPR_NOACCESS,
1017 &spr_read_generic, &spr_write_generic,
1018 0x00000000);
1019 /* XXX : not implemented */
1020 spr_register(env, SPR_DBCR, "DBCR",
1021 SPR_NOACCESS, SPR_NOACCESS,
1022 &spr_read_generic, &spr_write_generic,
1023 0x00000000);
1024 }
1025
1026 /* SPR specific to PowerPC 602 implementation */
1027 static void gen_spr_602 (CPUPPCState *env)
1028 {
1029 /* ESA registers */
1030 /* XXX : not implemented */
1031 spr_register(env, SPR_SER, "SER",
1032 SPR_NOACCESS, SPR_NOACCESS,
1033 &spr_read_generic, &spr_write_generic,
1034 0x00000000);
1035 /* XXX : not implemented */
1036 spr_register(env, SPR_SEBR, "SEBR",
1037 SPR_NOACCESS, SPR_NOACCESS,
1038 &spr_read_generic, &spr_write_generic,
1039 0x00000000);
1040 /* XXX : not implemented */
1041 spr_register(env, SPR_ESASRR, "ESASRR",
1042 SPR_NOACCESS, SPR_NOACCESS,
1043 &spr_read_generic, &spr_write_generic,
1044 0x00000000);
1045 /* Floating point status */
1046 /* XXX : not implemented */
1047 spr_register(env, SPR_SP, "SP",
1048 SPR_NOACCESS, SPR_NOACCESS,
1049 &spr_read_generic, &spr_write_generic,
1050 0x00000000);
1051 /* XXX : not implemented */
1052 spr_register(env, SPR_LT, "LT",
1053 SPR_NOACCESS, SPR_NOACCESS,
1054 &spr_read_generic, &spr_write_generic,
1055 0x00000000);
1056 /* Watchdog timer */
1057 /* XXX : not implemented */
1058 spr_register(env, SPR_TCR, "TCR",
1059 SPR_NOACCESS, SPR_NOACCESS,
1060 &spr_read_generic, &spr_write_generic,
1061 0x00000000);
1062 /* Interrupt base */
1063 spr_register(env, SPR_IBR, "IBR",
1064 SPR_NOACCESS, SPR_NOACCESS,
1065 &spr_read_generic, &spr_write_generic,
1066 0x00000000);
1067 /* XXX : not implemented */
1068 spr_register(env, SPR_IABR, "IABR",
1069 SPR_NOACCESS, SPR_NOACCESS,
1070 &spr_read_generic, &spr_write_generic,
1071 0x00000000);
1072 }
1073
1074 /* SPR specific to PowerPC 601 implementation */
1075 static void gen_spr_601 (CPUPPCState *env)
1076 {
1077 /* Multiplication/division register */
1078 /* MQ */
1079 spr_register(env, SPR_MQ, "MQ",
1080 &spr_read_generic, &spr_write_generic,
1081 &spr_read_generic, &spr_write_generic,
1082 0x00000000);
1083 /* RTC registers */
1084 spr_register(env, SPR_601_RTCU, "RTCU",
1085 SPR_NOACCESS, SPR_NOACCESS,
1086 SPR_NOACCESS, &spr_write_601_rtcu,
1087 0x00000000);
1088 spr_register(env, SPR_601_VRTCU, "RTCU",
1089 &spr_read_601_rtcu, SPR_NOACCESS,
1090 &spr_read_601_rtcu, SPR_NOACCESS,
1091 0x00000000);
1092 spr_register(env, SPR_601_RTCL, "RTCL",
1093 SPR_NOACCESS, SPR_NOACCESS,
1094 SPR_NOACCESS, &spr_write_601_rtcl,
1095 0x00000000);
1096 spr_register(env, SPR_601_VRTCL, "RTCL",
1097 &spr_read_601_rtcl, SPR_NOACCESS,
1098 &spr_read_601_rtcl, SPR_NOACCESS,
1099 0x00000000);
1100 /* Timer */
1101 #if 0 /* ? */
1102 spr_register(env, SPR_601_UDECR, "UDECR",
1103 &spr_read_decr, SPR_NOACCESS,
1104 &spr_read_decr, SPR_NOACCESS,
1105 0x00000000);
1106 #endif
1107 /* External access control */
1108 /* XXX : not implemented */
1109 spr_register(env, SPR_EAR, "EAR",
1110 SPR_NOACCESS, SPR_NOACCESS,
1111 &spr_read_generic, &spr_write_generic,
1112 0x00000000);
1113 /* Memory management */
1114 #if !defined(CONFIG_USER_ONLY)
1115 spr_register(env, SPR_IBAT0U, "IBAT0U",
1116 SPR_NOACCESS, SPR_NOACCESS,
1117 &spr_read_601_ubat, &spr_write_601_ubatu,
1118 0x00000000);
1119 spr_register(env, SPR_IBAT0L, "IBAT0L",
1120 SPR_NOACCESS, SPR_NOACCESS,
1121 &spr_read_601_ubat, &spr_write_601_ubatl,
1122 0x00000000);
1123 spr_register(env, SPR_IBAT1U, "IBAT1U",
1124 SPR_NOACCESS, SPR_NOACCESS,
1125 &spr_read_601_ubat, &spr_write_601_ubatu,
1126 0x00000000);
1127 spr_register(env, SPR_IBAT1L, "IBAT1L",
1128 SPR_NOACCESS, SPR_NOACCESS,
1129 &spr_read_601_ubat, &spr_write_601_ubatl,
1130 0x00000000);
1131 spr_register(env, SPR_IBAT2U, "IBAT2U",
1132 SPR_NOACCESS, SPR_NOACCESS,
1133 &spr_read_601_ubat, &spr_write_601_ubatu,
1134 0x00000000);
1135 spr_register(env, SPR_IBAT2L, "IBAT2L",
1136 SPR_NOACCESS, SPR_NOACCESS,
1137 &spr_read_601_ubat, &spr_write_601_ubatl,
1138 0x00000000);
1139 spr_register(env, SPR_IBAT3U, "IBAT3U",
1140 SPR_NOACCESS, SPR_NOACCESS,
1141 &spr_read_601_ubat, &spr_write_601_ubatu,
1142 0x00000000);
1143 spr_register(env, SPR_IBAT3L, "IBAT3L",
1144 SPR_NOACCESS, SPR_NOACCESS,
1145 &spr_read_601_ubat, &spr_write_601_ubatl,
1146 0x00000000);
1147 env->nb_BATs = 4;
1148 #endif
1149 }
1150
1151 static void gen_spr_74xx (CPUPPCState *env)
1152 {
1153 /* Processor identification */
1154 spr_register(env, SPR_PIR, "PIR",
1155 SPR_NOACCESS, SPR_NOACCESS,
1156 &spr_read_generic, &spr_write_pir,
1157 0x00000000);
1158 /* XXX : not implemented */
1159 spr_register(env, SPR_MMCR2, "MMCR2",
1160 SPR_NOACCESS, SPR_NOACCESS,
1161 &spr_read_generic, &spr_write_generic,
1162 0x00000000);
1163 /* XXX : not implemented */
1164 spr_register(env, SPR_UMMCR2, "UMMCR2",
1165 &spr_read_ureg, SPR_NOACCESS,
1166 &spr_read_ureg, SPR_NOACCESS,
1167 0x00000000);
1168 /* XXX: not implemented */
1169 spr_register(env, SPR_BAMR, "BAMR",
1170 SPR_NOACCESS, SPR_NOACCESS,
1171 &spr_read_generic, &spr_write_generic,
1172 0x00000000);
1173 /* XXX : not implemented */
1174 spr_register(env, SPR_UBAMR, "UBAMR",
1175 &spr_read_ureg, SPR_NOACCESS,
1176 &spr_read_ureg, SPR_NOACCESS,
1177 0x00000000);
1178 /* XXX : not implemented */
1179 spr_register(env, SPR_MSSCR0, "MSSCR0",
1180 SPR_NOACCESS, SPR_NOACCESS,
1181 &spr_read_generic, &spr_write_generic,
1182 0x00000000);
1183 /* Hardware implementation registers */
1184 /* XXX : not implemented */
1185 spr_register(env, SPR_HID0, "HID0",
1186 SPR_NOACCESS, SPR_NOACCESS,
1187 &spr_read_generic, &spr_write_generic,
1188 0x00000000);
1189 /* XXX : not implemented */
1190 spr_register(env, SPR_HID1, "HID1",
1191 SPR_NOACCESS, SPR_NOACCESS,
1192 &spr_read_generic, &spr_write_generic,
1193 0x00000000);
1194 /* Altivec */
1195 spr_register(env, SPR_VRSAVE, "VRSAVE",
1196 &spr_read_generic, &spr_write_generic,
1197 &spr_read_generic, &spr_write_generic,
1198 0x00000000);
1199 }
1200
1201 static void gen_l3_ctrl (CPUPPCState *env)
1202 {
1203 /* L3CR */
1204 /* XXX : not implemented */
1205 spr_register(env, SPR_L3CR, "L3CR",
1206 SPR_NOACCESS, SPR_NOACCESS,
1207 &spr_read_generic, &spr_write_generic,
1208 0x00000000);
1209 /* L3ITCR0 */
1210 /* XXX : not implemented */
1211 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1212 SPR_NOACCESS, SPR_NOACCESS,
1213 &spr_read_generic, &spr_write_generic,
1214 0x00000000);
1215 /* L3ITCR1 */
1216 /* XXX : not implemented */
1217 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1218 SPR_NOACCESS, SPR_NOACCESS,
1219 &spr_read_generic, &spr_write_generic,
1220 0x00000000);
1221 /* L3ITCR2 */
1222 /* XXX : not implemented */
1223 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1224 SPR_NOACCESS, SPR_NOACCESS,
1225 &spr_read_generic, &spr_write_generic,
1226 0x00000000);
1227 /* L3ITCR3 */
1228 /* XXX : not implemented */
1229 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1230 SPR_NOACCESS, SPR_NOACCESS,
1231 &spr_read_generic, &spr_write_generic,
1232 0x00000000);
1233 /* L3OHCR */
1234 /* XXX : not implemented */
1235 spr_register(env, SPR_L3OHCR, "L3OHCR",
1236 SPR_NOACCESS, SPR_NOACCESS,
1237 &spr_read_generic, &spr_write_generic,
1238 0x00000000);
1239 /* L3PM */
1240 /* XXX : not implemented */
1241 spr_register(env, SPR_L3PM, "L3PM",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_generic, &spr_write_generic,
1244 0x00000000);
1245 }
1246
1247 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1248 {
1249 #if !defined(CONFIG_USER_ONLY)
1250 env->nb_tlb = nb_tlbs;
1251 env->nb_ways = nb_ways;
1252 env->id_tlbs = 1;
1253 /* XXX : not implemented */
1254 spr_register(env, SPR_PTEHI, "PTEHI",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_generic, &spr_write_generic,
1257 0x00000000);
1258 /* XXX : not implemented */
1259 spr_register(env, SPR_PTELO, "PTELO",
1260 SPR_NOACCESS, SPR_NOACCESS,
1261 &spr_read_generic, &spr_write_generic,
1262 0x00000000);
1263 /* XXX : not implemented */
1264 spr_register(env, SPR_TLBMISS, "TLBMISS",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_generic,
1267 0x00000000);
1268 #endif
1269 }
1270
1271 /* PowerPC BookE SPR */
1272 static void gen_spr_BookE (CPUPPCState *env)
1273 {
1274 /* Processor identification */
1275 spr_register(env, SPR_BOOKE_PIR, "PIR",
1276 SPR_NOACCESS, SPR_NOACCESS,
1277 &spr_read_generic, &spr_write_pir,
1278 0x00000000);
1279 /* Interrupt processing */
1280 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1281 SPR_NOACCESS, SPR_NOACCESS,
1282 &spr_read_generic, &spr_write_generic,
1283 0x00000000);
1284 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_generic, &spr_write_generic,
1287 0x00000000);
1288 #if 0
1289 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1290 SPR_NOACCESS, SPR_NOACCESS,
1291 &spr_read_generic, &spr_write_generic,
1292 0x00000000);
1293 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1294 SPR_NOACCESS, SPR_NOACCESS,
1295 &spr_read_generic, &spr_write_generic,
1296 0x00000000);
1297 #endif
1298 /* Debug */
1299 /* XXX : not implemented */
1300 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1301 SPR_NOACCESS, SPR_NOACCESS,
1302 &spr_read_generic, &spr_write_generic,
1303 0x00000000);
1304 /* XXX : not implemented */
1305 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, &spr_write_generic,
1308 0x00000000);
1309 /* XXX : not implemented */
1310 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1311 SPR_NOACCESS, SPR_NOACCESS,
1312 &spr_read_generic, &spr_write_generic,
1313 0x00000000);
1314 /* XXX : not implemented */
1315 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1316 SPR_NOACCESS, SPR_NOACCESS,
1317 &spr_read_generic, &spr_write_generic,
1318 0x00000000);
1319 /* XXX : not implemented */
1320 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1321 SPR_NOACCESS, SPR_NOACCESS,
1322 &spr_read_generic, &spr_write_generic,
1323 0x00000000);
1324 /* XXX : not implemented */
1325 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1326 SPR_NOACCESS, SPR_NOACCESS,
1327 &spr_read_generic, &spr_write_generic,
1328 0x00000000);
1329 /* XXX : not implemented */
1330 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1333 0x00000000);
1334 /* XXX : not implemented */
1335 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1336 SPR_NOACCESS, SPR_NOACCESS,
1337 &spr_read_generic, &spr_write_generic,
1338 0x00000000);
1339 /* XXX : not implemented */
1340 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1341 SPR_NOACCESS, SPR_NOACCESS,
1342 &spr_read_generic, &spr_write_generic,
1343 0x00000000);
1344 /* XXX : not implemented */
1345 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1346 SPR_NOACCESS, SPR_NOACCESS,
1347 &spr_read_generic, &spr_write_generic,
1348 0x00000000);
1349 /* XXX : not implemented */
1350 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_generic,
1353 0x00000000);
1354 /* XXX : not implemented */
1355 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1356 SPR_NOACCESS, SPR_NOACCESS,
1357 &spr_read_generic, &spr_write_clear,
1358 0x00000000);
1359 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1360 SPR_NOACCESS, SPR_NOACCESS,
1361 &spr_read_generic, &spr_write_generic,
1362 0x00000000);
1363 spr_register(env, SPR_BOOKE_ESR, "ESR",
1364 SPR_NOACCESS, SPR_NOACCESS,
1365 &spr_read_generic, &spr_write_generic,
1366 0x00000000);
1367 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1368 SPR_NOACCESS, SPR_NOACCESS,
1369 &spr_read_generic, &spr_write_excp_prefix,
1370 0x00000000);
1371 /* Exception vectors */
1372 spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1373 SPR_NOACCESS, SPR_NOACCESS,
1374 &spr_read_generic, &spr_write_excp_vector,
1375 0x00000000);
1376 spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1377 SPR_NOACCESS, SPR_NOACCESS,
1378 &spr_read_generic, &spr_write_excp_vector,
1379 0x00000000);
1380 spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1381 SPR_NOACCESS, SPR_NOACCESS,
1382 &spr_read_generic, &spr_write_excp_vector,
1383 0x00000000);
1384 spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1385 SPR_NOACCESS, SPR_NOACCESS,
1386 &spr_read_generic, &spr_write_excp_vector,
1387 0x00000000);
1388 spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1389 SPR_NOACCESS, SPR_NOACCESS,
1390 &spr_read_generic, &spr_write_excp_vector,
1391 0x00000000);
1392 spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1393 SPR_NOACCESS, SPR_NOACCESS,
1394 &spr_read_generic, &spr_write_excp_vector,
1395 0x00000000);
1396 spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1397 SPR_NOACCESS, SPR_NOACCESS,
1398 &spr_read_generic, &spr_write_excp_vector,
1399 0x00000000);
1400 spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1401 SPR_NOACCESS, SPR_NOACCESS,
1402 &spr_read_generic, &spr_write_excp_vector,
1403 0x00000000);
1404 spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1405 SPR_NOACCESS, SPR_NOACCESS,
1406 &spr_read_generic, &spr_write_excp_vector,
1407 0x00000000);
1408 spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1409 SPR_NOACCESS, SPR_NOACCESS,
1410 &spr_read_generic, &spr_write_excp_vector,
1411 0x00000000);
1412 spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1413 SPR_NOACCESS, SPR_NOACCESS,
1414 &spr_read_generic, &spr_write_excp_vector,
1415 0x00000000);
1416 spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1417 SPR_NOACCESS, SPR_NOACCESS,
1418 &spr_read_generic, &spr_write_excp_vector,
1419 0x00000000);
1420 spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1421 SPR_NOACCESS, SPR_NOACCESS,
1422 &spr_read_generic, &spr_write_excp_vector,
1423 0x00000000);
1424 spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1425 SPR_NOACCESS, SPR_NOACCESS,
1426 &spr_read_generic, &spr_write_excp_vector,
1427 0x00000000);
1428 spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1429 SPR_NOACCESS, SPR_NOACCESS,
1430 &spr_read_generic, &spr_write_excp_vector,
1431 0x00000000);
1432 spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1433 SPR_NOACCESS, SPR_NOACCESS,
1434 &spr_read_generic, &spr_write_excp_vector,
1435 0x00000000);
1436 #if 0
1437 spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1438 SPR_NOACCESS, SPR_NOACCESS,
1439 &spr_read_generic, &spr_write_excp_vector,
1440 0x00000000);
1441 spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1442 SPR_NOACCESS, SPR_NOACCESS,
1443 &spr_read_generic, &spr_write_excp_vector,
1444 0x00000000);
1445 spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1446 SPR_NOACCESS, SPR_NOACCESS,
1447 &spr_read_generic, &spr_write_excp_vector,
1448 0x00000000);
1449 spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1450 SPR_NOACCESS, SPR_NOACCESS,
1451 &spr_read_generic, &spr_write_excp_vector,
1452 0x00000000);
1453 spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1454 SPR_NOACCESS, SPR_NOACCESS,
1455 &spr_read_generic, &spr_write_excp_vector,
1456 0x00000000);
1457 spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1458 SPR_NOACCESS, SPR_NOACCESS,
1459 &spr_read_generic, &spr_write_excp_vector,
1460 0x00000000);
1461 #endif
1462 spr_register(env, SPR_BOOKE_PID, "PID",
1463 SPR_NOACCESS, SPR_NOACCESS,
1464 &spr_read_generic, &spr_write_generic,
1465 0x00000000);
1466 spr_register(env, SPR_BOOKE_TCR, "TCR",
1467 SPR_NOACCESS, SPR_NOACCESS,
1468 &spr_read_generic, &spr_write_booke_tcr,
1469 0x00000000);
1470 spr_register(env, SPR_BOOKE_TSR, "TSR",
1471 SPR_NOACCESS, SPR_NOACCESS,
1472 &spr_read_generic, &spr_write_booke_tsr,
1473 0x00000000);
1474 /* Timer */
1475 spr_register(env, SPR_DECR, "DECR",
1476 SPR_NOACCESS, SPR_NOACCESS,
1477 &spr_read_decr, &spr_write_decr,
1478 0x00000000);
1479 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1480 SPR_NOACCESS, SPR_NOACCESS,
1481 SPR_NOACCESS, &spr_write_generic,
1482 0x00000000);
1483 /* SPRGs */
1484 spr_register(env, SPR_USPRG0, "USPRG0",
1485 &spr_read_generic, &spr_write_generic,
1486 &spr_read_generic, &spr_write_generic,
1487 0x00000000);
1488 spr_register(env, SPR_SPRG4, "SPRG4",
1489 SPR_NOACCESS, SPR_NOACCESS,
1490 &spr_read_generic, &spr_write_generic,
1491 0x00000000);
1492 spr_register(env, SPR_USPRG4, "USPRG4",
1493 &spr_read_ureg, SPR_NOACCESS,
1494 &spr_read_ureg, SPR_NOACCESS,
1495 0x00000000);
1496 spr_register(env, SPR_SPRG5, "SPRG5",
1497 SPR_NOACCESS, SPR_NOACCESS,
1498 &spr_read_generic, &spr_write_generic,
1499 0x00000000);
1500 spr_register(env, SPR_USPRG5, "USPRG5",
1501 &spr_read_ureg, SPR_NOACCESS,
1502 &spr_read_ureg, SPR_NOACCESS,
1503 0x00000000);
1504 spr_register(env, SPR_SPRG6, "SPRG6",
1505 SPR_NOACCESS, SPR_NOACCESS,
1506 &spr_read_generic, &spr_write_generic,
1507 0x00000000);
1508 spr_register(env, SPR_USPRG6, "USPRG6",
1509 &spr_read_ureg, SPR_NOACCESS,
1510 &spr_read_ureg, SPR_NOACCESS,
1511 0x00000000);
1512 spr_register(env, SPR_SPRG7, "SPRG7",
1513 SPR_NOACCESS, SPR_NOACCESS,
1514 &spr_read_generic, &spr_write_generic,
1515 0x00000000);
1516 spr_register(env, SPR_USPRG7, "USPRG7",
1517 &spr_read_ureg, SPR_NOACCESS,
1518 &spr_read_ureg, SPR_NOACCESS,
1519 0x00000000);
1520 }
1521
1522 /* FSL storage control registers */
1523 static void gen_spr_BookE_FSL (CPUPPCState *env)
1524 {
1525 #if !defined(CONFIG_USER_ONLY)
1526 /* TLB assist registers */
1527 /* XXX : not implemented */
1528 spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1529 SPR_NOACCESS, SPR_NOACCESS,
1530 &spr_read_generic, &spr_write_generic,
1531 0x00000000);
1532 /* XXX : not implemented */
1533 spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1534 SPR_NOACCESS, SPR_NOACCESS,
1535 &spr_read_generic, &spr_write_generic,
1536 0x00000000);
1537 /* XXX : not implemented */
1538 spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1539 SPR_NOACCESS, SPR_NOACCESS,
1540 &spr_read_generic, &spr_write_generic,
1541 0x00000000);
1542 /* XXX : not implemented */
1543 spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1544 SPR_NOACCESS, SPR_NOACCESS,
1545 &spr_read_generic, &spr_write_generic,
1546 0x00000000);
1547 /* XXX : not implemented */
1548 spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_generic,
1551 0x00000000);
1552 /* XXX : not implemented */
1553 spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
1557 /* XXX : not implemented */
1558 spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_generic, &spr_write_generic,
1561 0x00000000);
1562 if (env->nb_pids > 1) {
1563 /* XXX : not implemented */
1564 spr_register(env, SPR_BOOKE_PID1, "PID1",
1565 SPR_NOACCESS, SPR_NOACCESS,
1566 &spr_read_generic, &spr_write_generic,
1567 0x00000000);
1568 }
1569 if (env->nb_pids > 2) {
1570 /* XXX : not implemented */
1571 spr_register(env, SPR_BOOKE_PID2, "PID2",
1572 SPR_NOACCESS, SPR_NOACCESS,
1573 &spr_read_generic, &spr_write_generic,
1574 0x00000000);
1575 }
1576 /* XXX : not implemented */
1577 spr_register(env, SPR_MMUCFG, "MMUCFG",
1578 SPR_NOACCESS, SPR_NOACCESS,
1579 &spr_read_generic, SPR_NOACCESS,
1580 0x00000000); /* TOFIX */
1581 /* XXX : not implemented */
1582 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
1583 SPR_NOACCESS, SPR_NOACCESS,
1584 &spr_read_generic, &spr_write_generic,
1585 0x00000000); /* TOFIX */
1586 switch (env->nb_ways) {
1587 case 4:
1588 /* XXX : not implemented */
1589 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1590 SPR_NOACCESS, SPR_NOACCESS,
1591 &spr_read_generic, SPR_NOACCESS,
1592 0x00000000); /* TOFIX */
1593 /* Fallthru */
1594 case 3:
1595 /* XXX : not implemented */
1596 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1597 SPR_NOACCESS, SPR_NOACCESS,
1598 &spr_read_generic, SPR_NOACCESS,
1599 0x00000000); /* TOFIX */
1600 /* Fallthru */
1601 case 2:
1602 /* XXX : not implemented */
1603 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1604 SPR_NOACCESS, SPR_NOACCESS,
1605 &spr_read_generic, SPR_NOACCESS,
1606 0x00000000); /* TOFIX */
1607 /* Fallthru */
1608 case 1:
1609 /* XXX : not implemented */
1610 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1611 SPR_NOACCESS, SPR_NOACCESS,
1612 &spr_read_generic, SPR_NOACCESS,
1613 0x00000000); /* TOFIX */
1614 /* Fallthru */
1615 case 0:
1616 default:
1617 break;
1618 }
1619 #endif
1620 }
1621
1622 /* SPR specific to PowerPC 440 implementation */
1623 static void gen_spr_440 (CPUPPCState *env)
1624 {
1625 /* Cache control */
1626 /* XXX : not implemented */
1627 spr_register(env, SPR_440_DNV0, "DNV0",
1628 SPR_NOACCESS, SPR_NOACCESS,
1629 &spr_read_generic, &spr_write_generic,
1630 0x00000000);
1631 /* XXX : not implemented */
1632 spr_register(env, SPR_440_DNV1, "DNV1",
1633 SPR_NOACCESS, SPR_NOACCESS,
1634 &spr_read_generic, &spr_write_generic,
1635 0x00000000);
1636 /* XXX : not implemented */
1637 spr_register(env, SPR_440_DNV2, "DNV2",
1638 SPR_NOACCESS, SPR_NOACCESS,
1639 &spr_read_generic, &spr_write_generic,
1640 0x00000000);
1641 /* XXX : not implemented */
1642 spr_register(env, SPR_440_DNV3, "DNV3",
1643 SPR_NOACCESS, SPR_NOACCESS,
1644 &spr_read_generic, &spr_write_generic,
1645 0x00000000);
1646 /* XXX : not implemented */
1647 spr_register(env, SPR_440_DTV0, "DTV0",
1648 SPR_NOACCESS, SPR_NOACCESS,
1649 &spr_read_generic, &spr_write_generic,
1650 0x00000000);
1651 /* XXX : not implemented */
1652 spr_register(env, SPR_440_DTV1, "DTV1",
1653 SPR_NOACCESS, SPR_NOACCESS,
1654 &spr_read_generic, &spr_write_generic,
1655 0x00000000);
1656 /* XXX : not implemented */
1657 spr_register(env, SPR_440_DTV2, "DTV2",
1658 SPR_NOACCESS, SPR_NOACCESS,
1659 &spr_read_generic, &spr_write_generic,
1660 0x00000000);
1661 /* XXX : not implemented */
1662 spr_register(env, SPR_440_DTV3, "DTV3",
1663 SPR_NOACCESS, SPR_NOACCESS,
1664 &spr_read_generic, &spr_write_generic,
1665 0x00000000);
1666 /* XXX : not implemented */
1667 spr_register(env, SPR_440_DVLIM, "DVLIM",
1668 SPR_NOACCESS, SPR_NOACCESS,
1669 &spr_read_generic, &spr_write_generic,
1670 0x00000000);
1671 /* XXX : not implemented */
1672 spr_register(env, SPR_440_INV0, "INV0",
1673 SPR_NOACCESS, SPR_NOACCESS,
1674 &spr_read_generic, &spr_write_generic,
1675 0x00000000);
1676 /* XXX : not implemented */
1677 spr_register(env, SPR_440_INV1, "INV1",
1678 SPR_NOACCESS, SPR_NOACCESS,
1679 &spr_read_generic, &spr_write_generic,
1680 0x00000000);
1681 /* XXX : not implemented */
1682 spr_register(env, SPR_440_INV2, "INV2",
1683 SPR_NOACCESS, SPR_NOACCESS,
1684 &spr_read_generic, &spr_write_generic,
1685 0x00000000);
1686 /* XXX : not implemented */
1687 spr_register(env, SPR_440_INV3, "INV3",
1688 SPR_NOACCESS, SPR_NOACCESS,
1689 &spr_read_generic, &spr_write_generic,
1690 0x00000000);
1691 /* XXX : not implemented */
1692 spr_register(env, SPR_440_ITV0, "ITV0",
1693 SPR_NOACCESS, SPR_NOACCESS,
1694 &spr_read_generic, &spr_write_generic,
1695 0x00000000);
1696 /* XXX : not implemented */
1697 spr_register(env, SPR_440_ITV1, "ITV1",
1698 SPR_NOACCESS, SPR_NOACCESS,
1699 &spr_read_generic, &spr_write_generic,
1700 0x00000000);
1701 /* XXX : not implemented */
1702 spr_register(env, SPR_440_ITV2, "ITV2",
1703 SPR_NOACCESS, SPR_NOACCESS,
1704 &spr_read_generic, &spr_write_generic,
1705 0x00000000);
1706 /* XXX : not implemented */
1707 spr_register(env, SPR_440_ITV3, "ITV3",
1708 SPR_NOACCESS, SPR_NOACCESS,
1709 &spr_read_generic, &spr_write_generic,
1710 0x00000000);
1711 /* XXX : not implemented */
1712 spr_register(env, SPR_440_IVLIM, "IVLIM",
1713 SPR_NOACCESS, SPR_NOACCESS,
1714 &spr_read_generic, &spr_write_generic,
1715 0x00000000);
1716 /* Cache debug */
1717 /* XXX : not implemented */
1718 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, SPR_NOACCESS,
1721 0x00000000);
1722 /* XXX : not implemented */
1723 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_generic, SPR_NOACCESS,
1726 0x00000000);
1727 /* XXX : not implemented */
1728 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, SPR_NOACCESS,
1731 0x00000000);
1732 /* XXX : not implemented */
1733 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1734 SPR_NOACCESS, SPR_NOACCESS,
1735 &spr_read_generic, SPR_NOACCESS,
1736 0x00000000);
1737 /* XXX : not implemented */
1738 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, SPR_NOACCESS,
1741 0x00000000);
1742 /* XXX : not implemented */
1743 spr_register(env, SPR_440_DBDR, "DBDR",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, &spr_write_generic,
1746 0x00000000);
1747 /* Processor control */
1748 spr_register(env, SPR_4xx_CCR0, "CCR0",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1753 SPR_NOACCESS, SPR_NOACCESS,
1754 &spr_read_generic, SPR_NOACCESS,
1755 0x00000000);
1756 /* Storage control */
1757 spr_register(env, SPR_440_MMUCR, "MMUCR",
1758 SPR_NOACCESS, SPR_NOACCESS,
1759 &spr_read_generic, &spr_write_generic,
1760 0x00000000);
1761 }
1762
1763 /* SPR shared between PowerPC 40x implementations */
1764 static void gen_spr_40x (CPUPPCState *env)
1765 {
1766 /* Cache */
1767 /* not emulated, as Qemu do not emulate caches */
1768 spr_register(env, SPR_40x_DCCR, "DCCR",
1769 SPR_NOACCESS, SPR_NOACCESS,
1770 &spr_read_generic, &spr_write_generic,
1771 0x00000000);
1772 /* not emulated, as Qemu do not emulate caches */
1773 spr_register(env, SPR_40x_ICCR, "ICCR",
1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, &spr_write_generic,
1776 0x00000000);
1777 /* not emulated, as Qemu do not emulate caches */
1778 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1779 SPR_NOACCESS, SPR_NOACCESS,
1780 &spr_read_generic, SPR_NOACCESS,
1781 0x00000000);
1782 /* Exception */
1783 spr_register(env, SPR_40x_DEAR, "DEAR",
1784 SPR_NOACCESS, SPR_NOACCESS,
1785 &spr_read_generic, &spr_write_generic,
1786 0x00000000);
1787 spr_register(env, SPR_40x_ESR, "ESR",
1788 SPR_NOACCESS, SPR_NOACCESS,
1789 &spr_read_generic, &spr_write_generic,
1790 0x00000000);
1791 spr_register(env, SPR_40x_EVPR, "EVPR",
1792 SPR_NOACCESS, SPR_NOACCESS,
1793 &spr_read_generic, &spr_write_excp_prefix,
1794 0x00000000);
1795 spr_register(env, SPR_40x_SRR2, "SRR2",
1796 &spr_read_generic, &spr_write_generic,
1797 &spr_read_generic, &spr_write_generic,
1798 0x00000000);
1799 spr_register(env, SPR_40x_SRR3, "SRR3",
1800 &spr_read_generic, &spr_write_generic,
1801 &spr_read_generic, &spr_write_generic,
1802 0x00000000);
1803 /* Timers */
1804 spr_register(env, SPR_40x_PIT, "PIT",
1805 SPR_NOACCESS, SPR_NOACCESS,
1806 &spr_read_40x_pit, &spr_write_40x_pit,
1807 0x00000000);
1808 spr_register(env, SPR_40x_TCR, "TCR",
1809 SPR_NOACCESS, SPR_NOACCESS,
1810 &spr_read_generic, &spr_write_booke_tcr,
1811 0x00000000);
1812 spr_register(env, SPR_40x_TSR, "TSR",
1813 SPR_NOACCESS, SPR_NOACCESS,
1814 &spr_read_generic, &spr_write_booke_tsr,
1815 0x00000000);
1816 }
1817
1818 /* SPR specific to PowerPC 405 implementation */
1819 static void gen_spr_405 (CPUPPCState *env)
1820 {
1821 /* MMU */
1822 spr_register(env, SPR_40x_PID, "PID",
1823 SPR_NOACCESS, SPR_NOACCESS,
1824 &spr_read_generic, &spr_write_generic,
1825 0x00000000);
1826 spr_register(env, SPR_4xx_CCR0, "CCR0",
1827 SPR_NOACCESS, SPR_NOACCESS,
1828 &spr_read_generic, &spr_write_generic,
1829 0x00700000);
1830 /* Debug interface */
1831 /* XXX : not implemented */
1832 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1833 SPR_NOACCESS, SPR_NOACCESS,
1834 &spr_read_generic, &spr_write_40x_dbcr0,
1835 0x00000000);
1836 /* XXX : not implemented */
1837 spr_register(env, SPR_405_DBCR1, "DBCR1",
1838 SPR_NOACCESS, SPR_NOACCESS,
1839 &spr_read_generic, &spr_write_generic,
1840 0x00000000);
1841 /* XXX : not implemented */
1842 spr_register(env, SPR_40x_DBSR, "DBSR",
1843 SPR_NOACCESS, SPR_NOACCESS,
1844 &spr_read_generic, &spr_write_clear,
1845 /* Last reset was system reset */
1846 0x00000300);
1847 /* XXX : not implemented */
1848 spr_register(env, SPR_40x_DAC1, "DAC1",
1849 SPR_NOACCESS, SPR_NOACCESS,
1850 &spr_read_generic, &spr_write_generic,
1851 0x00000000);
1852 spr_register(env, SPR_40x_DAC2, "DAC2",
1853 SPR_NOACCESS, SPR_NOACCESS,
1854 &spr_read_generic, &spr_write_generic,
1855 0x00000000);
1856 /* XXX : not implemented */
1857 spr_register(env, SPR_405_DVC1, "DVC1",
1858 SPR_NOACCESS, SPR_NOACCESS,
1859 &spr_read_generic, &spr_write_generic,
1860 0x00000000);
1861 /* XXX : not implemented */
1862 spr_register(env, SPR_405_DVC2, "DVC2",
1863 SPR_NOACCESS, SPR_NOACCESS,
1864 &spr_read_generic, &spr_write_generic,
1865 0x00000000);
1866 /* XXX : not implemented */
1867 spr_register(env, SPR_40x_IAC1, "IAC1",
1868 SPR_NOACCESS, SPR_NOACCESS,
1869 &spr_read_generic, &spr_write_generic,
1870 0x00000000);
1871 spr_register(env, SPR_40x_IAC2, "IAC2",
1872 SPR_NOACCESS, SPR_NOACCESS,
1873 &spr_read_generic, &spr_write_generic,
1874 0x00000000);
1875 /* XXX : not implemented */
1876 spr_register(env, SPR_405_IAC3, "IAC3",
1877 SPR_NOACCESS, SPR_NOACCESS,
1878 &spr_read_generic, &spr_write_generic,
1879 0x00000000);
1880 /* XXX : not implemented */
1881 spr_register(env, SPR_405_IAC4, "IAC4",
1882 SPR_NOACCESS, SPR_NOACCESS,
1883 &spr_read_generic, &spr_write_generic,
1884 0x00000000);
1885 /* Storage control */
1886 /* XXX: TODO: not implemented */
1887 spr_register(env, SPR_405_SLER, "SLER",
1888 SPR_NOACCESS, SPR_NOACCESS,
1889 &spr_read_generic, &spr_write_40x_sler,
1890 0x00000000);
1891 spr_register(env, SPR_40x_ZPR, "ZPR",
1892 SPR_NOACCESS, SPR_NOACCESS,
1893 &spr_read_generic, &spr_write_generic,
1894 0x00000000);
1895 /* XXX : not implemented */
1896 spr_register(env, SPR_405_SU0R, "SU0R",
1897 SPR_NOACCESS, SPR_NOACCESS,
1898 &spr_read_generic, &spr_write_generic,
1899 0x00000000);
1900 /* SPRG */
1901 spr_register(env, SPR_USPRG0, "USPRG0",
1902 &spr_read_ureg, SPR_NOACCESS,
1903 &spr_read_ureg, SPR_NOACCESS,
1904 0x00000000);
1905 spr_register(env, SPR_SPRG4, "SPRG4",
1906 SPR_NOACCESS, SPR_NOACCESS,
1907 &spr_read_generic, &spr_write_generic,
1908 0x00000000);
1909 spr_register(env, SPR_USPRG4, "USPRG4",
1910 &spr_read_ureg, SPR_NOACCESS,
1911 &spr_read_ureg, SPR_NOACCESS,
1912 0x00000000);
1913 spr_register(env, SPR_SPRG5, "SPRG5",
1914 SPR_NOACCESS, SPR_NOACCESS,
1915 spr_read_generic, &spr_write_generic,
1916 0x00000000);
1917 spr_register(env, SPR_USPRG5, "USPRG5",
1918 &spr_read_ureg, SPR_NOACCESS,
1919 &spr_read_ureg, SPR_NOACCESS,
1920 0x00000000);
1921 spr_register(env, SPR_SPRG6, "SPRG6",
1922 SPR_NOACCESS, SPR_NOACCESS,
1923 spr_read_generic, &spr_write_generic,
1924 0x00000000);
1925 spr_register(env, SPR_USPRG6, "USPRG6",
1926 &spr_read_ureg, SPR_NOACCESS,
1927 &spr_read_ureg, SPR_NOACCESS,
1928 0x00000000);
1929 spr_register(env, SPR_SPRG7, "SPRG7",
1930 SPR_NOACCESS, SPR_NOACCESS,
1931 spr_read_generic, &spr_write_generic,
1932 0x00000000);
1933 spr_register(env, SPR_USPRG7, "USPRG7",
1934 &spr_read_ureg, SPR_NOACCESS,
1935 &spr_read_ureg, SPR_NOACCESS,
1936 0x00000000);
1937 }
1938
1939 /* SPR shared between PowerPC 401 & 403 implementations */
1940 static void gen_spr_401_403 (CPUPPCState *env)
1941 {
1942 /* Time base */
1943 spr_register(env, SPR_403_VTBL, "TBL",
1944 &spr_read_tbl, SPR_NOACCESS,
1945 &spr_read_tbl, SPR_NOACCESS,
1946 0x00000000);
1947 spr_register(env, SPR_403_TBL, "TBL",
1948 SPR_NOACCESS, SPR_NOACCESS,
1949 SPR_NOACCESS, &spr_write_tbl,
1950 0x00000000);
1951 spr_register(env, SPR_403_VTBU, "TBU",
1952 &spr_read_tbu, SPR_NOACCESS,
1953 &spr_read_tbu, SPR_NOACCESS,
1954 0x00000000);
1955 spr_register(env, SPR_403_TBU, "TBU",
1956 SPR_NOACCESS, SPR_NOACCESS,
1957 SPR_NOACCESS, &spr_write_tbu,
1958 0x00000000);
1959 /* Debug */
1960 /* not emulated, as Qemu do not emulate caches */
1961 spr_register(env, SPR_403_CDBCR, "CDBCR",
1962 SPR_NOACCESS, SPR_NOACCESS,
1963 &spr_read_generic, &spr_write_generic,
1964 0x00000000);
1965 }
1966
1967 /* SPR specific to PowerPC 401 implementation */
1968 static void gen_spr_401 (CPUPPCState *env)
1969 {
1970 /* Debug interface */
1971 /* XXX : not implemented */
1972 spr_register(env, SPR_40x_DBCR0, "DBCR",
1973 SPR_NOACCESS, SPR_NOACCESS,
1974 &spr_read_generic, &spr_write_40x_dbcr0,
1975 0x00000000);
1976 /* XXX : not implemented */
1977 spr_register(env, SPR_40x_DBSR, "DBSR",
1978 SPR_NOACCESS, SPR_NOACCESS,
1979 &spr_read_generic, &spr_write_clear,
1980 /* Last reset was system reset */
1981 0x00000300);
1982 /* XXX : not implemented */
1983 spr_register(env, SPR_40x_DAC1, "DAC",
1984 SPR_NOACCESS, SPR_NOACCESS,
1985 &spr_read_generic, &spr_write_generic,
1986 0x00000000);
1987 /* XXX : not implemented */
1988 spr_register(env, SPR_40x_IAC1, "IAC",
1989 SPR_NOACCESS, SPR_NOACCESS,
1990 &spr_read_generic, &spr_write_generic,
1991 0x00000000);
1992 /* Storage control */
1993 /* XXX: TODO: not implemented */
1994 spr_register(env, SPR_405_SLER, "SLER",
1995 SPR_NOACCESS, SPR_NOACCESS,
1996 &spr_read_generic, &spr_write_40x_sler,
1997 0x00000000);
1998 /* not emulated, as Qemu never does speculative access */
1999 spr_register(env, SPR_40x_SGR, "SGR",
2000 SPR_NOACCESS, SPR_NOACCESS,
2001 &spr_read_generic, &spr_write_generic,
2002 0xFFFFFFFF);
2003 /* not emulated, as Qemu do not emulate caches */
2004 spr_register(env, SPR_40x_DCWR, "DCWR",
2005 SPR_NOACCESS, SPR_NOACCESS,
2006 &spr_read_generic, &spr_write_generic,
2007 0x00000000);
2008 }
2009
2010 static void gen_spr_401x2 (CPUPPCState *env)
2011 {
2012 gen_spr_401(env);
2013 spr_register(env, SPR_40x_PID, "PID",
2014 SPR_NOACCESS, SPR_NOACCESS,
2015 &spr_read_generic, &spr_write_generic,
2016 0x00000000);
2017 spr_register(env, SPR_40x_ZPR, "ZPR",
2018 SPR_NOACCESS, SPR_NOACCESS,
2019 &spr_read_generic, &spr_write_generic,
2020 0x00000000);
2021 }
2022
2023 /* SPR specific to PowerPC 403 implementation */
2024 static void gen_spr_403 (CPUPPCState *env)
2025 {
2026 /* Debug interface */
2027 /* XXX : not implemented */
2028 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2029 SPR_NOACCESS, SPR_NOACCESS,
2030 &spr_read_generic, &spr_write_40x_dbcr0,
2031 0x00000000);
2032 /* XXX : not implemented */
2033 spr_register(env, SPR_40x_DBSR, "DBSR",
2034 SPR_NOACCESS, SPR_NOACCESS,
2035 &spr_read_generic, &spr_write_clear,
2036 /* Last reset was system reset */
2037 0x00000300);
2038 /* XXX : not implemented */
2039 spr_register(env, SPR_40x_DAC1, "DAC1",
2040 SPR_NOACCESS, SPR_NOACCESS,
2041 &spr_read_generic, &spr_write_generic,
2042 0x00000000);
2043 /* XXX : not implemented */
2044 spr_register(env, SPR_40x_DAC2, "DAC2",
2045 SPR_NOACCESS, SPR_NOACCESS,
2046 &spr_read_generic, &spr_write_generic,
2047 0x00000000);
2048 /* XXX : not implemented */
2049 spr_register(env, SPR_40x_IAC1, "IAC1",
2050 SPR_NOACCESS, SPR_NOACCESS,
2051 &spr_read_generic, &spr_write_generic,
2052 0x00000000);
2053 /* XXX : not implemented */
2054 spr_register(env, SPR_40x_IAC2, "IAC2",
2055 SPR_NOACCESS, SPR_NOACCESS,
2056 &spr_read_generic, &spr_write_generic,
2057 0x00000000);
2058 }
2059
2060 static void gen_spr_403_real (CPUPPCState *env)
2061 {
2062 spr_register(env, SPR_403_PBL1, "PBL1",
2063 SPR_NOACCESS, SPR_NOACCESS,
2064 &spr_read_403_pbr, &spr_write_403_pbr,
2065 0x00000000);
2066 spr_register(env, SPR_403_PBU1, "PBU1",
2067 SPR_NOACCESS, SPR_NOACCESS,
2068 &spr_read_403_pbr, &spr_write_403_pbr,
2069 0x00000000);
2070 spr_register(env, SPR_403_PBL2, "PBL2",
2071 SPR_NOACCESS, SPR_NOACCESS,
2072 &spr_read_403_pbr, &spr_write_403_pbr,
2073 0x00000000);
2074 spr_register(env, SPR_403_PBU2, "PBU2",
2075 SPR_NOACCESS, SPR_NOACCESS,
2076 &spr_read_403_pbr, &spr_write_403_pbr,
2077 0x00000000);
2078 }
2079
2080 static void gen_spr_403_mmu (CPUPPCState *env)
2081 {
2082 /* MMU */
2083 spr_register(env, SPR_40x_PID, "PID",
2084 SPR_NOACCESS, SPR_NOACCESS,
2085 &spr_read_generic, &spr_write_generic,
2086 0x00000000);
2087 spr_register(env, SPR_40x_ZPR, "ZPR",
2088 SPR_NOACCESS, SPR_NOACCESS,
2089 &spr_read_generic, &spr_write_generic,
2090 0x00000000);
2091 }
2092
2093 /* SPR specific to PowerPC compression coprocessor extension */
2094 static void gen_spr_compress (CPUPPCState *env)
2095 {
2096 /* XXX : not implemented */
2097 spr_register(env, SPR_401_SKR, "SKR",
2098 SPR_NOACCESS, SPR_NOACCESS,
2099 &spr_read_generic, &spr_write_generic,
2100 0x00000000);
2101 }
2102
2103 #if defined (TARGET_PPC64)
2104 /* SPR specific to PowerPC 620 */
2105 static void gen_spr_620 (CPUPPCState *env)
2106 {
2107 /* XXX : not implemented */
2108 spr_register(env, SPR_620_PMR0, "PMR0",
2109 SPR_NOACCESS, SPR_NOACCESS,
2110 &spr_read_generic, &spr_write_generic,
2111 0x00000000);
2112 /* XXX : not implemented */
2113 spr_register(env, SPR_620_PMR1, "PMR1",
2114 SPR_NOACCESS, SPR_NOACCESS,
2115 &spr_read_generic, &spr_write_generic,
2116 0x00000000);
2117 /* XXX : not implemented */
2118 spr_register(env, SPR_620_PMR2, "PMR2",
2119 SPR_NOACCESS, SPR_NOACCESS,
2120 &spr_read_generic, &spr_write_generic,
2121 0x00000000);
2122 /* XXX : not implemented */
2123 spr_register(env, SPR_620_PMR3, "PMR3",
2124 SPR_NOACCESS, SPR_NOACCESS,
2125 &spr_read_generic, &spr_write_generic,
2126 0x00000000);
2127 /* XXX : not implemented */
2128 spr_register(env, SPR_620_PMR4, "PMR4",
2129 SPR_NOACCESS, SPR_NOACCESS,
2130 &spr_read_generic, &spr_write_generic,
2131 0x00000000);
2132 /* XXX : not implemented */
2133 spr_register(env, SPR_620_PMR5, "PMR5",
2134 SPR_NOACCESS, SPR_NOACCESS,
2135 &spr_read_generic, &spr_write_generic,
2136 0x00000000);
2137 /* XXX : not implemented */
2138 spr_register(env, SPR_620_PMR6, "PMR6",
2139 SPR_NOACCESS, SPR_NOACCESS,
2140 &spr_read_generic, &spr_write_generic,
2141 0x00000000);
2142 /* XXX : not implemented */
2143 spr_register(env, SPR_620_PMR7, "PMR7",
2144 SPR_NOACCESS, SPR_NOACCESS,
2145 &spr_read_generic, &spr_write_generic,
2146 0x00000000);
2147 /* XXX : not implemented */
2148 spr_register(env, SPR_620_PMR8, "PMR8",
2149 SPR_NOACCESS, SPR_NOACCESS,
2150 &spr_read_generic, &spr_write_generic,
2151 0x00000000);
2152 /* XXX : not implemented */
2153 spr_register(env, SPR_620_PMR9, "PMR9",
2154 SPR_NOACCESS, SPR_NOACCESS,
2155 &spr_read_generic, &spr_write_generic,
2156 0x00000000);
2157 /* XXX : not implemented */
2158 spr_register(env, SPR_620_PMRA, "PMR10",
2159 SPR_NOACCESS, SPR_NOACCESS,
2160 &spr_read_generic, &spr_write_generic,
2161 0x00000000);
2162 /* XXX : not implemented */
2163 spr_register(env, SPR_620_PMRB, "PMR11",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 &spr_read_generic, &spr_write_generic,
2166 0x00000000);
2167 /* XXX : not implemented */
2168 spr_register(env, SPR_620_PMRC, "PMR12",
2169 SPR_NOACCESS, SPR_NOACCESS,
2170 &spr_read_generic, &spr_write_generic,
2171 0x00000000);
2172 /* XXX : not implemented */
2173 spr_register(env, SPR_620_PMRD, "PMR13",
2174 SPR_NOACCESS, SPR_NOACCESS,
2175 &spr_read_generic, &spr_write_generic,
2176 0x00000000);
2177 /* XXX : not implemented */
2178 spr_register(env, SPR_620_PMRE, "PMR14",
2179 SPR_NOACCESS, SPR_NOACCESS,
2180 &spr_read_generic, &spr_write_generic,
2181 0x00000000);
2182 /* XXX : not implemented */
2183 spr_register(env, SPR_620_PMRF, "PMR15",
2184 SPR_NOACCESS, SPR_NOACCESS,
2185 &spr_read_generic, &spr_write_generic,
2186 0x00000000);
2187 /* XXX : not implemented */
2188 spr_register(env, SPR_620_HID8, "HID8",
2189 SPR_NOACCESS, SPR_NOACCESS,
2190 &spr_read_generic, &spr_write_generic,
2191 0x00000000);
2192 /* XXX : not implemented */
2193 spr_register(env, SPR_620_HID9, "HID9",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 &spr_read_generic, &spr_write_generic,
2196 0x00000000);
2197 }
2198 #endif /* defined (TARGET_PPC64) */
2199
2200 // XXX: TODO
2201 /*
2202 * AMR => SPR 29 (Power 2.04)
2203 * CTRL => SPR 136 (Power 2.04)
2204 * CTRL => SPR 152 (Power 2.04)
2205 * SCOMC => SPR 276 (64 bits ?)
2206 * SCOMD => SPR 277 (64 bits ?)
2207 * TBU40 => SPR 286 (Power 2.04 hypv)
2208 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2209 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2210 * HDSISR => SPR 306 (Power 2.04 hypv)
2211 * HDAR => SPR 307 (Power 2.04 hypv)
2212 * PURR => SPR 309 (Power 2.04 hypv)
2213 * HDEC => SPR 310 (Power 2.04 hypv)
2214 * HIOR => SPR 311 (hypv)
2215 * RMOR => SPR 312 (970)
2216 * HRMOR => SPR 313 (Power 2.04 hypv)
2217 * HSRR0 => SPR 314 (Power 2.04 hypv)
2218 * HSRR1 => SPR 315 (Power 2.04 hypv)
2219 * LPCR => SPR 316 (970)
2220 * LPIDR => SPR 317 (970)
2221 * SPEFSCR => SPR 512 (Power 2.04 emb)
2222 * EPR => SPR 702 (Power 2.04 emb)
2223 * perf => 768-783 (Power 2.04)
2224 * perf => 784-799 (Power 2.04)
2225 * PPR => SPR 896 (Power 2.04)
2226 * EPLC => SPR 947 (Power 2.04 emb)
2227 * EPSC => SPR 948 (Power 2.04 emb)
2228 * DABRX => 1015 (Power 2.04 hypv)
2229 * FPECR => SPR 1022 (?)
2230 * ... and more (thermal management, performance counters, ...)
2231 */
2232
2233 /*****************************************************************************/
2234 /* Exception vectors models */
2235 static void init_excp_4xx_real (CPUPPCState *env)
2236 {
2237 #if !defined(CONFIG_USER_ONLY)
2238 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2239 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2240 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2241 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2242 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2243 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2244 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2245 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2246 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2247 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2248 env->excp_prefix = 0x00000000;
2249 env->ivor_mask = 0x0000FFF0;
2250 env->ivpr_mask = 0xFFFF0000;
2251 /* Hardware reset vector */
2252 env->hreset_vector = 0xFFFFFFFCUL;
2253 #endif
2254 }
2255
2256 static void init_excp_4xx_softmmu (CPUPPCState *env)
2257 {
2258 #if !defined(CONFIG_USER_ONLY)
2259 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2260 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2261 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2262 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2263 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2264 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2265 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2266 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2267 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2268 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2269 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2270 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2271 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2272 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2273 env->excp_prefix = 0x00000000;
2274 env->ivor_mask = 0x0000FFF0;
2275 env->ivpr_mask = 0xFFFF0000;
2276 /* Hardware reset vector */
2277 env->hreset_vector = 0xFFFFFFFCUL;
2278 #endif
2279 }
2280
2281 static void init_excp_BookE (CPUPPCState *env)
2282 {
2283 #if !defined(CONFIG_USER_ONLY)
2284 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2285 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2286 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2287 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2288 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2289 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2290 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2291 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2292 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2293 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2294 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2295 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2296 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2297 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2298 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2299 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2300 env->excp_prefix = 0x00000000;
2301 env->ivor_mask = 0x0000FFE0;
2302 env->ivpr_mask = 0xFFFF0000;
2303 /* Hardware reset vector */
2304 env->hreset_vector = 0xFFFFFFFCUL;
2305 #endif
2306 }
2307
2308 static void init_excp_601 (CPUPPCState *env)
2309 {
2310 #if !defined(CONFIG_USER_ONLY)
2311 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2312 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2313 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2314 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2315 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2316 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2317 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2318 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2319 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2320 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2321 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2322 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2323 env->excp_prefix = 0xFFF00000;
2324 /* Hardware reset vector */
2325 env->hreset_vector = 0xFFFFFFFCUL;
2326 #endif
2327 }
2328
2329 static void init_excp_602 (CPUPPCState *env)
2330 {
2331 #if !defined(CONFIG_USER_ONLY)
2332 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2333 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2334 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2335 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2336 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2337 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2338 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2339 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2340 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2341 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2342 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2343 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2344 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2345 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2346 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2347 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2348 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2349 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2350 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2351 env->excp_prefix = 0xFFF00000;
2352 /* Hardware reset vector */
2353 env->hreset_vector = 0xFFFFFFFCUL;
2354 #endif
2355 }
2356
2357 static void init_excp_603 (CPUPPCState *env)
2358 {
2359 #if !defined(CONFIG_USER_ONLY)
2360 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2361 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2362 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2363 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2364 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2365 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2366 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2367 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2368 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2369 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2370 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2371 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2372 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2373 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2374 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2375 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2376 /* Hardware reset vector */
2377 env->hreset_vector = 0xFFFFFFFCUL;
2378 #endif
2379 }
2380
2381 static void init_excp_G2 (CPUPPCState *env)
2382 {
2383 #if !defined(CONFIG_USER_ONLY)
2384 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2385 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2386 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2387 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2388 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2389 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2390 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2391 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2392 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2393 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2394 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2395 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2396 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2397 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2398 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2399 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2400 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2401 /* Hardware reset vector */
2402 env->hreset_vector = 0xFFFFFFFCUL;
2403 #endif
2404 }
2405
2406 static void init_excp_604 (CPUPPCState *env)
2407 {
2408 #if !defined(CONFIG_USER_ONLY)
2409 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2410 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2411 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2412 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2413 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2414 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2415 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2416 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2417 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2418 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2419 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2420 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2421 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2422 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2423 /* Hardware reset vector */
2424 env->hreset_vector = 0xFFFFFFFCUL;
2425 #endif
2426 }
2427
2428 #if defined(TARGET_PPC64)
2429 static void init_excp_620 (CPUPPCState *env)
2430 {
2431 #if !defined(CONFIG_USER_ONLY)
2432 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2433 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2434 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2435 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2436 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2437 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2438 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2439 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2440 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2441 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2442 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2443 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2444 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2445 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2446 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2447 /* Hardware reset vector */
2448 env->hreset_vector = 0x0000000000000100ULL; /* ? */
2449 #endif
2450 }
2451 #endif /* defined(TARGET_PPC64) */
2452
2453 static void init_excp_7x0 (CPUPPCState *env)
2454 {
2455 #if !defined(CONFIG_USER_ONLY)
2456 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2457 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2458 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2459 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2460 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2461 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2462 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2463 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2464 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2465 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2466 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2467 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2468 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2469 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2470 /* Hardware reset vector */
2471 env->hreset_vector = 0xFFFFFFFCUL;
2472 #endif
2473 }
2474
2475 static void init_excp_750FX (CPUPPCState *env)
2476 {
2477 #if !defined(CONFIG_USER_ONLY)
2478 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2479 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2480 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2481 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2482 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2483 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2484 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2485 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2486 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2487 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2488 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2489 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2490 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2491 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2492 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2493 /* Hardware reset vector */
2494 env->hreset_vector = 0xFFFFFFFCUL;
2495 #endif
2496 }
2497
2498 static void init_excp_7400 (CPUPPCState *env)
2499 {
2500 #if !defined(CONFIG_USER_ONLY)
2501 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2502 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2503 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2504 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2505 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2506 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2507 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2508 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2509 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2510 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2511 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2512 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2513 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2514 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2515 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2516 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2517 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2518 /* Hardware reset vector */
2519 env->hreset_vector = 0xFFFFFFFCUL;
2520 #endif
2521 }
2522
2523 static void init_excp_7450 (CPUPPCState *env)
2524 {
2525 #if !defined(CONFIG_USER_ONLY)
2526 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2527 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2528 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2529 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2530 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2531 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2532 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2533 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2534 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2535 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2536 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2537 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2538 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2539 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2540 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2541 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2542 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2543 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2544 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2545 /* Hardware reset vector */
2546 env->hreset_vector = 0xFFFFFFFCUL;
2547 #endif
2548 }
2549
2550 #if defined (TARGET_PPC64)
2551 static void init_excp_970 (CPUPPCState *env)
2552 {
2553 #if !defined(CONFIG_USER_ONLY)
2554 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2555 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2556 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2557 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2558 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2559 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2560 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2561 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2562 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2563 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2564 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2565 #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2566 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2567 #endif
2568 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2569 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2570 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2571 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2572 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2573 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2574 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2575 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2576 /* Hardware reset vector */
2577 env->hreset_vector = 0x0000000000000100ULL;
2578 #endif
2579 }
2580 #endif
2581
2582 /*****************************************************************************/
2583 /* PowerPC implementations definitions */
2584
2585 /* PowerPC 40x instruction set */
2586 #define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_CACHE_DCBZ | PPC_EMB_COMMON)
2587
2588 /* PowerPC 401 */
2589 #define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \
2590 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2591 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2592 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
2593 #define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx)
2594 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
2595 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
2596 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
2597 #define POWERPC_FLAG_401 (POWERPC_FLAG_NONE)
2598
2599 static void init_proc_401 (CPUPPCState *env)
2600 {
2601 gen_spr_40x(env);
2602 gen_spr_401_403(env);
2603 gen_spr_401(env);
2604 init_excp_4xx_real(env);
2605 env->dcache_line_size = 32;
2606 env->icache_line_size = 32;
2607 /* Allocate hardware IRQ controller */
2608 ppc40x_irq_init(env);
2609 }
2610
2611 /* PowerPC 401x2 */
2612 #define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | \
2613 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2614 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2615 PPC_CACHE_DCBA | PPC_MFTB | \
2616 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2617 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
2618 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
2619 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
2620 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
2621 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
2622 #define POWERPC_FLAG_401x2 (POWERPC_FLAG_NONE)
2623
2624 static void init_proc_401x2 (CPUPPCState *env)
2625 {
2626 gen_spr_40x(env);
2627 gen_spr_401_403(env);
2628 gen_spr_401x2(env);
2629 gen_spr_compress(env);
2630 /* Memory management */
2631 #if !defined(CONFIG_USER_ONLY)
2632 env->nb_tlb = 64;
2633 env->nb_ways = 1;
2634 env->id_tlbs = 0;
2635 #endif
2636 init_excp_4xx_softmmu(env);
2637 env->dcache_line_size = 32;
2638 env->icache_line_size = 32;
2639 /* Allocate hardware IRQ controller */
2640 ppc40x_irq_init(env);
2641 }
2642
2643 /* PowerPC 401x3 */
2644 #define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \
2645 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2646 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2647 PPC_CACHE_DCBA | PPC_MFTB | \
2648 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2649 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
2650 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
2651 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
2652 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
2653 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
2654 #define POWERPC_FLAG_401x3 (POWERPC_FLAG_NONE)
2655
2656 __attribute__ (( unused ))
2657 static void init_proc_401x3 (CPUPPCState *env)
2658 {
2659 gen_spr_40x(env);
2660 gen_spr_401_403(env);
2661 gen_spr_401(env);
2662 gen_spr_401x2(env);
2663 gen_spr_compress(env);
2664 init_excp_4xx_softmmu(env);
2665 env->dcache_line_size = 32;
2666 env->icache_line_size = 32;
2667 /* Allocate hardware IRQ controller */
2668 ppc40x_irq_init(env);
2669 }
2670
2671 /* IOP480 */
2672 #define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \
2673 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2674 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2675 PPC_CACHE_DCBA | \
2676 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2677 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
2678 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
2679 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
2680 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
2681 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
2682 #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_NONE)
2683
2684 static void init_proc_IOP480 (CPUPPCState *env)
2685 {
2686 gen_spr_40x(env);
2687 gen_spr_401_403(env);
2688 gen_spr_401x2(env);
2689 gen_spr_compress(env);
2690 /* Memory management */
2691 #if !defined(CONFIG_USER_ONLY)
2692 env->nb_tlb = 64;
2693 env->nb_ways = 1;
2694 env->id_tlbs = 0;
2695 #endif
2696 init_excp_4xx_softmmu(env);
2697 env->dcache_line_size = 32;
2698 env->icache_line_size = 32;
2699 /* Allocate hardware IRQ controller */
2700 ppc40x_irq_init(env);
2701 }
2702
2703 /* PowerPC 403 */
2704 #define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | \
2705 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2706 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2707 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2708 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
2709 #define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx)
2710 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
2711 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
2712 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
2713 #define POWERPC_FLAG_403 (POWERPC_FLAG_NONE)
2714
2715 static void init_proc_403 (CPUPPCState *env)
2716 {
2717 gen_spr_40x(env);
2718 gen_spr_401_403(env);
2719 gen_spr_403(env);
2720 gen_spr_403_real(env);
2721 init_excp_4xx_real(env);
2722 env->dcache_line_size = 32;
2723 env->icache_line_size = 32;
2724 /* Allocate hardware IRQ controller */
2725 ppc40x_irq_init(env);
2726 #if !defined(CONFIG_USER_ONLY)
2727 /* Hardware reset vector */
2728 env->hreset_vector = 0xFFFFFFFCUL;
2729 #endif
2730 }
2731
2732 /* PowerPC 403 GCX */
2733 #define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | \
2734 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2735 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2736 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2737 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
2738 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
2739 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
2740 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
2741 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
2742 #define POWERPC_FLAG_403GCX (POWERPC_FLAG_NONE)
2743
2744 static void init_proc_403GCX (CPUPPCState *env)
2745 {
2746 gen_spr_40x(env);
2747 gen_spr_401_403(env);
2748 gen_spr_403(env);
2749 gen_spr_403_real(env);
2750 gen_spr_403_mmu(env);
2751 /* Bus access control */
2752 /* not emulated, as Qemu never does speculative access */
2753 spr_register(env, SPR_40x_SGR, "SGR",
2754 SPR_NOACCESS, SPR_NOACCESS,
2755 &spr_read_generic, &spr_write_generic,
2756 0xFFFFFFFF);
2757 /* not emulated, as Qemu do not emulate caches */
2758 spr_register(env, SPR_40x_DCWR, "DCWR",
2759 SPR_NOACCESS, SPR_NOACCESS,
2760 &spr_read_generic, &spr_write_generic,
2761 0x00000000);
2762 /* Memory management */
2763 #if !defined(CONFIG_USER_ONLY)
2764 env->nb_tlb = 64;
2765 env->nb_ways = 1;
2766 env->id_tlbs = 0;
2767 #endif
2768 init_excp_4xx_softmmu(env);
2769 env->dcache_line_size = 32;
2770 env->icache_line_size = 32;
2771 /* Allocate hardware IRQ controller */
2772 ppc40x_irq_init(env);
2773 }
2774
2775 /* PowerPC 405 */
2776 #define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_MFTB | \
2777 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2778 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2779 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
2780 PPC_405_MAC)
2781 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
2782 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
2783 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
2784 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
2785 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
2786 #define POWERPC_FLAG_405 (POWERPC_FLAG_NONE)
2787
2788 static void init_proc_405 (CPUPPCState *env)
2789 {
2790 /* Time base */
2791 gen_tbl(env);
2792 gen_spr_40x(env);
2793 gen_spr_405(env);
2794 /* Bus access control */
2795 /* not emulated, as Qemu never does speculative access */
2796 spr_register(env, SPR_40x_SGR, "SGR",
2797 SPR_NOACCESS, SPR_NOACCESS,
2798 &spr_read_generic, &spr_write_generic,
2799 0xFFFFFFFF);
2800 /* not emulated, as Qemu do not emulate caches */
2801 spr_register(env, SPR_40x_DCWR, "DCWR",
2802 SPR_NOACCESS, SPR_NOACCESS,
2803 &spr_read_generic, &spr_write_generic,
2804 0x00000000);
2805 /* Memory management */
2806 #if !defined(CONFIG_USER_ONLY)
2807 env->nb_tlb = 64;
2808 env->nb_ways = 1;
2809 env->id_tlbs = 0;
2810 #endif
2811 init_excp_4xx_softmmu(env);
2812 env->dcache_line_size = 32;
2813 env->icache_line_size = 32;
2814 /* Allocate hardware IRQ controller */
2815 ppc40x_irq_init(env);
2816 }
2817
2818 /* PowerPC 440 EP */
2819 #define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | \
2820 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2821 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2822 PPC_440_SPEC | PPC_RFMCI)
2823 #define POWERPC_MSRM_440EP (0x000000000006D630ULL)
2824 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
2825 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
2826 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
2827 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
2828 #define POWERPC_FLAG_440EP (POWERPC_FLAG_NONE)
2829
2830 static void init_proc_440EP (CPUPPCState *env)
2831 {
2832 /* Time base */
2833 gen_tbl(env);
2834 gen_spr_BookE(env);
2835 gen_spr_440(env);
2836 /* XXX : not implemented */
2837 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2838 SPR_NOACCESS, SPR_NOACCESS,
2839 &spr_read_generic, &spr_write_generic,
2840 0x00000000);
2841 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2842 SPR_NOACCESS, SPR_NOACCESS,
2843 &spr_read_generic, &spr_write_generic,
2844 0x00000000);
2845 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2846 SPR_NOACCESS, SPR_NOACCESS,
2847 &spr_read_generic, &spr_write_generic,
2848 0x00000000);
2849 /* XXX : not implemented */
2850 spr_register(env, SPR_440_CCR1, "CCR1",
2851 SPR_NOACCESS, SPR_NOACCESS,
2852 &spr_read_generic, &spr_write_generic,
2853 0x00000000);
2854 /* Memory management */
2855 #if !defined(CONFIG_USER_ONLY)
2856 env->nb_tlb = 64;
2857 env->nb_ways = 1;
2858 env->id_tlbs = 0;
2859 #endif
2860 init_excp_BookE(env);
2861 env->dcache_line_size = 32;
2862 env->icache_line_size = 32;
2863 /* XXX: TODO: allocate internal IRQ controller */
2864 }
2865
2866 /* PowerPC 440 GP */
2867 #define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | \
2868 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2869 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2870 PPC_405_MAC | PPC_440_SPEC)
2871 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
2872 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
2873 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
2874 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
2875 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
2876 #define POWERPC_FLAG_440GP (POWERPC_FLAG_NONE)
2877
2878 static void init_proc_440GP (CPUPPCState *env)
2879 {
2880 /* Time base */
2881 gen_tbl(env);
2882 gen_spr_BookE(env);
2883 gen_spr_440(env);
2884 /* Memory management */
2885 #if !defined(CONFIG_USER_ONLY)
2886 env->nb_tlb = 64;
2887 env->nb_ways = 1;
2888 env->id_tlbs = 0;
2889 #endif
2890 init_excp_BookE(env);
2891 env->dcache_line_size = 32;
2892 env->icache_line_size = 32;
2893 /* XXX: TODO: allocate internal IRQ controller */
2894 }
2895
2896 /* PowerPC 440x4 */
2897 #define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \
2898 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2899 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2900 PPC_440_SPEC)
2901 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
2902 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
2903 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
2904 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
2905 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
2906 #define POWERPC_FLAG_440x4 (POWERPC_FLAG_NONE)
2907
2908 __attribute__ (( unused ))
2909 static void init_proc_440x4 (CPUPPCState *env)
2910 {
2911 /* Time base */
2912 gen_tbl(env);
2913 gen_spr_BookE(env);
2914 gen_spr_440(env);
2915 /* Memory management */
2916 #if !defined(CONFIG_USER_ONLY)
2917 env->nb_tlb = 64;
2918 env->nb_ways = 1;
2919 env->id_tlbs = 0;
2920 #endif
2921 init_excp_BookE(env);
2922 env->dcache_line_size = 32;
2923 env->icache_line_size = 32;
2924 /* XXX: TODO: allocate internal IRQ controller */
2925 }
2926
2927 /* PowerPC 440x5 */
2928 #define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \
2929 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2930 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2931 PPC_440_SPEC | PPC_RFMCI)
2932 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
2933 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
2934 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
2935 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
2936 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
2937 #define POWERPC_FLAG_440x5 (POWERPC_FLAG_NONE)
2938
2939 static void init_proc_440x5 (CPUPPCState *env)
2940 {
2941 /* Time base */
2942 gen_tbl(env);
2943 gen_spr_BookE(env);
2944 gen_spr_440(env);
2945 /* XXX : not implemented */
2946 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2947 SPR_NOACCESS, SPR_NOACCESS,
2948 &spr_read_generic, &spr_write_generic,
2949 0x00000000);
2950 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2951 SPR_NOACCESS, SPR_NOACCESS,
2952 &spr_read_generic, &spr_write_generic,
2953 0x00000000);
2954 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2955 SPR_NOACCESS, SPR_NOACCESS,
2956 &spr_read_generic, &spr_write_generic,
2957 0x00000000);
2958 /* XXX : not implemented */
2959 spr_register(env, SPR_440_CCR1, "CCR1",
2960 SPR_NOACCESS, SPR_NOACCESS,
2961 &spr_read_generic, &spr_write_generic,
2962 0x00000000);
2963 /* Memory management */
2964 #if !defined(CONFIG_USER_ONLY)
2965 env->nb_tlb = 64;
2966 env->nb_ways = 1;
2967 env->id_tlbs = 0;
2968 #endif
2969 init_excp_BookE(env);
2970 env->dcache_line_size = 32;
2971 env->icache_line_size = 32;
2972 /* XXX: TODO: allocate internal IRQ controller */
2973 }
2974
2975 /* PowerPC 460 (guessed) */
2976 #define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | \
2977 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2978 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2979 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
2980 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
2981 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
2982 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
2983 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
2984 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
2985 #define POWERPC_FLAG_460 (POWERPC_FLAG_NONE)
2986
2987 __attribute__ (( unused ))
2988 static void init_proc_460 (CPUPPCState *env)
2989 {
2990 /* Time base */
2991 gen_tbl(env);
2992 gen_spr_BookE(env);
2993 gen_spr_440(env);
2994 /* XXX : not implemented */
2995 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2996 SPR_NOACCESS, SPR_NOACCESS,
2997 &spr_read_generic, &spr_write_generic,
2998 0x00000000);
2999 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3000 SPR_NOACCESS, SPR_NOACCESS,
3001 &spr_read_generic, &spr_write_generic,
3002 0x00000000);
3003 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3004 SPR_NOACCESS, SPR_NOACCESS,
3005 &spr_read_generic, &spr_write_generic,
3006 0x00000000);
3007 /* XXX : not implemented */
3008 spr_register(env, SPR_440_CCR1, "CCR1",
3009 SPR_NOACCESS, SPR_NOACCESS,
3010 &spr_read_generic, &spr_write_generic,
3011 0x00000000);
3012 /* XXX : not implemented */
3013 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3014 &spr_read_generic, &spr_write_generic,
3015 &spr_read_generic, &spr_write_generic,
3016 0x00000000);
3017 /* Memory management */
3018 #if !defined(CONFIG_USER_ONLY)
3019 env->nb_tlb = 64;
3020 env->nb_ways = 1;
3021 env->id_tlbs = 0;
3022 #endif
3023 init_excp_BookE(env);
3024 env->dcache_line_size = 32;
3025 env->icache_line_size = 32;
3026 /* XXX: TODO: allocate internal IRQ controller */
3027 }
3028
3029 /* PowerPC 460F (guessed) */
3030 #define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
3031 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3032 PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
3033 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
3034 PPC_FLOAT_STFIWX | \
3035 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
3036 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3037 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3038 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3039 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3040 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3041 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3042 #define POWERPC_FLAG_460F (POWERPC_FLAG_NONE)
3043
3044 __attribute__ (( unused ))
3045 static void init_proc_460F (CPUPPCState *env)
3046 {
3047 /* Time base */
3048 gen_tbl(env);
3049 gen_spr_BookE(env);
3050 gen_spr_440(env);
3051 /* XXX : not implemented */
3052 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3053 SPR_NOACCESS, SPR_NOACCESS,
3054 &spr_read_generic, &spr_write_generic,
3055 0x00000000);
3056 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3057 SPR_NOACCESS, SPR_NOACCESS,
3058 &spr_read_generic, &spr_write_generic,
3059 0x00000000);
3060 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3061 SPR_NOACCESS, SPR_NOACCESS,
3062 &spr_read_generic, &spr_write_generic,
3063 0x00000000);
3064 /* XXX : not implemented */
3065 spr_register(env, SPR_440_CCR1, "CCR1",
3066 SPR_NOACCESS, SPR_NOACCESS,
3067 &spr_read_generic, &spr_write_generic,
3068 0x00000000);
3069 /* XXX : not implemented */
3070 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3071 &spr_read_generic, &spr_write_generic,
3072 &spr_read_generic, &spr_write_generic,
3073 0x00000000);
3074 /* Memory management */
3075 #if !defined(CONFIG_USER_ONLY)
3076 env->nb_tlb = 64;
3077 env->nb_ways = 1;
3078 env->id_tlbs = 0;
3079 #endif
3080 init_excp_BookE(env);
3081 env->dcache_line_size = 32;
3082 env->icache_line_size = 32;
3083 /* XXX: TODO: allocate internal IRQ controller */
3084 }
3085
3086 /* Generic BookE PowerPC */
3087 #define POWERPC_INSNS_BookE (POWERPC_INSNS_EMB | \
3088 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3089 PPC_CACHE_DCBA | \
3090 PPC_FLOAT | PPC_FLOAT_FSQRT | \
3091 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3092 PPC_FLOAT_FSEL | PPC_FLOAT_STFIW | \
3093 PPC_BOOKE)
3094 #define POWERPC_MSRM_BookE (0x000000000006D630ULL)
3095 #define POWERPC_MMU_BookE (POWERPC_MMU_BOOKE)
3096 #define POWERPC_EXCP_BookE (POWERPC_EXCP_BOOKE)
3097 #define POWERPC_INPUT_BookE (PPC_FLAGS_INPUT_BookE)
3098 #define POWERPC_BFDM_BookE (bfd_mach_ppc_403)
3099 #define POWERPC_FLAG_BookE (POWERPC_FLAG_NONE)
3100
3101 __attribute__ (( unused ))
3102 static void init_proc_BookE (CPUPPCState *env)
3103 {
3104 init_excp_BookE(env);
3105 env->dcache_line_size = 32;
3106 env->icache_line_size = 32;
3107 }
3108
3109 /* e200 core */
3110
3111 /* e300 core */
3112
3113 /* e500 core */
3114 #define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | \
3115 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3116 PPC_CACHE_DCBA | \
3117 PPC_BOOKE | PPC_E500_VECTOR)
3118 #define POWERPC_MMU_e500 (POWERPC_MMU_SOFT_4xx)
3119 #define POWERPC_EXCP_e500 (POWERPC_EXCP_40x)
3120 #define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
3121 #define POWERPC_BFDM_e500 (bfd_mach_ppc_403)
3122 #define POWERPC_FLAG_e500 (POWERPC_FLAG_SPE)
3123
3124 __attribute__ (( unused ))
3125 static void init_proc_e500 (CPUPPCState *env)
3126 {
3127 /* Time base */
3128 gen_tbl(env);
3129 gen_spr_BookE(env);
3130 /* Memory management */
3131 gen_spr_BookE_FSL(env);
3132 #if !defined(CONFIG_USER_ONLY)
3133 env->nb_tlb = 64;
3134 env->nb_ways = 1;
3135 env->id_tlbs = 0;
3136 #endif
3137 init_excp_BookE(env);
3138 env->dcache_line_size = 32;
3139 env->icache_line_size = 32;
3140 /* XXX: TODO: allocate internal IRQ controller */
3141 }
3142
3143 /* e600 core */
3144
3145 /* Non-embedded PowerPC */
3146 /* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
3147 #define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
3148 PPC_MEM_EIEIO | PPC_MEM_TLBIE)
3149 /* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
3150 #define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
3151 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3152 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3153 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB | \
3154 PPC_SEGMENT)
3155
3156 /* POWER : same as 601, without mfmsr, mfsr */
3157 #if defined(TODO)
3158 #define POWERPC_INSNS_POWER (XXX_TODO)
3159 /* POWER RSC (from RAD6000) */
3160 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
3161 #endif /* TODO */
3162
3163 /* PowerPC 601 */
3164 #define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ | \
3165 PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
3166 #define POWERPC_MSRM_601 (0x000000000000FE70ULL)
3167 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
3168 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
3169 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
3170 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
3171 #define POWERPC_FLAG_601 (POWERPC_FLAG_NONE)
3172
3173 static void init_proc_601 (CPUPPCState *env)
3174 {
3175 gen_spr_ne_601(env);
3176 gen_spr_601(env);
3177 /* Hardware implementation registers */
3178 /* XXX : not implemented */
3179 spr_register(env, SPR_HID0, "HID0",
3180 SPR_NOACCESS, SPR_NOACCESS,
3181 &spr_read_generic, &spr_write_generic,
3182 0x00000000);
3183 /* XXX : not implemented */
3184 spr_register(env, SPR_HID1, "HID1",
3185 SPR_NOACCESS, SPR_NOACCESS,
3186 &spr_read_generic, &spr_write_generic,
3187 0x00000000);
3188 /* XXX : not implemented */
3189 spr_register(env, SPR_601_HID2, "HID2",
3190 SPR_NOACCESS, SPR_NOACCESS,
3191 &spr_read_generic, &spr_write_generic,
3192 0x00000000);
3193 /* XXX : not implemented */
3194 spr_register(env, SPR_601_HID5, "HID5",
3195 SPR_NOACCESS, SPR_NOACCESS,
3196 &spr_read_generic, &spr_write_generic,
3197 0x00000000);
3198 /* XXX : not implemented */
3199 spr_register(env, SPR_601_HID15, "HID15",
3200 SPR_NOACCESS, SPR_NOACCESS,
3201 &spr_read_generic, &spr_write_generic,
3202 0x00000000);
3203 /* Memory management */
3204 #if !defined(CONFIG_USER_ONLY)
3205 env->nb_tlb = 64;
3206 env->nb_ways = 2;
3207 env->id_tlbs = 0;
3208 #endif
3209 init_excp_601(env);
3210 env->dcache_line_size = 64;
3211 env->icache_line_size = 64;
3212 /* XXX: TODO: allocate internal IRQ controller */
3213 }
3214
3215 /* PowerPC 602 */
3216 #define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
3217 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3218 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3219 PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\
3220 PPC_SEGMENT | PPC_602_SPEC)
3221 #define POWERPC_MSRM_602 (0x000000000033FF73ULL)
3222 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
3223 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
3224 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
3225 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
3226 #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR)
3227
3228 static void init_proc_602 (CPUPPCState *env)
3229 {
3230 gen_spr_ne_601(env);
3231 gen_spr_602(env);
3232 /* Time base */
3233 gen_tbl(env);
3234 /* hardware implementation registers */
3235 /* XXX : not implemented */
3236 spr_register(env, SPR_HID0, "HID0",
3237 SPR_NOACCESS, SPR_NOACCESS,
3238 &spr_read_generic, &spr_write_generic,
3239 0x00000000);
3240 /* XXX : not implemented */
3241 spr_register(env, SPR_HID1, "HID1",
3242 SPR_NOACCESS, SPR_NOACCESS,
3243 &spr_read_generic, &spr_write_generic,
3244 0x00000000);
3245 /* Memory management */
3246 gen_low_BATs(env);
3247 gen_6xx_7xx_soft_tlb(env, 64, 2);
3248 init_excp_602(env);
3249 env->dcache_line_size = 32;
3250 env->icache_line_size = 32;
3251 /* Allocate hardware IRQ controller */
3252 ppc6xx_irq_init(env);
3253 }
3254
3255 /* PowerPC 603 */
3256 #define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3257 #define POWERPC_MSRM_603 (0x000000000001FF73ULL)
3258 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
3259 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
3260 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
3261 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
3262 #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR)
3263
3264 static void init_proc_603 (CPUPPCState *env)
3265 {
3266 gen_spr_ne_601(env);
3267 gen_spr_603(env);
3268 /* Time base */
3269 gen_tbl(env);
3270 /* hardware implementation registers */
3271 /* XXX : not implemented */
3272 spr_register(env, SPR_HID0, "HID0",
3273 SPR_NOACCESS, SPR_NOACCESS,
3274 &spr_read_generic, &spr_write_generic,
3275 0x00000000);
3276 /* XXX : not implemented */
3277 spr_register(env, SPR_HID1, "HID1",
3278 SPR_NOACCESS, SPR_NOACCESS,
3279 &spr_read_generic, &spr_write_generic,
3280 0x00000000);
3281 /* Memory management */
3282 gen_low_BATs(env);
3283 gen_6xx_7xx_soft_tlb(env, 64, 2);
3284 init_excp_603(env);
3285 env->dcache_line_size = 32;
3286 env->icache_line_size = 32;
3287 /* Allocate hardware IRQ controller */
3288 ppc6xx_irq_init(env);
3289 }
3290
3291 /* PowerPC 603e */
3292 #define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3293 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
3294 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
3295 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
3296 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
3297 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
3298 #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR)
3299
3300 static void init_proc_603E (CPUPPCState *env)
3301 {
3302 gen_spr_ne_601(env);
3303 gen_spr_603(env);
3304 /* Time base */
3305 gen_tbl(env);
3306 /* hardware implementation registers */
3307 /* XXX : not implemented */
3308 spr_register(env, SPR_HID0, "HID0",
3309 SPR_NOACCESS, SPR_NOACCESS,
3310 &spr_read_generic, &spr_write_generic,
3311 0x00000000);
3312 /* XXX : not implemented */
3313 spr_register(env, SPR_HID1, "HID1",
3314 SPR_NOACCESS, SPR_NOACCESS,
3315 &spr_read_generic, &spr_write_generic,
3316 0x00000000);
3317 /* XXX : not implemented */
3318 spr_register(env, SPR_IABR, "IABR",
3319 SPR_NOACCESS, SPR_NOACCESS,
3320 &spr_read_generic, &spr_write_generic,
3321 0x00000000);
3322 /* Memory management */
3323 gen_low_BATs(env);
3324 gen_6xx_7xx_soft_tlb(env, 64, 2);
3325 init_excp_603(env);
3326 env->dcache_line_size = 32;
3327 env->icache_line_size = 32;
3328 /* Allocate hardware IRQ controller */
3329 ppc6xx_irq_init(env);
3330 }
3331
3332 /* PowerPC G2 */
3333 #define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3334 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3335 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3336 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3337 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3338 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3339 #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR)
3340
3341 static void init_proc_G2 (CPUPPCState *env)
3342 {
3343 gen_spr_ne_601(env);
3344 gen_spr_G2_755(env);
3345 gen_spr_G2(env);
3346 /* Time base */
3347 gen_tbl(env);
3348 /* Hardware implementation register */
3349 /* XXX : not implemented */
3350 spr_register(env, SPR_HID0, "HID0",
3351 SPR_NOACCESS, SPR_NOACCESS,
3352 &spr_read_generic, &spr_write_generic,
3353 0x00000000);
3354 /* XXX : not implemented */
3355 spr_register(env, SPR_HID1, "HID1",
3356 SPR_NOACCESS, SPR_NOACCESS,
3357 &spr_read_generic, &spr_write_generic,
3358 0x00000000);
3359 /* XXX : not implemented */
3360 spr_register(env, SPR_HID2, "HID2",
3361 SPR_NOACCESS, SPR_NOACCESS,
3362 &spr_read_generic, &spr_write_generic,
3363 0x00000000);
3364 /* Memory management */
3365 gen_low_BATs(env);
3366 gen_high_BATs(env);
3367 gen_6xx_7xx_soft_tlb(env, 64, 2);
3368 init_excp_G2(env);
3369 env->dcache_line_size = 32;
3370 env->icache_line_size = 32;
3371 /* Allocate hardware IRQ controller */
3372 ppc6xx_irq_init(env);
3373 }
3374
3375 /* PowerPC G2LE */
3376 #define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3377 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3378 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3379 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3380 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
3381 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
3382 #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR)
3383
3384 static void init_proc_G2LE (CPUPPCState *env)
3385 {
3386 gen_spr_ne_601(env);
3387 gen_spr_G2_755(env);
3388 gen_spr_G2(env);
3389 /* Time base */
3390 gen_tbl(env);
3391 /* Hardware implementation register */
3392 /* XXX : not implemented */
3393 spr_register(env, SPR_HID0, "HID0",
3394 SPR_NOACCESS, SPR_NOACCESS,
3395 &spr_read_generic, &spr_write_generic,
3396 0x00000000);
3397 /* XXX : not implemented */
3398 spr_register(env, SPR_HID1, "HID1",
3399 SPR_NOACCESS, SPR_NOACCESS,
3400 &spr_read_generic, &spr_write_generic,
3401 0x00000000);
3402 /* XXX : not implemented */
3403 spr_register(env, SPR_HID2, "HID2",
3404 SPR_NOACCESS, SPR_NOACCESS,
3405 &spr_read_generic, &spr_write_generic,
3406 0x00000000);
3407 /* Memory management */
3408 gen_low_BATs(env);
3409 gen_high_BATs(env);
3410 gen_6xx_7xx_soft_tlb(env, 64, 2);
3411 init_excp_G2(env);
3412 env->dcache_line_size = 32;
3413 env->icache_line_size = 32;
3414 /* Allocate hardware IRQ controller */
3415 ppc6xx_irq_init(env);
3416 }
3417
3418 /* PowerPC 604 */
3419 #define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3420 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
3421 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
3422 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
3423 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
3424 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
3425 #define POWERPC_FLAG_604 (POWERPC_FLAG_NONE)
3426
3427 static void init_proc_604 (CPUPPCState *env)
3428 {
3429 gen_spr_ne_601(env);
3430 gen_spr_604(env);
3431 /* Time base */
3432 gen_tbl(env);
3433 /* Hardware implementation registers */
3434 /* XXX : not implemented */
3435 spr_register(env, SPR_HID0, "HID0",
3436 SPR_NOACCESS, SPR_NOACCESS,
3437 &spr_read_generic, &spr_write_generic,
3438 0x00000000);
3439 /* XXX : not implemented */
3440 spr_register(env, SPR_HID1, "HID1",
3441 SPR_NOACCESS, SPR_NOACCESS,
3442 &spr_read_generic, &spr_write_generic,
3443 0x00000000);
3444 /* Memory management */
3445 gen_low_BATs(env);
3446 init_excp_604(env);
3447 env->dcache_line_size = 32;
3448 env->icache_line_size = 32;
3449 /* Allocate hardware IRQ controller */
3450 ppc6xx_irq_init(env);
3451 }
3452
3453 /* PowerPC 740/750 (aka G3) */
3454 #define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3455 #define POWERPC_MSRM_7x0 (0x000000000007FF77ULL)
3456 #define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
3457 //#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
3458 #define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
3459 #define POWERPC_BFDM_7x0 (bfd_mach_ppc_750)
3460 #define POWERPC_FLAG_7x0 (POWERPC_FLAG_NONE)
3461
3462 static void init_proc_7x0 (CPUPPCState *env)
3463 {
3464 gen_spr_ne_601(env);
3465 gen_spr_7xx(env);
3466 /* Time base */
3467 gen_tbl(env);
3468 /* Thermal management */
3469 gen_spr_thrm(env);
3470 /* Hardware implementation registers */
3471 /* XXX : not implemented */
3472 spr_register(env, SPR_HID0, "HID0",
3473 SPR_NOACCESS, SPR_NOACCESS,
3474 &spr_read_generic, &spr_write_generic,
3475 0x00000000);
3476 /* XXX : not implemented */
3477 spr_register(env, SPR_HID1, "HID1",
3478 SPR_NOACCESS, SPR_NOACCESS,
3479 &spr_read_generic, &spr_write_generic,
3480 0x00000000);
3481 /* Memory management */
3482 gen_low_BATs(env);
3483 init_excp_7x0(env);
3484 env->dcache_line_size = 32;
3485 env->icache_line_size = 32;
3486 /* Allocate hardware IRQ controller */
3487 ppc6xx_irq_init(env);
3488 }
3489
3490 /* PowerPC 750FX/GX */
3491 #define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN)
3492 #define POWERPC_MSRM_750fx (0x000000000007FF77ULL)
3493 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
3494 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
3495 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
3496 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
3497 #define POWERPC_FLAG_750fx (POWERPC_FLAG_NONE)
3498
3499 static void init_proc_750fx (CPUPPCState *env)
3500 {
3501 gen_spr_ne_601(env);
3502 gen_spr_7xx(env);
3503 /* Time base */
3504 gen_tbl(env);
3505 /* Thermal management */
3506 gen_spr_thrm(env);
3507 /* Hardware implementation registers */
3508 /* XXX : not implemented */
3509 spr_register(env, SPR_HID0, "HID0",
3510 SPR_NOACCESS, SPR_NOACCESS,
3511 &spr_read_generic, &spr_write_generic,
3512 0x00000000);
3513 /* XXX : not implemented */
3514 spr_register(env, SPR_HID1, "HID1",
3515 SPR_NOACCESS, SPR_NOACCESS,
3516 &spr_read_generic, &spr_write_generic,
3517 0x00000000);
3518 /* XXX : not implemented */
3519 spr_register(env, SPR_750_HID2, "HID2",
3520 SPR_NOACCESS, SPR_NOACCESS,
3521 &spr_read_generic, &spr_write_generic,
3522 0x00000000);
3523 /* Memory management */
3524 gen_low_BATs(env);
3525 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3526 gen_high_BATs(env);
3527 init_excp_750FX(env);
3528 env->dcache_line_size = 32;
3529 env->icache_line_size = 32;
3530 /* Allocate hardware IRQ controller */
3531 ppc6xx_irq_init(env);
3532 }
3533
3534 /* PowerPC 745/755 */
3535 #define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
3536 #define POWERPC_MSRM_7x5 (0x000000000007FF77ULL)
3537 #define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
3538 //#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
3539 #define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
3540 #define POWERPC_BFDM_7x5 (bfd_mach_ppc_750)
3541 #define POWERPC_FLAG_7x5 (POWERPC_FLAG_NONE)
3542
3543 static void init_proc_7x5 (CPUPPCState *env)
3544 {
3545 gen_spr_ne_601(env);
3546 gen_spr_G2_755(env);
3547 /* Time base */
3548 gen_tbl(env);
3549 /* L2 cache control */
3550 /* XXX : not implemented */
3551 spr_register(env, SPR_ICTC, "ICTC",
3552 SPR_NOACCESS, SPR_NOACCESS,
3553 &spr_read_generic, &spr_write_generic,
3554 0x00000000);
3555 /* XXX : not implemented */
3556 spr_register(env, SPR_L2PMCR, "L2PMCR",
3557 SPR_NOACCESS, SPR_NOACCESS,
3558 &spr_read_generic, &spr_write_generic,
3559 0x00000000);
3560 /* Hardware implementation registers */
3561 /* XXX : not implemented */
3562 spr_register(env, SPR_HID0, "HID0",
3563 SPR_NOACCESS, SPR_NOACCESS,
3564 &spr_read_generic, &spr_write_generic,
3565 0x00000000);
3566 /* XXX : not implemented */
3567 spr_register(env, SPR_HID1, "HID1",
3568 SPR_NOACCESS, SPR_NOACCESS,
3569 &spr_read_generic, &spr_write_generic,
3570 0x00000000);
3571 /* XXX : not implemented */
3572 spr_register(env, SPR_HID2, "HID2",
3573 SPR_NOACCESS, SPR_NOACCESS,
3574 &spr_read_generic, &spr_write_generic,
3575 0x00000000);
3576 /* Memory management */
3577 gen_low_BATs(env);
3578 gen_high_BATs(env);
3579 gen_6xx_7xx_soft_tlb(env, 64, 2);
3580 /* XXX: exception vectors ? */
3581 env->dcache_line_size = 32;
3582 env->icache_line_size = 32;
3583 /* Allocate hardware IRQ controller */
3584 ppc6xx_irq_init(env);
3585 #if !defined(CONFIG_USER_ONLY)
3586 /* Hardware reset vector */
3587 env->hreset_vector = 0xFFFFFFFCUL;
3588 #endif
3589 }
3590
3591 /* PowerPC 7400 (aka G4) */
3592 #define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3593 PPC_EXTERN | PPC_MEM_TLBIA | \
3594 PPC_ALTIVEC)
3595 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
3596 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
3597 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
3598 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
3599 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
3600 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE)
3601
3602 static void init_proc_7400 (CPUPPCState *env)
3603 {
3604 gen_spr_ne_601(env);
3605 gen_spr_7xx(env);
3606 /* Time base */
3607 gen_tbl(env);
3608 /* 74xx specific SPR */
3609 gen_spr_74xx(env);
3610 /* Thermal management */
3611 gen_spr_thrm(env);
3612 /* Memory management */
3613 gen_low_BATs(env);
3614 init_excp_7400(env);
3615 env->dcache_line_size = 32;
3616 env->icache_line_size = 32;
3617 /* Allocate hardware IRQ controller */
3618 ppc6xx_irq_init(env);
3619 }
3620
3621 /* PowerPC 7410 (aka G4) */
3622 #define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3623 PPC_EXTERN | PPC_MEM_TLBIA | \
3624 PPC_ALTIVEC)
3625 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
3626 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
3627 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
3628 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
3629 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
3630 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE)
3631
3632 static void init_proc_7410 (CPUPPCState *env)
3633 {
3634 gen_spr_ne_601(env);
3635 gen_spr_7xx(env);
3636 /* Time base */
3637 gen_tbl(env);
3638 /* 74xx specific SPR */
3639 gen_spr_74xx(env);
3640 /* Thermal management */
3641 gen_spr_thrm(env);
3642 /* L2PMCR */
3643 /* XXX : not implemented */
3644 spr_register(env, SPR_L2PMCR, "L2PMCR",
3645 SPR_NOACCESS, SPR_NOACCESS,
3646 &spr_read_generic, &spr_write_generic,
3647 0x00000000);
3648 /* LDSTDB */
3649 /* XXX : not implemented */
3650 spr_register(env, SPR_LDSTDB, "LDSTDB",
3651 SPR_NOACCESS, SPR_NOACCESS,
3652 &spr_read_generic, &spr_write_generic,
3653 0x00000000);
3654 /* Memory management */
3655 gen_low_BATs(env);
3656 init_excp_7400(env);
3657 env->dcache_line_size = 32;
3658 env->icache_line_size = 32;
3659 /* Allocate hardware IRQ controller */
3660 ppc6xx_irq_init(env);
3661 }
3662
3663 /* PowerPC 7440 (aka G4) */
3664 #define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3665 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3666 PPC_ALTIVEC)
3667 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
3668 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
3669 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
3670 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
3671 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
3672 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE)
3673
3674 __attribute__ (( unused ))
3675 static void init_proc_7440 (CPUPPCState *env)
3676 {
3677 gen_spr_ne_601(env);
3678 gen_spr_7xx(env);
3679 /* Time base */
3680 gen_tbl(env);
3681 /* 74xx specific SPR */
3682 gen_spr_74xx(env);
3683 /* LDSTCR */
3684 /* XXX : not implemented */
3685 spr_register(env, SPR_LDSTCR, "LDSTCR",
3686 SPR_NOACCESS, SPR_NOACCESS,
3687 &spr_read_generic, &spr_write_generic,
3688 0x00000000);
3689 /* ICTRL */
3690 /* XXX : not implemented */
3691 spr_register(env, SPR_ICTRL, "ICTRL",
3692 SPR_NOACCESS, SPR_NOACCESS,
3693 &spr_read_generic, &spr_write_generic,
3694 0x00000000);
3695 /* MSSSR0 */
3696 /* XXX : not implemented */
3697 spr_register(env, SPR_MSSSR0, "MSSSR0",
3698 SPR_NOACCESS, SPR_NOACCESS,
3699 &spr_read_generic, &spr_write_generic,
3700 0x00000000);
3701 /* PMC */
3702 /* XXX : not implemented */
3703 spr_register(env, SPR_PMC5, "PMC5",
3704 SPR_NOACCESS, SPR_NOACCESS,
3705 &spr_read_generic, &spr_write_generic,
3706 0x00000000);
3707 /* XXX : not implemented */
3708 spr_register(env, SPR_UPMC5, "UPMC5",
3709 &spr_read_ureg, SPR_NOACCESS,
3710 &spr_read_ureg, SPR_NOACCESS,
3711 0x00000000);
3712 /* XXX : not implemented */
3713 spr_register(env, SPR_PMC6, "PMC6",
3714 SPR_NOACCESS, SPR_NOACCESS,
3715 &spr_read_generic, &spr_write_generic,
3716 0x00000000);
3717 /* XXX : not implemented */
3718 spr_register(env, SPR_UPMC6, "UPMC6",
3719 &spr_read_ureg, SPR_NOACCESS,
3720 &spr_read_ureg, SPR_NOACCESS,
3721 0x00000000);
3722 /* Memory management */
3723 gen_low_BATs(env);
3724 gen_74xx_soft_tlb(env, 128, 2);
3725 init_excp_7450(env);
3726 env->dcache_line_size = 32;
3727 env->icache_line_size = 32;
3728 /* Allocate hardware IRQ controller */
3729 ppc6xx_irq_init(env);
3730 }
3731
3732 /* PowerPC 7450 (aka G4) */
3733 #define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3734 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3735 PPC_ALTIVEC)
3736 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
3737 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
3738 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
3739 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
3740 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
3741 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE)
3742
3743 __attribute__ (( unused ))
3744 static void init_proc_7450 (CPUPPCState *env)
3745 {
3746 gen_spr_ne_601(env);
3747 gen_spr_7xx(env);
3748 /* Time base */
3749 gen_tbl(env);
3750 /* 74xx specific SPR */
3751 gen_spr_74xx(env);
3752 /* Level 3 cache control */
3753 gen_l3_ctrl(env);
3754 /* LDSTCR */
3755 /* XXX : not implemented */
3756 spr_register(env, SPR_LDSTCR, "LDSTCR",
3757 SPR_NOACCESS, SPR_NOACCESS,
3758 &spr_read_generic, &spr_write_generic,
3759 0x00000000);
3760 /* ICTRL */
3761 /* XXX : not implemented */
3762 spr_register(env, SPR_ICTRL, "ICTRL",
3763 SPR_NOACCESS, SPR_NOACCESS,
3764 &spr_read_generic, &spr_write_generic,
3765 0x00000000);
3766 /* MSSSR0 */
3767 /* XXX : not implemented */
3768 spr_register(env, SPR_MSSSR0, "MSSSR0",
3769 SPR_NOACCESS, SPR_NOACCESS,
3770 &spr_read_generic, &spr_write_generic,
3771 0x00000000);
3772 /* PMC */
3773 /* XXX : not implemented */
3774 spr_register(env, SPR_PMC5, "PMC5",
3775 SPR_NOACCESS, SPR_NOACCESS,
3776 &spr_read_generic, &spr_write_generic,
3777 0x00000000);
3778 /* XXX : not implemented */
3779 spr_register(env, SPR_UPMC5, "UPMC5",
3780 &spr_read_ureg, SPR_NOACCESS,
3781 &spr_read_ureg, SPR_NOACCESS,
3782 0x00000000);
3783 /* XXX : not implemented */
3784 spr_register(env, SPR_PMC6, "PMC6",
3785 SPR_NOACCESS, SPR_NOACCESS,
3786 &spr_read_generic, &spr_write_generic,
3787 0x00000000);
3788 /* XXX : not implemented */
3789 spr_register(env, SPR_UPMC6, "UPMC6",
3790 &spr_read_ureg, SPR_NOACCESS,
3791 &spr_read_ureg, SPR_NOACCESS,
3792 0x00000000);
3793 /* Memory management */
3794 gen_low_BATs(env);
3795 gen_74xx_soft_tlb(env, 128, 2);
3796 init_excp_7450(env);
3797 env->dcache_line_size = 32;
3798 env->icache_line_size = 32;
3799 /* Allocate hardware IRQ controller */
3800 ppc6xx_irq_init(env);
3801 }
3802
3803 /* PowerPC 7445 (aka G4) */
3804 #define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3805 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3806 PPC_ALTIVEC)
3807 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
3808 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
3809 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
3810 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
3811 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
3812 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE)
3813
3814 __attribute__ (( unused ))
3815 static void init_proc_7445 (CPUPPCState *env)
3816 {
3817 gen_spr_ne_601(env);
3818 gen_spr_7xx(env);
3819 /* Time base */
3820 gen_tbl(env);
3821 /* 74xx specific SPR */
3822 gen_spr_74xx(env);
3823 /* LDSTCR */
3824 /* XXX : not implemented */
3825 spr_register(env, SPR_LDSTCR, "LDSTCR",
3826 SPR_NOACCESS, SPR_NOACCESS,
3827 &spr_read_generic, &spr_write_generic,
3828 0x00000000);
3829 /* ICTRL */
3830 /* XXX : not implemented */
3831 spr_register(env, SPR_ICTRL, "ICTRL",
3832 SPR_NOACCESS, SPR_NOACCESS,
3833 &spr_read_generic, &spr_write_generic,
3834 0x00000000);
3835 /* MSSSR0 */
3836 /* XXX : not implemented */
3837 spr_register(env, SPR_MSSSR0, "MSSSR0",
3838 SPR_NOACCESS, SPR_NOACCESS,
3839 &spr_read_generic, &spr_write_generic,
3840 0x00000000);
3841 /* PMC */
3842 /* XXX : not implemented */
3843 spr_register(env, SPR_PMC5, "PMC5",
3844 SPR_NOACCESS, SPR_NOACCESS,
3845 &spr_read_generic, &spr_write_generic,
3846 0x00000000);
3847 /* XXX : not implemented */
3848 spr_register(env, SPR_UPMC5, "UPMC5",
3849 &spr_read_ureg, SPR_NOACCESS,
3850 &spr_read_ureg, SPR_NOACCESS,
3851 0x00000000);
3852 /* XXX : not implemented */
3853 spr_register(env, SPR_PMC6, "PMC6",
3854 SPR_NOACCESS, SPR_NOACCESS,
3855 &spr_read_generic, &spr_write_generic,
3856 0x00000000);
3857 /* XXX : not implemented */
3858 spr_register(env, SPR_UPMC6, "UPMC6",
3859 &spr_read_ureg, SPR_NOACCESS,
3860 &spr_read_ureg, SPR_NOACCESS,
3861 0x00000000);
3862 /* SPRGs */
3863 spr_register(env, SPR_SPRG4, "SPRG4",
3864 SPR_NOACCESS, SPR_NOACCESS,
3865 &spr_read_generic, &spr_write_generic,
3866 0x00000000);
3867 spr_register(env, SPR_USPRG4, "USPRG4",
3868 &spr_read_ureg, SPR_NOACCESS,
3869 &spr_read_ureg, SPR_NOACCESS,
3870 0x00000000);
3871 spr_register(env, SPR_SPRG5, "SPRG5",
3872 SPR_NOACCESS, SPR_NOACCESS,
3873 &spr_read_generic, &spr_write_generic,
3874 0x00000000);
3875 spr_register(env, SPR_USPRG5, "USPRG5",
3876 &spr_read_ureg, SPR_NOACCESS,
3877 &spr_read_ureg, SPR_NOACCESS,
3878 0x00000000);
3879 spr_register(env, SPR_SPRG6, "SPRG6",
3880 SPR_NOACCESS, SPR_NOACCESS,
3881 &spr_read_generic, &spr_write_generic,
3882 0x00000000);
3883 spr_register(env, SPR_USPRG6, "USPRG6",
3884 &spr_read_ureg, SPR_NOACCESS,
3885 &spr_read_ureg, SPR_NOACCESS,
3886 0x00000000);
3887 spr_register(env, SPR_SPRG7, "SPRG7",
3888 SPR_NOACCESS, SPR_NOACCESS,
3889 &spr_read_generic, &spr_write_generic,
3890 0x00000000);
3891 spr_register(env, SPR_USPRG7, "USPRG7",
3892 &spr_read_ureg, SPR_NOACCESS,
3893 &spr_read_ureg, SPR_NOACCESS,
3894 0x00000000);
3895 /* Memory management */
3896 gen_low_BATs(env);
3897 gen_high_BATs(env);
3898 gen_74xx_soft_tlb(env, 128, 2);
3899 init_excp_7450(env);
3900 env->dcache_line_size = 32;
3901 env->icache_line_size = 32;
3902 /* Allocate hardware IRQ controller */
3903 ppc6xx_irq_init(env);
3904 }
3905
3906 /* PowerPC 7455 (aka G4) */
3907 #define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3908 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3909 PPC_ALTIVEC)
3910 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
3911 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
3912 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
3913 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
3914 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
3915 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE)
3916
3917 __attribute__ (( unused ))
3918 static void init_proc_7455 (CPUPPCState *env)
3919 {
3920 gen_spr_ne_601(env);
3921 gen_spr_7xx(env);
3922 /* Time base */
3923 gen_tbl(env);
3924 /* 74xx specific SPR */
3925 gen_spr_74xx(env);
3926 /* Level 3 cache control */
3927 gen_l3_ctrl(env);
3928 /* LDSTCR */
3929 /* XXX : not implemented */
3930 spr_register(env, SPR_LDSTCR, "LDSTCR",
3931 SPR_NOACCESS, SPR_NOACCESS,
3932 &spr_read_generic, &spr_write_generic,
3933 0x00000000);
3934 /* ICTRL */
3935 /* XXX : not implemented */
3936 spr_register(env, SPR_ICTRL, "ICTRL",
3937 SPR_NOACCESS, SPR_NOACCESS,
3938 &spr_read_generic, &spr_write_generic,
3939 0x00000000);
3940 /* MSSSR0 */
3941 /* XXX : not implemented */
3942 spr_register(env, SPR_MSSSR0, "MSSSR0",
3943 SPR_NOACCESS, SPR_NOACCESS,
3944 &spr_read_generic, &spr_write_generic,
3945 0x00000000);
3946 /* PMC */
3947 /* XXX : not implemented */
3948 spr_register(env, SPR_PMC5, "PMC5",
3949 SPR_NOACCESS, SPR_NOACCESS,
3950 &spr_read_generic, &spr_write_generic,
3951 0x00000000);
3952 /* XXX : not implemented */
3953 spr_register(env, SPR_UPMC5, "UPMC5",
3954 &spr_read_ureg, SPR_NOACCESS,
3955 &spr_read_ureg, SPR_NOACCESS,
3956 0x00000000);
3957 /* XXX : not implemented */
3958 spr_register(env, SPR_PMC6, "PMC6",
3959 SPR_NOACCESS, SPR_NOACCESS,
3960 &spr_read_generic, &spr_write_generic,
3961 0x00000000);
3962 /* XXX : not implemented */
3963 spr_register(env, SPR_UPMC6, "UPMC6",
3964 &spr_read_ureg, SPR_NOACCESS,
3965 &spr_read_ureg, SPR_NOACCESS,
3966 0x00000000);
3967 /* SPRGs */
3968 spr_register(env, SPR_SPRG4, "SPRG4",
3969 SPR_NOACCESS, SPR_NOACCESS,
3970 &spr_read_generic, &spr_write_generic,
3971 0x00000000);
3972 spr_register(env, SPR_USPRG4, "USPRG4",
3973 &spr_read_ureg, SPR_NOACCESS,
3974 &spr_read_ureg, SPR_NOACCESS,
3975 0x00000000);
3976 spr_register(env, SPR_SPRG5, "SPRG5",
3977 SPR_NOACCESS, SPR_NOACCESS,
3978 &spr_read_generic, &spr_write_generic,
3979 0x00000000);
3980 spr_register(env, SPR_USPRG5, "USPRG5",
3981 &spr_read_ureg, SPR_NOACCESS,
3982 &spr_read_ureg, SPR_NOACCESS,
3983 0x00000000);
3984 spr_register(env, SPR_SPRG6, "SPRG6",
3985 SPR_NOACCESS, SPR_NOACCESS,
3986 &spr_read_generic, &spr_write_generic,
3987 0x00000000);
3988 spr_register(env, SPR_USPRG6, "USPRG6",
3989 &spr_read_ureg, SPR_NOACCESS,
3990 &spr_read_ureg, SPR_NOACCESS,
3991 0x00000000);
3992 spr_register(env, SPR_SPRG7, "SPRG7",
3993 SPR_NOACCESS, SPR_NOACCESS,
3994 &spr_read_generic, &spr_write_generic,
3995 0x00000000);
3996 spr_register(env, SPR_USPRG7, "USPRG7",
3997 &spr_read_ureg, SPR_NOACCESS,
3998 &spr_read_ureg, SPR_NOACCESS,
3999 0x00000000);
4000 /* Memory management */
4001 gen_low_BATs(env);
4002 gen_high_BATs(env);
4003 gen_74xx_soft_tlb(env, 128, 2);
4004 init_excp_7450(env);
4005 env->dcache_line_size = 32;
4006 env->icache_line_size = 32;
4007 /* Allocate hardware IRQ controller */
4008 ppc6xx_irq_init(env);
4009 }
4010
4011 #if defined (TARGET_PPC64)
4012 #define POWERPC_INSNS_WORK64 (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
4013 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
4014 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
4015 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)
4016 /* PowerPC 970 */
4017 #define POWERPC_INSNS_970 (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4018 PPC_64B | PPC_ALTIVEC | \
4019 PPC_SEGMENT_64B | PPC_SLBI)
4020 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
4021 #define POWERPC_MMU_970 (POWERPC_MMU_64B)
4022 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
4023 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
4024 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
4025 #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE)
4026
4027 static void init_proc_970 (CPUPPCState *env)
4028 {
4029 gen_spr_ne_601(env);
4030 gen_spr_7xx(env);
4031 /* Time base */
4032 gen_tbl(env);
4033 /* Hardware implementation registers */
4034 /* XXX : not implemented */
4035 spr_register(env, SPR_HID0, "HID0",
4036 SPR_NOACCESS, SPR_NOACCESS,
4037 &spr_read_generic, &spr_write_clear,
4038 0x60000000);
4039 /* XXX : not implemented */
4040 spr_register(env, SPR_HID1, "HID1",
4041 SPR_NOACCESS, SPR_NOACCESS,
4042 &spr_read_generic, &spr_write_generic,
4043 0x00000000);
4044 /* XXX : not implemented */
4045 spr_register(env, SPR_750_HID2, "HID2",
4046 SPR_NOACCESS, SPR_NOACCESS,
4047 &spr_read_generic, &spr_write_generic,
4048 0x00000000);
4049 /* XXX : not implemented */
4050 spr_register(env, SPR_970_HID5, "HID5",
4051 SPR_NOACCESS, SPR_NOACCESS,
4052 &spr_read_generic, &spr_write_generic,
4053 #if defined(CONFIG_USER_ONLY)
4054 0x00000080
4055 #else
4056 0x00000000
4057 #endif
4058 );
4059 /* Memory management */
4060 /* XXX: not correct */
4061 gen_low_BATs(env);
4062 /* XXX : not implemented */
4063 spr_register(env, SPR_MMUCFG, "MMUCFG",
4064 SPR_NOACCESS, SPR_NOACCESS,
4065 &spr_read_generic, SPR_NOACCESS,
4066 0x00000000); /* TOFIX */
4067 /* XXX : not implemented */
4068 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4069 SPR_NOACCESS, SPR_NOACCESS,
4070 &spr_read_generic, &spr_write_generic,
4071 0x00000000); /* TOFIX */
4072 spr_register(env, SPR_HIOR, "SPR_HIOR",
4073 SPR_NOACCESS, SPR_NOACCESS,
4074 &spr_read_generic, &spr_write_generic,
4075 0xFFF00000); /* XXX: This is a hack */
4076 #if !defined(CONFIG_USER_ONLY)
4077 env->excp_prefix = 0xFFF00000;
4078 #endif
4079 #if !defined(CONFIG_USER_ONLY)
4080 env->slb_nr = 32;
4081 #endif
4082 init_excp_970(env);
4083 env->dcache_line_size = 128;
4084 env->icache_line_size = 128;
4085 /* Allocate hardware IRQ controller */
4086 ppc970_irq_init(env);
4087 }
4088
4089 /* PowerPC 970FX (aka G5) */
4090 #define POWERPC_INSNS_970FX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4091 PPC_64B | PPC_ALTIVEC | \
4092 PPC_SEGMENT_64B | PPC_SLBI)
4093 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
4094 #define POWERPC_MMU_970FX (POWERPC_MMU_64B)
4095 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
4096 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
4097 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
4098 #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE)
4099
4100 static void init_proc_970FX (CPUPPCState *env)
4101 {
4102 gen_spr_ne_601(env);
4103 gen_spr_7xx(env);
4104 /* Time base */
4105 gen_tbl(env);
4106 /* Hardware implementation registers */
4107 /* XXX : not implemented */
4108 spr_register(env, SPR_HID0, "HID0",
4109 SPR_NOACCESS, SPR_NOACCESS,
4110 &spr_read_generic, &spr_write_clear,
4111 0x60000000);
4112 /* XXX : not implemented */
4113 spr_register(env, SPR_HID1, "HID1",
4114 SPR_NOACCESS, SPR_NOACCESS,
4115 &spr_read_generic, &spr_write_generic,
4116 0x00000000);
4117 /* XXX : not implemented */
4118 spr_register(env, SPR_750_HID2, "HID2",
4119 SPR_NOACCESS, SPR_NOACCESS,
4120 &spr_read_generic, &spr_write_generic,
4121 0x00000000);
4122 /* XXX : not implemented */
4123 spr_register(env, SPR_970_HID5, "HID5",
4124 SPR_NOACCESS, SPR_NOACCESS,
4125 &spr_read_generic, &spr_write_generic,
4126 #if defined(CONFIG_USER_ONLY)
4127 0x00000080
4128 #else
4129 0x00000000
4130 #endif
4131 );
4132 /* Memory management */
4133 /* XXX: not correct */
4134 gen_low_BATs(env);
4135 /* XXX : not implemented */
4136 spr_register(env, SPR_MMUCFG, "MMUCFG",
4137 SPR_NOACCESS, SPR_NOACCESS,
4138 &spr_read_generic, SPR_NOACCESS,
4139 0x00000000); /* TOFIX */
4140 /* XXX : not implemented */
4141 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4142 SPR_NOACCESS, SPR_NOACCESS,
4143 &spr_read_generic, &spr_write_generic,
4144 0x00000000); /* TOFIX */
4145 spr_register(env, SPR_HIOR, "SPR_HIOR",
4146 SPR_NOACCESS, SPR_NOACCESS,
4147 &spr_read_generic, &spr_write_generic,
4148 0xFFF00000); /* XXX: This is a hack */
4149 #if !defined(CONFIG_USER_ONLY)
4150 env->excp_prefix = 0xFFF00000;
4151 #endif
4152 #if !defined(CONFIG_USER_ONLY)
4153 env->slb_nr = 32;
4154 #endif
4155 init_excp_970(env);
4156 env->dcache_line_size = 128;
4157 env->icache_line_size = 128;
4158 /* Allocate hardware IRQ controller */
4159 ppc970_irq_init(env);
4160 }
4161
4162 /* PowerPC 970 GX */
4163 #define POWERPC_INSNS_970GX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4164 PPC_64B | PPC_ALTIVEC | \
4165 PPC_SEGMENT_64B | PPC_SLBI)
4166 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
4167 #define POWERPC_MMU_970GX (POWERPC_MMU_64B)
4168 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
4169 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
4170 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
4171 #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE)
4172
4173 static void init_proc_970GX (CPUPPCState *env)
4174 {
4175 gen_spr_ne_601(env);
4176 gen_spr_7xx(env);
4177 /* Time base */
4178 gen_tbl(env);
4179 /* Hardware implementation registers */
4180 /* XXX : not implemented */
4181 spr_register(env, SPR_HID0, "HID0",
4182 SPR_NOACCESS, SPR_NOACCESS,
4183 &spr_read_generic, &spr_write_clear,
4184 0x60000000);
4185 /* XXX : not implemented */
4186 spr_register(env, SPR_HID1, "HID1",
4187 SPR_NOACCESS, SPR_NOACCESS,
4188 &spr_read_generic, &spr_write_generic,
4189 0x00000000);
4190 /* XXX : not implemented */
4191 spr_register(env, SPR_750_HID2, "HID2",
4192 SPR_NOACCESS, SPR_NOACCESS,
4193 &spr_read_generic, &spr_write_generic,
4194 0x00000000);
4195 /* XXX : not implemented */
4196 spr_register(env, SPR_970_HID5, "HID5",
4197 SPR_NOACCESS, SPR_NOACCESS,
4198 &spr_read_generic, &spr_write_generic,
4199 #if defined(CONFIG_USER_ONLY)
4200 0x00000080
4201 #else
4202 0x00000000
4203 #endif
4204 );
4205 /* Memory management */
4206 /* XXX: not correct */
4207 gen_low_BATs(env);
4208 /* XXX : not implemented */
4209 spr_register(env, SPR_MMUCFG, "MMUCFG",
4210 SPR_NOACCESS, SPR_NOACCESS,
4211 &spr_read_generic, SPR_NOACCESS,
4212 0x00000000); /* TOFIX */
4213 /* XXX : not implemented */
4214 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4215 SPR_NOACCESS, SPR_NOACCESS,
4216 &spr_read_generic, &spr_write_generic,
4217 0x00000000); /* TOFIX */
4218 spr_register(env, SPR_HIOR, "SPR_HIOR",
4219 SPR_NOACCESS, SPR_NOACCESS,
4220 &spr_read_generic, &spr_write_generic,
4221 0xFFF00000); /* XXX: This is a hack */
4222 #if !defined(CONFIG_USER_ONLY)
4223 env->excp_prefix = 0xFFF00000;
4224 #endif
4225 #if !defined(CONFIG_USER_ONLY)
4226 env->slb_nr = 32;
4227 #endif
4228 init_excp_970(env);
4229 env->dcache_line_size = 128;
4230 env->icache_line_size = 128;
4231 /* Allocate hardware IRQ controller */
4232 ppc970_irq_init(env);
4233 }
4234
4235 /* PowerPC 620 */
4236 #define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
4237 PPC_64B | PPC_SLBI)
4238 #define POWERPC_MSRM_620 (0x800000000005FF73ULL)
4239 #define POWERPC_MMU_620 (POWERPC_MMU_64B)
4240 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
4241 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_970)
4242 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
4243 #define POWERPC_FLAG_620 (POWERPC_FLAG_NONE)
4244
4245 __attribute__ (( unused ))
4246 static void init_proc_620 (CPUPPCState *env)
4247 {
4248 gen_spr_ne_601(env);
4249 gen_spr_620(env);
4250 /* Time base */
4251 gen_tbl(env);
4252 /* Hardware implementation registers */
4253 /* XXX : not implemented */
4254 spr_register(env, SPR_HID0, "HID0",
4255 SPR_NOACCESS, SPR_NOACCESS,
4256 &spr_read_generic, &spr_write_generic,
4257 0x00000000);
4258 /* Memory management */
4259 gen_low_BATs(env);
4260 gen_high_BATs(env);
4261 init_excp_620(env);
4262 env->dcache_line_size = 64;
4263 env->icache_line_size = 64;
4264 /* XXX: TODO: initialize internal interrupt controller */
4265 }
4266 #endif /* defined (TARGET_PPC64) */
4267
4268 /* Default 32 bits PowerPC target will be 604 */
4269 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
4270 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
4271 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
4272 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
4273 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
4274 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
4275 #define init_proc_PPC32 init_proc_604
4276 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
4277 #define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
4278
4279 /* Default 64 bits PowerPC target will be 970 FX */
4280 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
4281 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
4282 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
4283 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
4284 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
4285 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
4286 #define init_proc_PPC64 init_proc_970FX
4287 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
4288 #define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
4289
4290 /* Default PowerPC target will be PowerPC 32 */
4291 #if defined (TARGET_PPC64) && 0 // XXX: TODO
4292 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
4293 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
4294 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
4295 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
4296 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
4297 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
4298 #define init_proc_DEFAULT init_proc_PPC64
4299 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
4300 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
4301 #else
4302 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
4303 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
4304 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
4305 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
4306 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
4307 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
4308 #define init_proc_DEFAULT init_proc_PPC32
4309 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
4310 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
4311 #endif
4312
4313 /*****************************************************************************/
4314 /* PVR definitions for most known PowerPC */
4315 enum {
4316 /* PowerPC 401 family */
4317 /* Generic PowerPC 401 */
4318 #define CPU_POWERPC_401 CPU_POWERPC_401G2
4319 /* PowerPC 401 cores */
4320 CPU_POWERPC_401A1 = 0x00210000,
4321 CPU_POWERPC_401B2 = 0x00220000,
4322 #if 0
4323 CPU_POWERPC_401B3 = xxx,
4324 #endif
4325 CPU_POWERPC_401C2 = 0x00230000,
4326 CPU_POWERPC_401D2 = 0x00240000,
4327 CPU_POWERPC_401E2 = 0x00250000,
4328 CPU_POWERPC_401F2 = 0x00260000,
4329 CPU_POWERPC_401G2 = 0x00270000,
4330 /* PowerPC 401 microcontrolers */
4331 #if 0
4332 CPU_POWERPC_401GF = xxx,
4333 #endif
4334 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
4335 /* IBM Processor for Network Resources */
4336 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
4337 #if 0
4338 CPU_POWERPC_XIPCHIP = xxx,
4339 #endif
4340 /* PowerPC 403 family */
4341 /* Generic PowerPC 403 */
4342 #define CPU_POWERPC_403 CPU_POWERPC_403GC
4343 /* PowerPC 403 microcontrollers */
4344 CPU_POWERPC_403GA = 0x00200011,
4345 CPU_POWERPC_403GB = 0x00200100,
4346 CPU_POWERPC_403GC = 0x00200200,
4347 CPU_POWERPC_403GCX = 0x00201400,
4348 #if 0
4349 CPU_POWERPC_403GP = xxx,
4350 #endif
4351 /* PowerPC 405 family */
4352 /* Generic PowerPC 405 */
4353 #define CPU_POWERPC_405 CPU_POWERPC_405D4
4354 /* PowerPC 405 cores */
4355 #if 0
4356 CPU_POWERPC_405A3 = xxx,
4357 #endif
4358 #if 0
4359 CPU_POWERPC_405A4 = xxx,
4360 #endif
4361 #if 0
4362 CPU_POWERPC_405B3 = xxx,
4363 #endif
4364 #if 0
4365 CPU_POWERPC_405B4 = xxx,
4366 #endif
4367 #if 0
4368 CPU_POWERPC_405C3 = xxx,
4369 #endif
4370 #if 0
4371 CPU_POWERPC_405C4 = xxx,
4372 #endif
4373 CPU_POWERPC_405D2 = 0x20010000,
4374 #if 0
4375 CPU_POWERPC_405D3 = xxx,
4376 #endif
4377 CPU_POWERPC_405D4 = 0x41810000,
4378 #if 0
4379 CPU_POWERPC_405D5 = xxx,
4380 #endif
4381 #if 0
4382 CPU_POWERPC_405E4 = xxx,
4383 #endif
4384 #if 0
4385 CPU_POWERPC_405F4 = xxx,
4386 #endif
4387 #if 0
4388 CPU_POWERPC_405F5 = xxx,
4389 #endif
4390 #if 0
4391 CPU_POWERPC_405F6 = xxx,
4392 #endif
4393 /* PowerPC 405 microcontrolers */
4394 /* XXX: missing 0x200108a0 */
4395 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
4396 CPU_POWERPC_405CRa = 0x40110041,
4397 CPU_POWERPC_405CRb = 0x401100C5,
4398 CPU_POWERPC_405CRc = 0x40110145,
4399 CPU_POWERPC_405EP = 0x51210950,
4400 #if 0
4401 CPU_POWERPC_405EXr = xxx,
4402 #endif
4403 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
4404 #if 0
4405 CPU_POWERPC_405FX = xxx,
4406 #endif
4407 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
4408 CPU_POWERPC_405GPa = 0x40110000,
4409 CPU_POWERPC_405GPb = 0x40110040,
4410 CPU_POWERPC_405GPc = 0x40110082,
4411 CPU_POWERPC_405GPd = 0x401100C4,
4412 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
4413 CPU_POWERPC_405GPR = 0x50910951,
4414 #if 0
4415 CPU_POWERPC_405H = xxx,
4416 #endif
4417 #if 0
4418 CPU_POWERPC_405L = xxx,
4419 #endif
4420 CPU_POWERPC_405LP = 0x41F10000,
4421 #if 0
4422 CPU_POWERPC_405PM = xxx,
4423 #endif
4424 #if 0
4425 CPU_POWERPC_405PS = xxx,
4426 #endif
4427 #if 0
4428 CPU_POWERPC_405S = xxx,
4429 #endif
4430 /* IBM network processors */
4431 CPU_POWERPC_NPE405H = 0x414100C0,
4432 CPU_POWERPC_NPE405H2 = 0x41410140,
4433 CPU_POWERPC_NPE405L = 0x416100C0,
4434 CPU_POWERPC_NPE4GS3 = 0x40B10000,
4435 #if 0
4436 CPU_POWERPC_NPCxx1 = xxx,
4437 #endif
4438 #if 0
4439 CPU_POWERPC_NPR161 = xxx,
4440 #endif
4441 #if 0
4442 CPU_POWERPC_LC77700 = xxx,
4443 #endif
4444 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
4445 #if 0
4446 CPU_POWERPC_STB01000 = xxx,
4447 #endif
4448 #if 0
4449 CPU_POWERPC_STB01010 = xxx,
4450 #endif
4451 #if 0
4452 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
4453 #endif
4454 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
4455 #if 0
4456 CPU_POWERPC_STB043 = xxx,
4457 #endif
4458 #if 0
4459 CPU_POWERPC_STB045 = xxx,
4460 #endif
4461 CPU_POWERPC_STB04 = 0x41810000,
4462 CPU_POWERPC_STB25 = 0x51510950,
4463 #if 0
4464 CPU_POWERPC_STB130 = xxx,
4465 #endif
4466 /* Xilinx cores */
4467 CPU_POWERPC_X2VP4 = 0x20010820,
4468 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
4469 CPU_POWERPC_X2VP20 = 0x20010860,
4470 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
4471 #if 0
4472 CPU_POWERPC_ZL10310 = xxx,
4473 #endif
4474 #if 0
4475 CPU_POWERPC_ZL10311 = xxx,
4476 #endif
4477 #if 0
4478 CPU_POWERPC_ZL10320 = xxx,
4479 #endif
4480 #if 0
4481 CPU_POWERPC_ZL10321 = xxx,
4482 #endif
4483 /* PowerPC 440 family */
4484 /* Generic PowerPC 440 */
4485 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
4486 /* PowerPC 440 cores */
4487 #if 0
4488 CPU_POWERPC_440A4 = xxx,
4489 #endif
4490 #if 0
4491 CPU_POWERPC_440A5 = xxx,
4492 #endif
4493 #if 0
4494 CPU_POWERPC_440B4 = xxx,
4495 #endif
4496 #if 0
4497 CPU_POWERPC_440F5 = xxx,
4498 #endif
4499 #if 0
4500 CPU_POWERPC_440G5 = xxx,
4501 #endif
4502 #if 0
4503 CPU_POWERPC_440H4 = xxx,
4504 #endif
4505 #if 0
4506 CPU_POWERPC_440H6 = xxx,
4507 #endif
4508 /* PowerPC 440 microcontrolers */
4509 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
4510 CPU_POWERPC_440EPa = 0x42221850,
4511 CPU_POWERPC_440EPb = 0x422218D3,
4512 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
4513 CPU_POWERPC_440GPb = 0x40120440,
4514 CPU_POWERPC_440GPc = 0x40120481,
4515 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
4516 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
4517 CPU_POWERPC_440GRX = 0x200008D0,
4518 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
4519 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
4520 CPU_POWERPC_440GXa = 0x51B21850,
4521 CPU_POWERPC_440GXb = 0x51B21851,
4522 CPU_POWERPC_440GXc = 0x51B21892,
4523 CPU_POWERPC_440GXf = 0x51B21894,
4524 #if 0
4525 CPU_POWERPC_440S = xxx,
4526 #endif
4527 CPU_POWERPC_440SP = 0x53221850,
4528 CPU_POWERPC_440SP2 = 0x53221891,
4529 CPU_POWERPC_440SPE = 0x53421890,
4530 /* PowerPC 460 family */
4531 #if 0
4532 /* Generic PowerPC 464 */
4533 #define CPU_POWERPC_464 CPU_POWERPC_464H90
4534 #endif
4535 /* PowerPC 464 microcontrolers */
4536 #if 0
4537 CPU_POWERPC_464H90 = xxx,
4538 #endif
4539 #if 0
4540 CPU_POWERPC_464H90FP = xxx,
4541 #endif
4542 /* Freescale embedded PowerPC cores */
4543 /* e200 family */
4544 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
4545 #if 0
4546 CPU_POWERPC_e200z0 = xxx,
4547 #endif
4548 #if 0
4549 CPU_POWERPC_e200z3 = xxx,
4550 #endif
4551 CPU_POWERPC_e200z5 = 0x81000000,
4552 CPU_POWERPC_e200z6 = 0x81120000,
4553 /* e300 family */
4554 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
4555 CPU_POWERPC_e300c1 = 0x00830000,
4556 CPU_POWERPC_e300c2 = 0x00840000,
4557 CPU_POWERPC_e300c3 = 0x00850000,
4558 /* e500 family */
4559 #define CPU_POWERPC_e500 CPU_POWERPC_e500_v22
4560 CPU_POWERPC_e500_v11 = 0x80200010,
4561 CPU_POWERPC_e500_v12 = 0x80200020,
4562 CPU_POWERPC_e500_v21 = 0x80210010,
4563 CPU_POWERPC_e500_v22 = 0x80210020,
4564 #if 0
4565 CPU_POWERPC_e500mc = xxx,
4566 #endif
4567 /* e600 family */
4568 CPU_POWERPC_e600 = 0x80040010,
4569 /* PowerPC MPC 5xx cores */
4570 CPU_POWERPC_5xx = 0x00020020,
4571 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
4572 CPU_POWERPC_8xx = 0x00500000,
4573 /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
4574 CPU_POWERPC_82xx_HIP3 = 0x00810101,
4575 CPU_POWERPC_82xx_HIP4 = 0x80811014,
4576 CPU_POWERPC_827x = 0x80822013,
4577 /* PowerPC 6xx cores */
4578 CPU_POWERPC_601 = 0x00010001,
4579 CPU_POWERPC_601a = 0x00010002,
4580 CPU_POWERPC_602 = 0x00050100,
4581 CPU_POWERPC_603 = 0x00030100,
4582 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
4583 CPU_POWERPC_603E_v11 = 0x00060101,
4584 CPU_POWERPC_603E_v12 = 0x00060102,
4585 CPU_POWERPC_603E_v13 = 0x00060103,
4586 CPU_POWERPC_603E_v14 = 0x00060104,
4587 CPU_POWERPC_603E_v22 = 0x00060202,
4588 CPU_POWERPC_603E_v3 = 0x00060300,
4589 CPU_POWERPC_603E_v4 = 0x00060400,
4590 CPU_POWERPC_603E_v41 = 0x00060401,
4591 CPU_POWERPC_603E7t = 0x00071201,
4592 CPU_POWERPC_603E7v = 0x00070100,
4593 CPU_POWERPC_603E7v1 = 0x00070101,
4594 CPU_POWERPC_603E7v2 = 0x00070201,
4595 CPU_POWERPC_603E7 = 0x00070200,
4596 CPU_POWERPC_603P = 0x00070000,
4597 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
4598 CPU_POWERPC_G2 = 0x00810011,
4599 #if 0 // Linux pretends the MSB is zero...
4600 CPU_POWERPC_G2H4 = 0x80811010,
4601 CPU_POWERPC_G2gp = 0x80821010,
4602 CPU_POWERPC_G2ls = 0x90810010,
4603 CPU_POWERPC_G2LE = 0x80820010,
4604 CPU_POWERPC_G2LEgp = 0x80822010,
4605 CPU_POWERPC_G2LEls = 0xA0822010,
4606 #else
4607 CPU_POWERPC_G2H4 = 0x00811010,
4608 CPU_POWERPC_G2gp = 0x00821010,
4609 CPU_POWERPC_G2ls = 0x10810010,
4610 CPU_POWERPC_G2LE = 0x00820010,
4611 CPU_POWERPC_G2LEgp = 0x00822010,
4612 CPU_POWERPC_G2LEls = 0x20822010,
4613 #endif
4614 CPU_POWERPC_604 = 0x00040103,
4615 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
4616 CPU_POWERPC_604E_v10 = 0x00090100, /* Also 2110 & 2120 */
4617 CPU_POWERPC_604E_v22 = 0x00090202,
4618 CPU_POWERPC_604E_v24 = 0x00090204,
4619 CPU_POWERPC_604R = 0x000a0101, /* Also 0x00093102 */
4620 #if 0
4621 CPU_POWERPC_604EV = xxx,
4622 #endif
4623 /* PowerPC 740/750 cores (aka G3) */
4624 /* XXX: missing 0x00084202 */
4625 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
4626 CPU_POWERPC_7x0_v20 = 0x00080200,
4627 CPU_POWERPC_7x0_v21 = 0x00080201,
4628 CPU_POWERPC_7x0_v22 = 0x00080202,
4629 CPU_POWERPC_7x0_v30 = 0x00080300,
4630 CPU_POWERPC_7x0_v31 = 0x00080301,
4631 CPU_POWERPC_740E = 0x00080100,
4632 CPU_POWERPC_7x0P = 0x10080000,
4633 /* XXX: missing 0x00087010 (CL ?) */
4634 CPU_POWERPC_750CL = 0x00087200,
4635 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
4636 CPU_POWERPC_750CX_v21 = 0x00082201,
4637 CPU_POWERPC_750CX_v22 = 0x00082202,
4638 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
4639 CPU_POWERPC_750CXE_v21 = 0x00082211,
4640 CPU_POWERPC_750CXE_v22 = 0x00082212,
4641 CPU_POWERPC_750CXE_v23 = 0x00082213,
4642 CPU_POWERPC_750CXE_v24 = 0x00082214,
4643 CPU_POWERPC_750CXE_v24b = 0x00083214,
4644 CPU_POWERPC_750CXE_v31 = 0x00083211,
4645 CPU_POWERPC_750CXE_v31b = 0x00083311,
4646 CPU_POWERPC_750CXR = 0x00083410,
4647 CPU_POWERPC_750E = 0x00080200,
4648 CPU_POWERPC_750FL = 0x700A0203,
4649 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
4650 CPU_POWERPC_750FX_v10 = 0x70000100,
4651 CPU_POWERPC_750FX_v20 = 0x70000200,
4652 CPU_POWERPC_750FX_v21 = 0x70000201,
4653 CPU_POWERPC_750FX_v22 = 0x70000202,
4654 CPU_POWERPC_750FX_v23 = 0x70000203,
4655 CPU_POWERPC_750GL = 0x70020102,
4656 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
4657 CPU_POWERPC_750GX_v10 = 0x70020100,
4658 CPU_POWERPC_750GX_v11 = 0x70020101,
4659 CPU_POWERPC_750GX_v12 = 0x70020102,
4660 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
4661 CPU_POWERPC_750L_v22 = 0x00088202,
4662 CPU_POWERPC_750L_v30 = 0x00088300,
4663 CPU_POWERPC_750L_v32 = 0x00088302,
4664 /* PowerPC 745/755 cores */
4665 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
4666 CPU_POWERPC_7x5_v10 = 0x00083100,
4667 CPU_POWERPC_7x5_v11 = 0x00083101,
4668 CPU_POWERPC_7x5_v20 = 0x00083200,
4669 CPU_POWERPC_7x5_v21 = 0x00083201,
4670 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
4671 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
4672 CPU_POWERPC_7x5_v24 = 0x00083204,
4673 CPU_POWERPC_7x5_v25 = 0x00083205,
4674 CPU_POWERPC_7x5_v26 = 0x00083206,
4675 CPU_POWERPC_7x5_v27 = 0x00083207,
4676 CPU_POWERPC_7x5_v28 = 0x00083208,
4677 #if 0
4678 CPU_POWERPC_7x5P = xxx,
4679 #endif
4680 /* PowerPC 74xx cores (aka G4) */
4681 /* XXX: missing 0x000C1101 */
4682 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
4683 CPU_POWERPC_7400_v10 = 0x000C0100,
4684 CPU_POWERPC_7400_v11 = 0x000C0101,
4685 CPU_POWERPC_7400_v20 = 0x000C0200,
4686 CPU_POWERPC_7400_v22 = 0x000C0202,
4687 CPU_POWERPC_7400_v26 = 0x000C0206,
4688 CPU_POWERPC_7400_v27 = 0x000C0207,
4689 CPU_POWERPC_7400_v28 = 0x000C0208,
4690 CPU_POWERPC_7400_v29 = 0x000C0209,
4691 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
4692 CPU_POWERPC_7410_v10 = 0x800C1100,
4693 CPU_POWERPC_7410_v11 = 0x800C1101,
4694 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
4695 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
4696 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
4697 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
4698 CPU_POWERPC_7448_v10 = 0x80040100,
4699 CPU_POWERPC_7448_v11 = 0x80040101,
4700 CPU_POWERPC_7448_v20 = 0x80040200,
4701 CPU_POWERPC_7448_v21 = 0x80040201,
4702 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
4703 CPU_POWERPC_7450_v10 = 0x80000100,
4704 CPU_POWERPC_7450_v11 = 0x80000101,
4705 CPU_POWERPC_7450_v12 = 0x80000102,
4706 CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
4707 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
4708 CPU_POWERPC_74x1 = 0x80000203,
4709 CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
4710 /* XXX: missing 0x80010200 */
4711 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
4712 CPU_POWERPC_74x5_v10 = 0x80010100,
4713 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
4714 CPU_POWERPC_74x5_v32 = 0x80010302,
4715 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
4716 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
4717 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
4718 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
4719 CPU_POWERPC_74x7_v11 = 0x80030101, /* aka B: 1.1 */
4720 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
4721 /* 64 bits PowerPC */
4722 #if defined(TARGET_PPC64)
4723 CPU_POWERPC_620 = 0x00140000,
4724 CPU_POWERPC_630 = 0x00400000,
4725 CPU_POWERPC_631 = 0x00410104,
4726 CPU_POWERPC_POWER4 = 0x00350000,
4727 CPU_POWERPC_POWER4P = 0x00380000,
4728 CPU_POWERPC_POWER5 = 0x003A0203,
4729 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
4730 CPU_POWERPC_POWER5P = 0x003B0000,
4731 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
4732 CPU_POWERPC_POWER6 = 0x003E0000,
4733 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 running POWER5 mode */
4734 CPU_POWERPC_POWER6A = 0x0F000002,
4735 CPU_POWERPC_970 = 0x00390202,
4736 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
4737 CPU_POWERPC_970FX_v10 = 0x00391100,
4738 CPU_POWERPC_970FX_v20 = 0x003C0200,
4739 CPU_POWERPC_970FX_v21 = 0x003C0201,
4740 CPU_POWERPC_970FX_v30 = 0x003C0300,
4741 CPU_POWERPC_970FX_v31 = 0x003C0301,
4742 CPU_POWERPC_970GX = 0x00450000,
4743 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
4744 CPU_POWERPC_970MP_v10 = 0x00440100,
4745 CPU_POWERPC_970MP_v11 = 0x00440101,
4746 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
4747 CPU_POWERPC_CELL_v10 = 0x00700100,
4748 CPU_POWERPC_CELL_v20 = 0x00700400,
4749 CPU_POWERPC_CELL_v30 = 0x00700500,
4750 CPU_POWERPC_CELL_v31 = 0x00700501,
4751 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
4752 CPU_POWERPC_RS64 = 0x00330000,
4753 CPU_POWERPC_RS64II = 0x00340000,
4754 CPU_POWERPC_RS64III = 0x00360000,
4755 CPU_POWERPC_RS64IV = 0x00370000,
4756 #endif /* defined(TARGET_PPC64) */
4757 /* Original POWER */
4758 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
4759 * POWER2 (RIOS2) & RSC2 (P2SC) here
4760 */
4761 #if 0
4762 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
4763 #endif
4764 #if 0
4765 CPU_POWER2 = xxx, /* 0x40000 ? */
4766 #endif
4767 /* PA Semi core */
4768 CPU_POWERPC_PA6T = 0x00900000,
4769 };
4770
4771 /* System version register (used on MPC 8xxx) */
4772 enum {
4773 PPC_SVR_8540 = 0x80300000,
4774 PPC_SVR_8541E = 0x807A0010,
4775 PPC_SVR_8543v10 = 0x80320010,
4776 PPC_SVR_8543v11 = 0x80320011,
4777 PPC_SVR_8543v20 = 0x80320020,
4778 PPC_SVR_8543Ev10 = 0x803A0010,
4779 PPC_SVR_8543Ev11 = 0x803A0011,
4780 PPC_SVR_8543Ev20 = 0x803A0020,
4781 PPC_SVR_8545 = 0x80310220,
4782 PPC_SVR_8545E = 0x80390220,
4783 PPC_SVR_8547E = 0x80390120,
4784 PPC_SCR_8548v10 = 0x80310010,
4785 PPC_SCR_8548v11 = 0x80310011,
4786 PPC_SCR_8548v20 = 0x80310020,
4787 PPC_SVR_8548Ev10 = 0x80390010,
4788 PPC_SVR_8548Ev11 = 0x80390011,
4789 PPC_SVR_8548Ev20 = 0x80390020,
4790 PPC_SVR_8555E = 0x80790010,
4791 PPC_SVR_8560v10 = 0x80700010,
4792 PPC_SVR_8560v20 = 0x80700020,
4793 };
4794
4795 /*****************************************************************************/
4796 /* PowerPC CPU definitions */
4797 #define POWERPC_DEF(_name, _pvr, _pvr_mask, _type) \
4798 { \
4799 .name = _name, \
4800 .pvr = _pvr, \
4801 .pvr_mask = _pvr_mask, \
4802 .insns_flags = glue(POWERPC_INSNS_,_type), \
4803 .msr_mask = glue(POWERPC_MSRM_,_type), \
4804 .mmu_model = glue(POWERPC_MMU_,_type), \
4805 .excp_model = glue(POWERPC_EXCP_,_type), \
4806 .bus_model = glue(POWERPC_INPUT_,_type), \
4807 .bfd_mach = glue(POWERPC_BFDM_,_type), \
4808 .flags = glue(POWERPC_FLAG_,_type), \
4809 .init_proc = &glue(init_proc_,_type), \
4810 }
4811
4812 static ppc_def_t ppc_defs[] = {
4813 /* Embedded PowerPC */
4814 /* PowerPC 401 family */
4815 /* Generic PowerPC 401 */
4816 POWERPC_DEF("401", CPU_POWERPC_401, 0xFFFF0000, 401),
4817 /* PowerPC 401 cores */
4818 /* PowerPC 401A1 */
4819 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 0xFFFFFFFF, 401),
4820 /* PowerPC 401B2 */
4821 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 0xFFFFFFFF, 401x2),
4822 #if defined (TODO)
4823 /* PowerPC 401B3 */
4824 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 0xFFFFFFFF, 401x3),
4825 #endif
4826 /* PowerPC 401C2 */
4827 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 0xFFFFFFFF, 401x2),
4828 /* PowerPC 401D2 */
4829 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 0xFFFFFFFF, 401x2),
4830 /* PowerPC 401E2 */
4831 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 0xFFFFFFFF, 401x2),
4832 /* PowerPC 401F2 */
4833 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 0xFFFFFFFF, 401x2),
4834 /* PowerPC 401G2 */
4835 /* XXX: to be checked */
4836 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 0xFFFFFFFF, 401x2),
4837 /* PowerPC 401 microcontrolers */
4838 #if defined (TODO)
4839 /* PowerPC 401GF */
4840 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 0xFFFFFFFF, 401),
4841 #endif
4842 /* IOP480 (401 microcontroler) */
4843 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, 0xFFFFFFFF, IOP480),
4844 /* IBM Processor for Network Resources */
4845 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 0xFFFFFFFF, 401),
4846 #if defined (TODO)
4847 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 0xFFFFFFFF, 401),
4848 #endif
4849 /* PowerPC 403 family */
4850 /* Generic PowerPC 403 */
4851 POWERPC_DEF("403", CPU_POWERPC_403, 0xFFFF0000, 403),
4852 /* PowerPC 403 microcontrolers */
4853 /* PowerPC 403 GA */
4854 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 0xFFFFFFFF, 403),
4855 /* PowerPC 403 GB */
4856 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 0xFFFFFFFF, 403),
4857 /* PowerPC 403 GC */
4858 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 0xFFFFFFFF, 403),
4859 /* PowerPC 403 GCX */
4860 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 0xFFFFFFFF, 403GCX),
4861 #if defined (TODO)
4862 /* PowerPC 403 GP */
4863 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 0xFFFFFFFF, 403),
4864 #endif
4865 /* PowerPC 405 family */
4866 /* Generic PowerPC 405 */
4867 POWERPC_DEF("405", CPU_POWERPC_405, 0xFFFF0000, 405),
4868 /* PowerPC 405 cores */
4869 #if defined (TODO)
4870 /* PowerPC 405 A3 */
4871 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 0xFFFFFFFF, 405),
4872 #endif
4873 #if defined (TODO)
4874 /* PowerPC 405 A4 */
4875 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 0xFFFFFFFF, 405),
4876 #endif
4877 #if defined (TODO)
4878 /* PowerPC 405 B3 */
4879 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 0xFFFFFFFF, 405),
4880 #endif
4881 #if defined (TODO)
4882 /* PowerPC 405 B4 */
4883 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 0xFFFFFFFF, 405),
4884 #endif
4885 #if defined (TODO)
4886 /* PowerPC 405 C3 */
4887 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 0xFFFFFFFF, 405),
4888 #endif
4889 #if defined (TODO)
4890 /* PowerPC 405 C4 */
4891 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 0xFFFFFFFF, 405),
4892 #endif
4893 /* PowerPC 405 D2 */
4894 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 0xFFFFFFFF, 405),
4895 #if defined (TODO)
4896 /* PowerPC 405 D3 */
4897 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 0xFFFFFFFF, 405),
4898 #endif
4899 /* PowerPC 405 D4 */
4900 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 0xFFFFFFFF, 405),
4901 #if defined (TODO)
4902 /* PowerPC 405 D5 */
4903 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 0xFFFFFFFF, 405),
4904 #endif
4905 #if defined (TODO)
4906 /* PowerPC 405 E4 */
4907 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 0xFFFFFFFF, 405),
4908 #endif
4909 #if defined (TODO)
4910 /* PowerPC 405 F4 */
4911 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 0xFFFFFFFF, 405),
4912 #endif
4913 #if defined (TODO)
4914 /* PowerPC 405 F5 */
4915 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 0xFFFFFFFF, 405),
4916 #endif
4917 #if defined (TODO)
4918 /* PowerPC 405 F6 */
4919 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 0xFFFFFFFF, 405),
4920 #endif
4921 /* PowerPC 405 microcontrolers */
4922 /* PowerPC 405 CR */
4923 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 0xFFFFFFFF, 405),
4924 /* PowerPC 405 CRa */
4925 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 0xFFFFFFFF, 405),
4926 /* PowerPC 405 CRb */
4927 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 0xFFFFFFFF, 405),
4928 /* PowerPC 405 CRc */
4929 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 0xFFFFFFFF, 405),
4930 /* PowerPC 405 EP */
4931 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 0xFFFFFFFF, 405),
4932 #if defined(TODO)
4933 /* PowerPC 405 EXr */
4934 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 0xFFFFFFFF, 405),
4935 #endif
4936 /* PowerPC 405 EZ */
4937 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 0xFFFFFFFF, 405),
4938 #if defined(TODO)
4939 /* PowerPC 405 FX */
4940 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 0xFFFFFFFF, 405),
4941 #endif
4942 /* PowerPC 405 GP */
4943 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 0xFFFFFFFF, 405),
4944 /* PowerPC 405 GPa */
4945 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 0xFFFFFFFF, 405),
4946 /* PowerPC 405 GPb */
4947 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 0xFFFFFFFF, 405),
4948 /* PowerPC 405 GPc */
4949 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 0xFFFFFFFF, 405),
4950 /* PowerPC 405 GPd */
4951 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 0xFFFFFFFF, 405),
4952 /* PowerPC 405 GPe */
4953 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 0xFFFFFFFF, 405),
4954 /* PowerPC 405 GPR */
4955 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 0xFFFFFFFF, 405),
4956 #if defined(TODO)
4957 /* PowerPC 405 H */
4958 POWERPC_DEF("405H", CPU_POWERPC_405H, 0xFFFFFFFF, 405),
4959 #endif
4960 #if defined(TODO)
4961 /* PowerPC 405 L */
4962 POWERPC_DEF("405L", CPU_POWERPC_405L, 0xFFFFFFFF, 405),
4963 #endif
4964 /* PowerPC 405 LP */
4965 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 0xFFFFFFFF, 405),
4966 #if defined(TODO)
4967 /* PowerPC 405 PM */
4968 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 0xFFFFFFFF, 405),
4969 #endif
4970 #if defined(TODO)
4971 /* PowerPC 405 PS */
4972 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 0xFFFFFFFF, 405),
4973 #endif
4974 #if defined(TODO)
4975 /* PowerPC 405 S */
4976 POWERPC_DEF("405S", CPU_POWERPC_405S, 0xFFFFFFFF, 405),
4977 #endif
4978 /* Npe405 H */
4979 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 0xFFFFFFFF, 405),
4980 /* Npe405 H2 */
4981 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 0xFFFFFFFF, 405),
4982 /* Npe405 L */
4983 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 0xFFFFFFFF, 405),
4984 /* Npe4GS3 */
4985 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 0xFFFFFFFF, 405),
4986 #if defined (TODO)
4987 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 0xFFFFFFFF, 405),
4988 #endif
4989 #if defined (TODO)
4990 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 0xFFFFFFFF, 405),
4991 #endif
4992 #if defined (TODO)
4993 /* PowerPC LC77700 (Sanyo) */
4994 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 0xFFFFFFFF, 405),
4995 #endif
4996 /* PowerPC 401/403/405 based set-top-box microcontrolers */
4997 #if defined (TODO)
4998 /* STB010000 */
4999 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 0xFFFFFFFF, 401x2),
5000 #endif
5001 #if defined (TODO)
5002 /* STB01010 */
5003 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 0xFFFFFFFF, 401x2),
5004 #endif
5005 #if defined (TODO)
5006 /* STB0210 */
5007 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 0xFFFFFFFF, 401x3),
5008 #endif
5009 /* STB03xx */
5010 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 0xFFFFFFFF, 405),
5011 #if defined (TODO)
5012 /* STB043x */
5013 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 0xFFFFFFFF, 405),
5014 #endif
5015 #if defined (TODO)
5016 /* STB045x */
5017 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 0xFFFFFFFF, 405),
5018 #endif
5019 /* STB04xx */
5020 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 0xFFFF0000, 405),
5021 /* STB25xx */
5022 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 0xFFFFFFFF, 405),
5023 #if defined (TODO)
5024 /* STB130 */
5025 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 0xFFFFFFFF, 405),
5026 #endif
5027 /* Xilinx PowerPC 405 cores */
5028 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 0xFFFFFFFF, 405),
5029 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 0xFFFFFFFF, 405),
5030 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 0xFFFFFFFF, 405),
5031 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 0xFFFFFFFF, 405),
5032 #if defined (TODO)
5033 /* Zarlink ZL10310 */
5034 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 0xFFFFFFFF, 405),
5035 #endif
5036 #if defined (TODO)
5037 /* Zarlink ZL10311 */
5038 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 0xFFFFFFFF, 405),
5039 #endif
5040 #if defined (TODO)
5041 /* Zarlink ZL10320 */
5042 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 0xFFFFFFFF, 405),
5043 #endif
5044 #if defined (TODO)
5045 /* Zarlink ZL10321 */
5046 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 0xFFFFFFFF, 405),
5047 #endif
5048 /* PowerPC 440 family */
5049 /* Generic PowerPC 440 */
5050 POWERPC_DEF("440", CPU_POWERPC_440, 0xFFFFFFFF, 440GP),
5051 /* PowerPC 440 cores */
5052 #if defined (TODO)
5053 /* PowerPC 440 A4 */
5054 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 0xFFFFFFFF, 440x4),
5055 #endif
5056 #if defined (TODO)
5057 /* PowerPC 440 A5 */
5058 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 0xFFFFFFFF, 440x5),
5059 #endif
5060 #if defined (TODO)
5061 /* PowerPC 440 B4 */
5062 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 0xFFFFFFFF, 440x4),
5063 #endif
5064 #if defined (TODO)
5065 /* PowerPC 440 G4 */
5066 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 0xFFFFFFFF, 440x4),
5067 #endif
5068 #if defined (TODO)
5069 /* PowerPC 440 F5 */
5070 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 0xFFFFFFFF, 440x5),
5071 #endif
5072 #if defined (TODO)
5073 /* PowerPC 440 G5 */
5074 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 0xFFFFFFFF, 440x5),
5075 #endif
5076 #if defined (TODO)
5077 /* PowerPC 440H4 */
5078 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 0xFFFFFFFF, 440x4),
5079 #endif
5080 #if defined (TODO)
5081 /* PowerPC 440H6 */
5082 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 0xFFFFFFFF, 440Gx5),
5083 #endif
5084 /* PowerPC 440 microcontrolers */
5085 /* PowerPC 440 EP */
5086 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 0xFFFFFFFF, 440EP),
5087 /* PowerPC 440 EPa */
5088 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 0xFFFFFFFF, 440EP),
5089 /* PowerPC 440 EPb */
5090 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 0xFFFFFFFF, 440EP),
5091 /* PowerPC 440 EPX */
5092 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 0xFFFFFFFF, 440EP),
5093 /* PowerPC 440 GP */
5094 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 0xFFFFFFFF, 440GP),
5095 /* PowerPC 440 GPb */
5096 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 0xFFFFFFFF, 440GP),
5097 /* PowerPC 440 GPc */
5098 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 0xFFFFFFFF, 440GP),
5099 /* PowerPC 440 GR */
5100 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 0xFFFFFFFF, 440x5),
5101 /* PowerPC 440 GRa */
5102 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 0xFFFFFFFF, 440x5),
5103 /* PowerPC 440 GRX */
5104 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 0xFFFFFFFF, 440x5),
5105 /* PowerPC 440 GX */
5106 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 0xFFFFFFFF, 440EP),
5107 /* PowerPC 440 GXa */
5108 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 0xFFFFFFFF, 440EP),
5109 /* PowerPC 440 GXb */
5110 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 0xFFFFFFFF, 440EP),
5111 /* PowerPC 440 GXc */
5112 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 0xFFFFFFFF, 440EP),
5113 /* PowerPC 440 GXf */
5114 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 0xFFFFFFFF, 440EP),
5115 #if defined(TODO)
5116 /* PowerPC 440 S */
5117 POWERPC_DEF("440S", CPU_POWERPC_440S, 0xFFFFFFFF, 440),
5118 #endif
5119 /* PowerPC 440 SP */
5120 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 0xFFFFFFFF, 440EP),
5121 /* PowerPC 440 SP2 */
5122 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 0xFFFFFFFF, 440EP),
5123 /* PowerPC 440 SPE */
5124 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 0xFFFFFFFF, 440EP),
5125 /* PowerPC 460 family */
5126 #if defined (TODO)
5127 /* Generic PowerPC 464 */
5128 POWERPC_DEF("464", CPU_POWERPC_464, 0xFFFFFFFF, 460),
5129 #endif
5130 /* PowerPC 464 microcontrolers */
5131 #if defined (TODO)
5132 /* PowerPC 464H90 */
5133 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 0xFFFFFFFF, 460),
5134 #endif
5135 #if defined (TODO)
5136 /* PowerPC 464H90F */
5137 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 0xFFFFFFFF, 460F),
5138 #endif
5139 /* Freescale embedded PowerPC cores */
5140 /* e200 family */
5141 #if defined (TODO)
5142 /* Generic PowerPC e200 core */
5143 POWERPC_DEF("e200", CPU_POWERPC_e200, 0xFFFFFFFF, e200),
5144 #endif
5145 #if defined (TODO)
5146 /* PowerPC e200z5 core */
5147 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, 0xFFFFFFFF, e200),
5148 #endif
5149 #if defined (TODO)
5150 /* PowerPC e200z6 core */
5151 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, 0xFFFFFFFF, e200),
5152 #endif
5153 /* e300 family */
5154 #if defined (TODO)
5155 /* Generic PowerPC e300 core */
5156 POWERPC_DEF("e300", CPU_POWERPC_e300, 0xFFFFFFFF, e300),
5157 #endif
5158 #if defined (TODO)
5159 /* PowerPC e300c1 core */
5160 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, 0xFFFFFFFF, e300),
5161 #endif
5162 #if defined (TODO)
5163 /* PowerPC e300c2 core */
5164 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, 0xFFFFFFFF, e300),
5165 #endif
5166 #if defined (TODO)
5167 /* PowerPC e300c3 core */
5168 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, 0xFFFFFFFF, e300),
5169 #endif
5170 /* e500 family */
5171 #if defined (TODO)
5172 /* PowerPC e500 core */
5173 POWERPC_DEF("e500", CPU_POWERPC_e500, 0xFFFFFFFF, e500),
5174 #endif
5175 #if defined (TODO)
5176 /* PowerPC e500 v1.1 core */
5177 POWERPC_DEF("e500v1.1", CPU_POWERPC_e500_v11, 0xFFFFFFFF, e500),
5178 #endif
5179 #if defined (TODO)
5180 /* PowerPC e500 v1.2 core */
5181 POWERPC_DEF("e500v1.2", CPU_POWERPC_e500_v12, 0xFFFFFFFF, e500),
5182 #endif
5183 #if defined (TODO)
5184 /* PowerPC e500 v2.1 core */
5185 POWERPC_DEF("e500v2.1", CPU_POWERPC_e500_v21, 0xFFFFFFFF, e500),
5186 #endif
5187 #if defined (TODO)
5188 /* PowerPC e500 v2.2 core */
5189 POWERPC_DEF("e500v2.2", CPU_POWERPC_e500_v22, 0xFFFFFFFF, e500),
5190 #endif
5191 /* e600 family */
5192 #if defined (TODO)
5193 /* PowerPC e600 core */
5194 POWERPC_DEF("e600", CPU_POWERPC_e600, 0xFFFFFFFF, e600),
5195 #endif
5196 /* PowerPC MPC 5xx cores */
5197 #if defined (TODO)
5198 /* PowerPC MPC 5xx */
5199 POWERPC_DEF("mpc5xx", CPU_POWERPC_5xx, 0xFFFFFFFF, 5xx),
5200 #endif
5201 /* PowerPC MPC 8xx cores */
5202 #if defined (TODO)
5203 /* PowerPC MPC 8xx */
5204 POWERPC_DEF("mpc8xx", CPU_POWERPC_8xx, 0xFFFFFFFF, 8xx),
5205 #endif
5206 /* PowerPC MPC 8xxx cores */
5207 #if defined (TODO)
5208 /* PowerPC MPC 82xx HIP3 */
5209 POWERPC_DEF("mpc82xxhip3", CPU_POWERPC_82xx_HIP3, 0xFFFFFFFF, 82xx),
5210 #endif
5211 #if defined (TODO)
5212 /* PowerPC MPC 82xx HIP4 */
5213 POWERPC_DEF("mpc82xxhip4", CPU_POWERPC_82xx_HIP4, 0xFFFFFFFF, 82xx),
5214 #endif
5215 #if defined (TODO)
5216 /* PowerPC MPC 827x */
5217 POWERPC_DEF("mpc827x", CPU_POWERPC_827x, 0xFFFFFFFF, 827x),
5218 #endif
5219
5220 /* 32 bits "classic" PowerPC */
5221 /* PowerPC 6xx family */
5222 /* PowerPC 601 */
5223 POWERPC_DEF("601", CPU_POWERPC_601, 0xFFFFFFFF, 601),
5224 /* PowerPC 601v2 */
5225 POWERPC_DEF("601a", CPU_POWERPC_601a, 0xFFFFFFFF, 601),
5226 /* PowerPC 602 */
5227 POWERPC_DEF("602", CPU_POWERPC_602, 0xFFFFFFFF, 602),
5228 /* PowerPC 603 */
5229 POWERPC_DEF("603", CPU_POWERPC_603, 0xFFFFFFFF, 603),
5230 /* Code name for PowerPC 603 */
5231 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 0xFFFFFFFF, 603),
5232 /* PowerPC 603e */
5233 POWERPC_DEF("603e", CPU_POWERPC_603E, 0xFFFFFFFF, 603E),
5234 /* Code name for PowerPC 603e */
5235 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 0xFFFFFFFF, 603E),
5236 /* PowerPC 603e v1.1 */
5237 POWERPC_DEF("603e1.1", CPU_POWERPC_603E_v11, 0xFFFFFFFF, 603E),
5238 /* PowerPC 603e v1.2 */
5239 POWERPC_DEF("603e1.2", CPU_POWERPC_603E_v12, 0xFFFFFFFF, 603E),
5240 /* PowerPC 603e v1.3 */
5241 POWERPC_DEF("603e1.3", CPU_POWERPC_603E_v13, 0xFFFFFFFF, 603E),
5242 /* PowerPC 603e v1.4 */
5243 POWERPC_DEF("603e1.4", CPU_POWERPC_603E_v14, 0xFFFFFFFF, 603E),
5244 /* PowerPC 603e v2.2 */
5245 POWERPC_DEF("603e2.2", CPU_POWERPC_603E_v22, 0xFFFFFFFF, 603E),
5246 /* PowerPC 603e v3 */
5247 POWERPC_DEF("603e3", CPU_POWERPC_603E_v3, 0xFFFFFFFF, 603E),
5248 /* PowerPC 603e v4 */
5249 POWERPC_DEF("603e4", CPU_POWERPC_603E_v4, 0xFFFFFFFF, 603E),
5250 /* PowerPC 603e v4.1 */
5251 POWERPC_DEF("603e4.1", CPU_POWERPC_603E_v41, 0xFFFFFFFF, 603E),
5252 /* PowerPC 603e */
5253 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 0xFFFFFFFF, 603E),
5254 /* PowerPC 603e7t */
5255 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 0xFFFFFFFF, 603E),
5256 /* PowerPC 603e7v */
5257 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E),
5258 /* Code name for PowerPC 603ev */
5259 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E),
5260 /* PowerPC 603e7v1 */
5261 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 0xFFFFFFFF, 603E),
5262 /* PowerPC 603e7v2 */
5263 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 0xFFFFFFFF, 603E),
5264 /* PowerPC 603p */
5265 /* to be checked */
5266 POWERPC_DEF("603p", CPU_POWERPC_603P, 0xFFFFFFFF, 603),
5267 /* PowerPC 603r */
5268 POWERPC_DEF("603r", CPU_POWERPC_603R, 0xFFFFFFFF, 603E),
5269 /* Code name for PowerPC 603r */
5270 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 0xFFFFFFFF, 603E),
5271 /* PowerPC G2 core */
5272 POWERPC_DEF("G2", CPU_POWERPC_G2, 0xFFFFFFFF, G2),
5273 /* PowerPC G2 H4 */
5274 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, 0xFFFFFFFF, G2),
5275 /* PowerPC G2 GP */
5276 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, 0xFFFFFFFF, G2),
5277 /* PowerPC G2 LS */
5278 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, 0xFFFFFFFF, G2),
5279 /* PowerPC G2LE */
5280 /* Same as G2, with little-endian mode support */
5281 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, 0xFFFFFFFF, G2LE),
5282 /* PowerPC G2LE GP */
5283 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, 0xFFFFFFFF, G2LE),
5284 /* PowerPC G2LE LS */
5285 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, 0xFFFFFFFF, G2LE),
5286 /* PowerPC 604 */
5287 POWERPC_DEF("604", CPU_POWERPC_604, 0xFFFFFFFF, 604),
5288 /* PowerPC 604e */
5289 POWERPC_DEF("604e", CPU_POWERPC_604E, 0xFFFFFFFF, 604),
5290 /* PowerPC 604e v1.0 */
5291 POWERPC_DEF("604e1.0", CPU_POWERPC_604E_v10, 0xFFFFFFFF, 604),
5292 /* PowerPC 604e v2.2 */
5293 POWERPC_DEF("604e2.2", CPU_POWERPC_604E_v22, 0xFFFFFFFF, 604),
5294 /* PowerPC 604e v2.4 */
5295 POWERPC_DEF("604e2.4", CPU_POWERPC_604E_v24, 0xFFFFFFFF, 604),
5296 /* PowerPC 604r */
5297 POWERPC_DEF("604r", CPU_POWERPC_604R, 0xFFFFFFFF, 604),
5298 #if defined(TODO)
5299 /* PowerPC 604ev */
5300 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 0xFFFFFFFF, 604),
5301 #endif
5302 /* PowerPC 7xx family */
5303 /* Generic PowerPC 740 (G3) */
5304 POWERPC_DEF("740", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5305 /* Generic PowerPC 750 (G3) */
5306 POWERPC_DEF("750", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5307 /* Code name for generic PowerPC 740/750 (G3) */
5308 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5309 /* PowerPC 740/750 is also known as G3 */
5310 POWERPC_DEF("G3", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5311 /* PowerPC 740 v2.0 (G3) */
5312 POWERPC_DEF("740v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0),
5313 /* PowerPC 750 v2.0 (G3) */
5314 POWERPC_DEF("750v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0),
5315 /* PowerPC 740 v2.1 (G3) */
5316 POWERPC_DEF("740v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0),
5317 /* PowerPC 750 v2.1 (G3) */
5318 POWERPC_DEF("750v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0),
5319 /* PowerPC 740 v2.2 (G3) */
5320 POWERPC_DEF("740v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0),
5321 /* PowerPC 750 v2.2 (G3) */
5322 POWERPC_DEF("750v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0),
5323 /* PowerPC 740 v3.0 (G3) */
5324 POWERPC_DEF("740v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0),
5325 /* PowerPC 750 v3.0 (G3) */
5326 POWERPC_DEF("750v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0),
5327 /* PowerPC 740 v3.1 (G3) */
5328 POWERPC_DEF("740v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0),
5329 /* PowerPC 750 v3.1 (G3) */
5330 POWERPC_DEF("750v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0),
5331 /* PowerPC 740E (G3) */
5332 POWERPC_DEF("740e", CPU_POWERPC_740E, 0xFFFFFFFF, 7x0),
5333 /* PowerPC 740P (G3) */
5334 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5335 /* PowerPC 750P (G3) */
5336 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5337 /* Code name for PowerPC 740P/750P (G3) */
5338 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5339 /* PowerPC 750CL (G3 embedded) */
5340 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 0xFFFFFFFF, 7x0),
5341 /* PowerPC 750CX (G3 embedded) */
5342 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 0xFFFFFFFF, 7x0),
5343 /* PowerPC 750CX v2.1 (G3 embedded) */
5344 POWERPC_DEF("750cx2.1", CPU_POWERPC_750CX_v21, 0xFFFFFFFF, 7x0),
5345 /* PowerPC 750CX v2.2 (G3 embedded) */
5346 POWERPC_DEF("750cx2.2", CPU_POWERPC_750CX_v22, 0xFFFFFFFF, 7x0),
5347 /* PowerPC 750CXe (G3 embedded) */
5348 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 0xFFFFFFFF, 7x0),
5349 /* PowerPC 750CXe v2.1 (G3 embedded) */
5350 POWERPC_DEF("750cxe21", CPU_POWERPC_750CXE_v21, 0xFFFFFFFF, 7x0),
5351 /* PowerPC 750CXe v2.2 (G3 embedded) */
5352 POWERPC_DEF("750cxe22", CPU_POWERPC_750CXE_v22, 0xFFFFFFFF, 7x0),
5353 /* PowerPC 750CXe v2.3 (G3 embedded) */
5354 POWERPC_DEF("750cxe23", CPU_POWERPC_750CXE_v23, 0xFFFFFFFF, 7x0),
5355 /* PowerPC 750CXe v2.4 (G3 embedded) */
5356 POWERPC_DEF("750cxe24", CPU_POWERPC_750CXE_v24, 0xFFFFFFFF, 7x0),
5357 /* PowerPC 750CXe v2.4b (G3 embedded) */
5358 POWERPC_DEF("750cxe24b", CPU_POWERPC_750CXE_v24b, 0xFFFFFFFF, 7x0),
5359 /* PowerPC 750CXe v3.1 (G3 embedded) */
5360 POWERPC_DEF("750cxe31", CPU_POWERPC_750CXE_v31, 0xFFFFFFFF, 7x0),
5361 /* PowerPC 750CXe v3.1b (G3 embedded) */
5362 POWERPC_DEF("750cxe3.1b", CPU_POWERPC_750CXE_v31b, 0xFFFFFFFF, 7x0),
5363 /* PowerPC 750CXr (G3 embedded) */
5364 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 0xFFFFFFFF, 7x0),
5365 /* PowerPC 750E (G3) */
5366 POWERPC_DEF("750e", CPU_POWERPC_750E, 0xFFFFFFFF, 7x0),
5367 /* PowerPC 750FL (G3 embedded) */
5368 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 0xFFFFFFFF, 750fx),
5369 /* PowerPC 750FX (G3 embedded) */
5370 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 0xFFFFFFFF, 750fx),
5371 /* PowerPC 750FX v1.0 (G3 embedded) */
5372 POWERPC_DEF("750fx1.0", CPU_POWERPC_750FX_v10, 0xFFFFFFFF, 750fx),
5373 /* PowerPC 750FX v2.0 (G3 embedded) */
5374 POWERPC_DEF("750fx2.0", CPU_POWERPC_750FX_v20, 0xFFFFFFFF, 750fx),
5375 /* PowerPC 750FX v2.1 (G3 embedded) */
5376 POWERPC_DEF("750fx2.1", CPU_POWERPC_750FX_v21, 0xFFFFFFFF, 750fx),
5377 /* PowerPC 750FX v2.2 (G3 embedded) */
5378 POWERPC_DEF("750fx2.2", CPU_POWERPC_750FX_v22, 0xFFFFFFFF, 750fx),
5379 /* PowerPC 750FX v2.3 (G3 embedded) */
5380 POWERPC_DEF("750fx2.3", CPU_POWERPC_750FX_v23, 0xFFFFFFFF, 750fx),
5381 /* PowerPC 750GL (G3 embedded) */
5382 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 0xFFFFFFFF, 750fx),
5383 /* PowerPC 750GX (G3 embedded) */
5384 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 0xFFFFFFFF, 750fx),
5385 /* PowerPC 750GX v1.0 (G3 embedded) */
5386 POWERPC_DEF("750gx1.0", CPU_POWERPC_750GX_v10, 0xFFFFFFFF, 750fx),
5387 /* PowerPC 750GX v1.1 (G3 embedded) */
5388 POWERPC_DEF("750gx1.1", CPU_POWERPC_750GX_v11, 0xFFFFFFFF, 750fx),
5389 /* PowerPC 750GX v1.2 (G3 embedded) */
5390 POWERPC_DEF("750gx1.2", CPU_POWERPC_750GX_v12, 0xFFFFFFFF, 750fx),
5391 /* PowerPC 750L (G3 embedded) */
5392 POWERPC_DEF("750l", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0),
5393 /* Code name for PowerPC 750L (G3 embedded) */
5394 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0),
5395 /* PowerPC 750L v2.2 (G3 embedded) */
5396 POWERPC_DEF("750l2.2", CPU_POWERPC_750L_v22, 0xFFFFFFFF, 7x0),
5397 /* PowerPC 750L v3.0 (G3 embedded) */
5398 POWERPC_DEF("750l3.0", CPU_POWERPC_750L_v30, 0xFFFFFFFF, 7x0),
5399 /* PowerPC 750L v3.2 (G3 embedded) */
5400 POWERPC_DEF("750l3.2", CPU_POWERPC_750L_v32, 0xFFFFFFFF, 7x0),
5401 /* Generic PowerPC 745 */
5402 POWERPC_DEF("745", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5403 /* Generic PowerPC 755 */
5404 POWERPC_DEF("755", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5405 /* Code name for PowerPC 745/755 */
5406 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5407 /* PowerPC 745 v1.0 */
5408 POWERPC_DEF("745v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5),
5409 /* PowerPC 755 v1.0 */
5410 POWERPC_DEF("755v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5),
5411 /* PowerPC 745 v1.1 */
5412 POWERPC_DEF("745v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5),
5413 /* PowerPC 755 v1.1 */
5414 POWERPC_DEF("755v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5),
5415 /* PowerPC 745 v2.0 */
5416 POWERPC_DEF("745v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5),
5417 /* PowerPC 755 v2.0 */
5418 POWERPC_DEF("755v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5),
5419 /* PowerPC 745 v2.1 */
5420 POWERPC_DEF("745v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5),
5421 /* PowerPC 755 v2.1 */
5422 POWERPC_DEF("755v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5),
5423 /* PowerPC 745 v2.2 */
5424 POWERPC_DEF("745v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5),
5425 /* PowerPC 755 v2.2 */
5426 POWERPC_DEF("755v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5),
5427 /* PowerPC 745 v2.3 */
5428 POWERPC_DEF("745v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5),
5429 /* PowerPC 755 v2.3 */
5430 POWERPC_DEF("755v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5),
5431 /* PowerPC 745 v2.4 */
5432 POWERPC_DEF("745v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5),
5433 /* PowerPC 755 v2.4 */
5434 POWERPC_DEF("755v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5),
5435 /* PowerPC 745 v2.5 */
5436 POWERPC_DEF("745v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5),
5437 /* PowerPC 755 v2.5 */
5438 POWERPC_DEF("755v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5),
5439 /* PowerPC 745 v2.6 */
5440 POWERPC_DEF("745v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5),
5441 /* PowerPC 755 v2.6 */
5442 POWERPC_DEF("755v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5),
5443 /* PowerPC 745 v2.7 */
5444 POWERPC_DEF("745v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5),
5445 /* PowerPC 755 v2.7 */
5446 POWERPC_DEF("755v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5),
5447 /* PowerPC 745 v2.8 */
5448 POWERPC_DEF("745v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5),
5449 /* PowerPC 755 v2.8 */
5450 POWERPC_DEF("755v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5),
5451 #if defined (TODO)
5452 /* PowerPC 745P (G3) */
5453 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5),
5454 /* PowerPC 755P (G3) */
5455 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5),
5456 #endif
5457 /* PowerPC 74xx family */
5458 /* PowerPC 7400 (G4) */
5459 POWERPC_DEF("7400", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5460 /* Code name for PowerPC 7400 */
5461 POWERPC_DEF("Max", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5462 /* PowerPC 74xx is also well known as G4 */
5463 POWERPC_DEF("G4", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5464 /* PowerPC 7400 v1.0 (G4) */
5465 POWERPC_DEF("7400v1.0", CPU_POWERPC_7400_v10, 0xFFFFFFFF, 7400),
5466 /* PowerPC 7400 v1.1 (G4) */
5467 POWERPC_DEF("7400v1.1", CPU_POWERPC_7400_v11, 0xFFFFFFFF, 7400),
5468 /* PowerPC 7400 v2.0 (G4) */
5469 POWERPC_DEF("7400v2.0", CPU_POWERPC_7400_v20, 0xFFFFFFFF, 7400),
5470 /* PowerPC 7400 v2.2 (G4) */
5471 POWERPC_DEF("7400v2.2", CPU_POWERPC_7400_v22, 0xFFFFFFFF, 7400),
5472 /* PowerPC 7400 v2.6 (G4) */
5473 POWERPC_DEF("7400v2.6", CPU_POWERPC_7400_v26, 0xFFFFFFFF, 7400),
5474 /* PowerPC 7400 v2.7 (G4) */
5475 POWERPC_DEF("7400v2.7", CPU_POWERPC_7400_v27, 0xFFFFFFFF, 7400),
5476 /* PowerPC 7400 v2.8 (G4) */
5477 POWERPC_DEF("7400v2.8", CPU_POWERPC_7400_v28, 0xFFFFFFFF, 7400),
5478 /* PowerPC 7400 v2.9 (G4) */
5479 POWERPC_DEF("7400v2.9", CPU_POWERPC_7400_v29, 0xFFFFFFFF, 7400),
5480 /* PowerPC 7410 (G4) */
5481 POWERPC_DEF("7410", CPU_POWERPC_7410, 0xFFFFFFFF, 7410),
5482 /* Code name for PowerPC 7410 */
5483 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 0xFFFFFFFF, 7410),
5484 /* PowerPC 7410 v1.0 (G4) */
5485 POWERPC_DEF("7410v1.0", CPU_POWERPC_7410_v10, 0xFFFFFFFF, 7410),
5486 /* PowerPC 7410 v1.1 (G4) */
5487 POWERPC_DEF("7410v1.1", CPU_POWERPC_7410_v11, 0xFFFFFFFF, 7410),
5488 /* PowerPC 7410 v1.2 (G4) */
5489 POWERPC_DEF("7410v1.2", CPU_POWERPC_7410_v12, 0xFFFFFFFF, 7410),
5490 /* PowerPC 7410 v1.3 (G4) */
5491 POWERPC_DEF("7410v1.3", CPU_POWERPC_7410_v13, 0xFFFFFFFF, 7410),
5492 /* PowerPC 7410 v1.4 (G4) */
5493 POWERPC_DEF("7410v1.4", CPU_POWERPC_7410_v14, 0xFFFFFFFF, 7410),
5494 /* PowerPC 7448 (G4) */
5495 POWERPC_DEF("7448", CPU_POWERPC_7448, 0xFFFFFFFF, 7400),
5496 /* PowerPC 7448 v1.0 (G4) */
5497 POWERPC_DEF("7448v1.0", CPU_POWERPC_7448_v10, 0xFFFFFFFF, 7400),
5498 /* PowerPC 7448 v1.1 (G4) */
5499 POWERPC_DEF("7448v1.1", CPU_POWERPC_7448_v11, 0xFFFFFFFF, 7400),
5500 /* PowerPC 7448 v2.0 (G4) */
5501 POWERPC_DEF("7448v2.0", CPU_POWERPC_7448_v20, 0xFFFFFFFF, 7400),
5502 /* PowerPC 7448 v2.1 (G4) */
5503 POWERPC_DEF("7448v2.1", CPU_POWERPC_7448_v21, 0xFFFFFFFF, 7400),
5504 #if defined (TODO)
5505 /* PowerPC 7450 (G4) */
5506 POWERPC_DEF("7450", CPU_POWERPC_7450, 0xFFFFFFFF, 7450),
5507 /* Code name for PowerPC 7450 */
5508 POWERPC_DEF("Vger", CPU_POWERPC_7450, 0xFFFFFFFF, 7450),
5509 #endif
5510 #if defined (TODO)
5511 /* PowerPC 7450 v1.0 (G4) */
5512 POWERPC_DEF("7450v1.0", CPU_POWERPC_7450_v10, 0xFFFFFFFF, 7450),
5513 #endif
5514 #if defined (TODO)
5515 /* PowerPC 7450 v1.1 (G4) */
5516 POWERPC_DEF("7450v1.1", CPU_POWERPC_7450_v11, 0xFFFFFFFF, 7450),
5517 #endif
5518 #if defined (TODO)
5519 /* PowerPC 7450 v1.2 (G4) */
5520 POWERPC_DEF("7450v1.2", CPU_POWERPC_7450_v12, 0xFFFFFFFF, 7450),
5521 #endif
5522 #if defined (TODO)
5523 /* PowerPC 7450 v2.0 (G4) */
5524 POWERPC_DEF("7450v2.0", CPU_POWERPC_7450_v20, 0xFFFFFFFF, 7450),
5525 #endif
5526 #if defined (TODO)
5527 /* PowerPC 7450 v2.1 (G4) */
5528 POWERPC_DEF("7450v2.1", CPU_POWERPC_7450_v21, 0xFFFFFFFF, 7450),
5529 #endif
5530 #if defined (TODO)
5531 /* PowerPC 7441 (G4) */
5532 POWERPC_DEF("7441", CPU_POWERPC_74x1, 0xFFFFFFFF, 7440),
5533 /* PowerPC 7451 (G4) */
5534 POWERPC_DEF("7451", CPU_POWERPC_74x1, 0xFFFFFFFF, 7450),
5535 #endif
5536 #if defined (TODO)
5537 /* PowerPC 7441g (G4) */
5538 POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7440),
5539 /* PowerPC 7451g (G4) */
5540 POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7450),
5541 #endif
5542 #if defined (TODO)
5543 /* PowerPC 7445 (G4) */
5544 POWERPC_DEF("7445", CPU_POWERPC_74x5, 0xFFFFFFFF, 7445),
5545 /* PowerPC 7455 (G4) */
5546 POWERPC_DEF("7455", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455),
5547 /* Code name for PowerPC 7445/7455 */
5548 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455),
5549 #endif
5550 #if defined (TODO)
5551 /* PowerPC 7445 v1.0 (G4) */
5552 POWERPC_DEF("7445v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7445),
5553 /* PowerPC 7455 v1.0 (G4) */
5554 POWERPC_DEF("7455v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7455),
5555 #endif
5556 #if defined (TODO)
5557 /* PowerPC 7445 v2.1 (G4) */
5558 POWERPC_DEF("7445v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7445),
5559 /* PowerPC 7455 v2.1 (G4) */
5560 POWERPC_DEF("7455v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7455),
5561 #endif
5562 #if defined (TODO)
5563 /* PowerPC 7445 v3.2 (G4) */
5564 POWERPC_DEF("7445v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7445),
5565 /* PowerPC 7455 v3.2 (G4) */
5566 POWERPC_DEF("7455v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7455),
5567 #endif
5568 #if defined (TODO)
5569 /* PowerPC 7445 v3.3 (G4) */
5570 POWERPC_DEF("7445v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7445),
5571 /* PowerPC 7455 v3.3 (G4) */
5572 POWERPC_DEF("7455v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7455),
5573 #endif
5574 #if defined (TODO)
5575 /* PowerPC 7445 v3.4 (G4) */
5576 POWERPC_DEF("7445v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7445),
5577 /* PowerPC 7455 v3.4 (G4) */
5578 POWERPC_DEF("7455v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7455),
5579 #endif
5580 #if defined (TODO)
5581 /* PowerPC 7447 (G4) */
5582 POWERPC_DEF("7447", CPU_POWERPC_74x7, 0xFFFFFFFF, 7445),
5583 /* PowerPC 7457 (G4) */
5584 POWERPC_DEF("7457", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455),
5585 /* Code name for PowerPC 7447/7457 */
5586 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455),
5587 #endif
5588 #if defined (TODO)
5589 /* PowerPC 7447 v1.0 (G4) */
5590 POWERPC_DEF("7447v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7445),
5591 /* PowerPC 7457 v1.0 (G4) */
5592 POWERPC_DEF("7457v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455),
5593 /* Code name for PowerPC 7447A/7457A */
5594 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455),
5595 #endif
5596 #if defined (TODO)
5597 /* PowerPC 7447 v1.1 (G4) */
5598 POWERPC_DEF("7447v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7445),
5599 /* PowerPC 7457 v1.1 (G4) */
5600 POWERPC_DEF("7457v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7455),
5601 #endif
5602 #if defined (TODO)
5603 /* PowerPC 7447 v1.2 (G4) */
5604 POWERPC_DEF("7447v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7445),
5605 /* PowerPC 7457 v1.2 (G4) */
5606 POWERPC_DEF("7457v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7455),
5607 #endif
5608 /* 64 bits PowerPC */
5609 #if defined (TARGET_PPC64)
5610 #if defined (TODO)
5611 /* PowerPC 620 */
5612 POWERPC_DEF("620", CPU_POWERPC_620, 0xFFFFFFFF, 620),
5613 #endif
5614 #if defined (TODO)
5615 /* PowerPC 630 (POWER3) */
5616 POWERPC_DEF("630", CPU_POWERPC_630, 0xFFFFFFFF, 630),
5617 POWERPC_DEF("POWER3", CPU_POWERPC_630, 0xFFFFFFFF, 630),
5618 #endif
5619 #if defined (TODO)
5620 /* PowerPC 631 (Power 3+) */
5621 POWERPC_DEF("631", CPU_POWERPC_631, 0xFFFFFFFF, 631),
5622 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 0xFFFFFFFF, 631),
5623 #endif
5624 #if defined (TODO)
5625 /* POWER4 */
5626 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, 0xFFFFFFFF, POWER4),
5627 #endif
5628 #if defined (TODO)
5629 /* POWER4p */
5630 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, 0xFFFFFFFF, POWER4P),
5631 #endif
5632 #if defined (TODO)
5633 /* POWER5 */
5634 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, 0xFFFFFFFF, POWER5),
5635 /* POWER5GR */
5636 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, 0xFFFFFFFF, POWER5),
5637 #endif
5638 #if defined (TODO)
5639 /* POWER5+ */
5640 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, 0xFFFFFFFF, POWER5P),
5641 /* POWER5GS */
5642 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, 0xFFFFFFFF, POWER5P),
5643 #endif
5644 #if defined (TODO)
5645 /* POWER6 */
5646 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, 0xFFFFFFFF, POWER6),
5647 /* POWER6 running in POWER5 mode */
5648 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, 0xFFFFFFFF, POWER5),
5649 /* POWER6A */
5650 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, 0xFFFFFFFF, POWER6),
5651 #endif
5652 /* PowerPC 970 */
5653 POWERPC_DEF("970", CPU_POWERPC_970, 0xFFFFFFFF, 970),
5654 /* PowerPC 970FX (G5) */
5655 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 0xFFFFFFFF, 970FX),
5656 /* PowerPC 970FX v1.0 (G5) */
5657 POWERPC_DEF("970fx1.0", CPU_POWERPC_970FX_v10, 0xFFFFFFFF, 970FX),
5658 /* PowerPC 970FX v2.0 (G5) */
5659 POWERPC_DEF("970fx2.0", CPU_POWERPC_970FX_v20, 0xFFFFFFFF, 970FX),
5660 /* PowerPC 970FX v2.1 (G5) */
5661 POWERPC_DEF("970fx2.1", CPU_POWERPC_970FX_v21, 0xFFFFFFFF, 970FX),
5662 /* PowerPC 970FX v3.0 (G5) */
5663 POWERPC_DEF("970fx3.0", CPU_POWERPC_970FX_v30, 0xFFFFFFFF, 970FX),
5664 /* PowerPC 970FX v3.1 (G5) */
5665 POWERPC_DEF("970fx3.1", CPU_POWERPC_970FX_v31, 0xFFFFFFFF, 970FX),
5666 /* PowerPC 970GX (G5) */
5667 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 0xFFFFFFFF, 970GX),
5668 /* PowerPC 970MP */
5669 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 0xFFFFFFFF, 970),
5670 /* PowerPC 970MP v1.0 */
5671 POWERPC_DEF("970mp1.0", CPU_POWERPC_970MP_v10, 0xFFFFFFFF, 970),
5672 /* PowerPC 970MP v1.1 */
5673 POWERPC_DEF("970mp1.1", CPU_POWERPC_970MP_v11, 0xFFFFFFFF, 970),
5674 #if defined (TODO)
5675 /* PowerPC Cell */
5676 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 0xFFFFFFFF, 970),
5677 #endif
5678 #if defined (TODO)
5679 /* PowerPC Cell v1.0 */
5680 POWERPC_DEF("Cell1.0", CPU_POWERPC_CELL_v10, 0xFFFFFFFF, 970),
5681 #endif
5682 #if defined (TODO)
5683 /* PowerPC Cell v2.0 */
5684 POWERPC_DEF("Cell2.0", CPU_POWERPC_CELL_v20, 0xFFFFFFFF, 970),
5685 #endif
5686 #if defined (TODO)
5687 /* PowerPC Cell v3.0 */
5688 POWERPC_DEF("Cell3.0", CPU_POWERPC_CELL_v30, 0xFFFFFFFF, 970),
5689 #endif
5690 #if defined (TODO)
5691 /* PowerPC Cell v3.1 */
5692 POWERPC_DEF("Cell3.1", CPU_POWERPC_CELL_v31, 0xFFFFFFFF, 970),
5693 #endif
5694 #if defined (TODO)
5695 /* PowerPC Cell v3.2 */
5696 POWERPC_DEF("Cell3.2", CPU_POWERPC_CELL_v32, 0xFFFFFFFF, 970),
5697 #endif
5698 #if defined (TODO)
5699 /* RS64 (Apache/A35) */
5700 /* This one seems to support the whole POWER2 instruction set
5701 * and the PowerPC 64 one.
5702 */
5703 /* What about A10 & A30 ? */
5704 POWERPC_DEF("RS64", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
5705 POWERPC_DEF("Apache", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
5706 POWERPC_DEF("A35", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
5707 #endif
5708 #if defined (TODO)
5709 /* RS64-II (NorthStar/A50) */
5710 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
5711 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
5712 POWERPC_DEF("A50", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
5713 #endif
5714 #if defined (TODO)
5715 /* RS64-III (Pulsar) */
5716 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64),
5717 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64),
5718 #endif
5719 #if defined (TODO)
5720 /* RS64-IV (IceStar/IStar/SStar) */
5721 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5722 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5723 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5724 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5725 #endif
5726 #endif /* defined (TARGET_PPC64) */
5727 /* POWER */
5728 #if defined (TODO)
5729 /* Original POWER */
5730 POWERPC_DEF("POWER", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5731 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5732 POWERPC_DEF("RSC", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5733 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5734 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5735 #endif
5736 #if defined (TODO)
5737 /* POWER2 */
5738 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5739 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5740 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5741 #endif
5742 /* PA semi cores */
5743 #if defined (TODO)
5744 /* PA PA6T */
5745 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, 0xFFFFFFFF, PA6T),
5746 #endif
5747 /* Generic PowerPCs */
5748 #if defined (TARGET_PPC64)
5749 #if defined (TODO)
5750 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, 0xFFFFFFFF, PPC64),
5751 #endif
5752 #endif
5753 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, 0xFFFFFFFF, PPC32),
5754 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, 0xFFFFFFFF, DEFAULT),
5755 /* Fallback */
5756 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, 0xFFFFFFFF, DEFAULT),
5757 };
5758
5759 /*****************************************************************************/
5760 /* Generic CPU instanciation routine */
5761 static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
5762 {
5763 #if !defined(CONFIG_USER_ONLY)
5764 int i;
5765
5766 env->irq_inputs = NULL;
5767 /* Set all exception vectors to an invalid address */
5768 for (i = 0; i < POWERPC_EXCP_NB; i++)
5769 env->excp_vectors[i] = (target_ulong)(-1ULL);
5770 env->excp_prefix = 0x00000000;
5771 env->ivor_mask = 0x00000000;
5772 env->ivpr_mask = 0x00000000;
5773 /* Default MMU definitions */
5774 env->nb_BATs = 0;
5775 env->nb_tlb = 0;
5776 env->nb_ways = 0;
5777 #endif
5778 /* Register SPR common to all PowerPC implementations */
5779 gen_spr_generic(env);
5780 spr_register(env, SPR_PVR, "PVR",
5781 SPR_NOACCESS, SPR_NOACCESS,
5782 &spr_read_generic, SPR_NOACCESS,
5783 def->pvr);
5784 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
5785 (*def->init_proc)(env);
5786 /* Allocate TLBs buffer when needed */
5787 #if !defined(CONFIG_USER_ONLY)
5788 if (env->nb_tlb != 0) {
5789 int nb_tlb = env->nb_tlb;
5790 if (env->id_tlbs != 0)
5791 nb_tlb *= 2;
5792 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
5793 /* Pre-compute some useful values */
5794 env->tlb_per_way = env->nb_tlb / env->nb_ways;
5795 }
5796 if (env->irq_inputs == NULL) {
5797 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
5798 " Attempt Qemu to crash very soon !\n");
5799 }
5800 #endif
5801 }
5802
5803 #if defined(PPC_DUMP_CPU)
5804 static void dump_ppc_sprs (CPUPPCState *env)
5805 {
5806 ppc_spr_t *spr;
5807 #if !defined(CONFIG_USER_ONLY)
5808 uint32_t sr, sw;
5809 #endif
5810 uint32_t ur, uw;
5811 int i, j, n;
5812
5813 printf("Special purpose registers:\n");
5814 for (i = 0; i < 32; i++) {
5815 for (j = 0; j < 32; j++) {
5816 n = (i << 5) | j;
5817 spr = &env->spr_cb[n];
5818 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
5819 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
5820 #if !defined(CONFIG_USER_ONLY)
5821 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
5822 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
5823 if (sw || sr || uw || ur) {
5824 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
5825 (i << 5) | j, (i << 5) | j, spr->name,
5826 sw ? 'w' : '-', sr ? 'r' : '-',
5827 uw ? 'w' : '-', ur ? 'r' : '-');
5828 }
5829 #else
5830 if (uw || ur) {
5831 printf("SPR: %4d (%03x) %-8s u%c%c\n",
5832 (i << 5) | j, (i << 5) | j, spr->name,
5833 uw ? 'w' : '-', ur ? 'r' : '-');
5834 }
5835 #endif
5836 }
5837 }
5838 fflush(stdout);
5839 fflush(stderr);
5840 }
5841 #endif
5842
5843 /*****************************************************************************/
5844 #include <stdlib.h>
5845 #include <string.h>
5846
5847 int fflush (FILE *stream);
5848
5849 /* Opcode types */
5850 enum {
5851 PPC_DIRECT = 0, /* Opcode routine */
5852 PPC_INDIRECT = 1, /* Indirect opcode table */
5853 };
5854
5855 static inline int is_indirect_opcode (void *handler)
5856 {
5857 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
5858 }
5859
5860 static inline opc_handler_t **ind_table(void *handler)
5861 {
5862 return (opc_handler_t **)((unsigned long)handler & ~3);
5863 }
5864
5865 /* Instruction table creation */
5866 /* Opcodes tables creation */
5867 static void fill_new_table (opc_handler_t **table, int len)
5868 {
5869 int i;
5870
5871 for (i = 0; i < len; i++)
5872 table[i] = &invalid_handler;
5873 }
5874
5875 static int create_new_table (opc_handler_t **table, unsigned char idx)
5876 {
5877 opc_handler_t **tmp;
5878
5879 tmp = malloc(0x20 * sizeof(opc_handler_t));
5880 if (tmp == NULL)
5881 return -1;
5882 fill_new_table(tmp, 0x20);
5883 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
5884
5885 return 0;
5886 }
5887
5888 static int insert_in_table (opc_handler_t **table, unsigned char idx,
5889 opc_handler_t *handler)
5890 {
5891 if (table[idx] != &invalid_handler)
5892 return -1;
5893 table[idx] = handler;
5894
5895 return 0;
5896 }
5897
5898 static int register_direct_insn (opc_handler_t **ppc_opcodes,
5899 unsigned char idx, opc_handler_t *handler)
5900 {
5901 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
5902 printf("*** ERROR: opcode %02x already assigned in main "
5903 "opcode table\n", idx);
5904 return -1;
5905 }
5906
5907 return 0;
5908 }
5909
5910 static int register_ind_in_table (opc_handler_t **table,
5911 unsigned char idx1, unsigned char idx2,
5912 opc_handler_t *handler)
5913 {
5914 if (table[idx1] == &invalid_handler) {
5915 if (create_new_table(table, idx1) < 0) {
5916 printf("*** ERROR: unable to create indirect table "
5917 "idx=%02x\n", idx1);
5918 return -1;
5919 }
5920 } else {
5921 if (!is_indirect_opcode(table[idx1])) {
5922 printf("*** ERROR: idx %02x already assigned to a direct "
5923 "opcode\n", idx1);
5924 return -1;
5925 }
5926 }
5927 if (handler != NULL &&
5928 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
5929 printf("*** ERROR: opcode %02x already assigned in "
5930 "opcode table %02x\n", idx2, idx1);
5931 return -1;
5932 }
5933
5934 return 0;
5935 }
5936
5937 static int register_ind_insn (opc_handler_t **ppc_opcodes,
5938 unsigned char idx1, unsigned char idx2,
5939 opc_handler_t *handler)
5940 {
5941 int ret;
5942
5943 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
5944
5945 return ret;
5946 }
5947
5948 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
5949 unsigned char idx1, unsigned char idx2,
5950 unsigned char idx3, opc_handler_t *handler)
5951 {
5952 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
5953 printf("*** ERROR: unable to join indirect table idx "
5954 "[%02x-%02x]\n", idx1, idx2);
5955 return -1;
5956 }
5957 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
5958 handler) < 0) {
5959 printf("*** ERROR: unable to insert opcode "
5960 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
5961 return -1;
5962 }
5963
5964 return 0;
5965 }
5966
5967 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
5968 {
5969 if (insn->opc2 != 0xFF) {
5970 if (insn->opc3 != 0xFF) {
5971 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
5972 insn->opc3, &insn->handler) < 0)
5973 return -1;
5974 } else {
5975 if (register_ind_insn(ppc_opcodes, insn->opc1,
5976 insn->opc2, &insn->handler) < 0)
5977 return -1;
5978 }
5979 } else {
5980 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
5981 return -1;
5982 }
5983
5984 return 0;
5985 }
5986
5987 static int test_opcode_table (opc_handler_t **table, int len)
5988 {
5989 int i, count, tmp;
5990
5991 for (i = 0, count = 0; i < len; i++) {
5992 /* Consistency fixup */
5993 if (table[i] == NULL)
5994 table[i] = &invalid_handler;
5995 if (table[i] != &invalid_handler) {
5996 if (is_indirect_opcode(table[i])) {
5997 tmp = test_opcode_table(ind_table(table[i]), 0x20);
5998 if (tmp == 0) {
5999 free(table[i]);
6000 table[i] = &invalid_handler;
6001 } else {
6002 count++;
6003 }
6004 } else {
6005 count++;
6006 }
6007 }
6008 }
6009
6010 return count;
6011 }
6012
6013 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
6014 {
6015 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
6016 printf("*** WARNING: no opcode defined !\n");
6017 }
6018
6019 /*****************************************************************************/
6020 static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def)
6021 {
6022 opcode_t *opc, *start, *end;
6023
6024 fill_new_table(env->opcodes, 0x40);
6025 if (&opc_start < &opc_end) {
6026 start = &opc_start;
6027 end = &opc_end;
6028 } else {
6029 start = &opc_end;
6030 end = &opc_start;
6031 }
6032 for (opc = start + 1; opc != end; opc++) {
6033 if ((opc->handler.type & def->insns_flags) != 0) {
6034 if (register_insn(env->opcodes, opc) < 0) {
6035 printf("*** ERROR initializing PowerPC instruction "
6036 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
6037 opc->opc3);
6038 return -1;
6039 }
6040 }
6041 }
6042 fix_opcode_tables(env->opcodes);
6043 fflush(stdout);
6044 fflush(stderr);
6045
6046 return 0;
6047 }
6048
6049 #if defined(PPC_DUMP_CPU)
6050 static int dump_ppc_insns (CPUPPCState *env)
6051 {
6052 opc_handler_t **table, *handler;
6053 uint8_t opc1, opc2, opc3;
6054
6055 printf("Instructions set:\n");
6056 /* opc1 is 6 bits long */
6057 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
6058 table = env->opcodes;
6059 handler = table[opc1];
6060 if (is_indirect_opcode(handler)) {
6061 /* opc2 is 5 bits long */
6062 for (opc2 = 0; opc2 < 0x20; opc2++) {
6063 table = env->opcodes;
6064 handler = env->opcodes[opc1];
6065 table = ind_table(handler);
6066 handler = table[opc2];
6067 if (is_indirect_opcode(handler)) {
6068 table = ind_table(handler);
6069 /* opc3 is 5 bits long */
6070 for (opc3 = 0; opc3 < 0x20; opc3++) {
6071 handler = table[opc3];
6072 if (handler->handler != &gen_invalid) {
6073 printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
6074 opc1, opc2, opc3, opc1, (opc3 << 5) | opc2,
6075 handler->oname);
6076 }
6077 }
6078 } else {
6079 if (handler->handler != &gen_invalid) {
6080 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
6081 opc1, opc2, opc1, opc2, handler->oname);
6082 }
6083 }
6084 }
6085 } else {
6086 if (handler->handler != &gen_invalid) {
6087 printf("INSN: %02x -- -- (%02d ----) : %s\n",
6088 opc1, opc1, handler->oname);
6089 }
6090 }
6091 }
6092 }
6093 #endif
6094
6095 int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
6096 {
6097 env->msr_mask = def->msr_mask;
6098 env->mmu_model = def->mmu_model;
6099 env->excp_model = def->excp_model;
6100 env->bus_model = def->bus_model;
6101 env->flags = def->flags;
6102 env->bfd_mach = def->bfd_mach;
6103 if (create_ppc_opcodes(env, def) < 0)
6104 return -1;
6105 init_ppc_proc(env, def);
6106 #if defined(PPC_DUMP_CPU)
6107 {
6108 const unsigned char *mmu_model, *excp_model, *bus_model;
6109 switch (env->mmu_model) {
6110 case POWERPC_MMU_32B:
6111 mmu_model = "PowerPC 32";
6112 break;
6113 case POWERPC_MMU_601:
6114 mmu_model = "PowerPC 601";
6115 break;
6116 case POWERPC_MMU_SOFT_6xx:
6117 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
6118 break;
6119 case POWERPC_MMU_SOFT_74xx:
6120 mmu_model = "PowerPC 74xx with software driven TLBs";
6121 break;
6122 case POWERPC_MMU_SOFT_4xx:
6123 mmu_model = "PowerPC 4xx with software driven TLBs";
6124 break;
6125 case POWERPC_MMU_SOFT_4xx_Z:
6126 mmu_model = "PowerPC 4xx with software driven TLBs "
6127 "and zones protections";
6128 break;
6129 case POWERPC_MMU_REAL_4xx:
6130 mmu_model = "PowerPC 4xx real mode only";
6131 break;
6132 case POWERPC_MMU_BOOKE:
6133 mmu_model = "PowerPC BookE";
6134 break;
6135 case POWERPC_MMU_BOOKE_FSL:
6136 mmu_model = "PowerPC BookE FSL";
6137 break;
6138 #if defined (TARGET_PPC64)
6139 case POWERPC_MMU_64B:
6140 mmu_model = "PowerPC 64";
6141 break;
6142 #endif
6143 default:
6144 mmu_model = "Unknown or invalid";
6145 break;
6146 }
6147 switch (env->excp_model) {
6148 case POWERPC_EXCP_STD:
6149 excp_model = "PowerPC";
6150 break;
6151 case POWERPC_EXCP_40x:
6152 excp_model = "PowerPC 40x";
6153 break;
6154 case POWERPC_EXCP_601:
6155 excp_model = "PowerPC 601";
6156 break;
6157 case POWERPC_EXCP_602:
6158 excp_model = "PowerPC 602";
6159 break;
6160 case POWERPC_EXCP_603:
6161 excp_model = "PowerPC 603";
6162 break;
6163 case POWERPC_EXCP_603E:
6164 excp_model = "PowerPC 603e";
6165 break;
6166 case POWERPC_EXCP_604:
6167 excp_model = "PowerPC 604";
6168 break;
6169 case POWERPC_EXCP_7x0:
6170 excp_model = "PowerPC 740/750";
6171 break;
6172 case POWERPC_EXCP_7x5:
6173 excp_model = "PowerPC 745/755";
6174 break;
6175 case POWERPC_EXCP_74xx:
6176 excp_model = "PowerPC 74xx";
6177 break;
6178 case POWERPC_EXCP_BOOKE:
6179 excp_model = "PowerPC BookE";
6180 break;
6181 #if defined (TARGET_PPC64)
6182 case POWERPC_EXCP_970:
6183 excp_model = "PowerPC 970";
6184 break;
6185 #endif
6186 default:
6187 excp_model = "Unknown or invalid";
6188 break;
6189 }
6190 switch (env->bus_model) {
6191 case PPC_FLAGS_INPUT_6xx:
6192 bus_model = "PowerPC 6xx";
6193 break;
6194 case PPC_FLAGS_INPUT_BookE:
6195 bus_model = "PowerPC BookE";
6196 break;
6197 case PPC_FLAGS_INPUT_405:
6198 bus_model = "PowerPC 405";
6199 break;
6200 case PPC_FLAGS_INPUT_401:
6201 bus_model = "PowerPC 401/403";
6202 break;
6203 #if defined (TARGET_PPC64)
6204 case PPC_FLAGS_INPUT_970:
6205 bus_model = "PowerPC 970";
6206 break;
6207 #endif
6208 default:
6209 bus_model = "Unknown or invalid";
6210 break;
6211 }
6212 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
6213 " MMU model : %s\n",
6214 def->name, def->pvr, def->msr_mask, mmu_model);
6215 #if !defined(CONFIG_USER_ONLY)
6216 if (env->tlb != NULL) {
6217 printf(" %d %s TLB in %d ways\n",
6218 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
6219 env->nb_ways);
6220 }
6221 #endif
6222 printf(" Exceptions model : %s\n"
6223 " Bus model : %s\n",
6224 excp_model, bus_model);
6225 }
6226 dump_ppc_insns(env);
6227 dump_ppc_sprs(env);
6228 fflush(stdout);
6229 #endif
6230
6231 return 0;
6232 }
6233
6234 int ppc_find_by_name (const unsigned char *name, ppc_def_t **def)
6235 {
6236 int i, max, ret;
6237
6238 ret = -1;
6239 *def = NULL;
6240 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6241 for (i = 0; i < max; i++) {
6242 if (strcasecmp(name, ppc_defs[i].name) == 0) {
6243 *def = &ppc_defs[i];
6244 ret = 0;
6245 break;
6246 }
6247 }
6248
6249 return ret;
6250 }
6251
6252 int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
6253 {
6254 int i, max, ret;
6255
6256 ret = -1;
6257 *def = NULL;
6258 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6259 for (i = 0; i < max; i++) {
6260 if ((pvr & ppc_defs[i].pvr_mask) ==
6261 (ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) {
6262 *def = &ppc_defs[i];
6263 ret = 0;
6264 break;
6265 }
6266 }
6267
6268 return ret;
6269 }
6270
6271 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
6272 {
6273 int i, max;
6274
6275 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6276 for (i = 0; i < max; i++) {
6277 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
6278 ppc_defs[i].name, ppc_defs[i].pvr);
6279 }
6280 }
Qemu copy for testing