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[qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26 #include "dis-asm.h"
27
28 //#define PPC_DUMP_CPU
29 //#define PPC_DEBUG_SPR
30 //#define PPC_DEBUG_IRQ
31
32 struct ppc_def_t {
33 const unsigned char *name;
34 uint32_t pvr;
35 uint32_t pvr_mask;
36 uint64_t insns_flags;
37 uint64_t msr_mask;
38 uint8_t mmu_model;
39 uint8_t excp_model;
40 uint8_t bus_model;
41 uint8_t pad;
42 uint32_t flags;
43 int bfd_mach;
44 void (*init_proc)(CPUPPCState *env);
45 int (*check_pow)(CPUPPCState *env);
46 };
47
48 /* For user-mode emulation, we don't emulate any IRQ controller */
49 #if defined(CONFIG_USER_ONLY)
50 #define PPC_IRQ_INIT_FN(name) \
51 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
52 { \
53 }
54 #else
55 #define PPC_IRQ_INIT_FN(name) \
56 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
57 #endif
58
59 PPC_IRQ_INIT_FN(40x);
60 PPC_IRQ_INIT_FN(6xx);
61 PPC_IRQ_INIT_FN(970);
62
63 /* Generic callbacks:
64 * do nothing but store/retrieve spr value
65 */
66 #ifdef PPC_DUMP_SPR_ACCESSES
67 static void spr_read_generic (void *opaque, int sprn)
68 {
69 gen_op_load_dump_spr(sprn);
70 }
71
72 static void spr_write_generic (void *opaque, int sprn)
73 {
74 gen_op_store_dump_spr(sprn);
75 }
76 #else
77 static void spr_read_generic (void *opaque, int sprn)
78 {
79 gen_op_load_spr(sprn);
80 }
81
82 static void spr_write_generic (void *opaque, int sprn)
83 {
84 gen_op_store_spr(sprn);
85 }
86 #endif
87
88 #if !defined(CONFIG_USER_ONLY)
89 static void spr_write_clear (void *opaque, int sprn)
90 {
91 gen_op_mask_spr(sprn);
92 }
93 #endif
94
95 /* SPR common to all PowerPC */
96 /* XER */
97 static void spr_read_xer (void *opaque, int sprn)
98 {
99 gen_op_load_xer();
100 }
101
102 static void spr_write_xer (void *opaque, int sprn)
103 {
104 gen_op_store_xer();
105 }
106
107 /* LR */
108 static void spr_read_lr (void *opaque, int sprn)
109 {
110 gen_op_load_lr();
111 }
112
113 static void spr_write_lr (void *opaque, int sprn)
114 {
115 gen_op_store_lr();
116 }
117
118 /* CTR */
119 static void spr_read_ctr (void *opaque, int sprn)
120 {
121 gen_op_load_ctr();
122 }
123
124 static void spr_write_ctr (void *opaque, int sprn)
125 {
126 gen_op_store_ctr();
127 }
128
129 /* User read access to SPR */
130 /* USPRx */
131 /* UMMCRx */
132 /* UPMCx */
133 /* USIA */
134 /* UDECR */
135 static void spr_read_ureg (void *opaque, int sprn)
136 {
137 gen_op_load_spr(sprn + 0x10);
138 }
139
140 /* SPR common to all non-embedded PowerPC */
141 /* DECR */
142 #if !defined(CONFIG_USER_ONLY)
143 static void spr_read_decr (void *opaque, int sprn)
144 {
145 gen_op_load_decr();
146 }
147
148 static void spr_write_decr (void *opaque, int sprn)
149 {
150 gen_op_store_decr();
151 }
152 #endif
153
154 /* SPR common to all non-embedded PowerPC, except 601 */
155 /* Time base */
156 static void spr_read_tbl (void *opaque, int sprn)
157 {
158 gen_op_load_tbl();
159 }
160
161 static void spr_read_tbu (void *opaque, int sprn)
162 {
163 gen_op_load_tbu();
164 }
165
166 __attribute__ (( unused ))
167 static void spr_read_atbl (void *opaque, int sprn)
168 {
169 gen_op_load_atbl();
170 }
171
172 __attribute__ (( unused ))
173 static void spr_read_atbu (void *opaque, int sprn)
174 {
175 gen_op_load_atbu();
176 }
177
178 #if !defined(CONFIG_USER_ONLY)
179 static void spr_write_tbl (void *opaque, int sprn)
180 {
181 gen_op_store_tbl();
182 }
183
184 static void spr_write_tbu (void *opaque, int sprn)
185 {
186 gen_op_store_tbu();
187 }
188
189 __attribute__ (( unused ))
190 static void spr_write_atbl (void *opaque, int sprn)
191 {
192 gen_op_store_atbl();
193 }
194
195 __attribute__ (( unused ))
196 static void spr_write_atbu (void *opaque, int sprn)
197 {
198 gen_op_store_atbu();
199 }
200 #endif
201
202 #if !defined(CONFIG_USER_ONLY)
203 /* IBAT0U...IBAT0U */
204 /* IBAT0L...IBAT7L */
205 static void spr_read_ibat (void *opaque, int sprn)
206 {
207 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
208 }
209
210 static void spr_read_ibat_h (void *opaque, int sprn)
211 {
212 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
213 }
214
215 static void spr_write_ibatu (void *opaque, int sprn)
216 {
217 gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
218 }
219
220 static void spr_write_ibatu_h (void *opaque, int sprn)
221 {
222 gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
223 }
224
225 static void spr_write_ibatl (void *opaque, int sprn)
226 {
227 gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
228 }
229
230 static void spr_write_ibatl_h (void *opaque, int sprn)
231 {
232 gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
233 }
234
235 /* DBAT0U...DBAT7U */
236 /* DBAT0L...DBAT7L */
237 static void spr_read_dbat (void *opaque, int sprn)
238 {
239 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
240 }
241
242 static void spr_read_dbat_h (void *opaque, int sprn)
243 {
244 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
245 }
246
247 static void spr_write_dbatu (void *opaque, int sprn)
248 {
249 gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
250 }
251
252 static void spr_write_dbatu_h (void *opaque, int sprn)
253 {
254 gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
255 }
256
257 static void spr_write_dbatl (void *opaque, int sprn)
258 {
259 gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
260 }
261
262 static void spr_write_dbatl_h (void *opaque, int sprn)
263 {
264 gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
265 }
266
267 /* SDR1 */
268 static void spr_read_sdr1 (void *opaque, int sprn)
269 {
270 gen_op_load_sdr1();
271 }
272
273 static void spr_write_sdr1 (void *opaque, int sprn)
274 {
275 gen_op_store_sdr1();
276 }
277
278 /* 64 bits PowerPC specific SPRs */
279 /* ASR */
280 #if defined(TARGET_PPC64)
281 __attribute__ (( unused ))
282 static void spr_read_asr (void *opaque, int sprn)
283 {
284 gen_op_load_asr();
285 }
286
287 __attribute__ (( unused ))
288 static void spr_write_asr (void *opaque, int sprn)
289 {
290 gen_op_store_asr();
291 }
292 #endif
293 #endif
294
295 /* PowerPC 601 specific registers */
296 /* RTC */
297 static void spr_read_601_rtcl (void *opaque, int sprn)
298 {
299 gen_op_load_601_rtcl();
300 }
301
302 static void spr_read_601_rtcu (void *opaque, int sprn)
303 {
304 gen_op_load_601_rtcu();
305 }
306
307 #if !defined(CONFIG_USER_ONLY)
308 static void spr_write_601_rtcu (void *opaque, int sprn)
309 {
310 gen_op_store_601_rtcu();
311 }
312
313 static void spr_write_601_rtcl (void *opaque, int sprn)
314 {
315 gen_op_store_601_rtcl();
316 }
317 #endif
318
319 /* Unified bats */
320 #if !defined(CONFIG_USER_ONLY)
321 static void spr_read_601_ubat (void *opaque, int sprn)
322 {
323 gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
324 }
325
326 static void spr_write_601_ubatu (void *opaque, int sprn)
327 {
328 gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
329 }
330
331 static void spr_write_601_ubatl (void *opaque, int sprn)
332 {
333 gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
334 }
335 #endif
336
337 /* PowerPC 40x specific registers */
338 #if !defined(CONFIG_USER_ONLY)
339 static void spr_read_40x_pit (void *opaque, int sprn)
340 {
341 gen_op_load_40x_pit();
342 }
343
344 static void spr_write_40x_pit (void *opaque, int sprn)
345 {
346 gen_op_store_40x_pit();
347 }
348
349 static void spr_write_40x_dbcr0 (void *opaque, int sprn)
350 {
351 DisasContext *ctx = opaque;
352
353 gen_op_store_40x_dbcr0();
354 /* We must stop translation as we may have rebooted */
355 GEN_STOP(ctx);
356 }
357
358 static void spr_write_40x_sler (void *opaque, int sprn)
359 {
360 gen_op_store_40x_sler();
361 }
362
363 static void spr_write_booke_tcr (void *opaque, int sprn)
364 {
365 gen_op_store_booke_tcr();
366 }
367
368 static void spr_write_booke_tsr (void *opaque, int sprn)
369 {
370 gen_op_store_booke_tsr();
371 }
372 #endif
373
374 /* PowerPC 403 specific registers */
375 /* PBL1 / PBU1 / PBL2 / PBU2 */
376 #if !defined(CONFIG_USER_ONLY)
377 static void spr_read_403_pbr (void *opaque, int sprn)
378 {
379 gen_op_load_403_pb(sprn - SPR_403_PBL1);
380 }
381
382 static void spr_write_403_pbr (void *opaque, int sprn)
383 {
384 gen_op_store_403_pb(sprn - SPR_403_PBL1);
385 }
386
387 static void spr_write_pir (void *opaque, int sprn)
388 {
389 gen_op_store_pir();
390 }
391 #endif
392
393 #if !defined(CONFIG_USER_ONLY)
394 /* Callback used to write the exception vector base */
395 static void spr_write_excp_prefix (void *opaque, int sprn)
396 {
397 gen_op_store_excp_prefix();
398 gen_op_store_spr(sprn);
399 }
400
401 static void spr_write_excp_vector (void *opaque, int sprn)
402 {
403 DisasContext *ctx = opaque;
404
405 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
406 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR0);
407 gen_op_store_spr(sprn);
408 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
409 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR32 + 32);
410 gen_op_store_spr(sprn);
411 } else {
412 printf("Trying to write an unknown exception vector %d %03x\n",
413 sprn, sprn);
414 GEN_EXCP_PRIVREG(ctx);
415 }
416 }
417 #endif
418
419 #if defined(CONFIG_USER_ONLY)
420 #define spr_register(env, num, name, uea_read, uea_write, \
421 oea_read, oea_write, initial_value) \
422 do { \
423 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
424 } while (0)
425 static inline void _spr_register (CPUPPCState *env, int num,
426 const unsigned char *name,
427 void (*uea_read)(void *opaque, int sprn),
428 void (*uea_write)(void *opaque, int sprn),
429 target_ulong initial_value)
430 #else
431 static inline void spr_register (CPUPPCState *env, int num,
432 const unsigned char *name,
433 void (*uea_read)(void *opaque, int sprn),
434 void (*uea_write)(void *opaque, int sprn),
435 void (*oea_read)(void *opaque, int sprn),
436 void (*oea_write)(void *opaque, int sprn),
437 target_ulong initial_value)
438 #endif
439 {
440 ppc_spr_t *spr;
441
442 spr = &env->spr_cb[num];
443 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
444 #if !defined(CONFIG_USER_ONLY)
445 spr->oea_read != NULL || spr->oea_write != NULL ||
446 #endif
447 spr->uea_read != NULL || spr->uea_write != NULL) {
448 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
449 exit(1);
450 }
451 #if defined(PPC_DEBUG_SPR)
452 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
453 initial_value);
454 #endif
455 spr->name = name;
456 spr->uea_read = uea_read;
457 spr->uea_write = uea_write;
458 #if !defined(CONFIG_USER_ONLY)
459 spr->oea_read = oea_read;
460 spr->oea_write = oea_write;
461 #endif
462 env->spr[num] = initial_value;
463 }
464
465 /* Generic PowerPC SPRs */
466 static void gen_spr_generic (CPUPPCState *env)
467 {
468 /* Integer processing */
469 spr_register(env, SPR_XER, "XER",
470 &spr_read_xer, &spr_write_xer,
471 &spr_read_xer, &spr_write_xer,
472 0x00000000);
473 /* Branch contol */
474 spr_register(env, SPR_LR, "LR",
475 &spr_read_lr, &spr_write_lr,
476 &spr_read_lr, &spr_write_lr,
477 0x00000000);
478 spr_register(env, SPR_CTR, "CTR",
479 &spr_read_ctr, &spr_write_ctr,
480 &spr_read_ctr, &spr_write_ctr,
481 0x00000000);
482 /* Interrupt processing */
483 spr_register(env, SPR_SRR0, "SRR0",
484 SPR_NOACCESS, SPR_NOACCESS,
485 &spr_read_generic, &spr_write_generic,
486 0x00000000);
487 spr_register(env, SPR_SRR1, "SRR1",
488 SPR_NOACCESS, SPR_NOACCESS,
489 &spr_read_generic, &spr_write_generic,
490 0x00000000);
491 /* Processor control */
492 spr_register(env, SPR_SPRG0, "SPRG0",
493 SPR_NOACCESS, SPR_NOACCESS,
494 &spr_read_generic, &spr_write_generic,
495 0x00000000);
496 spr_register(env, SPR_SPRG1, "SPRG1",
497 SPR_NOACCESS, SPR_NOACCESS,
498 &spr_read_generic, &spr_write_generic,
499 0x00000000);
500 spr_register(env, SPR_SPRG2, "SPRG2",
501 SPR_NOACCESS, SPR_NOACCESS,
502 &spr_read_generic, &spr_write_generic,
503 0x00000000);
504 spr_register(env, SPR_SPRG3, "SPRG3",
505 SPR_NOACCESS, SPR_NOACCESS,
506 &spr_read_generic, &spr_write_generic,
507 0x00000000);
508 }
509
510 /* SPR common to all non-embedded PowerPC, including 601 */
511 static void gen_spr_ne_601 (CPUPPCState *env)
512 {
513 /* Exception processing */
514 spr_register(env, SPR_DSISR, "DSISR",
515 SPR_NOACCESS, SPR_NOACCESS,
516 &spr_read_generic, &spr_write_generic,
517 0x00000000);
518 spr_register(env, SPR_DAR, "DAR",
519 SPR_NOACCESS, SPR_NOACCESS,
520 &spr_read_generic, &spr_write_generic,
521 0x00000000);
522 /* Timer */
523 spr_register(env, SPR_DECR, "DECR",
524 SPR_NOACCESS, SPR_NOACCESS,
525 &spr_read_decr, &spr_write_decr,
526 0x00000000);
527 /* Memory management */
528 spr_register(env, SPR_SDR1, "SDR1",
529 SPR_NOACCESS, SPR_NOACCESS,
530 &spr_read_sdr1, &spr_write_sdr1,
531 0x00000000);
532 }
533
534 /* BATs 0-3 */
535 static void gen_low_BATs (CPUPPCState *env)
536 {
537 #if !defined(CONFIG_USER_ONLY)
538 spr_register(env, SPR_IBAT0U, "IBAT0U",
539 SPR_NOACCESS, SPR_NOACCESS,
540 &spr_read_ibat, &spr_write_ibatu,
541 0x00000000);
542 spr_register(env, SPR_IBAT0L, "IBAT0L",
543 SPR_NOACCESS, SPR_NOACCESS,
544 &spr_read_ibat, &spr_write_ibatl,
545 0x00000000);
546 spr_register(env, SPR_IBAT1U, "IBAT1U",
547 SPR_NOACCESS, SPR_NOACCESS,
548 &spr_read_ibat, &spr_write_ibatu,
549 0x00000000);
550 spr_register(env, SPR_IBAT1L, "IBAT1L",
551 SPR_NOACCESS, SPR_NOACCESS,
552 &spr_read_ibat, &spr_write_ibatl,
553 0x00000000);
554 spr_register(env, SPR_IBAT2U, "IBAT2U",
555 SPR_NOACCESS, SPR_NOACCESS,
556 &spr_read_ibat, &spr_write_ibatu,
557 0x00000000);
558 spr_register(env, SPR_IBAT2L, "IBAT2L",
559 SPR_NOACCESS, SPR_NOACCESS,
560 &spr_read_ibat, &spr_write_ibatl,
561 0x00000000);
562 spr_register(env, SPR_IBAT3U, "IBAT3U",
563 SPR_NOACCESS, SPR_NOACCESS,
564 &spr_read_ibat, &spr_write_ibatu,
565 0x00000000);
566 spr_register(env, SPR_IBAT3L, "IBAT3L",
567 SPR_NOACCESS, SPR_NOACCESS,
568 &spr_read_ibat, &spr_write_ibatl,
569 0x00000000);
570 spr_register(env, SPR_DBAT0U, "DBAT0U",
571 SPR_NOACCESS, SPR_NOACCESS,
572 &spr_read_dbat, &spr_write_dbatu,
573 0x00000000);
574 spr_register(env, SPR_DBAT0L, "DBAT0L",
575 SPR_NOACCESS, SPR_NOACCESS,
576 &spr_read_dbat, &spr_write_dbatl,
577 0x00000000);
578 spr_register(env, SPR_DBAT1U, "DBAT1U",
579 SPR_NOACCESS, SPR_NOACCESS,
580 &spr_read_dbat, &spr_write_dbatu,
581 0x00000000);
582 spr_register(env, SPR_DBAT1L, "DBAT1L",
583 SPR_NOACCESS, SPR_NOACCESS,
584 &spr_read_dbat, &spr_write_dbatl,
585 0x00000000);
586 spr_register(env, SPR_DBAT2U, "DBAT2U",
587 SPR_NOACCESS, SPR_NOACCESS,
588 &spr_read_dbat, &spr_write_dbatu,
589 0x00000000);
590 spr_register(env, SPR_DBAT2L, "DBAT2L",
591 SPR_NOACCESS, SPR_NOACCESS,
592 &spr_read_dbat, &spr_write_dbatl,
593 0x00000000);
594 spr_register(env, SPR_DBAT3U, "DBAT3U",
595 SPR_NOACCESS, SPR_NOACCESS,
596 &spr_read_dbat, &spr_write_dbatu,
597 0x00000000);
598 spr_register(env, SPR_DBAT3L, "DBAT3L",
599 SPR_NOACCESS, SPR_NOACCESS,
600 &spr_read_dbat, &spr_write_dbatl,
601 0x00000000);
602 env->nb_BATs += 4;
603 #endif
604 }
605
606 /* BATs 4-7 */
607 static void gen_high_BATs (CPUPPCState *env)
608 {
609 #if !defined(CONFIG_USER_ONLY)
610 spr_register(env, SPR_IBAT4U, "IBAT4U",
611 SPR_NOACCESS, SPR_NOACCESS,
612 &spr_read_ibat_h, &spr_write_ibatu_h,
613 0x00000000);
614 spr_register(env, SPR_IBAT4L, "IBAT4L",
615 SPR_NOACCESS, SPR_NOACCESS,
616 &spr_read_ibat_h, &spr_write_ibatl_h,
617 0x00000000);
618 spr_register(env, SPR_IBAT5U, "IBAT5U",
619 SPR_NOACCESS, SPR_NOACCESS,
620 &spr_read_ibat_h, &spr_write_ibatu_h,
621 0x00000000);
622 spr_register(env, SPR_IBAT5L, "IBAT5L",
623 SPR_NOACCESS, SPR_NOACCESS,
624 &spr_read_ibat_h, &spr_write_ibatl_h,
625 0x00000000);
626 spr_register(env, SPR_IBAT6U, "IBAT6U",
627 SPR_NOACCESS, SPR_NOACCESS,
628 &spr_read_ibat_h, &spr_write_ibatu_h,
629 0x00000000);
630 spr_register(env, SPR_IBAT6L, "IBAT6L",
631 SPR_NOACCESS, SPR_NOACCESS,
632 &spr_read_ibat_h, &spr_write_ibatl_h,
633 0x00000000);
634 spr_register(env, SPR_IBAT7U, "IBAT7U",
635 SPR_NOACCESS, SPR_NOACCESS,
636 &spr_read_ibat_h, &spr_write_ibatu_h,
637 0x00000000);
638 spr_register(env, SPR_IBAT7L, "IBAT7L",
639 SPR_NOACCESS, SPR_NOACCESS,
640 &spr_read_ibat_h, &spr_write_ibatl_h,
641 0x00000000);
642 spr_register(env, SPR_DBAT4U, "DBAT4U",
643 SPR_NOACCESS, SPR_NOACCESS,
644 &spr_read_dbat_h, &spr_write_dbatu_h,
645 0x00000000);
646 spr_register(env, SPR_DBAT4L, "DBAT4L",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_dbat_h, &spr_write_dbatl_h,
649 0x00000000);
650 spr_register(env, SPR_DBAT5U, "DBAT5U",
651 SPR_NOACCESS, SPR_NOACCESS,
652 &spr_read_dbat_h, &spr_write_dbatu_h,
653 0x00000000);
654 spr_register(env, SPR_DBAT5L, "DBAT5L",
655 SPR_NOACCESS, SPR_NOACCESS,
656 &spr_read_dbat_h, &spr_write_dbatl_h,
657 0x00000000);
658 spr_register(env, SPR_DBAT6U, "DBAT6U",
659 SPR_NOACCESS, SPR_NOACCESS,
660 &spr_read_dbat_h, &spr_write_dbatu_h,
661 0x00000000);
662 spr_register(env, SPR_DBAT6L, "DBAT6L",
663 SPR_NOACCESS, SPR_NOACCESS,
664 &spr_read_dbat_h, &spr_write_dbatl_h,
665 0x00000000);
666 spr_register(env, SPR_DBAT7U, "DBAT7U",
667 SPR_NOACCESS, SPR_NOACCESS,
668 &spr_read_dbat_h, &spr_write_dbatu_h,
669 0x00000000);
670 spr_register(env, SPR_DBAT7L, "DBAT7L",
671 SPR_NOACCESS, SPR_NOACCESS,
672 &spr_read_dbat_h, &spr_write_dbatl_h,
673 0x00000000);
674 env->nb_BATs += 4;
675 #endif
676 }
677
678 /* Generic PowerPC time base */
679 static void gen_tbl (CPUPPCState *env)
680 {
681 spr_register(env, SPR_VTBL, "TBL",
682 &spr_read_tbl, SPR_NOACCESS,
683 &spr_read_tbl, SPR_NOACCESS,
684 0x00000000);
685 spr_register(env, SPR_TBL, "TBL",
686 SPR_NOACCESS, SPR_NOACCESS,
687 SPR_NOACCESS, &spr_write_tbl,
688 0x00000000);
689 spr_register(env, SPR_VTBU, "TBU",
690 &spr_read_tbu, SPR_NOACCESS,
691 &spr_read_tbu, SPR_NOACCESS,
692 0x00000000);
693 spr_register(env, SPR_TBU, "TBU",
694 SPR_NOACCESS, SPR_NOACCESS,
695 SPR_NOACCESS, &spr_write_tbu,
696 0x00000000);
697 }
698
699 /* Softare table search registers */
700 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
701 {
702 #if !defined(CONFIG_USER_ONLY)
703 env->nb_tlb = nb_tlbs;
704 env->nb_ways = nb_ways;
705 env->id_tlbs = 1;
706 spr_register(env, SPR_DMISS, "DMISS",
707 SPR_NOACCESS, SPR_NOACCESS,
708 &spr_read_generic, SPR_NOACCESS,
709 0x00000000);
710 spr_register(env, SPR_DCMP, "DCMP",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_generic, SPR_NOACCESS,
713 0x00000000);
714 spr_register(env, SPR_HASH1, "HASH1",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_generic, SPR_NOACCESS,
717 0x00000000);
718 spr_register(env, SPR_HASH2, "HASH2",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_generic, SPR_NOACCESS,
721 0x00000000);
722 spr_register(env, SPR_IMISS, "IMISS",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_generic, SPR_NOACCESS,
725 0x00000000);
726 spr_register(env, SPR_ICMP, "ICMP",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_generic, SPR_NOACCESS,
729 0x00000000);
730 spr_register(env, SPR_RPA, "RPA",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_generic, &spr_write_generic,
733 0x00000000);
734 #endif
735 }
736
737 /* SPR common to MPC755 and G2 */
738 static void gen_spr_G2_755 (CPUPPCState *env)
739 {
740 /* SGPRs */
741 spr_register(env, SPR_SPRG4, "SPRG4",
742 SPR_NOACCESS, SPR_NOACCESS,
743 &spr_read_generic, &spr_write_generic,
744 0x00000000);
745 spr_register(env, SPR_SPRG5, "SPRG5",
746 SPR_NOACCESS, SPR_NOACCESS,
747 &spr_read_generic, &spr_write_generic,
748 0x00000000);
749 spr_register(env, SPR_SPRG6, "SPRG6",
750 SPR_NOACCESS, SPR_NOACCESS,
751 &spr_read_generic, &spr_write_generic,
752 0x00000000);
753 spr_register(env, SPR_SPRG7, "SPRG7",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_generic, &spr_write_generic,
756 0x00000000);
757 /* External access control */
758 /* XXX : not implemented */
759 spr_register(env, SPR_EAR, "EAR",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_generic, &spr_write_generic,
762 0x00000000);
763 }
764
765 /* SPR common to all 7xx PowerPC implementations */
766 static void gen_spr_7xx (CPUPPCState *env)
767 {
768 /* Breakpoints */
769 /* XXX : not implemented */
770 spr_register(env, SPR_DABR, "DABR",
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_generic, &spr_write_generic,
773 0x00000000);
774 /* XXX : not implemented */
775 spr_register(env, SPR_IABR, "IABR",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_generic, &spr_write_generic,
778 0x00000000);
779 /* Cache management */
780 /* XXX : not implemented */
781 spr_register(env, SPR_ICTC, "ICTC",
782 SPR_NOACCESS, SPR_NOACCESS,
783 &spr_read_generic, &spr_write_generic,
784 0x00000000);
785 /* XXX : not implemented */
786 spr_register(env, SPR_L2CR, "L2CR",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_generic, &spr_write_generic,
789 0x00000000);
790 /* Performance monitors */
791 /* XXX : not implemented */
792 spr_register(env, SPR_MMCR0, "MMCR0",
793 SPR_NOACCESS, SPR_NOACCESS,
794 &spr_read_generic, &spr_write_generic,
795 0x00000000);
796 /* XXX : not implemented */
797 spr_register(env, SPR_MMCR1, "MMCR1",
798 SPR_NOACCESS, SPR_NOACCESS,
799 &spr_read_generic, &spr_write_generic,
800 0x00000000);
801 /* XXX : not implemented */
802 spr_register(env, SPR_PMC1, "PMC1",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_generic, &spr_write_generic,
805 0x00000000);
806 /* XXX : not implemented */
807 spr_register(env, SPR_PMC2, "PMC2",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_generic, &spr_write_generic,
810 0x00000000);
811 /* XXX : not implemented */
812 spr_register(env, SPR_PMC3, "PMC3",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_generic, &spr_write_generic,
815 0x00000000);
816 /* XXX : not implemented */
817 spr_register(env, SPR_PMC4, "PMC4",
818 SPR_NOACCESS, SPR_NOACCESS,
819 &spr_read_generic, &spr_write_generic,
820 0x00000000);
821 /* XXX : not implemented */
822 spr_register(env, SPR_SIAR, "SIAR",
823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_generic, SPR_NOACCESS,
825 0x00000000);
826 /* XXX : not implemented */
827 spr_register(env, SPR_UMMCR0, "UMMCR0",
828 &spr_read_ureg, SPR_NOACCESS,
829 &spr_read_ureg, SPR_NOACCESS,
830 0x00000000);
831 /* XXX : not implemented */
832 spr_register(env, SPR_UMMCR1, "UMMCR1",
833 &spr_read_ureg, SPR_NOACCESS,
834 &spr_read_ureg, SPR_NOACCESS,
835 0x00000000);
836 /* XXX : not implemented */
837 spr_register(env, SPR_UPMC1, "UPMC1",
838 &spr_read_ureg, SPR_NOACCESS,
839 &spr_read_ureg, SPR_NOACCESS,
840 0x00000000);
841 /* XXX : not implemented */
842 spr_register(env, SPR_UPMC2, "UPMC2",
843 &spr_read_ureg, SPR_NOACCESS,
844 &spr_read_ureg, SPR_NOACCESS,
845 0x00000000);
846 /* XXX : not implemented */
847 spr_register(env, SPR_UPMC3, "UPMC3",
848 &spr_read_ureg, SPR_NOACCESS,
849 &spr_read_ureg, SPR_NOACCESS,
850 0x00000000);
851 /* XXX : not implemented */
852 spr_register(env, SPR_UPMC4, "UPMC4",
853 &spr_read_ureg, SPR_NOACCESS,
854 &spr_read_ureg, SPR_NOACCESS,
855 0x00000000);
856 /* XXX : not implemented */
857 spr_register(env, SPR_USIAR, "USIAR",
858 &spr_read_ureg, SPR_NOACCESS,
859 &spr_read_ureg, SPR_NOACCESS,
860 0x00000000);
861 /* External access control */
862 /* XXX : not implemented */
863 spr_register(env, SPR_EAR, "EAR",
864 SPR_NOACCESS, SPR_NOACCESS,
865 &spr_read_generic, &spr_write_generic,
866 0x00000000);
867 }
868
869 static void gen_spr_thrm (CPUPPCState *env)
870 {
871 /* Thermal management */
872 /* XXX : not implemented */
873 spr_register(env, SPR_THRM1, "THRM1",
874 SPR_NOACCESS, SPR_NOACCESS,
875 &spr_read_generic, &spr_write_generic,
876 0x00000000);
877 /* XXX : not implemented */
878 spr_register(env, SPR_THRM2, "THRM2",
879 SPR_NOACCESS, SPR_NOACCESS,
880 &spr_read_generic, &spr_write_generic,
881 0x00000000);
882 /* XXX : not implemented */
883 spr_register(env, SPR_THRM3, "THRM3",
884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_generic, &spr_write_generic,
886 0x00000000);
887 }
888
889 /* SPR specific to PowerPC 604 implementation */
890 static void gen_spr_604 (CPUPPCState *env)
891 {
892 /* Processor identification */
893 spr_register(env, SPR_PIR, "PIR",
894 SPR_NOACCESS, SPR_NOACCESS,
895 &spr_read_generic, &spr_write_pir,
896 0x00000000);
897 /* Breakpoints */
898 /* XXX : not implemented */
899 spr_register(env, SPR_IABR, "IABR",
900 SPR_NOACCESS, SPR_NOACCESS,
901 &spr_read_generic, &spr_write_generic,
902 0x00000000);
903 /* XXX : not implemented */
904 spr_register(env, SPR_DABR, "DABR",
905 SPR_NOACCESS, SPR_NOACCESS,
906 &spr_read_generic, &spr_write_generic,
907 0x00000000);
908 /* Performance counters */
909 /* XXX : not implemented */
910 spr_register(env, SPR_MMCR0, "MMCR0",
911 SPR_NOACCESS, SPR_NOACCESS,
912 &spr_read_generic, &spr_write_generic,
913 0x00000000);
914 /* XXX : not implemented */
915 spr_register(env, SPR_MMCR1, "MMCR1",
916 SPR_NOACCESS, SPR_NOACCESS,
917 &spr_read_generic, &spr_write_generic,
918 0x00000000);
919 /* XXX : not implemented */
920 spr_register(env, SPR_PMC1, "PMC1",
921 SPR_NOACCESS, SPR_NOACCESS,
922 &spr_read_generic, &spr_write_generic,
923 0x00000000);
924 /* XXX : not implemented */
925 spr_register(env, SPR_PMC2, "PMC2",
926 SPR_NOACCESS, SPR_NOACCESS,
927 &spr_read_generic, &spr_write_generic,
928 0x00000000);
929 /* XXX : not implemented */
930 spr_register(env, SPR_PMC3, "PMC3",
931 SPR_NOACCESS, SPR_NOACCESS,
932 &spr_read_generic, &spr_write_generic,
933 0x00000000);
934 /* XXX : not implemented */
935 spr_register(env, SPR_PMC4, "PMC4",
936 SPR_NOACCESS, SPR_NOACCESS,
937 &spr_read_generic, &spr_write_generic,
938 0x00000000);
939 /* XXX : not implemented */
940 spr_register(env, SPR_SIAR, "SIAR",
941 SPR_NOACCESS, SPR_NOACCESS,
942 &spr_read_generic, SPR_NOACCESS,
943 0x00000000);
944 /* XXX : not implemented */
945 spr_register(env, SPR_SDA, "SDA",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_generic, SPR_NOACCESS,
948 0x00000000);
949 /* External access control */
950 /* XXX : not implemented */
951 spr_register(env, SPR_EAR, "EAR",
952 SPR_NOACCESS, SPR_NOACCESS,
953 &spr_read_generic, &spr_write_generic,
954 0x00000000);
955 }
956
957 /* SPR specific to PowerPC 603 implementation */
958 static void gen_spr_603 (CPUPPCState *env)
959 {
960 /* External access control */
961 /* XXX : not implemented */
962 spr_register(env, SPR_EAR, "EAR",
963 SPR_NOACCESS, SPR_NOACCESS,
964 &spr_read_generic, &spr_write_generic,
965 0x00000000);
966 }
967
968 /* SPR specific to PowerPC G2 implementation */
969 static void gen_spr_G2 (CPUPPCState *env)
970 {
971 /* Memory base address */
972 /* MBAR */
973 /* XXX : not implemented */
974 spr_register(env, SPR_MBAR, "MBAR",
975 SPR_NOACCESS, SPR_NOACCESS,
976 &spr_read_generic, &spr_write_generic,
977 0x00000000);
978 /* System version register */
979 /* SVR */
980 /* XXX : TODO: initialize it to an appropriate value */
981 spr_register(env, SPR_SVR, "SVR",
982 SPR_NOACCESS, SPR_NOACCESS,
983 &spr_read_generic, SPR_NOACCESS,
984 0x00000000);
985 /* Exception processing */
986 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
987 SPR_NOACCESS, SPR_NOACCESS,
988 &spr_read_generic, &spr_write_generic,
989 0x00000000);
990 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
991 SPR_NOACCESS, SPR_NOACCESS,
992 &spr_read_generic, &spr_write_generic,
993 0x00000000);
994 /* Breakpoints */
995 /* XXX : not implemented */
996 spr_register(env, SPR_DABR, "DABR",
997 SPR_NOACCESS, SPR_NOACCESS,
998 &spr_read_generic, &spr_write_generic,
999 0x00000000);
1000 /* XXX : not implemented */
1001 spr_register(env, SPR_DABR2, "DABR2",
1002 SPR_NOACCESS, SPR_NOACCESS,
1003 &spr_read_generic, &spr_write_generic,
1004 0x00000000);
1005 /* XXX : not implemented */
1006 spr_register(env, SPR_IABR, "IABR",
1007 SPR_NOACCESS, SPR_NOACCESS,
1008 &spr_read_generic, &spr_write_generic,
1009 0x00000000);
1010 /* XXX : not implemented */
1011 spr_register(env, SPR_IABR2, "IABR2",
1012 SPR_NOACCESS, SPR_NOACCESS,
1013 &spr_read_generic, &spr_write_generic,
1014 0x00000000);
1015 /* XXX : not implemented */
1016 spr_register(env, SPR_IBCR, "IBCR",
1017 SPR_NOACCESS, SPR_NOACCESS,
1018 &spr_read_generic, &spr_write_generic,
1019 0x00000000);
1020 /* XXX : not implemented */
1021 spr_register(env, SPR_DBCR, "DBCR",
1022 SPR_NOACCESS, SPR_NOACCESS,
1023 &spr_read_generic, &spr_write_generic,
1024 0x00000000);
1025 }
1026
1027 /* SPR specific to PowerPC 602 implementation */
1028 static void gen_spr_602 (CPUPPCState *env)
1029 {
1030 /* ESA registers */
1031 /* XXX : not implemented */
1032 spr_register(env, SPR_SER, "SER",
1033 SPR_NOACCESS, SPR_NOACCESS,
1034 &spr_read_generic, &spr_write_generic,
1035 0x00000000);
1036 /* XXX : not implemented */
1037 spr_register(env, SPR_SEBR, "SEBR",
1038 SPR_NOACCESS, SPR_NOACCESS,
1039 &spr_read_generic, &spr_write_generic,
1040 0x00000000);
1041 /* XXX : not implemented */
1042 spr_register(env, SPR_ESASRR, "ESASRR",
1043 SPR_NOACCESS, SPR_NOACCESS,
1044 &spr_read_generic, &spr_write_generic,
1045 0x00000000);
1046 /* Floating point status */
1047 /* XXX : not implemented */
1048 spr_register(env, SPR_SP, "SP",
1049 SPR_NOACCESS, SPR_NOACCESS,
1050 &spr_read_generic, &spr_write_generic,
1051 0x00000000);
1052 /* XXX : not implemented */
1053 spr_register(env, SPR_LT, "LT",
1054 SPR_NOACCESS, SPR_NOACCESS,
1055 &spr_read_generic, &spr_write_generic,
1056 0x00000000);
1057 /* Watchdog timer */
1058 /* XXX : not implemented */
1059 spr_register(env, SPR_TCR, "TCR",
1060 SPR_NOACCESS, SPR_NOACCESS,
1061 &spr_read_generic, &spr_write_generic,
1062 0x00000000);
1063 /* Interrupt base */
1064 spr_register(env, SPR_IBR, "IBR",
1065 SPR_NOACCESS, SPR_NOACCESS,
1066 &spr_read_generic, &spr_write_generic,
1067 0x00000000);
1068 /* XXX : not implemented */
1069 spr_register(env, SPR_IABR, "IABR",
1070 SPR_NOACCESS, SPR_NOACCESS,
1071 &spr_read_generic, &spr_write_generic,
1072 0x00000000);
1073 }
1074
1075 /* SPR specific to PowerPC 601 implementation */
1076 static void gen_spr_601 (CPUPPCState *env)
1077 {
1078 /* Multiplication/division register */
1079 /* MQ */
1080 spr_register(env, SPR_MQ, "MQ",
1081 &spr_read_generic, &spr_write_generic,
1082 &spr_read_generic, &spr_write_generic,
1083 0x00000000);
1084 /* RTC registers */
1085 spr_register(env, SPR_601_RTCU, "RTCU",
1086 SPR_NOACCESS, SPR_NOACCESS,
1087 SPR_NOACCESS, &spr_write_601_rtcu,
1088 0x00000000);
1089 spr_register(env, SPR_601_VRTCU, "RTCU",
1090 &spr_read_601_rtcu, SPR_NOACCESS,
1091 &spr_read_601_rtcu, SPR_NOACCESS,
1092 0x00000000);
1093 spr_register(env, SPR_601_RTCL, "RTCL",
1094 SPR_NOACCESS, SPR_NOACCESS,
1095 SPR_NOACCESS, &spr_write_601_rtcl,
1096 0x00000000);
1097 spr_register(env, SPR_601_VRTCL, "RTCL",
1098 &spr_read_601_rtcl, SPR_NOACCESS,
1099 &spr_read_601_rtcl, SPR_NOACCESS,
1100 0x00000000);
1101 /* Timer */
1102 #if 0 /* ? */
1103 spr_register(env, SPR_601_UDECR, "UDECR",
1104 &spr_read_decr, SPR_NOACCESS,
1105 &spr_read_decr, SPR_NOACCESS,
1106 0x00000000);
1107 #endif
1108 /* External access control */
1109 /* XXX : not implemented */
1110 spr_register(env, SPR_EAR, "EAR",
1111 SPR_NOACCESS, SPR_NOACCESS,
1112 &spr_read_generic, &spr_write_generic,
1113 0x00000000);
1114 /* Memory management */
1115 #if !defined(CONFIG_USER_ONLY)
1116 spr_register(env, SPR_IBAT0U, "IBAT0U",
1117 SPR_NOACCESS, SPR_NOACCESS,
1118 &spr_read_601_ubat, &spr_write_601_ubatu,
1119 0x00000000);
1120 spr_register(env, SPR_IBAT0L, "IBAT0L",
1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_601_ubat, &spr_write_601_ubatl,
1123 0x00000000);
1124 spr_register(env, SPR_IBAT1U, "IBAT1U",
1125 SPR_NOACCESS, SPR_NOACCESS,
1126 &spr_read_601_ubat, &spr_write_601_ubatu,
1127 0x00000000);
1128 spr_register(env, SPR_IBAT1L, "IBAT1L",
1129 SPR_NOACCESS, SPR_NOACCESS,
1130 &spr_read_601_ubat, &spr_write_601_ubatl,
1131 0x00000000);
1132 spr_register(env, SPR_IBAT2U, "IBAT2U",
1133 SPR_NOACCESS, SPR_NOACCESS,
1134 &spr_read_601_ubat, &spr_write_601_ubatu,
1135 0x00000000);
1136 spr_register(env, SPR_IBAT2L, "IBAT2L",
1137 SPR_NOACCESS, SPR_NOACCESS,
1138 &spr_read_601_ubat, &spr_write_601_ubatl,
1139 0x00000000);
1140 spr_register(env, SPR_IBAT3U, "IBAT3U",
1141 SPR_NOACCESS, SPR_NOACCESS,
1142 &spr_read_601_ubat, &spr_write_601_ubatu,
1143 0x00000000);
1144 spr_register(env, SPR_IBAT3L, "IBAT3L",
1145 SPR_NOACCESS, SPR_NOACCESS,
1146 &spr_read_601_ubat, &spr_write_601_ubatl,
1147 0x00000000);
1148 env->nb_BATs = 4;
1149 #endif
1150 }
1151
1152 static void gen_spr_74xx (CPUPPCState *env)
1153 {
1154 /* Processor identification */
1155 spr_register(env, SPR_PIR, "PIR",
1156 SPR_NOACCESS, SPR_NOACCESS,
1157 &spr_read_generic, &spr_write_pir,
1158 0x00000000);
1159 /* XXX : not implemented */
1160 spr_register(env, SPR_MMCR2, "MMCR2",
1161 SPR_NOACCESS, SPR_NOACCESS,
1162 &spr_read_generic, &spr_write_generic,
1163 0x00000000);
1164 /* XXX : not implemented */
1165 spr_register(env, SPR_UMMCR2, "UMMCR2",
1166 &spr_read_ureg, SPR_NOACCESS,
1167 &spr_read_ureg, SPR_NOACCESS,
1168 0x00000000);
1169 /* XXX: not implemented */
1170 spr_register(env, SPR_BAMR, "BAMR",
1171 SPR_NOACCESS, SPR_NOACCESS,
1172 &spr_read_generic, &spr_write_generic,
1173 0x00000000);
1174 /* XXX : not implemented */
1175 spr_register(env, SPR_UBAMR, "UBAMR",
1176 &spr_read_ureg, SPR_NOACCESS,
1177 &spr_read_ureg, SPR_NOACCESS,
1178 0x00000000);
1179 /* XXX : not implemented */
1180 spr_register(env, SPR_MSSCR0, "MSSCR0",
1181 SPR_NOACCESS, SPR_NOACCESS,
1182 &spr_read_generic, &spr_write_generic,
1183 0x00000000);
1184 /* Hardware implementation registers */
1185 /* XXX : not implemented */
1186 spr_register(env, SPR_HID0, "HID0",
1187 SPR_NOACCESS, SPR_NOACCESS,
1188 &spr_read_generic, &spr_write_generic,
1189 0x00000000);
1190 /* XXX : not implemented */
1191 spr_register(env, SPR_HID1, "HID1",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
1195 /* Altivec */
1196 spr_register(env, SPR_VRSAVE, "VRSAVE",
1197 &spr_read_generic, &spr_write_generic,
1198 &spr_read_generic, &spr_write_generic,
1199 0x00000000);
1200 }
1201
1202 static void gen_l3_ctrl (CPUPPCState *env)
1203 {
1204 /* L3CR */
1205 /* XXX : not implemented */
1206 spr_register(env, SPR_L3CR, "L3CR",
1207 SPR_NOACCESS, SPR_NOACCESS,
1208 &spr_read_generic, &spr_write_generic,
1209 0x00000000);
1210 /* L3ITCR0 */
1211 /* XXX : not implemented */
1212 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1213 SPR_NOACCESS, SPR_NOACCESS,
1214 &spr_read_generic, &spr_write_generic,
1215 0x00000000);
1216 /* L3ITCR1 */
1217 /* XXX : not implemented */
1218 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1219 SPR_NOACCESS, SPR_NOACCESS,
1220 &spr_read_generic, &spr_write_generic,
1221 0x00000000);
1222 /* L3ITCR2 */
1223 /* XXX : not implemented */
1224 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1225 SPR_NOACCESS, SPR_NOACCESS,
1226 &spr_read_generic, &spr_write_generic,
1227 0x00000000);
1228 /* L3ITCR3 */
1229 /* XXX : not implemented */
1230 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1231 SPR_NOACCESS, SPR_NOACCESS,
1232 &spr_read_generic, &spr_write_generic,
1233 0x00000000);
1234 /* L3OHCR */
1235 /* XXX : not implemented */
1236 spr_register(env, SPR_L3OHCR, "L3OHCR",
1237 SPR_NOACCESS, SPR_NOACCESS,
1238 &spr_read_generic, &spr_write_generic,
1239 0x00000000);
1240 /* L3PM */
1241 /* XXX : not implemented */
1242 spr_register(env, SPR_L3PM, "L3PM",
1243 SPR_NOACCESS, SPR_NOACCESS,
1244 &spr_read_generic, &spr_write_generic,
1245 0x00000000);
1246 }
1247
1248 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1249 {
1250 #if !defined(CONFIG_USER_ONLY)
1251 env->nb_tlb = nb_tlbs;
1252 env->nb_ways = nb_ways;
1253 env->id_tlbs = 1;
1254 /* XXX : not implemented */
1255 spr_register(env, SPR_PTEHI, "PTEHI",
1256 SPR_NOACCESS, SPR_NOACCESS,
1257 &spr_read_generic, &spr_write_generic,
1258 0x00000000);
1259 /* XXX : not implemented */
1260 spr_register(env, SPR_PTELO, "PTELO",
1261 SPR_NOACCESS, SPR_NOACCESS,
1262 &spr_read_generic, &spr_write_generic,
1263 0x00000000);
1264 /* XXX : not implemented */
1265 spr_register(env, SPR_TLBMISS, "TLBMISS",
1266 SPR_NOACCESS, SPR_NOACCESS,
1267 &spr_read_generic, &spr_write_generic,
1268 0x00000000);
1269 #endif
1270 }
1271
1272 /* PowerPC BookE SPR */
1273 static void gen_spr_BookE (CPUPPCState *env)
1274 {
1275 /* Processor identification */
1276 spr_register(env, SPR_BOOKE_PIR, "PIR",
1277 SPR_NOACCESS, SPR_NOACCESS,
1278 &spr_read_generic, &spr_write_pir,
1279 0x00000000);
1280 /* Interrupt processing */
1281 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1282 SPR_NOACCESS, SPR_NOACCESS,
1283 &spr_read_generic, &spr_write_generic,
1284 0x00000000);
1285 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1286 SPR_NOACCESS, SPR_NOACCESS,
1287 &spr_read_generic, &spr_write_generic,
1288 0x00000000);
1289 #if 0
1290 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1291 SPR_NOACCESS, SPR_NOACCESS,
1292 &spr_read_generic, &spr_write_generic,
1293 0x00000000);
1294 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1295 SPR_NOACCESS, SPR_NOACCESS,
1296 &spr_read_generic, &spr_write_generic,
1297 0x00000000);
1298 #endif
1299 /* Debug */
1300 /* XXX : not implemented */
1301 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1302 SPR_NOACCESS, SPR_NOACCESS,
1303 &spr_read_generic, &spr_write_generic,
1304 0x00000000);
1305 /* XXX : not implemented */
1306 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1307 SPR_NOACCESS, SPR_NOACCESS,
1308 &spr_read_generic, &spr_write_generic,
1309 0x00000000);
1310 /* XXX : not implemented */
1311 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1312 SPR_NOACCESS, SPR_NOACCESS,
1313 &spr_read_generic, &spr_write_generic,
1314 0x00000000);
1315 /* XXX : not implemented */
1316 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1317 SPR_NOACCESS, SPR_NOACCESS,
1318 &spr_read_generic, &spr_write_generic,
1319 0x00000000);
1320 /* XXX : not implemented */
1321 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1322 SPR_NOACCESS, SPR_NOACCESS,
1323 &spr_read_generic, &spr_write_generic,
1324 0x00000000);
1325 /* XXX : not implemented */
1326 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1327 SPR_NOACCESS, SPR_NOACCESS,
1328 &spr_read_generic, &spr_write_generic,
1329 0x00000000);
1330 /* XXX : not implemented */
1331 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1332 SPR_NOACCESS, SPR_NOACCESS,
1333 &spr_read_generic, &spr_write_generic,
1334 0x00000000);
1335 /* XXX : not implemented */
1336 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1337 SPR_NOACCESS, SPR_NOACCESS,
1338 &spr_read_generic, &spr_write_generic,
1339 0x00000000);
1340 /* XXX : not implemented */
1341 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1342 SPR_NOACCESS, SPR_NOACCESS,
1343 &spr_read_generic, &spr_write_generic,
1344 0x00000000);
1345 /* XXX : not implemented */
1346 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1347 SPR_NOACCESS, SPR_NOACCESS,
1348 &spr_read_generic, &spr_write_generic,
1349 0x00000000);
1350 /* XXX : not implemented */
1351 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1352 SPR_NOACCESS, SPR_NOACCESS,
1353 &spr_read_generic, &spr_write_generic,
1354 0x00000000);
1355 /* XXX : not implemented */
1356 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1357 SPR_NOACCESS, SPR_NOACCESS,
1358 &spr_read_generic, &spr_write_clear,
1359 0x00000000);
1360 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1361 SPR_NOACCESS, SPR_NOACCESS,
1362 &spr_read_generic, &spr_write_generic,
1363 0x00000000);
1364 spr_register(env, SPR_BOOKE_ESR, "ESR",
1365 SPR_NOACCESS, SPR_NOACCESS,
1366 &spr_read_generic, &spr_write_generic,
1367 0x00000000);
1368 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1369 SPR_NOACCESS, SPR_NOACCESS,
1370 &spr_read_generic, &spr_write_excp_prefix,
1371 0x00000000);
1372 /* Exception vectors */
1373 spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1374 SPR_NOACCESS, SPR_NOACCESS,
1375 &spr_read_generic, &spr_write_excp_vector,
1376 0x00000000);
1377 spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1378 SPR_NOACCESS, SPR_NOACCESS,
1379 &spr_read_generic, &spr_write_excp_vector,
1380 0x00000000);
1381 spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1382 SPR_NOACCESS, SPR_NOACCESS,
1383 &spr_read_generic, &spr_write_excp_vector,
1384 0x00000000);
1385 spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1386 SPR_NOACCESS, SPR_NOACCESS,
1387 &spr_read_generic, &spr_write_excp_vector,
1388 0x00000000);
1389 spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1390 SPR_NOACCESS, SPR_NOACCESS,
1391 &spr_read_generic, &spr_write_excp_vector,
1392 0x00000000);
1393 spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1394 SPR_NOACCESS, SPR_NOACCESS,
1395 &spr_read_generic, &spr_write_excp_vector,
1396 0x00000000);
1397 spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1398 SPR_NOACCESS, SPR_NOACCESS,
1399 &spr_read_generic, &spr_write_excp_vector,
1400 0x00000000);
1401 spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1402 SPR_NOACCESS, SPR_NOACCESS,
1403 &spr_read_generic, &spr_write_excp_vector,
1404 0x00000000);
1405 spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1406 SPR_NOACCESS, SPR_NOACCESS,
1407 &spr_read_generic, &spr_write_excp_vector,
1408 0x00000000);
1409 spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1410 SPR_NOACCESS, SPR_NOACCESS,
1411 &spr_read_generic, &spr_write_excp_vector,
1412 0x00000000);
1413 spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1414 SPR_NOACCESS, SPR_NOACCESS,
1415 &spr_read_generic, &spr_write_excp_vector,
1416 0x00000000);
1417 spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1418 SPR_NOACCESS, SPR_NOACCESS,
1419 &spr_read_generic, &spr_write_excp_vector,
1420 0x00000000);
1421 spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1422 SPR_NOACCESS, SPR_NOACCESS,
1423 &spr_read_generic, &spr_write_excp_vector,
1424 0x00000000);
1425 spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1426 SPR_NOACCESS, SPR_NOACCESS,
1427 &spr_read_generic, &spr_write_excp_vector,
1428 0x00000000);
1429 spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1430 SPR_NOACCESS, SPR_NOACCESS,
1431 &spr_read_generic, &spr_write_excp_vector,
1432 0x00000000);
1433 spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1434 SPR_NOACCESS, SPR_NOACCESS,
1435 &spr_read_generic, &spr_write_excp_vector,
1436 0x00000000);
1437 #if 0
1438 spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1439 SPR_NOACCESS, SPR_NOACCESS,
1440 &spr_read_generic, &spr_write_excp_vector,
1441 0x00000000);
1442 spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1443 SPR_NOACCESS, SPR_NOACCESS,
1444 &spr_read_generic, &spr_write_excp_vector,
1445 0x00000000);
1446 spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1447 SPR_NOACCESS, SPR_NOACCESS,
1448 &spr_read_generic, &spr_write_excp_vector,
1449 0x00000000);
1450 spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1451 SPR_NOACCESS, SPR_NOACCESS,
1452 &spr_read_generic, &spr_write_excp_vector,
1453 0x00000000);
1454 spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1455 SPR_NOACCESS, SPR_NOACCESS,
1456 &spr_read_generic, &spr_write_excp_vector,
1457 0x00000000);
1458 spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1459 SPR_NOACCESS, SPR_NOACCESS,
1460 &spr_read_generic, &spr_write_excp_vector,
1461 0x00000000);
1462 #endif
1463 spr_register(env, SPR_BOOKE_PID, "PID",
1464 SPR_NOACCESS, SPR_NOACCESS,
1465 &spr_read_generic, &spr_write_generic,
1466 0x00000000);
1467 spr_register(env, SPR_BOOKE_TCR, "TCR",
1468 SPR_NOACCESS, SPR_NOACCESS,
1469 &spr_read_generic, &spr_write_booke_tcr,
1470 0x00000000);
1471 spr_register(env, SPR_BOOKE_TSR, "TSR",
1472 SPR_NOACCESS, SPR_NOACCESS,
1473 &spr_read_generic, &spr_write_booke_tsr,
1474 0x00000000);
1475 /* Timer */
1476 spr_register(env, SPR_DECR, "DECR",
1477 SPR_NOACCESS, SPR_NOACCESS,
1478 &spr_read_decr, &spr_write_decr,
1479 0x00000000);
1480 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1481 SPR_NOACCESS, SPR_NOACCESS,
1482 SPR_NOACCESS, &spr_write_generic,
1483 0x00000000);
1484 /* SPRGs */
1485 spr_register(env, SPR_USPRG0, "USPRG0",
1486 &spr_read_generic, &spr_write_generic,
1487 &spr_read_generic, &spr_write_generic,
1488 0x00000000);
1489 spr_register(env, SPR_SPRG4, "SPRG4",
1490 SPR_NOACCESS, SPR_NOACCESS,
1491 &spr_read_generic, &spr_write_generic,
1492 0x00000000);
1493 spr_register(env, SPR_USPRG4, "USPRG4",
1494 &spr_read_ureg, SPR_NOACCESS,
1495 &spr_read_ureg, SPR_NOACCESS,
1496 0x00000000);
1497 spr_register(env, SPR_SPRG5, "SPRG5",
1498 SPR_NOACCESS, SPR_NOACCESS,
1499 &spr_read_generic, &spr_write_generic,
1500 0x00000000);
1501 spr_register(env, SPR_USPRG5, "USPRG5",
1502 &spr_read_ureg, SPR_NOACCESS,
1503 &spr_read_ureg, SPR_NOACCESS,
1504 0x00000000);
1505 spr_register(env, SPR_SPRG6, "SPRG6",
1506 SPR_NOACCESS, SPR_NOACCESS,
1507 &spr_read_generic, &spr_write_generic,
1508 0x00000000);
1509 spr_register(env, SPR_USPRG6, "USPRG6",
1510 &spr_read_ureg, SPR_NOACCESS,
1511 &spr_read_ureg, SPR_NOACCESS,
1512 0x00000000);
1513 spr_register(env, SPR_SPRG7, "SPRG7",
1514 SPR_NOACCESS, SPR_NOACCESS,
1515 &spr_read_generic, &spr_write_generic,
1516 0x00000000);
1517 spr_register(env, SPR_USPRG7, "USPRG7",
1518 &spr_read_ureg, SPR_NOACCESS,
1519 &spr_read_ureg, SPR_NOACCESS,
1520 0x00000000);
1521 }
1522
1523 /* FSL storage control registers */
1524 static void gen_spr_BookE_FSL (CPUPPCState *env)
1525 {
1526 #if !defined(CONFIG_USER_ONLY)
1527 /* TLB assist registers */
1528 /* XXX : not implemented */
1529 spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1530 SPR_NOACCESS, SPR_NOACCESS,
1531 &spr_read_generic, &spr_write_generic,
1532 0x00000000);
1533 /* XXX : not implemented */
1534 spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1535 SPR_NOACCESS, SPR_NOACCESS,
1536 &spr_read_generic, &spr_write_generic,
1537 0x00000000);
1538 /* XXX : not implemented */
1539 spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1540 SPR_NOACCESS, SPR_NOACCESS,
1541 &spr_read_generic, &spr_write_generic,
1542 0x00000000);
1543 /* XXX : not implemented */
1544 spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1545 SPR_NOACCESS, SPR_NOACCESS,
1546 &spr_read_generic, &spr_write_generic,
1547 0x00000000);
1548 /* XXX : not implemented */
1549 spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1550 SPR_NOACCESS, SPR_NOACCESS,
1551 &spr_read_generic, &spr_write_generic,
1552 0x00000000);
1553 /* XXX : not implemented */
1554 spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1555 SPR_NOACCESS, SPR_NOACCESS,
1556 &spr_read_generic, &spr_write_generic,
1557 0x00000000);
1558 /* XXX : not implemented */
1559 spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1560 SPR_NOACCESS, SPR_NOACCESS,
1561 &spr_read_generic, &spr_write_generic,
1562 0x00000000);
1563 if (env->nb_pids > 1) {
1564 /* XXX : not implemented */
1565 spr_register(env, SPR_BOOKE_PID1, "PID1",
1566 SPR_NOACCESS, SPR_NOACCESS,
1567 &spr_read_generic, &spr_write_generic,
1568 0x00000000);
1569 }
1570 if (env->nb_pids > 2) {
1571 /* XXX : not implemented */
1572 spr_register(env, SPR_BOOKE_PID2, "PID2",
1573 SPR_NOACCESS, SPR_NOACCESS,
1574 &spr_read_generic, &spr_write_generic,
1575 0x00000000);
1576 }
1577 /* XXX : not implemented */
1578 spr_register(env, SPR_MMUCFG, "MMUCFG",
1579 SPR_NOACCESS, SPR_NOACCESS,
1580 &spr_read_generic, SPR_NOACCESS,
1581 0x00000000); /* TOFIX */
1582 /* XXX : not implemented */
1583 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
1584 SPR_NOACCESS, SPR_NOACCESS,
1585 &spr_read_generic, &spr_write_generic,
1586 0x00000000); /* TOFIX */
1587 switch (env->nb_ways) {
1588 case 4:
1589 /* XXX : not implemented */
1590 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1591 SPR_NOACCESS, SPR_NOACCESS,
1592 &spr_read_generic, SPR_NOACCESS,
1593 0x00000000); /* TOFIX */
1594 /* Fallthru */
1595 case 3:
1596 /* XXX : not implemented */
1597 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1598 SPR_NOACCESS, SPR_NOACCESS,
1599 &spr_read_generic, SPR_NOACCESS,
1600 0x00000000); /* TOFIX */
1601 /* Fallthru */
1602 case 2:
1603 /* XXX : not implemented */
1604 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1605 SPR_NOACCESS, SPR_NOACCESS,
1606 &spr_read_generic, SPR_NOACCESS,
1607 0x00000000); /* TOFIX */
1608 /* Fallthru */
1609 case 1:
1610 /* XXX : not implemented */
1611 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1612 SPR_NOACCESS, SPR_NOACCESS,
1613 &spr_read_generic, SPR_NOACCESS,
1614 0x00000000); /* TOFIX */
1615 /* Fallthru */
1616 case 0:
1617 default:
1618 break;
1619 }
1620 #endif
1621 }
1622
1623 /* SPR specific to PowerPC 440 implementation */
1624 static void gen_spr_440 (CPUPPCState *env)
1625 {
1626 /* Cache control */
1627 /* XXX : not implemented */
1628 spr_register(env, SPR_440_DNV0, "DNV0",
1629 SPR_NOACCESS, SPR_NOACCESS,
1630 &spr_read_generic, &spr_write_generic,
1631 0x00000000);
1632 /* XXX : not implemented */
1633 spr_register(env, SPR_440_DNV1, "DNV1",
1634 SPR_NOACCESS, SPR_NOACCESS,
1635 &spr_read_generic, &spr_write_generic,
1636 0x00000000);
1637 /* XXX : not implemented */
1638 spr_register(env, SPR_440_DNV2, "DNV2",
1639 SPR_NOACCESS, SPR_NOACCESS,
1640 &spr_read_generic, &spr_write_generic,
1641 0x00000000);
1642 /* XXX : not implemented */
1643 spr_register(env, SPR_440_DNV3, "DNV3",
1644 SPR_NOACCESS, SPR_NOACCESS,
1645 &spr_read_generic, &spr_write_generic,
1646 0x00000000);
1647 /* XXX : not implemented */
1648 spr_register(env, SPR_440_DTV0, "DTV0",
1649 SPR_NOACCESS, SPR_NOACCESS,
1650 &spr_read_generic, &spr_write_generic,
1651 0x00000000);
1652 /* XXX : not implemented */
1653 spr_register(env, SPR_440_DTV1, "DTV1",
1654 SPR_NOACCESS, SPR_NOACCESS,
1655 &spr_read_generic, &spr_write_generic,
1656 0x00000000);
1657 /* XXX : not implemented */
1658 spr_register(env, SPR_440_DTV2, "DTV2",
1659 SPR_NOACCESS, SPR_NOACCESS,
1660 &spr_read_generic, &spr_write_generic,
1661 0x00000000);
1662 /* XXX : not implemented */
1663 spr_register(env, SPR_440_DTV3, "DTV3",
1664 SPR_NOACCESS, SPR_NOACCESS,
1665 &spr_read_generic, &spr_write_generic,
1666 0x00000000);
1667 /* XXX : not implemented */
1668 spr_register(env, SPR_440_DVLIM, "DVLIM",
1669 SPR_NOACCESS, SPR_NOACCESS,
1670 &spr_read_generic, &spr_write_generic,
1671 0x00000000);
1672 /* XXX : not implemented */
1673 spr_register(env, SPR_440_INV0, "INV0",
1674 SPR_NOACCESS, SPR_NOACCESS,
1675 &spr_read_generic, &spr_write_generic,
1676 0x00000000);
1677 /* XXX : not implemented */
1678 spr_register(env, SPR_440_INV1, "INV1",
1679 SPR_NOACCESS, SPR_NOACCESS,
1680 &spr_read_generic, &spr_write_generic,
1681 0x00000000);
1682 /* XXX : not implemented */
1683 spr_register(env, SPR_440_INV2, "INV2",
1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, &spr_write_generic,
1686 0x00000000);
1687 /* XXX : not implemented */
1688 spr_register(env, SPR_440_INV3, "INV3",
1689 SPR_NOACCESS, SPR_NOACCESS,
1690 &spr_read_generic, &spr_write_generic,
1691 0x00000000);
1692 /* XXX : not implemented */
1693 spr_register(env, SPR_440_ITV0, "ITV0",
1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, &spr_write_generic,
1696 0x00000000);
1697 /* XXX : not implemented */
1698 spr_register(env, SPR_440_ITV1, "ITV1",
1699 SPR_NOACCESS, SPR_NOACCESS,
1700 &spr_read_generic, &spr_write_generic,
1701 0x00000000);
1702 /* XXX : not implemented */
1703 spr_register(env, SPR_440_ITV2, "ITV2",
1704 SPR_NOACCESS, SPR_NOACCESS,
1705 &spr_read_generic, &spr_write_generic,
1706 0x00000000);
1707 /* XXX : not implemented */
1708 spr_register(env, SPR_440_ITV3, "ITV3",
1709 SPR_NOACCESS, SPR_NOACCESS,
1710 &spr_read_generic, &spr_write_generic,
1711 0x00000000);
1712 /* XXX : not implemented */
1713 spr_register(env, SPR_440_IVLIM, "IVLIM",
1714 SPR_NOACCESS, SPR_NOACCESS,
1715 &spr_read_generic, &spr_write_generic,
1716 0x00000000);
1717 /* Cache debug */
1718 /* XXX : not implemented */
1719 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1720 SPR_NOACCESS, SPR_NOACCESS,
1721 &spr_read_generic, SPR_NOACCESS,
1722 0x00000000);
1723 /* XXX : not implemented */
1724 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1725 SPR_NOACCESS, SPR_NOACCESS,
1726 &spr_read_generic, SPR_NOACCESS,
1727 0x00000000);
1728 /* XXX : not implemented */
1729 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1730 SPR_NOACCESS, SPR_NOACCESS,
1731 &spr_read_generic, SPR_NOACCESS,
1732 0x00000000);
1733 /* XXX : not implemented */
1734 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1735 SPR_NOACCESS, SPR_NOACCESS,
1736 &spr_read_generic, SPR_NOACCESS,
1737 0x00000000);
1738 /* XXX : not implemented */
1739 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1740 SPR_NOACCESS, SPR_NOACCESS,
1741 &spr_read_generic, SPR_NOACCESS,
1742 0x00000000);
1743 /* XXX : not implemented */
1744 spr_register(env, SPR_440_DBDR, "DBDR",
1745 SPR_NOACCESS, SPR_NOACCESS,
1746 &spr_read_generic, &spr_write_generic,
1747 0x00000000);
1748 /* Processor control */
1749 spr_register(env, SPR_4xx_CCR0, "CCR0",
1750 SPR_NOACCESS, SPR_NOACCESS,
1751 &spr_read_generic, &spr_write_generic,
1752 0x00000000);
1753 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, SPR_NOACCESS,
1756 0x00000000);
1757 /* Storage control */
1758 spr_register(env, SPR_440_MMUCR, "MMUCR",
1759 SPR_NOACCESS, SPR_NOACCESS,
1760 &spr_read_generic, &spr_write_generic,
1761 0x00000000);
1762 }
1763
1764 /* SPR shared between PowerPC 40x implementations */
1765 static void gen_spr_40x (CPUPPCState *env)
1766 {
1767 /* Cache */
1768 /* not emulated, as Qemu do not emulate caches */
1769 spr_register(env, SPR_40x_DCCR, "DCCR",
1770 SPR_NOACCESS, SPR_NOACCESS,
1771 &spr_read_generic, &spr_write_generic,
1772 0x00000000);
1773 /* not emulated, as Qemu do not emulate caches */
1774 spr_register(env, SPR_40x_ICCR, "ICCR",
1775 SPR_NOACCESS, SPR_NOACCESS,
1776 &spr_read_generic, &spr_write_generic,
1777 0x00000000);
1778 /* not emulated, as Qemu do not emulate caches */
1779 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1780 SPR_NOACCESS, SPR_NOACCESS,
1781 &spr_read_generic, SPR_NOACCESS,
1782 0x00000000);
1783 /* Exception */
1784 spr_register(env, SPR_40x_DEAR, "DEAR",
1785 SPR_NOACCESS, SPR_NOACCESS,
1786 &spr_read_generic, &spr_write_generic,
1787 0x00000000);
1788 spr_register(env, SPR_40x_ESR, "ESR",
1789 SPR_NOACCESS, SPR_NOACCESS,
1790 &spr_read_generic, &spr_write_generic,
1791 0x00000000);
1792 spr_register(env, SPR_40x_EVPR, "EVPR",
1793 SPR_NOACCESS, SPR_NOACCESS,
1794 &spr_read_generic, &spr_write_excp_prefix,
1795 0x00000000);
1796 spr_register(env, SPR_40x_SRR2, "SRR2",
1797 &spr_read_generic, &spr_write_generic,
1798 &spr_read_generic, &spr_write_generic,
1799 0x00000000);
1800 spr_register(env, SPR_40x_SRR3, "SRR3",
1801 &spr_read_generic, &spr_write_generic,
1802 &spr_read_generic, &spr_write_generic,
1803 0x00000000);
1804 /* Timers */
1805 spr_register(env, SPR_40x_PIT, "PIT",
1806 SPR_NOACCESS, SPR_NOACCESS,
1807 &spr_read_40x_pit, &spr_write_40x_pit,
1808 0x00000000);
1809 spr_register(env, SPR_40x_TCR, "TCR",
1810 SPR_NOACCESS, SPR_NOACCESS,
1811 &spr_read_generic, &spr_write_booke_tcr,
1812 0x00000000);
1813 spr_register(env, SPR_40x_TSR, "TSR",
1814 SPR_NOACCESS, SPR_NOACCESS,
1815 &spr_read_generic, &spr_write_booke_tsr,
1816 0x00000000);
1817 }
1818
1819 /* SPR specific to PowerPC 405 implementation */
1820 static void gen_spr_405 (CPUPPCState *env)
1821 {
1822 /* MMU */
1823 spr_register(env, SPR_40x_PID, "PID",
1824 SPR_NOACCESS, SPR_NOACCESS,
1825 &spr_read_generic, &spr_write_generic,
1826 0x00000000);
1827 spr_register(env, SPR_4xx_CCR0, "CCR0",
1828 SPR_NOACCESS, SPR_NOACCESS,
1829 &spr_read_generic, &spr_write_generic,
1830 0x00700000);
1831 /* Debug interface */
1832 /* XXX : not implemented */
1833 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1834 SPR_NOACCESS, SPR_NOACCESS,
1835 &spr_read_generic, &spr_write_40x_dbcr0,
1836 0x00000000);
1837 /* XXX : not implemented */
1838 spr_register(env, SPR_405_DBCR1, "DBCR1",
1839 SPR_NOACCESS, SPR_NOACCESS,
1840 &spr_read_generic, &spr_write_generic,
1841 0x00000000);
1842 /* XXX : not implemented */
1843 spr_register(env, SPR_40x_DBSR, "DBSR",
1844 SPR_NOACCESS, SPR_NOACCESS,
1845 &spr_read_generic, &spr_write_clear,
1846 /* Last reset was system reset */
1847 0x00000300);
1848 /* XXX : not implemented */
1849 spr_register(env, SPR_40x_DAC1, "DAC1",
1850 SPR_NOACCESS, SPR_NOACCESS,
1851 &spr_read_generic, &spr_write_generic,
1852 0x00000000);
1853 spr_register(env, SPR_40x_DAC2, "DAC2",
1854 SPR_NOACCESS, SPR_NOACCESS,
1855 &spr_read_generic, &spr_write_generic,
1856 0x00000000);
1857 /* XXX : not implemented */
1858 spr_register(env, SPR_405_DVC1, "DVC1",
1859 SPR_NOACCESS, SPR_NOACCESS,
1860 &spr_read_generic, &spr_write_generic,
1861 0x00000000);
1862 /* XXX : not implemented */
1863 spr_register(env, SPR_405_DVC2, "DVC2",
1864 SPR_NOACCESS, SPR_NOACCESS,
1865 &spr_read_generic, &spr_write_generic,
1866 0x00000000);
1867 /* XXX : not implemented */
1868 spr_register(env, SPR_40x_IAC1, "IAC1",
1869 SPR_NOACCESS, SPR_NOACCESS,
1870 &spr_read_generic, &spr_write_generic,
1871 0x00000000);
1872 spr_register(env, SPR_40x_IAC2, "IAC2",
1873 SPR_NOACCESS, SPR_NOACCESS,
1874 &spr_read_generic, &spr_write_generic,
1875 0x00000000);
1876 /* XXX : not implemented */
1877 spr_register(env, SPR_405_IAC3, "IAC3",
1878 SPR_NOACCESS, SPR_NOACCESS,
1879 &spr_read_generic, &spr_write_generic,
1880 0x00000000);
1881 /* XXX : not implemented */
1882 spr_register(env, SPR_405_IAC4, "IAC4",
1883 SPR_NOACCESS, SPR_NOACCESS,
1884 &spr_read_generic, &spr_write_generic,
1885 0x00000000);
1886 /* Storage control */
1887 /* XXX: TODO: not implemented */
1888 spr_register(env, SPR_405_SLER, "SLER",
1889 SPR_NOACCESS, SPR_NOACCESS,
1890 &spr_read_generic, &spr_write_40x_sler,
1891 0x00000000);
1892 spr_register(env, SPR_40x_ZPR, "ZPR",
1893 SPR_NOACCESS, SPR_NOACCESS,
1894 &spr_read_generic, &spr_write_generic,
1895 0x00000000);
1896 /* XXX : not implemented */
1897 spr_register(env, SPR_405_SU0R, "SU0R",
1898 SPR_NOACCESS, SPR_NOACCESS,
1899 &spr_read_generic, &spr_write_generic,
1900 0x00000000);
1901 /* SPRG */
1902 spr_register(env, SPR_USPRG0, "USPRG0",
1903 &spr_read_ureg, SPR_NOACCESS,
1904 &spr_read_ureg, SPR_NOACCESS,
1905 0x00000000);
1906 spr_register(env, SPR_SPRG4, "SPRG4",
1907 SPR_NOACCESS, SPR_NOACCESS,
1908 &spr_read_generic, &spr_write_generic,
1909 0x00000000);
1910 spr_register(env, SPR_USPRG4, "USPRG4",
1911 &spr_read_ureg, SPR_NOACCESS,
1912 &spr_read_ureg, SPR_NOACCESS,
1913 0x00000000);
1914 spr_register(env, SPR_SPRG5, "SPRG5",
1915 SPR_NOACCESS, SPR_NOACCESS,
1916 spr_read_generic, &spr_write_generic,
1917 0x00000000);
1918 spr_register(env, SPR_USPRG5, "USPRG5",
1919 &spr_read_ureg, SPR_NOACCESS,
1920 &spr_read_ureg, SPR_NOACCESS,
1921 0x00000000);
1922 spr_register(env, SPR_SPRG6, "SPRG6",
1923 SPR_NOACCESS, SPR_NOACCESS,
1924 spr_read_generic, &spr_write_generic,
1925 0x00000000);
1926 spr_register(env, SPR_USPRG6, "USPRG6",
1927 &spr_read_ureg, SPR_NOACCESS,
1928 &spr_read_ureg, SPR_NOACCESS,
1929 0x00000000);
1930 spr_register(env, SPR_SPRG7, "SPRG7",
1931 SPR_NOACCESS, SPR_NOACCESS,
1932 spr_read_generic, &spr_write_generic,
1933 0x00000000);
1934 spr_register(env, SPR_USPRG7, "USPRG7",
1935 &spr_read_ureg, SPR_NOACCESS,
1936 &spr_read_ureg, SPR_NOACCESS,
1937 0x00000000);
1938 }
1939
1940 /* SPR shared between PowerPC 401 & 403 implementations */
1941 static void gen_spr_401_403 (CPUPPCState *env)
1942 {
1943 /* Time base */
1944 spr_register(env, SPR_403_VTBL, "TBL",
1945 &spr_read_tbl, SPR_NOACCESS,
1946 &spr_read_tbl, SPR_NOACCESS,
1947 0x00000000);
1948 spr_register(env, SPR_403_TBL, "TBL",
1949 SPR_NOACCESS, SPR_NOACCESS,
1950 SPR_NOACCESS, &spr_write_tbl,
1951 0x00000000);
1952 spr_register(env, SPR_403_VTBU, "TBU",
1953 &spr_read_tbu, SPR_NOACCESS,
1954 &spr_read_tbu, SPR_NOACCESS,
1955 0x00000000);
1956 spr_register(env, SPR_403_TBU, "TBU",
1957 SPR_NOACCESS, SPR_NOACCESS,
1958 SPR_NOACCESS, &spr_write_tbu,
1959 0x00000000);
1960 /* Debug */
1961 /* not emulated, as Qemu do not emulate caches */
1962 spr_register(env, SPR_403_CDBCR, "CDBCR",
1963 SPR_NOACCESS, SPR_NOACCESS,
1964 &spr_read_generic, &spr_write_generic,
1965 0x00000000);
1966 }
1967
1968 /* SPR specific to PowerPC 401 implementation */
1969 static void gen_spr_401 (CPUPPCState *env)
1970 {
1971 /* Debug interface */
1972 /* XXX : not implemented */
1973 spr_register(env, SPR_40x_DBCR0, "DBCR",
1974 SPR_NOACCESS, SPR_NOACCESS,
1975 &spr_read_generic, &spr_write_40x_dbcr0,
1976 0x00000000);
1977 /* XXX : not implemented */
1978 spr_register(env, SPR_40x_DBSR, "DBSR",
1979 SPR_NOACCESS, SPR_NOACCESS,
1980 &spr_read_generic, &spr_write_clear,
1981 /* Last reset was system reset */
1982 0x00000300);
1983 /* XXX : not implemented */
1984 spr_register(env, SPR_40x_DAC1, "DAC",
1985 SPR_NOACCESS, SPR_NOACCESS,
1986 &spr_read_generic, &spr_write_generic,
1987 0x00000000);
1988 /* XXX : not implemented */
1989 spr_register(env, SPR_40x_IAC1, "IAC",
1990 SPR_NOACCESS, SPR_NOACCESS,
1991 &spr_read_generic, &spr_write_generic,
1992 0x00000000);
1993 /* Storage control */
1994 /* XXX: TODO: not implemented */
1995 spr_register(env, SPR_405_SLER, "SLER",
1996 SPR_NOACCESS, SPR_NOACCESS,
1997 &spr_read_generic, &spr_write_40x_sler,
1998 0x00000000);
1999 /* not emulated, as Qemu never does speculative access */
2000 spr_register(env, SPR_40x_SGR, "SGR",
2001 SPR_NOACCESS, SPR_NOACCESS,
2002 &spr_read_generic, &spr_write_generic,
2003 0xFFFFFFFF);
2004 /* not emulated, as Qemu do not emulate caches */
2005 spr_register(env, SPR_40x_DCWR, "DCWR",
2006 SPR_NOACCESS, SPR_NOACCESS,
2007 &spr_read_generic, &spr_write_generic,
2008 0x00000000);
2009 }
2010
2011 static void gen_spr_401x2 (CPUPPCState *env)
2012 {
2013 gen_spr_401(env);
2014 spr_register(env, SPR_40x_PID, "PID",
2015 SPR_NOACCESS, SPR_NOACCESS,
2016 &spr_read_generic, &spr_write_generic,
2017 0x00000000);
2018 spr_register(env, SPR_40x_ZPR, "ZPR",
2019 SPR_NOACCESS, SPR_NOACCESS,
2020 &spr_read_generic, &spr_write_generic,
2021 0x00000000);
2022 }
2023
2024 /* SPR specific to PowerPC 403 implementation */
2025 static void gen_spr_403 (CPUPPCState *env)
2026 {
2027 /* Debug interface */
2028 /* XXX : not implemented */
2029 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2030 SPR_NOACCESS, SPR_NOACCESS,
2031 &spr_read_generic, &spr_write_40x_dbcr0,
2032 0x00000000);
2033 /* XXX : not implemented */
2034 spr_register(env, SPR_40x_DBSR, "DBSR",
2035 SPR_NOACCESS, SPR_NOACCESS,
2036 &spr_read_generic, &spr_write_clear,
2037 /* Last reset was system reset */
2038 0x00000300);
2039 /* XXX : not implemented */
2040 spr_register(env, SPR_40x_DAC1, "DAC1",
2041 SPR_NOACCESS, SPR_NOACCESS,
2042 &spr_read_generic, &spr_write_generic,
2043 0x00000000);
2044 /* XXX : not implemented */
2045 spr_register(env, SPR_40x_DAC2, "DAC2",
2046 SPR_NOACCESS, SPR_NOACCESS,
2047 &spr_read_generic, &spr_write_generic,
2048 0x00000000);
2049 /* XXX : not implemented */
2050 spr_register(env, SPR_40x_IAC1, "IAC1",
2051 SPR_NOACCESS, SPR_NOACCESS,
2052 &spr_read_generic, &spr_write_generic,
2053 0x00000000);
2054 /* XXX : not implemented */
2055 spr_register(env, SPR_40x_IAC2, "IAC2",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_generic, &spr_write_generic,
2058 0x00000000);
2059 }
2060
2061 static void gen_spr_403_real (CPUPPCState *env)
2062 {
2063 spr_register(env, SPR_403_PBL1, "PBL1",
2064 SPR_NOACCESS, SPR_NOACCESS,
2065 &spr_read_403_pbr, &spr_write_403_pbr,
2066 0x00000000);
2067 spr_register(env, SPR_403_PBU1, "PBU1",
2068 SPR_NOACCESS, SPR_NOACCESS,
2069 &spr_read_403_pbr, &spr_write_403_pbr,
2070 0x00000000);
2071 spr_register(env, SPR_403_PBL2, "PBL2",
2072 SPR_NOACCESS, SPR_NOACCESS,
2073 &spr_read_403_pbr, &spr_write_403_pbr,
2074 0x00000000);
2075 spr_register(env, SPR_403_PBU2, "PBU2",
2076 SPR_NOACCESS, SPR_NOACCESS,
2077 &spr_read_403_pbr, &spr_write_403_pbr,
2078 0x00000000);
2079 }
2080
2081 static void gen_spr_403_mmu (CPUPPCState *env)
2082 {
2083 /* MMU */
2084 spr_register(env, SPR_40x_PID, "PID",
2085 SPR_NOACCESS, SPR_NOACCESS,
2086 &spr_read_generic, &spr_write_generic,
2087 0x00000000);
2088 spr_register(env, SPR_40x_ZPR, "ZPR",
2089 SPR_NOACCESS, SPR_NOACCESS,
2090 &spr_read_generic, &spr_write_generic,
2091 0x00000000);
2092 }
2093
2094 /* SPR specific to PowerPC compression coprocessor extension */
2095 static void gen_spr_compress (CPUPPCState *env)
2096 {
2097 /* XXX : not implemented */
2098 spr_register(env, SPR_401_SKR, "SKR",
2099 SPR_NOACCESS, SPR_NOACCESS,
2100 &spr_read_generic, &spr_write_generic,
2101 0x00000000);
2102 }
2103
2104 #if defined (TARGET_PPC64)
2105 /* SPR specific to PowerPC 620 */
2106 static void gen_spr_620 (CPUPPCState *env)
2107 {
2108 /* XXX : not implemented */
2109 spr_register(env, SPR_620_PMR0, "PMR0",
2110 SPR_NOACCESS, SPR_NOACCESS,
2111 &spr_read_generic, &spr_write_generic,
2112 0x00000000);
2113 /* XXX : not implemented */
2114 spr_register(env, SPR_620_PMR1, "PMR1",
2115 SPR_NOACCESS, SPR_NOACCESS,
2116 &spr_read_generic, &spr_write_generic,
2117 0x00000000);
2118 /* XXX : not implemented */
2119 spr_register(env, SPR_620_PMR2, "PMR2",
2120 SPR_NOACCESS, SPR_NOACCESS,
2121 &spr_read_generic, &spr_write_generic,
2122 0x00000000);
2123 /* XXX : not implemented */
2124 spr_register(env, SPR_620_PMR3, "PMR3",
2125 SPR_NOACCESS, SPR_NOACCESS,
2126 &spr_read_generic, &spr_write_generic,
2127 0x00000000);
2128 /* XXX : not implemented */
2129 spr_register(env, SPR_620_PMR4, "PMR4",
2130 SPR_NOACCESS, SPR_NOACCESS,
2131 &spr_read_generic, &spr_write_generic,
2132 0x00000000);
2133 /* XXX : not implemented */
2134 spr_register(env, SPR_620_PMR5, "PMR5",
2135 SPR_NOACCESS, SPR_NOACCESS,
2136 &spr_read_generic, &spr_write_generic,
2137 0x00000000);
2138 /* XXX : not implemented */
2139 spr_register(env, SPR_620_PMR6, "PMR6",
2140 SPR_NOACCESS, SPR_NOACCESS,
2141 &spr_read_generic, &spr_write_generic,
2142 0x00000000);
2143 /* XXX : not implemented */
2144 spr_register(env, SPR_620_PMR7, "PMR7",
2145 SPR_NOACCESS, SPR_NOACCESS,
2146 &spr_read_generic, &spr_write_generic,
2147 0x00000000);
2148 /* XXX : not implemented */
2149 spr_register(env, SPR_620_PMR8, "PMR8",
2150 SPR_NOACCESS, SPR_NOACCESS,
2151 &spr_read_generic, &spr_write_generic,
2152 0x00000000);
2153 /* XXX : not implemented */
2154 spr_register(env, SPR_620_PMR9, "PMR9",
2155 SPR_NOACCESS, SPR_NOACCESS,
2156 &spr_read_generic, &spr_write_generic,
2157 0x00000000);
2158 /* XXX : not implemented */
2159 spr_register(env, SPR_620_PMRA, "PMR10",
2160 SPR_NOACCESS, SPR_NOACCESS,
2161 &spr_read_generic, &spr_write_generic,
2162 0x00000000);
2163 /* XXX : not implemented */
2164 spr_register(env, SPR_620_PMRB, "PMR11",
2165 SPR_NOACCESS, SPR_NOACCESS,
2166 &spr_read_generic, &spr_write_generic,
2167 0x00000000);
2168 /* XXX : not implemented */
2169 spr_register(env, SPR_620_PMRC, "PMR12",
2170 SPR_NOACCESS, SPR_NOACCESS,
2171 &spr_read_generic, &spr_write_generic,
2172 0x00000000);
2173 /* XXX : not implemented */
2174 spr_register(env, SPR_620_PMRD, "PMR13",
2175 SPR_NOACCESS, SPR_NOACCESS,
2176 &spr_read_generic, &spr_write_generic,
2177 0x00000000);
2178 /* XXX : not implemented */
2179 spr_register(env, SPR_620_PMRE, "PMR14",
2180 SPR_NOACCESS, SPR_NOACCESS,
2181 &spr_read_generic, &spr_write_generic,
2182 0x00000000);
2183 /* XXX : not implemented */
2184 spr_register(env, SPR_620_PMRF, "PMR15",
2185 SPR_NOACCESS, SPR_NOACCESS,
2186 &spr_read_generic, &spr_write_generic,
2187 0x00000000);
2188 /* XXX : not implemented */
2189 spr_register(env, SPR_620_HID8, "HID8",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 &spr_read_generic, &spr_write_generic,
2192 0x00000000);
2193 /* XXX : not implemented */
2194 spr_register(env, SPR_620_HID9, "HID9",
2195 SPR_NOACCESS, SPR_NOACCESS,
2196 &spr_read_generic, &spr_write_generic,
2197 0x00000000);
2198 }
2199 #endif /* defined (TARGET_PPC64) */
2200
2201 // XXX: TODO
2202 /*
2203 * AMR => SPR 29 (Power 2.04)
2204 * CTRL => SPR 136 (Power 2.04)
2205 * CTRL => SPR 152 (Power 2.04)
2206 * SCOMC => SPR 276 (64 bits ?)
2207 * SCOMD => SPR 277 (64 bits ?)
2208 * TBU40 => SPR 286 (Power 2.04 hypv)
2209 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2210 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2211 * HDSISR => SPR 306 (Power 2.04 hypv)
2212 * HDAR => SPR 307 (Power 2.04 hypv)
2213 * PURR => SPR 309 (Power 2.04 hypv)
2214 * HDEC => SPR 310 (Power 2.04 hypv)
2215 * HIOR => SPR 311 (hypv)
2216 * RMOR => SPR 312 (970)
2217 * HRMOR => SPR 313 (Power 2.04 hypv)
2218 * HSRR0 => SPR 314 (Power 2.04 hypv)
2219 * HSRR1 => SPR 315 (Power 2.04 hypv)
2220 * LPCR => SPR 316 (970)
2221 * LPIDR => SPR 317 (970)
2222 * SPEFSCR => SPR 512 (Power 2.04 emb)
2223 * EPR => SPR 702 (Power 2.04 emb)
2224 * perf => 768-783 (Power 2.04)
2225 * perf => 784-799 (Power 2.04)
2226 * PPR => SPR 896 (Power 2.04)
2227 * EPLC => SPR 947 (Power 2.04 emb)
2228 * EPSC => SPR 948 (Power 2.04 emb)
2229 * DABRX => 1015 (Power 2.04 hypv)
2230 * FPECR => SPR 1022 (?)
2231 * ... and more (thermal management, performance counters, ...)
2232 */
2233
2234 /*****************************************************************************/
2235 /* Exception vectors models */
2236 static void init_excp_4xx_real (CPUPPCState *env)
2237 {
2238 #if !defined(CONFIG_USER_ONLY)
2239 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2240 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2241 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2242 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2243 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2244 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2245 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2246 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2247 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2248 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2249 env->excp_prefix = 0x00000000UL;
2250 env->ivor_mask = 0x0000FFF0UL;
2251 env->ivpr_mask = 0xFFFF0000UL;
2252 /* Hardware reset vector */
2253 env->hreset_vector = 0xFFFFFFFCUL;
2254 #endif
2255 }
2256
2257 static void init_excp_4xx_softmmu (CPUPPCState *env)
2258 {
2259 #if !defined(CONFIG_USER_ONLY)
2260 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2261 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2262 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2263 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2264 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2265 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2266 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2267 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2268 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2269 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2270 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2271 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2272 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2273 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2274 env->excp_prefix = 0x00000000UL;
2275 env->ivor_mask = 0x0000FFF0UL;
2276 env->ivpr_mask = 0xFFFF0000UL;
2277 /* Hardware reset vector */
2278 env->hreset_vector = 0xFFFFFFFCUL;
2279 #endif
2280 }
2281
2282 static void init_excp_BookE (CPUPPCState *env)
2283 {
2284 #if !defined(CONFIG_USER_ONLY)
2285 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2286 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2287 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2288 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2289 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2290 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2291 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2292 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2293 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2294 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2295 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2296 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2297 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2298 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2299 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2300 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2301 env->excp_prefix = 0x00000000UL;
2302 env->ivor_mask = 0x0000FFE0UL;
2303 env->ivpr_mask = 0xFFFF0000UL;
2304 /* Hardware reset vector */
2305 env->hreset_vector = 0xFFFFFFFCUL;
2306 #endif
2307 }
2308
2309 static void init_excp_601 (CPUPPCState *env)
2310 {
2311 #if !defined(CONFIG_USER_ONLY)
2312 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2313 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2314 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2315 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2316 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2317 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2318 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2319 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2320 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2321 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2322 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2323 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2324 env->excp_prefix = 0xFFF00000UL;
2325 /* Hardware reset vector */
2326 env->hreset_vector = 0x00000100UL;
2327 #endif
2328 }
2329
2330 static void init_excp_602 (CPUPPCState *env)
2331 {
2332 #if !defined(CONFIG_USER_ONLY)
2333 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2334 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2335 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2336 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2337 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2338 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2339 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2340 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2341 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2342 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2343 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2344 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2345 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2346 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2347 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2348 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2349 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2350 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2351 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2352 env->excp_prefix = 0xFFF00000UL;
2353 /* Hardware reset vector */
2354 env->hreset_vector = 0xFFFFFFFCUL;
2355 #endif
2356 }
2357
2358 static void init_excp_603 (CPUPPCState *env)
2359 {
2360 #if !defined(CONFIG_USER_ONLY)
2361 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2362 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2363 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2364 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2365 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2366 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2367 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2368 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2369 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2370 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2371 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2372 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2373 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2374 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2375 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2376 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2377 env->excp_prefix = 0x00000000UL;
2378 /* Hardware reset vector */
2379 env->hreset_vector = 0xFFFFFFFCUL;
2380 #endif
2381 }
2382
2383 static void init_excp_G2 (CPUPPCState *env)
2384 {
2385 #if !defined(CONFIG_USER_ONLY)
2386 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2387 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2388 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2389 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2390 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2391 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2392 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2393 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2394 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2395 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2396 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2397 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2398 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2399 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2400 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2401 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2402 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2403 env->excp_prefix = 0x00000000UL;
2404 /* Hardware reset vector */
2405 env->hreset_vector = 0xFFFFFFFCUL;
2406 #endif
2407 }
2408
2409 static void init_excp_604 (CPUPPCState *env)
2410 {
2411 #if !defined(CONFIG_USER_ONLY)
2412 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2413 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2414 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2415 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2416 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2417 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2418 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2419 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2420 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2421 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2422 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2423 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2424 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2425 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2426 env->excp_prefix = 0x00000000UL;
2427 /* Hardware reset vector */
2428 env->hreset_vector = 0xFFFFFFFCUL;
2429 #endif
2430 }
2431
2432 #if defined(TARGET_PPC64)
2433 static void init_excp_620 (CPUPPCState *env)
2434 {
2435 #if !defined(CONFIG_USER_ONLY)
2436 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2437 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2438 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2439 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2440 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2441 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2442 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2443 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2444 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2445 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2446 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2447 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2448 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2449 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2450 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2451 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2452 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2453 env->excp_prefix = 0xFFF00000UL;
2454 /* Hardware reset vector */
2455 env->hreset_vector = 0x0000000000000100ULL;
2456 #endif
2457 }
2458 #endif /* defined(TARGET_PPC64) */
2459
2460 static void init_excp_7x0 (CPUPPCState *env)
2461 {
2462 #if !defined(CONFIG_USER_ONLY)
2463 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2464 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2465 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2466 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2467 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2468 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2469 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2470 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2471 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2472 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2473 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2474 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2475 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2476 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2477 env->excp_prefix = 0x00000000UL;
2478 /* Hardware reset vector */
2479 env->hreset_vector = 0xFFFFFFFCUL;
2480 #endif
2481 }
2482
2483 static void init_excp_750FX (CPUPPCState *env)
2484 {
2485 #if !defined(CONFIG_USER_ONLY)
2486 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2487 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2488 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2489 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2490 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2491 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2492 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2493 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2494 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2495 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2496 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2497 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2498 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2499 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2500 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2501 env->excp_prefix = 0x00000000UL;
2502 /* Hardware reset vector */
2503 env->hreset_vector = 0xFFFFFFFCUL;
2504 #endif
2505 }
2506
2507 /* XXX: Check if this is correct */
2508 static void init_excp_7x5 (CPUPPCState *env)
2509 {
2510 #if !defined(CONFIG_USER_ONLY)
2511 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2512 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2513 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2514 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2515 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2516 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2517 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2518 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2519 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2520 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2521 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2522 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2523 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2524 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2525 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2526 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2527 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2528 env->excp_prefix = 0x00000000UL;
2529 /* Hardware reset vector */
2530 env->hreset_vector = 0xFFFFFFFCUL;
2531 #endif
2532 }
2533
2534 static void init_excp_7400 (CPUPPCState *env)
2535 {
2536 #if !defined(CONFIG_USER_ONLY)
2537 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2538 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2539 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2540 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2541 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2542 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2543 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2544 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2545 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2546 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2547 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2548 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2549 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2550 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2551 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2552 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2553 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2554 env->excp_prefix = 0x00000000UL;
2555 /* Hardware reset vector */
2556 env->hreset_vector = 0xFFFFFFFCUL;
2557 #endif
2558 }
2559
2560 static void init_excp_7450 (CPUPPCState *env)
2561 {
2562 #if !defined(CONFIG_USER_ONLY)
2563 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2564 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2565 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2566 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2567 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2568 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2569 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2570 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2571 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2572 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2573 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2574 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2575 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2576 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2577 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2578 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2579 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2580 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2581 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2582 env->excp_prefix = 0x00000000UL;
2583 /* Hardware reset vector */
2584 env->hreset_vector = 0xFFFFFFFCUL;
2585 #endif
2586 }
2587
2588 #if defined (TARGET_PPC64)
2589 static void init_excp_970 (CPUPPCState *env)
2590 {
2591 #if !defined(CONFIG_USER_ONLY)
2592 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2593 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2594 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2595 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2596 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2597 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2598 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2599 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2600 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2601 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2602 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2603 #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2604 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2605 #endif
2606 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2607 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2608 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2609 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2610 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2611 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2612 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2613 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2614 env->excp_prefix = 0x00000000FFF00000ULL;
2615 /* Hardware reset vector */
2616 env->hreset_vector = 0x0000000000000100ULL;
2617 #endif
2618 }
2619 #endif
2620
2621 /*****************************************************************************/
2622 /* Power management enable checks */
2623 static int check_pow_none (CPUPPCState *env)
2624 {
2625 return 0;
2626 }
2627
2628 static int check_pow_nocheck (CPUPPCState *env)
2629 {
2630 return 1;
2631 }
2632
2633 static int check_pow_hid0 (CPUPPCState *env)
2634 {
2635 if (env->spr[SPR_HID0] & 0x00E00000)
2636 return 1;
2637
2638 return 0;
2639 }
2640
2641 /*****************************************************************************/
2642 /* PowerPC implementations definitions */
2643
2644 /* PowerPC 40x instruction set */
2645 #define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_CACHE_DCBZ | PPC_EMB_COMMON)
2646
2647 /* PowerPC 401 */
2648 #define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \
2649 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2650 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2651 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
2652 #define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx)
2653 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
2654 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
2655 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
2656 #define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2657 #define check_pow_401 check_pow_nocheck
2658
2659 static void init_proc_401 (CPUPPCState *env)
2660 {
2661 gen_spr_40x(env);
2662 gen_spr_401_403(env);
2663 gen_spr_401(env);
2664 init_excp_4xx_real(env);
2665 env->dcache_line_size = 32;
2666 env->icache_line_size = 32;
2667 /* Allocate hardware IRQ controller */
2668 ppc40x_irq_init(env);
2669 }
2670
2671 /* PowerPC 401x2 */
2672 #define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | \
2673 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2674 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2675 PPC_CACHE_DCBA | PPC_MFTB | \
2676 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2677 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
2678 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
2679 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
2680 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
2681 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
2682 #define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2683 #define check_pow_401x2 check_pow_nocheck
2684
2685 static void init_proc_401x2 (CPUPPCState *env)
2686 {
2687 gen_spr_40x(env);
2688 gen_spr_401_403(env);
2689 gen_spr_401x2(env);
2690 gen_spr_compress(env);
2691 /* Memory management */
2692 #if !defined(CONFIG_USER_ONLY)
2693 env->nb_tlb = 64;
2694 env->nb_ways = 1;
2695 env->id_tlbs = 0;
2696 #endif
2697 init_excp_4xx_softmmu(env);
2698 env->dcache_line_size = 32;
2699 env->icache_line_size = 32;
2700 /* Allocate hardware IRQ controller */
2701 ppc40x_irq_init(env);
2702 }
2703
2704 /* PowerPC 401x3 */
2705 #define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \
2706 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2707 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2708 PPC_CACHE_DCBA | PPC_MFTB | \
2709 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2710 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
2711 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
2712 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
2713 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
2714 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
2715 #define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2716 #define check_pow_401x3 check_pow_nocheck
2717
2718 __attribute__ (( unused ))
2719 static void init_proc_401x3 (CPUPPCState *env)
2720 {
2721 gen_spr_40x(env);
2722 gen_spr_401_403(env);
2723 gen_spr_401(env);
2724 gen_spr_401x2(env);
2725 gen_spr_compress(env);
2726 init_excp_4xx_softmmu(env);
2727 env->dcache_line_size = 32;
2728 env->icache_line_size = 32;
2729 /* Allocate hardware IRQ controller */
2730 ppc40x_irq_init(env);
2731 }
2732
2733 /* IOP480 */
2734 #define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \
2735 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2736 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2737 PPC_CACHE_DCBA | \
2738 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2739 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
2740 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
2741 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
2742 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
2743 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
2744 #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2745 #define check_pow_IOP480 check_pow_nocheck
2746
2747 static void init_proc_IOP480 (CPUPPCState *env)
2748 {
2749 gen_spr_40x(env);
2750 gen_spr_401_403(env);
2751 gen_spr_401x2(env);
2752 gen_spr_compress(env);
2753 /* Memory management */
2754 #if !defined(CONFIG_USER_ONLY)
2755 env->nb_tlb = 64;
2756 env->nb_ways = 1;
2757 env->id_tlbs = 0;
2758 #endif
2759 init_excp_4xx_softmmu(env);
2760 env->dcache_line_size = 32;
2761 env->icache_line_size = 32;
2762 /* Allocate hardware IRQ controller */
2763 ppc40x_irq_init(env);
2764 }
2765
2766 /* PowerPC 403 */
2767 #define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | \
2768 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2769 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2770 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
2771 #define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx)
2772 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
2773 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
2774 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
2775 #define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2776 #define check_pow_403 check_pow_nocheck
2777
2778 static void init_proc_403 (CPUPPCState *env)
2779 {
2780 gen_spr_40x(env);
2781 gen_spr_401_403(env);
2782 gen_spr_403(env);
2783 gen_spr_403_real(env);
2784 init_excp_4xx_real(env);
2785 env->dcache_line_size = 32;
2786 env->icache_line_size = 32;
2787 /* Allocate hardware IRQ controller */
2788 ppc40x_irq_init(env);
2789 #if !defined(CONFIG_USER_ONLY)
2790 /* Hardware reset vector */
2791 env->hreset_vector = 0xFFFFFFFCUL;
2792 #endif
2793 }
2794
2795 /* PowerPC 403 GCX */
2796 #define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | \
2797 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2798 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2799 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2800 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
2801 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
2802 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
2803 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
2804 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
2805 #define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2806 #define check_pow_403GCX check_pow_nocheck
2807
2808 static void init_proc_403GCX (CPUPPCState *env)
2809 {
2810 gen_spr_40x(env);
2811 gen_spr_401_403(env);
2812 gen_spr_403(env);
2813 gen_spr_403_real(env);
2814 gen_spr_403_mmu(env);
2815 /* Bus access control */
2816 /* not emulated, as Qemu never does speculative access */
2817 spr_register(env, SPR_40x_SGR, "SGR",
2818 SPR_NOACCESS, SPR_NOACCESS,
2819 &spr_read_generic, &spr_write_generic,
2820 0xFFFFFFFF);
2821 /* not emulated, as Qemu do not emulate caches */
2822 spr_register(env, SPR_40x_DCWR, "DCWR",
2823 SPR_NOACCESS, SPR_NOACCESS,
2824 &spr_read_generic, &spr_write_generic,
2825 0x00000000);
2826 /* Memory management */
2827 #if !defined(CONFIG_USER_ONLY)
2828 env->nb_tlb = 64;
2829 env->nb_ways = 1;
2830 env->id_tlbs = 0;
2831 #endif
2832 init_excp_4xx_softmmu(env);
2833 env->dcache_line_size = 32;
2834 env->icache_line_size = 32;
2835 /* Allocate hardware IRQ controller */
2836 ppc40x_irq_init(env);
2837 }
2838
2839 /* PowerPC 405 */
2840 #define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_MFTB | \
2841 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2842 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2843 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
2844 PPC_405_MAC)
2845 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
2846 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
2847 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
2848 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
2849 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
2850 #define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2851 POWERPC_FLAG_DE)
2852 #define check_pow_405 check_pow_nocheck
2853
2854 static void init_proc_405 (CPUPPCState *env)
2855 {
2856 /* Time base */
2857 gen_tbl(env);
2858 gen_spr_40x(env);
2859 gen_spr_405(env);
2860 /* Bus access control */
2861 /* not emulated, as Qemu never does speculative access */
2862 spr_register(env, SPR_40x_SGR, "SGR",
2863 SPR_NOACCESS, SPR_NOACCESS,
2864 &spr_read_generic, &spr_write_generic,
2865 0xFFFFFFFF);
2866 /* not emulated, as Qemu do not emulate caches */
2867 spr_register(env, SPR_40x_DCWR, "DCWR",
2868 SPR_NOACCESS, SPR_NOACCESS,
2869 &spr_read_generic, &spr_write_generic,
2870 0x00000000);
2871 /* Memory management */
2872 #if !defined(CONFIG_USER_ONLY)
2873 env->nb_tlb = 64;
2874 env->nb_ways = 1;
2875 env->id_tlbs = 0;
2876 #endif
2877 init_excp_4xx_softmmu(env);
2878 env->dcache_line_size = 32;
2879 env->icache_line_size = 32;
2880 /* Allocate hardware IRQ controller */
2881 ppc40x_irq_init(env);
2882 }
2883
2884 /* PowerPC 440 EP */
2885 #define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | \
2886 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2887 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2888 PPC_440_SPEC | PPC_RFMCI)
2889 #define POWERPC_MSRM_440EP (0x000000000006D630ULL)
2890 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
2891 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
2892 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
2893 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
2894 #define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2895 POWERPC_FLAG_DE)
2896 #define check_pow_440EP check_pow_nocheck
2897
2898 static void init_proc_440EP (CPUPPCState *env)
2899 {
2900 /* Time base */
2901 gen_tbl(env);
2902 gen_spr_BookE(env);
2903 gen_spr_440(env);
2904 /* XXX : not implemented */
2905 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2906 SPR_NOACCESS, SPR_NOACCESS,
2907 &spr_read_generic, &spr_write_generic,
2908 0x00000000);
2909 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2910 SPR_NOACCESS, SPR_NOACCESS,
2911 &spr_read_generic, &spr_write_generic,
2912 0x00000000);
2913 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2914 SPR_NOACCESS, SPR_NOACCESS,
2915 &spr_read_generic, &spr_write_generic,
2916 0x00000000);
2917 /* XXX : not implemented */
2918 spr_register(env, SPR_440_CCR1, "CCR1",
2919 SPR_NOACCESS, SPR_NOACCESS,
2920 &spr_read_generic, &spr_write_generic,
2921 0x00000000);
2922 /* Memory management */
2923 #if !defined(CONFIG_USER_ONLY)
2924 env->nb_tlb = 64;
2925 env->nb_ways = 1;
2926 env->id_tlbs = 0;
2927 #endif
2928 init_excp_BookE(env);
2929 env->dcache_line_size = 32;
2930 env->icache_line_size = 32;
2931 /* XXX: TODO: allocate internal IRQ controller */
2932 }
2933
2934 /* PowerPC 440 GP */
2935 #define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | \
2936 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2937 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2938 PPC_405_MAC | PPC_440_SPEC)
2939 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
2940 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
2941 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
2942 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
2943 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
2944 #define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2945 POWERPC_FLAG_DE)
2946 #define check_pow_440GP check_pow_nocheck
2947
2948 static void init_proc_440GP (CPUPPCState *env)
2949 {
2950 /* Time base */
2951 gen_tbl(env);
2952 gen_spr_BookE(env);
2953 gen_spr_440(env);
2954 /* Memory management */
2955 #if !defined(CONFIG_USER_ONLY)
2956 env->nb_tlb = 64;
2957 env->nb_ways = 1;
2958 env->id_tlbs = 0;
2959 #endif
2960 init_excp_BookE(env);
2961 env->dcache_line_size = 32;
2962 env->icache_line_size = 32;
2963 /* XXX: TODO: allocate internal IRQ controller */
2964 }
2965
2966 /* PowerPC 440x4 */
2967 #define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \
2968 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2969 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2970 PPC_440_SPEC)
2971 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
2972 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
2973 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
2974 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
2975 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
2976 #define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2977 POWERPC_FLAG_DE)
2978 #define check_pow_440x4 check_pow_nocheck
2979
2980 __attribute__ (( unused ))
2981 static void init_proc_440x4 (CPUPPCState *env)
2982 {
2983 /* Time base */
2984 gen_tbl(env);
2985 gen_spr_BookE(env);
2986 gen_spr_440(env);
2987 /* Memory management */
2988 #if !defined(CONFIG_USER_ONLY)
2989 env->nb_tlb = 64;
2990 env->nb_ways = 1;
2991 env->id_tlbs = 0;
2992 #endif
2993 init_excp_BookE(env);
2994 env->dcache_line_size = 32;
2995 env->icache_line_size = 32;
2996 /* XXX: TODO: allocate internal IRQ controller */
2997 }
2998
2999 /* PowerPC 440x5 */
3000 #define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \
3001 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3002 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3003 PPC_440_SPEC | PPC_RFMCI)
3004 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3005 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3006 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3007 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3008 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3009 #define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3010 POWERPC_FLAG_DE)
3011 #define check_pow_440x5 check_pow_nocheck
3012
3013 static void init_proc_440x5 (CPUPPCState *env)
3014 {
3015 /* Time base */
3016 gen_tbl(env);
3017 gen_spr_BookE(env);
3018 gen_spr_440(env);
3019 /* XXX : not implemented */
3020 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3021 SPR_NOACCESS, SPR_NOACCESS,
3022 &spr_read_generic, &spr_write_generic,
3023 0x00000000);
3024 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3025 SPR_NOACCESS, SPR_NOACCESS,
3026 &spr_read_generic, &spr_write_generic,
3027 0x00000000);
3028 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3029 SPR_NOACCESS, SPR_NOACCESS,
3030 &spr_read_generic, &spr_write_generic,
3031 0x00000000);
3032 /* XXX : not implemented */
3033 spr_register(env, SPR_440_CCR1, "CCR1",
3034 SPR_NOACCESS, SPR_NOACCESS,
3035 &spr_read_generic, &spr_write_generic,
3036 0x00000000);
3037 /* Memory management */
3038 #if !defined(CONFIG_USER_ONLY)
3039 env->nb_tlb = 64;
3040 env->nb_ways = 1;
3041 env->id_tlbs = 0;
3042 #endif
3043 init_excp_BookE(env);
3044 env->dcache_line_size = 32;
3045 env->icache_line_size = 32;
3046 /* XXX: TODO: allocate internal IRQ controller */
3047 }
3048
3049 /* PowerPC 460 (guessed) */
3050 #define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | \
3051 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3052 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
3053 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3054 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3055 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3056 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3057 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3058 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3059 #define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3060 POWERPC_FLAG_DE)
3061 #define check_pow_460 check_pow_nocheck
3062
3063 __attribute__ (( unused ))
3064 static void init_proc_460 (CPUPPCState *env)
3065 {
3066 /* Time base */
3067 gen_tbl(env);
3068 gen_spr_BookE(env);
3069 gen_spr_440(env);
3070 /* XXX : not implemented */
3071 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3072 SPR_NOACCESS, SPR_NOACCESS,
3073 &spr_read_generic, &spr_write_generic,
3074 0x00000000);
3075 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3076 SPR_NOACCESS, SPR_NOACCESS,
3077 &spr_read_generic, &spr_write_generic,
3078 0x00000000);
3079 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3080 SPR_NOACCESS, SPR_NOACCESS,
3081 &spr_read_generic, &spr_write_generic,
3082 0x00000000);
3083 /* XXX : not implemented */
3084 spr_register(env, SPR_440_CCR1, "CCR1",
3085 SPR_NOACCESS, SPR_NOACCESS,
3086 &spr_read_generic, &spr_write_generic,
3087 0x00000000);
3088 /* XXX : not implemented */
3089 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3090 &spr_read_generic, &spr_write_generic,
3091 &spr_read_generic, &spr_write_generic,
3092 0x00000000);
3093 /* Memory management */
3094 #if !defined(CONFIG_USER_ONLY)
3095 env->nb_tlb = 64;
3096 env->nb_ways = 1;
3097 env->id_tlbs = 0;
3098 #endif
3099 init_excp_BookE(env);
3100 env->dcache_line_size = 32;
3101 env->icache_line_size = 32;
3102 /* XXX: TODO: allocate internal IRQ controller */
3103 }
3104
3105 /* PowerPC 460F (guessed) */
3106 #define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
3107 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3108 PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
3109 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
3110 PPC_FLOAT_STFIWX | \
3111 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
3112 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3113 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3114 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3115 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3116 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3117 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3118 #define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3119 POWERPC_FLAG_DE)
3120 #define check_pow_460F check_pow_nocheck
3121
3122 __attribute__ (( unused ))
3123 static void init_proc_460F (CPUPPCState *env)
3124 {
3125 /* Time base */
3126 gen_tbl(env);
3127 gen_spr_BookE(env);
3128 gen_spr_440(env);
3129 /* XXX : not implemented */
3130 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3131 SPR_NOACCESS, SPR_NOACCESS,
3132 &spr_read_generic, &spr_write_generic,
3133 0x00000000);
3134 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3135 SPR_NOACCESS, SPR_NOACCESS,
3136 &spr_read_generic, &spr_write_generic,
3137 0x00000000);
3138 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3139 SPR_NOACCESS, SPR_NOACCESS,
3140 &spr_read_generic, &spr_write_generic,
3141 0x00000000);
3142 /* XXX : not implemented */
3143 spr_register(env, SPR_440_CCR1, "CCR1",
3144 SPR_NOACCESS, SPR_NOACCESS,
3145 &spr_read_generic, &spr_write_generic,
3146 0x00000000);
3147 /* XXX : not implemented */
3148 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3149 &spr_read_generic, &spr_write_generic,
3150 &spr_read_generic, &spr_write_generic,
3151 0x00000000);
3152 /* Memory management */
3153 #if !defined(CONFIG_USER_ONLY)
3154 env->nb_tlb = 64;
3155 env->nb_ways = 1;
3156 env->id_tlbs = 0;
3157 #endif
3158 init_excp_BookE(env);
3159 env->dcache_line_size = 32;
3160 env->icache_line_size = 32;
3161 /* XXX: TODO: allocate internal IRQ controller */
3162 }
3163
3164 /* Generic BookE PowerPC */
3165 #define POWERPC_INSNS_BookE (POWERPC_INSNS_EMB | \
3166 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3167 PPC_CACHE_DCBA | \
3168 PPC_FLOAT | PPC_FLOAT_FSQRT | \
3169 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3170 PPC_FLOAT_FSEL | PPC_FLOAT_STFIW | \
3171 PPC_BOOKE)
3172 #define POWERPC_MSRM_BookE (0x000000000006D630ULL)
3173 #define POWERPC_MMU_BookE (POWERPC_MMU_BOOKE)
3174 #define POWERPC_EXCP_BookE (POWERPC_EXCP_BOOKE)
3175 #define POWERPC_INPUT_BookE (PPC_FLAGS_INPUT_BookE)
3176 #define POWERPC_BFDM_BookE (bfd_mach_ppc_403)
3177 #define POWERPC_FLAG_BookE (POWERPC_FLAG_NONE)
3178 #define check_pow_BookE check_pow_nocheck
3179
3180 __attribute__ (( unused ))
3181 static void init_proc_BookE (CPUPPCState *env)
3182 {
3183 init_excp_BookE(env);
3184 env->dcache_line_size = 32;
3185 env->icache_line_size = 32;
3186 }
3187
3188 /* e200 core */
3189
3190 /* e300 core */
3191
3192 /* e500 core */
3193 #define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | \
3194 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3195 PPC_CACHE_DCBA | \
3196 PPC_BOOKE | PPC_E500_VECTOR)
3197 #define POWERPC_MMU_e500 (POWERPC_MMU_SOFT_4xx)
3198 #define POWERPC_EXCP_e500 (POWERPC_EXCP_40x)
3199 #define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
3200 #define POWERPC_BFDM_e500 (bfd_mach_ppc_403)
3201 #define POWERPC_FLAG_e500 (POWERPC_FLAG_SPE)
3202 #define check_pow_e500 check_pow_hid0
3203
3204 __attribute__ (( unused ))
3205 static void init_proc_e500 (CPUPPCState *env)
3206 {
3207 /* Time base */
3208 gen_tbl(env);
3209 gen_spr_BookE(env);
3210 /* Memory management */
3211 gen_spr_BookE_FSL(env);
3212 #if !defined(CONFIG_USER_ONLY)
3213 env->nb_tlb = 64;
3214 env->nb_ways = 1;
3215 env->id_tlbs = 0;
3216 #endif
3217 init_excp_BookE(env);
3218 env->dcache_line_size = 32;
3219 env->icache_line_size = 32;
3220 /* XXX: TODO: allocate internal IRQ controller */
3221 }
3222
3223 /* e600 core */
3224
3225 /* Non-embedded PowerPC */
3226 /* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
3227 #define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
3228 PPC_MEM_EIEIO | PPC_MEM_TLBIE)
3229 /* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
3230 #define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
3231 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3232 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3233 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB | \
3234 PPC_SEGMENT)
3235
3236 /* POWER : same as 601, without mfmsr, mfsr */
3237 #if defined(TODO)
3238 #define POWERPC_INSNS_POWER (XXX_TODO)
3239 /* POWER RSC (from RAD6000) */
3240 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
3241 #endif /* TODO */
3242
3243 /* PowerPC 601 */
3244 #define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ | \
3245 PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
3246 #define POWERPC_MSRM_601 (0x000000000000FD70ULL)
3247 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
3248 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
3249 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
3250 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
3251 #define POWERPC_FLAG_601 (POWERPC_FLAG_SE)
3252 #define check_pow_601 check_pow_none
3253
3254 static void init_proc_601 (CPUPPCState *env)
3255 {
3256 gen_spr_ne_601(env);
3257 gen_spr_601(env);
3258 /* Hardware implementation registers */
3259 /* XXX : not implemented */
3260 spr_register(env, SPR_HID0, "HID0",
3261 SPR_NOACCESS, SPR_NOACCESS,
3262 &spr_read_generic, &spr_write_generic,
3263 0x80010080);
3264 /* XXX : not implemented */
3265 spr_register(env, SPR_HID1, "HID1",
3266 SPR_NOACCESS, SPR_NOACCESS,
3267 &spr_read_generic, &spr_write_generic,
3268 0x00000000);
3269 /* XXX : not implemented */
3270 spr_register(env, SPR_601_HID2, "HID2",
3271 SPR_NOACCESS, SPR_NOACCESS,
3272 &spr_read_generic, &spr_write_generic,
3273 0x00000000);
3274 /* XXX : not implemented */
3275 spr_register(env, SPR_601_HID5, "HID5",
3276 SPR_NOACCESS, SPR_NOACCESS,
3277 &spr_read_generic, &spr_write_generic,
3278 0x00000000);
3279 /* XXX : not implemented */
3280 spr_register(env, SPR_601_HID15, "HID15",
3281 SPR_NOACCESS, SPR_NOACCESS,
3282 &spr_read_generic, &spr_write_generic,
3283 0x00000000);
3284 /* Memory management */
3285 #if !defined(CONFIG_USER_ONLY)
3286 env->nb_tlb = 64;
3287 env->nb_ways = 2;
3288 env->id_tlbs = 0;
3289 #endif
3290 init_excp_601(env);
3291 env->dcache_line_size = 64;
3292 env->icache_line_size = 64;
3293 /* Allocate hardware IRQ controller */
3294 ppc6xx_irq_init(env);
3295 }
3296
3297 /* PowerPC 602 */
3298 #define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
3299 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3300 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3301 PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\
3302 PPC_SEGMENT | PPC_602_SPEC)
3303 #define POWERPC_MSRM_602 (0x000000000033FF73ULL)
3304 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
3305 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
3306 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
3307 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
3308 #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3309 POWERPC_FLAG_BE)
3310 #define check_pow_602 check_pow_hid0
3311
3312 static void init_proc_602 (CPUPPCState *env)
3313 {
3314 gen_spr_ne_601(env);
3315 gen_spr_602(env);
3316 /* Time base */
3317 gen_tbl(env);
3318 /* hardware implementation registers */
3319 /* XXX : not implemented */
3320 spr_register(env, SPR_HID0, "HID0",
3321 SPR_NOACCESS, SPR_NOACCESS,
3322 &spr_read_generic, &spr_write_generic,
3323 0x00000000);
3324 /* XXX : not implemented */
3325 spr_register(env, SPR_HID1, "HID1",
3326 SPR_NOACCESS, SPR_NOACCESS,
3327 &spr_read_generic, &spr_write_generic,
3328 0x00000000);
3329 /* Memory management */
3330 gen_low_BATs(env);
3331 gen_6xx_7xx_soft_tlb(env, 64, 2);
3332 init_excp_602(env);
3333 env->dcache_line_size = 32;
3334 env->icache_line_size = 32;
3335 /* Allocate hardware IRQ controller */
3336 ppc6xx_irq_init(env);
3337 }
3338
3339 /* PowerPC 603 */
3340 #define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3341 #define POWERPC_MSRM_603 (0x000000000007FF73ULL)
3342 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
3343 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
3344 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
3345 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
3346 #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3347 POWERPC_FLAG_BE)
3348 #define check_pow_603 check_pow_hid0
3349
3350 static void init_proc_603 (CPUPPCState *env)
3351 {
3352 gen_spr_ne_601(env);
3353 gen_spr_603(env);
3354 /* Time base */
3355 gen_tbl(env);
3356 /* hardware implementation registers */
3357 /* XXX : not implemented */
3358 spr_register(env, SPR_HID0, "HID0",
3359 SPR_NOACCESS, SPR_NOACCESS,
3360 &spr_read_generic, &spr_write_generic,
3361 0x00000000);
3362 /* XXX : not implemented */
3363 spr_register(env, SPR_HID1, "HID1",
3364 SPR_NOACCESS, SPR_NOACCESS,
3365 &spr_read_generic, &spr_write_generic,
3366 0x00000000);
3367 /* Memory management */
3368 gen_low_BATs(env);
3369 gen_6xx_7xx_soft_tlb(env, 64, 2);
3370 init_excp_603(env);
3371 env->dcache_line_size = 32;
3372 env->icache_line_size = 32;
3373 /* Allocate hardware IRQ controller */
3374 ppc6xx_irq_init(env);
3375 }
3376
3377 /* PowerPC 603e */
3378 #define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3379 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
3380 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
3381 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
3382 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
3383 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
3384 #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3385 POWERPC_FLAG_BE)
3386 #define check_pow_603E check_pow_hid0
3387
3388 static void init_proc_603E (CPUPPCState *env)
3389 {
3390 gen_spr_ne_601(env);
3391 gen_spr_603(env);
3392 /* Time base */
3393 gen_tbl(env);
3394 /* hardware implementation registers */
3395 /* XXX : not implemented */
3396 spr_register(env, SPR_HID0, "HID0",
3397 SPR_NOACCESS, SPR_NOACCESS,
3398 &spr_read_generic, &spr_write_generic,
3399 0x00000000);
3400 /* XXX : not implemented */
3401 spr_register(env, SPR_HID1, "HID1",
3402 SPR_NOACCESS, SPR_NOACCESS,
3403 &spr_read_generic, &spr_write_generic,
3404 0x00000000);
3405 /* XXX : not implemented */
3406 spr_register(env, SPR_IABR, "IABR",
3407 SPR_NOACCESS, SPR_NOACCESS,
3408 &spr_read_generic, &spr_write_generic,
3409 0x00000000);
3410 /* Memory management */
3411 gen_low_BATs(env);
3412 gen_6xx_7xx_soft_tlb(env, 64, 2);
3413 init_excp_603(env);
3414 env->dcache_line_size = 32;
3415 env->icache_line_size = 32;
3416 /* Allocate hardware IRQ controller */
3417 ppc6xx_irq_init(env);
3418 }
3419
3420 /* PowerPC G2 */
3421 #define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3422 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3423 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3424 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3425 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3426 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3427 #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3428 POWERPC_FLAG_BE)
3429 #define check_pow_G2 check_pow_hid0
3430
3431 static void init_proc_G2 (CPUPPCState *env)
3432 {
3433 gen_spr_ne_601(env);
3434 gen_spr_G2_755(env);
3435 gen_spr_G2(env);
3436 /* Time base */
3437 gen_tbl(env);
3438 /* Hardware implementation register */
3439 /* XXX : not implemented */
3440 spr_register(env, SPR_HID0, "HID0",
3441 SPR_NOACCESS, SPR_NOACCESS,
3442 &spr_read_generic, &spr_write_generic,
3443 0x00000000);
3444 /* XXX : not implemented */
3445 spr_register(env, SPR_HID1, "HID1",
3446 SPR_NOACCESS, SPR_NOACCESS,
3447 &spr_read_generic, &spr_write_generic,
3448 0x00000000);
3449 /* XXX : not implemented */
3450 spr_register(env, SPR_HID2, "HID2",
3451 SPR_NOACCESS, SPR_NOACCESS,
3452 &spr_read_generic, &spr_write_generic,
3453 0x00000000);
3454 /* Memory management */
3455 gen_low_BATs(env);
3456 gen_high_BATs(env);
3457 gen_6xx_7xx_soft_tlb(env, 64, 2);
3458 init_excp_G2(env);
3459 env->dcache_line_size = 32;
3460 env->icache_line_size = 32;
3461 /* Allocate hardware IRQ controller */
3462 ppc6xx_irq_init(env);
3463 }
3464
3465 /* PowerPC G2LE */
3466 #define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3467 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3468 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3469 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3470 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
3471 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
3472 #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3473 POWERPC_FLAG_BE)
3474 #define check_pow_G2LE check_pow_hid0
3475
3476 static void init_proc_G2LE (CPUPPCState *env)
3477 {
3478 gen_spr_ne_601(env);
3479 gen_spr_G2_755(env);
3480 gen_spr_G2(env);
3481 /* Time base */
3482 gen_tbl(env);
3483 /* Hardware implementation register */
3484 /* XXX : not implemented */
3485 spr_register(env, SPR_HID0, "HID0",
3486 SPR_NOACCESS, SPR_NOACCESS,
3487 &spr_read_generic, &spr_write_generic,
3488 0x00000000);
3489 /* XXX : not implemented */
3490 spr_register(env, SPR_HID1, "HID1",
3491 SPR_NOACCESS, SPR_NOACCESS,
3492 &spr_read_generic, &spr_write_generic,
3493 0x00000000);
3494 /* XXX : not implemented */
3495 spr_register(env, SPR_HID2, "HID2",
3496 SPR_NOACCESS, SPR_NOACCESS,
3497 &spr_read_generic, &spr_write_generic,
3498 0x00000000);
3499 /* Memory management */
3500 gen_low_BATs(env);
3501 gen_high_BATs(env);
3502 gen_6xx_7xx_soft_tlb(env, 64, 2);
3503 init_excp_G2(env);
3504 env->dcache_line_size = 32;
3505 env->icache_line_size = 32;
3506 /* Allocate hardware IRQ controller */
3507 ppc6xx_irq_init(env);
3508 }
3509
3510 /* PowerPC 604 */
3511 #define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3512 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
3513 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
3514 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
3515 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
3516 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
3517 #define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3518 POWERPC_FLAG_PMM)
3519 #define check_pow_604 check_pow_nocheck
3520
3521 static void init_proc_604 (CPUPPCState *env)
3522 {
3523 gen_spr_ne_601(env);
3524 gen_spr_604(env);
3525 /* Time base */
3526 gen_tbl(env);
3527 /* Hardware implementation registers */
3528 /* XXX : not implemented */
3529 spr_register(env, SPR_HID0, "HID0",
3530 SPR_NOACCESS, SPR_NOACCESS,
3531 &spr_read_generic, &spr_write_generic,
3532 0x00000000);
3533 /* XXX : not implemented */
3534 spr_register(env, SPR_HID1, "HID1",
3535 SPR_NOACCESS, SPR_NOACCESS,
3536 &spr_read_generic, &spr_write_generic,
3537 0x00000000);
3538 /* Memory management */
3539 gen_low_BATs(env);
3540 init_excp_604(env);
3541 env->dcache_line_size = 32;
3542 env->icache_line_size = 32;
3543 /* Allocate hardware IRQ controller */
3544 ppc6xx_irq_init(env);
3545 }
3546
3547 /* PowerPC 740/750 (aka G3) */
3548 #define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3549 #define POWERPC_MSRM_7x0 (0x000000000005FF77ULL)
3550 #define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
3551 //#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
3552 #define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
3553 #define POWERPC_BFDM_7x0 (bfd_mach_ppc_750)
3554 #define POWERPC_FLAG_7x0 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3555 POWERPC_FLAG_PMM)
3556 #define check_pow_7x0 check_pow_hid0
3557
3558 static void init_proc_7x0 (CPUPPCState *env)
3559 {
3560 gen_spr_ne_601(env);
3561 gen_spr_7xx(env);
3562 /* Time base */
3563 gen_tbl(env);
3564 /* Thermal management */
3565 gen_spr_thrm(env);
3566 /* Hardware implementation registers */
3567 /* XXX : not implemented */
3568 spr_register(env, SPR_HID0, "HID0",
3569 SPR_NOACCESS, SPR_NOACCESS,
3570 &spr_read_generic, &spr_write_generic,
3571 0x00000000);
3572 /* XXX : not implemented */
3573 spr_register(env, SPR_HID1, "HID1",
3574 SPR_NOACCESS, SPR_NOACCESS,
3575 &spr_read_generic, &spr_write_generic,
3576 0x00000000);
3577 /* Memory management */
3578 gen_low_BATs(env);
3579 init_excp_7x0(env);
3580 env->dcache_line_size = 32;
3581 env->icache_line_size = 32;
3582 /* Allocate hardware IRQ controller */
3583 ppc6xx_irq_init(env);
3584 }
3585
3586 /* PowerPC 750FX/GX */
3587 #define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN)
3588 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
3589 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
3590 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
3591 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
3592 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
3593 #define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3594 POWERPC_FLAG_PMM)
3595 #define check_pow_750fx check_pow_hid0
3596
3597 static void init_proc_750fx (CPUPPCState *env)
3598 {
3599 gen_spr_ne_601(env);
3600 gen_spr_7xx(env);
3601 /* Time base */
3602 gen_tbl(env);
3603 /* Thermal management */
3604 gen_spr_thrm(env);
3605 /* Hardware implementation registers */
3606 /* XXX : not implemented */
3607 spr_register(env, SPR_HID0, "HID0",
3608 SPR_NOACCESS, SPR_NOACCESS,
3609 &spr_read_generic, &spr_write_generic,
3610 0x00000000);
3611 /* XXX : not implemented */
3612 spr_register(env, SPR_HID1, "HID1",
3613 SPR_NOACCESS, SPR_NOACCESS,
3614 &spr_read_generic, &spr_write_generic,
3615 0x00000000);
3616 /* XXX : not implemented */
3617 spr_register(env, SPR_750_HID2, "HID2",
3618 SPR_NOACCESS, SPR_NOACCESS,
3619 &spr_read_generic, &spr_write_generic,
3620 0x00000000);
3621 /* Memory management */
3622 gen_low_BATs(env);
3623 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3624 gen_high_BATs(env);
3625 init_excp_750FX(env);
3626 env->dcache_line_size = 32;
3627 env->icache_line_size = 32;
3628 /* Allocate hardware IRQ controller */
3629 ppc6xx_irq_init(env);
3630 }
3631
3632 /* PowerPC 745/755 */
3633 #define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
3634 #define POWERPC_MSRM_7x5 (0x000000000005FF77ULL)
3635 #define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
3636 //#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
3637 #define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
3638 #define POWERPC_BFDM_7x5 (bfd_mach_ppc_750)
3639 #define POWERPC_FLAG_7x5 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3640 POWERPC_FLAG_PMM)
3641 #define check_pow_7x5 check_pow_hid0
3642
3643 static void init_proc_7x5 (CPUPPCState *env)
3644 {
3645 gen_spr_ne_601(env);
3646 gen_spr_G2_755(env);
3647 /* Time base */
3648 gen_tbl(env);
3649 /* L2 cache control */
3650 /* XXX : not implemented */
3651 spr_register(env, SPR_ICTC, "ICTC",
3652 SPR_NOACCESS, SPR_NOACCESS,
3653 &spr_read_generic, &spr_write_generic,
3654 0x00000000);
3655 /* XXX : not implemented */
3656 spr_register(env, SPR_L2PMCR, "L2PMCR",
3657 SPR_NOACCESS, SPR_NOACCESS,
3658 &spr_read_generic, &spr_write_generic,
3659 0x00000000);
3660 /* Hardware implementation registers */
3661 /* XXX : not implemented */
3662 spr_register(env, SPR_HID0, "HID0",
3663 SPR_NOACCESS, SPR_NOACCESS,
3664 &spr_read_generic, &spr_write_generic,
3665 0x00000000);
3666 /* XXX : not implemented */
3667 spr_register(env, SPR_HID1, "HID1",
3668 SPR_NOACCESS, SPR_NOACCESS,
3669 &spr_read_generic, &spr_write_generic,
3670 0x00000000);
3671 /* XXX : not implemented */
3672 spr_register(env, SPR_HID2, "HID2",
3673 SPR_NOACCESS, SPR_NOACCESS,
3674 &spr_read_generic, &spr_write_generic,
3675 0x00000000);
3676 /* Memory management */
3677 gen_low_BATs(env);
3678 gen_high_BATs(env);
3679 gen_6xx_7xx_soft_tlb(env, 64, 2);
3680 init_excp_7x5(env);
3681 env->dcache_line_size = 32;
3682 env->icache_line_size = 32;
3683 /* Allocate hardware IRQ controller */
3684 ppc6xx_irq_init(env);
3685 #if !defined(CONFIG_USER_ONLY)
3686 /* Hardware reset vector */
3687 env->hreset_vector = 0xFFFFFFFCUL;
3688 #endif
3689 }
3690
3691 /* PowerPC 7400 (aka G4) */
3692 #define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3693 PPC_EXTERN | PPC_MEM_TLBIA | \
3694 PPC_ALTIVEC)
3695 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
3696 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
3697 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
3698 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
3699 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
3700 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3701 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3702 #define check_pow_7400 check_pow_hid0
3703
3704 static void init_proc_7400 (CPUPPCState *env)
3705 {
3706 gen_spr_ne_601(env);
3707 gen_spr_7xx(env);
3708 /* Time base */
3709 gen_tbl(env);
3710 /* 74xx specific SPR */
3711 gen_spr_74xx(env);
3712 /* Thermal management */
3713 gen_spr_thrm(env);
3714 /* Memory management */
3715 gen_low_BATs(env);
3716 init_excp_7400(env);
3717 env->dcache_line_size = 32;
3718 env->icache_line_size = 32;
3719 /* Allocate hardware IRQ controller */
3720 ppc6xx_irq_init(env);
3721 }
3722
3723 /* PowerPC 7410 (aka G4) */
3724 #define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3725 PPC_EXTERN | PPC_MEM_TLBIA | \
3726 PPC_ALTIVEC)
3727 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
3728 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
3729 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
3730 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
3731 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
3732 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3733 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3734 #define check_pow_7410 check_pow_hid0
3735
3736 static void init_proc_7410 (CPUPPCState *env)
3737 {
3738 gen_spr_ne_601(env);
3739 gen_spr_7xx(env);
3740 /* Time base */
3741 gen_tbl(env);
3742 /* 74xx specific SPR */
3743 gen_spr_74xx(env);
3744 /* Thermal management */
3745 gen_spr_thrm(env);
3746 /* L2PMCR */
3747 /* XXX : not implemented */
3748 spr_register(env, SPR_L2PMCR, "L2PMCR",
3749 SPR_NOACCESS, SPR_NOACCESS,
3750 &spr_read_generic, &spr_write_generic,
3751 0x00000000);
3752 /* LDSTDB */
3753 /* XXX : not implemented */
3754 spr_register(env, SPR_LDSTDB, "LDSTDB",
3755 SPR_NOACCESS, SPR_NOACCESS,
3756 &spr_read_generic, &spr_write_generic,
3757 0x00000000);
3758 /* Memory management */
3759 gen_low_BATs(env);
3760 init_excp_7400(env);
3761 env->dcache_line_size = 32;
3762 env->icache_line_size = 32;
3763 /* Allocate hardware IRQ controller */
3764 ppc6xx_irq_init(env);
3765 }
3766
3767 /* PowerPC 7440 (aka G4) */
3768 #define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3769 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3770 PPC_ALTIVEC)
3771 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
3772 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
3773 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
3774 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
3775 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
3776 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3777 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3778 #define check_pow_7440 check_pow_hid0
3779
3780 __attribute__ (( unused ))
3781 static void init_proc_7440 (CPUPPCState *env)
3782 {
3783 gen_spr_ne_601(env);
3784 gen_spr_7xx(env);
3785 /* Time base */
3786 gen_tbl(env);
3787 /* 74xx specific SPR */
3788 gen_spr_74xx(env);
3789 /* LDSTCR */
3790 /* XXX : not implemented */
3791 spr_register(env, SPR_LDSTCR, "LDSTCR",
3792 SPR_NOACCESS, SPR_NOACCESS,
3793 &spr_read_generic, &spr_write_generic,
3794 0x00000000);
3795 /* ICTRL */
3796 /* XXX : not implemented */
3797 spr_register(env, SPR_ICTRL, "ICTRL",
3798 SPR_NOACCESS, SPR_NOACCESS,
3799 &spr_read_generic, &spr_write_generic,
3800 0x00000000);
3801 /* MSSSR0 */
3802 /* XXX : not implemented */
3803 spr_register(env, SPR_MSSSR0, "MSSSR0",
3804 SPR_NOACCESS, SPR_NOACCESS,
3805 &spr_read_generic, &spr_write_generic,
3806 0x00000000);
3807 /* PMC */
3808 /* XXX : not implemented */
3809 spr_register(env, SPR_PMC5, "PMC5",
3810 SPR_NOACCESS, SPR_NOACCESS,
3811 &spr_read_generic, &spr_write_generic,
3812 0x00000000);
3813 /* XXX : not implemented */
3814 spr_register(env, SPR_UPMC5, "UPMC5",
3815 &spr_read_ureg, SPR_NOACCESS,
3816 &spr_read_ureg, SPR_NOACCESS,
3817 0x00000000);
3818 /* XXX : not implemented */
3819 spr_register(env, SPR_PMC6, "PMC6",
3820 SPR_NOACCESS, SPR_NOACCESS,
3821 &spr_read_generic, &spr_write_generic,
3822 0x00000000);
3823 /* XXX : not implemented */
3824 spr_register(env, SPR_UPMC6, "UPMC6",
3825 &spr_read_ureg, SPR_NOACCESS,
3826 &spr_read_ureg, SPR_NOACCESS,
3827 0x00000000);
3828 /* Memory management */
3829 gen_low_BATs(env);
3830 gen_74xx_soft_tlb(env, 128, 2);
3831 init_excp_7450(env);
3832 env->dcache_line_size = 32;
3833 env->icache_line_size = 32;
3834 /* Allocate hardware IRQ controller */
3835 ppc6xx_irq_init(env);
3836 }
3837
3838 /* PowerPC 7450 (aka G4) */
3839 #define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3840 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3841 PPC_ALTIVEC)
3842 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
3843 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
3844 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
3845 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
3846 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
3847 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3848 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3849 #define check_pow_7450 check_pow_hid0
3850
3851 __attribute__ (( unused ))
3852 static void init_proc_7450 (CPUPPCState *env)
3853 {
3854 gen_spr_ne_601(env);
3855 gen_spr_7xx(env);
3856 /* Time base */
3857 gen_tbl(env);
3858 /* 74xx specific SPR */
3859 gen_spr_74xx(env);
3860 /* Level 3 cache control */
3861 gen_l3_ctrl(env);
3862 /* LDSTCR */
3863 /* XXX : not implemented */
3864 spr_register(env, SPR_LDSTCR, "LDSTCR",
3865 SPR_NOACCESS, SPR_NOACCESS,
3866 &spr_read_generic, &spr_write_generic,
3867 0x00000000);
3868 /* ICTRL */
3869 /* XXX : not implemented */
3870 spr_register(env, SPR_ICTRL, "ICTRL",
3871 SPR_NOACCESS, SPR_NOACCESS,
3872 &spr_read_generic, &spr_write_generic,
3873 0x00000000);
3874 /* MSSSR0 */
3875 /* XXX : not implemented */
3876 spr_register(env, SPR_MSSSR0, "MSSSR0",
3877 SPR_NOACCESS, SPR_NOACCESS,
3878 &spr_read_generic, &spr_write_generic,
3879 0x00000000);
3880 /* PMC */
3881 /* XXX : not implemented */
3882 spr_register(env, SPR_PMC5, "PMC5",
3883 SPR_NOACCESS, SPR_NOACCESS,
3884 &spr_read_generic, &spr_write_generic,
3885 0x00000000);
3886 /* XXX : not implemented */
3887 spr_register(env, SPR_UPMC5, "UPMC5",
3888 &spr_read_ureg, SPR_NOACCESS,
3889 &spr_read_ureg, SPR_NOACCESS,
3890 0x00000000);
3891 /* XXX : not implemented */
3892 spr_register(env, SPR_PMC6, "PMC6",
3893 SPR_NOACCESS, SPR_NOACCESS,
3894 &spr_read_generic, &spr_write_generic,
3895 0x00000000);
3896 /* XXX : not implemented */
3897 spr_register(env, SPR_UPMC6, "UPMC6",
3898 &spr_read_ureg, SPR_NOACCESS,
3899 &spr_read_ureg, SPR_NOACCESS,
3900 0x00000000);
3901 /* Memory management */
3902 gen_low_BATs(env);
3903 gen_74xx_soft_tlb(env, 128, 2);
3904 init_excp_7450(env);
3905 env->dcache_line_size = 32;
3906 env->icache_line_size = 32;
3907 /* Allocate hardware IRQ controller */
3908 ppc6xx_irq_init(env);
3909 }
3910
3911 /* PowerPC 7445 (aka G4) */
3912 #define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3913 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3914 PPC_ALTIVEC)
3915 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
3916 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
3917 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
3918 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
3919 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
3920 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3921 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3922 #define check_pow_7445 check_pow_hid0
3923
3924 __attribute__ (( unused ))
3925 static void init_proc_7445 (CPUPPCState *env)
3926 {
3927 gen_spr_ne_601(env);
3928 gen_spr_7xx(env);
3929 /* Time base */
3930 gen_tbl(env);
3931 /* 74xx specific SPR */
3932 gen_spr_74xx(env);
3933 /* LDSTCR */
3934 /* XXX : not implemented */
3935 spr_register(env, SPR_LDSTCR, "LDSTCR",
3936 SPR_NOACCESS, SPR_NOACCESS,
3937 &spr_read_generic, &spr_write_generic,
3938 0x00000000);
3939 /* ICTRL */
3940 /* XXX : not implemented */
3941 spr_register(env, SPR_ICTRL, "ICTRL",
3942 SPR_NOACCESS, SPR_NOACCESS,
3943 &spr_read_generic, &spr_write_generic,
3944 0x00000000);
3945 /* MSSSR0 */
3946 /* XXX : not implemented */
3947 spr_register(env, SPR_MSSSR0, "MSSSR0",
3948 SPR_NOACCESS, SPR_NOACCESS,
3949 &spr_read_generic, &spr_write_generic,
3950 0x00000000);
3951 /* PMC */
3952 /* XXX : not implemented */
3953 spr_register(env, SPR_PMC5, "PMC5",
3954 SPR_NOACCESS, SPR_NOACCESS,
3955 &spr_read_generic, &spr_write_generic,
3956 0x00000000);
3957 /* XXX : not implemented */
3958 spr_register(env, SPR_UPMC5, "UPMC5",
3959 &spr_read_ureg, SPR_NOACCESS,
3960 &spr_read_ureg, SPR_NOACCESS,
3961 0x00000000);
3962 /* XXX : not implemented */
3963 spr_register(env, SPR_PMC6, "PMC6",
3964 SPR_NOACCESS, SPR_NOACCESS,
3965 &spr_read_generic, &spr_write_generic,
3966 0x00000000);
3967 /* XXX : not implemented */
3968 spr_register(env, SPR_UPMC6, "UPMC6",
3969 &spr_read_ureg, SPR_NOACCESS,
3970 &spr_read_ureg, SPR_NOACCESS,
3971 0x00000000);
3972 /* SPRGs */
3973 spr_register(env, SPR_SPRG4, "SPRG4",
3974 SPR_NOACCESS, SPR_NOACCESS,
3975 &spr_read_generic, &spr_write_generic,
3976 0x00000000);
3977 spr_register(env, SPR_USPRG4, "USPRG4",
3978 &spr_read_ureg, SPR_NOACCESS,
3979 &spr_read_ureg, SPR_NOACCESS,
3980 0x00000000);
3981 spr_register(env, SPR_SPRG5, "SPRG5",
3982 SPR_NOACCESS, SPR_NOACCESS,
3983 &spr_read_generic, &spr_write_generic,
3984 0x00000000);
3985 spr_register(env, SPR_USPRG5, "USPRG5",
3986 &spr_read_ureg, SPR_NOACCESS,
3987 &spr_read_ureg, SPR_NOACCESS,
3988 0x00000000);
3989 spr_register(env, SPR_SPRG6, "SPRG6",
3990 SPR_NOACCESS, SPR_NOACCESS,
3991 &spr_read_generic, &spr_write_generic,
3992 0x00000000);
3993 spr_register(env, SPR_USPRG6, "USPRG6",
3994 &spr_read_ureg, SPR_NOACCESS,
3995 &spr_read_ureg, SPR_NOACCESS,
3996 0x00000000);
3997 spr_register(env, SPR_SPRG7, "SPRG7",
3998 SPR_NOACCESS, SPR_NOACCESS,
3999 &spr_read_generic, &spr_write_generic,
4000 0x00000000);
4001 spr_register(env, SPR_USPRG7, "USPRG7",
4002 &spr_read_ureg, SPR_NOACCESS,
4003 &spr_read_ureg, SPR_NOACCESS,
4004 0x00000000);
4005 /* Memory management */
4006 gen_low_BATs(env);
4007 gen_high_BATs(env);
4008 gen_74xx_soft_tlb(env, 128, 2);
4009 init_excp_7450(env);
4010 env->dcache_line_size = 32;
4011 env->icache_line_size = 32;
4012 /* Allocate hardware IRQ controller */
4013 ppc6xx_irq_init(env);
4014 }
4015
4016 /* PowerPC 7455 (aka G4) */
4017 #define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
4018 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
4019 PPC_ALTIVEC)
4020 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
4021 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
4022 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
4023 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
4024 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
4025 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4026 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4027 #define check_pow_7455 check_pow_hid0
4028
4029 __attribute__ (( unused ))
4030 static void init_proc_7455 (CPUPPCState *env)
4031 {
4032 gen_spr_ne_601(env);
4033 gen_spr_7xx(env);
4034 /* Time base */
4035 gen_tbl(env);
4036 /* 74xx specific SPR */
4037 gen_spr_74xx(env);
4038 /* Level 3 cache control */
4039 gen_l3_ctrl(env);
4040 /* LDSTCR */
4041 /* XXX : not implemented */
4042 spr_register(env, SPR_LDSTCR, "LDSTCR",
4043 SPR_NOACCESS, SPR_NOACCESS,
4044 &spr_read_generic, &spr_write_generic,
4045 0x00000000);
4046 /* ICTRL */
4047 /* XXX : not implemented */
4048 spr_register(env, SPR_ICTRL, "ICTRL",
4049 SPR_NOACCESS, SPR_NOACCESS,
4050 &spr_read_generic, &spr_write_generic,
4051 0x00000000);
4052 /* MSSSR0 */
4053 /* XXX : not implemented */
4054 spr_register(env, SPR_MSSSR0, "MSSSR0",
4055 SPR_NOACCESS, SPR_NOACCESS,
4056 &spr_read_generic, &spr_write_generic,
4057 0x00000000);
4058 /* PMC */
4059 /* XXX : not implemented */
4060 spr_register(env, SPR_PMC5, "PMC5",
4061 SPR_NOACCESS, SPR_NOACCESS,
4062 &spr_read_generic, &spr_write_generic,
4063 0x00000000);
4064 /* XXX : not implemented */
4065 spr_register(env, SPR_UPMC5, "UPMC5",
4066 &spr_read_ureg, SPR_NOACCESS,
4067 &spr_read_ureg, SPR_NOACCESS,
4068 0x00000000);
4069 /* XXX : not implemented */
4070 spr_register(env, SPR_PMC6, "PMC6",
4071 SPR_NOACCESS, SPR_NOACCESS,
4072 &spr_read_generic, &spr_write_generic,
4073 0x00000000);
4074 /* XXX : not implemented */
4075 spr_register(env, SPR_UPMC6, "UPMC6",
4076 &spr_read_ureg, SPR_NOACCESS,
4077 &spr_read_ureg, SPR_NOACCESS,
4078 0x00000000);
4079 /* SPRGs */
4080 spr_register(env, SPR_SPRG4, "SPRG4",
4081 SPR_NOACCESS, SPR_NOACCESS,
4082 &spr_read_generic, &spr_write_generic,
4083 0x00000000);
4084 spr_register(env, SPR_USPRG4, "USPRG4",
4085 &spr_read_ureg, SPR_NOACCESS,
4086 &spr_read_ureg, SPR_NOACCESS,
4087 0x00000000);
4088 spr_register(env, SPR_SPRG5, "SPRG5",
4089 SPR_NOACCESS, SPR_NOACCESS,
4090 &spr_read_generic, &spr_write_generic,
4091 0x00000000);
4092 spr_register(env, SPR_USPRG5, "USPRG5",
4093 &spr_read_ureg, SPR_NOACCESS,
4094 &spr_read_ureg, SPR_NOACCESS,
4095 0x00000000);
4096 spr_register(env, SPR_SPRG6, "SPRG6",
4097 SPR_NOACCESS, SPR_NOACCESS,
4098 &spr_read_generic, &spr_write_generic,
4099 0x00000000);
4100 spr_register(env, SPR_USPRG6, "USPRG6",
4101 &spr_read_ureg, SPR_NOACCESS,
4102 &spr_read_ureg, SPR_NOACCESS,
4103 0x00000000);
4104 spr_register(env, SPR_SPRG7, "SPRG7",
4105 SPR_NOACCESS, SPR_NOACCESS,
4106 &spr_read_generic, &spr_write_generic,
4107 0x00000000);
4108 spr_register(env, SPR_USPRG7, "USPRG7",
4109 &spr_read_ureg, SPR_NOACCESS,
4110 &spr_read_ureg, SPR_NOACCESS,
4111 0x00000000);
4112 /* Memory management */
4113 gen_low_BATs(env);
4114 gen_high_BATs(env);
4115 gen_74xx_soft_tlb(env, 128, 2);
4116 init_excp_7450(env);
4117 env->dcache_line_size = 32;
4118 env->icache_line_size = 32;
4119 /* Allocate hardware IRQ controller */
4120 ppc6xx_irq_init(env);
4121 }
4122
4123 #if defined (TARGET_PPC64)
4124 #define POWERPC_INSNS_WORK64 (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
4125 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
4126 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
4127 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)
4128 /* PowerPC 970 */
4129 #define POWERPC_INSNS_970 (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4130 PPC_64B | PPC_ALTIVEC | \
4131 PPC_SEGMENT_64B | PPC_SLBI)
4132 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
4133 #define POWERPC_MMU_970 (POWERPC_MMU_64B)
4134 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
4135 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
4136 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
4137 #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4138 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4139
4140 #if defined(CONFIG_USER_ONLY)
4141 #define POWERPC970_HID5_INIT 0x00000080
4142 #else
4143 #define POWERPC970_HID5_INIT 0x00000000
4144 #endif
4145
4146 static int check_pow_970 (CPUPPCState *env)
4147 {
4148 if (env->spr[SPR_HID0] & 0x00600000)
4149 return 1;
4150
4151 return 0;
4152 }
4153
4154 static void init_proc_970 (CPUPPCState *env)
4155 {
4156 gen_spr_ne_601(env);
4157 gen_spr_7xx(env);
4158 /* Time base */
4159 gen_tbl(env);
4160 /* Hardware implementation registers */
4161 /* XXX : not implemented */
4162 spr_register(env, SPR_HID0, "HID0",
4163 SPR_NOACCESS, SPR_NOACCESS,
4164 &spr_read_generic, &spr_write_clear,
4165 0x60000000);
4166 /* XXX : not implemented */
4167 spr_register(env, SPR_HID1, "HID1",
4168 SPR_NOACCESS, SPR_NOACCESS,
4169 &spr_read_generic, &spr_write_generic,
4170 0x00000000);
4171 /* XXX : not implemented */
4172 spr_register(env, SPR_750_HID2, "HID2",
4173 SPR_NOACCESS, SPR_NOACCESS,
4174 &spr_read_generic, &spr_write_generic,
4175 0x00000000);
4176 /* XXX : not implemented */
4177 spr_register(env, SPR_970_HID5, "HID5",
4178 SPR_NOACCESS, SPR_NOACCESS,
4179 &spr_read_generic, &spr_write_generic,
4180 POWERPC970_HID5_INIT);
4181 /* Memory management */
4182 /* XXX: not correct */
4183 gen_low_BATs(env);
4184 /* XXX : not implemented */
4185 spr_register(env, SPR_MMUCFG, "MMUCFG",
4186 SPR_NOACCESS, SPR_NOACCESS,
4187 &spr_read_generic, SPR_NOACCESS,
4188 0x00000000); /* TOFIX */
4189 /* XXX : not implemented */
4190 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4191 SPR_NOACCESS, SPR_NOACCESS,
4192 &spr_read_generic, &spr_write_generic,
4193 0x00000000); /* TOFIX */
4194 spr_register(env, SPR_HIOR, "SPR_HIOR",
4195 SPR_NOACCESS, SPR_NOACCESS,
4196 &spr_read_generic, &spr_write_generic,
4197 0xFFF00000); /* XXX: This is a hack */
4198 #if !defined(CONFIG_USER_ONLY)
4199 env->slb_nr = 32;
4200 #endif
4201 init_excp_970(env);
4202 env->dcache_line_size = 128;
4203 env->icache_line_size = 128;
4204 /* Allocate hardware IRQ controller */
4205 ppc970_irq_init(env);
4206 }
4207
4208 /* PowerPC 970FX (aka G5) */
4209 #define POWERPC_INSNS_970FX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4210 PPC_64B | PPC_ALTIVEC | \
4211 PPC_SEGMENT_64B | PPC_SLBI)
4212 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
4213 #define POWERPC_MMU_970FX (POWERPC_MMU_64B)
4214 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
4215 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
4216 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
4217 #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4218 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4219
4220 static int check_pow_970FX (CPUPPCState *env)
4221 {
4222 if (env->spr[SPR_HID0] & 0x00600000)
4223 return 1;
4224
4225 return 0;
4226 }
4227
4228 static void init_proc_970FX (CPUPPCState *env)
4229 {
4230 gen_spr_ne_601(env);
4231 gen_spr_7xx(env);
4232 /* Time base */
4233 gen_tbl(env);
4234 /* Hardware implementation registers */
4235 /* XXX : not implemented */
4236 spr_register(env, SPR_HID0, "HID0",
4237 SPR_NOACCESS, SPR_NOACCESS,
4238 &spr_read_generic, &spr_write_clear,
4239 0x60000000);
4240 /* XXX : not implemented */
4241 spr_register(env, SPR_HID1, "HID1",
4242 SPR_NOACCESS, SPR_NOACCESS,
4243 &spr_read_generic, &spr_write_generic,
4244 0x00000000);
4245 /* XXX : not implemented */
4246 spr_register(env, SPR_750_HID2, "HID2",
4247 SPR_NOACCESS, SPR_NOACCESS,
4248 &spr_read_generic, &spr_write_generic,
4249 0x00000000);
4250 /* XXX : not implemented */
4251 spr_register(env, SPR_970_HID5, "HID5",
4252 SPR_NOACCESS, SPR_NOACCESS,
4253 &spr_read_generic, &spr_write_generic,
4254 POWERPC970_HID5_INIT);
4255 /* Memory management */
4256 /* XXX: not correct */
4257 gen_low_BATs(env);
4258 /* XXX : not implemented */
4259 spr_register(env, SPR_MMUCFG, "MMUCFG",
4260 SPR_NOACCESS, SPR_NOACCESS,
4261 &spr_read_generic, SPR_NOACCESS,
4262 0x00000000); /* TOFIX */
4263 /* XXX : not implemented */
4264 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4265 SPR_NOACCESS, SPR_NOACCESS,
4266 &spr_read_generic, &spr_write_generic,
4267 0x00000000); /* TOFIX */
4268 spr_register(env, SPR_HIOR, "SPR_HIOR",
4269 SPR_NOACCESS, SPR_NOACCESS,
4270 &spr_read_generic, &spr_write_generic,
4271 0xFFF00000); /* XXX: This is a hack */
4272 #if !defined(CONFIG_USER_ONLY)
4273 env->slb_nr = 32;
4274 #endif
4275 init_excp_970(env);
4276 env->dcache_line_size = 128;
4277 env->icache_line_size = 128;
4278 /* Allocate hardware IRQ controller */
4279 ppc970_irq_init(env);
4280 }
4281
4282 /* PowerPC 970 GX */
4283 #define POWERPC_INSNS_970GX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4284 PPC_64B | PPC_ALTIVEC | \
4285 PPC_SEGMENT_64B | PPC_SLBI)
4286 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
4287 #define POWERPC_MMU_970GX (POWERPC_MMU_64B)
4288 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
4289 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
4290 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
4291 #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4292 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4293
4294 static int check_pow_970GX (CPUPPCState *env)
4295 {
4296 if (env->spr[SPR_HID0] & 0x00600000)
4297 return 1;
4298
4299 return 0;
4300 }
4301
4302 static void init_proc_970GX (CPUPPCState *env)
4303 {
4304 gen_spr_ne_601(env);
4305 gen_spr_7xx(env);
4306 /* Time base */
4307 gen_tbl(env);
4308 /* Hardware implementation registers */
4309 /* XXX : not implemented */
4310 spr_register(env, SPR_HID0, "HID0",
4311 SPR_NOACCESS, SPR_NOACCESS,
4312 &spr_read_generic, &spr_write_clear,
4313 0x60000000);
4314 /* XXX : not implemented */
4315 spr_register(env, SPR_HID1, "HID1",
4316 SPR_NOACCESS, SPR_NOACCESS,
4317 &spr_read_generic, &spr_write_generic,
4318 0x00000000);
4319 /* XXX : not implemented */
4320 spr_register(env, SPR_750_HID2, "HID2",
4321 SPR_NOACCESS, SPR_NOACCESS,
4322 &spr_read_generic, &spr_write_generic,
4323 0x00000000);
4324 /* XXX : not implemented */
4325 spr_register(env, SPR_970_HID5, "HID5",
4326 SPR_NOACCESS, SPR_NOACCESS,
4327 &spr_read_generic, &spr_write_generic,
4328 POWERPC970_HID5_INIT);
4329 /* Memory management */
4330 /* XXX: not correct */
4331 gen_low_BATs(env);
4332 /* XXX : not implemented */
4333 spr_register(env, SPR_MMUCFG, "MMUCFG",
4334 SPR_NOACCESS, SPR_NOACCESS,
4335 &spr_read_generic, SPR_NOACCESS,
4336 0x00000000); /* TOFIX */
4337 /* XXX : not implemented */
4338 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4339 SPR_NOACCESS, SPR_NOACCESS,
4340 &spr_read_generic, &spr_write_generic,
4341 0x00000000); /* TOFIX */
4342 spr_register(env, SPR_HIOR, "SPR_HIOR",
4343 SPR_NOACCESS, SPR_NOACCESS,
4344 &spr_read_generic, &spr_write_generic,
4345 0xFFF00000); /* XXX: This is a hack */
4346 #if !defined(CONFIG_USER_ONLY)
4347 env->slb_nr = 32;
4348 #endif
4349 init_excp_970(env);
4350 env->dcache_line_size = 128;
4351 env->icache_line_size = 128;
4352 /* Allocate hardware IRQ controller */
4353 ppc970_irq_init(env);
4354 }
4355
4356 /* PowerPC 970 MP */
4357 #define POWERPC_INSNS_970MP (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4358 PPC_64B | PPC_ALTIVEC | \
4359 PPC_SEGMENT_64B | PPC_SLBI)
4360 #define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
4361 #define POWERPC_MMU_970MP (POWERPC_MMU_64B)
4362 #define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
4363 #define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
4364 #define POWERPC_BFDM_970MP (bfd_mach_ppc64)
4365 #define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4366 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4367
4368 static int check_pow_970MP (CPUPPCState *env)
4369 {
4370 if (env->spr[SPR_HID0] & 0x01C00000)
4371 return 1;
4372
4373 return 0;
4374 }
4375
4376 static void init_proc_970MP (CPUPPCState *env)
4377 {
4378 gen_spr_ne_601(env);
4379 gen_spr_7xx(env);
4380 /* Time base */
4381 gen_tbl(env);
4382 /* Hardware implementation registers */
4383 /* XXX : not implemented */
4384 spr_register(env, SPR_HID0, "HID0",
4385 SPR_NOACCESS, SPR_NOACCESS,
4386 &spr_read_generic, &spr_write_clear,
4387 0x60000000);
4388 /* XXX : not implemented */
4389 spr_register(env, SPR_HID1, "HID1",
4390 SPR_NOACCESS, SPR_NOACCESS,
4391 &spr_read_generic, &spr_write_generic,
4392 0x00000000);
4393 /* XXX : not implemented */
4394 spr_register(env, SPR_750_HID2, "HID2",
4395 SPR_NOACCESS, SPR_NOACCESS,
4396 &spr_read_generic, &spr_write_generic,
4397 0x00000000);
4398 /* XXX : not implemented */
4399 spr_register(env, SPR_970_HID5, "HID5",
4400 SPR_NOACCESS, SPR_NOACCESS,
4401 &spr_read_generic, &spr_write_generic,
4402 POWERPC970_HID5_INIT);
4403 /* Memory management */
4404 /* XXX: not correct */
4405 gen_low_BATs(env);
4406 /* XXX : not implemented */
4407 spr_register(env, SPR_MMUCFG, "MMUCFG",
4408 SPR_NOACCESS, SPR_NOACCESS,
4409 &spr_read_generic, SPR_NOACCESS,
4410 0x00000000); /* TOFIX */
4411 /* XXX : not implemented */
4412 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4413 SPR_NOACCESS, SPR_NOACCESS,
4414 &spr_read_generic, &spr_write_generic,
4415 0x00000000); /* TOFIX */
4416 spr_register(env, SPR_HIOR, "SPR_HIOR",
4417 SPR_NOACCESS, SPR_NOACCESS,
4418 &spr_read_generic, &spr_write_generic,
4419 0xFFF00000); /* XXX: This is a hack */
4420 #if !defined(CONFIG_USER_ONLY)
4421 env->slb_nr = 32;
4422 #endif
4423 init_excp_970(env);
4424 env->dcache_line_size = 128;
4425 env->icache_line_size = 128;
4426 /* Allocate hardware IRQ controller */
4427 ppc970_irq_init(env);
4428 }
4429
4430 /* PowerPC 620 */
4431 #define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
4432 PPC_64B | PPC_SLBI)
4433 #define POWERPC_MSRM_620 (0x800000000005FF73ULL)
4434 #define POWERPC_MMU_620 (POWERPC_MMU_64B)
4435 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
4436 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
4437 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
4438 #define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE)
4439 #define check_pow_620 check_pow_nocheck /* Check this */
4440
4441 __attribute__ (( unused ))
4442 static void init_proc_620 (CPUPPCState *env)
4443 {
4444 gen_spr_ne_601(env);
4445 gen_spr_620(env);
4446 /* Time base */
4447 gen_tbl(env);
4448 /* Hardware implementation registers */
4449 /* XXX : not implemented */
4450 spr_register(env, SPR_HID0, "HID0",
4451 SPR_NOACCESS, SPR_NOACCESS,
4452 &spr_read_generic, &spr_write_generic,
4453 0x00000000);
4454 /* Memory management */
4455 gen_low_BATs(env);
4456 gen_high_BATs(env);
4457 init_excp_620(env);
4458 env->dcache_line_size = 64;
4459 env->icache_line_size = 64;
4460 /* Allocate hardware IRQ controller */
4461 ppc6xx_irq_init(env);
4462 }
4463 #endif /* defined (TARGET_PPC64) */
4464
4465 /* Default 32 bits PowerPC target will be 604 */
4466 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
4467 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
4468 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
4469 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
4470 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
4471 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
4472 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
4473 #define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
4474 #define check_pow_PPC32 check_pow_604
4475 #define init_proc_PPC32 init_proc_604
4476
4477 /* Default 64 bits PowerPC target will be 970 FX */
4478 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
4479 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
4480 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
4481 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
4482 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
4483 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
4484 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
4485 #define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
4486 #define check_pow_PPC64 check_pow_970FX
4487 #define init_proc_PPC64 init_proc_970FX
4488
4489 /* Default PowerPC target will be PowerPC 32 */
4490 #if defined (TARGET_PPC64) && 0 // XXX: TODO
4491 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
4492 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
4493 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
4494 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
4495 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
4496 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
4497 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
4498 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
4499 #define check_pow_DEFAULT check_pow_PPC64
4500 #define init_proc_DEFAULT init_proc_PPC64
4501 #else
4502 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
4503 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
4504 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
4505 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
4506 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
4507 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
4508 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
4509 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
4510 #define check_pow_DEFAULT check_pow_PPC32
4511 #define init_proc_DEFAULT init_proc_PPC32
4512 #endif
4513
4514 /*****************************************************************************/
4515 /* PVR definitions for most known PowerPC */
4516 enum {
4517 /* PowerPC 401 family */
4518 /* Generic PowerPC 401 */
4519 #define CPU_POWERPC_401 CPU_POWERPC_401G2
4520 /* PowerPC 401 cores */
4521 CPU_POWERPC_401A1 = 0x00210000,
4522 CPU_POWERPC_401B2 = 0x00220000,
4523 #if 0
4524 CPU_POWERPC_401B3 = xxx,
4525 #endif
4526 CPU_POWERPC_401C2 = 0x00230000,
4527 CPU_POWERPC_401D2 = 0x00240000,
4528 CPU_POWERPC_401E2 = 0x00250000,
4529 CPU_POWERPC_401F2 = 0x00260000,
4530 CPU_POWERPC_401G2 = 0x00270000,
4531 /* PowerPC 401 microcontrolers */
4532 #if 0
4533 CPU_POWERPC_401GF = xxx,
4534 #endif
4535 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
4536 /* IBM Processor for Network Resources */
4537 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
4538 #if 0
4539 CPU_POWERPC_XIPCHIP = xxx,
4540 #endif
4541 /* PowerPC 403 family */
4542 /* Generic PowerPC 403 */
4543 #define CPU_POWERPC_403 CPU_POWERPC_403GC
4544 /* PowerPC 403 microcontrollers */
4545 CPU_POWERPC_403GA = 0x00200011,
4546 CPU_POWERPC_403GB = 0x00200100,
4547 CPU_POWERPC_403GC = 0x00200200,
4548 CPU_POWERPC_403GCX = 0x00201400,
4549 #if 0
4550 CPU_POWERPC_403GP = xxx,
4551 #endif
4552 /* PowerPC 405 family */
4553 /* Generic PowerPC 405 */
4554 #define CPU_POWERPC_405 CPU_POWERPC_405D4
4555 /* PowerPC 405 cores */
4556 #if 0
4557 CPU_POWERPC_405A3 = xxx,
4558 #endif
4559 #if 0
4560 CPU_POWERPC_405A4 = xxx,
4561 #endif
4562 #if 0
4563 CPU_POWERPC_405B3 = xxx,
4564 #endif
4565 #if 0
4566 CPU_POWERPC_405B4 = xxx,
4567 #endif
4568 #if 0
4569 CPU_POWERPC_405C3 = xxx,
4570 #endif
4571 #if 0
4572 CPU_POWERPC_405C4 = xxx,
4573 #endif
4574 CPU_POWERPC_405D2 = 0x20010000,
4575 #if 0
4576 CPU_POWERPC_405D3 = xxx,
4577 #endif
4578 CPU_POWERPC_405D4 = 0x41810000,
4579 #if 0
4580 CPU_POWERPC_405D5 = xxx,
4581 #endif
4582 #if 0
4583 CPU_POWERPC_405E4 = xxx,
4584 #endif
4585 #if 0
4586 CPU_POWERPC_405F4 = xxx,
4587 #endif
4588 #if 0
4589 CPU_POWERPC_405F5 = xxx,
4590 #endif
4591 #if 0
4592 CPU_POWERPC_405F6 = xxx,
4593 #endif
4594 /* PowerPC 405 microcontrolers */
4595 /* XXX: missing 0x200108a0 */
4596 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
4597 CPU_POWERPC_405CRa = 0x40110041,
4598 CPU_POWERPC_405CRb = 0x401100C5,
4599 CPU_POWERPC_405CRc = 0x40110145,
4600 CPU_POWERPC_405EP = 0x51210950,
4601 #if 0
4602 CPU_POWERPC_405EXr = xxx,
4603 #endif
4604 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
4605 #if 0
4606 CPU_POWERPC_405FX = xxx,
4607 #endif
4608 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
4609 CPU_POWERPC_405GPa = 0x40110000,
4610 CPU_POWERPC_405GPb = 0x40110040,
4611 CPU_POWERPC_405GPc = 0x40110082,
4612 CPU_POWERPC_405GPd = 0x401100C4,
4613 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
4614 CPU_POWERPC_405GPR = 0x50910951,
4615 #if 0
4616 CPU_POWERPC_405H = xxx,
4617 #endif
4618 #if 0
4619 CPU_POWERPC_405L = xxx,
4620 #endif
4621 CPU_POWERPC_405LP = 0x41F10000,
4622 #if 0
4623 CPU_POWERPC_405PM = xxx,
4624 #endif
4625 #if 0
4626 CPU_POWERPC_405PS = xxx,
4627 #endif
4628 #if 0
4629 CPU_POWERPC_405S = xxx,
4630 #endif
4631 /* IBM network processors */
4632 CPU_POWERPC_NPE405H = 0x414100C0,
4633 CPU_POWERPC_NPE405H2 = 0x41410140,
4634 CPU_POWERPC_NPE405L = 0x416100C0,
4635 CPU_POWERPC_NPE4GS3 = 0x40B10000,
4636 #if 0
4637 CPU_POWERPC_NPCxx1 = xxx,
4638 #endif
4639 #if 0
4640 CPU_POWERPC_NPR161 = xxx,
4641 #endif
4642 #if 0
4643 CPU_POWERPC_LC77700 = xxx,
4644 #endif
4645 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
4646 #if 0
4647 CPU_POWERPC_STB01000 = xxx,
4648 #endif
4649 #if 0
4650 CPU_POWERPC_STB01010 = xxx,
4651 #endif
4652 #if 0
4653 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
4654 #endif
4655 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
4656 #if 0
4657 CPU_POWERPC_STB043 = xxx,
4658 #endif
4659 #if 0
4660 CPU_POWERPC_STB045 = xxx,
4661 #endif
4662 CPU_POWERPC_STB04 = 0x41810000,
4663 CPU_POWERPC_STB25 = 0x51510950,
4664 #if 0
4665 CPU_POWERPC_STB130 = xxx,
4666 #endif
4667 /* Xilinx cores */
4668 CPU_POWERPC_X2VP4 = 0x20010820,
4669 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
4670 CPU_POWERPC_X2VP20 = 0x20010860,
4671 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
4672 #if 0
4673 CPU_POWERPC_ZL10310 = xxx,
4674 #endif
4675 #if 0
4676 CPU_POWERPC_ZL10311 = xxx,
4677 #endif
4678 #if 0
4679 CPU_POWERPC_ZL10320 = xxx,
4680 #endif
4681 #if 0
4682 CPU_POWERPC_ZL10321 = xxx,
4683 #endif
4684 /* PowerPC 440 family */
4685 /* Generic PowerPC 440 */
4686 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
4687 /* PowerPC 440 cores */
4688 #if 0
4689 CPU_POWERPC_440A4 = xxx,
4690 #endif
4691 #if 0
4692 CPU_POWERPC_440A5 = xxx,
4693 #endif
4694 #if 0
4695 CPU_POWERPC_440B4 = xxx,
4696 #endif
4697 #if 0
4698 CPU_POWERPC_440F5 = xxx,
4699 #endif
4700 #if 0
4701 CPU_POWERPC_440G5 = xxx,
4702 #endif
4703 #if 0
4704 CPU_POWERPC_440H4 = xxx,
4705 #endif
4706 #if 0
4707 CPU_POWERPC_440H6 = xxx,
4708 #endif
4709 /* PowerPC 440 microcontrolers */
4710 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
4711 CPU_POWERPC_440EPa = 0x42221850,
4712 CPU_POWERPC_440EPb = 0x422218D3,
4713 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
4714 CPU_POWERPC_440GPb = 0x40120440,
4715 CPU_POWERPC_440GPc = 0x40120481,
4716 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
4717 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
4718 CPU_POWERPC_440GRX = 0x200008D0,
4719 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
4720 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
4721 CPU_POWERPC_440GXa = 0x51B21850,
4722 CPU_POWERPC_440GXb = 0x51B21851,
4723 CPU_POWERPC_440GXc = 0x51B21892,
4724 CPU_POWERPC_440GXf = 0x51B21894,
4725 #if 0
4726 CPU_POWERPC_440S = xxx,
4727 #endif
4728 CPU_POWERPC_440SP = 0x53221850,
4729 CPU_POWERPC_440SP2 = 0x53221891,
4730 CPU_POWERPC_440SPE = 0x53421890,
4731 /* PowerPC 460 family */
4732 #if 0
4733 /* Generic PowerPC 464 */
4734 #define CPU_POWERPC_464 CPU_POWERPC_464H90
4735 #endif
4736 /* PowerPC 464 microcontrolers */
4737 #if 0
4738 CPU_POWERPC_464H90 = xxx,
4739 #endif
4740 #if 0
4741 CPU_POWERPC_464H90FP = xxx,
4742 #endif
4743 /* Freescale embedded PowerPC cores */
4744 /* e200 family */
4745 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
4746 #if 0
4747 CPU_POWERPC_e200z0 = xxx,
4748 #endif
4749 #if 0
4750 CPU_POWERPC_e200z3 = xxx,
4751 #endif
4752 CPU_POWERPC_e200z5 = 0x81000000,
4753 CPU_POWERPC_e200z6 = 0x81120000,
4754 /* e300 family */
4755 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
4756 CPU_POWERPC_e300c1 = 0x00830000,
4757 CPU_POWERPC_e300c2 = 0x00840000,
4758 CPU_POWERPC_e300c3 = 0x00850000,
4759 /* e500 family */
4760 #define CPU_POWERPC_e500 CPU_POWERPC_e500_v22
4761 CPU_POWERPC_e500_v11 = 0x80200010,
4762 CPU_POWERPC_e500_v12 = 0x80200020,
4763 CPU_POWERPC_e500_v21 = 0x80210010,
4764 CPU_POWERPC_e500_v22 = 0x80210020,
4765 #if 0
4766 CPU_POWERPC_e500mc = xxx,
4767 #endif
4768 /* e600 family */
4769 CPU_POWERPC_e600 = 0x80040010,
4770 /* PowerPC MPC 5xx cores */
4771 CPU_POWERPC_5xx = 0x00020020,
4772 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
4773 CPU_POWERPC_8xx = 0x00500000,
4774 /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
4775 CPU_POWERPC_82xx_HIP3 = 0x00810101,
4776 CPU_POWERPC_82xx_HIP4 = 0x80811014,
4777 CPU_POWERPC_827x = 0x80822013,
4778 /* PowerPC 6xx cores */
4779 CPU_POWERPC_601 = 0x00010001,
4780 CPU_POWERPC_601a = 0x00010002,
4781 CPU_POWERPC_602 = 0x00050100,
4782 CPU_POWERPC_603 = 0x00030100,
4783 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
4784 CPU_POWERPC_603E_v11 = 0x00060101,
4785 CPU_POWERPC_603E_v12 = 0x00060102,
4786 CPU_POWERPC_603E_v13 = 0x00060103,
4787 CPU_POWERPC_603E_v14 = 0x00060104,
4788 CPU_POWERPC_603E_v22 = 0x00060202,
4789 CPU_POWERPC_603E_v3 = 0x00060300,
4790 CPU_POWERPC_603E_v4 = 0x00060400,
4791 CPU_POWERPC_603E_v41 = 0x00060401,
4792 CPU_POWERPC_603E7t = 0x00071201,
4793 CPU_POWERPC_603E7v = 0x00070100,
4794 CPU_POWERPC_603E7v1 = 0x00070101,
4795 CPU_POWERPC_603E7v2 = 0x00070201,
4796 CPU_POWERPC_603E7 = 0x00070200,
4797 CPU_POWERPC_603P = 0x00070000,
4798 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
4799 CPU_POWERPC_G2 = 0x00810011,
4800 #if 0 // Linux pretends the MSB is zero...
4801 CPU_POWERPC_G2H4 = 0x80811010,
4802 CPU_POWERPC_G2gp = 0x80821010,
4803 CPU_POWERPC_G2ls = 0x90810010,
4804 CPU_POWERPC_G2LE = 0x80820010,
4805 CPU_POWERPC_G2LEgp = 0x80822010,
4806 CPU_POWERPC_G2LEls = 0xA0822010,
4807 #else
4808 CPU_POWERPC_G2H4 = 0x00811010,
4809 CPU_POWERPC_G2gp = 0x00821010,
4810 CPU_POWERPC_G2ls = 0x10810010,
4811 CPU_POWERPC_G2LE = 0x00820010,
4812 CPU_POWERPC_G2LEgp = 0x00822010,
4813 CPU_POWERPC_G2LEls = 0x20822010,
4814 #endif
4815 CPU_POWERPC_604 = 0x00040103,
4816 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
4817 CPU_POWERPC_604E_v10 = 0x00090100, /* Also 2110 & 2120 */
4818 CPU_POWERPC_604E_v22 = 0x00090202,
4819 CPU_POWERPC_604E_v24 = 0x00090204,
4820 CPU_POWERPC_604R = 0x000a0101, /* Also 0x00093102 */
4821 #if 0
4822 CPU_POWERPC_604EV = xxx,
4823 #endif
4824 /* PowerPC 740/750 cores (aka G3) */
4825 /* XXX: missing 0x00084202 */
4826 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
4827 CPU_POWERPC_7x0_v20 = 0x00080200,
4828 CPU_POWERPC_7x0_v21 = 0x00080201,
4829 CPU_POWERPC_7x0_v22 = 0x00080202,
4830 CPU_POWERPC_7x0_v30 = 0x00080300,
4831 CPU_POWERPC_7x0_v31 = 0x00080301,
4832 CPU_POWERPC_740E = 0x00080100,
4833 CPU_POWERPC_7x0P = 0x10080000,
4834 /* XXX: missing 0x00087010 (CL ?) */
4835 CPU_POWERPC_750CL = 0x00087200,
4836 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
4837 CPU_POWERPC_750CX_v21 = 0x00082201,
4838 CPU_POWERPC_750CX_v22 = 0x00082202,
4839 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
4840 CPU_POWERPC_750CXE_v21 = 0x00082211,
4841 CPU_POWERPC_750CXE_v22 = 0x00082212,
4842 CPU_POWERPC_750CXE_v23 = 0x00082213,
4843 CPU_POWERPC_750CXE_v24 = 0x00082214,
4844 CPU_POWERPC_750CXE_v24b = 0x00083214,
4845 CPU_POWERPC_750CXE_v31 = 0x00083211,
4846 CPU_POWERPC_750CXE_v31b = 0x00083311,
4847 CPU_POWERPC_750CXR = 0x00083410,
4848 CPU_POWERPC_750E = 0x00080200,
4849 CPU_POWERPC_750FL = 0x700A0203,
4850 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
4851 CPU_POWERPC_750FX_v10 = 0x70000100,
4852 CPU_POWERPC_750FX_v20 = 0x70000200,
4853 CPU_POWERPC_750FX_v21 = 0x70000201,
4854 CPU_POWERPC_750FX_v22 = 0x70000202,
4855 CPU_POWERPC_750FX_v23 = 0x70000203,
4856 CPU_POWERPC_750GL = 0x70020102,
4857 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
4858 CPU_POWERPC_750GX_v10 = 0x70020100,
4859 CPU_POWERPC_750GX_v11 = 0x70020101,
4860 CPU_POWERPC_750GX_v12 = 0x70020102,
4861 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
4862 CPU_POWERPC_750L_v22 = 0x00088202,
4863 CPU_POWERPC_750L_v30 = 0x00088300,
4864 CPU_POWERPC_750L_v32 = 0x00088302,
4865 /* PowerPC 745/755 cores */
4866 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
4867 CPU_POWERPC_7x5_v10 = 0x00083100,
4868 CPU_POWERPC_7x5_v11 = 0x00083101,
4869 CPU_POWERPC_7x5_v20 = 0x00083200,
4870 CPU_POWERPC_7x5_v21 = 0x00083201,
4871 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
4872 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
4873 CPU_POWERPC_7x5_v24 = 0x00083204,
4874 CPU_POWERPC_7x5_v25 = 0x00083205,
4875 CPU_POWERPC_7x5_v26 = 0x00083206,
4876 CPU_POWERPC_7x5_v27 = 0x00083207,
4877 CPU_POWERPC_7x5_v28 = 0x00083208,
4878 #if 0
4879 CPU_POWERPC_7x5P = xxx,
4880 #endif
4881 /* PowerPC 74xx cores (aka G4) */
4882 /* XXX: missing 0x000C1101 */
4883 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
4884 CPU_POWERPC_7400_v10 = 0x000C0100,
4885 CPU_POWERPC_7400_v11 = 0x000C0101,
4886 CPU_POWERPC_7400_v20 = 0x000C0200,
4887 CPU_POWERPC_7400_v22 = 0x000C0202,
4888 CPU_POWERPC_7400_v26 = 0x000C0206,
4889 CPU_POWERPC_7400_v27 = 0x000C0207,
4890 CPU_POWERPC_7400_v28 = 0x000C0208,
4891 CPU_POWERPC_7400_v29 = 0x000C0209,
4892 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
4893 CPU_POWERPC_7410_v10 = 0x800C1100,
4894 CPU_POWERPC_7410_v11 = 0x800C1101,
4895 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
4896 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
4897 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
4898 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
4899 CPU_POWERPC_7448_v10 = 0x80040100,
4900 CPU_POWERPC_7448_v11 = 0x80040101,
4901 CPU_POWERPC_7448_v20 = 0x80040200,
4902 CPU_POWERPC_7448_v21 = 0x80040201,
4903 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
4904 CPU_POWERPC_7450_v10 = 0x80000100,
4905 CPU_POWERPC_7450_v11 = 0x80000101,
4906 CPU_POWERPC_7450_v12 = 0x80000102,
4907 CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
4908 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
4909 CPU_POWERPC_74x1 = 0x80000203,
4910 CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
4911 /* XXX: missing 0x80010200 */
4912 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
4913 CPU_POWERPC_74x5_v10 = 0x80010100,
4914 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
4915 CPU_POWERPC_74x5_v32 = 0x80010302,
4916 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
4917 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
4918 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
4919 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
4920 CPU_POWERPC_74x7_v11 = 0x80030101, /* aka B: 1.1 */
4921 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
4922 /* 64 bits PowerPC */
4923 #if defined(TARGET_PPC64)
4924 CPU_POWERPC_620 = 0x00140000,
4925 CPU_POWERPC_630 = 0x00400000,
4926 CPU_POWERPC_631 = 0x00410104,
4927 CPU_POWERPC_POWER4 = 0x00350000,
4928 CPU_POWERPC_POWER4P = 0x00380000,
4929 CPU_POWERPC_POWER5 = 0x003A0203,
4930 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
4931 CPU_POWERPC_POWER5P = 0x003B0000,
4932 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
4933 CPU_POWERPC_POWER6 = 0x003E0000,
4934 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 running POWER5 mode */
4935 CPU_POWERPC_POWER6A = 0x0F000002,
4936 CPU_POWERPC_970 = 0x00390202,
4937 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
4938 CPU_POWERPC_970FX_v10 = 0x00391100,
4939 CPU_POWERPC_970FX_v20 = 0x003C0200,
4940 CPU_POWERPC_970FX_v21 = 0x003C0201,
4941 CPU_POWERPC_970FX_v30 = 0x003C0300,
4942 CPU_POWERPC_970FX_v31 = 0x003C0301,
4943 CPU_POWERPC_970GX = 0x00450000,
4944 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
4945 CPU_POWERPC_970MP_v10 = 0x00440100,
4946 CPU_POWERPC_970MP_v11 = 0x00440101,
4947 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
4948 CPU_POWERPC_CELL_v10 = 0x00700100,
4949 CPU_POWERPC_CELL_v20 = 0x00700400,
4950 CPU_POWERPC_CELL_v30 = 0x00700500,
4951 CPU_POWERPC_CELL_v31 = 0x00700501,
4952 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
4953 CPU_POWERPC_RS64 = 0x00330000,
4954 CPU_POWERPC_RS64II = 0x00340000,
4955 CPU_POWERPC_RS64III = 0x00360000,
4956 CPU_POWERPC_RS64IV = 0x00370000,
4957 #endif /* defined(TARGET_PPC64) */
4958 /* Original POWER */
4959 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
4960 * POWER2 (RIOS2) & RSC2 (P2SC) here
4961 */
4962 #if 0
4963 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
4964 #endif
4965 #if 0
4966 CPU_POWER2 = xxx, /* 0x40000 ? */
4967 #endif
4968 /* PA Semi core */
4969 CPU_POWERPC_PA6T = 0x00900000,
4970 };
4971
4972 /* System version register (used on MPC 8xxx) */
4973 enum {
4974 PPC_SVR_8540 = 0x80300000,
4975 PPC_SVR_8541E = 0x807A0010,
4976 PPC_SVR_8543v10 = 0x80320010,
4977 PPC_SVR_8543v11 = 0x80320011,
4978 PPC_SVR_8543v20 = 0x80320020,
4979 PPC_SVR_8543Ev10 = 0x803A0010,
4980 PPC_SVR_8543Ev11 = 0x803A0011,
4981 PPC_SVR_8543Ev20 = 0x803A0020,
4982 PPC_SVR_8545 = 0x80310220,
4983 PPC_SVR_8545E = 0x80390220,
4984 PPC_SVR_8547E = 0x80390120,
4985 PPC_SCR_8548v10 = 0x80310010,
4986 PPC_SCR_8548v11 = 0x80310011,
4987 PPC_SCR_8548v20 = 0x80310020,
4988 PPC_SVR_8548Ev10 = 0x80390010,
4989 PPC_SVR_8548Ev11 = 0x80390011,
4990 PPC_SVR_8548Ev20 = 0x80390020,
4991 PPC_SVR_8555E = 0x80790010,
4992 PPC_SVR_8560v10 = 0x80700010,
4993 PPC_SVR_8560v20 = 0x80700020,
4994 };
4995
4996 /*****************************************************************************/
4997 /* PowerPC CPU definitions */
4998 #define POWERPC_DEF(_name, _pvr, _pvr_mask, _type) \
4999 { \
5000 .name = _name, \
5001 .pvr = _pvr, \
5002 .pvr_mask = _pvr_mask, \
5003 .insns_flags = glue(POWERPC_INSNS_,_type), \
5004 .msr_mask = glue(POWERPC_MSRM_,_type), \
5005 .mmu_model = glue(POWERPC_MMU_,_type), \
5006 .excp_model = glue(POWERPC_EXCP_,_type), \
5007 .bus_model = glue(POWERPC_INPUT_,_type), \
5008 .bfd_mach = glue(POWERPC_BFDM_,_type), \
5009 .flags = glue(POWERPC_FLAG_,_type), \
5010 .init_proc = &glue(init_proc_,_type), \
5011 .check_pow = &glue(check_pow_,_type), \
5012 }
5013
5014 static ppc_def_t ppc_defs[] = {
5015 /* Embedded PowerPC */
5016 /* PowerPC 401 family */
5017 /* Generic PowerPC 401 */
5018 POWERPC_DEF("401", CPU_POWERPC_401, 0xFFFF0000, 401),
5019 /* PowerPC 401 cores */
5020 /* PowerPC 401A1 */
5021 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 0xFFFFFFFF, 401),
5022 /* PowerPC 401B2 */
5023 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 0xFFFFFFFF, 401x2),
5024 #if defined (TODO)
5025 /* PowerPC 401B3 */
5026 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 0xFFFFFFFF, 401x3),
5027 #endif
5028 /* PowerPC 401C2 */
5029 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 0xFFFFFFFF, 401x2),
5030 /* PowerPC 401D2 */
5031 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 0xFFFFFFFF, 401x2),
5032 /* PowerPC 401E2 */
5033 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 0xFFFFFFFF, 401x2),
5034 /* PowerPC 401F2 */
5035 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 0xFFFFFFFF, 401x2),
5036 /* PowerPC 401G2 */
5037 /* XXX: to be checked */
5038 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 0xFFFFFFFF, 401x2),
5039 /* PowerPC 401 microcontrolers */
5040 #if defined (TODO)
5041 /* PowerPC 401GF */
5042 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 0xFFFFFFFF, 401),
5043 #endif
5044 /* IOP480 (401 microcontroler) */
5045 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, 0xFFFFFFFF, IOP480),
5046 /* IBM Processor for Network Resources */
5047 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 0xFFFFFFFF, 401),
5048 #if defined (TODO)
5049 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 0xFFFFFFFF, 401),
5050 #endif
5051 /* PowerPC 403 family */
5052 /* Generic PowerPC 403 */
5053 POWERPC_DEF("403", CPU_POWERPC_403, 0xFFFF0000, 403),
5054 /* PowerPC 403 microcontrolers */
5055 /* PowerPC 403 GA */
5056 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 0xFFFFFFFF, 403),
5057 /* PowerPC 403 GB */
5058 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 0xFFFFFFFF, 403),
5059 /* PowerPC 403 GC */
5060 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 0xFFFFFFFF, 403),
5061 /* PowerPC 403 GCX */
5062 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 0xFFFFFFFF, 403GCX),
5063 #if defined (TODO)
5064 /* PowerPC 403 GP */
5065 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 0xFFFFFFFF, 403),
5066 #endif
5067 /* PowerPC 405 family */
5068 /* Generic PowerPC 405 */
5069 POWERPC_DEF("405", CPU_POWERPC_405, 0xFFFF0000, 405),
5070 /* PowerPC 405 cores */
5071 #if defined (TODO)
5072 /* PowerPC 405 A3 */
5073 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 0xFFFFFFFF, 405),
5074 #endif
5075 #if defined (TODO)
5076 /* PowerPC 405 A4 */
5077 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 0xFFFFFFFF, 405),
5078 #endif
5079 #if defined (TODO)
5080 /* PowerPC 405 B3 */
5081 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 0xFFFFFFFF, 405),
5082 #endif
5083 #if defined (TODO)
5084 /* PowerPC 405 B4 */
5085 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 0xFFFFFFFF, 405),
5086 #endif
5087 #if defined (TODO)
5088 /* PowerPC 405 C3 */
5089 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 0xFFFFFFFF, 405),
5090 #endif
5091 #if defined (TODO)
5092 /* PowerPC 405 C4 */
5093 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 0xFFFFFFFF, 405),
5094 #endif
5095 /* PowerPC 405 D2 */
5096 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 0xFFFFFFFF, 405),
5097 #if defined (TODO)
5098 /* PowerPC 405 D3 */
5099 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 0xFFFFFFFF, 405),
5100 #endif
5101 /* PowerPC 405 D4 */
5102 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 0xFFFFFFFF, 405),
5103 #if defined (TODO)
5104 /* PowerPC 405 D5 */
5105 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 0xFFFFFFFF, 405),
5106 #endif
5107 #if defined (TODO)
5108 /* PowerPC 405 E4 */
5109 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 0xFFFFFFFF, 405),
5110 #endif
5111 #if defined (TODO)
5112 /* PowerPC 405 F4 */
5113 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 0xFFFFFFFF, 405),
5114 #endif
5115 #if defined (TODO)
5116 /* PowerPC 405 F5 */
5117 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 0xFFFFFFFF, 405),
5118 #endif
5119 #if defined (TODO)
5120 /* PowerPC 405 F6 */
5121 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 0xFFFFFFFF, 405),
5122 #endif
5123 /* PowerPC 405 microcontrolers */
5124 /* PowerPC 405 CR */
5125 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 0xFFFFFFFF, 405),
5126 /* PowerPC 405 CRa */
5127 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 0xFFFFFFFF, 405),
5128 /* PowerPC 405 CRb */
5129 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 0xFFFFFFFF, 405),
5130 /* PowerPC 405 CRc */
5131 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 0xFFFFFFFF, 405),
5132 /* PowerPC 405 EP */
5133 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 0xFFFFFFFF, 405),
5134 #if defined(TODO)
5135 /* PowerPC 405 EXr */
5136 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 0xFFFFFFFF, 405),
5137 #endif
5138 /* PowerPC 405 EZ */
5139 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 0xFFFFFFFF, 405),
5140 #if defined(TODO)
5141 /* PowerPC 405 FX */
5142 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 0xFFFFFFFF, 405),
5143 #endif
5144 /* PowerPC 405 GP */
5145 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 0xFFFFFFFF, 405),
5146 /* PowerPC 405 GPa */
5147 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 0xFFFFFFFF, 405),
5148 /* PowerPC 405 GPb */
5149 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 0xFFFFFFFF, 405),
5150 /* PowerPC 405 GPc */
5151 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 0xFFFFFFFF, 405),
5152 /* PowerPC 405 GPd */
5153 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 0xFFFFFFFF, 405),
5154 /* PowerPC 405 GPe */
5155 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 0xFFFFFFFF, 405),
5156 /* PowerPC 405 GPR */
5157 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 0xFFFFFFFF, 405),
5158 #if defined(TODO)
5159 /* PowerPC 405 H */
5160 POWERPC_DEF("405H", CPU_POWERPC_405H, 0xFFFFFFFF, 405),
5161 #endif
5162 #if defined(TODO)
5163 /* PowerPC 405 L */
5164 POWERPC_DEF("405L", CPU_POWERPC_405L, 0xFFFFFFFF, 405),
5165 #endif
5166 /* PowerPC 405 LP */
5167 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 0xFFFFFFFF, 405),
5168 #if defined(TODO)
5169 /* PowerPC 405 PM */
5170 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 0xFFFFFFFF, 405),
5171 #endif
5172 #if defined(TODO)
5173 /* PowerPC 405 PS */
5174 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 0xFFFFFFFF, 405),
5175 #endif
5176 #if defined(TODO)
5177 /* PowerPC 405 S */
5178 POWERPC_DEF("405S", CPU_POWERPC_405S, 0xFFFFFFFF, 405),
5179 #endif
5180 /* Npe405 H */
5181 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 0xFFFFFFFF, 405),
5182 /* Npe405 H2 */
5183 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 0xFFFFFFFF, 405),
5184 /* Npe405 L */
5185 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 0xFFFFFFFF, 405),
5186 /* Npe4GS3 */
5187 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 0xFFFFFFFF, 405),
5188 #if defined (TODO)
5189 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 0xFFFFFFFF, 405),
5190 #endif
5191 #if defined (TODO)
5192 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 0xFFFFFFFF, 405),
5193 #endif
5194 #if defined (TODO)
5195 /* PowerPC LC77700 (Sanyo) */
5196 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 0xFFFFFFFF, 405),
5197 #endif
5198 /* PowerPC 401/403/405 based set-top-box microcontrolers */
5199 #if defined (TODO)
5200 /* STB010000 */
5201 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 0xFFFFFFFF, 401x2),
5202 #endif
5203 #if defined (TODO)
5204 /* STB01010 */
5205 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 0xFFFFFFFF, 401x2),
5206 #endif
5207 #if defined (TODO)
5208 /* STB0210 */
5209 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 0xFFFFFFFF, 401x3),
5210 #endif
5211 /* STB03xx */
5212 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 0xFFFFFFFF, 405),
5213 #if defined (TODO)
5214 /* STB043x */
5215 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 0xFFFFFFFF, 405),
5216 #endif
5217 #if defined (TODO)
5218 /* STB045x */
5219 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 0xFFFFFFFF, 405),
5220 #endif
5221 /* STB04xx */
5222 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 0xFFFF0000, 405),
5223 /* STB25xx */
5224 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 0xFFFFFFFF, 405),
5225 #if defined (TODO)
5226 /* STB130 */
5227 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 0xFFFFFFFF, 405),
5228 #endif
5229 /* Xilinx PowerPC 405 cores */
5230 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 0xFFFFFFFF, 405),
5231 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 0xFFFFFFFF, 405),
5232 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 0xFFFFFFFF, 405),
5233 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 0xFFFFFFFF, 405),
5234 #if defined (TODO)
5235 /* Zarlink ZL10310 */
5236 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 0xFFFFFFFF, 405),
5237 #endif
5238 #if defined (TODO)
5239 /* Zarlink ZL10311 */
5240 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 0xFFFFFFFF, 405),
5241 #endif
5242 #if defined (TODO)
5243 /* Zarlink ZL10320 */
5244 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 0xFFFFFFFF, 405),
5245 #endif
5246 #if defined (TODO)
5247 /* Zarlink ZL10321 */
5248 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 0xFFFFFFFF, 405),
5249 #endif
5250 /* PowerPC 440 family */
5251 /* Generic PowerPC 440 */
5252 POWERPC_DEF("440", CPU_POWERPC_440, 0xFFFFFFFF, 440GP),
5253 /* PowerPC 440 cores */
5254 #if defined (TODO)
5255 /* PowerPC 440 A4 */
5256 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 0xFFFFFFFF, 440x4),
5257 #endif
5258 #if defined (TODO)
5259 /* PowerPC 440 A5 */
5260 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 0xFFFFFFFF, 440x5),
5261 #endif
5262 #if defined (TODO)
5263 /* PowerPC 440 B4 */
5264 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 0xFFFFFFFF, 440x4),
5265 #endif
5266 #if defined (TODO)
5267 /* PowerPC 440 G4 */
5268 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 0xFFFFFFFF, 440x4),
5269 #endif
5270 #if defined (TODO)
5271 /* PowerPC 440 F5 */
5272 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 0xFFFFFFFF, 440x5),
5273 #endif
5274 #if defined (TODO)
5275 /* PowerPC 440 G5 */
5276 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 0xFFFFFFFF, 440x5),
5277 #endif
5278 #if defined (TODO)
5279 /* PowerPC 440H4 */
5280 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 0xFFFFFFFF, 440x4),
5281 #endif
5282 #if defined (TODO)
5283 /* PowerPC 440H6 */
5284 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 0xFFFFFFFF, 440Gx5),
5285 #endif
5286 /* PowerPC 440 microcontrolers */
5287 /* PowerPC 440 EP */
5288 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 0xFFFFFFFF, 440EP),
5289 /* PowerPC 440 EPa */
5290 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 0xFFFFFFFF, 440EP),
5291 /* PowerPC 440 EPb */
5292 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 0xFFFFFFFF, 440EP),
5293 /* PowerPC 440 EPX */
5294 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 0xFFFFFFFF, 440EP),
5295 /* PowerPC 440 GP */
5296 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 0xFFFFFFFF, 440GP),
5297 /* PowerPC 440 GPb */
5298 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 0xFFFFFFFF, 440GP),
5299 /* PowerPC 440 GPc */
5300 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 0xFFFFFFFF, 440GP),
5301 /* PowerPC 440 GR */
5302 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 0xFFFFFFFF, 440x5),
5303 /* PowerPC 440 GRa */
5304 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 0xFFFFFFFF, 440x5),
5305 /* PowerPC 440 GRX */
5306 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 0xFFFFFFFF, 440x5),
5307 /* PowerPC 440 GX */
5308 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 0xFFFFFFFF, 440EP),
5309 /* PowerPC 440 GXa */
5310 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 0xFFFFFFFF, 440EP),
5311 /* PowerPC 440 GXb */
5312 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 0xFFFFFFFF, 440EP),
5313 /* PowerPC 440 GXc */
5314 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 0xFFFFFFFF, 440EP),
5315 /* PowerPC 440 GXf */
5316 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 0xFFFFFFFF, 440EP),
5317 #if defined(TODO)
5318 /* PowerPC 440 S */
5319 POWERPC_DEF("440S", CPU_POWERPC_440S, 0xFFFFFFFF, 440),
5320 #endif
5321 /* PowerPC 440 SP */
5322 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 0xFFFFFFFF, 440EP),
5323 /* PowerPC 440 SP2 */
5324 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 0xFFFFFFFF, 440EP),
5325 /* PowerPC 440 SPE */
5326 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 0xFFFFFFFF, 440EP),
5327 /* PowerPC 460 family */
5328 #if defined (TODO)
5329 /* Generic PowerPC 464 */
5330 POWERPC_DEF("464", CPU_POWERPC_464, 0xFFFFFFFF, 460),
5331 #endif
5332 /* PowerPC 464 microcontrolers */
5333 #if defined (TODO)
5334 /* PowerPC 464H90 */
5335 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 0xFFFFFFFF, 460),
5336 #endif
5337 #if defined (TODO)
5338 /* PowerPC 464H90F */
5339 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 0xFFFFFFFF, 460F),
5340 #endif
5341 /* Freescale embedded PowerPC cores */
5342 /* e200 family */
5343 #if defined (TODO)
5344 /* Generic PowerPC e200 core */
5345 POWERPC_DEF("e200", CPU_POWERPC_e200, 0xFFFFFFFF, e200),
5346 #endif
5347 #if defined (TODO)
5348 /* PowerPC e200z5 core */
5349 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, 0xFFFFFFFF, e200),
5350 #endif
5351 #if defined (TODO)
5352 /* PowerPC e200z6 core */
5353 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, 0xFFFFFFFF, e200),
5354 #endif
5355 /* e300 family */
5356 #if defined (TODO)
5357 /* Generic PowerPC e300 core */
5358 POWERPC_DEF("e300", CPU_POWERPC_e300, 0xFFFFFFFF, e300),
5359 #endif
5360 #if defined (TODO)
5361 /* PowerPC e300c1 core */
5362 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, 0xFFFFFFFF, e300),
5363 #endif
5364 #if defined (TODO)
5365 /* PowerPC e300c2 core */
5366 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, 0xFFFFFFFF, e300),
5367 #endif
5368 #if defined (TODO)
5369 /* PowerPC e300c3 core */
5370 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, 0xFFFFFFFF, e300),
5371 #endif
5372 /* e500 family */
5373 #if defined (TODO)
5374 /* PowerPC e500 core */
5375 POWERPC_DEF("e500", CPU_POWERPC_e500, 0xFFFFFFFF, e500),
5376 #endif
5377 #if defined (TODO)
5378 /* PowerPC e500 v1.1 core */
5379 POWERPC_DEF("e500v1.1", CPU_POWERPC_e500_v11, 0xFFFFFFFF, e500),
5380 #endif
5381 #if defined (TODO)
5382 /* PowerPC e500 v1.2 core */
5383 POWERPC_DEF("e500v1.2", CPU_POWERPC_e500_v12, 0xFFFFFFFF, e500),
5384 #endif
5385 #if defined (TODO)
5386 /* PowerPC e500 v2.1 core */
5387 POWERPC_DEF("e500v2.1", CPU_POWERPC_e500_v21, 0xFFFFFFFF, e500),
5388 #endif
5389 #if defined (TODO)
5390 /* PowerPC e500 v2.2 core */
5391 POWERPC_DEF("e500v2.2", CPU_POWERPC_e500_v22, 0xFFFFFFFF, e500),
5392 #endif
5393 /* e600 family */
5394 #if defined (TODO)
5395 /* PowerPC e600 core */
5396 POWERPC_DEF("e600", CPU_POWERPC_e600, 0xFFFFFFFF, e600),
5397 #endif
5398 /* PowerPC MPC 5xx cores */
5399 #if defined (TODO)
5400 /* PowerPC MPC 5xx */
5401 POWERPC_DEF("mpc5xx", CPU_POWERPC_5xx, 0xFFFFFFFF, 5xx),
5402 #endif
5403 /* PowerPC MPC 8xx cores */
5404 #if defined (TODO)
5405 /* PowerPC MPC 8xx */
5406 POWERPC_DEF("mpc8xx", CPU_POWERPC_8xx, 0xFFFFFFFF, 8xx),
5407 #endif
5408 /* PowerPC MPC 8xxx cores */
5409 #if defined (TODO)
5410 /* PowerPC MPC 82xx HIP3 */
5411 POWERPC_DEF("mpc82xxhip3", CPU_POWERPC_82xx_HIP3, 0xFFFFFFFF, 82xx),
5412 #endif
5413 #if defined (TODO)
5414 /* PowerPC MPC 82xx HIP4 */
5415 POWERPC_DEF("mpc82xxhip4", CPU_POWERPC_82xx_HIP4, 0xFFFFFFFF, 82xx),
5416 #endif
5417 #if defined (TODO)
5418 /* PowerPC MPC 827x */
5419 POWERPC_DEF("mpc827x", CPU_POWERPC_827x, 0xFFFFFFFF, 827x),
5420 #endif
5421
5422 /* 32 bits "classic" PowerPC */
5423 /* PowerPC 6xx family */
5424 /* PowerPC 601 */
5425 POWERPC_DEF("601", CPU_POWERPC_601, 0xFFFFFFFF, 601),
5426 /* PowerPC 601v2 */
5427 POWERPC_DEF("601a", CPU_POWERPC_601a, 0xFFFFFFFF, 601),
5428 /* PowerPC 602 */
5429 POWERPC_DEF("602", CPU_POWERPC_602, 0xFFFFFFFF, 602),
5430 /* PowerPC 603 */
5431 POWERPC_DEF("603", CPU_POWERPC_603, 0xFFFFFFFF, 603),
5432 /* Code name for PowerPC 603 */
5433 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 0xFFFFFFFF, 603),
5434 /* PowerPC 603e */
5435 POWERPC_DEF("603e", CPU_POWERPC_603E, 0xFFFFFFFF, 603E),
5436 /* Code name for PowerPC 603e */
5437 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 0xFFFFFFFF, 603E),
5438 /* PowerPC 603e v1.1 */
5439 POWERPC_DEF("603e1.1", CPU_POWERPC_603E_v11, 0xFFFFFFFF, 603E),
5440 /* PowerPC 603e v1.2 */
5441 POWERPC_DEF("603e1.2", CPU_POWERPC_603E_v12, 0xFFFFFFFF, 603E),
5442 /* PowerPC 603e v1.3 */
5443 POWERPC_DEF("603e1.3", CPU_POWERPC_603E_v13, 0xFFFFFFFF, 603E),
5444 /* PowerPC 603e v1.4 */
5445 POWERPC_DEF("603e1.4", CPU_POWERPC_603E_v14, 0xFFFFFFFF, 603E),
5446 /* PowerPC 603e v2.2 */
5447 POWERPC_DEF("603e2.2", CPU_POWERPC_603E_v22, 0xFFFFFFFF, 603E),
5448 /* PowerPC 603e v3 */
5449 POWERPC_DEF("603e3", CPU_POWERPC_603E_v3, 0xFFFFFFFF, 603E),
5450 /* PowerPC 603e v4 */
5451 POWERPC_DEF("603e4", CPU_POWERPC_603E_v4, 0xFFFFFFFF, 603E),
5452 /* PowerPC 603e v4.1 */
5453 POWERPC_DEF("603e4.1", CPU_POWERPC_603E_v41, 0xFFFFFFFF, 603E),
5454 /* PowerPC 603e */
5455 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 0xFFFFFFFF, 603E),
5456 /* PowerPC 603e7t */
5457 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 0xFFFFFFFF, 603E),
5458 /* PowerPC 603e7v */
5459 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E),
5460 /* Code name for PowerPC 603ev */
5461 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E),
5462 /* PowerPC 603e7v1 */
5463 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 0xFFFFFFFF, 603E),
5464 /* PowerPC 603e7v2 */
5465 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 0xFFFFFFFF, 603E),
5466 /* PowerPC 603p */
5467 /* to be checked */
5468 POWERPC_DEF("603p", CPU_POWERPC_603P, 0xFFFFFFFF, 603),
5469 /* PowerPC 603r */
5470 POWERPC_DEF("603r", CPU_POWERPC_603R, 0xFFFFFFFF, 603E),
5471 /* Code name for PowerPC 603r */
5472 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 0xFFFFFFFF, 603E),
5473 /* PowerPC G2 core */
5474 POWERPC_DEF("G2", CPU_POWERPC_G2, 0xFFFFFFFF, G2),
5475 /* PowerPC G2 H4 */
5476 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, 0xFFFFFFFF, G2),
5477 /* PowerPC G2 GP */
5478 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, 0xFFFFFFFF, G2),
5479 /* PowerPC G2 LS */
5480 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, 0xFFFFFFFF, G2),
5481 /* PowerPC G2LE */
5482 /* Same as G2, with little-endian mode support */
5483 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, 0xFFFFFFFF, G2LE),
5484 /* PowerPC G2LE GP */
5485 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, 0xFFFFFFFF, G2LE),
5486 /* PowerPC G2LE LS */
5487 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, 0xFFFFFFFF, G2LE),
5488 /* PowerPC 604 */
5489 POWERPC_DEF("604", CPU_POWERPC_604, 0xFFFFFFFF, 604),
5490 /* PowerPC 604e */
5491 POWERPC_DEF("604e", CPU_POWERPC_604E, 0xFFFFFFFF, 604),
5492 /* PowerPC 604e v1.0 */
5493 POWERPC_DEF("604e1.0", CPU_POWERPC_604E_v10, 0xFFFFFFFF, 604),
5494 /* PowerPC 604e v2.2 */
5495 POWERPC_DEF("604e2.2", CPU_POWERPC_604E_v22, 0xFFFFFFFF, 604),
5496 /* PowerPC 604e v2.4 */
5497 POWERPC_DEF("604e2.4", CPU_POWERPC_604E_v24, 0xFFFFFFFF, 604),
5498 /* PowerPC 604r */
5499 POWERPC_DEF("604r", CPU_POWERPC_604R, 0xFFFFFFFF, 604),
5500 #if defined(TODO)
5501 /* PowerPC 604ev */
5502 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 0xFFFFFFFF, 604),
5503 #endif
5504 /* PowerPC 7xx family */
5505 /* Generic PowerPC 740 (G3) */
5506 POWERPC_DEF("740", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5507 /* Generic PowerPC 750 (G3) */
5508 POWERPC_DEF("750", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5509 /* Code name for generic PowerPC 740/750 (G3) */
5510 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5511 /* PowerPC 740/750 is also known as G3 */
5512 POWERPC_DEF("G3", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5513 /* PowerPC 740 v2.0 (G3) */
5514 POWERPC_DEF("740v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0),
5515 /* PowerPC 750 v2.0 (G3) */
5516 POWERPC_DEF("750v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0),
5517 /* PowerPC 740 v2.1 (G3) */
5518 POWERPC_DEF("740v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0),
5519 /* PowerPC 750 v2.1 (G3) */
5520 POWERPC_DEF("750v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0),
5521 /* PowerPC 740 v2.2 (G3) */
5522 POWERPC_DEF("740v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0),
5523 /* PowerPC 750 v2.2 (G3) */
5524 POWERPC_DEF("750v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0),
5525 /* PowerPC 740 v3.0 (G3) */
5526 POWERPC_DEF("740v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0),
5527 /* PowerPC 750 v3.0 (G3) */
5528 POWERPC_DEF("750v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0),
5529 /* PowerPC 740 v3.1 (G3) */
5530 POWERPC_DEF("740v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0),
5531 /* PowerPC 750 v3.1 (G3) */
5532 POWERPC_DEF("750v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0),
5533 /* PowerPC 740E (G3) */
5534 POWERPC_DEF("740e", CPU_POWERPC_740E, 0xFFFFFFFF, 7x0),
5535 /* PowerPC 740P (G3) */
5536 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5537 /* PowerPC 750P (G3) */
5538 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5539 /* Code name for PowerPC 740P/750P (G3) */
5540 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5541 /* PowerPC 750CL (G3 embedded) */
5542 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 0xFFFFFFFF, 7x0),
5543 /* PowerPC 750CX (G3 embedded) */
5544 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 0xFFFFFFFF, 7x0),
5545 /* PowerPC 750CX v2.1 (G3 embedded) */
5546 POWERPC_DEF("750cx2.1", CPU_POWERPC_750CX_v21, 0xFFFFFFFF, 7x0),
5547 /* PowerPC 750CX v2.2 (G3 embedded) */
5548 POWERPC_DEF("750cx2.2", CPU_POWERPC_750CX_v22, 0xFFFFFFFF, 7x0),
5549 /* PowerPC 750CXe (G3 embedded) */
5550 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 0xFFFFFFFF, 7x0),
5551 /* PowerPC 750CXe v2.1 (G3 embedded) */
5552 POWERPC_DEF("750cxe21", CPU_POWERPC_750CXE_v21, 0xFFFFFFFF, 7x0),
5553 /* PowerPC 750CXe v2.2 (G3 embedded) */
5554 POWERPC_DEF("750cxe22", CPU_POWERPC_750CXE_v22, 0xFFFFFFFF, 7x0),
5555 /* PowerPC 750CXe v2.3 (G3 embedded) */
5556 POWERPC_DEF("750cxe23", CPU_POWERPC_750CXE_v23, 0xFFFFFFFF, 7x0),
5557 /* PowerPC 750CXe v2.4 (G3 embedded) */
5558 POWERPC_DEF("750cxe24", CPU_POWERPC_750CXE_v24, 0xFFFFFFFF, 7x0),
5559 /* PowerPC 750CXe v2.4b (G3 embedded) */
5560 POWERPC_DEF("750cxe24b", CPU_POWERPC_750CXE_v24b, 0xFFFFFFFF, 7x0),
5561 /* PowerPC 750CXe v3.1 (G3 embedded) */
5562 POWERPC_DEF("750cxe31", CPU_POWERPC_750CXE_v31, 0xFFFFFFFF, 7x0),
5563 /* PowerPC 750CXe v3.1b (G3 embedded) */
5564 POWERPC_DEF("750cxe3.1b", CPU_POWERPC_750CXE_v31b, 0xFFFFFFFF, 7x0),
5565 /* PowerPC 750CXr (G3 embedded) */
5566 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 0xFFFFFFFF, 7x0),
5567 /* PowerPC 750E (G3) */
5568 POWERPC_DEF("750e", CPU_POWERPC_750E, 0xFFFFFFFF, 7x0),
5569 /* PowerPC 750FL (G3 embedded) */
5570 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 0xFFFFFFFF, 750fx),
5571 /* PowerPC 750FX (G3 embedded) */
5572 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 0xFFFFFFFF, 750fx),
5573 /* PowerPC 750FX v1.0 (G3 embedded) */
5574 POWERPC_DEF("750fx1.0", CPU_POWERPC_750FX_v10, 0xFFFFFFFF, 750fx),
5575 /* PowerPC 750FX v2.0 (G3 embedded) */
5576 POWERPC_DEF("750fx2.0", CPU_POWERPC_750FX_v20, 0xFFFFFFFF, 750fx),
5577 /* PowerPC 750FX v2.1 (G3 embedded) */
5578 POWERPC_DEF("750fx2.1", CPU_POWERPC_750FX_v21, 0xFFFFFFFF, 750fx),
5579 /* PowerPC 750FX v2.2 (G3 embedded) */
5580 POWERPC_DEF("750fx2.2", CPU_POWERPC_750FX_v22, 0xFFFFFFFF, 750fx),
5581 /* PowerPC 750FX v2.3 (G3 embedded) */
5582 POWERPC_DEF("750fx2.3", CPU_POWERPC_750FX_v23, 0xFFFFFFFF, 750fx),
5583 /* PowerPC 750GL (G3 embedded) */
5584 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 0xFFFFFFFF, 750fx),
5585 /* PowerPC 750GX (G3 embedded) */
5586 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 0xFFFFFFFF, 750fx),
5587 /* PowerPC 750GX v1.0 (G3 embedded) */
5588 POWERPC_DEF("750gx1.0", CPU_POWERPC_750GX_v10, 0xFFFFFFFF, 750fx),
5589 /* PowerPC 750GX v1.1 (G3 embedded) */
5590 POWERPC_DEF("750gx1.1", CPU_POWERPC_750GX_v11, 0xFFFFFFFF, 750fx),
5591 /* PowerPC 750GX v1.2 (G3 embedded) */
5592 POWERPC_DEF("750gx1.2", CPU_POWERPC_750GX_v12, 0xFFFFFFFF, 750fx),
5593 /* PowerPC 750L (G3 embedded) */
5594 POWERPC_DEF("750l", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0),
5595 /* Code name for PowerPC 750L (G3 embedded) */
5596 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0),
5597 /* PowerPC 750L v2.2 (G3 embedded) */
5598 POWERPC_DEF("750l2.2", CPU_POWERPC_750L_v22, 0xFFFFFFFF, 7x0),
5599 /* PowerPC 750L v3.0 (G3 embedded) */
5600 POWERPC_DEF("750l3.0", CPU_POWERPC_750L_v30, 0xFFFFFFFF, 7x0),
5601 /* PowerPC 750L v3.2 (G3 embedded) */
5602 POWERPC_DEF("750l3.2", CPU_POWERPC_750L_v32, 0xFFFFFFFF, 7x0),
5603 /* Generic PowerPC 745 */
5604 POWERPC_DEF("745", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5605 /* Generic PowerPC 755 */
5606 POWERPC_DEF("755", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5607 /* Code name for PowerPC 745/755 */
5608 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5609 /* PowerPC 745 v1.0 */
5610 POWERPC_DEF("745v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5),
5611 /* PowerPC 755 v1.0 */
5612 POWERPC_DEF("755v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5),
5613 /* PowerPC 745 v1.1 */
5614 POWERPC_DEF("745v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5),
5615 /* PowerPC 755 v1.1 */
5616 POWERPC_DEF("755v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5),
5617 /* PowerPC 745 v2.0 */
5618 POWERPC_DEF("745v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5),
5619 /* PowerPC 755 v2.0 */
5620 POWERPC_DEF("755v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5),
5621 /* PowerPC 745 v2.1 */
5622 POWERPC_DEF("745v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5),
5623 /* PowerPC 755 v2.1 */
5624 POWERPC_DEF("755v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5),
5625 /* PowerPC 745 v2.2 */
5626 POWERPC_DEF("745v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5),
5627 /* PowerPC 755 v2.2 */
5628 POWERPC_DEF("755v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5),
5629 /* PowerPC 745 v2.3 */
5630 POWERPC_DEF("745v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5),
5631 /* PowerPC 755 v2.3 */
5632 POWERPC_DEF("755v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5),
5633 /* PowerPC 745 v2.4 */
5634 POWERPC_DEF("745v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5),
5635 /* PowerPC 755 v2.4 */
5636 POWERPC_DEF("755v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5),
5637 /* PowerPC 745 v2.5 */
5638 POWERPC_DEF("745v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5),
5639 /* PowerPC 755 v2.5 */
5640 POWERPC_DEF("755v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5),
5641 /* PowerPC 745 v2.6 */
5642 POWERPC_DEF("745v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5),
5643 /* PowerPC 755 v2.6 */
5644 POWERPC_DEF("755v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5),
5645 /* PowerPC 745 v2.7 */
5646 POWERPC_DEF("745v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5),
5647 /* PowerPC 755 v2.7 */
5648 POWERPC_DEF("755v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5),
5649 /* PowerPC 745 v2.8 */
5650 POWERPC_DEF("745v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5),
5651 /* PowerPC 755 v2.8 */
5652 POWERPC_DEF("755v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5),
5653 #if defined (TODO)
5654 /* PowerPC 745P (G3) */
5655 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5),
5656 /* PowerPC 755P (G3) */
5657 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5),
5658 #endif
5659 /* PowerPC 74xx family */
5660 /* PowerPC 7400 (G4) */
5661 POWERPC_DEF("7400", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5662 /* Code name for PowerPC 7400 */
5663 POWERPC_DEF("Max", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5664 /* PowerPC 74xx is also well known as G4 */
5665 POWERPC_DEF("G4", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5666 /* PowerPC 7400 v1.0 (G4) */
5667 POWERPC_DEF("7400v1.0", CPU_POWERPC_7400_v10, 0xFFFFFFFF, 7400),
5668 /* PowerPC 7400 v1.1 (G4) */
5669 POWERPC_DEF("7400v1.1", CPU_POWERPC_7400_v11, 0xFFFFFFFF, 7400),
5670 /* PowerPC 7400 v2.0 (G4) */
5671 POWERPC_DEF("7400v2.0", CPU_POWERPC_7400_v20, 0xFFFFFFFF, 7400),
5672 /* PowerPC 7400 v2.2 (G4) */
5673 POWERPC_DEF("7400v2.2", CPU_POWERPC_7400_v22, 0xFFFFFFFF, 7400),
5674 /* PowerPC 7400 v2.6 (G4) */
5675 POWERPC_DEF("7400v2.6", CPU_POWERPC_7400_v26, 0xFFFFFFFF, 7400),
5676 /* PowerPC 7400 v2.7 (G4) */
5677 POWERPC_DEF("7400v2.7", CPU_POWERPC_7400_v27, 0xFFFFFFFF, 7400),
5678 /* PowerPC 7400 v2.8 (G4) */
5679 POWERPC_DEF("7400v2.8", CPU_POWERPC_7400_v28, 0xFFFFFFFF, 7400),
5680 /* PowerPC 7400 v2.9 (G4) */
5681 POWERPC_DEF("7400v2.9", CPU_POWERPC_7400_v29, 0xFFFFFFFF, 7400),
5682 /* PowerPC 7410 (G4) */
5683 POWERPC_DEF("7410", CPU_POWERPC_7410, 0xFFFFFFFF, 7410),
5684 /* Code name for PowerPC 7410 */
5685 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 0xFFFFFFFF, 7410),
5686 /* PowerPC 7410 v1.0 (G4) */
5687 POWERPC_DEF("7410v1.0", CPU_POWERPC_7410_v10, 0xFFFFFFFF, 7410),
5688 /* PowerPC 7410 v1.1 (G4) */
5689 POWERPC_DEF("7410v1.1", CPU_POWERPC_7410_v11, 0xFFFFFFFF, 7410),
5690 /* PowerPC 7410 v1.2 (G4) */
5691 POWERPC_DEF("7410v1.2", CPU_POWERPC_7410_v12, 0xFFFFFFFF, 7410),
5692 /* PowerPC 7410 v1.3 (G4) */
5693 POWERPC_DEF("7410v1.3", CPU_POWERPC_7410_v13, 0xFFFFFFFF, 7410),
5694 /* PowerPC 7410 v1.4 (G4) */
5695 POWERPC_DEF("7410v1.4", CPU_POWERPC_7410_v14, 0xFFFFFFFF, 7410),
5696 /* PowerPC 7448 (G4) */
5697 POWERPC_DEF("7448", CPU_POWERPC_7448, 0xFFFFFFFF, 7400),
5698 /* PowerPC 7448 v1.0 (G4) */
5699 POWERPC_DEF("7448v1.0", CPU_POWERPC_7448_v10, 0xFFFFFFFF, 7400),
5700 /* PowerPC 7448 v1.1 (G4) */
5701 POWERPC_DEF("7448v1.1", CPU_POWERPC_7448_v11, 0xFFFFFFFF, 7400),
5702 /* PowerPC 7448 v2.0 (G4) */
5703 POWERPC_DEF("7448v2.0", CPU_POWERPC_7448_v20, 0xFFFFFFFF, 7400),
5704 /* PowerPC 7448 v2.1 (G4) */
5705 POWERPC_DEF("7448v2.1", CPU_POWERPC_7448_v21, 0xFFFFFFFF, 7400),
5706 /* PowerPC 7450 (G4) */
5707 POWERPC_DEF("7450", CPU_POWERPC_7450, 0xFFFFFFFF, 7450),
5708 /* Code name for PowerPC 7450 */
5709 POWERPC_DEF("Vger", CPU_POWERPC_7450, 0xFFFFFFFF, 7450),
5710 /* PowerPC 7450 v1.0 (G4) */
5711 POWERPC_DEF("7450v1.0", CPU_POWERPC_7450_v10, 0xFFFFFFFF, 7450),
5712 /* PowerPC 7450 v1.1 (G4) */
5713 POWERPC_DEF("7450v1.1", CPU_POWERPC_7450_v11, 0xFFFFFFFF, 7450),
5714 /* PowerPC 7450 v1.2 (G4) */
5715 POWERPC_DEF("7450v1.2", CPU_POWERPC_7450_v12, 0xFFFFFFFF, 7450),
5716 /* PowerPC 7450 v2.0 (G4) */
5717 POWERPC_DEF("7450v2.0", CPU_POWERPC_7450_v20, 0xFFFFFFFF, 7450),
5718 /* PowerPC 7450 v2.1 (G4) */
5719 POWERPC_DEF("7450v2.1", CPU_POWERPC_7450_v21, 0xFFFFFFFF, 7450),
5720 /* PowerPC 7441 (G4) */
5721 POWERPC_DEF("7441", CPU_POWERPC_74x1, 0xFFFFFFFF, 7440),
5722 /* PowerPC 7451 (G4) */
5723 POWERPC_DEF("7451", CPU_POWERPC_74x1, 0xFFFFFFFF, 7450),
5724 /* PowerPC 7441g (G4) */
5725 POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7440),
5726 /* PowerPC 7451g (G4) */
5727 POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7450),
5728 /* PowerPC 7445 (G4) */
5729 POWERPC_DEF("7445", CPU_POWERPC_74x5, 0xFFFFFFFF, 7445),
5730 /* PowerPC 7455 (G4) */
5731 POWERPC_DEF("7455", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455),
5732 /* Code name for PowerPC 7445/7455 */
5733 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455),
5734 /* PowerPC 7445 v1.0 (G4) */
5735 POWERPC_DEF("7445v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7445),
5736 /* PowerPC 7455 v1.0 (G4) */
5737 POWERPC_DEF("7455v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7455),
5738 /* PowerPC 7445 v2.1 (G4) */
5739 POWERPC_DEF("7445v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7445),
5740 /* PowerPC 7455 v2.1 (G4) */
5741 POWERPC_DEF("7455v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7455),
5742 /* PowerPC 7445 v3.2 (G4) */
5743 POWERPC_DEF("7445v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7445),
5744 /* PowerPC 7455 v3.2 (G4) */
5745 POWERPC_DEF("7455v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7455),
5746 /* PowerPC 7445 v3.3 (G4) */
5747 POWERPC_DEF("7445v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7445),
5748 /* PowerPC 7455 v3.3 (G4) */
5749 POWERPC_DEF("7455v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7455),
5750 /* PowerPC 7445 v3.4 (G4) */
5751 POWERPC_DEF("7445v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7445),
5752 /* PowerPC 7455 v3.4 (G4) */
5753 POWERPC_DEF("7455v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7455),
5754 /* PowerPC 7447 (G4) */
5755 POWERPC_DEF("7447", CPU_POWERPC_74x7, 0xFFFFFFFF, 7445),
5756 /* PowerPC 7457 (G4) */
5757 POWERPC_DEF("7457", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455),
5758 /* Code name for PowerPC 7447/7457 */
5759 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455),
5760 /* PowerPC 7447 v1.0 (G4) */
5761 POWERPC_DEF("7447v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7445),
5762 /* PowerPC 7457 v1.0 (G4) */
5763 POWERPC_DEF("7457v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455),
5764 /* Code name for PowerPC 7447A/7457A */
5765 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455),
5766 /* PowerPC 7447 v1.1 (G4) */
5767 POWERPC_DEF("7447v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7445),
5768 /* PowerPC 7457 v1.1 (G4) */
5769 POWERPC_DEF("7457v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7455),
5770 /* PowerPC 7447 v1.2 (G4) */
5771 POWERPC_DEF("7447v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7445),
5772 /* PowerPC 7457 v1.2 (G4) */
5773 POWERPC_DEF("7457v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7455),
5774 /* 64 bits PowerPC */
5775 #if defined (TARGET_PPC64)
5776 /* PowerPC 620 */
5777 POWERPC_DEF("620", CPU_POWERPC_620, 0xFFFFFFFF, 620),
5778 #if defined (TODO)
5779 /* PowerPC 630 (POWER3) */
5780 POWERPC_DEF("630", CPU_POWERPC_630, 0xFFFFFFFF, 630),
5781 POWERPC_DEF("POWER3", CPU_POWERPC_630, 0xFFFFFFFF, 630),
5782 #endif
5783 #if defined (TODO)
5784 /* PowerPC 631 (Power 3+) */
5785 POWERPC_DEF("631", CPU_POWERPC_631, 0xFFFFFFFF, 631),
5786 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 0xFFFFFFFF, 631),
5787 #endif
5788 #if defined (TODO)
5789 /* POWER4 */
5790 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, 0xFFFFFFFF, POWER4),
5791 #endif
5792 #if defined (TODO)
5793 /* POWER4p */
5794 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, 0xFFFFFFFF, POWER4P),
5795 #endif
5796 #if defined (TODO)
5797 /* POWER5 */
5798 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, 0xFFFFFFFF, POWER5),
5799 /* POWER5GR */
5800 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, 0xFFFFFFFF, POWER5),
5801 #endif
5802 #if defined (TODO)
5803 /* POWER5+ */
5804 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, 0xFFFFFFFF, POWER5P),
5805 /* POWER5GS */
5806 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, 0xFFFFFFFF, POWER5P),
5807 #endif
5808 #if defined (TODO)
5809 /* POWER6 */
5810 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, 0xFFFFFFFF, POWER6),
5811 /* POWER6 running in POWER5 mode */
5812 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, 0xFFFFFFFF, POWER5),
5813 /* POWER6A */
5814 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, 0xFFFFFFFF, POWER6),
5815 #endif
5816 /* PowerPC 970 */
5817 POWERPC_DEF("970", CPU_POWERPC_970, 0xFFFFFFFF, 970),
5818 /* PowerPC 970FX (G5) */
5819 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 0xFFFFFFFF, 970FX),
5820 /* PowerPC 970FX v1.0 (G5) */
5821 POWERPC_DEF("970fx1.0", CPU_POWERPC_970FX_v10, 0xFFFFFFFF, 970FX),
5822 /* PowerPC 970FX v2.0 (G5) */
5823 POWERPC_DEF("970fx2.0", CPU_POWERPC_970FX_v20, 0xFFFFFFFF, 970FX),
5824 /* PowerPC 970FX v2.1 (G5) */
5825 POWERPC_DEF("970fx2.1", CPU_POWERPC_970FX_v21, 0xFFFFFFFF, 970FX),
5826 /* PowerPC 970FX v3.0 (G5) */
5827 POWERPC_DEF("970fx3.0", CPU_POWERPC_970FX_v30, 0xFFFFFFFF, 970FX),
5828 /* PowerPC 970FX v3.1 (G5) */
5829 POWERPC_DEF("970fx3.1", CPU_POWERPC_970FX_v31, 0xFFFFFFFF, 970FX),
5830 /* PowerPC 970GX (G5) */
5831 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 0xFFFFFFFF, 970GX),
5832 /* PowerPC 970MP */
5833 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 0xFFFFFFFF, 970MP),
5834 /* PowerPC 970MP v1.0 */
5835 POWERPC_DEF("970mp1.0", CPU_POWERPC_970MP_v10, 0xFFFFFFFF, 970MP),
5836 /* PowerPC 970MP v1.1 */
5837 POWERPC_DEF("970mp1.1", CPU_POWERPC_970MP_v11, 0xFFFFFFFF, 970MP),
5838 #if defined (TODO)
5839 /* PowerPC Cell */
5840 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 0xFFFFFFFF, 970),
5841 #endif
5842 #if defined (TODO)
5843 /* PowerPC Cell v1.0 */
5844 POWERPC_DEF("Cell1.0", CPU_POWERPC_CELL_v10, 0xFFFFFFFF, 970),
5845 #endif
5846 #if defined (TODO)
5847 /* PowerPC Cell v2.0 */
5848 POWERPC_DEF("Cell2.0", CPU_POWERPC_CELL_v20, 0xFFFFFFFF, 970),
5849 #endif
5850 #if defined (TODO)
5851 /* PowerPC Cell v3.0 */
5852 POWERPC_DEF("Cell3.0", CPU_POWERPC_CELL_v30, 0xFFFFFFFF, 970),
5853 #endif
5854 #if defined (TODO)
5855 /* PowerPC Cell v3.1 */
5856 POWERPC_DEF("Cell3.1", CPU_POWERPC_CELL_v31, 0xFFFFFFFF, 970),
5857 #endif
5858 #if defined (TODO)
5859 /* PowerPC Cell v3.2 */
5860 POWERPC_DEF("Cell3.2", CPU_POWERPC_CELL_v32, 0xFFFFFFFF, 970),
5861 #endif
5862 #if defined (TODO)
5863 /* RS64 (Apache/A35) */
5864 /* This one seems to support the whole POWER2 instruction set
5865 * and the PowerPC 64 one.
5866 */
5867 /* What about A10 & A30 ? */
5868 POWERPC_DEF("RS64", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
5869 POWERPC_DEF("Apache", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
5870 POWERPC_DEF("A35", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
5871 #endif
5872 #if defined (TODO)
5873 /* RS64-II (NorthStar/A50) */
5874 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
5875 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
5876 POWERPC_DEF("A50", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
5877 #endif
5878 #if defined (TODO)
5879 /* RS64-III (Pulsar) */
5880 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64),
5881 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64),
5882 #endif
5883 #if defined (TODO)
5884 /* RS64-IV (IceStar/IStar/SStar) */
5885 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5886 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5887 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5888 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5889 #endif
5890 #endif /* defined (TARGET_PPC64) */
5891 /* POWER */
5892 #if defined (TODO)
5893 /* Original POWER */
5894 POWERPC_DEF("POWER", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5895 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5896 POWERPC_DEF("RSC", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5897 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5898 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5899 #endif
5900 #if defined (TODO)
5901 /* POWER2 */
5902 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5903 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5904 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5905 #endif
5906 /* PA semi cores */
5907 #if defined (TODO)
5908 /* PA PA6T */
5909 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, 0xFFFFFFFF, PA6T),
5910 #endif
5911 /* Generic PowerPCs */
5912 #if defined (TARGET_PPC64)
5913 #if defined (TODO)
5914 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, 0xFFFFFFFF, PPC64),
5915 #endif
5916 #endif
5917 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, 0xFFFFFFFF, PPC32),
5918 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, 0xFFFFFFFF, DEFAULT),
5919 /* Fallback */
5920 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, 0xFFFFFFFF, DEFAULT),
5921 };
5922
5923 /*****************************************************************************/
5924 /* Generic CPU instanciation routine */
5925 static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
5926 {
5927 #if !defined(CONFIG_USER_ONLY)
5928 int i;
5929
5930 env->irq_inputs = NULL;
5931 /* Set all exception vectors to an invalid address */
5932 for (i = 0; i < POWERPC_EXCP_NB; i++)
5933 env->excp_vectors[i] = (target_ulong)(-1ULL);
5934 env->excp_prefix = 0x00000000;
5935 env->ivor_mask = 0x00000000;
5936 env->ivpr_mask = 0x00000000;
5937 /* Default MMU definitions */
5938 env->nb_BATs = 0;
5939 env->nb_tlb = 0;
5940 env->nb_ways = 0;
5941 #endif
5942 /* Register SPR common to all PowerPC implementations */
5943 gen_spr_generic(env);
5944 spr_register(env, SPR_PVR, "PVR",
5945 SPR_NOACCESS, SPR_NOACCESS,
5946 &spr_read_generic, SPR_NOACCESS,
5947 def->pvr);
5948 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
5949 (*def->init_proc)(env);
5950 /* MSR bits & flags consistency checks */
5951 if (env->msr_mask & (1 << 25)) {
5952 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
5953 case POWERPC_FLAG_SPE:
5954 case POWERPC_FLAG_VRE:
5955 break;
5956 default:
5957 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5958 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
5959 exit(1);
5960 }
5961 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
5962 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5963 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
5964 exit(1);
5965 }
5966 if (env->msr_mask & (1 << 17)) {
5967 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
5968 case POWERPC_FLAG_TGPR:
5969 case POWERPC_FLAG_CE:
5970 break;
5971 default:
5972 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5973 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
5974 exit(1);
5975 }
5976 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
5977 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5978 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
5979 exit(1);
5980 }
5981 if (env->msr_mask & (1 << 10)) {
5982 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
5983 POWERPC_FLAG_UBLE)) {
5984 case POWERPC_FLAG_SE:
5985 case POWERPC_FLAG_DWE:
5986 case POWERPC_FLAG_UBLE:
5987 break;
5988 default:
5989 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5990 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
5991 "POWERPC_FLAG_UBLE\n");
5992 exit(1);
5993 }
5994 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
5995 POWERPC_FLAG_UBLE)) {
5996 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5997 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
5998 "POWERPC_FLAG_UBLE\n");
5999 exit(1);
6000 }
6001 if (env->msr_mask & (1 << 9)) {
6002 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6003 case POWERPC_FLAG_BE:
6004 case POWERPC_FLAG_DE:
6005 break;
6006 default:
6007 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6008 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
6009 exit(1);
6010 }
6011 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6012 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6013 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
6014 exit(1);
6015 }
6016 if (env->msr_mask & (1 << 2)) {
6017 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6018 case POWERPC_FLAG_PX:
6019 case POWERPC_FLAG_PMM:
6020 break;
6021 default:
6022 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6023 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
6024 exit(1);
6025 }
6026 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6027 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6028 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
6029 exit(1);
6030 }
6031 /* Allocate TLBs buffer when needed */
6032 #if !defined(CONFIG_USER_ONLY)
6033 if (env->nb_tlb != 0) {
6034 int nb_tlb = env->nb_tlb;
6035 if (env->id_tlbs != 0)
6036 nb_tlb *= 2;
6037 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
6038 /* Pre-compute some useful values */
6039 env->tlb_per_way = env->nb_tlb / env->nb_ways;
6040 }
6041 if (env->irq_inputs == NULL) {
6042 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
6043 " Attempt Qemu to crash very soon !\n");
6044 }
6045 #endif
6046 if (env->check_pow == NULL) {
6047 fprintf(stderr, "WARNING: no power management check handler "
6048 "registered.\n"
6049 " Attempt Qemu to crash very soon !\n");
6050 }
6051 }
6052
6053 #if defined(PPC_DUMP_CPU)
6054 static void dump_ppc_sprs (CPUPPCState *env)
6055 {
6056 ppc_spr_t *spr;
6057 #if !defined(CONFIG_USER_ONLY)
6058 uint32_t sr, sw;
6059 #endif
6060 uint32_t ur, uw;
6061 int i, j, n;
6062
6063 printf("Special purpose registers:\n");
6064 for (i = 0; i < 32; i++) {
6065 for (j = 0; j < 32; j++) {
6066 n = (i << 5) | j;
6067 spr = &env->spr_cb[n];
6068 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
6069 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
6070 #if !defined(CONFIG_USER_ONLY)
6071 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
6072 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
6073 if (sw || sr || uw || ur) {
6074 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
6075 (i << 5) | j, (i << 5) | j, spr->name,
6076 sw ? 'w' : '-', sr ? 'r' : '-',
6077 uw ? 'w' : '-', ur ? 'r' : '-');
6078 }
6079 #else
6080 if (uw || ur) {
6081 printf("SPR: %4d (%03x) %-8s u%c%c\n",
6082 (i << 5) | j, (i << 5) | j, spr->name,
6083 uw ? 'w' : '-', ur ? 'r' : '-');
6084 }
6085 #endif
6086 }
6087 }
6088 fflush(stdout);
6089 fflush(stderr);
6090 }
6091 #endif
6092
6093 /*****************************************************************************/
6094 #include <stdlib.h>
6095 #include <string.h>
6096
6097 int fflush (FILE *stream);
6098
6099 /* Opcode types */
6100 enum {
6101 PPC_DIRECT = 0, /* Opcode routine */
6102 PPC_INDIRECT = 1, /* Indirect opcode table */
6103 };
6104
6105 static inline int is_indirect_opcode (void *handler)
6106 {
6107 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
6108 }
6109
6110 static inline opc_handler_t **ind_table(void *handler)
6111 {
6112 return (opc_handler_t **)((unsigned long)handler & ~3);
6113 }
6114
6115 /* Instruction table creation */
6116 /* Opcodes tables creation */
6117 static void fill_new_table (opc_handler_t **table, int len)
6118 {
6119 int i;
6120
6121 for (i = 0; i < len; i++)
6122 table[i] = &invalid_handler;
6123 }
6124
6125 static int create_new_table (opc_handler_t **table, unsigned char idx)
6126 {
6127 opc_handler_t **tmp;
6128
6129 tmp = malloc(0x20 * sizeof(opc_handler_t));
6130 if (tmp == NULL)
6131 return -1;
6132 fill_new_table(tmp, 0x20);
6133 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
6134
6135 return 0;
6136 }
6137
6138 static int insert_in_table (opc_handler_t **table, unsigned char idx,
6139 opc_handler_t *handler)
6140 {
6141 if (table[idx] != &invalid_handler)
6142 return -1;
6143 table[idx] = handler;
6144
6145 return 0;
6146 }
6147
6148 static int register_direct_insn (opc_handler_t **ppc_opcodes,
6149 unsigned char idx, opc_handler_t *handler)
6150 {
6151 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
6152 printf("*** ERROR: opcode %02x already assigned in main "
6153 "opcode table\n", idx);
6154 return -1;
6155 }
6156
6157 return 0;
6158 }
6159
6160 static int register_ind_in_table (opc_handler_t **table,
6161 unsigned char idx1, unsigned char idx2,
6162 opc_handler_t *handler)
6163 {
6164 if (table[idx1] == &invalid_handler) {
6165 if (create_new_table(table, idx1) < 0) {
6166 printf("*** ERROR: unable to create indirect table "
6167 "idx=%02x\n", idx1);
6168 return -1;
6169 }
6170 } else {
6171 if (!is_indirect_opcode(table[idx1])) {
6172 printf("*** ERROR: idx %02x already assigned to a direct "
6173 "opcode\n", idx1);
6174 return -1;
6175 }
6176 }
6177 if (handler != NULL &&
6178 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
6179 printf("*** ERROR: opcode %02x already assigned in "
6180 "opcode table %02x\n", idx2, idx1);
6181 return -1;
6182 }
6183
6184 return 0;
6185 }
6186
6187 static int register_ind_insn (opc_handler_t **ppc_opcodes,
6188 unsigned char idx1, unsigned char idx2,
6189 opc_handler_t *handler)
6190 {
6191 int ret;
6192
6193 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
6194
6195 return ret;
6196 }
6197
6198 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
6199 unsigned char idx1, unsigned char idx2,
6200 unsigned char idx3, opc_handler_t *handler)
6201 {
6202 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
6203 printf("*** ERROR: unable to join indirect table idx "
6204 "[%02x-%02x]\n", idx1, idx2);
6205 return -1;
6206 }
6207 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
6208 handler) < 0) {
6209 printf("*** ERROR: unable to insert opcode "
6210 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
6211 return -1;
6212 }
6213
6214 return 0;
6215 }
6216
6217 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
6218 {
6219 if (insn->opc2 != 0xFF) {
6220 if (insn->opc3 != 0xFF) {
6221 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
6222 insn->opc3, &insn->handler) < 0)
6223 return -1;
6224 } else {
6225 if (register_ind_insn(ppc_opcodes, insn->opc1,
6226 insn->opc2, &insn->handler) < 0)
6227 return -1;
6228 }
6229 } else {
6230 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
6231 return -1;
6232 }
6233
6234 return 0;
6235 }
6236
6237 static int test_opcode_table (opc_handler_t **table, int len)
6238 {
6239 int i, count, tmp;
6240
6241 for (i = 0, count = 0; i < len; i++) {
6242 /* Consistency fixup */
6243 if (table[i] == NULL)
6244 table[i] = &invalid_handler;
6245 if (table[i] != &invalid_handler) {
6246 if (is_indirect_opcode(table[i])) {
6247 tmp = test_opcode_table(ind_table(table[i]), 0x20);
6248 if (tmp == 0) {
6249 free(table[i]);
6250 table[i] = &invalid_handler;
6251 } else {
6252 count++;
6253 }
6254 } else {
6255 count++;
6256 }
6257 }
6258 }
6259
6260 return count;
6261 }
6262
6263 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
6264 {
6265 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
6266 printf("*** WARNING: no opcode defined !\n");
6267 }
6268
6269 /*****************************************************************************/
6270 static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def)
6271 {
6272 opcode_t *opc, *start, *end;
6273
6274 fill_new_table(env->opcodes, 0x40);
6275 if (&opc_start < &opc_end) {
6276 start = &opc_start;
6277 end = &opc_end;
6278 } else {
6279 start = &opc_end;
6280 end = &opc_start;
6281 }
6282 for (opc = start + 1; opc != end; opc++) {
6283 if ((opc->handler.type & def->insns_flags) != 0) {
6284 if (register_insn(env->opcodes, opc) < 0) {
6285 printf("*** ERROR initializing PowerPC instruction "
6286 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
6287 opc->opc3);
6288 return -1;
6289 }
6290 }
6291 }
6292 fix_opcode_tables(env->opcodes);
6293 fflush(stdout);
6294 fflush(stderr);
6295
6296 return 0;
6297 }
6298
6299 #if defined(PPC_DUMP_CPU)
6300 static void dump_ppc_insns (CPUPPCState *env)
6301 {
6302 opc_handler_t **table, *handler;
6303 uint8_t opc1, opc2, opc3;
6304
6305 printf("Instructions set:\n");
6306 /* opc1 is 6 bits long */
6307 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
6308 table = env->opcodes;
6309 handler = table[opc1];
6310 if (is_indirect_opcode(handler)) {
6311 /* opc2 is 5 bits long */
6312 for (opc2 = 0; opc2 < 0x20; opc2++) {
6313 table = env->opcodes;
6314 handler = env->opcodes[opc1];
6315 table = ind_table(handler);
6316 handler = table[opc2];
6317 if (is_indirect_opcode(handler)) {
6318 table = ind_table(handler);
6319 /* opc3 is 5 bits long */
6320 for (opc3 = 0; opc3 < 0x20; opc3++) {
6321 handler = table[opc3];
6322 if (handler->handler != &gen_invalid) {
6323 printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
6324 opc1, opc2, opc3, opc1, (opc3 << 5) | opc2,
6325 handler->oname);
6326 }
6327 }
6328 } else {
6329 if (handler->handler != &gen_invalid) {
6330 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
6331 opc1, opc2, opc1, opc2, handler->oname);
6332 }
6333 }
6334 }
6335 } else {
6336 if (handler->handler != &gen_invalid) {
6337 printf("INSN: %02x -- -- (%02d ----) : %s\n",
6338 opc1, opc1, handler->oname);
6339 }
6340 }
6341 }
6342 }
6343 #endif
6344
6345 int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
6346 {
6347 env->msr_mask = def->msr_mask;
6348 env->mmu_model = def->mmu_model;
6349 env->excp_model = def->excp_model;
6350 env->bus_model = def->bus_model;
6351 env->flags = def->flags;
6352 env->bfd_mach = def->bfd_mach;
6353 env->check_pow = def->check_pow;
6354 if (create_ppc_opcodes(env, def) < 0)
6355 return -1;
6356 init_ppc_proc(env, def);
6357 #if defined(PPC_DUMP_CPU)
6358 {
6359 const unsigned char *mmu_model, *excp_model, *bus_model;
6360 switch (env->mmu_model) {
6361 case POWERPC_MMU_32B:
6362 mmu_model = "PowerPC 32";
6363 break;
6364 case POWERPC_MMU_SOFT_6xx:
6365 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
6366 break;
6367 case POWERPC_MMU_SOFT_74xx:
6368 mmu_model = "PowerPC 74xx with software driven TLBs";
6369 break;
6370 case POWERPC_MMU_SOFT_4xx:
6371 mmu_model = "PowerPC 4xx with software driven TLBs";
6372 break;
6373 case POWERPC_MMU_SOFT_4xx_Z:
6374 mmu_model = "PowerPC 4xx with software driven TLBs "
6375 "and zones protections";
6376 break;
6377 case POWERPC_MMU_REAL_4xx:
6378 mmu_model = "PowerPC 4xx real mode only";
6379 break;
6380 case POWERPC_MMU_BOOKE:
6381 mmu_model = "PowerPC BookE";
6382 break;
6383 case POWERPC_MMU_BOOKE_FSL:
6384 mmu_model = "PowerPC BookE FSL";
6385 break;
6386 #if defined (TARGET_PPC64)
6387 case POWERPC_MMU_64B:
6388 mmu_model = "PowerPC 64";
6389 break;
6390 #endif
6391 default:
6392 mmu_model = "Unknown or invalid";
6393 break;
6394 }
6395 switch (env->excp_model) {
6396 case POWERPC_EXCP_STD:
6397 excp_model = "PowerPC";
6398 break;
6399 case POWERPC_EXCP_40x:
6400 excp_model = "PowerPC 40x";
6401 break;
6402 case POWERPC_EXCP_601:
6403 excp_model = "PowerPC 601";
6404 break;
6405 case POWERPC_EXCP_602:
6406 excp_model = "PowerPC 602";
6407 break;
6408 case POWERPC_EXCP_603:
6409 excp_model = "PowerPC 603";
6410 break;
6411 case POWERPC_EXCP_603E:
6412 excp_model = "PowerPC 603e";
6413 break;
6414 case POWERPC_EXCP_604:
6415 excp_model = "PowerPC 604";
6416 break;
6417 case POWERPC_EXCP_7x0:
6418 excp_model = "PowerPC 740/750";
6419 break;
6420 case POWERPC_EXCP_7x5:
6421 excp_model = "PowerPC 745/755";
6422 break;
6423 case POWERPC_EXCP_74xx:
6424 excp_model = "PowerPC 74xx";
6425 break;
6426 case POWERPC_EXCP_BOOKE:
6427 excp_model = "PowerPC BookE";
6428 break;
6429 #if defined (TARGET_PPC64)
6430 case POWERPC_EXCP_970:
6431 excp_model = "PowerPC 970";
6432 break;
6433 #endif
6434 default:
6435 excp_model = "Unknown or invalid";
6436 break;
6437 }
6438 switch (env->bus_model) {
6439 case PPC_FLAGS_INPUT_6xx:
6440 bus_model = "PowerPC 6xx";
6441 break;
6442 case PPC_FLAGS_INPUT_BookE:
6443 bus_model = "PowerPC BookE";
6444 break;
6445 case PPC_FLAGS_INPUT_405:
6446 bus_model = "PowerPC 405";
6447 break;
6448 case PPC_FLAGS_INPUT_401:
6449 bus_model = "PowerPC 401/403";
6450 break;
6451 #if defined (TARGET_PPC64)
6452 case PPC_FLAGS_INPUT_970:
6453 bus_model = "PowerPC 970";
6454 break;
6455 #endif
6456 default:
6457 bus_model = "Unknown or invalid";
6458 break;
6459 }
6460 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
6461 " MMU model : %s\n",
6462 def->name, def->pvr, def->msr_mask, mmu_model);
6463 #if !defined(CONFIG_USER_ONLY)
6464 if (env->tlb != NULL) {
6465 printf(" %d %s TLB in %d ways\n",
6466 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
6467 env->nb_ways);
6468 }
6469 #endif
6470 printf(" Exceptions model : %s\n"
6471 " Bus model : %s\n",
6472 excp_model, bus_model);
6473 printf(" MSR features :\n");
6474 if (env->flags & POWERPC_FLAG_SPE)
6475 printf(" signal processing engine enable"
6476 "\n");
6477 else if (env->flags & POWERPC_FLAG_VRE)
6478 printf(" vector processor enable\n");
6479 if (env->flags & POWERPC_FLAG_TGPR)
6480 printf(" temporary GPRs\n");
6481 else if (env->flags & POWERPC_FLAG_CE)
6482 printf(" critical input enable\n");
6483 if (env->flags & POWERPC_FLAG_SE)
6484 printf(" single-step trace mode\n");
6485 else if (env->flags & POWERPC_FLAG_DWE)
6486 printf(" debug wait enable\n");
6487 else if (env->flags & POWERPC_FLAG_UBLE)
6488 printf(" user BTB lock enable\n");
6489 if (env->flags & POWERPC_FLAG_BE)
6490 printf(" branch-step trace mode\n");
6491 else if (env->flags & POWERPC_FLAG_DE)
6492 printf(" debug interrupt enable\n");
6493 if (env->flags & POWERPC_FLAG_PX)
6494 printf(" inclusive protection\n");
6495 else if (env->flags & POWERPC_FLAG_PMM)
6496 printf(" performance monitor mark\n");
6497 if (env->flags == POWERPC_FLAG_NONE)
6498 printf(" none\n");
6499 }
6500 dump_ppc_insns(env);
6501 dump_ppc_sprs(env);
6502 fflush(stdout);
6503 #endif
6504
6505 return 0;
6506 }
6507
6508 int ppc_find_by_name (const unsigned char *name, ppc_def_t **def)
6509 {
6510 int i, max, ret;
6511
6512 ret = -1;
6513 *def = NULL;
6514 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6515 for (i = 0; i < max; i++) {
6516 if (strcasecmp(name, ppc_defs[i].name) == 0) {
6517 *def = &ppc_defs[i];
6518 ret = 0;
6519 break;
6520 }
6521 }
6522
6523 return ret;
6524 }
6525
6526 int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
6527 {
6528 int i, max, ret;
6529
6530 ret = -1;
6531 *def = NULL;
6532 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6533 for (i = 0; i < max; i++) {
6534 if ((pvr & ppc_defs[i].pvr_mask) ==
6535 (ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) {
6536 *def = &ppc_defs[i];
6537 ret = 0;
6538 break;
6539 }
6540 }
6541
6542 return ret;
6543 }
6544
6545 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
6546 {
6547 int i, max;
6548
6549 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6550 for (i = 0; i < max; i++) {
6551 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
6552 ppc_defs[i].name, ppc_defs[i].pvr);
6553 }
6554 }
Qemu copy for testing