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s390: I/O interrupt and machine check injection.
[qemu.git] / target-s390x / cpu.h
1 /*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 */
22 #ifndef CPU_S390X_H
23 #define CPU_S390X_H
24
25 #include "config.h"
26 #include "qemu-common.h"
27
28 #define TARGET_LONG_BITS 64
29
30 #define ELF_MACHINE EM_S390
31
32 #define CPUArchState struct CPUS390XState
33
34 #include "exec/cpu-defs.h"
35 #define TARGET_PAGE_BITS 12
36
37 #define TARGET_PHYS_ADDR_SPACE_BITS 64
38 #define TARGET_VIRT_ADDR_SPACE_BITS 64
39
40 #include "exec/cpu-all.h"
41
42 #include "fpu/softfloat.h"
43
44 #define NB_MMU_MODES 3
45
46 #define MMU_MODE0_SUFFIX _primary
47 #define MMU_MODE1_SUFFIX _secondary
48 #define MMU_MODE2_SUFFIX _home
49
50 #define MMU_USER_IDX 1
51
52 #define MAX_EXT_QUEUE 16
53 #define MAX_IO_QUEUE 16
54 #define MAX_MCHK_QUEUE 16
55
56 #define PSW_MCHK_MASK 0x0004000000000000
57 #define PSW_IO_MASK 0x0200000000000000
58
59 typedef struct PSW {
60 uint64_t mask;
61 uint64_t addr;
62 } PSW;
63
64 typedef struct ExtQueue {
65 uint32_t code;
66 uint32_t param;
67 uint32_t param64;
68 } ExtQueue;
69
70 typedef struct IOIntQueue {
71 uint16_t id;
72 uint16_t nr;
73 uint32_t parm;
74 uint32_t word;
75 } IOIntQueue;
76
77 typedef struct MchkQueue {
78 uint16_t type;
79 } MchkQueue;
80
81 typedef struct CPUS390XState {
82 uint64_t regs[16]; /* GP registers */
83 CPU_DoubleU fregs[16]; /* FP registers */
84 uint32_t aregs[16]; /* access registers */
85
86 uint32_t fpc; /* floating-point control register */
87 uint32_t cc_op;
88
89 float_status fpu_status; /* passed to softfloat lib */
90
91 /* The low part of a 128-bit return, or remainder of a divide. */
92 uint64_t retxl;
93
94 PSW psw;
95
96 uint64_t cc_src;
97 uint64_t cc_dst;
98 uint64_t cc_vr;
99
100 uint64_t __excp_addr;
101 uint64_t psa;
102
103 uint32_t int_pgm_code;
104 uint32_t int_pgm_ilen;
105
106 uint32_t int_svc_code;
107 uint32_t int_svc_ilen;
108
109 uint64_t cregs[16]; /* control registers */
110
111 ExtQueue ext_queue[MAX_EXT_QUEUE];
112 IOIntQueue io_queue[MAX_IO_QUEUE][8];
113 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
114
115 int pending_int;
116 int ext_index;
117 int io_index[8];
118 int mchk_index;
119
120 uint64_t ckc;
121 uint64_t cputm;
122 uint32_t todpr;
123
124 CPU_COMMON
125
126 /* reset does memset(0) up to here */
127
128 int cpu_num;
129 uint8_t *storage_keys;
130
131 uint64_t tod_offset;
132 uint64_t tod_basetime;
133 QEMUTimer *tod_timer;
134
135 QEMUTimer *cpu_timer;
136 } CPUS390XState;
137
138 #include "cpu-qom.h"
139
140 #if defined(CONFIG_USER_ONLY)
141 static inline void cpu_clone_regs(CPUS390XState *env, target_ulong newsp)
142 {
143 if (newsp) {
144 env->regs[15] = newsp;
145 }
146 env->regs[2] = 0;
147 }
148 #endif
149
150 /* Interrupt Codes */
151 /* Program Interrupts */
152 #define PGM_OPERATION 0x0001
153 #define PGM_PRIVILEGED 0x0002
154 #define PGM_EXECUTE 0x0003
155 #define PGM_PROTECTION 0x0004
156 #define PGM_ADDRESSING 0x0005
157 #define PGM_SPECIFICATION 0x0006
158 #define PGM_DATA 0x0007
159 #define PGM_FIXPT_OVERFLOW 0x0008
160 #define PGM_FIXPT_DIVIDE 0x0009
161 #define PGM_DEC_OVERFLOW 0x000a
162 #define PGM_DEC_DIVIDE 0x000b
163 #define PGM_HFP_EXP_OVERFLOW 0x000c
164 #define PGM_HFP_EXP_UNDERFLOW 0x000d
165 #define PGM_HFP_SIGNIFICANCE 0x000e
166 #define PGM_HFP_DIVIDE 0x000f
167 #define PGM_SEGMENT_TRANS 0x0010
168 #define PGM_PAGE_TRANS 0x0011
169 #define PGM_TRANS_SPEC 0x0012
170 #define PGM_SPECIAL_OP 0x0013
171 #define PGM_OPERAND 0x0015
172 #define PGM_TRACE_TABLE 0x0016
173 #define PGM_SPACE_SWITCH 0x001c
174 #define PGM_HFP_SQRT 0x001d
175 #define PGM_PC_TRANS_SPEC 0x001f
176 #define PGM_AFX_TRANS 0x0020
177 #define PGM_ASX_TRANS 0x0021
178 #define PGM_LX_TRANS 0x0022
179 #define PGM_EX_TRANS 0x0023
180 #define PGM_PRIM_AUTH 0x0024
181 #define PGM_SEC_AUTH 0x0025
182 #define PGM_ALET_SPEC 0x0028
183 #define PGM_ALEN_SPEC 0x0029
184 #define PGM_ALE_SEQ 0x002a
185 #define PGM_ASTE_VALID 0x002b
186 #define PGM_ASTE_SEQ 0x002c
187 #define PGM_EXT_AUTH 0x002d
188 #define PGM_STACK_FULL 0x0030
189 #define PGM_STACK_EMPTY 0x0031
190 #define PGM_STACK_SPEC 0x0032
191 #define PGM_STACK_TYPE 0x0033
192 #define PGM_STACK_OP 0x0034
193 #define PGM_ASCE_TYPE 0x0038
194 #define PGM_REG_FIRST_TRANS 0x0039
195 #define PGM_REG_SEC_TRANS 0x003a
196 #define PGM_REG_THIRD_TRANS 0x003b
197 #define PGM_MONITOR 0x0040
198 #define PGM_PER 0x0080
199 #define PGM_CRYPTO 0x0119
200
201 /* External Interrupts */
202 #define EXT_INTERRUPT_KEY 0x0040
203 #define EXT_CLOCK_COMP 0x1004
204 #define EXT_CPU_TIMER 0x1005
205 #define EXT_MALFUNCTION 0x1200
206 #define EXT_EMERGENCY 0x1201
207 #define EXT_EXTERNAL_CALL 0x1202
208 #define EXT_ETR 0x1406
209 #define EXT_SERVICE 0x2401
210 #define EXT_VIRTIO 0x2603
211
212 /* PSW defines */
213 #undef PSW_MASK_PER
214 #undef PSW_MASK_DAT
215 #undef PSW_MASK_IO
216 #undef PSW_MASK_EXT
217 #undef PSW_MASK_KEY
218 #undef PSW_SHIFT_KEY
219 #undef PSW_MASK_MCHECK
220 #undef PSW_MASK_WAIT
221 #undef PSW_MASK_PSTATE
222 #undef PSW_MASK_ASC
223 #undef PSW_MASK_CC
224 #undef PSW_MASK_PM
225 #undef PSW_MASK_64
226
227 #define PSW_MASK_PER 0x4000000000000000ULL
228 #define PSW_MASK_DAT 0x0400000000000000ULL
229 #define PSW_MASK_IO 0x0200000000000000ULL
230 #define PSW_MASK_EXT 0x0100000000000000ULL
231 #define PSW_MASK_KEY 0x00F0000000000000ULL
232 #define PSW_SHIFT_KEY 56
233 #define PSW_MASK_MCHECK 0x0004000000000000ULL
234 #define PSW_MASK_WAIT 0x0002000000000000ULL
235 #define PSW_MASK_PSTATE 0x0001000000000000ULL
236 #define PSW_MASK_ASC 0x0000C00000000000ULL
237 #define PSW_MASK_CC 0x0000300000000000ULL
238 #define PSW_MASK_PM 0x00000F0000000000ULL
239 #define PSW_MASK_64 0x0000000100000000ULL
240 #define PSW_MASK_32 0x0000000080000000ULL
241
242 #undef PSW_ASC_PRIMARY
243 #undef PSW_ASC_ACCREG
244 #undef PSW_ASC_SECONDARY
245 #undef PSW_ASC_HOME
246
247 #define PSW_ASC_PRIMARY 0x0000000000000000ULL
248 #define PSW_ASC_ACCREG 0x0000400000000000ULL
249 #define PSW_ASC_SECONDARY 0x0000800000000000ULL
250 #define PSW_ASC_HOME 0x0000C00000000000ULL
251
252 /* tb flags */
253
254 #define FLAG_MASK_PER (PSW_MASK_PER >> 32)
255 #define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
256 #define FLAG_MASK_IO (PSW_MASK_IO >> 32)
257 #define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
258 #define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
259 #define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
260 #define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
261 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
262 #define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
263 #define FLAG_MASK_CC (PSW_MASK_CC >> 32)
264 #define FLAG_MASK_PM (PSW_MASK_PM >> 32)
265 #define FLAG_MASK_64 (PSW_MASK_64 >> 32)
266 #define FLAG_MASK_32 0x00001000
267
268 static inline int cpu_mmu_index (CPUS390XState *env)
269 {
270 if (env->psw.mask & PSW_MASK_PSTATE) {
271 return 1;
272 }
273
274 return 0;
275 }
276
277 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
278 target_ulong *cs_base, int *flags)
279 {
280 *pc = env->psw.addr;
281 *cs_base = 0;
282 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
283 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
284 }
285
286 /* While the PoO talks about ILC (a number between 1-3) what is actually
287 stored in LowCore is shifted left one bit (an even between 2-6). As
288 this is the actual length of the insn and therefore more useful, that
289 is what we want to pass around and manipulate. To make sure that we
290 have applied this distinction universally, rename the "ILC" to "ILEN". */
291 static inline int get_ilen(uint8_t opc)
292 {
293 switch (opc >> 6) {
294 case 0:
295 return 2;
296 case 1:
297 case 2:
298 return 4;
299 default:
300 return 6;
301 }
302 }
303
304 #ifndef CONFIG_USER_ONLY
305 /* In several cases of runtime exceptions, we havn't recorded the true
306 instruction length. Use these codes when raising exceptions in order
307 to re-compute the length by examining the insn in memory. */
308 #define ILEN_LATER 0x20
309 #define ILEN_LATER_INC 0x21
310 #endif
311
312 S390CPU *cpu_s390x_init(const char *cpu_model);
313 void s390x_translate_init(void);
314 int cpu_s390x_exec(CPUS390XState *s);
315 void cpu_s390x_close(CPUS390XState *s);
316 void do_interrupt (CPUS390XState *env);
317
318 /* you can call this signal handler from your SIGBUS and SIGSEGV
319 signal handlers to inform the virtual CPU of exceptions. non zero
320 is returned if the signal was handled by the virtual CPU. */
321 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
322 void *puc);
323 int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
324 int mmu_idx);
325 #define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault
326
327 #include "ioinst.h"
328
329 #ifndef CONFIG_USER_ONLY
330 void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
331 int is_write);
332 void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
333 int is_write);
334 void s390x_tod_timer(void *opaque);
335 void s390x_cpu_timer(void *opaque);
336
337 int s390_virtio_hypercall(CPUS390XState *env);
338
339 #ifdef CONFIG_KVM
340 void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code);
341 void kvm_s390_virtio_irq(S390CPU *cpu, int config_change, uint64_t token);
342 void kvm_s390_interrupt_internal(S390CPU *cpu, int type, uint32_t parm,
343 uint64_t parm64, int vm);
344 #else
345 static inline void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code)
346 {
347 }
348
349 static inline void kvm_s390_virtio_irq(S390CPU *cpu, int config_change,
350 uint64_t token)
351 {
352 }
353
354 static inline void kvm_s390_interrupt_internal(S390CPU *cpu, int type,
355 uint32_t parm, uint64_t parm64,
356 int vm)
357 {
358 }
359 #endif
360 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
361 void s390_add_running_cpu(CPUS390XState *env);
362 unsigned s390_del_running_cpu(CPUS390XState *env);
363
364 /* service interrupts are floating therefore we must not pass an cpustate */
365 void s390_sclp_extint(uint32_t parm);
366
367 /* from s390-virtio-bus */
368 extern const hwaddr virtio_size;
369
370 #else
371 static inline void s390_add_running_cpu(CPUS390XState *env)
372 {
373 }
374
375 static inline unsigned s390_del_running_cpu(CPUS390XState *env)
376 {
377 return 0;
378 }
379 #endif
380 void cpu_lock(void);
381 void cpu_unlock(void);
382
383 static inline void cpu_set_tls(CPUS390XState *env, target_ulong newtls)
384 {
385 env->aregs[0] = newtls >> 32;
386 env->aregs[1] = newtls & 0xffffffffULL;
387 }
388
389 #define cpu_init(model) (&cpu_s390x_init(model)->env)
390 #define cpu_exec cpu_s390x_exec
391 #define cpu_gen_code cpu_s390x_gen_code
392 #define cpu_signal_handler cpu_s390x_signal_handler
393
394 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
395 #define cpu_list s390_cpu_list
396
397 #include "exec/exec-all.h"
398
399 #define EXCP_EXT 1 /* external interrupt */
400 #define EXCP_SVC 2 /* supervisor call (syscall) */
401 #define EXCP_PGM 3 /* program interruption */
402 #define EXCP_IO 7 /* I/O interrupt */
403 #define EXCP_MCHK 8 /* machine check */
404
405 #define INTERRUPT_EXT (1 << 0)
406 #define INTERRUPT_TOD (1 << 1)
407 #define INTERRUPT_CPUTIMER (1 << 2)
408 #define INTERRUPT_IO (1 << 3)
409 #define INTERRUPT_MCHK (1 << 4)
410
411 /* Program Status Word. */
412 #define S390_PSWM_REGNUM 0
413 #define S390_PSWA_REGNUM 1
414 /* General Purpose Registers. */
415 #define S390_R0_REGNUM 2
416 #define S390_R1_REGNUM 3
417 #define S390_R2_REGNUM 4
418 #define S390_R3_REGNUM 5
419 #define S390_R4_REGNUM 6
420 #define S390_R5_REGNUM 7
421 #define S390_R6_REGNUM 8
422 #define S390_R7_REGNUM 9
423 #define S390_R8_REGNUM 10
424 #define S390_R9_REGNUM 11
425 #define S390_R10_REGNUM 12
426 #define S390_R11_REGNUM 13
427 #define S390_R12_REGNUM 14
428 #define S390_R13_REGNUM 15
429 #define S390_R14_REGNUM 16
430 #define S390_R15_REGNUM 17
431 /* Access Registers. */
432 #define S390_A0_REGNUM 18
433 #define S390_A1_REGNUM 19
434 #define S390_A2_REGNUM 20
435 #define S390_A3_REGNUM 21
436 #define S390_A4_REGNUM 22
437 #define S390_A5_REGNUM 23
438 #define S390_A6_REGNUM 24
439 #define S390_A7_REGNUM 25
440 #define S390_A8_REGNUM 26
441 #define S390_A9_REGNUM 27
442 #define S390_A10_REGNUM 28
443 #define S390_A11_REGNUM 29
444 #define S390_A12_REGNUM 30
445 #define S390_A13_REGNUM 31
446 #define S390_A14_REGNUM 32
447 #define S390_A15_REGNUM 33
448 /* Floating Point Control Word. */
449 #define S390_FPC_REGNUM 34
450 /* Floating Point Registers. */
451 #define S390_F0_REGNUM 35
452 #define S390_F1_REGNUM 36
453 #define S390_F2_REGNUM 37
454 #define S390_F3_REGNUM 38
455 #define S390_F4_REGNUM 39
456 #define S390_F5_REGNUM 40
457 #define S390_F6_REGNUM 41
458 #define S390_F7_REGNUM 42
459 #define S390_F8_REGNUM 43
460 #define S390_F9_REGNUM 44
461 #define S390_F10_REGNUM 45
462 #define S390_F11_REGNUM 46
463 #define S390_F12_REGNUM 47
464 #define S390_F13_REGNUM 48
465 #define S390_F14_REGNUM 49
466 #define S390_F15_REGNUM 50
467 /* Total. */
468 #define S390_NUM_REGS 51
469
470 /* CC optimization */
471
472 enum cc_op {
473 CC_OP_CONST0 = 0, /* CC is 0 */
474 CC_OP_CONST1, /* CC is 1 */
475 CC_OP_CONST2, /* CC is 2 */
476 CC_OP_CONST3, /* CC is 3 */
477
478 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
479 CC_OP_STATIC, /* CC value is env->cc_op */
480
481 CC_OP_NZ, /* env->cc_dst != 0 */
482 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
483 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
484 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
485 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
486 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
487 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
488
489 CC_OP_ADD_64, /* overflow on add (64bit) */
490 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
491 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
492 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
493 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
494 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
495 CC_OP_ABS_64, /* sign eval on abs (64bit) */
496 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
497
498 CC_OP_ADD_32, /* overflow on add (32bit) */
499 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
500 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
501 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
502 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
503 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
504 CC_OP_ABS_32, /* sign eval on abs (64bit) */
505 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
506
507 CC_OP_COMP_32, /* complement */
508 CC_OP_COMP_64, /* complement */
509
510 CC_OP_TM_32, /* test under mask (32bit) */
511 CC_OP_TM_64, /* test under mask (64bit) */
512
513 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
514 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
515 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
516
517 CC_OP_ICM, /* insert characters under mask */
518 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
519 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
520 CC_OP_FLOGR, /* find leftmost one */
521 CC_OP_MAX
522 };
523
524 static const char *cc_names[] = {
525 [CC_OP_CONST0] = "CC_OP_CONST0",
526 [CC_OP_CONST1] = "CC_OP_CONST1",
527 [CC_OP_CONST2] = "CC_OP_CONST2",
528 [CC_OP_CONST3] = "CC_OP_CONST3",
529 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
530 [CC_OP_STATIC] = "CC_OP_STATIC",
531 [CC_OP_NZ] = "CC_OP_NZ",
532 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
533 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
534 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
535 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
536 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
537 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
538 [CC_OP_ADD_64] = "CC_OP_ADD_64",
539 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
540 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
541 [CC_OP_SUB_64] = "CC_OP_SUB_64",
542 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
543 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
544 [CC_OP_ABS_64] = "CC_OP_ABS_64",
545 [CC_OP_NABS_64] = "CC_OP_NABS_64",
546 [CC_OP_ADD_32] = "CC_OP_ADD_32",
547 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
548 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
549 [CC_OP_SUB_32] = "CC_OP_SUB_32",
550 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
551 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
552 [CC_OP_ABS_32] = "CC_OP_ABS_32",
553 [CC_OP_NABS_32] = "CC_OP_NABS_32",
554 [CC_OP_COMP_32] = "CC_OP_COMP_32",
555 [CC_OP_COMP_64] = "CC_OP_COMP_64",
556 [CC_OP_TM_32] = "CC_OP_TM_32",
557 [CC_OP_TM_64] = "CC_OP_TM_64",
558 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
559 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
560 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
561 [CC_OP_ICM] = "CC_OP_ICM",
562 [CC_OP_SLA_32] = "CC_OP_SLA_32",
563 [CC_OP_SLA_64] = "CC_OP_SLA_64",
564 [CC_OP_FLOGR] = "CC_OP_FLOGR",
565 };
566
567 static inline const char *cc_name(int cc_op)
568 {
569 return cc_names[cc_op];
570 }
571
572 typedef struct LowCore
573 {
574 /* prefix area: defined by architecture */
575 uint32_t ccw1[2]; /* 0x000 */
576 uint32_t ccw2[4]; /* 0x008 */
577 uint8_t pad1[0x80-0x18]; /* 0x018 */
578 uint32_t ext_params; /* 0x080 */
579 uint16_t cpu_addr; /* 0x084 */
580 uint16_t ext_int_code; /* 0x086 */
581 uint16_t svc_ilen; /* 0x088 */
582 uint16_t svc_code; /* 0x08a */
583 uint16_t pgm_ilen; /* 0x08c */
584 uint16_t pgm_code; /* 0x08e */
585 uint32_t data_exc_code; /* 0x090 */
586 uint16_t mon_class_num; /* 0x094 */
587 uint16_t per_perc_atmid; /* 0x096 */
588 uint64_t per_address; /* 0x098 */
589 uint8_t exc_access_id; /* 0x0a0 */
590 uint8_t per_access_id; /* 0x0a1 */
591 uint8_t op_access_id; /* 0x0a2 */
592 uint8_t ar_access_id; /* 0x0a3 */
593 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
594 uint64_t trans_exc_code; /* 0x0a8 */
595 uint64_t monitor_code; /* 0x0b0 */
596 uint16_t subchannel_id; /* 0x0b8 */
597 uint16_t subchannel_nr; /* 0x0ba */
598 uint32_t io_int_parm; /* 0x0bc */
599 uint32_t io_int_word; /* 0x0c0 */
600 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
601 uint32_t stfl_fac_list; /* 0x0c8 */
602 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
603 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
604 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
605 uint32_t external_damage_code; /* 0x0f4 */
606 uint64_t failing_storage_address; /* 0x0f8 */
607 uint8_t pad6[0x120-0x100]; /* 0x100 */
608 PSW restart_old_psw; /* 0x120 */
609 PSW external_old_psw; /* 0x130 */
610 PSW svc_old_psw; /* 0x140 */
611 PSW program_old_psw; /* 0x150 */
612 PSW mcck_old_psw; /* 0x160 */
613 PSW io_old_psw; /* 0x170 */
614 uint8_t pad7[0x1a0-0x180]; /* 0x180 */
615 PSW restart_psw; /* 0x1a0 */
616 PSW external_new_psw; /* 0x1b0 */
617 PSW svc_new_psw; /* 0x1c0 */
618 PSW program_new_psw; /* 0x1d0 */
619 PSW mcck_new_psw; /* 0x1e0 */
620 PSW io_new_psw; /* 0x1f0 */
621 PSW return_psw; /* 0x200 */
622 uint8_t irb[64]; /* 0x210 */
623 uint64_t sync_enter_timer; /* 0x250 */
624 uint64_t async_enter_timer; /* 0x258 */
625 uint64_t exit_timer; /* 0x260 */
626 uint64_t last_update_timer; /* 0x268 */
627 uint64_t user_timer; /* 0x270 */
628 uint64_t system_timer; /* 0x278 */
629 uint64_t last_update_clock; /* 0x280 */
630 uint64_t steal_clock; /* 0x288 */
631 PSW return_mcck_psw; /* 0x290 */
632 uint8_t pad8[0xc00-0x2a0]; /* 0x2a0 */
633 /* System info area */
634 uint64_t save_area[16]; /* 0xc00 */
635 uint8_t pad9[0xd40-0xc80]; /* 0xc80 */
636 uint64_t kernel_stack; /* 0xd40 */
637 uint64_t thread_info; /* 0xd48 */
638 uint64_t async_stack; /* 0xd50 */
639 uint64_t kernel_asce; /* 0xd58 */
640 uint64_t user_asce; /* 0xd60 */
641 uint64_t panic_stack; /* 0xd68 */
642 uint64_t user_exec_asce; /* 0xd70 */
643 uint8_t pad10[0xdc0-0xd78]; /* 0xd78 */
644
645 /* SMP info area: defined by DJB */
646 uint64_t clock_comparator; /* 0xdc0 */
647 uint64_t ext_call_fast; /* 0xdc8 */
648 uint64_t percpu_offset; /* 0xdd0 */
649 uint64_t current_task; /* 0xdd8 */
650 uint32_t softirq_pending; /* 0xde0 */
651 uint32_t pad_0x0de4; /* 0xde4 */
652 uint64_t int_clock; /* 0xde8 */
653 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
654
655 /* 0xe00 is used as indicator for dump tools */
656 /* whether the kernel died with panic() or not */
657 uint32_t panic_magic; /* 0xe00 */
658
659 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
660
661 /* 64 bit extparam used for pfault, diag 250 etc */
662 uint64_t ext_params2; /* 0x11B8 */
663
664 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
665
666 /* System info area */
667
668 uint64_t floating_pt_save_area[16]; /* 0x1200 */
669 uint64_t gpregs_save_area[16]; /* 0x1280 */
670 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
671 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
672 uint32_t prefixreg_save_area; /* 0x1318 */
673 uint32_t fpt_creg_save_area; /* 0x131c */
674 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
675 uint32_t tod_progreg_save_area; /* 0x1324 */
676 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
677 uint32_t clock_comp_save_area[2]; /* 0x1330 */
678 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
679 uint32_t access_regs_save_area[16]; /* 0x1340 */
680 uint64_t cregs_save_area[16]; /* 0x1380 */
681
682 /* align to the top of the prefix area */
683
684 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
685 } QEMU_PACKED LowCore;
686
687 /* STSI */
688 #define STSI_LEVEL_MASK 0x00000000f0000000ULL
689 #define STSI_LEVEL_CURRENT 0x0000000000000000ULL
690 #define STSI_LEVEL_1 0x0000000010000000ULL
691 #define STSI_LEVEL_2 0x0000000020000000ULL
692 #define STSI_LEVEL_3 0x0000000030000000ULL
693 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
694 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL
695 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
696 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL
697
698 /* Basic Machine Configuration */
699 struct sysib_111 {
700 uint32_t res1[8];
701 uint8_t manuf[16];
702 uint8_t type[4];
703 uint8_t res2[12];
704 uint8_t model[16];
705 uint8_t sequence[16];
706 uint8_t plant[4];
707 uint8_t res3[156];
708 };
709
710 /* Basic Machine CPU */
711 struct sysib_121 {
712 uint32_t res1[80];
713 uint8_t sequence[16];
714 uint8_t plant[4];
715 uint8_t res2[2];
716 uint16_t cpu_addr;
717 uint8_t res3[152];
718 };
719
720 /* Basic Machine CPUs */
721 struct sysib_122 {
722 uint8_t res1[32];
723 uint32_t capability;
724 uint16_t total_cpus;
725 uint16_t active_cpus;
726 uint16_t standby_cpus;
727 uint16_t reserved_cpus;
728 uint16_t adjustments[2026];
729 };
730
731 /* LPAR CPU */
732 struct sysib_221 {
733 uint32_t res1[80];
734 uint8_t sequence[16];
735 uint8_t plant[4];
736 uint16_t cpu_id;
737 uint16_t cpu_addr;
738 uint8_t res3[152];
739 };
740
741 /* LPAR CPUs */
742 struct sysib_222 {
743 uint32_t res1[32];
744 uint16_t lpar_num;
745 uint8_t res2;
746 uint8_t lcpuc;
747 uint16_t total_cpus;
748 uint16_t conf_cpus;
749 uint16_t standby_cpus;
750 uint16_t reserved_cpus;
751 uint8_t name[8];
752 uint32_t caf;
753 uint8_t res3[16];
754 uint16_t dedicated_cpus;
755 uint16_t shared_cpus;
756 uint8_t res4[180];
757 };
758
759 /* VM CPUs */
760 struct sysib_322 {
761 uint8_t res1[31];
762 uint8_t count;
763 struct {
764 uint8_t res2[4];
765 uint16_t total_cpus;
766 uint16_t conf_cpus;
767 uint16_t standby_cpus;
768 uint16_t reserved_cpus;
769 uint8_t name[8];
770 uint32_t caf;
771 uint8_t cpi[16];
772 uint8_t res3[24];
773 } vm[8];
774 uint8_t res4[3552];
775 };
776
777 /* MMU defines */
778 #define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
779 #define _ASCE_SUBSPACE 0x200 /* subspace group control */
780 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
781 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
782 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
783 #define _ASCE_REAL_SPACE 0x20 /* real space control */
784 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
785 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */
786 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */
787 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */
788 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
789 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */
790
791 #define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
792 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
793 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
794 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
795 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
796 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
797 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */
798
799 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
800 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
801 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
802
803 #define _PAGE_RO 0x200 /* HW read-only bit */
804 #define _PAGE_INVALID 0x400 /* HW invalid bit */
805
806 #define SK_C (0x1 << 1)
807 #define SK_R (0x1 << 2)
808 #define SK_F (0x1 << 3)
809 #define SK_ACC_MASK (0xf << 4)
810
811 #define SIGP_SENSE 0x01
812 #define SIGP_EXTERNAL_CALL 0x02
813 #define SIGP_EMERGENCY 0x03
814 #define SIGP_START 0x04
815 #define SIGP_STOP 0x05
816 #define SIGP_RESTART 0x06
817 #define SIGP_STOP_STORE_STATUS 0x09
818 #define SIGP_INITIAL_CPU_RESET 0x0b
819 #define SIGP_CPU_RESET 0x0c
820 #define SIGP_SET_PREFIX 0x0d
821 #define SIGP_STORE_STATUS_ADDR 0x0e
822 #define SIGP_SET_ARCH 0x12
823
824 /* cpu status bits */
825 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
826 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL
827 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
828 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
829 #define SIGP_STAT_STOPPED 0x00000040UL
830 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
831 #define SIGP_STAT_CHECK_STOP 0x00000010UL
832 #define SIGP_STAT_INOPERATIVE 0x00000004UL
833 #define SIGP_STAT_INVALID_ORDER 0x00000002UL
834 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
835
836 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
837 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
838 target_ulong *raddr, int *flags);
839 int sclp_service_call(uint32_t sccb, uint64_t code);
840 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
841 uint64_t vr);
842
843 #define TARGET_HAS_ICE 1
844
845 /* The value of the TOD clock for 1.1.1970. */
846 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
847
848 /* Converts ns to s390's clock format */
849 static inline uint64_t time2tod(uint64_t ns) {
850 return (ns << 9) / 125;
851 }
852
853 static inline void cpu_inject_ext(CPUS390XState *env, uint32_t code, uint32_t param,
854 uint64_t param64)
855 {
856 if (env->ext_index == MAX_EXT_QUEUE - 1) {
857 /* ugh - can't queue anymore. Let's drop. */
858 return;
859 }
860
861 env->ext_index++;
862 assert(env->ext_index < MAX_EXT_QUEUE);
863
864 env->ext_queue[env->ext_index].code = code;
865 env->ext_queue[env->ext_index].param = param;
866 env->ext_queue[env->ext_index].param64 = param64;
867
868 env->pending_int |= INTERRUPT_EXT;
869 cpu_interrupt(env, CPU_INTERRUPT_HARD);
870 }
871
872 static inline void cpu_inject_io(CPUS390XState *env, uint16_t subchannel_id,
873 uint16_t subchannel_number,
874 uint32_t io_int_parm, uint32_t io_int_word)
875 {
876 int isc = ffs(io_int_word << 2) - 1;
877
878 if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
879 /* ugh - can't queue anymore. Let's drop. */
880 return;
881 }
882
883 env->io_index[isc]++;
884 assert(env->io_index[isc] < MAX_IO_QUEUE);
885
886 env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
887 env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
888 env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
889 env->io_queue[env->io_index[isc]][isc].word = io_int_word;
890
891 env->pending_int |= INTERRUPT_IO;
892 cpu_interrupt(env, CPU_INTERRUPT_HARD);
893 }
894
895 static inline void cpu_inject_crw_mchk(CPUS390XState *env)
896 {
897 if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
898 /* ugh - can't queue anymore. Let's drop. */
899 return;
900 }
901
902 env->mchk_index++;
903 assert(env->mchk_index < MAX_MCHK_QUEUE);
904
905 env->mchk_queue[env->mchk_index].type = 1;
906
907 env->pending_int |= INTERRUPT_MCHK;
908 cpu_interrupt(env, CPU_INTERRUPT_HARD);
909 }
910
911 static inline bool cpu_has_work(CPUState *cpu)
912 {
913 CPUS390XState *env = &S390_CPU(cpu)->env;
914
915 return (env->interrupt_request & CPU_INTERRUPT_HARD) &&
916 (env->psw.mask & PSW_MASK_EXT);
917 }
918
919 static inline void cpu_pc_from_tb(CPUS390XState *env, TranslationBlock* tb)
920 {
921 env->psw.addr = tb->pc;
922 }
923
924 /* fpu_helper.c */
925 uint32_t set_cc_nz_f32(float32 v);
926 uint32_t set_cc_nz_f64(float64 v);
927 uint32_t set_cc_nz_f128(float128 v);
928
929 /* misc_helper.c */
930 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
931 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
932 uintptr_t retaddr);
933
934 #endif
Qemu copy for testing