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s390: Fix handling of iscs.
[qemu.git] / target-s390x / cpu.h
1 /*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 */
22 #ifndef CPU_S390X_H
23 #define CPU_S390X_H
24
25 #include "config.h"
26 #include "qemu-common.h"
27
28 #define TARGET_LONG_BITS 64
29
30 #define ELF_MACHINE EM_S390
31
32 #define CPUArchState struct CPUS390XState
33
34 #include "exec/cpu-defs.h"
35 #define TARGET_PAGE_BITS 12
36
37 #define TARGET_PHYS_ADDR_SPACE_BITS 64
38 #define TARGET_VIRT_ADDR_SPACE_BITS 64
39
40 #include "exec/cpu-all.h"
41
42 #include "fpu/softfloat.h"
43
44 #define NB_MMU_MODES 3
45
46 #define MMU_MODE0_SUFFIX _primary
47 #define MMU_MODE1_SUFFIX _secondary
48 #define MMU_MODE2_SUFFIX _home
49
50 #define MMU_USER_IDX 1
51
52 #define MAX_EXT_QUEUE 16
53 #define MAX_IO_QUEUE 16
54 #define MAX_MCHK_QUEUE 16
55
56 #define PSW_MCHK_MASK 0x0004000000000000
57 #define PSW_IO_MASK 0x0200000000000000
58
59 typedef struct PSW {
60 uint64_t mask;
61 uint64_t addr;
62 } PSW;
63
64 typedef struct ExtQueue {
65 uint32_t code;
66 uint32_t param;
67 uint32_t param64;
68 } ExtQueue;
69
70 typedef struct IOIntQueue {
71 uint16_t id;
72 uint16_t nr;
73 uint32_t parm;
74 uint32_t word;
75 } IOIntQueue;
76
77 typedef struct MchkQueue {
78 uint16_t type;
79 } MchkQueue;
80
81 typedef struct CPUS390XState {
82 uint64_t regs[16]; /* GP registers */
83 CPU_DoubleU fregs[16]; /* FP registers */
84 uint32_t aregs[16]; /* access registers */
85
86 uint32_t fpc; /* floating-point control register */
87 uint32_t cc_op;
88
89 float_status fpu_status; /* passed to softfloat lib */
90
91 /* The low part of a 128-bit return, or remainder of a divide. */
92 uint64_t retxl;
93
94 PSW psw;
95
96 uint64_t cc_src;
97 uint64_t cc_dst;
98 uint64_t cc_vr;
99
100 uint64_t __excp_addr;
101 uint64_t psa;
102
103 uint32_t int_pgm_code;
104 uint32_t int_pgm_ilen;
105
106 uint32_t int_svc_code;
107 uint32_t int_svc_ilen;
108
109 uint64_t cregs[16]; /* control registers */
110
111 ExtQueue ext_queue[MAX_EXT_QUEUE];
112 IOIntQueue io_queue[MAX_IO_QUEUE][8];
113 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
114
115 int pending_int;
116 int ext_index;
117 int io_index[8];
118 int mchk_index;
119
120 uint64_t ckc;
121 uint64_t cputm;
122 uint32_t todpr;
123
124 CPU_COMMON
125
126 /* reset does memset(0) up to here */
127
128 int cpu_num;
129 uint8_t *storage_keys;
130
131 uint64_t tod_offset;
132 uint64_t tod_basetime;
133 QEMUTimer *tod_timer;
134
135 QEMUTimer *cpu_timer;
136 } CPUS390XState;
137
138 #include "cpu-qom.h"
139
140 #if defined(CONFIG_USER_ONLY)
141 static inline void cpu_clone_regs(CPUS390XState *env, target_ulong newsp)
142 {
143 if (newsp) {
144 env->regs[15] = newsp;
145 }
146 env->regs[2] = 0;
147 }
148 #endif
149
150 /* distinguish between 24 bit and 31 bit addressing */
151 #define HIGH_ORDER_BIT 0x80000000
152
153 /* Interrupt Codes */
154 /* Program Interrupts */
155 #define PGM_OPERATION 0x0001
156 #define PGM_PRIVILEGED 0x0002
157 #define PGM_EXECUTE 0x0003
158 #define PGM_PROTECTION 0x0004
159 #define PGM_ADDRESSING 0x0005
160 #define PGM_SPECIFICATION 0x0006
161 #define PGM_DATA 0x0007
162 #define PGM_FIXPT_OVERFLOW 0x0008
163 #define PGM_FIXPT_DIVIDE 0x0009
164 #define PGM_DEC_OVERFLOW 0x000a
165 #define PGM_DEC_DIVIDE 0x000b
166 #define PGM_HFP_EXP_OVERFLOW 0x000c
167 #define PGM_HFP_EXP_UNDERFLOW 0x000d
168 #define PGM_HFP_SIGNIFICANCE 0x000e
169 #define PGM_HFP_DIVIDE 0x000f
170 #define PGM_SEGMENT_TRANS 0x0010
171 #define PGM_PAGE_TRANS 0x0011
172 #define PGM_TRANS_SPEC 0x0012
173 #define PGM_SPECIAL_OP 0x0013
174 #define PGM_OPERAND 0x0015
175 #define PGM_TRACE_TABLE 0x0016
176 #define PGM_SPACE_SWITCH 0x001c
177 #define PGM_HFP_SQRT 0x001d
178 #define PGM_PC_TRANS_SPEC 0x001f
179 #define PGM_AFX_TRANS 0x0020
180 #define PGM_ASX_TRANS 0x0021
181 #define PGM_LX_TRANS 0x0022
182 #define PGM_EX_TRANS 0x0023
183 #define PGM_PRIM_AUTH 0x0024
184 #define PGM_SEC_AUTH 0x0025
185 #define PGM_ALET_SPEC 0x0028
186 #define PGM_ALEN_SPEC 0x0029
187 #define PGM_ALE_SEQ 0x002a
188 #define PGM_ASTE_VALID 0x002b
189 #define PGM_ASTE_SEQ 0x002c
190 #define PGM_EXT_AUTH 0x002d
191 #define PGM_STACK_FULL 0x0030
192 #define PGM_STACK_EMPTY 0x0031
193 #define PGM_STACK_SPEC 0x0032
194 #define PGM_STACK_TYPE 0x0033
195 #define PGM_STACK_OP 0x0034
196 #define PGM_ASCE_TYPE 0x0038
197 #define PGM_REG_FIRST_TRANS 0x0039
198 #define PGM_REG_SEC_TRANS 0x003a
199 #define PGM_REG_THIRD_TRANS 0x003b
200 #define PGM_MONITOR 0x0040
201 #define PGM_PER 0x0080
202 #define PGM_CRYPTO 0x0119
203
204 /* External Interrupts */
205 #define EXT_INTERRUPT_KEY 0x0040
206 #define EXT_CLOCK_COMP 0x1004
207 #define EXT_CPU_TIMER 0x1005
208 #define EXT_MALFUNCTION 0x1200
209 #define EXT_EMERGENCY 0x1201
210 #define EXT_EXTERNAL_CALL 0x1202
211 #define EXT_ETR 0x1406
212 #define EXT_SERVICE 0x2401
213 #define EXT_VIRTIO 0x2603
214
215 /* PSW defines */
216 #undef PSW_MASK_PER
217 #undef PSW_MASK_DAT
218 #undef PSW_MASK_IO
219 #undef PSW_MASK_EXT
220 #undef PSW_MASK_KEY
221 #undef PSW_SHIFT_KEY
222 #undef PSW_MASK_MCHECK
223 #undef PSW_MASK_WAIT
224 #undef PSW_MASK_PSTATE
225 #undef PSW_MASK_ASC
226 #undef PSW_MASK_CC
227 #undef PSW_MASK_PM
228 #undef PSW_MASK_64
229
230 #define PSW_MASK_PER 0x4000000000000000ULL
231 #define PSW_MASK_DAT 0x0400000000000000ULL
232 #define PSW_MASK_IO 0x0200000000000000ULL
233 #define PSW_MASK_EXT 0x0100000000000000ULL
234 #define PSW_MASK_KEY 0x00F0000000000000ULL
235 #define PSW_SHIFT_KEY 56
236 #define PSW_MASK_MCHECK 0x0004000000000000ULL
237 #define PSW_MASK_WAIT 0x0002000000000000ULL
238 #define PSW_MASK_PSTATE 0x0001000000000000ULL
239 #define PSW_MASK_ASC 0x0000C00000000000ULL
240 #define PSW_MASK_CC 0x0000300000000000ULL
241 #define PSW_MASK_PM 0x00000F0000000000ULL
242 #define PSW_MASK_64 0x0000000100000000ULL
243 #define PSW_MASK_32 0x0000000080000000ULL
244
245 #undef PSW_ASC_PRIMARY
246 #undef PSW_ASC_ACCREG
247 #undef PSW_ASC_SECONDARY
248 #undef PSW_ASC_HOME
249
250 #define PSW_ASC_PRIMARY 0x0000000000000000ULL
251 #define PSW_ASC_ACCREG 0x0000400000000000ULL
252 #define PSW_ASC_SECONDARY 0x0000800000000000ULL
253 #define PSW_ASC_HOME 0x0000C00000000000ULL
254
255 /* tb flags */
256
257 #define FLAG_MASK_PER (PSW_MASK_PER >> 32)
258 #define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
259 #define FLAG_MASK_IO (PSW_MASK_IO >> 32)
260 #define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
261 #define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
262 #define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
263 #define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
264 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
265 #define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
266 #define FLAG_MASK_CC (PSW_MASK_CC >> 32)
267 #define FLAG_MASK_PM (PSW_MASK_PM >> 32)
268 #define FLAG_MASK_64 (PSW_MASK_64 >> 32)
269 #define FLAG_MASK_32 0x00001000
270
271 static inline int cpu_mmu_index (CPUS390XState *env)
272 {
273 if (env->psw.mask & PSW_MASK_PSTATE) {
274 return 1;
275 }
276
277 return 0;
278 }
279
280 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
281 target_ulong *cs_base, int *flags)
282 {
283 *pc = env->psw.addr;
284 *cs_base = 0;
285 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
286 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
287 }
288
289 /* While the PoO talks about ILC (a number between 1-3) what is actually
290 stored in LowCore is shifted left one bit (an even between 2-6). As
291 this is the actual length of the insn and therefore more useful, that
292 is what we want to pass around and manipulate. To make sure that we
293 have applied this distinction universally, rename the "ILC" to "ILEN". */
294 static inline int get_ilen(uint8_t opc)
295 {
296 switch (opc >> 6) {
297 case 0:
298 return 2;
299 case 1:
300 case 2:
301 return 4;
302 default:
303 return 6;
304 }
305 }
306
307 #ifndef CONFIG_USER_ONLY
308 /* In several cases of runtime exceptions, we havn't recorded the true
309 instruction length. Use these codes when raising exceptions in order
310 to re-compute the length by examining the insn in memory. */
311 #define ILEN_LATER 0x20
312 #define ILEN_LATER_INC 0x21
313 #endif
314
315 S390CPU *cpu_s390x_init(const char *cpu_model);
316 void s390x_translate_init(void);
317 int cpu_s390x_exec(CPUS390XState *s);
318 void cpu_s390x_close(CPUS390XState *s);
319 void do_interrupt (CPUS390XState *env);
320
321 /* you can call this signal handler from your SIGBUS and SIGSEGV
322 signal handlers to inform the virtual CPU of exceptions. non zero
323 is returned if the signal was handled by the virtual CPU. */
324 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
325 void *puc);
326 int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
327 int mmu_idx);
328 #define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault
329
330 #include "ioinst.h"
331
332 #ifndef CONFIG_USER_ONLY
333 void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
334 int is_write);
335 void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
336 int is_write);
337 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
338 {
339 hwaddr addr = 0;
340 uint8_t reg;
341
342 reg = ipb >> 28;
343 if (reg > 0) {
344 addr = env->regs[reg];
345 }
346 addr += (ipb >> 16) & 0xfff;
347
348 return addr;
349 }
350
351 void s390x_tod_timer(void *opaque);
352 void s390x_cpu_timer(void *opaque);
353
354 int s390_virtio_hypercall(CPUS390XState *env);
355
356 #ifdef CONFIG_KVM
357 void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code);
358 void kvm_s390_virtio_irq(S390CPU *cpu, int config_change, uint64_t token);
359 void kvm_s390_interrupt_internal(S390CPU *cpu, int type, uint32_t parm,
360 uint64_t parm64, int vm);
361 #else
362 static inline void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code)
363 {
364 }
365
366 static inline void kvm_s390_virtio_irq(S390CPU *cpu, int config_change,
367 uint64_t token)
368 {
369 }
370
371 static inline void kvm_s390_interrupt_internal(S390CPU *cpu, int type,
372 uint32_t parm, uint64_t parm64,
373 int vm)
374 {
375 }
376 #endif
377 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
378 void s390_add_running_cpu(S390CPU *cpu);
379 unsigned s390_del_running_cpu(S390CPU *cpu);
380
381 /* service interrupts are floating therefore we must not pass an cpustate */
382 void s390_sclp_extint(uint32_t parm);
383
384 /* from s390-virtio-bus */
385 extern const hwaddr virtio_size;
386
387 #else
388 static inline void s390_add_running_cpu(S390CPU *cpu)
389 {
390 }
391
392 static inline unsigned s390_del_running_cpu(S390CPU *cpu)
393 {
394 return 0;
395 }
396 #endif
397 void cpu_lock(void);
398 void cpu_unlock(void);
399
400 typedef struct SubchDev SubchDev;
401
402 #ifndef CONFIG_USER_ONLY
403 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
404 uint16_t schid);
405 bool css_subch_visible(SubchDev *sch);
406 void css_conditional_io_interrupt(SubchDev *sch);
407 int css_do_stsch(SubchDev *sch, SCHIB *schib);
408 bool css_schid_final(uint8_t cssid, uint8_t ssid, uint16_t schid);
409 int css_do_msch(SubchDev *sch, SCHIB *schib);
410 int css_do_xsch(SubchDev *sch);
411 int css_do_csch(SubchDev *sch);
412 int css_do_hsch(SubchDev *sch);
413 int css_do_ssch(SubchDev *sch, ORB *orb);
414 int css_do_tsch(SubchDev *sch, IRB *irb);
415 int css_do_stcrw(CRW *crw);
416 int css_do_tpi(IOIntCode *int_code, int lowcore);
417 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
418 int rfmt, void *buf);
419 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
420 int css_enable_mcsse(void);
421 int css_enable_mss(void);
422 int css_do_rsch(SubchDev *sch);
423 int css_do_rchp(uint8_t cssid, uint8_t chpid);
424 bool css_present(uint8_t cssid);
425 #else
426 static inline SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
427 uint16_t schid)
428 {
429 return NULL;
430 }
431 static inline bool css_subch_visible(SubchDev *sch)
432 {
433 return false;
434 }
435 static inline void css_conditional_io_interrupt(SubchDev *sch)
436 {
437 }
438 static inline int css_do_stsch(SubchDev *sch, SCHIB *schib)
439 {
440 return -ENODEV;
441 }
442 static inline bool css_schid_final(uint8_t cssid, uint8_t ssid, uint16_t schid)
443 {
444 return true;
445 }
446 static inline int css_do_msch(SubchDev *sch, SCHIB *schib)
447 {
448 return -ENODEV;
449 }
450 static inline int css_do_xsch(SubchDev *sch)
451 {
452 return -ENODEV;
453 }
454 static inline int css_do_csch(SubchDev *sch)
455 {
456 return -ENODEV;
457 }
458 static inline int css_do_hsch(SubchDev *sch)
459 {
460 return -ENODEV;
461 }
462 static inline int css_do_ssch(SubchDev *sch, ORB *orb)
463 {
464 return -ENODEV;
465 }
466 static inline int css_do_tsch(SubchDev *sch, IRB *irb)
467 {
468 return -ENODEV;
469 }
470 static inline int css_do_stcrw(CRW *crw)
471 {
472 return 1;
473 }
474 static inline int css_do_tpi(IOIntCode *int_code, int lowcore)
475 {
476 return 0;
477 }
478 static inline int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid,
479 int rfmt, uint8_t l_chpid, void *buf)
480 {
481 return 0;
482 }
483 static inline void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
484 {
485 }
486 static inline int css_enable_mss(void)
487 {
488 return -EINVAL;
489 }
490 static inline int css_enable_mcsse(void)
491 {
492 return -EINVAL;
493 }
494 static inline int css_do_rsch(SubchDev *sch)
495 {
496 return -ENODEV;
497 }
498 static inline int css_do_rchp(uint8_t cssid, uint8_t chpid)
499 {
500 return -ENODEV;
501 }
502 static inline bool css_present(uint8_t cssid)
503 {
504 return false;
505 }
506 #endif
507
508 static inline void cpu_set_tls(CPUS390XState *env, target_ulong newtls)
509 {
510 env->aregs[0] = newtls >> 32;
511 env->aregs[1] = newtls & 0xffffffffULL;
512 }
513
514 #define cpu_init(model) (&cpu_s390x_init(model)->env)
515 #define cpu_exec cpu_s390x_exec
516 #define cpu_gen_code cpu_s390x_gen_code
517 #define cpu_signal_handler cpu_s390x_signal_handler
518
519 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
520 #define cpu_list s390_cpu_list
521
522 #include "exec/exec-all.h"
523
524 #define EXCP_EXT 1 /* external interrupt */
525 #define EXCP_SVC 2 /* supervisor call (syscall) */
526 #define EXCP_PGM 3 /* program interruption */
527 #define EXCP_IO 7 /* I/O interrupt */
528 #define EXCP_MCHK 8 /* machine check */
529
530 #define INTERRUPT_EXT (1 << 0)
531 #define INTERRUPT_TOD (1 << 1)
532 #define INTERRUPT_CPUTIMER (1 << 2)
533 #define INTERRUPT_IO (1 << 3)
534 #define INTERRUPT_MCHK (1 << 4)
535
536 /* Program Status Word. */
537 #define S390_PSWM_REGNUM 0
538 #define S390_PSWA_REGNUM 1
539 /* General Purpose Registers. */
540 #define S390_R0_REGNUM 2
541 #define S390_R1_REGNUM 3
542 #define S390_R2_REGNUM 4
543 #define S390_R3_REGNUM 5
544 #define S390_R4_REGNUM 6
545 #define S390_R5_REGNUM 7
546 #define S390_R6_REGNUM 8
547 #define S390_R7_REGNUM 9
548 #define S390_R8_REGNUM 10
549 #define S390_R9_REGNUM 11
550 #define S390_R10_REGNUM 12
551 #define S390_R11_REGNUM 13
552 #define S390_R12_REGNUM 14
553 #define S390_R13_REGNUM 15
554 #define S390_R14_REGNUM 16
555 #define S390_R15_REGNUM 17
556 /* Access Registers. */
557 #define S390_A0_REGNUM 18
558 #define S390_A1_REGNUM 19
559 #define S390_A2_REGNUM 20
560 #define S390_A3_REGNUM 21
561 #define S390_A4_REGNUM 22
562 #define S390_A5_REGNUM 23
563 #define S390_A6_REGNUM 24
564 #define S390_A7_REGNUM 25
565 #define S390_A8_REGNUM 26
566 #define S390_A9_REGNUM 27
567 #define S390_A10_REGNUM 28
568 #define S390_A11_REGNUM 29
569 #define S390_A12_REGNUM 30
570 #define S390_A13_REGNUM 31
571 #define S390_A14_REGNUM 32
572 #define S390_A15_REGNUM 33
573 /* Floating Point Control Word. */
574 #define S390_FPC_REGNUM 34
575 /* Floating Point Registers. */
576 #define S390_F0_REGNUM 35
577 #define S390_F1_REGNUM 36
578 #define S390_F2_REGNUM 37
579 #define S390_F3_REGNUM 38
580 #define S390_F4_REGNUM 39
581 #define S390_F5_REGNUM 40
582 #define S390_F6_REGNUM 41
583 #define S390_F7_REGNUM 42
584 #define S390_F8_REGNUM 43
585 #define S390_F9_REGNUM 44
586 #define S390_F10_REGNUM 45
587 #define S390_F11_REGNUM 46
588 #define S390_F12_REGNUM 47
589 #define S390_F13_REGNUM 48
590 #define S390_F14_REGNUM 49
591 #define S390_F15_REGNUM 50
592 /* Total. */
593 #define S390_NUM_REGS 51
594
595 /* CC optimization */
596
597 enum cc_op {
598 CC_OP_CONST0 = 0, /* CC is 0 */
599 CC_OP_CONST1, /* CC is 1 */
600 CC_OP_CONST2, /* CC is 2 */
601 CC_OP_CONST3, /* CC is 3 */
602
603 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
604 CC_OP_STATIC, /* CC value is env->cc_op */
605
606 CC_OP_NZ, /* env->cc_dst != 0 */
607 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
608 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
609 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
610 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
611 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
612 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
613
614 CC_OP_ADD_64, /* overflow on add (64bit) */
615 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
616 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
617 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
618 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
619 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
620 CC_OP_ABS_64, /* sign eval on abs (64bit) */
621 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
622
623 CC_OP_ADD_32, /* overflow on add (32bit) */
624 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
625 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
626 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
627 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
628 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
629 CC_OP_ABS_32, /* sign eval on abs (64bit) */
630 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
631
632 CC_OP_COMP_32, /* complement */
633 CC_OP_COMP_64, /* complement */
634
635 CC_OP_TM_32, /* test under mask (32bit) */
636 CC_OP_TM_64, /* test under mask (64bit) */
637
638 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
639 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
640 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
641
642 CC_OP_ICM, /* insert characters under mask */
643 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
644 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
645 CC_OP_FLOGR, /* find leftmost one */
646 CC_OP_MAX
647 };
648
649 static const char *cc_names[] = {
650 [CC_OP_CONST0] = "CC_OP_CONST0",
651 [CC_OP_CONST1] = "CC_OP_CONST1",
652 [CC_OP_CONST2] = "CC_OP_CONST2",
653 [CC_OP_CONST3] = "CC_OP_CONST3",
654 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
655 [CC_OP_STATIC] = "CC_OP_STATIC",
656 [CC_OP_NZ] = "CC_OP_NZ",
657 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
658 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
659 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
660 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
661 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
662 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
663 [CC_OP_ADD_64] = "CC_OP_ADD_64",
664 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
665 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
666 [CC_OP_SUB_64] = "CC_OP_SUB_64",
667 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
668 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
669 [CC_OP_ABS_64] = "CC_OP_ABS_64",
670 [CC_OP_NABS_64] = "CC_OP_NABS_64",
671 [CC_OP_ADD_32] = "CC_OP_ADD_32",
672 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
673 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
674 [CC_OP_SUB_32] = "CC_OP_SUB_32",
675 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
676 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
677 [CC_OP_ABS_32] = "CC_OP_ABS_32",
678 [CC_OP_NABS_32] = "CC_OP_NABS_32",
679 [CC_OP_COMP_32] = "CC_OP_COMP_32",
680 [CC_OP_COMP_64] = "CC_OP_COMP_64",
681 [CC_OP_TM_32] = "CC_OP_TM_32",
682 [CC_OP_TM_64] = "CC_OP_TM_64",
683 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
684 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
685 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
686 [CC_OP_ICM] = "CC_OP_ICM",
687 [CC_OP_SLA_32] = "CC_OP_SLA_32",
688 [CC_OP_SLA_64] = "CC_OP_SLA_64",
689 [CC_OP_FLOGR] = "CC_OP_FLOGR",
690 };
691
692 static inline const char *cc_name(int cc_op)
693 {
694 return cc_names[cc_op];
695 }
696
697 typedef struct LowCore
698 {
699 /* prefix area: defined by architecture */
700 uint32_t ccw1[2]; /* 0x000 */
701 uint32_t ccw2[4]; /* 0x008 */
702 uint8_t pad1[0x80-0x18]; /* 0x018 */
703 uint32_t ext_params; /* 0x080 */
704 uint16_t cpu_addr; /* 0x084 */
705 uint16_t ext_int_code; /* 0x086 */
706 uint16_t svc_ilen; /* 0x088 */
707 uint16_t svc_code; /* 0x08a */
708 uint16_t pgm_ilen; /* 0x08c */
709 uint16_t pgm_code; /* 0x08e */
710 uint32_t data_exc_code; /* 0x090 */
711 uint16_t mon_class_num; /* 0x094 */
712 uint16_t per_perc_atmid; /* 0x096 */
713 uint64_t per_address; /* 0x098 */
714 uint8_t exc_access_id; /* 0x0a0 */
715 uint8_t per_access_id; /* 0x0a1 */
716 uint8_t op_access_id; /* 0x0a2 */
717 uint8_t ar_access_id; /* 0x0a3 */
718 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
719 uint64_t trans_exc_code; /* 0x0a8 */
720 uint64_t monitor_code; /* 0x0b0 */
721 uint16_t subchannel_id; /* 0x0b8 */
722 uint16_t subchannel_nr; /* 0x0ba */
723 uint32_t io_int_parm; /* 0x0bc */
724 uint32_t io_int_word; /* 0x0c0 */
725 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
726 uint32_t stfl_fac_list; /* 0x0c8 */
727 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
728 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
729 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
730 uint32_t external_damage_code; /* 0x0f4 */
731 uint64_t failing_storage_address; /* 0x0f8 */
732 uint8_t pad6[0x120-0x100]; /* 0x100 */
733 PSW restart_old_psw; /* 0x120 */
734 PSW external_old_psw; /* 0x130 */
735 PSW svc_old_psw; /* 0x140 */
736 PSW program_old_psw; /* 0x150 */
737 PSW mcck_old_psw; /* 0x160 */
738 PSW io_old_psw; /* 0x170 */
739 uint8_t pad7[0x1a0-0x180]; /* 0x180 */
740 PSW restart_psw; /* 0x1a0 */
741 PSW external_new_psw; /* 0x1b0 */
742 PSW svc_new_psw; /* 0x1c0 */
743 PSW program_new_psw; /* 0x1d0 */
744 PSW mcck_new_psw; /* 0x1e0 */
745 PSW io_new_psw; /* 0x1f0 */
746 PSW return_psw; /* 0x200 */
747 uint8_t irb[64]; /* 0x210 */
748 uint64_t sync_enter_timer; /* 0x250 */
749 uint64_t async_enter_timer; /* 0x258 */
750 uint64_t exit_timer; /* 0x260 */
751 uint64_t last_update_timer; /* 0x268 */
752 uint64_t user_timer; /* 0x270 */
753 uint64_t system_timer; /* 0x278 */
754 uint64_t last_update_clock; /* 0x280 */
755 uint64_t steal_clock; /* 0x288 */
756 PSW return_mcck_psw; /* 0x290 */
757 uint8_t pad8[0xc00-0x2a0]; /* 0x2a0 */
758 /* System info area */
759 uint64_t save_area[16]; /* 0xc00 */
760 uint8_t pad9[0xd40-0xc80]; /* 0xc80 */
761 uint64_t kernel_stack; /* 0xd40 */
762 uint64_t thread_info; /* 0xd48 */
763 uint64_t async_stack; /* 0xd50 */
764 uint64_t kernel_asce; /* 0xd58 */
765 uint64_t user_asce; /* 0xd60 */
766 uint64_t panic_stack; /* 0xd68 */
767 uint64_t user_exec_asce; /* 0xd70 */
768 uint8_t pad10[0xdc0-0xd78]; /* 0xd78 */
769
770 /* SMP info area: defined by DJB */
771 uint64_t clock_comparator; /* 0xdc0 */
772 uint64_t ext_call_fast; /* 0xdc8 */
773 uint64_t percpu_offset; /* 0xdd0 */
774 uint64_t current_task; /* 0xdd8 */
775 uint32_t softirq_pending; /* 0xde0 */
776 uint32_t pad_0x0de4; /* 0xde4 */
777 uint64_t int_clock; /* 0xde8 */
778 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
779
780 /* 0xe00 is used as indicator for dump tools */
781 /* whether the kernel died with panic() or not */
782 uint32_t panic_magic; /* 0xe00 */
783
784 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
785
786 /* 64 bit extparam used for pfault, diag 250 etc */
787 uint64_t ext_params2; /* 0x11B8 */
788
789 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
790
791 /* System info area */
792
793 uint64_t floating_pt_save_area[16]; /* 0x1200 */
794 uint64_t gpregs_save_area[16]; /* 0x1280 */
795 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
796 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
797 uint32_t prefixreg_save_area; /* 0x1318 */
798 uint32_t fpt_creg_save_area; /* 0x131c */
799 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
800 uint32_t tod_progreg_save_area; /* 0x1324 */
801 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
802 uint32_t clock_comp_save_area[2]; /* 0x1330 */
803 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
804 uint32_t access_regs_save_area[16]; /* 0x1340 */
805 uint64_t cregs_save_area[16]; /* 0x1380 */
806
807 /* align to the top of the prefix area */
808
809 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
810 } QEMU_PACKED LowCore;
811
812 /* STSI */
813 #define STSI_LEVEL_MASK 0x00000000f0000000ULL
814 #define STSI_LEVEL_CURRENT 0x0000000000000000ULL
815 #define STSI_LEVEL_1 0x0000000010000000ULL
816 #define STSI_LEVEL_2 0x0000000020000000ULL
817 #define STSI_LEVEL_3 0x0000000030000000ULL
818 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
819 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL
820 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
821 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL
822
823 /* Basic Machine Configuration */
824 struct sysib_111 {
825 uint32_t res1[8];
826 uint8_t manuf[16];
827 uint8_t type[4];
828 uint8_t res2[12];
829 uint8_t model[16];
830 uint8_t sequence[16];
831 uint8_t plant[4];
832 uint8_t res3[156];
833 };
834
835 /* Basic Machine CPU */
836 struct sysib_121 {
837 uint32_t res1[80];
838 uint8_t sequence[16];
839 uint8_t plant[4];
840 uint8_t res2[2];
841 uint16_t cpu_addr;
842 uint8_t res3[152];
843 };
844
845 /* Basic Machine CPUs */
846 struct sysib_122 {
847 uint8_t res1[32];
848 uint32_t capability;
849 uint16_t total_cpus;
850 uint16_t active_cpus;
851 uint16_t standby_cpus;
852 uint16_t reserved_cpus;
853 uint16_t adjustments[2026];
854 };
855
856 /* LPAR CPU */
857 struct sysib_221 {
858 uint32_t res1[80];
859 uint8_t sequence[16];
860 uint8_t plant[4];
861 uint16_t cpu_id;
862 uint16_t cpu_addr;
863 uint8_t res3[152];
864 };
865
866 /* LPAR CPUs */
867 struct sysib_222 {
868 uint32_t res1[32];
869 uint16_t lpar_num;
870 uint8_t res2;
871 uint8_t lcpuc;
872 uint16_t total_cpus;
873 uint16_t conf_cpus;
874 uint16_t standby_cpus;
875 uint16_t reserved_cpus;
876 uint8_t name[8];
877 uint32_t caf;
878 uint8_t res3[16];
879 uint16_t dedicated_cpus;
880 uint16_t shared_cpus;
881 uint8_t res4[180];
882 };
883
884 /* VM CPUs */
885 struct sysib_322 {
886 uint8_t res1[31];
887 uint8_t count;
888 struct {
889 uint8_t res2[4];
890 uint16_t total_cpus;
891 uint16_t conf_cpus;
892 uint16_t standby_cpus;
893 uint16_t reserved_cpus;
894 uint8_t name[8];
895 uint32_t caf;
896 uint8_t cpi[16];
897 uint8_t res3[24];
898 } vm[8];
899 uint8_t res4[3552];
900 };
901
902 /* MMU defines */
903 #define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
904 #define _ASCE_SUBSPACE 0x200 /* subspace group control */
905 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
906 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
907 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
908 #define _ASCE_REAL_SPACE 0x20 /* real space control */
909 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
910 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */
911 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */
912 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */
913 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
914 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */
915
916 #define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
917 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
918 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
919 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
920 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
921 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
922 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */
923
924 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
925 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
926 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
927
928 #define _PAGE_RO 0x200 /* HW read-only bit */
929 #define _PAGE_INVALID 0x400 /* HW invalid bit */
930
931 #define SK_C (0x1 << 1)
932 #define SK_R (0x1 << 2)
933 #define SK_F (0x1 << 3)
934 #define SK_ACC_MASK (0xf << 4)
935
936 #define SIGP_SENSE 0x01
937 #define SIGP_EXTERNAL_CALL 0x02
938 #define SIGP_EMERGENCY 0x03
939 #define SIGP_START 0x04
940 #define SIGP_STOP 0x05
941 #define SIGP_RESTART 0x06
942 #define SIGP_STOP_STORE_STATUS 0x09
943 #define SIGP_INITIAL_CPU_RESET 0x0b
944 #define SIGP_CPU_RESET 0x0c
945 #define SIGP_SET_PREFIX 0x0d
946 #define SIGP_STORE_STATUS_ADDR 0x0e
947 #define SIGP_SET_ARCH 0x12
948
949 /* cpu status bits */
950 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
951 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL
952 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
953 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
954 #define SIGP_STAT_STOPPED 0x00000040UL
955 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
956 #define SIGP_STAT_CHECK_STOP 0x00000010UL
957 #define SIGP_STAT_INOPERATIVE 0x00000004UL
958 #define SIGP_STAT_INVALID_ORDER 0x00000002UL
959 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
960
961 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
962 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
963 target_ulong *raddr, int *flags);
964 int sclp_service_call(uint32_t sccb, uint64_t code);
965 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
966 uint64_t vr);
967
968 #define TARGET_HAS_ICE 1
969
970 /* The value of the TOD clock for 1.1.1970. */
971 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
972
973 /* Converts ns to s390's clock format */
974 static inline uint64_t time2tod(uint64_t ns) {
975 return (ns << 9) / 125;
976 }
977
978 static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
979 uint64_t param64)
980 {
981 CPUS390XState *env = &cpu->env;
982
983 if (env->ext_index == MAX_EXT_QUEUE - 1) {
984 /* ugh - can't queue anymore. Let's drop. */
985 return;
986 }
987
988 env->ext_index++;
989 assert(env->ext_index < MAX_EXT_QUEUE);
990
991 env->ext_queue[env->ext_index].code = code;
992 env->ext_queue[env->ext_index].param = param;
993 env->ext_queue[env->ext_index].param64 = param64;
994
995 env->pending_int |= INTERRUPT_EXT;
996 cpu_interrupt(env, CPU_INTERRUPT_HARD);
997 }
998
999 static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
1000 uint16_t subchannel_number,
1001 uint32_t io_int_parm, uint32_t io_int_word)
1002 {
1003 CPUS390XState *env = &cpu->env;
1004 int isc = IO_INT_WORD_ISC(io_int_word);
1005
1006 if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1007 /* ugh - can't queue anymore. Let's drop. */
1008 return;
1009 }
1010
1011 env->io_index[isc]++;
1012 assert(env->io_index[isc] < MAX_IO_QUEUE);
1013
1014 env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1015 env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1016 env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1017 env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1018
1019 env->pending_int |= INTERRUPT_IO;
1020 cpu_interrupt(env, CPU_INTERRUPT_HARD);
1021 }
1022
1023 static inline void cpu_inject_crw_mchk(S390CPU *cpu)
1024 {
1025 CPUS390XState *env = &cpu->env;
1026
1027 if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1028 /* ugh - can't queue anymore. Let's drop. */
1029 return;
1030 }
1031
1032 env->mchk_index++;
1033 assert(env->mchk_index < MAX_MCHK_QUEUE);
1034
1035 env->mchk_queue[env->mchk_index].type = 1;
1036
1037 env->pending_int |= INTERRUPT_MCHK;
1038 cpu_interrupt(env, CPU_INTERRUPT_HARD);
1039 }
1040
1041 static inline bool cpu_has_work(CPUState *cpu)
1042 {
1043 CPUS390XState *env = &S390_CPU(cpu)->env;
1044
1045 return (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1046 (env->psw.mask & PSW_MASK_EXT);
1047 }
1048
1049 static inline void cpu_pc_from_tb(CPUS390XState *env, TranslationBlock* tb)
1050 {
1051 env->psw.addr = tb->pc;
1052 }
1053
1054 /* fpu_helper.c */
1055 uint32_t set_cc_nz_f32(float32 v);
1056 uint32_t set_cc_nz_f64(float64 v);
1057 uint32_t set_cc_nz_f128(float128 v);
1058
1059 /* misc_helper.c */
1060 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1061 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1062 uintptr_t retaddr);
1063
1064 #include <sysemu/kvm.h>
1065
1066 #ifdef CONFIG_KVM
1067 void kvm_s390_io_interrupt(S390CPU *cpu, uint16_t subchannel_id,
1068 uint16_t subchannel_nr, uint32_t io_int_parm,
1069 uint32_t io_int_word);
1070 void kvm_s390_crw_mchk(S390CPU *cpu);
1071 void kvm_s390_enable_css_support(S390CPU *cpu);
1072 #else
1073 static inline void kvm_s390_io_interrupt(S390CPU *cpu,
1074 uint16_t subchannel_id,
1075 uint16_t subchannel_nr,
1076 uint32_t io_int_parm,
1077 uint32_t io_int_word)
1078 {
1079 }
1080 static inline void kvm_s390_crw_mchk(S390CPU *cpu)
1081 {
1082 }
1083 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1084 {
1085 }
1086 #endif
1087
1088 static inline void s390_io_interrupt(S390CPU *cpu,
1089 uint16_t subchannel_id,
1090 uint16_t subchannel_nr,
1091 uint32_t io_int_parm,
1092 uint32_t io_int_word)
1093 {
1094 if (kvm_enabled()) {
1095 kvm_s390_io_interrupt(cpu, subchannel_id, subchannel_nr, io_int_parm,
1096 io_int_word);
1097 } else {
1098 cpu_inject_io(cpu, subchannel_id, subchannel_nr, io_int_parm,
1099 io_int_word);
1100 }
1101 }
1102
1103 static inline void s390_crw_mchk(S390CPU *cpu)
1104 {
1105 if (kvm_enabled()) {
1106 kvm_s390_crw_mchk(cpu);
1107 } else {
1108 cpu_inject_crw_mchk(cpu);
1109 }
1110 }
1111
1112 #endif
Qemu copy for testing