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s390x: Remove inline function ebcdic_put and related data from cpu.h
[qemu.git] / target-s390x / cpu.h
1 /*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 */
22 #ifndef CPU_S390X_H
23 #define CPU_S390X_H
24
25 #include "config.h"
26 #include "qemu-common.h"
27
28 #define TARGET_LONG_BITS 64
29
30 #define ELF_MACHINE EM_S390
31
32 #define CPUArchState struct CPUS390XState
33
34 #include "exec/cpu-defs.h"
35 #define TARGET_PAGE_BITS 12
36
37 #define TARGET_PHYS_ADDR_SPACE_BITS 64
38 #define TARGET_VIRT_ADDR_SPACE_BITS 64
39
40 #include "exec/cpu-all.h"
41
42 #include "fpu/softfloat.h"
43
44 #define NB_MMU_MODES 3
45
46 #define MMU_MODE0_SUFFIX _primary
47 #define MMU_MODE1_SUFFIX _secondary
48 #define MMU_MODE2_SUFFIX _home
49
50 #define MMU_USER_IDX 1
51
52 #define MAX_EXT_QUEUE 16
53
54 typedef struct PSW {
55 uint64_t mask;
56 uint64_t addr;
57 } PSW;
58
59 typedef struct ExtQueue {
60 uint32_t code;
61 uint32_t param;
62 uint32_t param64;
63 } ExtQueue;
64
65 typedef struct CPUS390XState {
66 uint64_t regs[16]; /* GP registers */
67 CPU_DoubleU fregs[16]; /* FP registers */
68 uint32_t aregs[16]; /* access registers */
69
70 uint32_t fpc; /* floating-point control register */
71 uint32_t cc_op;
72
73 float_status fpu_status; /* passed to softfloat lib */
74
75 /* The low part of a 128-bit return, or remainder of a divide. */
76 uint64_t retxl;
77
78 PSW psw;
79
80 uint64_t cc_src;
81 uint64_t cc_dst;
82 uint64_t cc_vr;
83
84 uint64_t __excp_addr;
85 uint64_t psa;
86
87 uint32_t int_pgm_code;
88 uint32_t int_pgm_ilen;
89
90 uint32_t int_svc_code;
91 uint32_t int_svc_ilen;
92
93 uint64_t cregs[16]; /* control registers */
94
95 ExtQueue ext_queue[MAX_EXT_QUEUE];
96 int pending_int;
97
98 int ext_index;
99
100 CPU_COMMON
101
102 /* reset does memset(0) up to here */
103
104 int cpu_num;
105 uint8_t *storage_keys;
106
107 uint64_t tod_offset;
108 uint64_t tod_basetime;
109 QEMUTimer *tod_timer;
110
111 QEMUTimer *cpu_timer;
112 } CPUS390XState;
113
114 #include "cpu-qom.h"
115
116 #if defined(CONFIG_USER_ONLY)
117 static inline void cpu_clone_regs(CPUS390XState *env, target_ulong newsp)
118 {
119 if (newsp) {
120 env->regs[15] = newsp;
121 }
122 env->regs[2] = 0;
123 }
124 #endif
125
126 /* Interrupt Codes */
127 /* Program Interrupts */
128 #define PGM_OPERATION 0x0001
129 #define PGM_PRIVILEGED 0x0002
130 #define PGM_EXECUTE 0x0003
131 #define PGM_PROTECTION 0x0004
132 #define PGM_ADDRESSING 0x0005
133 #define PGM_SPECIFICATION 0x0006
134 #define PGM_DATA 0x0007
135 #define PGM_FIXPT_OVERFLOW 0x0008
136 #define PGM_FIXPT_DIVIDE 0x0009
137 #define PGM_DEC_OVERFLOW 0x000a
138 #define PGM_DEC_DIVIDE 0x000b
139 #define PGM_HFP_EXP_OVERFLOW 0x000c
140 #define PGM_HFP_EXP_UNDERFLOW 0x000d
141 #define PGM_HFP_SIGNIFICANCE 0x000e
142 #define PGM_HFP_DIVIDE 0x000f
143 #define PGM_SEGMENT_TRANS 0x0010
144 #define PGM_PAGE_TRANS 0x0011
145 #define PGM_TRANS_SPEC 0x0012
146 #define PGM_SPECIAL_OP 0x0013
147 #define PGM_OPERAND 0x0015
148 #define PGM_TRACE_TABLE 0x0016
149 #define PGM_SPACE_SWITCH 0x001c
150 #define PGM_HFP_SQRT 0x001d
151 #define PGM_PC_TRANS_SPEC 0x001f
152 #define PGM_AFX_TRANS 0x0020
153 #define PGM_ASX_TRANS 0x0021
154 #define PGM_LX_TRANS 0x0022
155 #define PGM_EX_TRANS 0x0023
156 #define PGM_PRIM_AUTH 0x0024
157 #define PGM_SEC_AUTH 0x0025
158 #define PGM_ALET_SPEC 0x0028
159 #define PGM_ALEN_SPEC 0x0029
160 #define PGM_ALE_SEQ 0x002a
161 #define PGM_ASTE_VALID 0x002b
162 #define PGM_ASTE_SEQ 0x002c
163 #define PGM_EXT_AUTH 0x002d
164 #define PGM_STACK_FULL 0x0030
165 #define PGM_STACK_EMPTY 0x0031
166 #define PGM_STACK_SPEC 0x0032
167 #define PGM_STACK_TYPE 0x0033
168 #define PGM_STACK_OP 0x0034
169 #define PGM_ASCE_TYPE 0x0038
170 #define PGM_REG_FIRST_TRANS 0x0039
171 #define PGM_REG_SEC_TRANS 0x003a
172 #define PGM_REG_THIRD_TRANS 0x003b
173 #define PGM_MONITOR 0x0040
174 #define PGM_PER 0x0080
175 #define PGM_CRYPTO 0x0119
176
177 /* External Interrupts */
178 #define EXT_INTERRUPT_KEY 0x0040
179 #define EXT_CLOCK_COMP 0x1004
180 #define EXT_CPU_TIMER 0x1005
181 #define EXT_MALFUNCTION 0x1200
182 #define EXT_EMERGENCY 0x1201
183 #define EXT_EXTERNAL_CALL 0x1202
184 #define EXT_ETR 0x1406
185 #define EXT_SERVICE 0x2401
186 #define EXT_VIRTIO 0x2603
187
188 /* PSW defines */
189 #undef PSW_MASK_PER
190 #undef PSW_MASK_DAT
191 #undef PSW_MASK_IO
192 #undef PSW_MASK_EXT
193 #undef PSW_MASK_KEY
194 #undef PSW_SHIFT_KEY
195 #undef PSW_MASK_MCHECK
196 #undef PSW_MASK_WAIT
197 #undef PSW_MASK_PSTATE
198 #undef PSW_MASK_ASC
199 #undef PSW_MASK_CC
200 #undef PSW_MASK_PM
201 #undef PSW_MASK_64
202
203 #define PSW_MASK_PER 0x4000000000000000ULL
204 #define PSW_MASK_DAT 0x0400000000000000ULL
205 #define PSW_MASK_IO 0x0200000000000000ULL
206 #define PSW_MASK_EXT 0x0100000000000000ULL
207 #define PSW_MASK_KEY 0x00F0000000000000ULL
208 #define PSW_SHIFT_KEY 56
209 #define PSW_MASK_MCHECK 0x0004000000000000ULL
210 #define PSW_MASK_WAIT 0x0002000000000000ULL
211 #define PSW_MASK_PSTATE 0x0001000000000000ULL
212 #define PSW_MASK_ASC 0x0000C00000000000ULL
213 #define PSW_MASK_CC 0x0000300000000000ULL
214 #define PSW_MASK_PM 0x00000F0000000000ULL
215 #define PSW_MASK_64 0x0000000100000000ULL
216 #define PSW_MASK_32 0x0000000080000000ULL
217
218 #undef PSW_ASC_PRIMARY
219 #undef PSW_ASC_ACCREG
220 #undef PSW_ASC_SECONDARY
221 #undef PSW_ASC_HOME
222
223 #define PSW_ASC_PRIMARY 0x0000000000000000ULL
224 #define PSW_ASC_ACCREG 0x0000400000000000ULL
225 #define PSW_ASC_SECONDARY 0x0000800000000000ULL
226 #define PSW_ASC_HOME 0x0000C00000000000ULL
227
228 /* tb flags */
229
230 #define FLAG_MASK_PER (PSW_MASK_PER >> 32)
231 #define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
232 #define FLAG_MASK_IO (PSW_MASK_IO >> 32)
233 #define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
234 #define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
235 #define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
236 #define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
237 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
238 #define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
239 #define FLAG_MASK_CC (PSW_MASK_CC >> 32)
240 #define FLAG_MASK_PM (PSW_MASK_PM >> 32)
241 #define FLAG_MASK_64 (PSW_MASK_64 >> 32)
242 #define FLAG_MASK_32 0x00001000
243
244 static inline int cpu_mmu_index (CPUS390XState *env)
245 {
246 if (env->psw.mask & PSW_MASK_PSTATE) {
247 return 1;
248 }
249
250 return 0;
251 }
252
253 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
254 target_ulong *cs_base, int *flags)
255 {
256 *pc = env->psw.addr;
257 *cs_base = 0;
258 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
259 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
260 }
261
262 /* While the PoO talks about ILC (a number between 1-3) what is actually
263 stored in LowCore is shifted left one bit (an even between 2-6). As
264 this is the actual length of the insn and therefore more useful, that
265 is what we want to pass around and manipulate. To make sure that we
266 have applied this distinction universally, rename the "ILC" to "ILEN". */
267 static inline int get_ilen(uint8_t opc)
268 {
269 switch (opc >> 6) {
270 case 0:
271 return 2;
272 case 1:
273 case 2:
274 return 4;
275 default:
276 return 6;
277 }
278 }
279
280 #ifndef CONFIG_USER_ONLY
281 /* In several cases of runtime exceptions, we havn't recorded the true
282 instruction length. Use these codes when raising exceptions in order
283 to re-compute the length by examining the insn in memory. */
284 #define ILEN_LATER 0x20
285 #define ILEN_LATER_INC 0x21
286 #endif
287
288 S390CPU *cpu_s390x_init(const char *cpu_model);
289 void s390x_translate_init(void);
290 int cpu_s390x_exec(CPUS390XState *s);
291 void cpu_s390x_close(CPUS390XState *s);
292 void do_interrupt (CPUS390XState *env);
293
294 /* you can call this signal handler from your SIGBUS and SIGSEGV
295 signal handlers to inform the virtual CPU of exceptions. non zero
296 is returned if the signal was handled by the virtual CPU. */
297 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
298 void *puc);
299 int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
300 int mmu_idx);
301 #define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault
302
303
304 #ifndef CONFIG_USER_ONLY
305 void s390x_tod_timer(void *opaque);
306 void s390x_cpu_timer(void *opaque);
307
308 int s390_virtio_hypercall(CPUS390XState *env, uint64_t mem, uint64_t hypercall);
309
310 #ifdef CONFIG_KVM
311 void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code);
312 void kvm_s390_virtio_irq(S390CPU *cpu, int config_change, uint64_t token);
313 void kvm_s390_interrupt_internal(S390CPU *cpu, int type, uint32_t parm,
314 uint64_t parm64, int vm);
315 #else
316 static inline void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code)
317 {
318 }
319
320 static inline void kvm_s390_virtio_irq(S390CPU *cpu, int config_change,
321 uint64_t token)
322 {
323 }
324
325 static inline void kvm_s390_interrupt_internal(S390CPU *cpu, int type,
326 uint32_t parm, uint64_t parm64,
327 int vm)
328 {
329 }
330 #endif
331 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
332 void s390_add_running_cpu(CPUS390XState *env);
333 unsigned s390_del_running_cpu(CPUS390XState *env);
334
335 /* service interrupts are floating therefore we must not pass an cpustate */
336 void s390_sclp_extint(uint32_t parm);
337
338 /* from s390-virtio-bus */
339 extern const hwaddr virtio_size;
340
341 #else
342 static inline void s390_add_running_cpu(CPUS390XState *env)
343 {
344 }
345
346 static inline unsigned s390_del_running_cpu(CPUS390XState *env)
347 {
348 return 0;
349 }
350 #endif
351 void cpu_lock(void);
352 void cpu_unlock(void);
353
354 static inline void cpu_set_tls(CPUS390XState *env, target_ulong newtls)
355 {
356 env->aregs[0] = newtls >> 32;
357 env->aregs[1] = newtls & 0xffffffffULL;
358 }
359
360 #define cpu_init(model) (&cpu_s390x_init(model)->env)
361 #define cpu_exec cpu_s390x_exec
362 #define cpu_gen_code cpu_s390x_gen_code
363 #define cpu_signal_handler cpu_s390x_signal_handler
364
365 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
366 #define cpu_list s390_cpu_list
367
368 #include "exec/exec-all.h"
369
370 #define EXCP_EXT 1 /* external interrupt */
371 #define EXCP_SVC 2 /* supervisor call (syscall) */
372 #define EXCP_PGM 3 /* program interruption */
373
374 #define INTERRUPT_EXT (1 << 0)
375 #define INTERRUPT_TOD (1 << 1)
376 #define INTERRUPT_CPUTIMER (1 << 2)
377
378 /* Program Status Word. */
379 #define S390_PSWM_REGNUM 0
380 #define S390_PSWA_REGNUM 1
381 /* General Purpose Registers. */
382 #define S390_R0_REGNUM 2
383 #define S390_R1_REGNUM 3
384 #define S390_R2_REGNUM 4
385 #define S390_R3_REGNUM 5
386 #define S390_R4_REGNUM 6
387 #define S390_R5_REGNUM 7
388 #define S390_R6_REGNUM 8
389 #define S390_R7_REGNUM 9
390 #define S390_R8_REGNUM 10
391 #define S390_R9_REGNUM 11
392 #define S390_R10_REGNUM 12
393 #define S390_R11_REGNUM 13
394 #define S390_R12_REGNUM 14
395 #define S390_R13_REGNUM 15
396 #define S390_R14_REGNUM 16
397 #define S390_R15_REGNUM 17
398 /* Access Registers. */
399 #define S390_A0_REGNUM 18
400 #define S390_A1_REGNUM 19
401 #define S390_A2_REGNUM 20
402 #define S390_A3_REGNUM 21
403 #define S390_A4_REGNUM 22
404 #define S390_A5_REGNUM 23
405 #define S390_A6_REGNUM 24
406 #define S390_A7_REGNUM 25
407 #define S390_A8_REGNUM 26
408 #define S390_A9_REGNUM 27
409 #define S390_A10_REGNUM 28
410 #define S390_A11_REGNUM 29
411 #define S390_A12_REGNUM 30
412 #define S390_A13_REGNUM 31
413 #define S390_A14_REGNUM 32
414 #define S390_A15_REGNUM 33
415 /* Floating Point Control Word. */
416 #define S390_FPC_REGNUM 34
417 /* Floating Point Registers. */
418 #define S390_F0_REGNUM 35
419 #define S390_F1_REGNUM 36
420 #define S390_F2_REGNUM 37
421 #define S390_F3_REGNUM 38
422 #define S390_F4_REGNUM 39
423 #define S390_F5_REGNUM 40
424 #define S390_F6_REGNUM 41
425 #define S390_F7_REGNUM 42
426 #define S390_F8_REGNUM 43
427 #define S390_F9_REGNUM 44
428 #define S390_F10_REGNUM 45
429 #define S390_F11_REGNUM 46
430 #define S390_F12_REGNUM 47
431 #define S390_F13_REGNUM 48
432 #define S390_F14_REGNUM 49
433 #define S390_F15_REGNUM 50
434 /* Total. */
435 #define S390_NUM_REGS 51
436
437 /* CC optimization */
438
439 enum cc_op {
440 CC_OP_CONST0 = 0, /* CC is 0 */
441 CC_OP_CONST1, /* CC is 1 */
442 CC_OP_CONST2, /* CC is 2 */
443 CC_OP_CONST3, /* CC is 3 */
444
445 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
446 CC_OP_STATIC, /* CC value is env->cc_op */
447
448 CC_OP_NZ, /* env->cc_dst != 0 */
449 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
450 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
451 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
452 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
453 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
454 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
455
456 CC_OP_ADD_64, /* overflow on add (64bit) */
457 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
458 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
459 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
460 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
461 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
462 CC_OP_ABS_64, /* sign eval on abs (64bit) */
463 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
464
465 CC_OP_ADD_32, /* overflow on add (32bit) */
466 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
467 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
468 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
469 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
470 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
471 CC_OP_ABS_32, /* sign eval on abs (64bit) */
472 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
473
474 CC_OP_COMP_32, /* complement */
475 CC_OP_COMP_64, /* complement */
476
477 CC_OP_TM_32, /* test under mask (32bit) */
478 CC_OP_TM_64, /* test under mask (64bit) */
479
480 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
481 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
482 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
483
484 CC_OP_ICM, /* insert characters under mask */
485 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
486 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
487 CC_OP_FLOGR, /* find leftmost one */
488 CC_OP_MAX
489 };
490
491 static const char *cc_names[] = {
492 [CC_OP_CONST0] = "CC_OP_CONST0",
493 [CC_OP_CONST1] = "CC_OP_CONST1",
494 [CC_OP_CONST2] = "CC_OP_CONST2",
495 [CC_OP_CONST3] = "CC_OP_CONST3",
496 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
497 [CC_OP_STATIC] = "CC_OP_STATIC",
498 [CC_OP_NZ] = "CC_OP_NZ",
499 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
500 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
501 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
502 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
503 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
504 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
505 [CC_OP_ADD_64] = "CC_OP_ADD_64",
506 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
507 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
508 [CC_OP_SUB_64] = "CC_OP_SUB_64",
509 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
510 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
511 [CC_OP_ABS_64] = "CC_OP_ABS_64",
512 [CC_OP_NABS_64] = "CC_OP_NABS_64",
513 [CC_OP_ADD_32] = "CC_OP_ADD_32",
514 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
515 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
516 [CC_OP_SUB_32] = "CC_OP_SUB_32",
517 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
518 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
519 [CC_OP_ABS_32] = "CC_OP_ABS_32",
520 [CC_OP_NABS_32] = "CC_OP_NABS_32",
521 [CC_OP_COMP_32] = "CC_OP_COMP_32",
522 [CC_OP_COMP_64] = "CC_OP_COMP_64",
523 [CC_OP_TM_32] = "CC_OP_TM_32",
524 [CC_OP_TM_64] = "CC_OP_TM_64",
525 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
526 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
527 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
528 [CC_OP_ICM] = "CC_OP_ICM",
529 [CC_OP_SLA_32] = "CC_OP_SLA_32",
530 [CC_OP_SLA_64] = "CC_OP_SLA_64",
531 [CC_OP_FLOGR] = "CC_OP_FLOGR",
532 };
533
534 static inline const char *cc_name(int cc_op)
535 {
536 return cc_names[cc_op];
537 }
538
539 typedef struct LowCore
540 {
541 /* prefix area: defined by architecture */
542 uint32_t ccw1[2]; /* 0x000 */
543 uint32_t ccw2[4]; /* 0x008 */
544 uint8_t pad1[0x80-0x18]; /* 0x018 */
545 uint32_t ext_params; /* 0x080 */
546 uint16_t cpu_addr; /* 0x084 */
547 uint16_t ext_int_code; /* 0x086 */
548 uint16_t svc_ilen; /* 0x088 */
549 uint16_t svc_code; /* 0x08a */
550 uint16_t pgm_ilen; /* 0x08c */
551 uint16_t pgm_code; /* 0x08e */
552 uint32_t data_exc_code; /* 0x090 */
553 uint16_t mon_class_num; /* 0x094 */
554 uint16_t per_perc_atmid; /* 0x096 */
555 uint64_t per_address; /* 0x098 */
556 uint8_t exc_access_id; /* 0x0a0 */
557 uint8_t per_access_id; /* 0x0a1 */
558 uint8_t op_access_id; /* 0x0a2 */
559 uint8_t ar_access_id; /* 0x0a3 */
560 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
561 uint64_t trans_exc_code; /* 0x0a8 */
562 uint64_t monitor_code; /* 0x0b0 */
563 uint16_t subchannel_id; /* 0x0b8 */
564 uint16_t subchannel_nr; /* 0x0ba */
565 uint32_t io_int_parm; /* 0x0bc */
566 uint32_t io_int_word; /* 0x0c0 */
567 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
568 uint32_t stfl_fac_list; /* 0x0c8 */
569 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
570 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
571 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
572 uint32_t external_damage_code; /* 0x0f4 */
573 uint64_t failing_storage_address; /* 0x0f8 */
574 uint8_t pad6[0x120-0x100]; /* 0x100 */
575 PSW restart_old_psw; /* 0x120 */
576 PSW external_old_psw; /* 0x130 */
577 PSW svc_old_psw; /* 0x140 */
578 PSW program_old_psw; /* 0x150 */
579 PSW mcck_old_psw; /* 0x160 */
580 PSW io_old_psw; /* 0x170 */
581 uint8_t pad7[0x1a0-0x180]; /* 0x180 */
582 PSW restart_psw; /* 0x1a0 */
583 PSW external_new_psw; /* 0x1b0 */
584 PSW svc_new_psw; /* 0x1c0 */
585 PSW program_new_psw; /* 0x1d0 */
586 PSW mcck_new_psw; /* 0x1e0 */
587 PSW io_new_psw; /* 0x1f0 */
588 PSW return_psw; /* 0x200 */
589 uint8_t irb[64]; /* 0x210 */
590 uint64_t sync_enter_timer; /* 0x250 */
591 uint64_t async_enter_timer; /* 0x258 */
592 uint64_t exit_timer; /* 0x260 */
593 uint64_t last_update_timer; /* 0x268 */
594 uint64_t user_timer; /* 0x270 */
595 uint64_t system_timer; /* 0x278 */
596 uint64_t last_update_clock; /* 0x280 */
597 uint64_t steal_clock; /* 0x288 */
598 PSW return_mcck_psw; /* 0x290 */
599 uint8_t pad8[0xc00-0x2a0]; /* 0x2a0 */
600 /* System info area */
601 uint64_t save_area[16]; /* 0xc00 */
602 uint8_t pad9[0xd40-0xc80]; /* 0xc80 */
603 uint64_t kernel_stack; /* 0xd40 */
604 uint64_t thread_info; /* 0xd48 */
605 uint64_t async_stack; /* 0xd50 */
606 uint64_t kernel_asce; /* 0xd58 */
607 uint64_t user_asce; /* 0xd60 */
608 uint64_t panic_stack; /* 0xd68 */
609 uint64_t user_exec_asce; /* 0xd70 */
610 uint8_t pad10[0xdc0-0xd78]; /* 0xd78 */
611
612 /* SMP info area: defined by DJB */
613 uint64_t clock_comparator; /* 0xdc0 */
614 uint64_t ext_call_fast; /* 0xdc8 */
615 uint64_t percpu_offset; /* 0xdd0 */
616 uint64_t current_task; /* 0xdd8 */
617 uint32_t softirq_pending; /* 0xde0 */
618 uint32_t pad_0x0de4; /* 0xde4 */
619 uint64_t int_clock; /* 0xde8 */
620 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
621
622 /* 0xe00 is used as indicator for dump tools */
623 /* whether the kernel died with panic() or not */
624 uint32_t panic_magic; /* 0xe00 */
625
626 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
627
628 /* 64 bit extparam used for pfault, diag 250 etc */
629 uint64_t ext_params2; /* 0x11B8 */
630
631 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
632
633 /* System info area */
634
635 uint64_t floating_pt_save_area[16]; /* 0x1200 */
636 uint64_t gpregs_save_area[16]; /* 0x1280 */
637 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
638 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
639 uint32_t prefixreg_save_area; /* 0x1318 */
640 uint32_t fpt_creg_save_area; /* 0x131c */
641 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
642 uint32_t tod_progreg_save_area; /* 0x1324 */
643 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
644 uint32_t clock_comp_save_area[2]; /* 0x1330 */
645 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
646 uint32_t access_regs_save_area[16]; /* 0x1340 */
647 uint64_t cregs_save_area[16]; /* 0x1380 */
648
649 /* align to the top of the prefix area */
650
651 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
652 } QEMU_PACKED LowCore;
653
654 /* STSI */
655 #define STSI_LEVEL_MASK 0x00000000f0000000ULL
656 #define STSI_LEVEL_CURRENT 0x0000000000000000ULL
657 #define STSI_LEVEL_1 0x0000000010000000ULL
658 #define STSI_LEVEL_2 0x0000000020000000ULL
659 #define STSI_LEVEL_3 0x0000000030000000ULL
660 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
661 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL
662 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
663 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL
664
665 /* Basic Machine Configuration */
666 struct sysib_111 {
667 uint32_t res1[8];
668 uint8_t manuf[16];
669 uint8_t type[4];
670 uint8_t res2[12];
671 uint8_t model[16];
672 uint8_t sequence[16];
673 uint8_t plant[4];
674 uint8_t res3[156];
675 };
676
677 /* Basic Machine CPU */
678 struct sysib_121 {
679 uint32_t res1[80];
680 uint8_t sequence[16];
681 uint8_t plant[4];
682 uint8_t res2[2];
683 uint16_t cpu_addr;
684 uint8_t res3[152];
685 };
686
687 /* Basic Machine CPUs */
688 struct sysib_122 {
689 uint8_t res1[32];
690 uint32_t capability;
691 uint16_t total_cpus;
692 uint16_t active_cpus;
693 uint16_t standby_cpus;
694 uint16_t reserved_cpus;
695 uint16_t adjustments[2026];
696 };
697
698 /* LPAR CPU */
699 struct sysib_221 {
700 uint32_t res1[80];
701 uint8_t sequence[16];
702 uint8_t plant[4];
703 uint16_t cpu_id;
704 uint16_t cpu_addr;
705 uint8_t res3[152];
706 };
707
708 /* LPAR CPUs */
709 struct sysib_222 {
710 uint32_t res1[32];
711 uint16_t lpar_num;
712 uint8_t res2;
713 uint8_t lcpuc;
714 uint16_t total_cpus;
715 uint16_t conf_cpus;
716 uint16_t standby_cpus;
717 uint16_t reserved_cpus;
718 uint8_t name[8];
719 uint32_t caf;
720 uint8_t res3[16];
721 uint16_t dedicated_cpus;
722 uint16_t shared_cpus;
723 uint8_t res4[180];
724 };
725
726 /* VM CPUs */
727 struct sysib_322 {
728 uint8_t res1[31];
729 uint8_t count;
730 struct {
731 uint8_t res2[4];
732 uint16_t total_cpus;
733 uint16_t conf_cpus;
734 uint16_t standby_cpus;
735 uint16_t reserved_cpus;
736 uint8_t name[8];
737 uint32_t caf;
738 uint8_t cpi[16];
739 uint8_t res3[24];
740 } vm[8];
741 uint8_t res4[3552];
742 };
743
744 /* MMU defines */
745 #define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
746 #define _ASCE_SUBSPACE 0x200 /* subspace group control */
747 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
748 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
749 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
750 #define _ASCE_REAL_SPACE 0x20 /* real space control */
751 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
752 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */
753 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */
754 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */
755 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
756 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */
757
758 #define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
759 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
760 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
761 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
762 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
763 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
764 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */
765
766 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
767 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
768 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
769
770 #define _PAGE_RO 0x200 /* HW read-only bit */
771 #define _PAGE_INVALID 0x400 /* HW invalid bit */
772
773 #define SK_C (0x1 << 1)
774 #define SK_R (0x1 << 2)
775 #define SK_F (0x1 << 3)
776 #define SK_ACC_MASK (0xf << 4)
777
778 #define SIGP_SENSE 0x01
779 #define SIGP_EXTERNAL_CALL 0x02
780 #define SIGP_EMERGENCY 0x03
781 #define SIGP_START 0x04
782 #define SIGP_STOP 0x05
783 #define SIGP_RESTART 0x06
784 #define SIGP_STOP_STORE_STATUS 0x09
785 #define SIGP_INITIAL_CPU_RESET 0x0b
786 #define SIGP_CPU_RESET 0x0c
787 #define SIGP_SET_PREFIX 0x0d
788 #define SIGP_STORE_STATUS_ADDR 0x0e
789 #define SIGP_SET_ARCH 0x12
790
791 /* cpu status bits */
792 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
793 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL
794 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
795 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
796 #define SIGP_STAT_STOPPED 0x00000040UL
797 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
798 #define SIGP_STAT_CHECK_STOP 0x00000010UL
799 #define SIGP_STAT_INOPERATIVE 0x00000004UL
800 #define SIGP_STAT_INVALID_ORDER 0x00000002UL
801 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
802
803 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
804 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
805 target_ulong *raddr, int *flags);
806 int sclp_service_call(uint32_t sccb, uint64_t code);
807 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
808 uint64_t vr);
809
810 #define TARGET_HAS_ICE 1
811
812 /* The value of the TOD clock for 1.1.1970. */
813 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
814
815 /* Converts ns to s390's clock format */
816 static inline uint64_t time2tod(uint64_t ns) {
817 return (ns << 9) / 125;
818 }
819
820 static inline void cpu_inject_ext(CPUS390XState *env, uint32_t code, uint32_t param,
821 uint64_t param64)
822 {
823 if (env->ext_index == MAX_EXT_QUEUE - 1) {
824 /* ugh - can't queue anymore. Let's drop. */
825 return;
826 }
827
828 env->ext_index++;
829 assert(env->ext_index < MAX_EXT_QUEUE);
830
831 env->ext_queue[env->ext_index].code = code;
832 env->ext_queue[env->ext_index].param = param;
833 env->ext_queue[env->ext_index].param64 = param64;
834
835 env->pending_int |= INTERRUPT_EXT;
836 cpu_interrupt(env, CPU_INTERRUPT_HARD);
837 }
838
839 static inline bool cpu_has_work(CPUState *cpu)
840 {
841 CPUS390XState *env = &S390_CPU(cpu)->env;
842
843 return (env->interrupt_request & CPU_INTERRUPT_HARD) &&
844 (env->psw.mask & PSW_MASK_EXT);
845 }
846
847 static inline void cpu_pc_from_tb(CPUS390XState *env, TranslationBlock* tb)
848 {
849 env->psw.addr = tb->pc;
850 }
851
852 /* fpu_helper.c */
853 uint32_t set_cc_nz_f32(float32 v);
854 uint32_t set_cc_nz_f64(float64 v);
855 uint32_t set_cc_nz_f128(float128 v);
856
857 /* misc_helper.c */
858 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
859 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
860 uintptr_t retaddr);
861
862 #endif
Qemu copy for testing