target-s390x/misc_helper.c

   1 /*
   2  *  S/390 misc helper routines
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *  Copyright (c) 2009 Alexander Graf
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "cpu.h"
  22 #include "memory.h"
  23 #include "cputlb.h"
  24 #include "host-utils.h"
  25 #include "helper.h"
  26 #include <string.h>
  27 #include "kvm.h"
  28 #include "qemu-timer.h"
  29 #ifdef CONFIG_KVM
  30 #include <linux/kvm.h>
  31 #endif
  32
  33 #if !defined(CONFIG_USER_ONLY)
  34 /* temporarily disabled due to wrapper use */
  35 #if 0
  36 #include "softmmu_exec.h"
  37 #endif
  38 #include "sysemu.h"
  39 #endif
  40
  41 /* #define DEBUG_HELPER */
  42 #ifdef DEBUG_HELPER
  43 #define HELPER_LOG(x...) qemu_log(x)
  44 #else
  45 #define HELPER_LOG(x...)
  46 #endif
  47
  48 /* raise an exception */
  49 void HELPER(exception)(CPUS390XState *env, uint32_t excp)
  50 {
  51     HELPER_LOG("%s: exception %d\n", __func__, excp);
  52     env->exception_index = excp;
  53     cpu_loop_exit(env);
  54 }
  55
  56 #ifndef CONFIG_USER_ONLY
  57 void program_interrupt(CPUS390XState *env, uint32_t code, int ilc)
  58 {
  59     qemu_log("program interrupt at %#" PRIx64 "\n", env->psw.addr);
  60
  61     if (kvm_enabled()) {
  62 #ifdef CONFIG_KVM
  63         kvm_s390_interrupt(env, KVM_S390_PROGRAM_INT, code);
  64 #endif
  65     } else {
  66         env->int_pgm_code = code;
  67         env->int_pgm_ilc = ilc;
  68         env->exception_index = EXCP_PGM;
  69         cpu_loop_exit(env);
  70     }
  71 }
  72
  73 /*
  74  * ret < 0 indicates program check, ret = 0, 1, 2, 3 -> cc
  75  */
  76 int sclp_service_call(CPUS390XState *env, uint32_t sccb, uint64_t code)
  77 {
  78     int r = 0;
  79     int shift = 0;
  80
  81 #ifdef DEBUG_HELPER
  82     printf("sclp(0x%x, 0x%" PRIx64 ")\n", sccb, code);
  83 #endif
  84
  85     /* basic checks */
  86     if (!memory_region_is_ram(phys_page_find(sccb >> TARGET_PAGE_BITS)->mr)) {
  87         return -PGM_ADDRESSING;
  88     }
  89     if (sccb & ~0x7ffffff8ul) {
  90         return -PGM_SPECIFICATION;
  91     }
  92
  93     switch (code) {
  94     case SCLP_CMDW_READ_SCP_INFO:
  95     case SCLP_CMDW_READ_SCP_INFO_FORCED:
  96         while ((ram_size >> (20 + shift)) > 65535) {
  97             shift++;
  98         }
  99         stw_phys(sccb + SCP_MEM_CODE, ram_size >> (20 + shift));
 100         stb_phys(sccb + SCP_INCREMENT, 1 << shift);
 101         stw_phys(sccb + SCP_RESPONSE_CODE, 0x10);
 102
 103         s390_sclp_extint(sccb & ~3);
 104         break;
 105     default:
 106 #ifdef DEBUG_HELPER
 107         printf("KVM: invalid sclp call 0x%x / 0x%" PRIx64 "x\n", sccb, code);
 108 #endif
 109         r = 3;
 110         break;
 111     }
 112
 113     return r;
 114 }
 115
 116 /* SCLP service call */
 117 uint32_t HELPER(servc)(CPUS390XState *env, uint32_t r1, uint64_t r2)
 118 {
 119     int r;
 120
 121     r = sclp_service_call(env, r1, r2);
 122     if (r < 0) {
 123         program_interrupt(env, -r, 4);
 124         return 0;
 125     }
 126     return r;
 127 }
 128
 129 /* DIAG */
 130 uint64_t HELPER(diag)(CPUS390XState *env, uint32_t num, uint64_t mem,
 131                       uint64_t code)
 132 {
 133     uint64_t r;
 134
 135     switch (num) {
 136     case 0x500:
 137         /* KVM hypercall */
 138         r = s390_virtio_hypercall(env, mem, code);
 139         break;
 140     case 0x44:
 141         /* yield */
 142         r = 0;
 143         break;
 144     case 0x308:
 145         /* ipl */
 146         r = 0;
 147         break;
 148     default:
 149         r = -1;
 150         break;
 151     }
 152
 153     if (r) {
 154         program_interrupt(env, PGM_OPERATION, ILC_LATER_INC);
 155     }
 156
 157     return r;
 158 }
 159
 160 /* Store CPU ID */
 161 void HELPER(stidp)(CPUS390XState *env, uint64_t a1)
 162 {
 163     cpu_stq_data(env, a1, env->cpu_num);
 164 }
 165
 166 /* Set Prefix */
 167 void HELPER(spx)(CPUS390XState *env, uint64_t a1)
 168 {
 169     uint32_t prefix;
 170
 171     prefix = cpu_ldl_data(env, a1);
 172     env->psa = prefix & 0xfffff000;
 173     qemu_log("prefix: %#x\n", prefix);
 174     tlb_flush_page(env, 0);
 175     tlb_flush_page(env, TARGET_PAGE_SIZE);
 176 }
 177
 178 /* Set Clock */
 179 uint32_t HELPER(sck)(uint64_t a1)
 180 {
 181     /* XXX not implemented - is it necessary? */
 182
 183     return 0;
 184 }
 185
 186 static inline uint64_t clock_value(CPUS390XState *env)
 187 {
 188     uint64_t time;
 189
 190     time = env->tod_offset +
 191         time2tod(qemu_get_clock_ns(vm_clock) - env->tod_basetime);
 192
 193     return time;
 194 }
 195
 196 /* Store Clock */
 197 uint32_t HELPER(stck)(CPUS390XState *env, uint64_t a1)
 198 {
 199     cpu_stq_data(env, a1, clock_value(env));
 200
 201     return 0;
 202 }
 203
 204 /* Store Clock Extended */
 205 uint32_t HELPER(stcke)(CPUS390XState *env, uint64_t a1)
 206 {
 207     cpu_stb_data(env, a1, 0);
 208     /* basically the same value as stck */
 209     cpu_stq_data(env, a1 + 1, clock_value(env) | env->cpu_num);
 210     /* more fine grained than stck */
 211     cpu_stq_data(env, a1 + 9, 0);
 212     /* XXX programmable fields */
 213     cpu_stw_data(env, a1 + 17, 0);
 214
 215     return 0;
 216 }
 217
 218 /* Set Clock Comparator */
 219 void HELPER(sckc)(CPUS390XState *env, uint64_t a1)
 220 {
 221     uint64_t time = cpu_ldq_data(env, a1);
 222
 223     if (time == -1ULL) {
 224         return;
 225     }
 226
 227     /* difference between now and then */
 228     time -= clock_value(env);
 229     /* nanoseconds */
 230     time = (time * 125) >> 9;
 231
 232     qemu_mod_timer(env->tod_timer, qemu_get_clock_ns(vm_clock) + time);
 233 }
 234
 235 /* Store Clock Comparator */
 236 void HELPER(stckc)(CPUS390XState *env, uint64_t a1)
 237 {
 238     /* XXX implement */
 239     cpu_stq_data(env, a1, 0);
 240 }
 241
 242 /* Set CPU Timer */
 243 void HELPER(spt)(CPUS390XState *env, uint64_t a1)
 244 {
 245     uint64_t time = cpu_ldq_data(env, a1);
 246
 247     if (time == -1ULL) {
 248         return;
 249     }
 250
 251     /* nanoseconds */
 252     time = (time * 125) >> 9;
 253
 254     qemu_mod_timer(env->cpu_timer, qemu_get_clock_ns(vm_clock) + time);
 255 }
 256
 257 /* Store CPU Timer */
 258 void HELPER(stpt)(CPUS390XState *env, uint64_t a1)
 259 {
 260     /* XXX implement */
 261     cpu_stq_data(env, a1, 0);
 262 }
 263
 264 /* Store System Information */
 265 uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, uint32_t r0,
 266                       uint32_t r1)
 267 {
 268     int cc = 0;
 269     int sel1, sel2;
 270
 271     if ((r0 & STSI_LEVEL_MASK) <= STSI_LEVEL_3 &&
 272         ((r0 & STSI_R0_RESERVED_MASK) || (r1 & STSI_R1_RESERVED_MASK))) {
 273         /* valid function code, invalid reserved bits */
 274         program_interrupt(env, PGM_SPECIFICATION, 2);
 275     }
 276
 277     sel1 = r0 & STSI_R0_SEL1_MASK;
 278     sel2 = r1 & STSI_R1_SEL2_MASK;
 279
 280     /* XXX: spec exception if sysib is not 4k-aligned */
 281
 282     switch (r0 & STSI_LEVEL_MASK) {
 283     case STSI_LEVEL_1:
 284         if ((sel1 == 1) && (sel2 == 1)) {
 285             /* Basic Machine Configuration */
 286             struct sysib_111 sysib;
 287
 288             memset(&sysib, 0, sizeof(sysib));
 289             ebcdic_put(sysib.manuf, "QEMU            ", 16);
 290             /* same as machine type number in STORE CPU ID */
 291             ebcdic_put(sysib.type, "QEMU", 4);
 292             /* same as model number in STORE CPU ID */
 293             ebcdic_put(sysib.model, "QEMU            ", 16);
 294             ebcdic_put(sysib.sequence, "QEMU            ", 16);
 295             ebcdic_put(sysib.plant, "QEMU", 4);
 296             cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
 297         } else if ((sel1 == 2) && (sel2 == 1)) {
 298             /* Basic Machine CPU */
 299             struct sysib_121 sysib;
 300
 301             memset(&sysib, 0, sizeof(sysib));
 302             /* XXX make different for different CPUs? */
 303             ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
 304             ebcdic_put(sysib.plant, "QEMU", 4);
 305             stw_p(&sysib.cpu_addr, env->cpu_num);
 306             cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
 307         } else if ((sel1 == 2) && (sel2 == 2)) {
 308             /* Basic Machine CPUs */
 309             struct sysib_122 sysib;
 310
 311             memset(&sysib, 0, sizeof(sysib));
 312             stl_p(&sysib.capability, 0x443afc29);
 313             /* XXX change when SMP comes */
 314             stw_p(&sysib.total_cpus, 1);
 315             stw_p(&sysib.active_cpus, 1);
 316             stw_p(&sysib.standby_cpus, 0);
 317             stw_p(&sysib.reserved_cpus, 0);
 318             cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
 319         } else {
 320             cc = 3;
 321         }
 322         break;
 323     case STSI_LEVEL_2:
 324         {
 325             if ((sel1 == 2) && (sel2 == 1)) {
 326                 /* LPAR CPU */
 327                 struct sysib_221 sysib;
 328
 329                 memset(&sysib, 0, sizeof(sysib));
 330                 /* XXX make different for different CPUs? */
 331                 ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
 332                 ebcdic_put(sysib.plant, "QEMU", 4);
 333                 stw_p(&sysib.cpu_addr, env->cpu_num);
 334                 stw_p(&sysib.cpu_id, 0);
 335                 cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
 336             } else if ((sel1 == 2) && (sel2 == 2)) {
 337                 /* LPAR CPUs */
 338                 struct sysib_222 sysib;
 339
 340                 memset(&sysib, 0, sizeof(sysib));
 341                 stw_p(&sysib.lpar_num, 0);
 342                 sysib.lcpuc = 0;
 343                 /* XXX change when SMP comes */
 344                 stw_p(&sysib.total_cpus, 1);
 345                 stw_p(&sysib.conf_cpus, 1);
 346                 stw_p(&sysib.standby_cpus, 0);
 347                 stw_p(&sysib.reserved_cpus, 0);
 348                 ebcdic_put(sysib.name, "QEMU    ", 8);
 349                 stl_p(&sysib.caf, 1000);
 350                 stw_p(&sysib.dedicated_cpus, 0);
 351                 stw_p(&sysib.shared_cpus, 0);
 352                 cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
 353             } else {
 354                 cc = 3;
 355             }
 356             break;
 357         }
 358     case STSI_LEVEL_3:
 359         {
 360             if ((sel1 == 2) && (sel2 == 2)) {
 361                 /* VM CPUs */
 362                 struct sysib_322 sysib;
 363
 364                 memset(&sysib, 0, sizeof(sysib));
 365                 sysib.count = 1;
 366                 /* XXX change when SMP comes */
 367                 stw_p(&sysib.vm[0].total_cpus, 1);
 368                 stw_p(&sysib.vm[0].conf_cpus, 1);
 369                 stw_p(&sysib.vm[0].standby_cpus, 0);
 370                 stw_p(&sysib.vm[0].reserved_cpus, 0);
 371                 ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
 372                 stl_p(&sysib.vm[0].caf, 1000);
 373                 ebcdic_put(sysib.vm[0].cpi, "KVM/Linux       ", 16);
 374                 cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
 375             } else {
 376                 cc = 3;
 377             }
 378             break;
 379         }
 380     case STSI_LEVEL_CURRENT:
 381         env->regs[0] = STSI_LEVEL_3;
 382         break;
 383     default:
 384         cc = 3;
 385         break;
 386     }
 387
 388     return cc;
 389 }
 390
 391 uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
 392                       uint64_t cpu_addr)
 393 {
 394     int cc = 0;
 395
 396     HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n",
 397                __func__, order_code, r1, cpu_addr);
 398
 399     /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
 400        as parameter (input). Status (output) is always R1. */
 401
 402     switch (order_code) {
 403     case SIGP_SET_ARCH:
 404         /* switch arch */
 405         break;
 406     case SIGP_SENSE:
 407         /* enumerate CPU status */
 408         if (cpu_addr) {
 409             /* XXX implement when SMP comes */
 410             return 3;
 411         }
 412         env->regs[r1] &= 0xffffffff00000000ULL;
 413         cc = 1;
 414         break;
 415 #if !defined(CONFIG_USER_ONLY)
 416     case SIGP_RESTART:
 417         qemu_system_reset_request();
 418         cpu_loop_exit(env);
 419         break;
 420     case SIGP_STOP:
 421         qemu_system_shutdown_request();
 422         cpu_loop_exit(env);
 423         break;
 424 #endif
 425     default:
 426         /* unknown sigp */
 427         fprintf(stderr, "XXX unknown sigp: 0x%" PRIx64 "\n", order_code);
 428         cc = 3;
 429     }
 430
 431     return cc;
 432 }
 433 #endif