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target-s390: Convert STCK
[qemu.git] / target-s390x / translate.c
1 /*
2 * S/390 translation
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* #define DEBUG_INLINE_BRANCHES */
22 #define S390X_DEBUG_DISAS
23 /* #define S390X_DEBUG_DISAS_VERBOSE */
24
25 #ifdef S390X_DEBUG_DISAS_VERBOSE
26 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
27 #else
28 # define LOG_DISAS(...) do { } while (0)
29 #endif
30
31 #include "cpu.h"
32 #include "disas/disas.h"
33 #include "tcg-op.h"
34 #include "qemu/log.h"
35 #include "qemu/host-utils.h"
36
37 /* global register indexes */
38 static TCGv_ptr cpu_env;
39
40 #include "exec/gen-icount.h"
41 #include "helper.h"
42 #define GEN_HELPER 1
43 #include "helper.h"
44
45
46 /* Information that (most) every instruction needs to manipulate. */
47 typedef struct DisasContext DisasContext;
48 typedef struct DisasInsn DisasInsn;
49 typedef struct DisasFields DisasFields;
50
51 struct DisasContext {
52 struct TranslationBlock *tb;
53 const DisasInsn *insn;
54 DisasFields *fields;
55 uint64_t pc, next_pc;
56 enum cc_op cc_op;
57 bool singlestep_enabled;
58 int is_jmp;
59 };
60
61 /* Information carried about a condition to be evaluated. */
62 typedef struct {
63 TCGCond cond:8;
64 bool is_64;
65 bool g1;
66 bool g2;
67 union {
68 struct { TCGv_i64 a, b; } s64;
69 struct { TCGv_i32 a, b; } s32;
70 } u;
71 } DisasCompare;
72
73 #define DISAS_EXCP 4
74
75 static void gen_op_calc_cc(DisasContext *s);
76
77 #ifdef DEBUG_INLINE_BRANCHES
78 static uint64_t inline_branch_hit[CC_OP_MAX];
79 static uint64_t inline_branch_miss[CC_OP_MAX];
80 #endif
81
82 static inline void debug_insn(uint64_t insn)
83 {
84 LOG_DISAS("insn: 0x%" PRIx64 "\n", insn);
85 }
86
87 static inline uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
88 {
89 if (!(s->tb->flags & FLAG_MASK_64)) {
90 if (s->tb->flags & FLAG_MASK_32) {
91 return pc | 0x80000000;
92 }
93 }
94 return pc;
95 }
96
97 void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
98 int flags)
99 {
100 int i;
101
102 if (env->cc_op > 3) {
103 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
104 env->psw.mask, env->psw.addr, cc_name(env->cc_op));
105 } else {
106 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
107 env->psw.mask, env->psw.addr, env->cc_op);
108 }
109
110 for (i = 0; i < 16; i++) {
111 cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
112 if ((i % 4) == 3) {
113 cpu_fprintf(f, "\n");
114 } else {
115 cpu_fprintf(f, " ");
116 }
117 }
118
119 for (i = 0; i < 16; i++) {
120 cpu_fprintf(f, "F%02d=%016" PRIx64, i, env->fregs[i].ll);
121 if ((i % 4) == 3) {
122 cpu_fprintf(f, "\n");
123 } else {
124 cpu_fprintf(f, " ");
125 }
126 }
127
128 #ifndef CONFIG_USER_ONLY
129 for (i = 0; i < 16; i++) {
130 cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
131 if ((i % 4) == 3) {
132 cpu_fprintf(f, "\n");
133 } else {
134 cpu_fprintf(f, " ");
135 }
136 }
137 #endif
138
139 #ifdef DEBUG_INLINE_BRANCHES
140 for (i = 0; i < CC_OP_MAX; i++) {
141 cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
142 inline_branch_miss[i], inline_branch_hit[i]);
143 }
144 #endif
145
146 cpu_fprintf(f, "\n");
147 }
148
149 static TCGv_i64 psw_addr;
150 static TCGv_i64 psw_mask;
151
152 static TCGv_i32 cc_op;
153 static TCGv_i64 cc_src;
154 static TCGv_i64 cc_dst;
155 static TCGv_i64 cc_vr;
156
157 static char cpu_reg_names[32][4];
158 static TCGv_i64 regs[16];
159 static TCGv_i64 fregs[16];
160
161 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
162
163 void s390x_translate_init(void)
164 {
165 int i;
166
167 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
168 psw_addr = tcg_global_mem_new_i64(TCG_AREG0,
169 offsetof(CPUS390XState, psw.addr),
170 "psw_addr");
171 psw_mask = tcg_global_mem_new_i64(TCG_AREG0,
172 offsetof(CPUS390XState, psw.mask),
173 "psw_mask");
174
175 cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUS390XState, cc_op),
176 "cc_op");
177 cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_src),
178 "cc_src");
179 cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_dst),
180 "cc_dst");
181 cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_vr),
182 "cc_vr");
183
184 for (i = 0; i < 16; i++) {
185 snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i);
186 regs[i] = tcg_global_mem_new(TCG_AREG0,
187 offsetof(CPUS390XState, regs[i]),
188 cpu_reg_names[i]);
189 }
190
191 for (i = 0; i < 16; i++) {
192 snprintf(cpu_reg_names[i + 16], sizeof(cpu_reg_names[0]), "f%d", i);
193 fregs[i] = tcg_global_mem_new(TCG_AREG0,
194 offsetof(CPUS390XState, fregs[i].d),
195 cpu_reg_names[i + 16]);
196 }
197
198 /* register helpers */
199 #define GEN_HELPER 2
200 #include "helper.h"
201 }
202
203 static inline TCGv_i64 load_reg(int reg)
204 {
205 TCGv_i64 r = tcg_temp_new_i64();
206 tcg_gen_mov_i64(r, regs[reg]);
207 return r;
208 }
209
210 static inline TCGv_i64 load_freg(int reg)
211 {
212 TCGv_i64 r = tcg_temp_new_i64();
213 tcg_gen_mov_i64(r, fregs[reg]);
214 return r;
215 }
216
217 static inline TCGv_i32 load_freg32(int reg)
218 {
219 TCGv_i32 r = tcg_temp_new_i32();
220 #if HOST_LONG_BITS == 32
221 tcg_gen_mov_i32(r, TCGV_HIGH(fregs[reg]));
222 #else
223 tcg_gen_shri_i64(MAKE_TCGV_I64(GET_TCGV_I32(r)), fregs[reg], 32);
224 #endif
225 return r;
226 }
227
228 static inline TCGv_i64 load_freg32_i64(int reg)
229 {
230 TCGv_i64 r = tcg_temp_new_i64();
231 tcg_gen_shri_i64(r, fregs[reg], 32);
232 return r;
233 }
234
235 static inline TCGv_i32 load_reg32(int reg)
236 {
237 TCGv_i32 r = tcg_temp_new_i32();
238 tcg_gen_trunc_i64_i32(r, regs[reg]);
239 return r;
240 }
241
242 static inline TCGv_i64 load_reg32_i64(int reg)
243 {
244 TCGv_i64 r = tcg_temp_new_i64();
245 tcg_gen_ext32s_i64(r, regs[reg]);
246 return r;
247 }
248
249 static inline void store_reg(int reg, TCGv_i64 v)
250 {
251 tcg_gen_mov_i64(regs[reg], v);
252 }
253
254 static inline void store_freg(int reg, TCGv_i64 v)
255 {
256 tcg_gen_mov_i64(fregs[reg], v);
257 }
258
259 static inline void store_reg32(int reg, TCGv_i32 v)
260 {
261 /* 32 bit register writes keep the upper half */
262 #if HOST_LONG_BITS == 32
263 tcg_gen_mov_i32(TCGV_LOW(regs[reg]), v);
264 #else
265 tcg_gen_deposit_i64(regs[reg], regs[reg],
266 MAKE_TCGV_I64(GET_TCGV_I32(v)), 0, 32);
267 #endif
268 }
269
270 static inline void store_reg32_i64(int reg, TCGv_i64 v)
271 {
272 /* 32 bit register writes keep the upper half */
273 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
274 }
275
276 static inline void store_reg32h_i64(int reg, TCGv_i64 v)
277 {
278 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 32, 32);
279 }
280
281 static inline void store_freg32(int reg, TCGv_i32 v)
282 {
283 /* 32 bit register writes keep the lower half */
284 #if HOST_LONG_BITS == 32
285 tcg_gen_mov_i32(TCGV_HIGH(fregs[reg]), v);
286 #else
287 tcg_gen_deposit_i64(fregs[reg], fregs[reg],
288 MAKE_TCGV_I64(GET_TCGV_I32(v)), 32, 32);
289 #endif
290 }
291
292 static inline void store_freg32_i64(int reg, TCGv_i64 v)
293 {
294 tcg_gen_deposit_i64(fregs[reg], fregs[reg], v, 32, 32);
295 }
296
297 static inline void return_low128(TCGv_i64 dest)
298 {
299 tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl));
300 }
301
302 static inline void update_psw_addr(DisasContext *s)
303 {
304 /* psw.addr */
305 tcg_gen_movi_i64(psw_addr, s->pc);
306 }
307
308 static inline void potential_page_fault(DisasContext *s)
309 {
310 #ifndef CONFIG_USER_ONLY
311 update_psw_addr(s);
312 gen_op_calc_cc(s);
313 #endif
314 }
315
316 static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
317 {
318 return (uint64_t)cpu_lduw_code(env, pc);
319 }
320
321 static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
322 {
323 return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
324 }
325
326 static inline uint64_t ld_code6(CPUS390XState *env, uint64_t pc)
327 {
328 return (ld_code2(env, pc) << 32) | ld_code4(env, pc + 2);
329 }
330
331 static inline int get_mem_index(DisasContext *s)
332 {
333 switch (s->tb->flags & FLAG_MASK_ASC) {
334 case PSW_ASC_PRIMARY >> 32:
335 return 0;
336 case PSW_ASC_SECONDARY >> 32:
337 return 1;
338 case PSW_ASC_HOME >> 32:
339 return 2;
340 default:
341 tcg_abort();
342 break;
343 }
344 }
345
346 static void gen_exception(int excp)
347 {
348 TCGv_i32 tmp = tcg_const_i32(excp);
349 gen_helper_exception(cpu_env, tmp);
350 tcg_temp_free_i32(tmp);
351 }
352
353 static void gen_program_exception(DisasContext *s, int code)
354 {
355 TCGv_i32 tmp;
356
357 /* Remember what pgm exeption this was. */
358 tmp = tcg_const_i32(code);
359 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
360 tcg_temp_free_i32(tmp);
361
362 tmp = tcg_const_i32(s->next_pc - s->pc);
363 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen));
364 tcg_temp_free_i32(tmp);
365
366 /* Advance past instruction. */
367 s->pc = s->next_pc;
368 update_psw_addr(s);
369
370 /* Save off cc. */
371 gen_op_calc_cc(s);
372
373 /* Trigger exception. */
374 gen_exception(EXCP_PGM);
375
376 /* End TB here. */
377 s->is_jmp = DISAS_EXCP;
378 }
379
380 static inline void gen_illegal_opcode(DisasContext *s)
381 {
382 gen_program_exception(s, PGM_SPECIFICATION);
383 }
384
385 static inline void check_privileged(DisasContext *s)
386 {
387 if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
388 gen_program_exception(s, PGM_PRIVILEGED);
389 }
390 }
391
392 static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
393 {
394 TCGv_i64 tmp;
395
396 /* 31-bitify the immediate part; register contents are dealt with below */
397 if (!(s->tb->flags & FLAG_MASK_64)) {
398 d2 &= 0x7fffffffUL;
399 }
400
401 if (x2) {
402 if (d2) {
403 tmp = tcg_const_i64(d2);
404 tcg_gen_add_i64(tmp, tmp, regs[x2]);
405 } else {
406 tmp = load_reg(x2);
407 }
408 if (b2) {
409 tcg_gen_add_i64(tmp, tmp, regs[b2]);
410 }
411 } else if (b2) {
412 if (d2) {
413 tmp = tcg_const_i64(d2);
414 tcg_gen_add_i64(tmp, tmp, regs[b2]);
415 } else {
416 tmp = load_reg(b2);
417 }
418 } else {
419 tmp = tcg_const_i64(d2);
420 }
421
422 /* 31-bit mode mask if there are values loaded from registers */
423 if (!(s->tb->flags & FLAG_MASK_64) && (x2 || b2)) {
424 tcg_gen_andi_i64(tmp, tmp, 0x7fffffffUL);
425 }
426
427 return tmp;
428 }
429
430 static inline void gen_op_movi_cc(DisasContext *s, uint32_t val)
431 {
432 s->cc_op = CC_OP_CONST0 + val;
433 }
434
435 static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
436 {
437 tcg_gen_discard_i64(cc_src);
438 tcg_gen_mov_i64(cc_dst, dst);
439 tcg_gen_discard_i64(cc_vr);
440 s->cc_op = op;
441 }
442
443 static void gen_op_update1_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 dst)
444 {
445 tcg_gen_discard_i64(cc_src);
446 tcg_gen_extu_i32_i64(cc_dst, dst);
447 tcg_gen_discard_i64(cc_vr);
448 s->cc_op = op;
449 }
450
451 static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
452 TCGv_i64 dst)
453 {
454 tcg_gen_mov_i64(cc_src, src);
455 tcg_gen_mov_i64(cc_dst, dst);
456 tcg_gen_discard_i64(cc_vr);
457 s->cc_op = op;
458 }
459
460 static void gen_op_update2_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src,
461 TCGv_i32 dst)
462 {
463 tcg_gen_extu_i32_i64(cc_src, src);
464 tcg_gen_extu_i32_i64(cc_dst, dst);
465 tcg_gen_discard_i64(cc_vr);
466 s->cc_op = op;
467 }
468
469 static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
470 TCGv_i64 dst, TCGv_i64 vr)
471 {
472 tcg_gen_mov_i64(cc_src, src);
473 tcg_gen_mov_i64(cc_dst, dst);
474 tcg_gen_mov_i64(cc_vr, vr);
475 s->cc_op = op;
476 }
477
478 static inline void set_cc_nz_u32(DisasContext *s, TCGv_i32 val)
479 {
480 gen_op_update1_cc_i32(s, CC_OP_NZ, val);
481 }
482
483 static inline void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
484 {
485 gen_op_update1_cc_i64(s, CC_OP_NZ, val);
486 }
487
488 static inline void gen_set_cc_nz_f32(DisasContext *s, TCGv_i64 val)
489 {
490 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, val);
491 }
492
493 static inline void gen_set_cc_nz_f64(DisasContext *s, TCGv_i64 val)
494 {
495 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, val);
496 }
497
498 static inline void gen_set_cc_nz_f128(DisasContext *s, TCGv_i64 vh, TCGv_i64 vl)
499 {
500 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, vh, vl);
501 }
502
503 static inline void cmp_32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
504 enum cc_op cond)
505 {
506 gen_op_update2_cc_i32(s, cond, v1, v2);
507 }
508
509 static inline void cmp_64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
510 enum cc_op cond)
511 {
512 gen_op_update2_cc_i64(s, cond, v1, v2);
513 }
514
515 static inline void cmp_s32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
516 {
517 cmp_32(s, v1, v2, CC_OP_LTGT_32);
518 }
519
520 static inline void cmp_u32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
521 {
522 cmp_32(s, v1, v2, CC_OP_LTUGTU_32);
523 }
524
525 static inline void cmp_s32c(DisasContext *s, TCGv_i32 v1, int32_t v2)
526 {
527 /* XXX optimize for the constant? put it in s? */
528 TCGv_i32 tmp = tcg_const_i32(v2);
529 cmp_32(s, v1, tmp, CC_OP_LTGT_32);
530 tcg_temp_free_i32(tmp);
531 }
532
533 static inline void cmp_u32c(DisasContext *s, TCGv_i32 v1, uint32_t v2)
534 {
535 TCGv_i32 tmp = tcg_const_i32(v2);
536 cmp_32(s, v1, tmp, CC_OP_LTUGTU_32);
537 tcg_temp_free_i32(tmp);
538 }
539
540 static inline void cmp_s64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
541 {
542 cmp_64(s, v1, v2, CC_OP_LTGT_64);
543 }
544
545 static inline void cmp_u64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
546 {
547 cmp_64(s, v1, v2, CC_OP_LTUGTU_64);
548 }
549
550 static inline void cmp_s64c(DisasContext *s, TCGv_i64 v1, int64_t v2)
551 {
552 TCGv_i64 tmp = tcg_const_i64(v2);
553 cmp_s64(s, v1, tmp);
554 tcg_temp_free_i64(tmp);
555 }
556
557 static inline void cmp_u64c(DisasContext *s, TCGv_i64 v1, uint64_t v2)
558 {
559 TCGv_i64 tmp = tcg_const_i64(v2);
560 cmp_u64(s, v1, tmp);
561 tcg_temp_free_i64(tmp);
562 }
563
564 static inline void set_cc_s32(DisasContext *s, TCGv_i32 val)
565 {
566 gen_op_update1_cc_i32(s, CC_OP_LTGT0_32, val);
567 }
568
569 static inline void set_cc_s64(DisasContext *s, TCGv_i64 val)
570 {
571 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, val);
572 }
573
574 /* CC value is in env->cc_op */
575 static inline void set_cc_static(DisasContext *s)
576 {
577 tcg_gen_discard_i64(cc_src);
578 tcg_gen_discard_i64(cc_dst);
579 tcg_gen_discard_i64(cc_vr);
580 s->cc_op = CC_OP_STATIC;
581 }
582
583 static inline void gen_op_set_cc_op(DisasContext *s)
584 {
585 if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
586 tcg_gen_movi_i32(cc_op, s->cc_op);
587 }
588 }
589
590 static inline void gen_update_cc_op(DisasContext *s)
591 {
592 gen_op_set_cc_op(s);
593 }
594
595 /* calculates cc into cc_op */
596 static void gen_op_calc_cc(DisasContext *s)
597 {
598 TCGv_i32 local_cc_op = tcg_const_i32(s->cc_op);
599 TCGv_i64 dummy = tcg_const_i64(0);
600
601 switch (s->cc_op) {
602 case CC_OP_CONST0:
603 case CC_OP_CONST1:
604 case CC_OP_CONST2:
605 case CC_OP_CONST3:
606 /* s->cc_op is the cc value */
607 tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
608 break;
609 case CC_OP_STATIC:
610 /* env->cc_op already is the cc value */
611 break;
612 case CC_OP_NZ:
613 case CC_OP_ABS_64:
614 case CC_OP_NABS_64:
615 case CC_OP_ABS_32:
616 case CC_OP_NABS_32:
617 case CC_OP_LTGT0_32:
618 case CC_OP_LTGT0_64:
619 case CC_OP_COMP_32:
620 case CC_OP_COMP_64:
621 case CC_OP_NZ_F32:
622 case CC_OP_NZ_F64:
623 case CC_OP_FLOGR:
624 /* 1 argument */
625 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dummy);
626 break;
627 case CC_OP_ICM:
628 case CC_OP_LTGT_32:
629 case CC_OP_LTGT_64:
630 case CC_OP_LTUGTU_32:
631 case CC_OP_LTUGTU_64:
632 case CC_OP_TM_32:
633 case CC_OP_TM_64:
634 case CC_OP_SLA_32:
635 case CC_OP_SLA_64:
636 case CC_OP_NZ_F128:
637 /* 2 arguments */
638 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
639 break;
640 case CC_OP_ADD_64:
641 case CC_OP_ADDU_64:
642 case CC_OP_ADDC_64:
643 case CC_OP_SUB_64:
644 case CC_OP_SUBU_64:
645 case CC_OP_SUBB_64:
646 case CC_OP_ADD_32:
647 case CC_OP_ADDU_32:
648 case CC_OP_ADDC_32:
649 case CC_OP_SUB_32:
650 case CC_OP_SUBU_32:
651 case CC_OP_SUBB_32:
652 /* 3 arguments */
653 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc_vr);
654 break;
655 case CC_OP_DYNAMIC:
656 /* unknown operation - assume 3 arguments and cc_op in env */
657 gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr);
658 break;
659 default:
660 tcg_abort();
661 }
662
663 tcg_temp_free_i32(local_cc_op);
664 tcg_temp_free_i64(dummy);
665
666 /* We now have cc in cc_op as constant */
667 set_cc_static(s);
668 }
669
670 static inline void decode_rr(DisasContext *s, uint64_t insn, int *r1, int *r2)
671 {
672 debug_insn(insn);
673
674 *r1 = (insn >> 4) & 0xf;
675 *r2 = insn & 0xf;
676 }
677
678 static inline TCGv_i64 decode_rx(DisasContext *s, uint64_t insn, int *r1,
679 int *x2, int *b2, int *d2)
680 {
681 debug_insn(insn);
682
683 *r1 = (insn >> 20) & 0xf;
684 *x2 = (insn >> 16) & 0xf;
685 *b2 = (insn >> 12) & 0xf;
686 *d2 = insn & 0xfff;
687
688 return get_address(s, *x2, *b2, *d2);
689 }
690
691 static inline void decode_rs(DisasContext *s, uint64_t insn, int *r1, int *r3,
692 int *b2, int *d2)
693 {
694 debug_insn(insn);
695
696 *r1 = (insn >> 20) & 0xf;
697 /* aka m3 */
698 *r3 = (insn >> 16) & 0xf;
699 *b2 = (insn >> 12) & 0xf;
700 *d2 = insn & 0xfff;
701 }
702
703 static inline TCGv_i64 decode_si(DisasContext *s, uint64_t insn, int *i2,
704 int *b1, int *d1)
705 {
706 debug_insn(insn);
707
708 *i2 = (insn >> 16) & 0xff;
709 *b1 = (insn >> 12) & 0xf;
710 *d1 = insn & 0xfff;
711
712 return get_address(s, 0, *b1, *d1);
713 }
714
715 static int use_goto_tb(DisasContext *s, uint64_t dest)
716 {
717 /* NOTE: we handle the case where the TB spans two pages here */
718 return (((dest & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK)
719 || (dest & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK))
720 && !s->singlestep_enabled
721 && !(s->tb->cflags & CF_LAST_IO));
722 }
723
724 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong pc)
725 {
726 gen_update_cc_op(s);
727
728 if (use_goto_tb(s, pc)) {
729 tcg_gen_goto_tb(tb_num);
730 tcg_gen_movi_i64(psw_addr, pc);
731 tcg_gen_exit_tb((tcg_target_long)s->tb + tb_num);
732 } else {
733 /* jump to another page: currently not optimized */
734 tcg_gen_movi_i64(psw_addr, pc);
735 tcg_gen_exit_tb(0);
736 }
737 }
738
739 static inline void account_noninline_branch(DisasContext *s, int cc_op)
740 {
741 #ifdef DEBUG_INLINE_BRANCHES
742 inline_branch_miss[cc_op]++;
743 #endif
744 }
745
746 static inline void account_inline_branch(DisasContext *s, int cc_op)
747 {
748 #ifdef DEBUG_INLINE_BRANCHES
749 inline_branch_hit[cc_op]++;
750 #endif
751 }
752
753 /* Table of mask values to comparison codes, given a comparison as input.
754 For a true comparison CC=3 will never be set, but we treat this
755 conservatively for possible use when CC=3 indicates overflow. */
756 static const TCGCond ltgt_cond[16] = {
757 TCG_COND_NEVER, TCG_COND_NEVER, /* | | | x */
758 TCG_COND_GT, TCG_COND_NEVER, /* | | GT | x */
759 TCG_COND_LT, TCG_COND_NEVER, /* | LT | | x */
760 TCG_COND_NE, TCG_COND_NEVER, /* | LT | GT | x */
761 TCG_COND_EQ, TCG_COND_NEVER, /* EQ | | | x */
762 TCG_COND_GE, TCG_COND_NEVER, /* EQ | | GT | x */
763 TCG_COND_LE, TCG_COND_NEVER, /* EQ | LT | | x */
764 TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | LT | GT | x */
765 };
766
767 /* Table of mask values to comparison codes, given a logic op as input.
768 For such, only CC=0 and CC=1 should be possible. */
769 static const TCGCond nz_cond[16] = {
770 /* | | x | x */
771 TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER,
772 /* | NE | x | x */
773 TCG_COND_NE, TCG_COND_NE, TCG_COND_NE, TCG_COND_NE,
774 /* EQ | | x | x */
775 TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ,
776 /* EQ | NE | x | x */
777 TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS,
778 };
779
780 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
781 details required to generate a TCG comparison. */
782 static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
783 {
784 TCGCond cond;
785 enum cc_op old_cc_op = s->cc_op;
786
787 if (mask == 15 || mask == 0) {
788 c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER);
789 c->u.s32.a = cc_op;
790 c->u.s32.b = cc_op;
791 c->g1 = c->g2 = true;
792 c->is_64 = false;
793 return;
794 }
795
796 /* Find the TCG condition for the mask + cc op. */
797 switch (old_cc_op) {
798 case CC_OP_LTGT0_32:
799 case CC_OP_LTGT0_64:
800 case CC_OP_LTGT_32:
801 case CC_OP_LTGT_64:
802 cond = ltgt_cond[mask];
803 if (cond == TCG_COND_NEVER) {
804 goto do_dynamic;
805 }
806 account_inline_branch(s, old_cc_op);
807 break;
808
809 case CC_OP_LTUGTU_32:
810 case CC_OP_LTUGTU_64:
811 cond = tcg_unsigned_cond(ltgt_cond[mask]);
812 if (cond == TCG_COND_NEVER) {
813 goto do_dynamic;
814 }
815 account_inline_branch(s, old_cc_op);
816 break;
817
818 case CC_OP_NZ:
819 cond = nz_cond[mask];
820 if (cond == TCG_COND_NEVER) {
821 goto do_dynamic;
822 }
823 account_inline_branch(s, old_cc_op);
824 break;
825
826 case CC_OP_TM_32:
827 case CC_OP_TM_64:
828 switch (mask) {
829 case 8:
830 cond = TCG_COND_EQ;
831 break;
832 case 4 | 2 | 1:
833 cond = TCG_COND_NE;
834 break;
835 default:
836 goto do_dynamic;
837 }
838 account_inline_branch(s, old_cc_op);
839 break;
840
841 case CC_OP_ICM:
842 switch (mask) {
843 case 8:
844 cond = TCG_COND_EQ;
845 break;
846 case 4 | 2 | 1:
847 case 4 | 2:
848 cond = TCG_COND_NE;
849 break;
850 default:
851 goto do_dynamic;
852 }
853 account_inline_branch(s, old_cc_op);
854 break;
855
856 case CC_OP_FLOGR:
857 switch (mask & 0xa) {
858 case 8: /* src == 0 -> no one bit found */
859 cond = TCG_COND_EQ;
860 break;
861 case 2: /* src != 0 -> one bit found */
862 cond = TCG_COND_NE;
863 break;
864 default:
865 goto do_dynamic;
866 }
867 account_inline_branch(s, old_cc_op);
868 break;
869
870 default:
871 do_dynamic:
872 /* Calculate cc value. */
873 gen_op_calc_cc(s);
874 /* FALLTHRU */
875
876 case CC_OP_STATIC:
877 /* Jump based on CC. We'll load up the real cond below;
878 the assignment here merely avoids a compiler warning. */
879 account_noninline_branch(s, old_cc_op);
880 old_cc_op = CC_OP_STATIC;
881 cond = TCG_COND_NEVER;
882 break;
883 }
884
885 /* Load up the arguments of the comparison. */
886 c->is_64 = true;
887 c->g1 = c->g2 = false;
888 switch (old_cc_op) {
889 case CC_OP_LTGT0_32:
890 c->is_64 = false;
891 c->u.s32.a = tcg_temp_new_i32();
892 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_dst);
893 c->u.s32.b = tcg_const_i32(0);
894 break;
895 case CC_OP_LTGT_32:
896 case CC_OP_LTUGTU_32:
897 c->is_64 = false;
898 c->u.s32.a = tcg_temp_new_i32();
899 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_src);
900 c->u.s32.b = tcg_temp_new_i32();
901 tcg_gen_trunc_i64_i32(c->u.s32.b, cc_dst);
902 break;
903
904 case CC_OP_LTGT0_64:
905 case CC_OP_NZ:
906 case CC_OP_FLOGR:
907 c->u.s64.a = cc_dst;
908 c->u.s64.b = tcg_const_i64(0);
909 c->g1 = true;
910 break;
911 case CC_OP_LTGT_64:
912 case CC_OP_LTUGTU_64:
913 c->u.s64.a = cc_src;
914 c->u.s64.b = cc_dst;
915 c->g1 = c->g2 = true;
916 break;
917
918 case CC_OP_TM_32:
919 case CC_OP_TM_64:
920 case CC_OP_ICM:
921 c->u.s64.a = tcg_temp_new_i64();
922 c->u.s64.b = tcg_const_i64(0);
923 tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
924 break;
925
926 case CC_OP_STATIC:
927 c->is_64 = false;
928 c->u.s32.a = cc_op;
929 c->g1 = true;
930 switch (mask) {
931 case 0x8 | 0x4 | 0x2: /* cc != 3 */
932 cond = TCG_COND_NE;
933 c->u.s32.b = tcg_const_i32(3);
934 break;
935 case 0x8 | 0x4 | 0x1: /* cc != 2 */
936 cond = TCG_COND_NE;
937 c->u.s32.b = tcg_const_i32(2);
938 break;
939 case 0x8 | 0x2 | 0x1: /* cc != 1 */
940 cond = TCG_COND_NE;
941 c->u.s32.b = tcg_const_i32(1);
942 break;
943 case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
944 cond = TCG_COND_EQ;
945 c->g1 = false;
946 c->u.s32.a = tcg_temp_new_i32();
947 c->u.s32.b = tcg_const_i32(0);
948 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
949 break;
950 case 0x8 | 0x4: /* cc < 2 */
951 cond = TCG_COND_LTU;
952 c->u.s32.b = tcg_const_i32(2);
953 break;
954 case 0x8: /* cc == 0 */
955 cond = TCG_COND_EQ;
956 c->u.s32.b = tcg_const_i32(0);
957 break;
958 case 0x4 | 0x2 | 0x1: /* cc != 0 */
959 cond = TCG_COND_NE;
960 c->u.s32.b = tcg_const_i32(0);
961 break;
962 case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
963 cond = TCG_COND_NE;
964 c->g1 = false;
965 c->u.s32.a = tcg_temp_new_i32();
966 c->u.s32.b = tcg_const_i32(0);
967 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
968 break;
969 case 0x4: /* cc == 1 */
970 cond = TCG_COND_EQ;
971 c->u.s32.b = tcg_const_i32(1);
972 break;
973 case 0x2 | 0x1: /* cc > 1 */
974 cond = TCG_COND_GTU;
975 c->u.s32.b = tcg_const_i32(1);
976 break;
977 case 0x2: /* cc == 2 */
978 cond = TCG_COND_EQ;
979 c->u.s32.b = tcg_const_i32(2);
980 break;
981 case 0x1: /* cc == 3 */
982 cond = TCG_COND_EQ;
983 c->u.s32.b = tcg_const_i32(3);
984 break;
985 default:
986 /* CC is masked by something else: (8 >> cc) & mask. */
987 cond = TCG_COND_NE;
988 c->g1 = false;
989 c->u.s32.a = tcg_const_i32(8);
990 c->u.s32.b = tcg_const_i32(0);
991 tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op);
992 tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
993 break;
994 }
995 break;
996
997 default:
998 abort();
999 }
1000 c->cond = cond;
1001 }
1002
1003 static void free_compare(DisasCompare *c)
1004 {
1005 if (!c->g1) {
1006 if (c->is_64) {
1007 tcg_temp_free_i64(c->u.s64.a);
1008 } else {
1009 tcg_temp_free_i32(c->u.s32.a);
1010 }
1011 }
1012 if (!c->g2) {
1013 if (c->is_64) {
1014 tcg_temp_free_i64(c->u.s64.b);
1015 } else {
1016 tcg_temp_free_i32(c->u.s32.b);
1017 }
1018 }
1019 }
1020
1021 static void disas_b2(CPUS390XState *env, DisasContext *s, int op,
1022 uint32_t insn)
1023 {
1024 #ifndef CONFIG_USER_ONLY
1025 TCGv_i64 tmp, tmp2, tmp3;
1026 TCGv_i32 tmp32_1, tmp32_2;
1027 int r1, r2;
1028 int r3, d2, b2;
1029
1030 r1 = (insn >> 4) & 0xf;
1031 r2 = insn & 0xf;
1032
1033 LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op, r1, r2);
1034
1035 switch (op) {
1036 case 0x06: /* SCKC D2(B2) [S] */
1037 /* Set Clock Comparator */
1038 check_privileged(s);
1039 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1040 tmp = get_address(s, 0, b2, d2);
1041 potential_page_fault(s);
1042 gen_helper_sckc(cpu_env, tmp);
1043 tcg_temp_free_i64(tmp);
1044 break;
1045 case 0x07: /* STCKC D2(B2) [S] */
1046 /* Store Clock Comparator */
1047 check_privileged(s);
1048 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1049 tmp = get_address(s, 0, b2, d2);
1050 potential_page_fault(s);
1051 gen_helper_stckc(cpu_env, tmp);
1052 tcg_temp_free_i64(tmp);
1053 break;
1054 case 0x08: /* SPT D2(B2) [S] */
1055 /* Set CPU Timer */
1056 check_privileged(s);
1057 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1058 tmp = get_address(s, 0, b2, d2);
1059 potential_page_fault(s);
1060 gen_helper_spt(cpu_env, tmp);
1061 tcg_temp_free_i64(tmp);
1062 break;
1063 case 0x09: /* STPT D2(B2) [S] */
1064 /* Store CPU Timer */
1065 check_privileged(s);
1066 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1067 tmp = get_address(s, 0, b2, d2);
1068 potential_page_fault(s);
1069 gen_helper_stpt(cpu_env, tmp);
1070 tcg_temp_free_i64(tmp);
1071 break;
1072 case 0x0a: /* SPKA D2(B2) [S] */
1073 /* Set PSW Key from Address */
1074 check_privileged(s);
1075 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1076 tmp = get_address(s, 0, b2, d2);
1077 tmp2 = tcg_temp_new_i64();
1078 tcg_gen_andi_i64(tmp2, psw_mask, ~PSW_MASK_KEY);
1079 tcg_gen_shli_i64(tmp, tmp, PSW_SHIFT_KEY - 4);
1080 tcg_gen_or_i64(psw_mask, tmp2, tmp);
1081 tcg_temp_free_i64(tmp2);
1082 tcg_temp_free_i64(tmp);
1083 break;
1084 case 0x0d: /* PTLB [S] */
1085 /* Purge TLB */
1086 check_privileged(s);
1087 gen_helper_ptlb(cpu_env);
1088 break;
1089 case 0x10: /* SPX D2(B2) [S] */
1090 /* Set Prefix Register */
1091 check_privileged(s);
1092 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1093 tmp = get_address(s, 0, b2, d2);
1094 potential_page_fault(s);
1095 gen_helper_spx(cpu_env, tmp);
1096 tcg_temp_free_i64(tmp);
1097 break;
1098 case 0x11: /* STPX D2(B2) [S] */
1099 /* Store Prefix */
1100 check_privileged(s);
1101 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1102 tmp = get_address(s, 0, b2, d2);
1103 tmp2 = tcg_temp_new_i64();
1104 tcg_gen_ld_i64(tmp2, cpu_env, offsetof(CPUS390XState, psa));
1105 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1106 tcg_temp_free_i64(tmp);
1107 tcg_temp_free_i64(tmp2);
1108 break;
1109 case 0x12: /* STAP D2(B2) [S] */
1110 /* Store CPU Address */
1111 check_privileged(s);
1112 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1113 tmp = get_address(s, 0, b2, d2);
1114 tmp2 = tcg_temp_new_i64();
1115 tmp32_1 = tcg_temp_new_i32();
1116 tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, cpu_num));
1117 tcg_gen_extu_i32_i64(tmp2, tmp32_1);
1118 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1119 tcg_temp_free_i64(tmp);
1120 tcg_temp_free_i64(tmp2);
1121 tcg_temp_free_i32(tmp32_1);
1122 break;
1123 case 0x21: /* IPTE R1,R2 [RRE] */
1124 /* Invalidate PTE */
1125 check_privileged(s);
1126 r1 = (insn >> 4) & 0xf;
1127 r2 = insn & 0xf;
1128 tmp = load_reg(r1);
1129 tmp2 = load_reg(r2);
1130 gen_helper_ipte(cpu_env, tmp, tmp2);
1131 tcg_temp_free_i64(tmp);
1132 tcg_temp_free_i64(tmp2);
1133 break;
1134 case 0x29: /* ISKE R1,R2 [RRE] */
1135 /* Insert Storage Key Extended */
1136 check_privileged(s);
1137 r1 = (insn >> 4) & 0xf;
1138 r2 = insn & 0xf;
1139 tmp = load_reg(r2);
1140 tmp2 = tcg_temp_new_i64();
1141 gen_helper_iske(tmp2, cpu_env, tmp);
1142 store_reg(r1, tmp2);
1143 tcg_temp_free_i64(tmp);
1144 tcg_temp_free_i64(tmp2);
1145 break;
1146 case 0x2a: /* RRBE R1,R2 [RRE] */
1147 /* Set Storage Key Extended */
1148 check_privileged(s);
1149 r1 = (insn >> 4) & 0xf;
1150 r2 = insn & 0xf;
1151 tmp32_1 = load_reg32(r1);
1152 tmp = load_reg(r2);
1153 gen_helper_rrbe(cc_op, cpu_env, tmp32_1, tmp);
1154 set_cc_static(s);
1155 tcg_temp_free_i32(tmp32_1);
1156 tcg_temp_free_i64(tmp);
1157 break;
1158 case 0x2b: /* SSKE R1,R2 [RRE] */
1159 /* Set Storage Key Extended */
1160 check_privileged(s);
1161 r1 = (insn >> 4) & 0xf;
1162 r2 = insn & 0xf;
1163 tmp32_1 = load_reg32(r1);
1164 tmp = load_reg(r2);
1165 gen_helper_sske(cpu_env, tmp32_1, tmp);
1166 tcg_temp_free_i32(tmp32_1);
1167 tcg_temp_free_i64(tmp);
1168 break;
1169 case 0x34: /* STCH ? */
1170 /* Store Subchannel */
1171 check_privileged(s);
1172 gen_op_movi_cc(s, 3);
1173 break;
1174 case 0x46: /* STURA R1,R2 [RRE] */
1175 /* Store Using Real Address */
1176 check_privileged(s);
1177 r1 = (insn >> 4) & 0xf;
1178 r2 = insn & 0xf;
1179 tmp32_1 = load_reg32(r1);
1180 tmp = load_reg(r2);
1181 potential_page_fault(s);
1182 gen_helper_stura(cpu_env, tmp, tmp32_1);
1183 tcg_temp_free_i32(tmp32_1);
1184 tcg_temp_free_i64(tmp);
1185 break;
1186 case 0x50: /* CSP R1,R2 [RRE] */
1187 /* Compare And Swap And Purge */
1188 check_privileged(s);
1189 r1 = (insn >> 4) & 0xf;
1190 r2 = insn & 0xf;
1191 tmp32_1 = tcg_const_i32(r1);
1192 tmp32_2 = tcg_const_i32(r2);
1193 gen_helper_csp(cc_op, cpu_env, tmp32_1, tmp32_2);
1194 set_cc_static(s);
1195 tcg_temp_free_i32(tmp32_1);
1196 tcg_temp_free_i32(tmp32_2);
1197 break;
1198 case 0x5f: /* CHSC ? */
1199 /* Channel Subsystem Call */
1200 check_privileged(s);
1201 gen_op_movi_cc(s, 3);
1202 break;
1203 case 0x78: /* STCKE D2(B2) [S] */
1204 /* Store Clock Extended */
1205 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1206 tmp = get_address(s, 0, b2, d2);
1207 potential_page_fault(s);
1208 gen_helper_stcke(cc_op, cpu_env, tmp);
1209 set_cc_static(s);
1210 tcg_temp_free_i64(tmp);
1211 break;
1212 case 0x79: /* SACF D2(B2) [S] */
1213 /* Set Address Space Control Fast */
1214 check_privileged(s);
1215 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1216 tmp = get_address(s, 0, b2, d2);
1217 potential_page_fault(s);
1218 gen_helper_sacf(cpu_env, tmp);
1219 tcg_temp_free_i64(tmp);
1220 /* addressing mode has changed, so end the block */
1221 s->pc = s->next_pc;
1222 update_psw_addr(s);
1223 s->is_jmp = DISAS_JUMP;
1224 break;
1225 case 0x7d: /* STSI D2,(B2) [S] */
1226 check_privileged(s);
1227 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1228 tmp = get_address(s, 0, b2, d2);
1229 tmp32_1 = load_reg32(0);
1230 tmp32_2 = load_reg32(1);
1231 potential_page_fault(s);
1232 gen_helper_stsi(cc_op, cpu_env, tmp, tmp32_1, tmp32_2);
1233 set_cc_static(s);
1234 tcg_temp_free_i64(tmp);
1235 tcg_temp_free_i32(tmp32_1);
1236 tcg_temp_free_i32(tmp32_2);
1237 break;
1238 case 0xb1: /* STFL D2(B2) [S] */
1239 /* Store Facility List (CPU features) at 200 */
1240 check_privileged(s);
1241 tmp2 = tcg_const_i64(0xc0000000);
1242 tmp = tcg_const_i64(200);
1243 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1244 tcg_temp_free_i64(tmp2);
1245 tcg_temp_free_i64(tmp);
1246 break;
1247 case 0xb2: /* LPSWE D2(B2) [S] */
1248 /* Load PSW Extended */
1249 check_privileged(s);
1250 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1251 tmp = get_address(s, 0, b2, d2);
1252 tmp2 = tcg_temp_new_i64();
1253 tmp3 = tcg_temp_new_i64();
1254 tcg_gen_qemu_ld64(tmp2, tmp, get_mem_index(s));
1255 tcg_gen_addi_i64(tmp, tmp, 8);
1256 tcg_gen_qemu_ld64(tmp3, tmp, get_mem_index(s));
1257 gen_helper_load_psw(cpu_env, tmp2, tmp3);
1258 /* we need to keep cc_op intact */
1259 s->is_jmp = DISAS_JUMP;
1260 tcg_temp_free_i64(tmp);
1261 tcg_temp_free_i64(tmp2);
1262 tcg_temp_free_i64(tmp3);
1263 break;
1264 case 0x20: /* SERVC R1,R2 [RRE] */
1265 /* SCLP Service call (PV hypercall) */
1266 check_privileged(s);
1267 potential_page_fault(s);
1268 tmp32_1 = load_reg32(r2);
1269 tmp = load_reg(r1);
1270 gen_helper_servc(cc_op, cpu_env, tmp32_1, tmp);
1271 set_cc_static(s);
1272 tcg_temp_free_i32(tmp32_1);
1273 tcg_temp_free_i64(tmp);
1274 break;
1275 default:
1276 #endif
1277 LOG_DISAS("illegal b2 operation 0x%x\n", op);
1278 gen_illegal_opcode(s);
1279 #ifndef CONFIG_USER_ONLY
1280 break;
1281 }
1282 #endif
1283 }
1284
1285 static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
1286 {
1287 unsigned char opc;
1288 uint64_t insn;
1289 int op;
1290
1291 opc = cpu_ldub_code(env, s->pc);
1292 LOG_DISAS("opc 0x%x\n", opc);
1293
1294 switch (opc) {
1295 case 0xb2:
1296 insn = ld_code4(env, s->pc);
1297 op = (insn >> 16) & 0xff;
1298 disas_b2(env, s, op, insn);
1299 break;
1300 default:
1301 qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%x\n", opc);
1302 gen_illegal_opcode(s);
1303 break;
1304 }
1305 }
1306
1307 /* ====================================================================== */
1308 /* Define the insn format enumeration. */
1309 #define F0(N) FMT_##N,
1310 #define F1(N, X1) F0(N)
1311 #define F2(N, X1, X2) F0(N)
1312 #define F3(N, X1, X2, X3) F0(N)
1313 #define F4(N, X1, X2, X3, X4) F0(N)
1314 #define F5(N, X1, X2, X3, X4, X5) F0(N)
1315
1316 typedef enum {
1317 #include "insn-format.def"
1318 } DisasFormat;
1319
1320 #undef F0
1321 #undef F1
1322 #undef F2
1323 #undef F3
1324 #undef F4
1325 #undef F5
1326
1327 /* Define a structure to hold the decoded fields. We'll store each inside
1328 an array indexed by an enum. In order to conserve memory, we'll arrange
1329 for fields that do not exist at the same time to overlap, thus the "C"
1330 for compact. For checking purposes there is an "O" for original index
1331 as well that will be applied to availability bitmaps. */
1332
1333 enum DisasFieldIndexO {
1334 FLD_O_r1,
1335 FLD_O_r2,
1336 FLD_O_r3,
1337 FLD_O_m1,
1338 FLD_O_m3,
1339 FLD_O_m4,
1340 FLD_O_b1,
1341 FLD_O_b2,
1342 FLD_O_b4,
1343 FLD_O_d1,
1344 FLD_O_d2,
1345 FLD_O_d4,
1346 FLD_O_x2,
1347 FLD_O_l1,
1348 FLD_O_l2,
1349 FLD_O_i1,
1350 FLD_O_i2,
1351 FLD_O_i3,
1352 FLD_O_i4,
1353 FLD_O_i5
1354 };
1355
1356 enum DisasFieldIndexC {
1357 FLD_C_r1 = 0,
1358 FLD_C_m1 = 0,
1359 FLD_C_b1 = 0,
1360 FLD_C_i1 = 0,
1361
1362 FLD_C_r2 = 1,
1363 FLD_C_b2 = 1,
1364 FLD_C_i2 = 1,
1365
1366 FLD_C_r3 = 2,
1367 FLD_C_m3 = 2,
1368 FLD_C_i3 = 2,
1369
1370 FLD_C_m4 = 3,
1371 FLD_C_b4 = 3,
1372 FLD_C_i4 = 3,
1373 FLD_C_l1 = 3,
1374
1375 FLD_C_i5 = 4,
1376 FLD_C_d1 = 4,
1377
1378 FLD_C_d2 = 5,
1379
1380 FLD_C_d4 = 6,
1381 FLD_C_x2 = 6,
1382 FLD_C_l2 = 6,
1383
1384 NUM_C_FIELD = 7
1385 };
1386
1387 struct DisasFields {
1388 unsigned op:8;
1389 unsigned op2:8;
1390 unsigned presentC:16;
1391 unsigned int presentO;
1392 int c[NUM_C_FIELD];
1393 };
1394
1395 /* This is the way fields are to be accessed out of DisasFields. */
1396 #define have_field(S, F) have_field1((S), FLD_O_##F)
1397 #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
1398
1399 static bool have_field1(const DisasFields *f, enum DisasFieldIndexO c)
1400 {
1401 return (f->presentO >> c) & 1;
1402 }
1403
1404 static int get_field1(const DisasFields *f, enum DisasFieldIndexO o,
1405 enum DisasFieldIndexC c)
1406 {
1407 assert(have_field1(f, o));
1408 return f->c[c];
1409 }
1410
1411 /* Describe the layout of each field in each format. */
1412 typedef struct DisasField {
1413 unsigned int beg:8;
1414 unsigned int size:8;
1415 unsigned int type:2;
1416 unsigned int indexC:6;
1417 enum DisasFieldIndexO indexO:8;
1418 } DisasField;
1419
1420 typedef struct DisasFormatInfo {
1421 DisasField op[NUM_C_FIELD];
1422 } DisasFormatInfo;
1423
1424 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
1425 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
1426 #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1427 { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
1428 #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1429 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1430 { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
1431 #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1432 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1433 #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1434 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1435 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1436 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
1437 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
1438
1439 #define F0(N) { { } },
1440 #define F1(N, X1) { { X1 } },
1441 #define F2(N, X1, X2) { { X1, X2 } },
1442 #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
1443 #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
1444 #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
1445
1446 static const DisasFormatInfo format_info[] = {
1447 #include "insn-format.def"
1448 };
1449
1450 #undef F0
1451 #undef F1
1452 #undef F2
1453 #undef F3
1454 #undef F4
1455 #undef F5
1456 #undef R
1457 #undef M
1458 #undef BD
1459 #undef BXD
1460 #undef BDL
1461 #undef BXDL
1462 #undef I
1463 #undef L
1464
1465 /* Generally, we'll extract operands into this structures, operate upon
1466 them, and store them back. See the "in1", "in2", "prep", "wout" sets
1467 of routines below for more details. */
1468 typedef struct {
1469 bool g_out, g_out2, g_in1, g_in2;
1470 TCGv_i64 out, out2, in1, in2;
1471 TCGv_i64 addr1;
1472 } DisasOps;
1473
1474 /* Return values from translate_one, indicating the state of the TB. */
1475 typedef enum {
1476 /* Continue the TB. */
1477 NO_EXIT,
1478 /* We have emitted one or more goto_tb. No fixup required. */
1479 EXIT_GOTO_TB,
1480 /* We are not using a goto_tb (for whatever reason), but have updated
1481 the PC (for whatever reason), so there's no need to do it again on
1482 exiting the TB. */
1483 EXIT_PC_UPDATED,
1484 /* We are exiting the TB, but have neither emitted a goto_tb, nor
1485 updated the PC for the next instruction to be executed. */
1486 EXIT_PC_STALE,
1487 /* We are ending the TB with a noreturn function call, e.g. longjmp.
1488 No following code will be executed. */
1489 EXIT_NORETURN,
1490 } ExitStatus;
1491
1492 typedef enum DisasFacility {
1493 FAC_Z, /* zarch (default) */
1494 FAC_CASS, /* compare and swap and store */
1495 FAC_CASS2, /* compare and swap and store 2*/
1496 FAC_DFP, /* decimal floating point */
1497 FAC_DFPR, /* decimal floating point rounding */
1498 FAC_DO, /* distinct operands */
1499 FAC_EE, /* execute extensions */
1500 FAC_EI, /* extended immediate */
1501 FAC_FPE, /* floating point extension */
1502 FAC_FPSSH, /* floating point support sign handling */
1503 FAC_FPRGR, /* FPR-GR transfer */
1504 FAC_GIE, /* general instructions extension */
1505 FAC_HFP_MA, /* HFP multiply-and-add/subtract */
1506 FAC_HW, /* high-word */
1507 FAC_IEEEE_SIM, /* IEEE exception sumilation */
1508 FAC_LOC, /* load/store on condition */
1509 FAC_LD, /* long displacement */
1510 FAC_PC, /* population count */
1511 FAC_SCF, /* store clock fast */
1512 FAC_SFLE, /* store facility list extended */
1513 } DisasFacility;
1514
1515 struct DisasInsn {
1516 unsigned opc:16;
1517 DisasFormat fmt:6;
1518 DisasFacility fac:6;
1519
1520 const char *name;
1521
1522 void (*help_in1)(DisasContext *, DisasFields *, DisasOps *);
1523 void (*help_in2)(DisasContext *, DisasFields *, DisasOps *);
1524 void (*help_prep)(DisasContext *, DisasFields *, DisasOps *);
1525 void (*help_wout)(DisasContext *, DisasFields *, DisasOps *);
1526 void (*help_cout)(DisasContext *, DisasOps *);
1527 ExitStatus (*help_op)(DisasContext *, DisasOps *);
1528
1529 uint64_t data;
1530 };
1531
1532 /* ====================================================================== */
1533 /* Miscelaneous helpers, used by several operations. */
1534
1535 static void help_l2_shift(DisasContext *s, DisasFields *f,
1536 DisasOps *o, int mask)
1537 {
1538 int b2 = get_field(f, b2);
1539 int d2 = get_field(f, d2);
1540
1541 if (b2 == 0) {
1542 o->in2 = tcg_const_i64(d2 & mask);
1543 } else {
1544 o->in2 = get_address(s, 0, b2, d2);
1545 tcg_gen_andi_i64(o->in2, o->in2, mask);
1546 }
1547 }
1548
1549 static ExitStatus help_goto_direct(DisasContext *s, uint64_t dest)
1550 {
1551 if (dest == s->next_pc) {
1552 return NO_EXIT;
1553 }
1554 if (use_goto_tb(s, dest)) {
1555 gen_update_cc_op(s);
1556 tcg_gen_goto_tb(0);
1557 tcg_gen_movi_i64(psw_addr, dest);
1558 tcg_gen_exit_tb((tcg_target_long)s->tb);
1559 return EXIT_GOTO_TB;
1560 } else {
1561 tcg_gen_movi_i64(psw_addr, dest);
1562 return EXIT_PC_UPDATED;
1563 }
1564 }
1565
1566 static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
1567 bool is_imm, int imm, TCGv_i64 cdest)
1568 {
1569 ExitStatus ret;
1570 uint64_t dest = s->pc + 2 * imm;
1571 int lab;
1572
1573 /* Take care of the special cases first. */
1574 if (c->cond == TCG_COND_NEVER) {
1575 ret = NO_EXIT;
1576 goto egress;
1577 }
1578 if (is_imm) {
1579 if (dest == s->next_pc) {
1580 /* Branch to next. */
1581 ret = NO_EXIT;
1582 goto egress;
1583 }
1584 if (c->cond == TCG_COND_ALWAYS) {
1585 ret = help_goto_direct(s, dest);
1586 goto egress;
1587 }
1588 } else {
1589 if (TCGV_IS_UNUSED_I64(cdest)) {
1590 /* E.g. bcr %r0 -> no branch. */
1591 ret = NO_EXIT;
1592 goto egress;
1593 }
1594 if (c->cond == TCG_COND_ALWAYS) {
1595 tcg_gen_mov_i64(psw_addr, cdest);
1596 ret = EXIT_PC_UPDATED;
1597 goto egress;
1598 }
1599 }
1600
1601 if (use_goto_tb(s, s->next_pc)) {
1602 if (is_imm && use_goto_tb(s, dest)) {
1603 /* Both exits can use goto_tb. */
1604 gen_update_cc_op(s);
1605
1606 lab = gen_new_label();
1607 if (c->is_64) {
1608 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1609 } else {
1610 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1611 }
1612
1613 /* Branch not taken. */
1614 tcg_gen_goto_tb(0);
1615 tcg_gen_movi_i64(psw_addr, s->next_pc);
1616 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
1617
1618 /* Branch taken. */
1619 gen_set_label(lab);
1620 tcg_gen_goto_tb(1);
1621 tcg_gen_movi_i64(psw_addr, dest);
1622 tcg_gen_exit_tb((tcg_target_long)s->tb + 1);
1623
1624 ret = EXIT_GOTO_TB;
1625 } else {
1626 /* Fallthru can use goto_tb, but taken branch cannot. */
1627 /* Store taken branch destination before the brcond. This
1628 avoids having to allocate a new local temp to hold it.
1629 We'll overwrite this in the not taken case anyway. */
1630 if (!is_imm) {
1631 tcg_gen_mov_i64(psw_addr, cdest);
1632 }
1633
1634 lab = gen_new_label();
1635 if (c->is_64) {
1636 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1637 } else {
1638 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1639 }
1640
1641 /* Branch not taken. */
1642 gen_update_cc_op(s);
1643 tcg_gen_goto_tb(0);
1644 tcg_gen_movi_i64(psw_addr, s->next_pc);
1645 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
1646
1647 gen_set_label(lab);
1648 if (is_imm) {
1649 tcg_gen_movi_i64(psw_addr, dest);
1650 }
1651 ret = EXIT_PC_UPDATED;
1652 }
1653 } else {
1654 /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
1655 Most commonly we're single-stepping or some other condition that
1656 disables all use of goto_tb. Just update the PC and exit. */
1657
1658 TCGv_i64 next = tcg_const_i64(s->next_pc);
1659 if (is_imm) {
1660 cdest = tcg_const_i64(dest);
1661 }
1662
1663 if (c->is_64) {
1664 tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b,
1665 cdest, next);
1666 } else {
1667 TCGv_i32 t0 = tcg_temp_new_i32();
1668 TCGv_i64 t1 = tcg_temp_new_i64();
1669 TCGv_i64 z = tcg_const_i64(0);
1670 tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b);
1671 tcg_gen_extu_i32_i64(t1, t0);
1672 tcg_temp_free_i32(t0);
1673 tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next);
1674 tcg_temp_free_i64(t1);
1675 tcg_temp_free_i64(z);
1676 }
1677
1678 if (is_imm) {
1679 tcg_temp_free_i64(cdest);
1680 }
1681 tcg_temp_free_i64(next);
1682
1683 ret = EXIT_PC_UPDATED;
1684 }
1685
1686 egress:
1687 free_compare(c);
1688 return ret;
1689 }
1690
1691 /* ====================================================================== */
1692 /* The operations. These perform the bulk of the work for any insn,
1693 usually after the operands have been loaded and output initialized. */
1694
1695 static ExitStatus op_abs(DisasContext *s, DisasOps *o)
1696 {
1697 gen_helper_abs_i64(o->out, o->in2);
1698 return NO_EXIT;
1699 }
1700
1701 static ExitStatus op_absf32(DisasContext *s, DisasOps *o)
1702 {
1703 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffull);
1704 return NO_EXIT;
1705 }
1706
1707 static ExitStatus op_absf64(DisasContext *s, DisasOps *o)
1708 {
1709 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull);
1710 return NO_EXIT;
1711 }
1712
1713 static ExitStatus op_absf128(DisasContext *s, DisasOps *o)
1714 {
1715 tcg_gen_andi_i64(o->out, o->in1, 0x7fffffffffffffffull);
1716 tcg_gen_mov_i64(o->out2, o->in2);
1717 return NO_EXIT;
1718 }
1719
1720 static ExitStatus op_add(DisasContext *s, DisasOps *o)
1721 {
1722 tcg_gen_add_i64(o->out, o->in1, o->in2);
1723 return NO_EXIT;
1724 }
1725
1726 static ExitStatus op_addc(DisasContext *s, DisasOps *o)
1727 {
1728 TCGv_i64 cc;
1729
1730 tcg_gen_add_i64(o->out, o->in1, o->in2);
1731
1732 /* XXX possible optimization point */
1733 gen_op_calc_cc(s);
1734 cc = tcg_temp_new_i64();
1735 tcg_gen_extu_i32_i64(cc, cc_op);
1736 tcg_gen_shri_i64(cc, cc, 1);
1737
1738 tcg_gen_add_i64(o->out, o->out, cc);
1739 tcg_temp_free_i64(cc);
1740 return NO_EXIT;
1741 }
1742
1743 static ExitStatus op_aeb(DisasContext *s, DisasOps *o)
1744 {
1745 gen_helper_aeb(o->out, cpu_env, o->in1, o->in2);
1746 return NO_EXIT;
1747 }
1748
1749 static ExitStatus op_adb(DisasContext *s, DisasOps *o)
1750 {
1751 gen_helper_adb(o->out, cpu_env, o->in1, o->in2);
1752 return NO_EXIT;
1753 }
1754
1755 static ExitStatus op_axb(DisasContext *s, DisasOps *o)
1756 {
1757 gen_helper_axb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
1758 return_low128(o->out2);
1759 return NO_EXIT;
1760 }
1761
1762 static ExitStatus op_and(DisasContext *s, DisasOps *o)
1763 {
1764 tcg_gen_and_i64(o->out, o->in1, o->in2);
1765 return NO_EXIT;
1766 }
1767
1768 static ExitStatus op_andi(DisasContext *s, DisasOps *o)
1769 {
1770 int shift = s->insn->data & 0xff;
1771 int size = s->insn->data >> 8;
1772 uint64_t mask = ((1ull << size) - 1) << shift;
1773
1774 assert(!o->g_in2);
1775 tcg_gen_shli_i64(o->in2, o->in2, shift);
1776 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
1777 tcg_gen_and_i64(o->out, o->in1, o->in2);
1778
1779 /* Produce the CC from only the bits manipulated. */
1780 tcg_gen_andi_i64(cc_dst, o->out, mask);
1781 set_cc_nz_u64(s, cc_dst);
1782 return NO_EXIT;
1783 }
1784
1785 static ExitStatus op_bas(DisasContext *s, DisasOps *o)
1786 {
1787 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1788 if (!TCGV_IS_UNUSED_I64(o->in2)) {
1789 tcg_gen_mov_i64(psw_addr, o->in2);
1790 return EXIT_PC_UPDATED;
1791 } else {
1792 return NO_EXIT;
1793 }
1794 }
1795
1796 static ExitStatus op_basi(DisasContext *s, DisasOps *o)
1797 {
1798 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1799 return help_goto_direct(s, s->pc + 2 * get_field(s->fields, i2));
1800 }
1801
1802 static ExitStatus op_bc(DisasContext *s, DisasOps *o)
1803 {
1804 int m1 = get_field(s->fields, m1);
1805 bool is_imm = have_field(s->fields, i2);
1806 int imm = is_imm ? get_field(s->fields, i2) : 0;
1807 DisasCompare c;
1808
1809 disas_jcc(s, &c, m1);
1810 return help_branch(s, &c, is_imm, imm, o->in2);
1811 }
1812
1813 static ExitStatus op_bct32(DisasContext *s, DisasOps *o)
1814 {
1815 int r1 = get_field(s->fields, r1);
1816 bool is_imm = have_field(s->fields, i2);
1817 int imm = is_imm ? get_field(s->fields, i2) : 0;
1818 DisasCompare c;
1819 TCGv_i64 t;
1820
1821 c.cond = TCG_COND_NE;
1822 c.is_64 = false;
1823 c.g1 = false;
1824 c.g2 = false;
1825
1826 t = tcg_temp_new_i64();
1827 tcg_gen_subi_i64(t, regs[r1], 1);
1828 store_reg32_i64(r1, t);
1829 c.u.s32.a = tcg_temp_new_i32();
1830 c.u.s32.b = tcg_const_i32(0);
1831 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
1832 tcg_temp_free_i64(t);
1833
1834 return help_branch(s, &c, is_imm, imm, o->in2);
1835 }
1836
1837 static ExitStatus op_bct64(DisasContext *s, DisasOps *o)
1838 {
1839 int r1 = get_field(s->fields, r1);
1840 bool is_imm = have_field(s->fields, i2);
1841 int imm = is_imm ? get_field(s->fields, i2) : 0;
1842 DisasCompare c;
1843
1844 c.cond = TCG_COND_NE;
1845 c.is_64 = true;
1846 c.g1 = true;
1847 c.g2 = false;
1848
1849 tcg_gen_subi_i64(regs[r1], regs[r1], 1);
1850 c.u.s64.a = regs[r1];
1851 c.u.s64.b = tcg_const_i64(0);
1852
1853 return help_branch(s, &c, is_imm, imm, o->in2);
1854 }
1855
1856 static ExitStatus op_ceb(DisasContext *s, DisasOps *o)
1857 {
1858 gen_helper_ceb(cc_op, cpu_env, o->in1, o->in2);
1859 set_cc_static(s);
1860 return NO_EXIT;
1861 }
1862
1863 static ExitStatus op_cdb(DisasContext *s, DisasOps *o)
1864 {
1865 gen_helper_cdb(cc_op, cpu_env, o->in1, o->in2);
1866 set_cc_static(s);
1867 return NO_EXIT;
1868 }
1869
1870 static ExitStatus op_cxb(DisasContext *s, DisasOps *o)
1871 {
1872 gen_helper_cxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2);
1873 set_cc_static(s);
1874 return NO_EXIT;
1875 }
1876
1877 static ExitStatus op_cfeb(DisasContext *s, DisasOps *o)
1878 {
1879 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1880 gen_helper_cfeb(o->out, cpu_env, o->in2, m3);
1881 tcg_temp_free_i32(m3);
1882 gen_set_cc_nz_f32(s, o->in2);
1883 return NO_EXIT;
1884 }
1885
1886 static ExitStatus op_cfdb(DisasContext *s, DisasOps *o)
1887 {
1888 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1889 gen_helper_cfdb(o->out, cpu_env, o->in2, m3);
1890 tcg_temp_free_i32(m3);
1891 gen_set_cc_nz_f64(s, o->in2);
1892 return NO_EXIT;
1893 }
1894
1895 static ExitStatus op_cfxb(DisasContext *s, DisasOps *o)
1896 {
1897 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1898 gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m3);
1899 tcg_temp_free_i32(m3);
1900 gen_set_cc_nz_f128(s, o->in1, o->in2);
1901 return NO_EXIT;
1902 }
1903
1904 static ExitStatus op_cgeb(DisasContext *s, DisasOps *o)
1905 {
1906 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1907 gen_helper_cgeb(o->out, cpu_env, o->in2, m3);
1908 tcg_temp_free_i32(m3);
1909 gen_set_cc_nz_f32(s, o->in2);
1910 return NO_EXIT;
1911 }
1912
1913 static ExitStatus op_cgdb(DisasContext *s, DisasOps *o)
1914 {
1915 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1916 gen_helper_cgdb(o->out, cpu_env, o->in2, m3);
1917 tcg_temp_free_i32(m3);
1918 gen_set_cc_nz_f64(s, o->in2);
1919 return NO_EXIT;
1920 }
1921
1922 static ExitStatus op_cgxb(DisasContext *s, DisasOps *o)
1923 {
1924 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1925 gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m3);
1926 tcg_temp_free_i32(m3);
1927 gen_set_cc_nz_f128(s, o->in1, o->in2);
1928 return NO_EXIT;
1929 }
1930
1931 static ExitStatus op_cegb(DisasContext *s, DisasOps *o)
1932 {
1933 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1934 gen_helper_cegb(o->out, cpu_env, o->in2, m3);
1935 tcg_temp_free_i32(m3);
1936 return NO_EXIT;
1937 }
1938
1939 static ExitStatus op_cdgb(DisasContext *s, DisasOps *o)
1940 {
1941 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1942 gen_helper_cdgb(o->out, cpu_env, o->in2, m3);
1943 tcg_temp_free_i32(m3);
1944 return NO_EXIT;
1945 }
1946
1947 static ExitStatus op_cxgb(DisasContext *s, DisasOps *o)
1948 {
1949 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1950 gen_helper_cxgb(o->out, cpu_env, o->in2, m3);
1951 tcg_temp_free_i32(m3);
1952 return_low128(o->out2);
1953 return NO_EXIT;
1954 }
1955
1956 static ExitStatus op_cksm(DisasContext *s, DisasOps *o)
1957 {
1958 int r2 = get_field(s->fields, r2);
1959 TCGv_i64 len = tcg_temp_new_i64();
1960
1961 potential_page_fault(s);
1962 gen_helper_cksm(len, cpu_env, o->in1, o->in2, regs[r2 + 1]);
1963 set_cc_static(s);
1964 return_low128(o->out);
1965
1966 tcg_gen_add_i64(regs[r2], regs[r2], len);
1967 tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len);
1968 tcg_temp_free_i64(len);
1969
1970 return NO_EXIT;
1971 }
1972
1973 static ExitStatus op_clc(DisasContext *s, DisasOps *o)
1974 {
1975 int l = get_field(s->fields, l1);
1976 TCGv_i32 vl;
1977
1978 switch (l + 1) {
1979 case 1:
1980 tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s));
1981 tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s));
1982 break;
1983 case 2:
1984 tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s));
1985 tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s));
1986 break;
1987 case 4:
1988 tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s));
1989 tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s));
1990 break;
1991 case 8:
1992 tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s));
1993 tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
1994 break;
1995 default:
1996 potential_page_fault(s);
1997 vl = tcg_const_i32(l);
1998 gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
1999 tcg_temp_free_i32(vl);
2000 set_cc_static(s);
2001 return NO_EXIT;
2002 }
2003 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
2004 return NO_EXIT;
2005 }
2006
2007 static ExitStatus op_clcle(DisasContext *s, DisasOps *o)
2008 {
2009 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2010 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2011 potential_page_fault(s);
2012 gen_helper_clcle(cc_op, cpu_env, r1, o->in2, r3);
2013 tcg_temp_free_i32(r1);
2014 tcg_temp_free_i32(r3);
2015 set_cc_static(s);
2016 return NO_EXIT;
2017 }
2018
2019 static ExitStatus op_clm(DisasContext *s, DisasOps *o)
2020 {
2021 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
2022 TCGv_i32 t1 = tcg_temp_new_i32();
2023 tcg_gen_trunc_i64_i32(t1, o->in1);
2024 potential_page_fault(s);
2025 gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2);
2026 set_cc_static(s);
2027 tcg_temp_free_i32(t1);
2028 tcg_temp_free_i32(m3);
2029 return NO_EXIT;
2030 }
2031
2032 static ExitStatus op_clst(DisasContext *s, DisasOps *o)
2033 {
2034 potential_page_fault(s);
2035 gen_helper_clst(o->in1, cpu_env, regs[0], o->in1, o->in2);
2036 set_cc_static(s);
2037 return_low128(o->in2);
2038 return NO_EXIT;
2039 }
2040
2041 static ExitStatus op_cs(DisasContext *s, DisasOps *o)
2042 {
2043 int r3 = get_field(s->fields, r3);
2044 potential_page_fault(s);
2045 gen_helper_cs(o->out, cpu_env, o->in1, o->in2, regs[r3]);
2046 set_cc_static(s);
2047 return NO_EXIT;
2048 }
2049
2050 static ExitStatus op_csg(DisasContext *s, DisasOps *o)
2051 {
2052 int r3 = get_field(s->fields, r3);
2053 potential_page_fault(s);
2054 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, regs[r3]);
2055 set_cc_static(s);
2056 return NO_EXIT;
2057 }
2058
2059 static ExitStatus op_cds(DisasContext *s, DisasOps *o)
2060 {
2061 int r3 = get_field(s->fields, r3);
2062 TCGv_i64 in3 = tcg_temp_new_i64();
2063 tcg_gen_deposit_i64(in3, regs[r3 + 1], regs[r3], 32, 32);
2064 potential_page_fault(s);
2065 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, in3);
2066 tcg_temp_free_i64(in3);
2067 set_cc_static(s);
2068 return NO_EXIT;
2069 }
2070
2071 static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
2072 {
2073 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2074 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2075 potential_page_fault(s);
2076 /* XXX rewrite in tcg */
2077 gen_helper_cdsg(cc_op, cpu_env, r1, o->in2, r3);
2078 set_cc_static(s);
2079 return NO_EXIT;
2080 }
2081
2082 static ExitStatus op_cvd(DisasContext *s, DisasOps *o)
2083 {
2084 TCGv_i64 t1 = tcg_temp_new_i64();
2085 TCGv_i32 t2 = tcg_temp_new_i32();
2086 tcg_gen_trunc_i64_i32(t2, o->in1);
2087 gen_helper_cvd(t1, t2);
2088 tcg_temp_free_i32(t2);
2089 tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
2090 tcg_temp_free_i64(t1);
2091 return NO_EXIT;
2092 }
2093
2094 #ifndef CONFIG_USER_ONLY
2095 static ExitStatus op_diag(DisasContext *s, DisasOps *o)
2096 {
2097 TCGv_i32 tmp;
2098
2099 check_privileged(s);
2100 potential_page_fault(s);
2101
2102 /* We pretend the format is RX_a so that D2 is the field we want. */
2103 tmp = tcg_const_i32(get_field(s->fields, d2) & 0xfff);
2104 gen_helper_diag(regs[2], cpu_env, tmp, regs[2], regs[1]);
2105 tcg_temp_free_i32(tmp);
2106 return NO_EXIT;
2107 }
2108 #endif
2109
2110 static ExitStatus op_divs32(DisasContext *s, DisasOps *o)
2111 {
2112 gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2);
2113 return_low128(o->out);
2114 return NO_EXIT;
2115 }
2116
2117 static ExitStatus op_divu32(DisasContext *s, DisasOps *o)
2118 {
2119 gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2);
2120 return_low128(o->out);
2121 return NO_EXIT;
2122 }
2123
2124 static ExitStatus op_divs64(DisasContext *s, DisasOps *o)
2125 {
2126 gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2);
2127 return_low128(o->out);
2128 return NO_EXIT;
2129 }
2130
2131 static ExitStatus op_divu64(DisasContext *s, DisasOps *o)
2132 {
2133 gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2);
2134 return_low128(o->out);
2135 return NO_EXIT;
2136 }
2137
2138 static ExitStatus op_deb(DisasContext *s, DisasOps *o)
2139 {
2140 gen_helper_deb(o->out, cpu_env, o->in1, o->in2);
2141 return NO_EXIT;
2142 }
2143
2144 static ExitStatus op_ddb(DisasContext *s, DisasOps *o)
2145 {
2146 gen_helper_ddb(o->out, cpu_env, o->in1, o->in2);
2147 return NO_EXIT;
2148 }
2149
2150 static ExitStatus op_dxb(DisasContext *s, DisasOps *o)
2151 {
2152 gen_helper_dxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2153 return_low128(o->out2);
2154 return NO_EXIT;
2155 }
2156
2157 static ExitStatus op_ear(DisasContext *s, DisasOps *o)
2158 {
2159 int r2 = get_field(s->fields, r2);
2160 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, aregs[r2]));
2161 return NO_EXIT;
2162 }
2163
2164 static ExitStatus op_efpc(DisasContext *s, DisasOps *o)
2165 {
2166 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, fpc));
2167 return NO_EXIT;
2168 }
2169
2170 static ExitStatus op_ex(DisasContext *s, DisasOps *o)
2171 {
2172 /* ??? Perhaps a better way to implement EXECUTE is to set a bit in
2173 tb->flags, (ab)use the tb->cs_base field as the address of
2174 the template in memory, and grab 8 bits of tb->flags/cflags for
2175 the contents of the register. We would then recognize all this
2176 in gen_intermediate_code_internal, generating code for exactly
2177 one instruction. This new TB then gets executed normally.
2178
2179 On the other hand, this seems to be mostly used for modifying
2180 MVC inside of memcpy, which needs a helper call anyway. So
2181 perhaps this doesn't bear thinking about any further. */
2182
2183 TCGv_i64 tmp;
2184
2185 update_psw_addr(s);
2186 gen_op_calc_cc(s);
2187
2188 tmp = tcg_const_i64(s->next_pc);
2189 gen_helper_ex(cc_op, cpu_env, cc_op, o->in1, o->in2, tmp);
2190 tcg_temp_free_i64(tmp);
2191
2192 set_cc_static(s);
2193 return NO_EXIT;
2194 }
2195
2196 static ExitStatus op_flogr(DisasContext *s, DisasOps *o)
2197 {
2198 /* We'll use the original input for cc computation, since we get to
2199 compare that against 0, which ought to be better than comparing
2200 the real output against 64. It also lets cc_dst be a convenient
2201 temporary during our computation. */
2202 gen_op_update1_cc_i64(s, CC_OP_FLOGR, o->in2);
2203
2204 /* R1 = IN ? CLZ(IN) : 64. */
2205 gen_helper_clz(o->out, o->in2);
2206
2207 /* R1+1 = IN & ~(found bit). Note that we may attempt to shift this
2208 value by 64, which is undefined. But since the shift is 64 iff the
2209 input is zero, we still get the correct result after and'ing. */
2210 tcg_gen_movi_i64(o->out2, 0x8000000000000000ull);
2211 tcg_gen_shr_i64(o->out2, o->out2, o->out);
2212 tcg_gen_andc_i64(o->out2, cc_dst, o->out2);
2213 return NO_EXIT;
2214 }
2215
2216 static ExitStatus op_icm(DisasContext *s, DisasOps *o)
2217 {
2218 int m3 = get_field(s->fields, m3);
2219 int pos, len, base = s->insn->data;
2220 TCGv_i64 tmp = tcg_temp_new_i64();
2221 uint64_t ccm;
2222
2223 switch (m3) {
2224 case 0xf:
2225 /* Effectively a 32-bit load. */
2226 tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
2227 len = 32;
2228 goto one_insert;
2229
2230 case 0xc:
2231 case 0x6:
2232 case 0x3:
2233 /* Effectively a 16-bit load. */
2234 tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
2235 len = 16;
2236 goto one_insert;
2237
2238 case 0x8:
2239 case 0x4:
2240 case 0x2:
2241 case 0x1:
2242 /* Effectively an 8-bit load. */
2243 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2244 len = 8;
2245 goto one_insert;
2246
2247 one_insert:
2248 pos = base + ctz32(m3) * 8;
2249 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len);
2250 ccm = ((1ull << len) - 1) << pos;
2251 break;
2252
2253 default:
2254 /* This is going to be a sequence of loads and inserts. */
2255 pos = base + 32 - 8;
2256 ccm = 0;
2257 while (m3) {
2258 if (m3 & 0x8) {
2259 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2260 tcg_gen_addi_i64(o->in2, o->in2, 1);
2261 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
2262 ccm |= 0xff << pos;
2263 }
2264 m3 = (m3 << 1) & 0xf;
2265 pos -= 8;
2266 }
2267 break;
2268 }
2269
2270 tcg_gen_movi_i64(tmp, ccm);
2271 gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out);
2272 tcg_temp_free_i64(tmp);
2273 return NO_EXIT;
2274 }
2275
2276 static ExitStatus op_insi(DisasContext *s, DisasOps *o)
2277 {
2278 int shift = s->insn->data & 0xff;
2279 int size = s->insn->data >> 8;
2280 tcg_gen_deposit_i64(o->out, o->in1, o->in2, shift, size);
2281 return NO_EXIT;
2282 }
2283
2284 static ExitStatus op_ipm(DisasContext *s, DisasOps *o)
2285 {
2286 TCGv_i64 t1;
2287
2288 gen_op_calc_cc(s);
2289 tcg_gen_andi_i64(o->out, o->out, ~0xff000000ull);
2290
2291 t1 = tcg_temp_new_i64();
2292 tcg_gen_shli_i64(t1, psw_mask, 20);
2293 tcg_gen_shri_i64(t1, t1, 36);
2294 tcg_gen_or_i64(o->out, o->out, t1);
2295
2296 tcg_gen_extu_i32_i64(t1, cc_op);
2297 tcg_gen_shli_i64(t1, t1, 28);
2298 tcg_gen_or_i64(o->out, o->out, t1);
2299 tcg_temp_free_i64(t1);
2300 return NO_EXIT;
2301 }
2302
2303 static ExitStatus op_ldeb(DisasContext *s, DisasOps *o)
2304 {
2305 gen_helper_ldeb(o->out, cpu_env, o->in2);
2306 return NO_EXIT;
2307 }
2308
2309 static ExitStatus op_ledb(DisasContext *s, DisasOps *o)
2310 {
2311 gen_helper_ledb(o->out, cpu_env, o->in2);
2312 return NO_EXIT;
2313 }
2314
2315 static ExitStatus op_ldxb(DisasContext *s, DisasOps *o)
2316 {
2317 gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2);
2318 return NO_EXIT;
2319 }
2320
2321 static ExitStatus op_lexb(DisasContext *s, DisasOps *o)
2322 {
2323 gen_helper_lexb(o->out, cpu_env, o->in1, o->in2);
2324 return NO_EXIT;
2325 }
2326
2327 static ExitStatus op_lxdb(DisasContext *s, DisasOps *o)
2328 {
2329 gen_helper_lxdb(o->out, cpu_env, o->in2);
2330 return_low128(o->out2);
2331 return NO_EXIT;
2332 }
2333
2334 static ExitStatus op_lxeb(DisasContext *s, DisasOps *o)
2335 {
2336 gen_helper_lxeb(o->out, cpu_env, o->in2);
2337 return_low128(o->out2);
2338 return NO_EXIT;
2339 }
2340
2341 static ExitStatus op_llgt(DisasContext *s, DisasOps *o)
2342 {
2343 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffff);
2344 return NO_EXIT;
2345 }
2346
2347 static ExitStatus op_ld8s(DisasContext *s, DisasOps *o)
2348 {
2349 tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
2350 return NO_EXIT;
2351 }
2352
2353 static ExitStatus op_ld8u(DisasContext *s, DisasOps *o)
2354 {
2355 tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
2356 return NO_EXIT;
2357 }
2358
2359 static ExitStatus op_ld16s(DisasContext *s, DisasOps *o)
2360 {
2361 tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
2362 return NO_EXIT;
2363 }
2364
2365 static ExitStatus op_ld16u(DisasContext *s, DisasOps *o)
2366 {
2367 tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
2368 return NO_EXIT;
2369 }
2370
2371 static ExitStatus op_ld32s(DisasContext *s, DisasOps *o)
2372 {
2373 tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s));
2374 return NO_EXIT;
2375 }
2376
2377 static ExitStatus op_ld32u(DisasContext *s, DisasOps *o)
2378 {
2379 tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
2380 return NO_EXIT;
2381 }
2382
2383 static ExitStatus op_ld64(DisasContext *s, DisasOps *o)
2384 {
2385 tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
2386 return NO_EXIT;
2387 }
2388
2389 #ifndef CONFIG_USER_ONLY
2390 static ExitStatus op_lctl(DisasContext *s, DisasOps *o)
2391 {
2392 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2393 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2394 check_privileged(s);
2395 potential_page_fault(s);
2396 gen_helper_lctl(cpu_env, r1, o->in2, r3);
2397 tcg_temp_free_i32(r1);
2398 tcg_temp_free_i32(r3);
2399 return NO_EXIT;
2400 }
2401
2402 static ExitStatus op_lctlg(DisasContext *s, DisasOps *o)
2403 {
2404 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2405 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2406 check_privileged(s);
2407 potential_page_fault(s);
2408 gen_helper_lctlg(cpu_env, r1, o->in2, r3);
2409 tcg_temp_free_i32(r1);
2410 tcg_temp_free_i32(r3);
2411 return NO_EXIT;
2412 }
2413 static ExitStatus op_lra(DisasContext *s, DisasOps *o)
2414 {
2415 check_privileged(s);
2416 potential_page_fault(s);
2417 gen_helper_lra(o->out, cpu_env, o->in2);
2418 set_cc_static(s);
2419 return NO_EXIT;
2420 }
2421
2422 static ExitStatus op_lpsw(DisasContext *s, DisasOps *o)
2423 {
2424 TCGv_i64 t1, t2;
2425
2426 check_privileged(s);
2427
2428 t1 = tcg_temp_new_i64();
2429 t2 = tcg_temp_new_i64();
2430 tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
2431 tcg_gen_addi_i64(o->in2, o->in2, 4);
2432 tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s));
2433 /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
2434 tcg_gen_shli_i64(t1, t1, 32);
2435 gen_helper_load_psw(cpu_env, t1, t2);
2436 tcg_temp_free_i64(t1);
2437 tcg_temp_free_i64(t2);
2438 return EXIT_NORETURN;
2439 }
2440 #endif
2441
2442 static ExitStatus op_lam(DisasContext *s, DisasOps *o)
2443 {
2444 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2445 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2446 potential_page_fault(s);
2447 gen_helper_lam(cpu_env, r1, o->in2, r3);
2448 tcg_temp_free_i32(r1);
2449 tcg_temp_free_i32(r3);
2450 return NO_EXIT;
2451 }
2452
2453 static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
2454 {
2455 int r1 = get_field(s->fields, r1);
2456 int r3 = get_field(s->fields, r3);
2457 TCGv_i64 t = tcg_temp_new_i64();
2458 TCGv_i64 t4 = tcg_const_i64(4);
2459
2460 while (1) {
2461 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2462 store_reg32_i64(r1, t);
2463 if (r1 == r3) {
2464 break;
2465 }
2466 tcg_gen_add_i64(o->in2, o->in2, t4);
2467 r1 = (r1 + 1) & 15;
2468 }
2469
2470 tcg_temp_free_i64(t);
2471 tcg_temp_free_i64(t4);
2472 return NO_EXIT;
2473 }
2474
2475 static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
2476 {
2477 int r1 = get_field(s->fields, r1);
2478 int r3 = get_field(s->fields, r3);
2479 TCGv_i64 t = tcg_temp_new_i64();
2480 TCGv_i64 t4 = tcg_const_i64(4);
2481
2482 while (1) {
2483 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2484 store_reg32h_i64(r1, t);
2485 if (r1 == r3) {
2486 break;
2487 }
2488 tcg_gen_add_i64(o->in2, o->in2, t4);
2489 r1 = (r1 + 1) & 15;
2490 }
2491
2492 tcg_temp_free_i64(t);
2493 tcg_temp_free_i64(t4);
2494 return NO_EXIT;
2495 }
2496
2497 static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
2498 {
2499 int r1 = get_field(s->fields, r1);
2500 int r3 = get_field(s->fields, r3);
2501 TCGv_i64 t8 = tcg_const_i64(8);
2502
2503 while (1) {
2504 tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
2505 if (r1 == r3) {
2506 break;
2507 }
2508 tcg_gen_add_i64(o->in2, o->in2, t8);
2509 r1 = (r1 + 1) & 15;
2510 }
2511
2512 tcg_temp_free_i64(t8);
2513 return NO_EXIT;
2514 }
2515
2516 static ExitStatus op_mov2(DisasContext *s, DisasOps *o)
2517 {
2518 o->out = o->in2;
2519 o->g_out = o->g_in2;
2520 TCGV_UNUSED_I64(o->in2);
2521 o->g_in2 = false;
2522 return NO_EXIT;
2523 }
2524
2525 static ExitStatus op_movx(DisasContext *s, DisasOps *o)
2526 {
2527 o->out = o->in1;
2528 o->out2 = o->in2;
2529 o->g_out = o->g_in1;
2530 o->g_out2 = o->g_in2;
2531 TCGV_UNUSED_I64(o->in1);
2532 TCGV_UNUSED_I64(o->in2);
2533 o->g_in1 = o->g_in2 = false;
2534 return NO_EXIT;
2535 }
2536
2537 static ExitStatus op_mvc(DisasContext *s, DisasOps *o)
2538 {
2539 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2540 potential_page_fault(s);
2541 gen_helper_mvc(cpu_env, l, o->addr1, o->in2);
2542 tcg_temp_free_i32(l);
2543 return NO_EXIT;
2544 }
2545
2546 static ExitStatus op_mvcl(DisasContext *s, DisasOps *o)
2547 {
2548 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2549 TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
2550 potential_page_fault(s);
2551 gen_helper_mvcl(cc_op, cpu_env, r1, r2);
2552 tcg_temp_free_i32(r1);
2553 tcg_temp_free_i32(r2);
2554 set_cc_static(s);
2555 return NO_EXIT;
2556 }
2557
2558 static ExitStatus op_mvcle(DisasContext *s, DisasOps *o)
2559 {
2560 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2561 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2562 potential_page_fault(s);
2563 gen_helper_mvcle(cc_op, cpu_env, r1, o->in2, r3);
2564 tcg_temp_free_i32(r1);
2565 tcg_temp_free_i32(r3);
2566 set_cc_static(s);
2567 return NO_EXIT;
2568 }
2569
2570 #ifndef CONFIG_USER_ONLY
2571 static ExitStatus op_mvcp(DisasContext *s, DisasOps *o)
2572 {
2573 int r1 = get_field(s->fields, l1);
2574 check_privileged(s);
2575 potential_page_fault(s);
2576 gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2577 set_cc_static(s);
2578 return NO_EXIT;
2579 }
2580
2581 static ExitStatus op_mvcs(DisasContext *s, DisasOps *o)
2582 {
2583 int r1 = get_field(s->fields, l1);
2584 check_privileged(s);
2585 potential_page_fault(s);
2586 gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2587 set_cc_static(s);
2588 return NO_EXIT;
2589 }
2590 #endif
2591
2592 static ExitStatus op_mvpg(DisasContext *s, DisasOps *o)
2593 {
2594 potential_page_fault(s);
2595 gen_helper_mvpg(cpu_env, regs[0], o->in1, o->in2);
2596 set_cc_static(s);
2597 return NO_EXIT;
2598 }
2599
2600 static ExitStatus op_mvst(DisasContext *s, DisasOps *o)
2601 {
2602 potential_page_fault(s);
2603 gen_helper_mvst(o->in1, cpu_env, regs[0], o->in1, o->in2);
2604 set_cc_static(s);
2605 return_low128(o->in2);
2606 return NO_EXIT;
2607 }
2608
2609 static ExitStatus op_mul(DisasContext *s, DisasOps *o)
2610 {
2611 tcg_gen_mul_i64(o->out, o->in1, o->in2);
2612 return NO_EXIT;
2613 }
2614
2615 static ExitStatus op_mul128(DisasContext *s, DisasOps *o)
2616 {
2617 gen_helper_mul128(o->out, cpu_env, o->in1, o->in2);
2618 return_low128(o->out2);
2619 return NO_EXIT;
2620 }
2621
2622 static ExitStatus op_meeb(DisasContext *s, DisasOps *o)
2623 {
2624 gen_helper_meeb(o->out, cpu_env, o->in1, o->in2);
2625 return NO_EXIT;
2626 }
2627
2628 static ExitStatus op_mdeb(DisasContext *s, DisasOps *o)
2629 {
2630 gen_helper_mdeb(o->out, cpu_env, o->in1, o->in2);
2631 return NO_EXIT;
2632 }
2633
2634 static ExitStatus op_mdb(DisasContext *s, DisasOps *o)
2635 {
2636 gen_helper_mdb(o->out, cpu_env, o->in1, o->in2);
2637 return NO_EXIT;
2638 }
2639
2640 static ExitStatus op_mxb(DisasContext *s, DisasOps *o)
2641 {
2642 gen_helper_mxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2643 return_low128(o->out2);
2644 return NO_EXIT;
2645 }
2646
2647 static ExitStatus op_mxdb(DisasContext *s, DisasOps *o)
2648 {
2649 gen_helper_mxdb(o->out, cpu_env, o->out, o->out2, o->in2);
2650 return_low128(o->out2);
2651 return NO_EXIT;
2652 }
2653
2654 static ExitStatus op_maeb(DisasContext *s, DisasOps *o)
2655 {
2656 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2657 gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3);
2658 tcg_temp_free_i64(r3);
2659 return NO_EXIT;
2660 }
2661
2662 static ExitStatus op_madb(DisasContext *s, DisasOps *o)
2663 {
2664 int r3 = get_field(s->fields, r3);
2665 gen_helper_madb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2666 return NO_EXIT;
2667 }
2668
2669 static ExitStatus op_mseb(DisasContext *s, DisasOps *o)
2670 {
2671 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2672 gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3);
2673 tcg_temp_free_i64(r3);
2674 return NO_EXIT;
2675 }
2676
2677 static ExitStatus op_msdb(DisasContext *s, DisasOps *o)
2678 {
2679 int r3 = get_field(s->fields, r3);
2680 gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2681 return NO_EXIT;
2682 }
2683
2684 static ExitStatus op_nabs(DisasContext *s, DisasOps *o)
2685 {
2686 gen_helper_nabs_i64(o->out, o->in2);
2687 return NO_EXIT;
2688 }
2689
2690 static ExitStatus op_nabsf32(DisasContext *s, DisasOps *o)
2691 {
2692 tcg_gen_ori_i64(o->out, o->in2, 0x80000000ull);
2693 return NO_EXIT;
2694 }
2695
2696 static ExitStatus op_nabsf64(DisasContext *s, DisasOps *o)
2697 {
2698 tcg_gen_ori_i64(o->out, o->in2, 0x8000000000000000ull);
2699 return NO_EXIT;
2700 }
2701
2702 static ExitStatus op_nabsf128(DisasContext *s, DisasOps *o)
2703 {
2704 tcg_gen_ori_i64(o->out, o->in1, 0x8000000000000000ull);
2705 tcg_gen_mov_i64(o->out2, o->in2);
2706 return NO_EXIT;
2707 }
2708
2709 static ExitStatus op_nc(DisasContext *s, DisasOps *o)
2710 {
2711 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2712 potential_page_fault(s);
2713 gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2);
2714 tcg_temp_free_i32(l);
2715 set_cc_static(s);
2716 return NO_EXIT;
2717 }
2718
2719 static ExitStatus op_neg(DisasContext *s, DisasOps *o)
2720 {
2721 tcg_gen_neg_i64(o->out, o->in2);
2722 return NO_EXIT;
2723 }
2724
2725 static ExitStatus op_negf32(DisasContext *s, DisasOps *o)
2726 {
2727 tcg_gen_xori_i64(o->out, o->in2, 0x80000000ull);
2728 return NO_EXIT;
2729 }
2730
2731 static ExitStatus op_negf64(DisasContext *s, DisasOps *o)
2732 {
2733 tcg_gen_xori_i64(o->out, o->in2, 0x8000000000000000ull);
2734 return NO_EXIT;
2735 }
2736
2737 static ExitStatus op_negf128(DisasContext *s, DisasOps *o)
2738 {
2739 tcg_gen_xori_i64(o->out, o->in1, 0x8000000000000000ull);
2740 tcg_gen_mov_i64(o->out2, o->in2);
2741 return NO_EXIT;
2742 }
2743
2744 static ExitStatus op_oc(DisasContext *s, DisasOps *o)
2745 {
2746 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2747 potential_page_fault(s);
2748 gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2);
2749 tcg_temp_free_i32(l);
2750 set_cc_static(s);
2751 return NO_EXIT;
2752 }
2753
2754 static ExitStatus op_or(DisasContext *s, DisasOps *o)
2755 {
2756 tcg_gen_or_i64(o->out, o->in1, o->in2);
2757 return NO_EXIT;
2758 }
2759
2760 static ExitStatus op_ori(DisasContext *s, DisasOps *o)
2761 {
2762 int shift = s->insn->data & 0xff;
2763 int size = s->insn->data >> 8;
2764 uint64_t mask = ((1ull << size) - 1) << shift;
2765
2766 assert(!o->g_in2);
2767 tcg_gen_shli_i64(o->in2, o->in2, shift);
2768 tcg_gen_or_i64(o->out, o->in1, o->in2);
2769
2770 /* Produce the CC from only the bits manipulated. */
2771 tcg_gen_andi_i64(cc_dst, o->out, mask);
2772 set_cc_nz_u64(s, cc_dst);
2773 return NO_EXIT;
2774 }
2775
2776 static ExitStatus op_rev16(DisasContext *s, DisasOps *o)
2777 {
2778 tcg_gen_bswap16_i64(o->out, o->in2);
2779 return NO_EXIT;
2780 }
2781
2782 static ExitStatus op_rev32(DisasContext *s, DisasOps *o)
2783 {
2784 tcg_gen_bswap32_i64(o->out, o->in2);
2785 return NO_EXIT;
2786 }
2787
2788 static ExitStatus op_rev64(DisasContext *s, DisasOps *o)
2789 {
2790 tcg_gen_bswap64_i64(o->out, o->in2);
2791 return NO_EXIT;
2792 }
2793
2794 static ExitStatus op_rll32(DisasContext *s, DisasOps *o)
2795 {
2796 TCGv_i32 t1 = tcg_temp_new_i32();
2797 TCGv_i32 t2 = tcg_temp_new_i32();
2798 TCGv_i32 to = tcg_temp_new_i32();
2799 tcg_gen_trunc_i64_i32(t1, o->in1);
2800 tcg_gen_trunc_i64_i32(t2, o->in2);
2801 tcg_gen_rotl_i32(to, t1, t2);
2802 tcg_gen_extu_i32_i64(o->out, to);
2803 tcg_temp_free_i32(t1);
2804 tcg_temp_free_i32(t2);
2805 tcg_temp_free_i32(to);
2806 return NO_EXIT;
2807 }
2808
2809 static ExitStatus op_rll64(DisasContext *s, DisasOps *o)
2810 {
2811 tcg_gen_rotl_i64(o->out, o->in1, o->in2);
2812 return NO_EXIT;
2813 }
2814
2815 static ExitStatus op_sar(DisasContext *s, DisasOps *o)
2816 {
2817 int r1 = get_field(s->fields, r1);
2818 tcg_gen_st32_i64(o->in2, cpu_env, offsetof(CPUS390XState, aregs[r1]));
2819 return NO_EXIT;
2820 }
2821
2822 static ExitStatus op_seb(DisasContext *s, DisasOps *o)
2823 {
2824 gen_helper_seb(o->out, cpu_env, o->in1, o->in2);
2825 return NO_EXIT;
2826 }
2827
2828 static ExitStatus op_sdb(DisasContext *s, DisasOps *o)
2829 {
2830 gen_helper_sdb(o->out, cpu_env, o->in1, o->in2);
2831 return NO_EXIT;
2832 }
2833
2834 static ExitStatus op_sxb(DisasContext *s, DisasOps *o)
2835 {
2836 gen_helper_sxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2837 return_low128(o->out2);
2838 return NO_EXIT;
2839 }
2840
2841 static ExitStatus op_sqeb(DisasContext *s, DisasOps *o)
2842 {
2843 gen_helper_sqeb(o->out, cpu_env, o->in2);
2844 return NO_EXIT;
2845 }
2846
2847 static ExitStatus op_sqdb(DisasContext *s, DisasOps *o)
2848 {
2849 gen_helper_sqdb(o->out, cpu_env, o->in2);
2850 return NO_EXIT;
2851 }
2852
2853 static ExitStatus op_sqxb(DisasContext *s, DisasOps *o)
2854 {
2855 gen_helper_sqxb(o->out, cpu_env, o->in1, o->in2);
2856 return_low128(o->out2);
2857 return NO_EXIT;
2858 }
2859
2860 #ifndef CONFIG_USER_ONLY
2861 static ExitStatus op_sigp(DisasContext *s, DisasOps *o)
2862 {
2863 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2864 check_privileged(s);
2865 potential_page_fault(s);
2866 gen_helper_sigp(cc_op, cpu_env, o->in2, r1, o->in1);
2867 tcg_temp_free_i32(r1);
2868 return NO_EXIT;
2869 }
2870 #endif
2871
2872 static ExitStatus op_sla(DisasContext *s, DisasOps *o)
2873 {
2874 uint64_t sign = 1ull << s->insn->data;
2875 enum cc_op cco = s->insn->data == 31 ? CC_OP_SLA_32 : CC_OP_SLA_64;
2876 gen_op_update2_cc_i64(s, cco, o->in1, o->in2);
2877 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2878 /* The arithmetic left shift is curious in that it does not affect
2879 the sign bit. Copy that over from the source unchanged. */
2880 tcg_gen_andi_i64(o->out, o->out, ~sign);
2881 tcg_gen_andi_i64(o->in1, o->in1, sign);
2882 tcg_gen_or_i64(o->out, o->out, o->in1);
2883 return NO_EXIT;
2884 }
2885
2886 static ExitStatus op_sll(DisasContext *s, DisasOps *o)
2887 {
2888 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2889 return NO_EXIT;
2890 }
2891
2892 static ExitStatus op_sra(DisasContext *s, DisasOps *o)
2893 {
2894 tcg_gen_sar_i64(o->out, o->in1, o->in2);
2895 return NO_EXIT;
2896 }
2897
2898 static ExitStatus op_srl(DisasContext *s, DisasOps *o)
2899 {
2900 tcg_gen_shr_i64(o->out, o->in1, o->in2);
2901 return NO_EXIT;
2902 }
2903
2904 static ExitStatus op_sfpc(DisasContext *s, DisasOps *o)
2905 {
2906 gen_helper_sfpc(cpu_env, o->in2);
2907 return NO_EXIT;
2908 }
2909
2910 #ifndef CONFIG_USER_ONLY
2911 static ExitStatus op_ssm(DisasContext *s, DisasOps *o)
2912 {
2913 check_privileged(s);
2914 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8);
2915 return NO_EXIT;
2916 }
2917
2918 static ExitStatus op_stck(DisasContext *s, DisasOps *o)
2919 {
2920 gen_helper_stck(o->out, cpu_env);
2921 /* ??? We don't implement clock states. */
2922 gen_op_movi_cc(s, 0);
2923 return NO_EXIT;
2924 }
2925
2926 static ExitStatus op_stctg(DisasContext *s, DisasOps *o)
2927 {
2928 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2929 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2930 check_privileged(s);
2931 potential_page_fault(s);
2932 gen_helper_stctg(cpu_env, r1, o->in2, r3);
2933 tcg_temp_free_i32(r1);
2934 tcg_temp_free_i32(r3);
2935 return NO_EXIT;
2936 }
2937
2938 static ExitStatus op_stctl(DisasContext *s, DisasOps *o)
2939 {
2940 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2941 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2942 check_privileged(s);
2943 potential_page_fault(s);
2944 gen_helper_stctl(cpu_env, r1, o->in2, r3);
2945 tcg_temp_free_i32(r1);
2946 tcg_temp_free_i32(r3);
2947 return NO_EXIT;
2948 }
2949
2950 static ExitStatus op_stidp(DisasContext *s, DisasOps *o)
2951 {
2952 check_privileged(s);
2953 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num));
2954 return NO_EXIT;
2955 }
2956
2957 static ExitStatus op_stnosm(DisasContext *s, DisasOps *o)
2958 {
2959 uint64_t i2 = get_field(s->fields, i2);
2960 TCGv_i64 t;
2961
2962 check_privileged(s);
2963
2964 /* It is important to do what the instruction name says: STORE THEN.
2965 If we let the output hook perform the store then if we fault and
2966 restart, we'll have the wrong SYSTEM MASK in place. */
2967 t = tcg_temp_new_i64();
2968 tcg_gen_shri_i64(t, psw_mask, 56);
2969 tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
2970 tcg_temp_free_i64(t);
2971
2972 if (s->fields->op == 0xac) {
2973 tcg_gen_andi_i64(psw_mask, psw_mask,
2974 (i2 << 56) | 0x00ffffffffffffffull);
2975 } else {
2976 tcg_gen_ori_i64(psw_mask, psw_mask, i2 << 56);
2977 }
2978 return NO_EXIT;
2979 }
2980 #endif
2981
2982 static ExitStatus op_st8(DisasContext *s, DisasOps *o)
2983 {
2984 tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
2985 return NO_EXIT;
2986 }
2987
2988 static ExitStatus op_st16(DisasContext *s, DisasOps *o)
2989 {
2990 tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
2991 return NO_EXIT;
2992 }
2993
2994 static ExitStatus op_st32(DisasContext *s, DisasOps *o)
2995 {
2996 tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s));
2997 return NO_EXIT;
2998 }
2999
3000 static ExitStatus op_st64(DisasContext *s, DisasOps *o)
3001 {
3002 tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
3003 return NO_EXIT;
3004 }
3005
3006 static ExitStatus op_stam(DisasContext *s, DisasOps *o)
3007 {
3008 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3009 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
3010 potential_page_fault(s);
3011 gen_helper_stam(cpu_env, r1, o->in2, r3);
3012 tcg_temp_free_i32(r1);
3013 tcg_temp_free_i32(r3);
3014 return NO_EXIT;
3015 }
3016
3017 static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
3018 {
3019 int m3 = get_field(s->fields, m3);
3020 int pos, base = s->insn->data;
3021 TCGv_i64 tmp = tcg_temp_new_i64();
3022
3023 pos = base + ctz32(m3) * 8;
3024 switch (m3) {
3025 case 0xf:
3026 /* Effectively a 32-bit store. */
3027 tcg_gen_shri_i64(tmp, o->in1, pos);
3028 tcg_gen_qemu_st32(tmp, o->in2, get_mem_index(s));
3029 break;
3030
3031 case 0xc:
3032 case 0x6:
3033 case 0x3:
3034 /* Effectively a 16-bit store. */
3035 tcg_gen_shri_i64(tmp, o->in1, pos);
3036 tcg_gen_qemu_st16(tmp, o->in2, get_mem_index(s));
3037 break;
3038
3039 case 0x8:
3040 case 0x4:
3041 case 0x2:
3042 case 0x1:
3043 /* Effectively an 8-bit store. */
3044 tcg_gen_shri_i64(tmp, o->in1, pos);
3045 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3046 break;
3047
3048 default:
3049 /* This is going to be a sequence of shifts and stores. */
3050 pos = base + 32 - 8;
3051 while (m3) {
3052 if (m3 & 0x8) {
3053 tcg_gen_shri_i64(tmp, o->in1, pos);
3054 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3055 tcg_gen_addi_i64(o->in2, o->in2, 1);
3056 }
3057 m3 = (m3 << 1) & 0xf;
3058 pos -= 8;
3059 }
3060 break;
3061 }
3062 tcg_temp_free_i64(tmp);
3063 return NO_EXIT;
3064 }
3065
3066 static ExitStatus op_stm(DisasContext *s, DisasOps *o)
3067 {
3068 int r1 = get_field(s->fields, r1);
3069 int r3 = get_field(s->fields, r3);
3070 int size = s->insn->data;
3071 TCGv_i64 tsize = tcg_const_i64(size);
3072
3073 while (1) {
3074 if (size == 8) {
3075 tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
3076 } else {
3077 tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s));
3078 }
3079 if (r1 == r3) {
3080 break;
3081 }
3082 tcg_gen_add_i64(o->in2, o->in2, tsize);
3083 r1 = (r1 + 1) & 15;
3084 }
3085
3086 tcg_temp_free_i64(tsize);
3087 return NO_EXIT;
3088 }
3089
3090 static ExitStatus op_stmh(DisasContext *s, DisasOps *o)
3091 {
3092 int r1 = get_field(s->fields, r1);
3093 int r3 = get_field(s->fields, r3);
3094 TCGv_i64 t = tcg_temp_new_i64();
3095 TCGv_i64 t4 = tcg_const_i64(4);
3096 TCGv_i64 t32 = tcg_const_i64(32);
3097
3098 while (1) {
3099 tcg_gen_shl_i64(t, regs[r1], t32);
3100 tcg_gen_qemu_st32(t, o->in2, get_mem_index(s));
3101 if (r1 == r3) {
3102 break;
3103 }
3104 tcg_gen_add_i64(o->in2, o->in2, t4);
3105 r1 = (r1 + 1) & 15;
3106 }
3107
3108 tcg_temp_free_i64(t);
3109 tcg_temp_free_i64(t4);
3110 tcg_temp_free_i64(t32);
3111 return NO_EXIT;
3112 }
3113
3114 static ExitStatus op_srst(DisasContext *s, DisasOps *o)
3115 {
3116 potential_page_fault(s);
3117 gen_helper_srst(o->in1, cpu_env, regs[0], o->in1, o->in2);
3118 set_cc_static(s);
3119 return_low128(o->in2);
3120 return NO_EXIT;
3121 }
3122
3123 static ExitStatus op_sub(DisasContext *s, DisasOps *o)
3124 {
3125 tcg_gen_sub_i64(o->out, o->in1, o->in2);
3126 return NO_EXIT;
3127 }
3128
3129 static ExitStatus op_subb(DisasContext *s, DisasOps *o)
3130 {
3131 TCGv_i64 cc;
3132
3133 assert(!o->g_in2);
3134 tcg_gen_not_i64(o->in2, o->in2);
3135 tcg_gen_add_i64(o->out, o->in1, o->in2);
3136
3137 /* XXX possible optimization point */
3138 gen_op_calc_cc(s);
3139 cc = tcg_temp_new_i64();
3140 tcg_gen_extu_i32_i64(cc, cc_op);
3141 tcg_gen_shri_i64(cc, cc, 1);
3142 tcg_gen_add_i64(o->out, o->out, cc);
3143 tcg_temp_free_i64(cc);
3144 return NO_EXIT;
3145 }
3146
3147 static ExitStatus op_svc(DisasContext *s, DisasOps *o)
3148 {
3149 TCGv_i32 t;
3150
3151 update_psw_addr(s);
3152 gen_op_calc_cc(s);
3153
3154 t = tcg_const_i32(get_field(s->fields, i1) & 0xff);
3155 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code));
3156 tcg_temp_free_i32(t);
3157
3158 t = tcg_const_i32(s->next_pc - s->pc);
3159 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen));
3160 tcg_temp_free_i32(t);
3161
3162 gen_exception(EXCP_SVC);
3163 return EXIT_NORETURN;
3164 }
3165
3166 static ExitStatus op_tceb(DisasContext *s, DisasOps *o)
3167 {
3168 gen_helper_tceb(cc_op, o->in1, o->in2);
3169 set_cc_static(s);
3170 return NO_EXIT;
3171 }
3172
3173 static ExitStatus op_tcdb(DisasContext *s, DisasOps *o)
3174 {
3175 gen_helper_tcdb(cc_op, o->in1, o->in2);
3176 set_cc_static(s);
3177 return NO_EXIT;
3178 }
3179
3180 static ExitStatus op_tcxb(DisasContext *s, DisasOps *o)
3181 {
3182 gen_helper_tcxb(cc_op, o->out, o->out2, o->in2);
3183 set_cc_static(s);
3184 return NO_EXIT;
3185 }
3186
3187 #ifndef CONFIG_USER_ONLY
3188 static ExitStatus op_tprot(DisasContext *s, DisasOps *o)
3189 {
3190 potential_page_fault(s);
3191 gen_helper_tprot(cc_op, o->addr1, o->in2);
3192 set_cc_static(s);
3193 return NO_EXIT;
3194 }
3195 #endif
3196
3197 static ExitStatus op_tr(DisasContext *s, DisasOps *o)
3198 {
3199 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3200 potential_page_fault(s);
3201 gen_helper_tr(cpu_env, l, o->addr1, o->in2);
3202 tcg_temp_free_i32(l);
3203 set_cc_static(s);
3204 return NO_EXIT;
3205 }
3206
3207 static ExitStatus op_unpk(DisasContext *s, DisasOps *o)
3208 {
3209 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3210 potential_page_fault(s);
3211 gen_helper_unpk(cpu_env, l, o->addr1, o->in2);
3212 tcg_temp_free_i32(l);
3213 return NO_EXIT;
3214 }
3215
3216 static ExitStatus op_xc(DisasContext *s, DisasOps *o)
3217 {
3218 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3219 potential_page_fault(s);
3220 gen_helper_xc(cc_op, cpu_env, l, o->addr1, o->in2);
3221 tcg_temp_free_i32(l);
3222 set_cc_static(s);
3223 return NO_EXIT;
3224 }
3225
3226 static ExitStatus op_xor(DisasContext *s, DisasOps *o)
3227 {
3228 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3229 return NO_EXIT;
3230 }
3231
3232 static ExitStatus op_xori(DisasContext *s, DisasOps *o)
3233 {
3234 int shift = s->insn->data & 0xff;
3235 int size = s->insn->data >> 8;
3236 uint64_t mask = ((1ull << size) - 1) << shift;
3237
3238 assert(!o->g_in2);
3239 tcg_gen_shli_i64(o->in2, o->in2, shift);
3240 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3241
3242 /* Produce the CC from only the bits manipulated. */
3243 tcg_gen_andi_i64(cc_dst, o->out, mask);
3244 set_cc_nz_u64(s, cc_dst);
3245 return NO_EXIT;
3246 }
3247
3248 static ExitStatus op_zero(DisasContext *s, DisasOps *o)
3249 {
3250 o->out = tcg_const_i64(0);
3251 return NO_EXIT;
3252 }
3253
3254 static ExitStatus op_zero2(DisasContext *s, DisasOps *o)
3255 {
3256 o->out = tcg_const_i64(0);
3257 o->out2 = o->out;
3258 o->g_out2 = true;
3259 return NO_EXIT;
3260 }
3261
3262 /* ====================================================================== */
3263 /* The "Cc OUTput" generators. Given the generated output (and in some cases
3264 the original inputs), update the various cc data structures in order to
3265 be able to compute the new condition code. */
3266
3267 static void cout_abs32(DisasContext *s, DisasOps *o)
3268 {
3269 gen_op_update1_cc_i64(s, CC_OP_ABS_32, o->out);
3270 }
3271
3272 static void cout_abs64(DisasContext *s, DisasOps *o)
3273 {
3274 gen_op_update1_cc_i64(s, CC_OP_ABS_64, o->out);
3275 }
3276
3277 static void cout_adds32(DisasContext *s, DisasOps *o)
3278 {
3279 gen_op_update3_cc_i64(s, CC_OP_ADD_32, o->in1, o->in2, o->out);
3280 }
3281
3282 static void cout_adds64(DisasContext *s, DisasOps *o)
3283 {
3284 gen_op_update3_cc_i64(s, CC_OP_ADD_64, o->in1, o->in2, o->out);
3285 }
3286
3287 static void cout_addu32(DisasContext *s, DisasOps *o)
3288 {
3289 gen_op_update3_cc_i64(s, CC_OP_ADDU_32, o->in1, o->in2, o->out);
3290 }
3291
3292 static void cout_addu64(DisasContext *s, DisasOps *o)
3293 {
3294 gen_op_update3_cc_i64(s, CC_OP_ADDU_64, o->in1, o->in2, o->out);
3295 }
3296
3297 static void cout_addc32(DisasContext *s, DisasOps *o)
3298 {
3299 gen_op_update3_cc_i64(s, CC_OP_ADDC_32, o->in1, o->in2, o->out);
3300 }
3301
3302 static void cout_addc64(DisasContext *s, DisasOps *o)
3303 {
3304 gen_op_update3_cc_i64(s, CC_OP_ADDC_64, o->in1, o->in2, o->out);
3305 }
3306
3307 static void cout_cmps32(DisasContext *s, DisasOps *o)
3308 {
3309 gen_op_update2_cc_i64(s, CC_OP_LTGT_32, o->in1, o->in2);
3310 }
3311
3312 static void cout_cmps64(DisasContext *s, DisasOps *o)
3313 {
3314 gen_op_update2_cc_i64(s, CC_OP_LTGT_64, o->in1, o->in2);
3315 }
3316
3317 static void cout_cmpu32(DisasContext *s, DisasOps *o)
3318 {
3319 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_32, o->in1, o->in2);
3320 }
3321
3322 static void cout_cmpu64(DisasContext *s, DisasOps *o)
3323 {
3324 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, o->in1, o->in2);
3325 }
3326
3327 static void cout_f32(DisasContext *s, DisasOps *o)
3328 {
3329 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, o->out);
3330 }
3331
3332 static void cout_f64(DisasContext *s, DisasOps *o)
3333 {
3334 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, o->out);
3335 }
3336
3337 static void cout_f128(DisasContext *s, DisasOps *o)
3338 {
3339 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, o->out, o->out2);
3340 }
3341
3342 static void cout_nabs32(DisasContext *s, DisasOps *o)
3343 {
3344 gen_op_update1_cc_i64(s, CC_OP_NABS_32, o->out);
3345 }
3346
3347 static void cout_nabs64(DisasContext *s, DisasOps *o)
3348 {
3349 gen_op_update1_cc_i64(s, CC_OP_NABS_64, o->out);
3350 }
3351
3352 static void cout_neg32(DisasContext *s, DisasOps *o)
3353 {
3354 gen_op_update1_cc_i64(s, CC_OP_COMP_32, o->out);
3355 }
3356
3357 static void cout_neg64(DisasContext *s, DisasOps *o)
3358 {
3359 gen_op_update1_cc_i64(s, CC_OP_COMP_64, o->out);
3360 }
3361
3362 static void cout_nz32(DisasContext *s, DisasOps *o)
3363 {
3364 tcg_gen_ext32u_i64(cc_dst, o->out);
3365 gen_op_update1_cc_i64(s, CC_OP_NZ, cc_dst);
3366 }
3367
3368 static void cout_nz64(DisasContext *s, DisasOps *o)
3369 {
3370 gen_op_update1_cc_i64(s, CC_OP_NZ, o->out);
3371 }
3372
3373 static void cout_s32(DisasContext *s, DisasOps *o)
3374 {
3375 gen_op_update1_cc_i64(s, CC_OP_LTGT0_32, o->out);
3376 }
3377
3378 static void cout_s64(DisasContext *s, DisasOps *o)
3379 {
3380 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, o->out);
3381 }
3382
3383 static void cout_subs32(DisasContext *s, DisasOps *o)
3384 {
3385 gen_op_update3_cc_i64(s, CC_OP_SUB_32, o->in1, o->in2, o->out);
3386 }
3387
3388 static void cout_subs64(DisasContext *s, DisasOps *o)
3389 {
3390 gen_op_update3_cc_i64(s, CC_OP_SUB_64, o->in1, o->in2, o->out);
3391 }
3392
3393 static void cout_subu32(DisasContext *s, DisasOps *o)
3394 {
3395 gen_op_update3_cc_i64(s, CC_OP_SUBU_32, o->in1, o->in2, o->out);
3396 }
3397
3398 static void cout_subu64(DisasContext *s, DisasOps *o)
3399 {
3400 gen_op_update3_cc_i64(s, CC_OP_SUBU_64, o->in1, o->in2, o->out);
3401 }
3402
3403 static void cout_subb32(DisasContext *s, DisasOps *o)
3404 {
3405 gen_op_update3_cc_i64(s, CC_OP_SUBB_32, o->in1, o->in2, o->out);
3406 }
3407
3408 static void cout_subb64(DisasContext *s, DisasOps *o)
3409 {
3410 gen_op_update3_cc_i64(s, CC_OP_SUBB_64, o->in1, o->in2, o->out);
3411 }
3412
3413 static void cout_tm32(DisasContext *s, DisasOps *o)
3414 {
3415 gen_op_update2_cc_i64(s, CC_OP_TM_32, o->in1, o->in2);
3416 }
3417
3418 static void cout_tm64(DisasContext *s, DisasOps *o)
3419 {
3420 gen_op_update2_cc_i64(s, CC_OP_TM_64, o->in1, o->in2);
3421 }
3422
3423 /* ====================================================================== */
3424 /* The "PREPeration" generators. These initialize the DisasOps.OUT fields
3425 with the TCG register to which we will write. Used in combination with
3426 the "wout" generators, in some cases we need a new temporary, and in
3427 some cases we can write to a TCG global. */
3428
3429 static void prep_new(DisasContext *s, DisasFields *f, DisasOps *o)
3430 {
3431 o->out = tcg_temp_new_i64();
3432 }
3433
3434 static void prep_new_P(DisasContext *s, DisasFields *f, DisasOps *o)
3435 {
3436 o->out = tcg_temp_new_i64();
3437 o->out2 = tcg_temp_new_i64();
3438 }
3439
3440 static void prep_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3441 {
3442 o->out = regs[get_field(f, r1)];
3443 o->g_out = true;
3444 }
3445
3446 static void prep_r1_P(DisasContext *s, DisasFields *f, DisasOps *o)
3447 {
3448 /* ??? Specification exception: r1 must be even. */
3449 int r1 = get_field(f, r1);
3450 o->out = regs[r1];
3451 o->out2 = regs[(r1 + 1) & 15];
3452 o->g_out = o->g_out2 = true;
3453 }
3454
3455 static void prep_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3456 {
3457 o->out = fregs[get_field(f, r1)];
3458 o->g_out = true;
3459 }
3460
3461 static void prep_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3462 {
3463 /* ??? Specification exception: r1 must be < 14. */
3464 int r1 = get_field(f, r1);
3465 o->out = fregs[r1];
3466 o->out2 = fregs[(r1 + 2) & 15];
3467 o->g_out = o->g_out2 = true;
3468 }
3469
3470 /* ====================================================================== */
3471 /* The "Write OUTput" generators. These generally perform some non-trivial
3472 copy of data to TCG globals, or to main memory. The trivial cases are
3473 generally handled by having a "prep" generator install the TCG global
3474 as the destination of the operation. */
3475
3476 static void wout_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3477 {
3478 store_reg(get_field(f, r1), o->out);
3479 }
3480
3481 static void wout_r1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3482 {
3483 int r1 = get_field(f, r1);
3484 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8);
3485 }
3486
3487 static void wout_r1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3488 {
3489 int r1 = get_field(f, r1);
3490 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 16);
3491 }
3492
3493 static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3494 {
3495 store_reg32_i64(get_field(f, r1), o->out);
3496 }
3497
3498 static void wout_r1_P32(DisasContext *s, DisasFields *f, DisasOps *o)
3499 {
3500 /* ??? Specification exception: r1 must be even. */
3501 int r1 = get_field(f, r1);
3502 store_reg32_i64(r1, o->out);
3503 store_reg32_i64((r1 + 1) & 15, o->out2);
3504 }
3505
3506 static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3507 {
3508 /* ??? Specification exception: r1 must be even. */
3509 int r1 = get_field(f, r1);
3510 store_reg32_i64((r1 + 1) & 15, o->out);
3511 tcg_gen_shri_i64(o->out, o->out, 32);
3512 store_reg32_i64(r1, o->out);
3513 }
3514
3515 static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3516 {
3517 store_freg32_i64(get_field(f, r1), o->out);
3518 }
3519
3520 static void wout_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3521 {
3522 store_freg(get_field(f, r1), o->out);
3523 }
3524
3525 static void wout_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3526 {
3527 /* ??? Specification exception: r1 must be < 14. */
3528 int f1 = get_field(s->fields, r1);
3529 store_freg(f1, o->out);
3530 store_freg((f1 + 2) & 15, o->out2);
3531 }
3532
3533 static void wout_cond_r1r2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3534 {
3535 if (get_field(f, r1) != get_field(f, r2)) {
3536 store_reg32_i64(get_field(f, r1), o->out);
3537 }
3538 }
3539
3540 static void wout_cond_e1e2(DisasContext *s, DisasFields *f, DisasOps *o)
3541 {
3542 if (get_field(f, r1) != get_field(f, r2)) {
3543 store_freg32_i64(get_field(f, r1), o->out);
3544 }
3545 }
3546
3547 static void wout_m1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3548 {
3549 tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s));
3550 }
3551
3552 static void wout_m1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3553 {
3554 tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s));
3555 }
3556
3557 static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3558 {
3559 tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
3560 }
3561
3562 static void wout_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3563 {
3564 tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
3565 }
3566
3567 static void wout_m2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3568 {
3569 tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s));
3570 }
3571
3572 /* ====================================================================== */
3573 /* The "INput 1" generators. These load the first operand to an insn. */
3574
3575 static void in1_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3576 {
3577 o->in1 = load_reg(get_field(f, r1));
3578 }
3579
3580 static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3581 {
3582 o->in1 = regs[get_field(f, r1)];
3583 o->g_in1 = true;
3584 }
3585
3586 static void in1_r1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3587 {
3588 o->in1 = tcg_temp_new_i64();
3589 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r1)]);
3590 }
3591
3592 static void in1_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3593 {
3594 o->in1 = tcg_temp_new_i64();
3595 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r1)]);
3596 }
3597
3598 static void in1_r1_sr32(DisasContext *s, DisasFields *f, DisasOps *o)
3599 {
3600 o->in1 = tcg_temp_new_i64();
3601 tcg_gen_shri_i64(o->in1, regs[get_field(f, r1)], 32);
3602 }
3603
3604 static void in1_r1p1(DisasContext *s, DisasFields *f, DisasOps *o)
3605 {
3606 /* ??? Specification exception: r1 must be even. */
3607 int r1 = get_field(f, r1);
3608 o->in1 = load_reg((r1 + 1) & 15);
3609 }
3610
3611 static void in1_r1p1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3612 {
3613 /* ??? Specification exception: r1 must be even. */
3614 int r1 = get_field(f, r1);
3615 o->in1 = tcg_temp_new_i64();
3616 tcg_gen_ext32s_i64(o->in1, regs[(r1 + 1) & 15]);
3617 }
3618
3619 static void in1_r1p1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3620 {
3621 /* ??? Specification exception: r1 must be even. */
3622 int r1 = get_field(f, r1);
3623 o->in1 = tcg_temp_new_i64();
3624 tcg_gen_ext32u_i64(o->in1, regs[(r1 + 1) & 15]);
3625 }
3626
3627 static void in1_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3628 {
3629 /* ??? Specification exception: r1 must be even. */
3630 int r1 = get_field(f, r1);
3631 o->in1 = tcg_temp_new_i64();
3632 tcg_gen_concat32_i64(o->in1, regs[r1 + 1], regs[r1]);
3633 }
3634
3635 static void in1_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3636 {
3637 o->in1 = load_reg(get_field(f, r2));
3638 }
3639
3640 static void in1_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3641 {
3642 o->in1 = load_reg(get_field(f, r3));
3643 }
3644
3645 static void in1_r3_o(DisasContext *s, DisasFields *f, DisasOps *o)
3646 {
3647 o->in1 = regs[get_field(f, r3)];
3648 o->g_in1 = true;
3649 }
3650
3651 static void in1_r3_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3652 {
3653 o->in1 = tcg_temp_new_i64();
3654 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r3)]);
3655 }
3656
3657 static void in1_r3_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3658 {
3659 o->in1 = tcg_temp_new_i64();
3660 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r3)]);
3661 }
3662
3663 static void in1_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3664 {
3665 o->in1 = load_freg32_i64(get_field(f, r1));
3666 }
3667
3668 static void in1_f1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3669 {
3670 o->in1 = fregs[get_field(f, r1)];
3671 o->g_in1 = true;
3672 }
3673
3674 static void in1_x1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3675 {
3676 /* ??? Specification exception: r1 must be < 14. */
3677 int r1 = get_field(f, r1);
3678 o->out = fregs[r1];
3679 o->out2 = fregs[(r1 + 2) & 15];
3680 o->g_out = o->g_out2 = true;
3681 }
3682
3683 static void in1_la1(DisasContext *s, DisasFields *f, DisasOps *o)
3684 {
3685 o->addr1 = get_address(s, 0, get_field(f, b1), get_field(f, d1));
3686 }
3687
3688 static void in1_la2(DisasContext *s, DisasFields *f, DisasOps *o)
3689 {
3690 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3691 o->addr1 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3692 }
3693
3694 static void in1_m1_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3695 {
3696 in1_la1(s, f, o);
3697 o->in1 = tcg_temp_new_i64();
3698 tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s));
3699 }
3700
3701 static void in1_m1_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3702 {
3703 in1_la1(s, f, o);
3704 o->in1 = tcg_temp_new_i64();
3705 tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s));
3706 }
3707
3708 static void in1_m1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3709 {
3710 in1_la1(s, f, o);
3711 o->in1 = tcg_temp_new_i64();
3712 tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s));
3713 }
3714
3715 static void in1_m1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3716 {
3717 in1_la1(s, f, o);
3718 o->in1 = tcg_temp_new_i64();
3719 tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s));
3720 }
3721
3722 static void in1_m1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3723 {
3724 in1_la1(s, f, o);
3725 o->in1 = tcg_temp_new_i64();
3726 tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s));
3727 }
3728
3729 static void in1_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3730 {
3731 in1_la1(s, f, o);
3732 o->in1 = tcg_temp_new_i64();
3733 tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s));
3734 }
3735
3736 /* ====================================================================== */
3737 /* The "INput 2" generators. These load the second operand to an insn. */
3738
3739 static void in2_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3740 {
3741 o->in2 = regs[get_field(f, r1)];
3742 o->g_in2 = true;
3743 }
3744
3745 static void in2_r1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3746 {
3747 o->in2 = tcg_temp_new_i64();
3748 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r1)]);
3749 }
3750
3751 static void in2_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3752 {
3753 o->in2 = tcg_temp_new_i64();
3754 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r1)]);
3755 }
3756
3757 static void in2_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3758 {
3759 o->in2 = load_reg(get_field(f, r2));
3760 }
3761
3762 static void in2_r2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3763 {
3764 o->in2 = regs[get_field(f, r2)];
3765 o->g_in2 = true;
3766 }
3767
3768 static void in2_r2_nz(DisasContext *s, DisasFields *f, DisasOps *o)
3769 {
3770 int r2 = get_field(f, r2);
3771 if (r2 != 0) {
3772 o->in2 = load_reg(r2);
3773 }
3774 }
3775
3776 static void in2_r2_8s(DisasContext *s, DisasFields *f, DisasOps *o)
3777 {
3778 o->in2 = tcg_temp_new_i64();
3779 tcg_gen_ext8s_i64(o->in2, regs[get_field(f, r2)]);
3780 }
3781
3782 static void in2_r2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3783 {
3784 o->in2 = tcg_temp_new_i64();
3785 tcg_gen_ext8u_i64(o->in2, regs[get_field(f, r2)]);
3786 }
3787
3788 static void in2_r2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3789 {
3790 o->in2 = tcg_temp_new_i64();
3791 tcg_gen_ext16s_i64(o->in2, regs[get_field(f, r2)]);
3792 }
3793
3794 static void in2_r2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3795 {
3796 o->in2 = tcg_temp_new_i64();
3797 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r2)]);
3798 }
3799
3800 static void in2_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3801 {
3802 o->in2 = load_reg(get_field(f, r3));
3803 }
3804
3805 static void in2_r2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3806 {
3807 o->in2 = tcg_temp_new_i64();
3808 tcg_gen_ext32s_i64(o->in2, regs[get_field(f, r2)]);
3809 }
3810
3811 static void in2_r2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3812 {
3813 o->in2 = tcg_temp_new_i64();
3814 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r2)]);
3815 }
3816
3817 static void in2_e2(DisasContext *s, DisasFields *f, DisasOps *o)
3818 {
3819 o->in2 = load_freg32_i64(get_field(f, r2));
3820 }
3821
3822 static void in2_f2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3823 {
3824 o->in2 = fregs[get_field(f, r2)];
3825 o->g_in2 = true;
3826 }
3827
3828 static void in2_x2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3829 {
3830 /* ??? Specification exception: r1 must be < 14. */
3831 int r2 = get_field(f, r2);
3832 o->in1 = fregs[r2];
3833 o->in2 = fregs[(r2 + 2) & 15];
3834 o->g_in1 = o->g_in2 = true;
3835 }
3836
3837 static void in2_ra2(DisasContext *s, DisasFields *f, DisasOps *o)
3838 {
3839 o->in2 = get_address(s, 0, get_field(f, r2), 0);
3840 }
3841
3842 static void in2_a2(DisasContext *s, DisasFields *f, DisasOps *o)
3843 {
3844 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3845 o->in2 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3846 }
3847
3848 static void in2_ri2(DisasContext *s, DisasFields *f, DisasOps *o)
3849 {
3850 o->in2 = tcg_const_i64(s->pc + (int64_t)get_field(f, i2) * 2);
3851 }
3852
3853 static void in2_sh32(DisasContext *s, DisasFields *f, DisasOps *o)
3854 {
3855 help_l2_shift(s, f, o, 31);
3856 }
3857
3858 static void in2_sh64(DisasContext *s, DisasFields *f, DisasOps *o)
3859 {
3860 help_l2_shift(s, f, o, 63);
3861 }
3862
3863 static void in2_m2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3864 {
3865 in2_a2(s, f, o);
3866 tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s));
3867 }
3868
3869 static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3870 {
3871 in2_a2(s, f, o);
3872 tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
3873 }
3874
3875 static void in2_m2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3876 {
3877 in2_a2(s, f, o);
3878 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3879 }
3880
3881 static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3882 {
3883 in2_a2(s, f, o);
3884 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3885 }
3886
3887 static void in2_m2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3888 {
3889 in2_a2(s, f, o);
3890 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3891 }
3892
3893 static void in2_m2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3894 {
3895 in2_a2(s, f, o);
3896 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3897 }
3898
3899 static void in2_mri2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3900 {
3901 in2_ri2(s, f, o);
3902 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3903 }
3904
3905 static void in2_mri2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3906 {
3907 in2_ri2(s, f, o);
3908 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3909 }
3910
3911 static void in2_mri2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3912 {
3913 in2_ri2(s, f, o);
3914 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3915 }
3916
3917 static void in2_mri2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3918 {
3919 in2_ri2(s, f, o);
3920 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3921 }
3922
3923 static void in2_i2(DisasContext *s, DisasFields *f, DisasOps *o)
3924 {
3925 o->in2 = tcg_const_i64(get_field(f, i2));
3926 }
3927
3928 static void in2_i2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3929 {
3930 o->in2 = tcg_const_i64((uint8_t)get_field(f, i2));
3931 }
3932
3933 static void in2_i2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3934 {
3935 o->in2 = tcg_const_i64((uint16_t)get_field(f, i2));
3936 }
3937
3938 static void in2_i2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3939 {
3940 o->in2 = tcg_const_i64((uint32_t)get_field(f, i2));
3941 }
3942
3943 static void in2_i2_16u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
3944 {
3945 uint64_t i2 = (uint16_t)get_field(f, i2);
3946 o->in2 = tcg_const_i64(i2 << s->insn->data);
3947 }
3948
3949 static void in2_i2_32u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
3950 {
3951 uint64_t i2 = (uint32_t)get_field(f, i2);
3952 o->in2 = tcg_const_i64(i2 << s->insn->data);
3953 }
3954
3955 /* ====================================================================== */
3956
3957 /* Find opc within the table of insns. This is formulated as a switch
3958 statement so that (1) we get compile-time notice of cut-paste errors
3959 for duplicated opcodes, and (2) the compiler generates the binary
3960 search tree, rather than us having to post-process the table. */
3961
3962 #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
3963 D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0)
3964
3965 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) insn_ ## NM,
3966
3967 enum DisasInsnEnum {
3968 #include "insn-data.def"
3969 };
3970
3971 #undef D
3972 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) { \
3973 .opc = OPC, \
3974 .fmt = FMT_##FT, \
3975 .fac = FAC_##FC, \
3976 .name = #NM, \
3977 .help_in1 = in1_##I1, \
3978 .help_in2 = in2_##I2, \
3979 .help_prep = prep_##P, \
3980 .help_wout = wout_##W, \
3981 .help_cout = cout_##CC, \
3982 .help_op = op_##OP, \
3983 .data = D \
3984 },
3985
3986 /* Allow 0 to be used for NULL in the table below. */
3987 #define in1_0 NULL
3988 #define in2_0 NULL
3989 #define prep_0 NULL
3990 #define wout_0 NULL
3991 #define cout_0 NULL
3992 #define op_0 NULL
3993
3994 static const DisasInsn insn_info[] = {
3995 #include "insn-data.def"
3996 };
3997
3998 #undef D
3999 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
4000 case OPC: return &insn_info[insn_ ## NM];
4001
4002 static const DisasInsn *lookup_opc(uint16_t opc)
4003 {
4004 switch (opc) {
4005 #include "insn-data.def"
4006 default:
4007 return NULL;
4008 }
4009 }
4010
4011 #undef D
4012 #undef C
4013
4014 /* Extract a field from the insn. The INSN should be left-aligned in
4015 the uint64_t so that we can more easily utilize the big-bit-endian
4016 definitions we extract from the Principals of Operation. */
4017
4018 static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn)
4019 {
4020 uint32_t r, m;
4021
4022 if (f->size == 0) {
4023 return;
4024 }
4025
4026 /* Zero extract the field from the insn. */
4027 r = (insn << f->beg) >> (64 - f->size);
4028
4029 /* Sign-extend, or un-swap the field as necessary. */
4030 switch (f->type) {
4031 case 0: /* unsigned */
4032 break;
4033 case 1: /* signed */
4034 assert(f->size <= 32);
4035 m = 1u << (f->size - 1);
4036 r = (r ^ m) - m;
4037 break;
4038 case 2: /* dl+dh split, signed 20 bit. */
4039 r = ((int8_t)r << 12) | (r >> 8);
4040 break;
4041 default:
4042 abort();
4043 }
4044
4045 /* Validate that the "compressed" encoding we selected above is valid.
4046 I.e. we havn't make two different original fields overlap. */
4047 assert(((o->presentC >> f->indexC) & 1) == 0);
4048 o->presentC |= 1 << f->indexC;
4049 o->presentO |= 1 << f->indexO;
4050
4051 o->c[f->indexC] = r;
4052 }
4053
4054 /* Lookup the insn at the current PC, extracting the operands into O and
4055 returning the info struct for the insn. Returns NULL for invalid insn. */
4056
4057 static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
4058 DisasFields *f)
4059 {
4060 uint64_t insn, pc = s->pc;
4061 int op, op2, ilen;
4062 const DisasInsn *info;
4063
4064 insn = ld_code2(env, pc);
4065 op = (insn >> 8) & 0xff;
4066 ilen = get_ilen(op);
4067 s->next_pc = s->pc + ilen;
4068
4069 switch (ilen) {
4070 case 2:
4071 insn = insn << 48;
4072 break;
4073 case 4:
4074 insn = ld_code4(env, pc) << 32;
4075 break;
4076 case 6:
4077 insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
4078 break;
4079 default:
4080 abort();
4081 }
4082
4083 /* We can't actually determine the insn format until we've looked up
4084 the full insn opcode. Which we can't do without locating the
4085 secondary opcode. Assume by default that OP2 is at bit 40; for
4086 those smaller insns that don't actually have a secondary opcode
4087 this will correctly result in OP2 = 0. */
4088 switch (op) {
4089 case 0x01: /* E */
4090 case 0x80: /* S */
4091 case 0x82: /* S */
4092 case 0x93: /* S */
4093 case 0xb2: /* S, RRF, RRE */
4094 case 0xb3: /* RRE, RRD, RRF */
4095 case 0xb9: /* RRE, RRF */
4096 case 0xe5: /* SSE, SIL */
4097 op2 = (insn << 8) >> 56;
4098 break;
4099 case 0xa5: /* RI */
4100 case 0xa7: /* RI */
4101 case 0xc0: /* RIL */
4102 case 0xc2: /* RIL */
4103 case 0xc4: /* RIL */
4104 case 0xc6: /* RIL */
4105 case 0xc8: /* SSF */
4106 case 0xcc: /* RIL */
4107 op2 = (insn << 12) >> 60;
4108 break;
4109 case 0xd0 ... 0xdf: /* SS */
4110 case 0xe1: /* SS */
4111 case 0xe2: /* SS */
4112 case 0xe8: /* SS */
4113 case 0xe9: /* SS */
4114 case 0xea: /* SS */
4115 case 0xee ... 0xf3: /* SS */
4116 case 0xf8 ... 0xfd: /* SS */
4117 op2 = 0;
4118 break;
4119 default:
4120 op2 = (insn << 40) >> 56;
4121 break;
4122 }
4123
4124 memset(f, 0, sizeof(*f));
4125 f->op = op;
4126 f->op2 = op2;
4127
4128 /* Lookup the instruction. */
4129 info = lookup_opc(op << 8 | op2);
4130
4131 /* If we found it, extract the operands. */
4132 if (info != NULL) {
4133 DisasFormat fmt = info->fmt;
4134 int i;
4135
4136 for (i = 0; i < NUM_C_FIELD; ++i) {
4137 extract_field(f, &format_info[fmt].op[i], insn);
4138 }
4139 }
4140 return info;
4141 }
4142
4143 static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
4144 {
4145 const DisasInsn *insn;
4146 ExitStatus ret = NO_EXIT;
4147 DisasFields f;
4148 DisasOps o;
4149
4150 insn = extract_insn(env, s, &f);
4151
4152 /* If not found, try the old interpreter. This includes ILLOPC. */
4153 if (insn == NULL) {
4154 disas_s390_insn(env, s);
4155 switch (s->is_jmp) {
4156 case DISAS_NEXT:
4157 ret = NO_EXIT;
4158 break;
4159 case DISAS_TB_JUMP:
4160 ret = EXIT_GOTO_TB;
4161 break;
4162 case DISAS_JUMP:
4163 ret = EXIT_PC_UPDATED;
4164 break;
4165 case DISAS_EXCP:
4166 ret = EXIT_NORETURN;
4167 break;
4168 default:
4169 abort();
4170 }
4171
4172 s->pc = s->next_pc;
4173 return ret;
4174 }
4175
4176 /* Set up the strutures we use to communicate with the helpers. */
4177 s->insn = insn;
4178 s->fields = &f;
4179 o.g_out = o.g_out2 = o.g_in1 = o.g_in2 = false;
4180 TCGV_UNUSED_I64(o.out);
4181 TCGV_UNUSED_I64(o.out2);
4182 TCGV_UNUSED_I64(o.in1);
4183 TCGV_UNUSED_I64(o.in2);
4184 TCGV_UNUSED_I64(o.addr1);
4185
4186 /* Implement the instruction. */
4187 if (insn->help_in1) {
4188 insn->help_in1(s, &f, &o);
4189 }
4190 if (insn->help_in2) {
4191 insn->help_in2(s, &f, &o);
4192 }
4193 if (insn->help_prep) {
4194 insn->help_prep(s, &f, &o);
4195 }
4196 if (insn->help_op) {
4197 ret = insn->help_op(s, &o);
4198 }
4199 if (insn->help_wout) {
4200 insn->help_wout(s, &f, &o);
4201 }
4202 if (insn->help_cout) {
4203 insn->help_cout(s, &o);
4204 }
4205
4206 /* Free any temporaries created by the helpers. */
4207 if (!TCGV_IS_UNUSED_I64(o.out) && !o.g_out) {
4208 tcg_temp_free_i64(o.out);
4209 }
4210 if (!TCGV_IS_UNUSED_I64(o.out2) && !o.g_out2) {
4211 tcg_temp_free_i64(o.out2);
4212 }
4213 if (!TCGV_IS_UNUSED_I64(o.in1) && !o.g_in1) {
4214 tcg_temp_free_i64(o.in1);
4215 }
4216 if (!TCGV_IS_UNUSED_I64(o.in2) && !o.g_in2) {
4217 tcg_temp_free_i64(o.in2);
4218 }
4219 if (!TCGV_IS_UNUSED_I64(o.addr1)) {
4220 tcg_temp_free_i64(o.addr1);
4221 }
4222
4223 /* Advance to the next instruction. */
4224 s->pc = s->next_pc;
4225 return ret;
4226 }
4227
4228 static inline void gen_intermediate_code_internal(CPUS390XState *env,
4229 TranslationBlock *tb,
4230 int search_pc)
4231 {
4232 DisasContext dc;
4233 target_ulong pc_start;
4234 uint64_t next_page_start;
4235 uint16_t *gen_opc_end;
4236 int j, lj = -1;
4237 int num_insns, max_insns;
4238 CPUBreakpoint *bp;
4239 ExitStatus status;
4240 bool do_debug;
4241
4242 pc_start = tb->pc;
4243
4244 /* 31-bit mode */
4245 if (!(tb->flags & FLAG_MASK_64)) {
4246 pc_start &= 0x7fffffff;
4247 }
4248
4249 dc.tb = tb;
4250 dc.pc = pc_start;
4251 dc.cc_op = CC_OP_DYNAMIC;
4252 do_debug = dc.singlestep_enabled = env->singlestep_enabled;
4253 dc.is_jmp = DISAS_NEXT;
4254
4255 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
4256
4257 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4258
4259 num_insns = 0;
4260 max_insns = tb->cflags & CF_COUNT_MASK;
4261 if (max_insns == 0) {
4262 max_insns = CF_COUNT_MASK;
4263 }
4264
4265 gen_icount_start();
4266
4267 do {
4268 if (search_pc) {
4269 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4270 if (lj < j) {
4271 lj++;
4272 while (lj < j) {
4273 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4274 }
4275 }
4276 tcg_ctx.gen_opc_pc[lj] = dc.pc;
4277 gen_opc_cc_op[lj] = dc.cc_op;
4278 tcg_ctx.gen_opc_instr_start[lj] = 1;
4279 tcg_ctx.gen_opc_icount[lj] = num_insns;
4280 }
4281 if (++num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
4282 gen_io_start();
4283 }
4284
4285 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4286 tcg_gen_debug_insn_start(dc.pc);
4287 }
4288
4289 status = NO_EXIT;
4290 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
4291 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
4292 if (bp->pc == dc.pc) {
4293 status = EXIT_PC_STALE;
4294 do_debug = true;
4295 break;
4296 }
4297 }
4298 }
4299 if (status == NO_EXIT) {
4300 status = translate_one(env, &dc);
4301 }
4302
4303 /* If we reach a page boundary, are single stepping,
4304 or exhaust instruction count, stop generation. */
4305 if (status == NO_EXIT
4306 && (dc.pc >= next_page_start
4307 || tcg_ctx.gen_opc_ptr >= gen_opc_end
4308 || num_insns >= max_insns
4309 || singlestep
4310 || env->singlestep_enabled)) {
4311 status = EXIT_PC_STALE;
4312 }
4313 } while (status == NO_EXIT);
4314
4315 if (tb->cflags & CF_LAST_IO) {
4316 gen_io_end();
4317 }
4318
4319 switch (status) {
4320 case EXIT_GOTO_TB:
4321 case EXIT_NORETURN:
4322 break;
4323 case EXIT_PC_STALE:
4324 update_psw_addr(&dc);
4325 /* FALLTHRU */
4326 case EXIT_PC_UPDATED:
4327 if (singlestep && dc.cc_op != CC_OP_DYNAMIC) {
4328 gen_op_calc_cc(&dc);
4329 } else {
4330 /* Next TB starts off with CC_OP_DYNAMIC,
4331 so make sure the cc op type is in env */
4332 gen_op_set_cc_op(&dc);
4333 }
4334 if (do_debug) {
4335 gen_exception(EXCP_DEBUG);
4336 } else {
4337 /* Generate the return instruction */
4338 tcg_gen_exit_tb(0);
4339 }
4340 break;
4341 default:
4342 abort();
4343 }
4344
4345 gen_icount_end(tb, num_insns);
4346 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
4347 if (search_pc) {
4348 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4349 lj++;
4350 while (lj <= j) {
4351 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4352 }
4353 } else {
4354 tb->size = dc.pc - pc_start;
4355 tb->icount = num_insns;
4356 }
4357
4358 #if defined(S390X_DEBUG_DISAS)
4359 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
4360 qemu_log("IN: %s\n", lookup_symbol(pc_start));
4361 log_target_disas(env, pc_start, dc.pc - pc_start, 1);
4362 qemu_log("\n");
4363 }
4364 #endif
4365 }
4366
4367 void gen_intermediate_code (CPUS390XState *env, struct TranslationBlock *tb)
4368 {
4369 gen_intermediate_code_internal(env, tb, 0);
4370 }
4371
4372 void gen_intermediate_code_pc (CPUS390XState *env, struct TranslationBlock *tb)
4373 {
4374 gen_intermediate_code_internal(env, tb, 1);
4375 }
4376
4377 void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos)
4378 {
4379 int cc_op;
4380 env->psw.addr = tcg_ctx.gen_opc_pc[pc_pos];
4381 cc_op = gen_opc_cc_op[pc_pos];
4382 if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {
4383 env->cc_op = cc_op;
4384 }
4385 }
Qemu copy for testing