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[qemu.git] / target-s390x / translate.c
1 /*
2 * S/390 translation
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* #define DEBUG_INLINE_BRANCHES */
22 #define S390X_DEBUG_DISAS
23 /* #define S390X_DEBUG_DISAS_VERBOSE */
24
25 #ifdef S390X_DEBUG_DISAS_VERBOSE
26 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
27 #else
28 # define LOG_DISAS(...) do { } while (0)
29 #endif
30
31 #include "cpu.h"
32 #include "disas/disas.h"
33 #include "tcg-op.h"
34 #include "qemu/log.h"
35 #include "qemu/host-utils.h"
36
37 /* global register indexes */
38 static TCGv_ptr cpu_env;
39
40 #include "exec/gen-icount.h"
41 #include "helper.h"
42 #define GEN_HELPER 1
43 #include "helper.h"
44
45
46 /* Information that (most) every instruction needs to manipulate. */
47 typedef struct DisasContext DisasContext;
48 typedef struct DisasInsn DisasInsn;
49 typedef struct DisasFields DisasFields;
50
51 struct DisasContext {
52 struct TranslationBlock *tb;
53 const DisasInsn *insn;
54 DisasFields *fields;
55 uint64_t pc, next_pc;
56 enum cc_op cc_op;
57 bool singlestep_enabled;
58 int is_jmp;
59 };
60
61 /* Information carried about a condition to be evaluated. */
62 typedef struct {
63 TCGCond cond:8;
64 bool is_64;
65 bool g1;
66 bool g2;
67 union {
68 struct { TCGv_i64 a, b; } s64;
69 struct { TCGv_i32 a, b; } s32;
70 } u;
71 } DisasCompare;
72
73 #define DISAS_EXCP 4
74
75 static void gen_op_calc_cc(DisasContext *s);
76
77 #ifdef DEBUG_INLINE_BRANCHES
78 static uint64_t inline_branch_hit[CC_OP_MAX];
79 static uint64_t inline_branch_miss[CC_OP_MAX];
80 #endif
81
82 static inline void debug_insn(uint64_t insn)
83 {
84 LOG_DISAS("insn: 0x%" PRIx64 "\n", insn);
85 }
86
87 static inline uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
88 {
89 if (!(s->tb->flags & FLAG_MASK_64)) {
90 if (s->tb->flags & FLAG_MASK_32) {
91 return pc | 0x80000000;
92 }
93 }
94 return pc;
95 }
96
97 void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
98 int flags)
99 {
100 int i;
101
102 if (env->cc_op > 3) {
103 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
104 env->psw.mask, env->psw.addr, cc_name(env->cc_op));
105 } else {
106 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
107 env->psw.mask, env->psw.addr, env->cc_op);
108 }
109
110 for (i = 0; i < 16; i++) {
111 cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
112 if ((i % 4) == 3) {
113 cpu_fprintf(f, "\n");
114 } else {
115 cpu_fprintf(f, " ");
116 }
117 }
118
119 for (i = 0; i < 16; i++) {
120 cpu_fprintf(f, "F%02d=%016" PRIx64, i, env->fregs[i].ll);
121 if ((i % 4) == 3) {
122 cpu_fprintf(f, "\n");
123 } else {
124 cpu_fprintf(f, " ");
125 }
126 }
127
128 #ifndef CONFIG_USER_ONLY
129 for (i = 0; i < 16; i++) {
130 cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
131 if ((i % 4) == 3) {
132 cpu_fprintf(f, "\n");
133 } else {
134 cpu_fprintf(f, " ");
135 }
136 }
137 #endif
138
139 #ifdef DEBUG_INLINE_BRANCHES
140 for (i = 0; i < CC_OP_MAX; i++) {
141 cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
142 inline_branch_miss[i], inline_branch_hit[i]);
143 }
144 #endif
145
146 cpu_fprintf(f, "\n");
147 }
148
149 static TCGv_i64 psw_addr;
150 static TCGv_i64 psw_mask;
151
152 static TCGv_i32 cc_op;
153 static TCGv_i64 cc_src;
154 static TCGv_i64 cc_dst;
155 static TCGv_i64 cc_vr;
156
157 static char cpu_reg_names[32][4];
158 static TCGv_i64 regs[16];
159 static TCGv_i64 fregs[16];
160
161 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
162
163 void s390x_translate_init(void)
164 {
165 int i;
166
167 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
168 psw_addr = tcg_global_mem_new_i64(TCG_AREG0,
169 offsetof(CPUS390XState, psw.addr),
170 "psw_addr");
171 psw_mask = tcg_global_mem_new_i64(TCG_AREG0,
172 offsetof(CPUS390XState, psw.mask),
173 "psw_mask");
174
175 cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUS390XState, cc_op),
176 "cc_op");
177 cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_src),
178 "cc_src");
179 cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_dst),
180 "cc_dst");
181 cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_vr),
182 "cc_vr");
183
184 for (i = 0; i < 16; i++) {
185 snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i);
186 regs[i] = tcg_global_mem_new(TCG_AREG0,
187 offsetof(CPUS390XState, regs[i]),
188 cpu_reg_names[i]);
189 }
190
191 for (i = 0; i < 16; i++) {
192 snprintf(cpu_reg_names[i + 16], sizeof(cpu_reg_names[0]), "f%d", i);
193 fregs[i] = tcg_global_mem_new(TCG_AREG0,
194 offsetof(CPUS390XState, fregs[i].d),
195 cpu_reg_names[i + 16]);
196 }
197
198 /* register helpers */
199 #define GEN_HELPER 2
200 #include "helper.h"
201 }
202
203 static inline TCGv_i64 load_reg(int reg)
204 {
205 TCGv_i64 r = tcg_temp_new_i64();
206 tcg_gen_mov_i64(r, regs[reg]);
207 return r;
208 }
209
210 static inline TCGv_i64 load_freg(int reg)
211 {
212 TCGv_i64 r = tcg_temp_new_i64();
213 tcg_gen_mov_i64(r, fregs[reg]);
214 return r;
215 }
216
217 static inline TCGv_i32 load_freg32(int reg)
218 {
219 TCGv_i32 r = tcg_temp_new_i32();
220 #if HOST_LONG_BITS == 32
221 tcg_gen_mov_i32(r, TCGV_HIGH(fregs[reg]));
222 #else
223 tcg_gen_shri_i64(MAKE_TCGV_I64(GET_TCGV_I32(r)), fregs[reg], 32);
224 #endif
225 return r;
226 }
227
228 static inline TCGv_i64 load_freg32_i64(int reg)
229 {
230 TCGv_i64 r = tcg_temp_new_i64();
231 tcg_gen_shri_i64(r, fregs[reg], 32);
232 return r;
233 }
234
235 static inline TCGv_i32 load_reg32(int reg)
236 {
237 TCGv_i32 r = tcg_temp_new_i32();
238 tcg_gen_trunc_i64_i32(r, regs[reg]);
239 return r;
240 }
241
242 static inline TCGv_i64 load_reg32_i64(int reg)
243 {
244 TCGv_i64 r = tcg_temp_new_i64();
245 tcg_gen_ext32s_i64(r, regs[reg]);
246 return r;
247 }
248
249 static inline void store_reg(int reg, TCGv_i64 v)
250 {
251 tcg_gen_mov_i64(regs[reg], v);
252 }
253
254 static inline void store_freg(int reg, TCGv_i64 v)
255 {
256 tcg_gen_mov_i64(fregs[reg], v);
257 }
258
259 static inline void store_reg32(int reg, TCGv_i32 v)
260 {
261 /* 32 bit register writes keep the upper half */
262 #if HOST_LONG_BITS == 32
263 tcg_gen_mov_i32(TCGV_LOW(regs[reg]), v);
264 #else
265 tcg_gen_deposit_i64(regs[reg], regs[reg],
266 MAKE_TCGV_I64(GET_TCGV_I32(v)), 0, 32);
267 #endif
268 }
269
270 static inline void store_reg32_i64(int reg, TCGv_i64 v)
271 {
272 /* 32 bit register writes keep the upper half */
273 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
274 }
275
276 static inline void store_reg32h_i64(int reg, TCGv_i64 v)
277 {
278 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 32, 32);
279 }
280
281 static inline void store_reg16(int reg, TCGv_i32 v)
282 {
283 /* 16 bit register writes keep the upper bytes */
284 #if HOST_LONG_BITS == 32
285 tcg_gen_deposit_i32(TCGV_LOW(regs[reg]), TCGV_LOW(regs[reg]), v, 0, 16);
286 #else
287 tcg_gen_deposit_i64(regs[reg], regs[reg],
288 MAKE_TCGV_I64(GET_TCGV_I32(v)), 0, 16);
289 #endif
290 }
291
292 static inline void store_freg32(int reg, TCGv_i32 v)
293 {
294 /* 32 bit register writes keep the lower half */
295 #if HOST_LONG_BITS == 32
296 tcg_gen_mov_i32(TCGV_HIGH(fregs[reg]), v);
297 #else
298 tcg_gen_deposit_i64(fregs[reg], fregs[reg],
299 MAKE_TCGV_I64(GET_TCGV_I32(v)), 32, 32);
300 #endif
301 }
302
303 static inline void store_freg32_i64(int reg, TCGv_i64 v)
304 {
305 tcg_gen_deposit_i64(fregs[reg], fregs[reg], v, 32, 32);
306 }
307
308 static inline void return_low128(TCGv_i64 dest)
309 {
310 tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl));
311 }
312
313 static inline void update_psw_addr(DisasContext *s)
314 {
315 /* psw.addr */
316 tcg_gen_movi_i64(psw_addr, s->pc);
317 }
318
319 static inline void potential_page_fault(DisasContext *s)
320 {
321 #ifndef CONFIG_USER_ONLY
322 update_psw_addr(s);
323 gen_op_calc_cc(s);
324 #endif
325 }
326
327 static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
328 {
329 return (uint64_t)cpu_lduw_code(env, pc);
330 }
331
332 static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
333 {
334 return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
335 }
336
337 static inline uint64_t ld_code6(CPUS390XState *env, uint64_t pc)
338 {
339 return (ld_code2(env, pc) << 32) | ld_code4(env, pc + 2);
340 }
341
342 static inline int get_mem_index(DisasContext *s)
343 {
344 switch (s->tb->flags & FLAG_MASK_ASC) {
345 case PSW_ASC_PRIMARY >> 32:
346 return 0;
347 case PSW_ASC_SECONDARY >> 32:
348 return 1;
349 case PSW_ASC_HOME >> 32:
350 return 2;
351 default:
352 tcg_abort();
353 break;
354 }
355 }
356
357 static void gen_exception(int excp)
358 {
359 TCGv_i32 tmp = tcg_const_i32(excp);
360 gen_helper_exception(cpu_env, tmp);
361 tcg_temp_free_i32(tmp);
362 }
363
364 static void gen_program_exception(DisasContext *s, int code)
365 {
366 TCGv_i32 tmp;
367
368 /* Remember what pgm exeption this was. */
369 tmp = tcg_const_i32(code);
370 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
371 tcg_temp_free_i32(tmp);
372
373 tmp = tcg_const_i32(s->next_pc - s->pc);
374 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen));
375 tcg_temp_free_i32(tmp);
376
377 /* Advance past instruction. */
378 s->pc = s->next_pc;
379 update_psw_addr(s);
380
381 /* Save off cc. */
382 gen_op_calc_cc(s);
383
384 /* Trigger exception. */
385 gen_exception(EXCP_PGM);
386
387 /* End TB here. */
388 s->is_jmp = DISAS_EXCP;
389 }
390
391 static inline void gen_illegal_opcode(DisasContext *s)
392 {
393 gen_program_exception(s, PGM_SPECIFICATION);
394 }
395
396 static inline void check_privileged(DisasContext *s)
397 {
398 if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
399 gen_program_exception(s, PGM_PRIVILEGED);
400 }
401 }
402
403 static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
404 {
405 TCGv_i64 tmp;
406
407 /* 31-bitify the immediate part; register contents are dealt with below */
408 if (!(s->tb->flags & FLAG_MASK_64)) {
409 d2 &= 0x7fffffffUL;
410 }
411
412 if (x2) {
413 if (d2) {
414 tmp = tcg_const_i64(d2);
415 tcg_gen_add_i64(tmp, tmp, regs[x2]);
416 } else {
417 tmp = load_reg(x2);
418 }
419 if (b2) {
420 tcg_gen_add_i64(tmp, tmp, regs[b2]);
421 }
422 } else if (b2) {
423 if (d2) {
424 tmp = tcg_const_i64(d2);
425 tcg_gen_add_i64(tmp, tmp, regs[b2]);
426 } else {
427 tmp = load_reg(b2);
428 }
429 } else {
430 tmp = tcg_const_i64(d2);
431 }
432
433 /* 31-bit mode mask if there are values loaded from registers */
434 if (!(s->tb->flags & FLAG_MASK_64) && (x2 || b2)) {
435 tcg_gen_andi_i64(tmp, tmp, 0x7fffffffUL);
436 }
437
438 return tmp;
439 }
440
441 static void gen_op_movi_cc(DisasContext *s, uint32_t val)
442 {
443 s->cc_op = CC_OP_CONST0 + val;
444 }
445
446 static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
447 {
448 tcg_gen_discard_i64(cc_src);
449 tcg_gen_mov_i64(cc_dst, dst);
450 tcg_gen_discard_i64(cc_vr);
451 s->cc_op = op;
452 }
453
454 static void gen_op_update1_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 dst)
455 {
456 tcg_gen_discard_i64(cc_src);
457 tcg_gen_extu_i32_i64(cc_dst, dst);
458 tcg_gen_discard_i64(cc_vr);
459 s->cc_op = op;
460 }
461
462 static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
463 TCGv_i64 dst)
464 {
465 tcg_gen_mov_i64(cc_src, src);
466 tcg_gen_mov_i64(cc_dst, dst);
467 tcg_gen_discard_i64(cc_vr);
468 s->cc_op = op;
469 }
470
471 static void gen_op_update2_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src,
472 TCGv_i32 dst)
473 {
474 tcg_gen_extu_i32_i64(cc_src, src);
475 tcg_gen_extu_i32_i64(cc_dst, dst);
476 tcg_gen_discard_i64(cc_vr);
477 s->cc_op = op;
478 }
479
480 static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
481 TCGv_i64 dst, TCGv_i64 vr)
482 {
483 tcg_gen_mov_i64(cc_src, src);
484 tcg_gen_mov_i64(cc_dst, dst);
485 tcg_gen_mov_i64(cc_vr, vr);
486 s->cc_op = op;
487 }
488
489 static inline void set_cc_nz_u32(DisasContext *s, TCGv_i32 val)
490 {
491 gen_op_update1_cc_i32(s, CC_OP_NZ, val);
492 }
493
494 static inline void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
495 {
496 gen_op_update1_cc_i64(s, CC_OP_NZ, val);
497 }
498
499 static inline void cmp_32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
500 enum cc_op cond)
501 {
502 gen_op_update2_cc_i32(s, cond, v1, v2);
503 }
504
505 static inline void cmp_64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
506 enum cc_op cond)
507 {
508 gen_op_update2_cc_i64(s, cond, v1, v2);
509 }
510
511 static inline void cmp_s32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
512 {
513 cmp_32(s, v1, v2, CC_OP_LTGT_32);
514 }
515
516 static inline void cmp_u32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
517 {
518 cmp_32(s, v1, v2, CC_OP_LTUGTU_32);
519 }
520
521 static inline void cmp_s32c(DisasContext *s, TCGv_i32 v1, int32_t v2)
522 {
523 /* XXX optimize for the constant? put it in s? */
524 TCGv_i32 tmp = tcg_const_i32(v2);
525 cmp_32(s, v1, tmp, CC_OP_LTGT_32);
526 tcg_temp_free_i32(tmp);
527 }
528
529 static inline void cmp_u32c(DisasContext *s, TCGv_i32 v1, uint32_t v2)
530 {
531 TCGv_i32 tmp = tcg_const_i32(v2);
532 cmp_32(s, v1, tmp, CC_OP_LTUGTU_32);
533 tcg_temp_free_i32(tmp);
534 }
535
536 static inline void cmp_s64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
537 {
538 cmp_64(s, v1, v2, CC_OP_LTGT_64);
539 }
540
541 static inline void cmp_u64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
542 {
543 cmp_64(s, v1, v2, CC_OP_LTUGTU_64);
544 }
545
546 static inline void cmp_s64c(DisasContext *s, TCGv_i64 v1, int64_t v2)
547 {
548 TCGv_i64 tmp = tcg_const_i64(v2);
549 cmp_s64(s, v1, tmp);
550 tcg_temp_free_i64(tmp);
551 }
552
553 static inline void cmp_u64c(DisasContext *s, TCGv_i64 v1, uint64_t v2)
554 {
555 TCGv_i64 tmp = tcg_const_i64(v2);
556 cmp_u64(s, v1, tmp);
557 tcg_temp_free_i64(tmp);
558 }
559
560 static inline void set_cc_s32(DisasContext *s, TCGv_i32 val)
561 {
562 gen_op_update1_cc_i32(s, CC_OP_LTGT0_32, val);
563 }
564
565 static inline void set_cc_s64(DisasContext *s, TCGv_i64 val)
566 {
567 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, val);
568 }
569
570 static void set_cc_cmp_f32_i64(DisasContext *s, TCGv_i32 v1, TCGv_i64 v2)
571 {
572 tcg_gen_extu_i32_i64(cc_src, v1);
573 tcg_gen_mov_i64(cc_dst, v2);
574 tcg_gen_discard_i64(cc_vr);
575 s->cc_op = CC_OP_LTGT_F32;
576 }
577
578 static void gen_set_cc_nz_f32(DisasContext *s, TCGv_i32 v1)
579 {
580 gen_op_update1_cc_i32(s, CC_OP_NZ_F32, v1);
581 }
582
583 /* CC value is in env->cc_op */
584 static inline void set_cc_static(DisasContext *s)
585 {
586 tcg_gen_discard_i64(cc_src);
587 tcg_gen_discard_i64(cc_dst);
588 tcg_gen_discard_i64(cc_vr);
589 s->cc_op = CC_OP_STATIC;
590 }
591
592 static inline void gen_op_set_cc_op(DisasContext *s)
593 {
594 if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
595 tcg_gen_movi_i32(cc_op, s->cc_op);
596 }
597 }
598
599 static inline void gen_update_cc_op(DisasContext *s)
600 {
601 gen_op_set_cc_op(s);
602 }
603
604 /* calculates cc into cc_op */
605 static void gen_op_calc_cc(DisasContext *s)
606 {
607 TCGv_i32 local_cc_op = tcg_const_i32(s->cc_op);
608 TCGv_i64 dummy = tcg_const_i64(0);
609
610 switch (s->cc_op) {
611 case CC_OP_CONST0:
612 case CC_OP_CONST1:
613 case CC_OP_CONST2:
614 case CC_OP_CONST3:
615 /* s->cc_op is the cc value */
616 tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
617 break;
618 case CC_OP_STATIC:
619 /* env->cc_op already is the cc value */
620 break;
621 case CC_OP_NZ:
622 case CC_OP_ABS_64:
623 case CC_OP_NABS_64:
624 case CC_OP_ABS_32:
625 case CC_OP_NABS_32:
626 case CC_OP_LTGT0_32:
627 case CC_OP_LTGT0_64:
628 case CC_OP_COMP_32:
629 case CC_OP_COMP_64:
630 case CC_OP_NZ_F32:
631 case CC_OP_NZ_F64:
632 /* 1 argument */
633 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dummy);
634 break;
635 case CC_OP_ICM:
636 case CC_OP_LTGT_32:
637 case CC_OP_LTGT_64:
638 case CC_OP_LTUGTU_32:
639 case CC_OP_LTUGTU_64:
640 case CC_OP_TM_32:
641 case CC_OP_TM_64:
642 case CC_OP_LTGT_F32:
643 case CC_OP_LTGT_F64:
644 case CC_OP_SLA_32:
645 case CC_OP_SLA_64:
646 /* 2 arguments */
647 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
648 break;
649 case CC_OP_ADD_64:
650 case CC_OP_ADDU_64:
651 case CC_OP_ADDC_64:
652 case CC_OP_SUB_64:
653 case CC_OP_SUBU_64:
654 case CC_OP_SUBB_64:
655 case CC_OP_ADD_32:
656 case CC_OP_ADDU_32:
657 case CC_OP_ADDC_32:
658 case CC_OP_SUB_32:
659 case CC_OP_SUBU_32:
660 case CC_OP_SUBB_32:
661 /* 3 arguments */
662 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc_vr);
663 break;
664 case CC_OP_DYNAMIC:
665 /* unknown operation - assume 3 arguments and cc_op in env */
666 gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr);
667 break;
668 default:
669 tcg_abort();
670 }
671
672 tcg_temp_free_i32(local_cc_op);
673 tcg_temp_free_i64(dummy);
674
675 /* We now have cc in cc_op as constant */
676 set_cc_static(s);
677 }
678
679 static inline void decode_rr(DisasContext *s, uint64_t insn, int *r1, int *r2)
680 {
681 debug_insn(insn);
682
683 *r1 = (insn >> 4) & 0xf;
684 *r2 = insn & 0xf;
685 }
686
687 static inline TCGv_i64 decode_rx(DisasContext *s, uint64_t insn, int *r1,
688 int *x2, int *b2, int *d2)
689 {
690 debug_insn(insn);
691
692 *r1 = (insn >> 20) & 0xf;
693 *x2 = (insn >> 16) & 0xf;
694 *b2 = (insn >> 12) & 0xf;
695 *d2 = insn & 0xfff;
696
697 return get_address(s, *x2, *b2, *d2);
698 }
699
700 static inline void decode_rs(DisasContext *s, uint64_t insn, int *r1, int *r3,
701 int *b2, int *d2)
702 {
703 debug_insn(insn);
704
705 *r1 = (insn >> 20) & 0xf;
706 /* aka m3 */
707 *r3 = (insn >> 16) & 0xf;
708 *b2 = (insn >> 12) & 0xf;
709 *d2 = insn & 0xfff;
710 }
711
712 static inline TCGv_i64 decode_si(DisasContext *s, uint64_t insn, int *i2,
713 int *b1, int *d1)
714 {
715 debug_insn(insn);
716
717 *i2 = (insn >> 16) & 0xff;
718 *b1 = (insn >> 12) & 0xf;
719 *d1 = insn & 0xfff;
720
721 return get_address(s, 0, *b1, *d1);
722 }
723
724 static int use_goto_tb(DisasContext *s, uint64_t dest)
725 {
726 /* NOTE: we handle the case where the TB spans two pages here */
727 return (((dest & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK)
728 || (dest & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK))
729 && !s->singlestep_enabled
730 && !(s->tb->cflags & CF_LAST_IO));
731 }
732
733 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong pc)
734 {
735 gen_update_cc_op(s);
736
737 if (use_goto_tb(s, pc)) {
738 tcg_gen_goto_tb(tb_num);
739 tcg_gen_movi_i64(psw_addr, pc);
740 tcg_gen_exit_tb((tcg_target_long)s->tb + tb_num);
741 } else {
742 /* jump to another page: currently not optimized */
743 tcg_gen_movi_i64(psw_addr, pc);
744 tcg_gen_exit_tb(0);
745 }
746 }
747
748 static inline void account_noninline_branch(DisasContext *s, int cc_op)
749 {
750 #ifdef DEBUG_INLINE_BRANCHES
751 inline_branch_miss[cc_op]++;
752 #endif
753 }
754
755 static inline void account_inline_branch(DisasContext *s, int cc_op)
756 {
757 #ifdef DEBUG_INLINE_BRANCHES
758 inline_branch_hit[cc_op]++;
759 #endif
760 }
761
762 /* Table of mask values to comparison codes, given a comparison as input.
763 For a true comparison CC=3 will never be set, but we treat this
764 conservatively for possible use when CC=3 indicates overflow. */
765 static const TCGCond ltgt_cond[16] = {
766 TCG_COND_NEVER, TCG_COND_NEVER, /* | | | x */
767 TCG_COND_GT, TCG_COND_NEVER, /* | | GT | x */
768 TCG_COND_LT, TCG_COND_NEVER, /* | LT | | x */
769 TCG_COND_NE, TCG_COND_NEVER, /* | LT | GT | x */
770 TCG_COND_EQ, TCG_COND_NEVER, /* EQ | | | x */
771 TCG_COND_GE, TCG_COND_NEVER, /* EQ | | GT | x */
772 TCG_COND_LE, TCG_COND_NEVER, /* EQ | LT | | x */
773 TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | LT | GT | x */
774 };
775
776 /* Table of mask values to comparison codes, given a logic op as input.
777 For such, only CC=0 and CC=1 should be possible. */
778 static const TCGCond nz_cond[16] = {
779 /* | | x | x */
780 TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER,
781 /* | NE | x | x */
782 TCG_COND_NE, TCG_COND_NE, TCG_COND_NE, TCG_COND_NE,
783 /* EQ | | x | x */
784 TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ,
785 /* EQ | NE | x | x */
786 TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS,
787 };
788
789 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
790 details required to generate a TCG comparison. */
791 static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
792 {
793 TCGCond cond;
794 enum cc_op old_cc_op = s->cc_op;
795
796 if (mask == 15 || mask == 0) {
797 c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER);
798 c->u.s32.a = cc_op;
799 c->u.s32.b = cc_op;
800 c->g1 = c->g2 = true;
801 c->is_64 = false;
802 return;
803 }
804
805 /* Find the TCG condition for the mask + cc op. */
806 switch (old_cc_op) {
807 case CC_OP_LTGT0_32:
808 case CC_OP_LTGT0_64:
809 case CC_OP_LTGT_32:
810 case CC_OP_LTGT_64:
811 cond = ltgt_cond[mask];
812 if (cond == TCG_COND_NEVER) {
813 goto do_dynamic;
814 }
815 account_inline_branch(s, old_cc_op);
816 break;
817
818 case CC_OP_LTUGTU_32:
819 case CC_OP_LTUGTU_64:
820 cond = tcg_unsigned_cond(ltgt_cond[mask]);
821 if (cond == TCG_COND_NEVER) {
822 goto do_dynamic;
823 }
824 account_inline_branch(s, old_cc_op);
825 break;
826
827 case CC_OP_NZ:
828 cond = nz_cond[mask];
829 if (cond == TCG_COND_NEVER) {
830 goto do_dynamic;
831 }
832 account_inline_branch(s, old_cc_op);
833 break;
834
835 case CC_OP_TM_32:
836 case CC_OP_TM_64:
837 switch (mask) {
838 case 8:
839 cond = TCG_COND_EQ;
840 break;
841 case 4 | 2 | 1:
842 cond = TCG_COND_NE;
843 break;
844 default:
845 goto do_dynamic;
846 }
847 account_inline_branch(s, old_cc_op);
848 break;
849
850 case CC_OP_ICM:
851 switch (mask) {
852 case 8:
853 cond = TCG_COND_EQ;
854 break;
855 case 4 | 2 | 1:
856 case 4 | 2:
857 cond = TCG_COND_NE;
858 break;
859 default:
860 goto do_dynamic;
861 }
862 account_inline_branch(s, old_cc_op);
863 break;
864
865 default:
866 do_dynamic:
867 /* Calculate cc value. */
868 gen_op_calc_cc(s);
869 /* FALLTHRU */
870
871 case CC_OP_STATIC:
872 /* Jump based on CC. We'll load up the real cond below;
873 the assignment here merely avoids a compiler warning. */
874 account_noninline_branch(s, old_cc_op);
875 old_cc_op = CC_OP_STATIC;
876 cond = TCG_COND_NEVER;
877 break;
878 }
879
880 /* Load up the arguments of the comparison. */
881 c->is_64 = true;
882 c->g1 = c->g2 = false;
883 switch (old_cc_op) {
884 case CC_OP_LTGT0_32:
885 c->is_64 = false;
886 c->u.s32.a = tcg_temp_new_i32();
887 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_dst);
888 c->u.s32.b = tcg_const_i32(0);
889 break;
890 case CC_OP_LTGT_32:
891 case CC_OP_LTUGTU_32:
892 c->is_64 = false;
893 c->u.s32.a = tcg_temp_new_i32();
894 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_src);
895 c->u.s32.b = tcg_temp_new_i32();
896 tcg_gen_trunc_i64_i32(c->u.s32.b, cc_dst);
897 break;
898
899 case CC_OP_LTGT0_64:
900 case CC_OP_NZ:
901 c->u.s64.a = cc_dst;
902 c->u.s64.b = tcg_const_i64(0);
903 c->g1 = true;
904 break;
905 case CC_OP_LTGT_64:
906 case CC_OP_LTUGTU_64:
907 c->u.s64.a = cc_src;
908 c->u.s64.b = cc_dst;
909 c->g1 = c->g2 = true;
910 break;
911
912 case CC_OP_TM_32:
913 case CC_OP_TM_64:
914 case CC_OP_ICM:
915 c->u.s64.a = tcg_temp_new_i64();
916 c->u.s64.b = tcg_const_i64(0);
917 tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
918 break;
919
920 case CC_OP_STATIC:
921 c->is_64 = false;
922 c->u.s32.a = cc_op;
923 c->g1 = true;
924 switch (mask) {
925 case 0x8 | 0x4 | 0x2: /* cc != 3 */
926 cond = TCG_COND_NE;
927 c->u.s32.b = tcg_const_i32(3);
928 break;
929 case 0x8 | 0x4 | 0x1: /* cc != 2 */
930 cond = TCG_COND_NE;
931 c->u.s32.b = tcg_const_i32(2);
932 break;
933 case 0x8 | 0x2 | 0x1: /* cc != 1 */
934 cond = TCG_COND_NE;
935 c->u.s32.b = tcg_const_i32(1);
936 break;
937 case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
938 cond = TCG_COND_EQ;
939 c->g1 = false;
940 c->u.s32.a = tcg_temp_new_i32();
941 c->u.s32.b = tcg_const_i32(0);
942 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
943 break;
944 case 0x8 | 0x4: /* cc < 2 */
945 cond = TCG_COND_LTU;
946 c->u.s32.b = tcg_const_i32(2);
947 break;
948 case 0x8: /* cc == 0 */
949 cond = TCG_COND_EQ;
950 c->u.s32.b = tcg_const_i32(0);
951 break;
952 case 0x4 | 0x2 | 0x1: /* cc != 0 */
953 cond = TCG_COND_NE;
954 c->u.s32.b = tcg_const_i32(0);
955 break;
956 case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
957 cond = TCG_COND_NE;
958 c->g1 = false;
959 c->u.s32.a = tcg_temp_new_i32();
960 c->u.s32.b = tcg_const_i32(0);
961 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
962 break;
963 case 0x4: /* cc == 1 */
964 cond = TCG_COND_EQ;
965 c->u.s32.b = tcg_const_i32(1);
966 break;
967 case 0x2 | 0x1: /* cc > 1 */
968 cond = TCG_COND_GTU;
969 c->u.s32.b = tcg_const_i32(1);
970 break;
971 case 0x2: /* cc == 2 */
972 cond = TCG_COND_EQ;
973 c->u.s32.b = tcg_const_i32(2);
974 break;
975 case 0x1: /* cc == 3 */
976 cond = TCG_COND_EQ;
977 c->u.s32.b = tcg_const_i32(3);
978 break;
979 default:
980 /* CC is masked by something else: (8 >> cc) & mask. */
981 cond = TCG_COND_NE;
982 c->g1 = false;
983 c->u.s32.a = tcg_const_i32(8);
984 c->u.s32.b = tcg_const_i32(0);
985 tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op);
986 tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
987 break;
988 }
989 break;
990
991 default:
992 abort();
993 }
994 c->cond = cond;
995 }
996
997 static void free_compare(DisasCompare *c)
998 {
999 if (!c->g1) {
1000 if (c->is_64) {
1001 tcg_temp_free_i64(c->u.s64.a);
1002 } else {
1003 tcg_temp_free_i32(c->u.s32.a);
1004 }
1005 }
1006 if (!c->g2) {
1007 if (c->is_64) {
1008 tcg_temp_free_i64(c->u.s64.b);
1009 } else {
1010 tcg_temp_free_i32(c->u.s32.b);
1011 }
1012 }
1013 }
1014
1015 static void disas_e3(CPUS390XState *env, DisasContext* s, int op, int r1,
1016 int x2, int b2, int d2)
1017 {
1018 TCGv_i64 addr, tmp2;
1019 TCGv_i32 tmp32_1;
1020
1021 LOG_DISAS("disas_e3: op 0x%x r1 %d x2 %d b2 %d d2 %d\n",
1022 op, r1, x2, b2, d2);
1023 addr = get_address(s, x2, b2, d2);
1024 switch (op) {
1025 case 0xf: /* LRVG R1,D2(X2,B2) [RXE] */
1026 tmp2 = tcg_temp_new_i64();
1027 tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1028 tcg_gen_bswap64_i64(tmp2, tmp2);
1029 store_reg(r1, tmp2);
1030 tcg_temp_free_i64(tmp2);
1031 break;
1032 case 0x17: /* LLGT R1,D2(X2,B2) [RXY] */
1033 tmp2 = tcg_temp_new_i64();
1034 tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1035 tcg_gen_andi_i64(tmp2, tmp2, 0x7fffffffULL);
1036 store_reg(r1, tmp2);
1037 tcg_temp_free_i64(tmp2);
1038 break;
1039 case 0x1e: /* LRV R1,D2(X2,B2) [RXY] */
1040 tmp2 = tcg_temp_new_i64();
1041 tmp32_1 = tcg_temp_new_i32();
1042 tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1043 tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
1044 tcg_temp_free_i64(tmp2);
1045 tcg_gen_bswap32_i32(tmp32_1, tmp32_1);
1046 store_reg32(r1, tmp32_1);
1047 tcg_temp_free_i32(tmp32_1);
1048 break;
1049 case 0x1f: /* LRVH R1,D2(X2,B2) [RXY] */
1050 tmp2 = tcg_temp_new_i64();
1051 tmp32_1 = tcg_temp_new_i32();
1052 tcg_gen_qemu_ld16u(tmp2, addr, get_mem_index(s));
1053 tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
1054 tcg_temp_free_i64(tmp2);
1055 tcg_gen_bswap16_i32(tmp32_1, tmp32_1);
1056 store_reg16(r1, tmp32_1);
1057 tcg_temp_free_i32(tmp32_1);
1058 break;
1059 case 0x3e: /* STRV R1,D2(X2,B2) [RXY] */
1060 tmp32_1 = load_reg32(r1);
1061 tmp2 = tcg_temp_new_i64();
1062 tcg_gen_bswap32_i32(tmp32_1, tmp32_1);
1063 tcg_gen_extu_i32_i64(tmp2, tmp32_1);
1064 tcg_temp_free_i32(tmp32_1);
1065 tcg_gen_qemu_st32(tmp2, addr, get_mem_index(s));
1066 tcg_temp_free_i64(tmp2);
1067 break;
1068 default:
1069 LOG_DISAS("illegal e3 operation 0x%x\n", op);
1070 gen_illegal_opcode(s);
1071 break;
1072 }
1073 tcg_temp_free_i64(addr);
1074 }
1075
1076 #ifndef CONFIG_USER_ONLY
1077 static void disas_e5(CPUS390XState *env, DisasContext* s, uint64_t insn)
1078 {
1079 TCGv_i64 tmp, tmp2;
1080 int op = (insn >> 32) & 0xff;
1081
1082 tmp = get_address(s, 0, (insn >> 28) & 0xf, (insn >> 16) & 0xfff);
1083 tmp2 = get_address(s, 0, (insn >> 12) & 0xf, insn & 0xfff);
1084
1085 LOG_DISAS("disas_e5: insn %" PRIx64 "\n", insn);
1086 switch (op) {
1087 case 0x01: /* TPROT D1(B1),D2(B2) [SSE] */
1088 /* Test Protection */
1089 potential_page_fault(s);
1090 gen_helper_tprot(cc_op, tmp, tmp2);
1091 set_cc_static(s);
1092 break;
1093 default:
1094 LOG_DISAS("illegal e5 operation 0x%x\n", op);
1095 gen_illegal_opcode(s);
1096 break;
1097 }
1098
1099 tcg_temp_free_i64(tmp);
1100 tcg_temp_free_i64(tmp2);
1101 }
1102 #endif
1103
1104 static void disas_eb(CPUS390XState *env, DisasContext *s, int op, int r1,
1105 int r3, int b2, int d2)
1106 {
1107 TCGv_i64 tmp;
1108 TCGv_i32 tmp32_1, tmp32_2;
1109
1110 LOG_DISAS("disas_eb: op 0x%x r1 %d r3 %d b2 %d d2 0x%x\n",
1111 op, r1, r3, b2, d2);
1112 switch (op) {
1113 case 0x2c: /* STCMH R1,M3,D2(B2) [RSY] */
1114 tmp = get_address(s, 0, b2, d2);
1115 tmp32_1 = tcg_const_i32(r1);
1116 tmp32_2 = tcg_const_i32(r3);
1117 potential_page_fault(s);
1118 gen_helper_stcmh(cpu_env, tmp32_1, tmp, tmp32_2);
1119 tcg_temp_free_i64(tmp);
1120 tcg_temp_free_i32(tmp32_1);
1121 tcg_temp_free_i32(tmp32_2);
1122 break;
1123 #ifndef CONFIG_USER_ONLY
1124 case 0x2f: /* LCTLG R1,R3,D2(B2) [RSE] */
1125 /* Load Control */
1126 check_privileged(s);
1127 tmp = get_address(s, 0, b2, d2);
1128 tmp32_1 = tcg_const_i32(r1);
1129 tmp32_2 = tcg_const_i32(r3);
1130 potential_page_fault(s);
1131 gen_helper_lctlg(cpu_env, tmp32_1, tmp, tmp32_2);
1132 tcg_temp_free_i64(tmp);
1133 tcg_temp_free_i32(tmp32_1);
1134 tcg_temp_free_i32(tmp32_2);
1135 break;
1136 case 0x25: /* STCTG R1,R3,D2(B2) [RSE] */
1137 /* Store Control */
1138 check_privileged(s);
1139 tmp = get_address(s, 0, b2, d2);
1140 tmp32_1 = tcg_const_i32(r1);
1141 tmp32_2 = tcg_const_i32(r3);
1142 potential_page_fault(s);
1143 gen_helper_stctg(cpu_env, tmp32_1, tmp, tmp32_2);
1144 tcg_temp_free_i64(tmp);
1145 tcg_temp_free_i32(tmp32_1);
1146 tcg_temp_free_i32(tmp32_2);
1147 break;
1148 #endif
1149 case 0x30: /* CSG R1,R3,D2(B2) [RSY] */
1150 tmp = get_address(s, 0, b2, d2);
1151 tmp32_1 = tcg_const_i32(r1);
1152 tmp32_2 = tcg_const_i32(r3);
1153 potential_page_fault(s);
1154 /* XXX rewrite in tcg */
1155 gen_helper_csg(cc_op, cpu_env, tmp32_1, tmp, tmp32_2);
1156 set_cc_static(s);
1157 tcg_temp_free_i64(tmp);
1158 tcg_temp_free_i32(tmp32_1);
1159 tcg_temp_free_i32(tmp32_2);
1160 break;
1161 case 0x3e: /* CDSG R1,R3,D2(B2) [RSY] */
1162 tmp = get_address(s, 0, b2, d2);
1163 tmp32_1 = tcg_const_i32(r1);
1164 tmp32_2 = tcg_const_i32(r3);
1165 potential_page_fault(s);
1166 /* XXX rewrite in tcg */
1167 gen_helper_cdsg(cc_op, cpu_env, tmp32_1, tmp, tmp32_2);
1168 set_cc_static(s);
1169 tcg_temp_free_i64(tmp);
1170 tcg_temp_free_i32(tmp32_1);
1171 tcg_temp_free_i32(tmp32_2);
1172 break;
1173 default:
1174 LOG_DISAS("illegal eb operation 0x%x\n", op);
1175 gen_illegal_opcode(s);
1176 break;
1177 }
1178 }
1179
1180 static void disas_ed(CPUS390XState *env, DisasContext *s, int op, int r1,
1181 int x2, int b2, int d2, int r1b)
1182 {
1183 TCGv_i32 tmp_r1, tmp32;
1184 TCGv_i64 addr, tmp;
1185 addr = get_address(s, x2, b2, d2);
1186 tmp_r1 = tcg_const_i32(r1);
1187 switch (op) {
1188 case 0x4: /* LDEB R1,D2(X2,B2) [RXE] */
1189 potential_page_fault(s);
1190 gen_helper_ldeb(cpu_env, tmp_r1, addr);
1191 break;
1192 case 0x5: /* LXDB R1,D2(X2,B2) [RXE] */
1193 potential_page_fault(s);
1194 gen_helper_lxdb(cpu_env, tmp_r1, addr);
1195 break;
1196 case 0x9: /* CEB R1,D2(X2,B2) [RXE] */
1197 tmp = tcg_temp_new_i64();
1198 tmp32 = load_freg32(r1);
1199 tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
1200 set_cc_cmp_f32_i64(s, tmp32, tmp);
1201 tcg_temp_free_i64(tmp);
1202 tcg_temp_free_i32(tmp32);
1203 break;
1204 case 0xa: /* AEB R1,D2(X2,B2) [RXE] */
1205 tmp = tcg_temp_new_i64();
1206 tmp32 = tcg_temp_new_i32();
1207 tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
1208 tcg_gen_trunc_i64_i32(tmp32, tmp);
1209 gen_helper_aeb(cpu_env, tmp_r1, tmp32);
1210 tcg_temp_free_i64(tmp);
1211 tcg_temp_free_i32(tmp32);
1212
1213 tmp32 = load_freg32(r1);
1214 gen_set_cc_nz_f32(s, tmp32);
1215 tcg_temp_free_i32(tmp32);
1216 break;
1217 case 0xb: /* SEB R1,D2(X2,B2) [RXE] */
1218 tmp = tcg_temp_new_i64();
1219 tmp32 = tcg_temp_new_i32();
1220 tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
1221 tcg_gen_trunc_i64_i32(tmp32, tmp);
1222 gen_helper_seb(cpu_env, tmp_r1, tmp32);
1223 tcg_temp_free_i64(tmp);
1224 tcg_temp_free_i32(tmp32);
1225
1226 tmp32 = load_freg32(r1);
1227 gen_set_cc_nz_f32(s, tmp32);
1228 tcg_temp_free_i32(tmp32);
1229 break;
1230 case 0xd: /* DEB R1,D2(X2,B2) [RXE] */
1231 tmp = tcg_temp_new_i64();
1232 tmp32 = tcg_temp_new_i32();
1233 tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
1234 tcg_gen_trunc_i64_i32(tmp32, tmp);
1235 gen_helper_deb(cpu_env, tmp_r1, tmp32);
1236 tcg_temp_free_i64(tmp);
1237 tcg_temp_free_i32(tmp32);
1238 break;
1239 case 0x10: /* TCEB R1,D2(X2,B2) [RXE] */
1240 potential_page_fault(s);
1241 gen_helper_tceb(cc_op, cpu_env, tmp_r1, addr);
1242 set_cc_static(s);
1243 break;
1244 case 0x11: /* TCDB R1,D2(X2,B2) [RXE] */
1245 potential_page_fault(s);
1246 gen_helper_tcdb(cc_op, cpu_env, tmp_r1, addr);
1247 set_cc_static(s);
1248 break;
1249 case 0x12: /* TCXB R1,D2(X2,B2) [RXE] */
1250 potential_page_fault(s);
1251 gen_helper_tcxb(cc_op, cpu_env, tmp_r1, addr);
1252 set_cc_static(s);
1253 break;
1254 case 0x17: /* MEEB R1,D2(X2,B2) [RXE] */
1255 tmp = tcg_temp_new_i64();
1256 tmp32 = tcg_temp_new_i32();
1257 tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
1258 tcg_gen_trunc_i64_i32(tmp32, tmp);
1259 gen_helper_meeb(cpu_env, tmp_r1, tmp32);
1260 tcg_temp_free_i64(tmp);
1261 tcg_temp_free_i32(tmp32);
1262 break;
1263 case 0x19: /* CDB R1,D2(X2,B2) [RXE] */
1264 potential_page_fault(s);
1265 gen_helper_cdb(cc_op, cpu_env, tmp_r1, addr);
1266 set_cc_static(s);
1267 break;
1268 case 0x1a: /* ADB R1,D2(X2,B2) [RXE] */
1269 potential_page_fault(s);
1270 gen_helper_adb(cc_op, cpu_env, tmp_r1, addr);
1271 set_cc_static(s);
1272 break;
1273 case 0x1b: /* SDB R1,D2(X2,B2) [RXE] */
1274 potential_page_fault(s);
1275 gen_helper_sdb(cc_op, cpu_env, tmp_r1, addr);
1276 set_cc_static(s);
1277 break;
1278 case 0x1c: /* MDB R1,D2(X2,B2) [RXE] */
1279 potential_page_fault(s);
1280 gen_helper_mdb(cpu_env, tmp_r1, addr);
1281 break;
1282 case 0x1d: /* DDB R1,D2(X2,B2) [RXE] */
1283 potential_page_fault(s);
1284 gen_helper_ddb(cpu_env, tmp_r1, addr);
1285 break;
1286 case 0x1e: /* MADB R1,R3,D2(X2,B2) [RXF] */
1287 /* for RXF insns, r1 is R3 and r1b is R1 */
1288 tmp32 = tcg_const_i32(r1b);
1289 potential_page_fault(s);
1290 gen_helper_madb(cpu_env, tmp32, addr, tmp_r1);
1291 tcg_temp_free_i32(tmp32);
1292 break;
1293 default:
1294 LOG_DISAS("illegal ed operation 0x%x\n", op);
1295 gen_illegal_opcode(s);
1296 return;
1297 }
1298 tcg_temp_free_i32(tmp_r1);
1299 tcg_temp_free_i64(addr);
1300 }
1301
1302 static void disas_b2(CPUS390XState *env, DisasContext *s, int op,
1303 uint32_t insn)
1304 {
1305 TCGv_i64 tmp, tmp2, tmp3;
1306 TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
1307 int r1, r2;
1308 #ifndef CONFIG_USER_ONLY
1309 int r3, d2, b2;
1310 #endif
1311
1312 r1 = (insn >> 4) & 0xf;
1313 r2 = insn & 0xf;
1314
1315 LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op, r1, r2);
1316
1317 switch (op) {
1318 case 0x22: /* IPM R1 [RRE] */
1319 tmp32_1 = tcg_const_i32(r1);
1320 gen_op_calc_cc(s);
1321 gen_helper_ipm(cpu_env, cc_op, tmp32_1);
1322 tcg_temp_free_i32(tmp32_1);
1323 break;
1324 case 0x41: /* CKSM R1,R2 [RRE] */
1325 tmp32_1 = tcg_const_i32(r1);
1326 tmp32_2 = tcg_const_i32(r2);
1327 potential_page_fault(s);
1328 gen_helper_cksm(cpu_env, tmp32_1, tmp32_2);
1329 tcg_temp_free_i32(tmp32_1);
1330 tcg_temp_free_i32(tmp32_2);
1331 gen_op_movi_cc(s, 0);
1332 break;
1333 case 0x4e: /* SAR R1,R2 [RRE] */
1334 tmp32_1 = load_reg32(r2);
1335 tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, aregs[r1]));
1336 tcg_temp_free_i32(tmp32_1);
1337 break;
1338 case 0x4f: /* EAR R1,R2 [RRE] */
1339 tmp32_1 = tcg_temp_new_i32();
1340 tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, aregs[r2]));
1341 store_reg32(r1, tmp32_1);
1342 tcg_temp_free_i32(tmp32_1);
1343 break;
1344 case 0x54: /* MVPG R1,R2 [RRE] */
1345 tmp = load_reg(0);
1346 tmp2 = load_reg(r1);
1347 tmp3 = load_reg(r2);
1348 potential_page_fault(s);
1349 gen_helper_mvpg(cpu_env, tmp, tmp2, tmp3);
1350 tcg_temp_free_i64(tmp);
1351 tcg_temp_free_i64(tmp2);
1352 tcg_temp_free_i64(tmp3);
1353 /* XXX check CCO bit and set CC accordingly */
1354 gen_op_movi_cc(s, 0);
1355 break;
1356 case 0x55: /* MVST R1,R2 [RRE] */
1357 tmp32_1 = load_reg32(0);
1358 tmp32_2 = tcg_const_i32(r1);
1359 tmp32_3 = tcg_const_i32(r2);
1360 potential_page_fault(s);
1361 gen_helper_mvst(cpu_env, tmp32_1, tmp32_2, tmp32_3);
1362 tcg_temp_free_i32(tmp32_1);
1363 tcg_temp_free_i32(tmp32_2);
1364 tcg_temp_free_i32(tmp32_3);
1365 gen_op_movi_cc(s, 1);
1366 break;
1367 case 0x5d: /* CLST R1,R2 [RRE] */
1368 tmp32_1 = load_reg32(0);
1369 tmp32_2 = tcg_const_i32(r1);
1370 tmp32_3 = tcg_const_i32(r2);
1371 potential_page_fault(s);
1372 gen_helper_clst(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1373 set_cc_static(s);
1374 tcg_temp_free_i32(tmp32_1);
1375 tcg_temp_free_i32(tmp32_2);
1376 tcg_temp_free_i32(tmp32_3);
1377 break;
1378 case 0x5e: /* SRST R1,R2 [RRE] */
1379 tmp32_1 = load_reg32(0);
1380 tmp32_2 = tcg_const_i32(r1);
1381 tmp32_3 = tcg_const_i32(r2);
1382 potential_page_fault(s);
1383 gen_helper_srst(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1384 set_cc_static(s);
1385 tcg_temp_free_i32(tmp32_1);
1386 tcg_temp_free_i32(tmp32_2);
1387 tcg_temp_free_i32(tmp32_3);
1388 break;
1389
1390 #ifndef CONFIG_USER_ONLY
1391 case 0x02: /* STIDP D2(B2) [S] */
1392 /* Store CPU ID */
1393 check_privileged(s);
1394 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1395 tmp = get_address(s, 0, b2, d2);
1396 potential_page_fault(s);
1397 gen_helper_stidp(cpu_env, tmp);
1398 tcg_temp_free_i64(tmp);
1399 break;
1400 case 0x04: /* SCK D2(B2) [S] */
1401 /* Set Clock */
1402 check_privileged(s);
1403 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1404 tmp = get_address(s, 0, b2, d2);
1405 potential_page_fault(s);
1406 gen_helper_sck(cc_op, tmp);
1407 set_cc_static(s);
1408 tcg_temp_free_i64(tmp);
1409 break;
1410 case 0x05: /* STCK D2(B2) [S] */
1411 /* Store Clock */
1412 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1413 tmp = get_address(s, 0, b2, d2);
1414 potential_page_fault(s);
1415 gen_helper_stck(cc_op, cpu_env, tmp);
1416 set_cc_static(s);
1417 tcg_temp_free_i64(tmp);
1418 break;
1419 case 0x06: /* SCKC D2(B2) [S] */
1420 /* Set Clock Comparator */
1421 check_privileged(s);
1422 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1423 tmp = get_address(s, 0, b2, d2);
1424 potential_page_fault(s);
1425 gen_helper_sckc(cpu_env, tmp);
1426 tcg_temp_free_i64(tmp);
1427 break;
1428 case 0x07: /* STCKC D2(B2) [S] */
1429 /* Store Clock Comparator */
1430 check_privileged(s);
1431 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1432 tmp = get_address(s, 0, b2, d2);
1433 potential_page_fault(s);
1434 gen_helper_stckc(cpu_env, tmp);
1435 tcg_temp_free_i64(tmp);
1436 break;
1437 case 0x08: /* SPT D2(B2) [S] */
1438 /* Set CPU Timer */
1439 check_privileged(s);
1440 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1441 tmp = get_address(s, 0, b2, d2);
1442 potential_page_fault(s);
1443 gen_helper_spt(cpu_env, tmp);
1444 tcg_temp_free_i64(tmp);
1445 break;
1446 case 0x09: /* STPT D2(B2) [S] */
1447 /* Store CPU Timer */
1448 check_privileged(s);
1449 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1450 tmp = get_address(s, 0, b2, d2);
1451 potential_page_fault(s);
1452 gen_helper_stpt(cpu_env, tmp);
1453 tcg_temp_free_i64(tmp);
1454 break;
1455 case 0x0a: /* SPKA D2(B2) [S] */
1456 /* Set PSW Key from Address */
1457 check_privileged(s);
1458 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1459 tmp = get_address(s, 0, b2, d2);
1460 tmp2 = tcg_temp_new_i64();
1461 tcg_gen_andi_i64(tmp2, psw_mask, ~PSW_MASK_KEY);
1462 tcg_gen_shli_i64(tmp, tmp, PSW_SHIFT_KEY - 4);
1463 tcg_gen_or_i64(psw_mask, tmp2, tmp);
1464 tcg_temp_free_i64(tmp2);
1465 tcg_temp_free_i64(tmp);
1466 break;
1467 case 0x0d: /* PTLB [S] */
1468 /* Purge TLB */
1469 check_privileged(s);
1470 gen_helper_ptlb(cpu_env);
1471 break;
1472 case 0x10: /* SPX D2(B2) [S] */
1473 /* Set Prefix Register */
1474 check_privileged(s);
1475 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1476 tmp = get_address(s, 0, b2, d2);
1477 potential_page_fault(s);
1478 gen_helper_spx(cpu_env, tmp);
1479 tcg_temp_free_i64(tmp);
1480 break;
1481 case 0x11: /* STPX D2(B2) [S] */
1482 /* Store Prefix */
1483 check_privileged(s);
1484 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1485 tmp = get_address(s, 0, b2, d2);
1486 tmp2 = tcg_temp_new_i64();
1487 tcg_gen_ld_i64(tmp2, cpu_env, offsetof(CPUS390XState, psa));
1488 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1489 tcg_temp_free_i64(tmp);
1490 tcg_temp_free_i64(tmp2);
1491 break;
1492 case 0x12: /* STAP D2(B2) [S] */
1493 /* Store CPU Address */
1494 check_privileged(s);
1495 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1496 tmp = get_address(s, 0, b2, d2);
1497 tmp2 = tcg_temp_new_i64();
1498 tmp32_1 = tcg_temp_new_i32();
1499 tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, cpu_num));
1500 tcg_gen_extu_i32_i64(tmp2, tmp32_1);
1501 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1502 tcg_temp_free_i64(tmp);
1503 tcg_temp_free_i64(tmp2);
1504 tcg_temp_free_i32(tmp32_1);
1505 break;
1506 case 0x21: /* IPTE R1,R2 [RRE] */
1507 /* Invalidate PTE */
1508 check_privileged(s);
1509 r1 = (insn >> 4) & 0xf;
1510 r2 = insn & 0xf;
1511 tmp = load_reg(r1);
1512 tmp2 = load_reg(r2);
1513 gen_helper_ipte(cpu_env, tmp, tmp2);
1514 tcg_temp_free_i64(tmp);
1515 tcg_temp_free_i64(tmp2);
1516 break;
1517 case 0x29: /* ISKE R1,R2 [RRE] */
1518 /* Insert Storage Key Extended */
1519 check_privileged(s);
1520 r1 = (insn >> 4) & 0xf;
1521 r2 = insn & 0xf;
1522 tmp = load_reg(r2);
1523 tmp2 = tcg_temp_new_i64();
1524 gen_helper_iske(tmp2, cpu_env, tmp);
1525 store_reg(r1, tmp2);
1526 tcg_temp_free_i64(tmp);
1527 tcg_temp_free_i64(tmp2);
1528 break;
1529 case 0x2a: /* RRBE R1,R2 [RRE] */
1530 /* Set Storage Key Extended */
1531 check_privileged(s);
1532 r1 = (insn >> 4) & 0xf;
1533 r2 = insn & 0xf;
1534 tmp32_1 = load_reg32(r1);
1535 tmp = load_reg(r2);
1536 gen_helper_rrbe(cc_op, cpu_env, tmp32_1, tmp);
1537 set_cc_static(s);
1538 tcg_temp_free_i32(tmp32_1);
1539 tcg_temp_free_i64(tmp);
1540 break;
1541 case 0x2b: /* SSKE R1,R2 [RRE] */
1542 /* Set Storage Key Extended */
1543 check_privileged(s);
1544 r1 = (insn >> 4) & 0xf;
1545 r2 = insn & 0xf;
1546 tmp32_1 = load_reg32(r1);
1547 tmp = load_reg(r2);
1548 gen_helper_sske(cpu_env, tmp32_1, tmp);
1549 tcg_temp_free_i32(tmp32_1);
1550 tcg_temp_free_i64(tmp);
1551 break;
1552 case 0x34: /* STCH ? */
1553 /* Store Subchannel */
1554 check_privileged(s);
1555 gen_op_movi_cc(s, 3);
1556 break;
1557 case 0x46: /* STURA R1,R2 [RRE] */
1558 /* Store Using Real Address */
1559 check_privileged(s);
1560 r1 = (insn >> 4) & 0xf;
1561 r2 = insn & 0xf;
1562 tmp32_1 = load_reg32(r1);
1563 tmp = load_reg(r2);
1564 potential_page_fault(s);
1565 gen_helper_stura(cpu_env, tmp, tmp32_1);
1566 tcg_temp_free_i32(tmp32_1);
1567 tcg_temp_free_i64(tmp);
1568 break;
1569 case 0x50: /* CSP R1,R2 [RRE] */
1570 /* Compare And Swap And Purge */
1571 check_privileged(s);
1572 r1 = (insn >> 4) & 0xf;
1573 r2 = insn & 0xf;
1574 tmp32_1 = tcg_const_i32(r1);
1575 tmp32_2 = tcg_const_i32(r2);
1576 gen_helper_csp(cc_op, cpu_env, tmp32_1, tmp32_2);
1577 set_cc_static(s);
1578 tcg_temp_free_i32(tmp32_1);
1579 tcg_temp_free_i32(tmp32_2);
1580 break;
1581 case 0x5f: /* CHSC ? */
1582 /* Channel Subsystem Call */
1583 check_privileged(s);
1584 gen_op_movi_cc(s, 3);
1585 break;
1586 case 0x78: /* STCKE D2(B2) [S] */
1587 /* Store Clock Extended */
1588 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1589 tmp = get_address(s, 0, b2, d2);
1590 potential_page_fault(s);
1591 gen_helper_stcke(cc_op, cpu_env, tmp);
1592 set_cc_static(s);
1593 tcg_temp_free_i64(tmp);
1594 break;
1595 case 0x79: /* SACF D2(B2) [S] */
1596 /* Set Address Space Control Fast */
1597 check_privileged(s);
1598 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1599 tmp = get_address(s, 0, b2, d2);
1600 potential_page_fault(s);
1601 gen_helper_sacf(cpu_env, tmp);
1602 tcg_temp_free_i64(tmp);
1603 /* addressing mode has changed, so end the block */
1604 s->pc = s->next_pc;
1605 update_psw_addr(s);
1606 s->is_jmp = DISAS_JUMP;
1607 break;
1608 case 0x7d: /* STSI D2,(B2) [S] */
1609 check_privileged(s);
1610 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1611 tmp = get_address(s, 0, b2, d2);
1612 tmp32_1 = load_reg32(0);
1613 tmp32_2 = load_reg32(1);
1614 potential_page_fault(s);
1615 gen_helper_stsi(cc_op, cpu_env, tmp, tmp32_1, tmp32_2);
1616 set_cc_static(s);
1617 tcg_temp_free_i64(tmp);
1618 tcg_temp_free_i32(tmp32_1);
1619 tcg_temp_free_i32(tmp32_2);
1620 break;
1621 case 0x9d: /* LFPC D2(B2) [S] */
1622 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1623 tmp = get_address(s, 0, b2, d2);
1624 tmp2 = tcg_temp_new_i64();
1625 tmp32_1 = tcg_temp_new_i32();
1626 tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
1627 tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
1628 tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc));
1629 tcg_temp_free_i64(tmp);
1630 tcg_temp_free_i64(tmp2);
1631 tcg_temp_free_i32(tmp32_1);
1632 break;
1633 case 0xb1: /* STFL D2(B2) [S] */
1634 /* Store Facility List (CPU features) at 200 */
1635 check_privileged(s);
1636 tmp2 = tcg_const_i64(0xc0000000);
1637 tmp = tcg_const_i64(200);
1638 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1639 tcg_temp_free_i64(tmp2);
1640 tcg_temp_free_i64(tmp);
1641 break;
1642 case 0xb2: /* LPSWE D2(B2) [S] */
1643 /* Load PSW Extended */
1644 check_privileged(s);
1645 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1646 tmp = get_address(s, 0, b2, d2);
1647 tmp2 = tcg_temp_new_i64();
1648 tmp3 = tcg_temp_new_i64();
1649 tcg_gen_qemu_ld64(tmp2, tmp, get_mem_index(s));
1650 tcg_gen_addi_i64(tmp, tmp, 8);
1651 tcg_gen_qemu_ld64(tmp3, tmp, get_mem_index(s));
1652 gen_helper_load_psw(cpu_env, tmp2, tmp3);
1653 /* we need to keep cc_op intact */
1654 s->is_jmp = DISAS_JUMP;
1655 tcg_temp_free_i64(tmp);
1656 tcg_temp_free_i64(tmp2);
1657 tcg_temp_free_i64(tmp3);
1658 break;
1659 case 0x20: /* SERVC R1,R2 [RRE] */
1660 /* SCLP Service call (PV hypercall) */
1661 check_privileged(s);
1662 potential_page_fault(s);
1663 tmp32_1 = load_reg32(r2);
1664 tmp = load_reg(r1);
1665 gen_helper_servc(cc_op, cpu_env, tmp32_1, tmp);
1666 set_cc_static(s);
1667 tcg_temp_free_i32(tmp32_1);
1668 tcg_temp_free_i64(tmp);
1669 break;
1670 #endif
1671 default:
1672 LOG_DISAS("illegal b2 operation 0x%x\n", op);
1673 gen_illegal_opcode(s);
1674 break;
1675 }
1676 }
1677
1678 static void disas_b3(CPUS390XState *env, DisasContext *s, int op, int m3,
1679 int r1, int r2)
1680 {
1681 TCGv_i64 tmp;
1682 TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
1683 LOG_DISAS("disas_b3: op 0x%x m3 0x%x r1 %d r2 %d\n", op, m3, r1, r2);
1684 #define FP_HELPER(i) \
1685 tmp32_1 = tcg_const_i32(r1); \
1686 tmp32_2 = tcg_const_i32(r2); \
1687 gen_helper_ ## i(cpu_env, tmp32_1, tmp32_2); \
1688 tcg_temp_free_i32(tmp32_1); \
1689 tcg_temp_free_i32(tmp32_2);
1690
1691 #define FP_HELPER_CC(i) \
1692 tmp32_1 = tcg_const_i32(r1); \
1693 tmp32_2 = tcg_const_i32(r2); \
1694 gen_helper_ ## i(cc_op, cpu_env, tmp32_1, tmp32_2); \
1695 set_cc_static(s); \
1696 tcg_temp_free_i32(tmp32_1); \
1697 tcg_temp_free_i32(tmp32_2);
1698
1699 switch (op) {
1700 case 0x0: /* LPEBR R1,R2 [RRE] */
1701 FP_HELPER_CC(lpebr);
1702 break;
1703 case 0x2: /* LTEBR R1,R2 [RRE] */
1704 FP_HELPER_CC(ltebr);
1705 break;
1706 case 0x3: /* LCEBR R1,R2 [RRE] */
1707 FP_HELPER_CC(lcebr);
1708 break;
1709 case 0x4: /* LDEBR R1,R2 [RRE] */
1710 FP_HELPER(ldebr);
1711 break;
1712 case 0x5: /* LXDBR R1,R2 [RRE] */
1713 FP_HELPER(lxdbr);
1714 break;
1715 case 0x9: /* CEBR R1,R2 [RRE] */
1716 FP_HELPER_CC(cebr);
1717 break;
1718 case 0xa: /* AEBR R1,R2 [RRE] */
1719 FP_HELPER_CC(aebr);
1720 break;
1721 case 0xb: /* SEBR R1,R2 [RRE] */
1722 FP_HELPER_CC(sebr);
1723 break;
1724 case 0xd: /* DEBR R1,R2 [RRE] */
1725 FP_HELPER(debr);
1726 break;
1727 case 0x10: /* LPDBR R1,R2 [RRE] */
1728 FP_HELPER_CC(lpdbr);
1729 break;
1730 case 0x12: /* LTDBR R1,R2 [RRE] */
1731 FP_HELPER_CC(ltdbr);
1732 break;
1733 case 0x13: /* LCDBR R1,R2 [RRE] */
1734 FP_HELPER_CC(lcdbr);
1735 break;
1736 case 0x15: /* SQBDR R1,R2 [RRE] */
1737 FP_HELPER(sqdbr);
1738 break;
1739 case 0x17: /* MEEBR R1,R2 [RRE] */
1740 FP_HELPER(meebr);
1741 break;
1742 case 0x19: /* CDBR R1,R2 [RRE] */
1743 FP_HELPER_CC(cdbr);
1744 break;
1745 case 0x1a: /* ADBR R1,R2 [RRE] */
1746 FP_HELPER_CC(adbr);
1747 break;
1748 case 0x1b: /* SDBR R1,R2 [RRE] */
1749 FP_HELPER_CC(sdbr);
1750 break;
1751 case 0x1c: /* MDBR R1,R2 [RRE] */
1752 FP_HELPER(mdbr);
1753 break;
1754 case 0x1d: /* DDBR R1,R2 [RRE] */
1755 FP_HELPER(ddbr);
1756 break;
1757 case 0xe: /* MAEBR R1,R3,R2 [RRF] */
1758 case 0x1e: /* MADBR R1,R3,R2 [RRF] */
1759 case 0x1f: /* MSDBR R1,R3,R2 [RRF] */
1760 /* for RRF insns, m3 is R1, r1 is R3, and r2 is R2 */
1761 tmp32_1 = tcg_const_i32(m3);
1762 tmp32_2 = tcg_const_i32(r2);
1763 tmp32_3 = tcg_const_i32(r1);
1764 switch (op) {
1765 case 0xe:
1766 gen_helper_maebr(cpu_env, tmp32_1, tmp32_3, tmp32_2);
1767 break;
1768 case 0x1e:
1769 gen_helper_madbr(cpu_env, tmp32_1, tmp32_3, tmp32_2);
1770 break;
1771 case 0x1f:
1772 gen_helper_msdbr(cpu_env, tmp32_1, tmp32_3, tmp32_2);
1773 break;
1774 default:
1775 tcg_abort();
1776 }
1777 tcg_temp_free_i32(tmp32_1);
1778 tcg_temp_free_i32(tmp32_2);
1779 tcg_temp_free_i32(tmp32_3);
1780 break;
1781 case 0x40: /* LPXBR R1,R2 [RRE] */
1782 FP_HELPER_CC(lpxbr);
1783 break;
1784 case 0x42: /* LTXBR R1,R2 [RRE] */
1785 FP_HELPER_CC(ltxbr);
1786 break;
1787 case 0x43: /* LCXBR R1,R2 [RRE] */
1788 FP_HELPER_CC(lcxbr);
1789 break;
1790 case 0x44: /* LEDBR R1,R2 [RRE] */
1791 FP_HELPER(ledbr);
1792 break;
1793 case 0x45: /* LDXBR R1,R2 [RRE] */
1794 FP_HELPER(ldxbr);
1795 break;
1796 case 0x46: /* LEXBR R1,R2 [RRE] */
1797 FP_HELPER(lexbr);
1798 break;
1799 case 0x49: /* CXBR R1,R2 [RRE] */
1800 FP_HELPER_CC(cxbr);
1801 break;
1802 case 0x4a: /* AXBR R1,R2 [RRE] */
1803 FP_HELPER_CC(axbr);
1804 break;
1805 case 0x4b: /* SXBR R1,R2 [RRE] */
1806 FP_HELPER_CC(sxbr);
1807 break;
1808 case 0x4c: /* MXBR R1,R2 [RRE] */
1809 FP_HELPER(mxbr);
1810 break;
1811 case 0x4d: /* DXBR R1,R2 [RRE] */
1812 FP_HELPER(dxbr);
1813 break;
1814 case 0x65: /* LXR R1,R2 [RRE] */
1815 tmp = load_freg(r2);
1816 store_freg(r1, tmp);
1817 tcg_temp_free_i64(tmp);
1818 tmp = load_freg(r2 + 2);
1819 store_freg(r1 + 2, tmp);
1820 tcg_temp_free_i64(tmp);
1821 break;
1822 case 0x74: /* LZER R1 [RRE] */
1823 tmp32_1 = tcg_const_i32(r1);
1824 gen_helper_lzer(cpu_env, tmp32_1);
1825 tcg_temp_free_i32(tmp32_1);
1826 break;
1827 case 0x75: /* LZDR R1 [RRE] */
1828 tmp32_1 = tcg_const_i32(r1);
1829 gen_helper_lzdr(cpu_env, tmp32_1);
1830 tcg_temp_free_i32(tmp32_1);
1831 break;
1832 case 0x76: /* LZXR R1 [RRE] */
1833 tmp32_1 = tcg_const_i32(r1);
1834 gen_helper_lzxr(cpu_env, tmp32_1);
1835 tcg_temp_free_i32(tmp32_1);
1836 break;
1837 case 0x84: /* SFPC R1 [RRE] */
1838 tmp32_1 = load_reg32(r1);
1839 tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc));
1840 tcg_temp_free_i32(tmp32_1);
1841 break;
1842 case 0x8c: /* EFPC R1 [RRE] */
1843 tmp32_1 = tcg_temp_new_i32();
1844 tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc));
1845 store_reg32(r1, tmp32_1);
1846 tcg_temp_free_i32(tmp32_1);
1847 break;
1848 case 0x94: /* CEFBR R1,R2 [RRE] */
1849 case 0x95: /* CDFBR R1,R2 [RRE] */
1850 case 0x96: /* CXFBR R1,R2 [RRE] */
1851 tmp32_1 = tcg_const_i32(r1);
1852 tmp32_2 = load_reg32(r2);
1853 switch (op) {
1854 case 0x94:
1855 gen_helper_cefbr(cpu_env, tmp32_1, tmp32_2);
1856 break;
1857 case 0x95:
1858 gen_helper_cdfbr(cpu_env, tmp32_1, tmp32_2);
1859 break;
1860 case 0x96:
1861 gen_helper_cxfbr(cpu_env, tmp32_1, tmp32_2);
1862 break;
1863 default:
1864 tcg_abort();
1865 }
1866 tcg_temp_free_i32(tmp32_1);
1867 tcg_temp_free_i32(tmp32_2);
1868 break;
1869 case 0x98: /* CFEBR R1,R2 [RRE] */
1870 case 0x99: /* CFDBR R1,R2 [RRE] */
1871 case 0x9a: /* CFXBR R1,R2 [RRE] */
1872 tmp32_1 = tcg_const_i32(r1);
1873 tmp32_2 = tcg_const_i32(r2);
1874 tmp32_3 = tcg_const_i32(m3);
1875 switch (op) {
1876 case 0x98:
1877 gen_helper_cfebr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1878 break;
1879 case 0x99:
1880 gen_helper_cfdbr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1881 break;
1882 case 0x9a:
1883 gen_helper_cfxbr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1884 break;
1885 default:
1886 tcg_abort();
1887 }
1888 set_cc_static(s);
1889 tcg_temp_free_i32(tmp32_1);
1890 tcg_temp_free_i32(tmp32_2);
1891 tcg_temp_free_i32(tmp32_3);
1892 break;
1893 case 0xa4: /* CEGBR R1,R2 [RRE] */
1894 case 0xa5: /* CDGBR R1,R2 [RRE] */
1895 tmp32_1 = tcg_const_i32(r1);
1896 tmp = load_reg(r2);
1897 switch (op) {
1898 case 0xa4:
1899 gen_helper_cegbr(cpu_env, tmp32_1, tmp);
1900 break;
1901 case 0xa5:
1902 gen_helper_cdgbr(cpu_env, tmp32_1, tmp);
1903 break;
1904 default:
1905 tcg_abort();
1906 }
1907 tcg_temp_free_i32(tmp32_1);
1908 tcg_temp_free_i64(tmp);
1909 break;
1910 case 0xa6: /* CXGBR R1,R2 [RRE] */
1911 tmp32_1 = tcg_const_i32(r1);
1912 tmp = load_reg(r2);
1913 gen_helper_cxgbr(cpu_env, tmp32_1, tmp);
1914 tcg_temp_free_i32(tmp32_1);
1915 tcg_temp_free_i64(tmp);
1916 break;
1917 case 0xa8: /* CGEBR R1,R2 [RRE] */
1918 tmp32_1 = tcg_const_i32(r1);
1919 tmp32_2 = tcg_const_i32(r2);
1920 tmp32_3 = tcg_const_i32(m3);
1921 gen_helper_cgebr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1922 set_cc_static(s);
1923 tcg_temp_free_i32(tmp32_1);
1924 tcg_temp_free_i32(tmp32_2);
1925 tcg_temp_free_i32(tmp32_3);
1926 break;
1927 case 0xa9: /* CGDBR R1,R2 [RRE] */
1928 tmp32_1 = tcg_const_i32(r1);
1929 tmp32_2 = tcg_const_i32(r2);
1930 tmp32_3 = tcg_const_i32(m3);
1931 gen_helper_cgdbr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1932 set_cc_static(s);
1933 tcg_temp_free_i32(tmp32_1);
1934 tcg_temp_free_i32(tmp32_2);
1935 tcg_temp_free_i32(tmp32_3);
1936 break;
1937 case 0xaa: /* CGXBR R1,R2 [RRE] */
1938 tmp32_1 = tcg_const_i32(r1);
1939 tmp32_2 = tcg_const_i32(r2);
1940 tmp32_3 = tcg_const_i32(m3);
1941 gen_helper_cgxbr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1942 set_cc_static(s);
1943 tcg_temp_free_i32(tmp32_1);
1944 tcg_temp_free_i32(tmp32_2);
1945 tcg_temp_free_i32(tmp32_3);
1946 break;
1947 default:
1948 LOG_DISAS("illegal b3 operation 0x%x\n", op);
1949 gen_illegal_opcode(s);
1950 break;
1951 }
1952
1953 #undef FP_HELPER_CC
1954 #undef FP_HELPER
1955 }
1956
1957 static void disas_b9(CPUS390XState *env, DisasContext *s, int op, int r1,
1958 int r2)
1959 {
1960 TCGv_i64 tmp;
1961 TCGv_i32 tmp32_1;
1962
1963 LOG_DISAS("disas_b9: op 0x%x r1 %d r2 %d\n", op, r1, r2);
1964 switch (op) {
1965 case 0x17: /* LLGTR R1,R2 [RRE] */
1966 tmp32_1 = load_reg32(r2);
1967 tmp = tcg_temp_new_i64();
1968 tcg_gen_andi_i32(tmp32_1, tmp32_1, 0x7fffffffUL);
1969 tcg_gen_extu_i32_i64(tmp, tmp32_1);
1970 store_reg(r1, tmp);
1971 tcg_temp_free_i32(tmp32_1);
1972 tcg_temp_free_i64(tmp);
1973 break;
1974 case 0x0f: /* LRVGR R1,R2 [RRE] */
1975 tcg_gen_bswap64_i64(regs[r1], regs[r2]);
1976 break;
1977 case 0x1f: /* LRVR R1,R2 [RRE] */
1978 tmp32_1 = load_reg32(r2);
1979 tcg_gen_bswap32_i32(tmp32_1, tmp32_1);
1980 store_reg32(r1, tmp32_1);
1981 tcg_temp_free_i32(tmp32_1);
1982 break;
1983 case 0x83: /* FLOGR R1,R2 [RRE] */
1984 tmp = load_reg(r2);
1985 tmp32_1 = tcg_const_i32(r1);
1986 gen_helper_flogr(cc_op, cpu_env, tmp32_1, tmp);
1987 set_cc_static(s);
1988 tcg_temp_free_i64(tmp);
1989 tcg_temp_free_i32(tmp32_1);
1990 break;
1991 default:
1992 LOG_DISAS("illegal b9 operation 0x%x\n", op);
1993 gen_illegal_opcode(s);
1994 break;
1995 }
1996 }
1997
1998 static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
1999 {
2000 TCGv_i64 tmp, tmp2;
2001 TCGv_i32 tmp32_1, tmp32_2;
2002 unsigned char opc;
2003 uint64_t insn;
2004 int op, r1, r2, r3, d1, d2, x2, b1, b2, r1b;
2005
2006 opc = cpu_ldub_code(env, s->pc);
2007 LOG_DISAS("opc 0x%x\n", opc);
2008
2009 switch (opc) {
2010 #ifndef CONFIG_USER_ONLY
2011 case 0xae: /* SIGP R1,R3,D2(B2) [RS] */
2012 check_privileged(s);
2013 insn = ld_code4(env, s->pc);
2014 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2015 tmp = get_address(s, 0, b2, d2);
2016 tmp2 = load_reg(r3);
2017 tmp32_1 = tcg_const_i32(r1);
2018 potential_page_fault(s);
2019 gen_helper_sigp(cc_op, cpu_env, tmp, tmp32_1, tmp2);
2020 set_cc_static(s);
2021 tcg_temp_free_i64(tmp);
2022 tcg_temp_free_i64(tmp2);
2023 tcg_temp_free_i32(tmp32_1);
2024 break;
2025 case 0xb1: /* LRA R1,D2(X2, B2) [RX] */
2026 check_privileged(s);
2027 insn = ld_code4(env, s->pc);
2028 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
2029 tmp32_1 = tcg_const_i32(r1);
2030 potential_page_fault(s);
2031 gen_helper_lra(cc_op, cpu_env, tmp, tmp32_1);
2032 set_cc_static(s);
2033 tcg_temp_free_i64(tmp);
2034 tcg_temp_free_i32(tmp32_1);
2035 break;
2036 #endif
2037 case 0xb2:
2038 insn = ld_code4(env, s->pc);
2039 op = (insn >> 16) & 0xff;
2040 switch (op) {
2041 case 0x9c: /* STFPC D2(B2) [S] */
2042 d2 = insn & 0xfff;
2043 b2 = (insn >> 12) & 0xf;
2044 tmp32_1 = tcg_temp_new_i32();
2045 tmp = tcg_temp_new_i64();
2046 tmp2 = get_address(s, 0, b2, d2);
2047 tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc));
2048 tcg_gen_extu_i32_i64(tmp, tmp32_1);
2049 tcg_gen_qemu_st32(tmp, tmp2, get_mem_index(s));
2050 tcg_temp_free_i32(tmp32_1);
2051 tcg_temp_free_i64(tmp);
2052 tcg_temp_free_i64(tmp2);
2053 break;
2054 default:
2055 disas_b2(env, s, op, insn);
2056 break;
2057 }
2058 break;
2059 case 0xb3:
2060 insn = ld_code4(env, s->pc);
2061 op = (insn >> 16) & 0xff;
2062 r3 = (insn >> 12) & 0xf; /* aka m3 */
2063 r1 = (insn >> 4) & 0xf;
2064 r2 = insn & 0xf;
2065 disas_b3(env, s, op, r3, r1, r2);
2066 break;
2067 #ifndef CONFIG_USER_ONLY
2068 case 0xb6: /* STCTL R1,R3,D2(B2) [RS] */
2069 /* Store Control */
2070 check_privileged(s);
2071 insn = ld_code4(env, s->pc);
2072 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2073 tmp = get_address(s, 0, b2, d2);
2074 tmp32_1 = tcg_const_i32(r1);
2075 tmp32_2 = tcg_const_i32(r3);
2076 potential_page_fault(s);
2077 gen_helper_stctl(cpu_env, tmp32_1, tmp, tmp32_2);
2078 tcg_temp_free_i64(tmp);
2079 tcg_temp_free_i32(tmp32_1);
2080 tcg_temp_free_i32(tmp32_2);
2081 break;
2082 case 0xb7: /* LCTL R1,R3,D2(B2) [RS] */
2083 /* Load Control */
2084 check_privileged(s);
2085 insn = ld_code4(env, s->pc);
2086 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2087 tmp = get_address(s, 0, b2, d2);
2088 tmp32_1 = tcg_const_i32(r1);
2089 tmp32_2 = tcg_const_i32(r3);
2090 potential_page_fault(s);
2091 gen_helper_lctl(cpu_env, tmp32_1, tmp, tmp32_2);
2092 tcg_temp_free_i64(tmp);
2093 tcg_temp_free_i32(tmp32_1);
2094 tcg_temp_free_i32(tmp32_2);
2095 break;
2096 #endif
2097 case 0xb9:
2098 insn = ld_code4(env, s->pc);
2099 r1 = (insn >> 4) & 0xf;
2100 r2 = insn & 0xf;
2101 op = (insn >> 16) & 0xff;
2102 disas_b9(env, s, op, r1, r2);
2103 break;
2104 case 0xba: /* CS R1,R3,D2(B2) [RS] */
2105 insn = ld_code4(env, s->pc);
2106 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2107 tmp = get_address(s, 0, b2, d2);
2108 tmp32_1 = tcg_const_i32(r1);
2109 tmp32_2 = tcg_const_i32(r3);
2110 potential_page_fault(s);
2111 gen_helper_cs(cc_op, cpu_env, tmp32_1, tmp, tmp32_2);
2112 set_cc_static(s);
2113 tcg_temp_free_i64(tmp);
2114 tcg_temp_free_i32(tmp32_1);
2115 tcg_temp_free_i32(tmp32_2);
2116 break;
2117 case 0xbd: /* CLM R1,M3,D2(B2) [RS] */
2118 insn = ld_code4(env, s->pc);
2119 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2120 tmp = get_address(s, 0, b2, d2);
2121 tmp32_1 = load_reg32(r1);
2122 tmp32_2 = tcg_const_i32(r3);
2123 potential_page_fault(s);
2124 gen_helper_clm(cc_op, cpu_env, tmp32_1, tmp32_2, tmp);
2125 set_cc_static(s);
2126 tcg_temp_free_i64(tmp);
2127 tcg_temp_free_i32(tmp32_1);
2128 tcg_temp_free_i32(tmp32_2);
2129 break;
2130 case 0xbe: /* STCM R1,M3,D2(B2) [RS] */
2131 insn = ld_code4(env, s->pc);
2132 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2133 tmp = get_address(s, 0, b2, d2);
2134 tmp32_1 = load_reg32(r1);
2135 tmp32_2 = tcg_const_i32(r3);
2136 potential_page_fault(s);
2137 gen_helper_stcm(cpu_env, tmp32_1, tmp32_2, tmp);
2138 tcg_temp_free_i64(tmp);
2139 tcg_temp_free_i32(tmp32_1);
2140 tcg_temp_free_i32(tmp32_2);
2141 break;
2142 #ifndef CONFIG_USER_ONLY
2143 case 0xda: /* MVCP D1(R1,B1),D2(B2),R3 [SS] */
2144 case 0xdb: /* MVCS D1(R1,B1),D2(B2),R3 [SS] */
2145 check_privileged(s);
2146 potential_page_fault(s);
2147 insn = ld_code6(env, s->pc);
2148 r1 = (insn >> 36) & 0xf;
2149 r3 = (insn >> 32) & 0xf;
2150 b1 = (insn >> 28) & 0xf;
2151 d1 = (insn >> 16) & 0xfff;
2152 b2 = (insn >> 12) & 0xf;
2153 d2 = insn & 0xfff;
2154 /* XXX key in r3 */
2155 tmp = get_address(s, 0, b1, d1);
2156 tmp2 = get_address(s, 0, b2, d2);
2157 if (opc == 0xda) {
2158 gen_helper_mvcp(cc_op, cpu_env, regs[r1], tmp, tmp2);
2159 } else {
2160 gen_helper_mvcs(cc_op, cpu_env, regs[r1], tmp, tmp2);
2161 }
2162 set_cc_static(s);
2163 tcg_temp_free_i64(tmp);
2164 tcg_temp_free_i64(tmp2);
2165 break;
2166 #endif
2167 case 0xe3:
2168 insn = ld_code6(env, s->pc);
2169 debug_insn(insn);
2170 op = insn & 0xff;
2171 r1 = (insn >> 36) & 0xf;
2172 x2 = (insn >> 32) & 0xf;
2173 b2 = (insn >> 28) & 0xf;
2174 d2 = ((int)((((insn >> 16) & 0xfff)
2175 | ((insn << 4) & 0xff000)) << 12)) >> 12;
2176 disas_e3(env, s, op, r1, x2, b2, d2 );
2177 break;
2178 #ifndef CONFIG_USER_ONLY
2179 case 0xe5:
2180 /* Test Protection */
2181 check_privileged(s);
2182 insn = ld_code6(env, s->pc);
2183 debug_insn(insn);
2184 disas_e5(env, s, insn);
2185 break;
2186 #endif
2187 case 0xeb:
2188 insn = ld_code6(env, s->pc);
2189 debug_insn(insn);
2190 op = insn & 0xff;
2191 r1 = (insn >> 36) & 0xf;
2192 r3 = (insn >> 32) & 0xf;
2193 b2 = (insn >> 28) & 0xf;
2194 d2 = ((int)((((insn >> 16) & 0xfff)
2195 | ((insn << 4) & 0xff000)) << 12)) >> 12;
2196 disas_eb(env, s, op, r1, r3, b2, d2);
2197 break;
2198 case 0xed:
2199 insn = ld_code6(env, s->pc);
2200 debug_insn(insn);
2201 op = insn & 0xff;
2202 r1 = (insn >> 36) & 0xf;
2203 x2 = (insn >> 32) & 0xf;
2204 b2 = (insn >> 28) & 0xf;
2205 d2 = (short)((insn >> 16) & 0xfff);
2206 r1b = (insn >> 12) & 0xf;
2207 disas_ed(env, s, op, r1, x2, b2, d2, r1b);
2208 break;
2209 default:
2210 qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%x\n", opc);
2211 gen_illegal_opcode(s);
2212 break;
2213 }
2214 }
2215
2216 /* ====================================================================== */
2217 /* Define the insn format enumeration. */
2218 #define F0(N) FMT_##N,
2219 #define F1(N, X1) F0(N)
2220 #define F2(N, X1, X2) F0(N)
2221 #define F3(N, X1, X2, X3) F0(N)
2222 #define F4(N, X1, X2, X3, X4) F0(N)
2223 #define F5(N, X1, X2, X3, X4, X5) F0(N)
2224
2225 typedef enum {
2226 #include "insn-format.def"
2227 } DisasFormat;
2228
2229 #undef F0
2230 #undef F1
2231 #undef F2
2232 #undef F3
2233 #undef F4
2234 #undef F5
2235
2236 /* Define a structure to hold the decoded fields. We'll store each inside
2237 an array indexed by an enum. In order to conserve memory, we'll arrange
2238 for fields that do not exist at the same time to overlap, thus the "C"
2239 for compact. For checking purposes there is an "O" for original index
2240 as well that will be applied to availability bitmaps. */
2241
2242 enum DisasFieldIndexO {
2243 FLD_O_r1,
2244 FLD_O_r2,
2245 FLD_O_r3,
2246 FLD_O_m1,
2247 FLD_O_m3,
2248 FLD_O_m4,
2249 FLD_O_b1,
2250 FLD_O_b2,
2251 FLD_O_b4,
2252 FLD_O_d1,
2253 FLD_O_d2,
2254 FLD_O_d4,
2255 FLD_O_x2,
2256 FLD_O_l1,
2257 FLD_O_l2,
2258 FLD_O_i1,
2259 FLD_O_i2,
2260 FLD_O_i3,
2261 FLD_O_i4,
2262 FLD_O_i5
2263 };
2264
2265 enum DisasFieldIndexC {
2266 FLD_C_r1 = 0,
2267 FLD_C_m1 = 0,
2268 FLD_C_b1 = 0,
2269 FLD_C_i1 = 0,
2270
2271 FLD_C_r2 = 1,
2272 FLD_C_b2 = 1,
2273 FLD_C_i2 = 1,
2274
2275 FLD_C_r3 = 2,
2276 FLD_C_m3 = 2,
2277 FLD_C_i3 = 2,
2278
2279 FLD_C_m4 = 3,
2280 FLD_C_b4 = 3,
2281 FLD_C_i4 = 3,
2282 FLD_C_l1 = 3,
2283
2284 FLD_C_i5 = 4,
2285 FLD_C_d1 = 4,
2286
2287 FLD_C_d2 = 5,
2288
2289 FLD_C_d4 = 6,
2290 FLD_C_x2 = 6,
2291 FLD_C_l2 = 6,
2292
2293 NUM_C_FIELD = 7
2294 };
2295
2296 struct DisasFields {
2297 unsigned op:8;
2298 unsigned op2:8;
2299 unsigned presentC:16;
2300 unsigned int presentO;
2301 int c[NUM_C_FIELD];
2302 };
2303
2304 /* This is the way fields are to be accessed out of DisasFields. */
2305 #define have_field(S, F) have_field1((S), FLD_O_##F)
2306 #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
2307
2308 static bool have_field1(const DisasFields *f, enum DisasFieldIndexO c)
2309 {
2310 return (f->presentO >> c) & 1;
2311 }
2312
2313 static int get_field1(const DisasFields *f, enum DisasFieldIndexO o,
2314 enum DisasFieldIndexC c)
2315 {
2316 assert(have_field1(f, o));
2317 return f->c[c];
2318 }
2319
2320 /* Describe the layout of each field in each format. */
2321 typedef struct DisasField {
2322 unsigned int beg:8;
2323 unsigned int size:8;
2324 unsigned int type:2;
2325 unsigned int indexC:6;
2326 enum DisasFieldIndexO indexO:8;
2327 } DisasField;
2328
2329 typedef struct DisasFormatInfo {
2330 DisasField op[NUM_C_FIELD];
2331 } DisasFormatInfo;
2332
2333 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
2334 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
2335 #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
2336 { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
2337 #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
2338 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
2339 { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
2340 #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
2341 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
2342 #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
2343 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
2344 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
2345 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
2346 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
2347
2348 #define F0(N) { { } },
2349 #define F1(N, X1) { { X1 } },
2350 #define F2(N, X1, X2) { { X1, X2 } },
2351 #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
2352 #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
2353 #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
2354
2355 static const DisasFormatInfo format_info[] = {
2356 #include "insn-format.def"
2357 };
2358
2359 #undef F0
2360 #undef F1
2361 #undef F2
2362 #undef F3
2363 #undef F4
2364 #undef F5
2365 #undef R
2366 #undef M
2367 #undef BD
2368 #undef BXD
2369 #undef BDL
2370 #undef BXDL
2371 #undef I
2372 #undef L
2373
2374 /* Generally, we'll extract operands into this structures, operate upon
2375 them, and store them back. See the "in1", "in2", "prep", "wout" sets
2376 of routines below for more details. */
2377 typedef struct {
2378 bool g_out, g_out2, g_in1, g_in2;
2379 TCGv_i64 out, out2, in1, in2;
2380 TCGv_i64 addr1;
2381 } DisasOps;
2382
2383 /* Return values from translate_one, indicating the state of the TB. */
2384 typedef enum {
2385 /* Continue the TB. */
2386 NO_EXIT,
2387 /* We have emitted one or more goto_tb. No fixup required. */
2388 EXIT_GOTO_TB,
2389 /* We are not using a goto_tb (for whatever reason), but have updated
2390 the PC (for whatever reason), so there's no need to do it again on
2391 exiting the TB. */
2392 EXIT_PC_UPDATED,
2393 /* We are exiting the TB, but have neither emitted a goto_tb, nor
2394 updated the PC for the next instruction to be executed. */
2395 EXIT_PC_STALE,
2396 /* We are ending the TB with a noreturn function call, e.g. longjmp.
2397 No following code will be executed. */
2398 EXIT_NORETURN,
2399 } ExitStatus;
2400
2401 typedef enum DisasFacility {
2402 FAC_Z, /* zarch (default) */
2403 FAC_CASS, /* compare and swap and store */
2404 FAC_CASS2, /* compare and swap and store 2*/
2405 FAC_DFP, /* decimal floating point */
2406 FAC_DFPR, /* decimal floating point rounding */
2407 FAC_DO, /* distinct operands */
2408 FAC_EE, /* execute extensions */
2409 FAC_EI, /* extended immediate */
2410 FAC_FPE, /* floating point extension */
2411 FAC_FPSSH, /* floating point support sign handling */
2412 FAC_FPRGR, /* FPR-GR transfer */
2413 FAC_GIE, /* general instructions extension */
2414 FAC_HFP_MA, /* HFP multiply-and-add/subtract */
2415 FAC_HW, /* high-word */
2416 FAC_IEEEE_SIM, /* IEEE exception sumilation */
2417 FAC_LOC, /* load/store on condition */
2418 FAC_LD, /* long displacement */
2419 FAC_PC, /* population count */
2420 FAC_SCF, /* store clock fast */
2421 FAC_SFLE, /* store facility list extended */
2422 } DisasFacility;
2423
2424 struct DisasInsn {
2425 unsigned opc:16;
2426 DisasFormat fmt:6;
2427 DisasFacility fac:6;
2428
2429 const char *name;
2430
2431 void (*help_in1)(DisasContext *, DisasFields *, DisasOps *);
2432 void (*help_in2)(DisasContext *, DisasFields *, DisasOps *);
2433 void (*help_prep)(DisasContext *, DisasFields *, DisasOps *);
2434 void (*help_wout)(DisasContext *, DisasFields *, DisasOps *);
2435 void (*help_cout)(DisasContext *, DisasOps *);
2436 ExitStatus (*help_op)(DisasContext *, DisasOps *);
2437
2438 uint64_t data;
2439 };
2440
2441 /* ====================================================================== */
2442 /* Miscelaneous helpers, used by several operations. */
2443
2444 static void help_l2_shift(DisasContext *s, DisasFields *f,
2445 DisasOps *o, int mask)
2446 {
2447 int b2 = get_field(f, b2);
2448 int d2 = get_field(f, d2);
2449
2450 if (b2 == 0) {
2451 o->in2 = tcg_const_i64(d2 & mask);
2452 } else {
2453 o->in2 = get_address(s, 0, b2, d2);
2454 tcg_gen_andi_i64(o->in2, o->in2, mask);
2455 }
2456 }
2457
2458 static ExitStatus help_goto_direct(DisasContext *s, uint64_t dest)
2459 {
2460 if (dest == s->next_pc) {
2461 return NO_EXIT;
2462 }
2463 if (use_goto_tb(s, dest)) {
2464 gen_update_cc_op(s);
2465 tcg_gen_goto_tb(0);
2466 tcg_gen_movi_i64(psw_addr, dest);
2467 tcg_gen_exit_tb((tcg_target_long)s->tb);
2468 return EXIT_GOTO_TB;
2469 } else {
2470 tcg_gen_movi_i64(psw_addr, dest);
2471 return EXIT_PC_UPDATED;
2472 }
2473 }
2474
2475 static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
2476 bool is_imm, int imm, TCGv_i64 cdest)
2477 {
2478 ExitStatus ret;
2479 uint64_t dest = s->pc + 2 * imm;
2480 int lab;
2481
2482 /* Take care of the special cases first. */
2483 if (c->cond == TCG_COND_NEVER) {
2484 ret = NO_EXIT;
2485 goto egress;
2486 }
2487 if (is_imm) {
2488 if (dest == s->next_pc) {
2489 /* Branch to next. */
2490 ret = NO_EXIT;
2491 goto egress;
2492 }
2493 if (c->cond == TCG_COND_ALWAYS) {
2494 ret = help_goto_direct(s, dest);
2495 goto egress;
2496 }
2497 } else {
2498 if (TCGV_IS_UNUSED_I64(cdest)) {
2499 /* E.g. bcr %r0 -> no branch. */
2500 ret = NO_EXIT;
2501 goto egress;
2502 }
2503 if (c->cond == TCG_COND_ALWAYS) {
2504 tcg_gen_mov_i64(psw_addr, cdest);
2505 ret = EXIT_PC_UPDATED;
2506 goto egress;
2507 }
2508 }
2509
2510 if (use_goto_tb(s, s->next_pc)) {
2511 if (is_imm && use_goto_tb(s, dest)) {
2512 /* Both exits can use goto_tb. */
2513 gen_update_cc_op(s);
2514
2515 lab = gen_new_label();
2516 if (c->is_64) {
2517 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
2518 } else {
2519 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
2520 }
2521
2522 /* Branch not taken. */
2523 tcg_gen_goto_tb(0);
2524 tcg_gen_movi_i64(psw_addr, s->next_pc);
2525 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
2526
2527 /* Branch taken. */
2528 gen_set_label(lab);
2529 tcg_gen_goto_tb(1);
2530 tcg_gen_movi_i64(psw_addr, dest);
2531 tcg_gen_exit_tb((tcg_target_long)s->tb + 1);
2532
2533 ret = EXIT_GOTO_TB;
2534 } else {
2535 /* Fallthru can use goto_tb, but taken branch cannot. */
2536 /* Store taken branch destination before the brcond. This
2537 avoids having to allocate a new local temp to hold it.
2538 We'll overwrite this in the not taken case anyway. */
2539 if (!is_imm) {
2540 tcg_gen_mov_i64(psw_addr, cdest);
2541 }
2542
2543 lab = gen_new_label();
2544 if (c->is_64) {
2545 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
2546 } else {
2547 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
2548 }
2549
2550 /* Branch not taken. */
2551 gen_update_cc_op(s);
2552 tcg_gen_goto_tb(0);
2553 tcg_gen_movi_i64(psw_addr, s->next_pc);
2554 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
2555
2556 gen_set_label(lab);
2557 if (is_imm) {
2558 tcg_gen_movi_i64(psw_addr, dest);
2559 }
2560 ret = EXIT_PC_UPDATED;
2561 }
2562 } else {
2563 /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
2564 Most commonly we're single-stepping or some other condition that
2565 disables all use of goto_tb. Just update the PC and exit. */
2566
2567 TCGv_i64 next = tcg_const_i64(s->next_pc);
2568 if (is_imm) {
2569 cdest = tcg_const_i64(dest);
2570 }
2571
2572 if (c->is_64) {
2573 tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b,
2574 cdest, next);
2575 } else {
2576 TCGv_i32 t0 = tcg_temp_new_i32();
2577 TCGv_i64 t1 = tcg_temp_new_i64();
2578 TCGv_i64 z = tcg_const_i64(0);
2579 tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b);
2580 tcg_gen_extu_i32_i64(t1, t0);
2581 tcg_temp_free_i32(t0);
2582 tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next);
2583 tcg_temp_free_i64(t1);
2584 tcg_temp_free_i64(z);
2585 }
2586
2587 if (is_imm) {
2588 tcg_temp_free_i64(cdest);
2589 }
2590 tcg_temp_free_i64(next);
2591
2592 ret = EXIT_PC_UPDATED;
2593 }
2594
2595 egress:
2596 free_compare(c);
2597 return ret;
2598 }
2599
2600 /* ====================================================================== */
2601 /* The operations. These perform the bulk of the work for any insn,
2602 usually after the operands have been loaded and output initialized. */
2603
2604 static ExitStatus op_abs(DisasContext *s, DisasOps *o)
2605 {
2606 gen_helper_abs_i64(o->out, o->in2);
2607 return NO_EXIT;
2608 }
2609
2610 static ExitStatus op_add(DisasContext *s, DisasOps *o)
2611 {
2612 tcg_gen_add_i64(o->out, o->in1, o->in2);
2613 return NO_EXIT;
2614 }
2615
2616 static ExitStatus op_addc(DisasContext *s, DisasOps *o)
2617 {
2618 TCGv_i64 cc;
2619
2620 tcg_gen_add_i64(o->out, o->in1, o->in2);
2621
2622 /* XXX possible optimization point */
2623 gen_op_calc_cc(s);
2624 cc = tcg_temp_new_i64();
2625 tcg_gen_extu_i32_i64(cc, cc_op);
2626 tcg_gen_shri_i64(cc, cc, 1);
2627
2628 tcg_gen_add_i64(o->out, o->out, cc);
2629 tcg_temp_free_i64(cc);
2630 return NO_EXIT;
2631 }
2632
2633 static ExitStatus op_and(DisasContext *s, DisasOps *o)
2634 {
2635 tcg_gen_and_i64(o->out, o->in1, o->in2);
2636 return NO_EXIT;
2637 }
2638
2639 static ExitStatus op_andi(DisasContext *s, DisasOps *o)
2640 {
2641 int shift = s->insn->data & 0xff;
2642 int size = s->insn->data >> 8;
2643 uint64_t mask = ((1ull << size) - 1) << shift;
2644
2645 assert(!o->g_in2);
2646 tcg_gen_shli_i64(o->in2, o->in2, shift);
2647 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
2648 tcg_gen_and_i64(o->out, o->in1, o->in2);
2649
2650 /* Produce the CC from only the bits manipulated. */
2651 tcg_gen_andi_i64(cc_dst, o->out, mask);
2652 set_cc_nz_u64(s, cc_dst);
2653 return NO_EXIT;
2654 }
2655
2656 static ExitStatus op_bas(DisasContext *s, DisasOps *o)
2657 {
2658 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
2659 if (!TCGV_IS_UNUSED_I64(o->in2)) {
2660 tcg_gen_mov_i64(psw_addr, o->in2);
2661 return EXIT_PC_UPDATED;
2662 } else {
2663 return NO_EXIT;
2664 }
2665 }
2666
2667 static ExitStatus op_basi(DisasContext *s, DisasOps *o)
2668 {
2669 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
2670 return help_goto_direct(s, s->pc + 2 * get_field(s->fields, i2));
2671 }
2672
2673 static ExitStatus op_bc(DisasContext *s, DisasOps *o)
2674 {
2675 int m1 = get_field(s->fields, m1);
2676 bool is_imm = have_field(s->fields, i2);
2677 int imm = is_imm ? get_field(s->fields, i2) : 0;
2678 DisasCompare c;
2679
2680 disas_jcc(s, &c, m1);
2681 return help_branch(s, &c, is_imm, imm, o->in2);
2682 }
2683
2684 static ExitStatus op_bct32(DisasContext *s, DisasOps *o)
2685 {
2686 int r1 = get_field(s->fields, r1);
2687 bool is_imm = have_field(s->fields, i2);
2688 int imm = is_imm ? get_field(s->fields, i2) : 0;
2689 DisasCompare c;
2690 TCGv_i64 t;
2691
2692 c.cond = TCG_COND_NE;
2693 c.is_64 = false;
2694 c.g1 = false;
2695 c.g2 = false;
2696
2697 t = tcg_temp_new_i64();
2698 tcg_gen_subi_i64(t, regs[r1], 1);
2699 store_reg32_i64(r1, t);
2700 c.u.s32.a = tcg_temp_new_i32();
2701 c.u.s32.b = tcg_const_i32(0);
2702 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
2703 tcg_temp_free_i64(t);
2704
2705 return help_branch(s, &c, is_imm, imm, o->in2);
2706 }
2707
2708 static ExitStatus op_bct64(DisasContext *s, DisasOps *o)
2709 {
2710 int r1 = get_field(s->fields, r1);
2711 bool is_imm = have_field(s->fields, i2);
2712 int imm = is_imm ? get_field(s->fields, i2) : 0;
2713 DisasCompare c;
2714
2715 c.cond = TCG_COND_NE;
2716 c.is_64 = true;
2717 c.g1 = true;
2718 c.g2 = false;
2719
2720 tcg_gen_subi_i64(regs[r1], regs[r1], 1);
2721 c.u.s64.a = regs[r1];
2722 c.u.s64.b = tcg_const_i64(0);
2723
2724 return help_branch(s, &c, is_imm, imm, o->in2);
2725 }
2726
2727 static ExitStatus op_clc(DisasContext *s, DisasOps *o)
2728 {
2729 int l = get_field(s->fields, l1);
2730 TCGv_i32 vl;
2731
2732 switch (l + 1) {
2733 case 1:
2734 tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s));
2735 tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s));
2736 break;
2737 case 2:
2738 tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s));
2739 tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s));
2740 break;
2741 case 4:
2742 tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s));
2743 tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s));
2744 break;
2745 case 8:
2746 tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s));
2747 tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
2748 break;
2749 default:
2750 potential_page_fault(s);
2751 vl = tcg_const_i32(l);
2752 gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
2753 tcg_temp_free_i32(vl);
2754 set_cc_static(s);
2755 return NO_EXIT;
2756 }
2757 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
2758 return NO_EXIT;
2759 }
2760
2761 static ExitStatus op_clcle(DisasContext *s, DisasOps *o)
2762 {
2763 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2764 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2765 potential_page_fault(s);
2766 gen_helper_clcle(cc_op, cpu_env, r1, o->in2, r3);
2767 tcg_temp_free_i32(r1);
2768 tcg_temp_free_i32(r3);
2769 set_cc_static(s);
2770 return NO_EXIT;
2771 }
2772
2773 static ExitStatus op_cvd(DisasContext *s, DisasOps *o)
2774 {
2775 TCGv_i64 t1 = tcg_temp_new_i64();
2776 TCGv_i32 t2 = tcg_temp_new_i32();
2777 tcg_gen_trunc_i64_i32(t2, o->in1);
2778 gen_helper_cvd(t1, t2);
2779 tcg_temp_free_i32(t2);
2780 tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
2781 tcg_temp_free_i64(t1);
2782 return NO_EXIT;
2783 }
2784
2785 #ifndef CONFIG_USER_ONLY
2786 static ExitStatus op_diag(DisasContext *s, DisasOps *o)
2787 {
2788 TCGv_i32 tmp;
2789
2790 check_privileged(s);
2791 potential_page_fault(s);
2792
2793 /* We pretend the format is RX_a so that D2 is the field we want. */
2794 tmp = tcg_const_i32(get_field(s->fields, d2) & 0xfff);
2795 gen_helper_diag(regs[2], cpu_env, tmp, regs[2], regs[1]);
2796 tcg_temp_free_i32(tmp);
2797 return NO_EXIT;
2798 }
2799 #endif
2800
2801 static ExitStatus op_divs32(DisasContext *s, DisasOps *o)
2802 {
2803 gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2);
2804 return_low128(o->out);
2805 return NO_EXIT;
2806 }
2807
2808 static ExitStatus op_divu32(DisasContext *s, DisasOps *o)
2809 {
2810 gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2);
2811 return_low128(o->out);
2812 return NO_EXIT;
2813 }
2814
2815 static ExitStatus op_divs64(DisasContext *s, DisasOps *o)
2816 {
2817 gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2);
2818 return_low128(o->out);
2819 return NO_EXIT;
2820 }
2821
2822 static ExitStatus op_divu64(DisasContext *s, DisasOps *o)
2823 {
2824 gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2);
2825 return_low128(o->out);
2826 return NO_EXIT;
2827 }
2828
2829 static ExitStatus op_ex(DisasContext *s, DisasOps *o)
2830 {
2831 /* ??? Perhaps a better way to implement EXECUTE is to set a bit in
2832 tb->flags, (ab)use the tb->cs_base field as the address of
2833 the template in memory, and grab 8 bits of tb->flags/cflags for
2834 the contents of the register. We would then recognize all this
2835 in gen_intermediate_code_internal, generating code for exactly
2836 one instruction. This new TB then gets executed normally.
2837
2838 On the other hand, this seems to be mostly used for modifying
2839 MVC inside of memcpy, which needs a helper call anyway. So
2840 perhaps this doesn't bear thinking about any further. */
2841
2842 TCGv_i64 tmp;
2843
2844 update_psw_addr(s);
2845 gen_op_calc_cc(s);
2846
2847 tmp = tcg_const_i64(s->next_pc);
2848 gen_helper_ex(cc_op, cpu_env, cc_op, o->in1, o->in2, tmp);
2849 tcg_temp_free_i64(tmp);
2850
2851 set_cc_static(s);
2852 return NO_EXIT;
2853 }
2854
2855 static ExitStatus op_icm(DisasContext *s, DisasOps *o)
2856 {
2857 int m3 = get_field(s->fields, m3);
2858 int pos, len, base = s->insn->data;
2859 TCGv_i64 tmp = tcg_temp_new_i64();
2860 uint64_t ccm;
2861
2862 switch (m3) {
2863 case 0xf:
2864 /* Effectively a 32-bit load. */
2865 tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
2866 len = 32;
2867 goto one_insert;
2868
2869 case 0xc:
2870 case 0x6:
2871 case 0x3:
2872 /* Effectively a 16-bit load. */
2873 tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
2874 len = 16;
2875 goto one_insert;
2876
2877 case 0x8:
2878 case 0x4:
2879 case 0x2:
2880 case 0x1:
2881 /* Effectively an 8-bit load. */
2882 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2883 len = 8;
2884 goto one_insert;
2885
2886 one_insert:
2887 pos = base + ctz32(m3) * 8;
2888 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len);
2889 ccm = ((1ull << len) - 1) << pos;
2890 break;
2891
2892 default:
2893 /* This is going to be a sequence of loads and inserts. */
2894 pos = base + 32 - 8;
2895 ccm = 0;
2896 while (m3) {
2897 if (m3 & 0x8) {
2898 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2899 tcg_gen_addi_i64(o->in2, o->in2, 1);
2900 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
2901 ccm |= 0xff << pos;
2902 }
2903 m3 = (m3 << 1) & 0xf;
2904 pos -= 8;
2905 }
2906 break;
2907 }
2908
2909 tcg_gen_movi_i64(tmp, ccm);
2910 gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out);
2911 tcg_temp_free_i64(tmp);
2912 return NO_EXIT;
2913 }
2914
2915 static ExitStatus op_insi(DisasContext *s, DisasOps *o)
2916 {
2917 int shift = s->insn->data & 0xff;
2918 int size = s->insn->data >> 8;
2919 tcg_gen_deposit_i64(o->out, o->in1, o->in2, shift, size);
2920 return NO_EXIT;
2921 }
2922
2923 static ExitStatus op_ld8s(DisasContext *s, DisasOps *o)
2924 {
2925 tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
2926 return NO_EXIT;
2927 }
2928
2929 static ExitStatus op_ld8u(DisasContext *s, DisasOps *o)
2930 {
2931 tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
2932 return NO_EXIT;
2933 }
2934
2935 static ExitStatus op_ld16s(DisasContext *s, DisasOps *o)
2936 {
2937 tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
2938 return NO_EXIT;
2939 }
2940
2941 static ExitStatus op_ld16u(DisasContext *s, DisasOps *o)
2942 {
2943 tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
2944 return NO_EXIT;
2945 }
2946
2947 static ExitStatus op_ld32s(DisasContext *s, DisasOps *o)
2948 {
2949 tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s));
2950 return NO_EXIT;
2951 }
2952
2953 static ExitStatus op_ld32u(DisasContext *s, DisasOps *o)
2954 {
2955 tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
2956 return NO_EXIT;
2957 }
2958
2959 static ExitStatus op_ld64(DisasContext *s, DisasOps *o)
2960 {
2961 tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
2962 return NO_EXIT;
2963 }
2964
2965 #ifndef CONFIG_USER_ONLY
2966 static ExitStatus op_lpsw(DisasContext *s, DisasOps *o)
2967 {
2968 TCGv_i64 t1, t2;
2969
2970 check_privileged(s);
2971
2972 t1 = tcg_temp_new_i64();
2973 t2 = tcg_temp_new_i64();
2974 tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
2975 tcg_gen_addi_i64(o->in2, o->in2, 4);
2976 tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s));
2977 /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
2978 tcg_gen_shli_i64(t1, t1, 32);
2979 gen_helper_load_psw(cpu_env, t1, t2);
2980 tcg_temp_free_i64(t1);
2981 tcg_temp_free_i64(t2);
2982 return EXIT_NORETURN;
2983 }
2984 #endif
2985
2986 static ExitStatus op_lam(DisasContext *s, DisasOps *o)
2987 {
2988 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2989 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2990 potential_page_fault(s);
2991 gen_helper_lam(cpu_env, r1, o->in2, r3);
2992 tcg_temp_free_i32(r1);
2993 tcg_temp_free_i32(r3);
2994 return NO_EXIT;
2995 }
2996
2997 static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
2998 {
2999 int r1 = get_field(s->fields, r1);
3000 int r3 = get_field(s->fields, r3);
3001 TCGv_i64 t = tcg_temp_new_i64();
3002 TCGv_i64 t4 = tcg_const_i64(4);
3003
3004 while (1) {
3005 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
3006 store_reg32_i64(r1, t);
3007 if (r1 == r3) {
3008 break;
3009 }
3010 tcg_gen_add_i64(o->in2, o->in2, t4);
3011 r1 = (r1 + 1) & 15;
3012 }
3013
3014 tcg_temp_free_i64(t);
3015 tcg_temp_free_i64(t4);
3016 return NO_EXIT;
3017 }
3018
3019 static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
3020 {
3021 int r1 = get_field(s->fields, r1);
3022 int r3 = get_field(s->fields, r3);
3023 TCGv_i64 t = tcg_temp_new_i64();
3024 TCGv_i64 t4 = tcg_const_i64(4);
3025
3026 while (1) {
3027 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
3028 store_reg32h_i64(r1, t);
3029 if (r1 == r3) {
3030 break;
3031 }
3032 tcg_gen_add_i64(o->in2, o->in2, t4);
3033 r1 = (r1 + 1) & 15;
3034 }
3035
3036 tcg_temp_free_i64(t);
3037 tcg_temp_free_i64(t4);
3038 return NO_EXIT;
3039 }
3040
3041 static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
3042 {
3043 int r1 = get_field(s->fields, r1);
3044 int r3 = get_field(s->fields, r3);
3045 TCGv_i64 t8 = tcg_const_i64(8);
3046
3047 while (1) {
3048 tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
3049 if (r1 == r3) {
3050 break;
3051 }
3052 tcg_gen_add_i64(o->in2, o->in2, t8);
3053 r1 = (r1 + 1) & 15;
3054 }
3055
3056 tcg_temp_free_i64(t8);
3057 return NO_EXIT;
3058 }
3059
3060 static ExitStatus op_mov2(DisasContext *s, DisasOps *o)
3061 {
3062 o->out = o->in2;
3063 o->g_out = o->g_in2;
3064 TCGV_UNUSED_I64(o->in2);
3065 o->g_in2 = false;
3066 return NO_EXIT;
3067 }
3068
3069 static ExitStatus op_movx(DisasContext *s, DisasOps *o)
3070 {
3071 o->out = o->in1;
3072 o->out2 = o->in2;
3073 o->g_out = o->g_in1;
3074 o->g_out2 = o->g_in2;
3075 TCGV_UNUSED_I64(o->in1);
3076 TCGV_UNUSED_I64(o->in2);
3077 o->g_in1 = o->g_in2 = false;
3078 return NO_EXIT;
3079 }
3080
3081 static ExitStatus op_mvc(DisasContext *s, DisasOps *o)
3082 {
3083 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3084 potential_page_fault(s);
3085 gen_helper_mvc(cpu_env, l, o->addr1, o->in2);
3086 tcg_temp_free_i32(l);
3087 return NO_EXIT;
3088 }
3089
3090 static ExitStatus op_mvcl(DisasContext *s, DisasOps *o)
3091 {
3092 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3093 TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
3094 potential_page_fault(s);
3095 gen_helper_mvcl(cc_op, cpu_env, r1, r2);
3096 tcg_temp_free_i32(r1);
3097 tcg_temp_free_i32(r2);
3098 set_cc_static(s);
3099 return NO_EXIT;
3100 }
3101
3102 static ExitStatus op_mvcle(DisasContext *s, DisasOps *o)
3103 {
3104 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3105 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
3106 potential_page_fault(s);
3107 gen_helper_mvcle(cc_op, cpu_env, r1, o->in2, r3);
3108 tcg_temp_free_i32(r1);
3109 tcg_temp_free_i32(r3);
3110 set_cc_static(s);
3111 return NO_EXIT;
3112 }
3113
3114 static ExitStatus op_mul(DisasContext *s, DisasOps *o)
3115 {
3116 tcg_gen_mul_i64(o->out, o->in1, o->in2);
3117 return NO_EXIT;
3118 }
3119
3120 static ExitStatus op_mul128(DisasContext *s, DisasOps *o)
3121 {
3122 gen_helper_mul128(o->out, cpu_env, o->in1, o->in2);
3123 return_low128(o->out2);
3124 return NO_EXIT;
3125 }
3126
3127 static ExitStatus op_nabs(DisasContext *s, DisasOps *o)
3128 {
3129 gen_helper_nabs_i64(o->out, o->in2);
3130 return NO_EXIT;
3131 }
3132
3133 static ExitStatus op_nc(DisasContext *s, DisasOps *o)
3134 {
3135 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3136 potential_page_fault(s);
3137 gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2);
3138 tcg_temp_free_i32(l);
3139 set_cc_static(s);
3140 return NO_EXIT;
3141 }
3142
3143 static ExitStatus op_neg(DisasContext *s, DisasOps *o)
3144 {
3145 tcg_gen_neg_i64(o->out, o->in2);
3146 return NO_EXIT;
3147 }
3148
3149 static ExitStatus op_oc(DisasContext *s, DisasOps *o)
3150 {
3151 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3152 potential_page_fault(s);
3153 gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2);
3154 tcg_temp_free_i32(l);
3155 set_cc_static(s);
3156 return NO_EXIT;
3157 }
3158
3159 static ExitStatus op_or(DisasContext *s, DisasOps *o)
3160 {
3161 tcg_gen_or_i64(o->out, o->in1, o->in2);
3162 return NO_EXIT;
3163 }
3164
3165 static ExitStatus op_ori(DisasContext *s, DisasOps *o)
3166 {
3167 int shift = s->insn->data & 0xff;
3168 int size = s->insn->data >> 8;
3169 uint64_t mask = ((1ull << size) - 1) << shift;
3170
3171 assert(!o->g_in2);
3172 tcg_gen_shli_i64(o->in2, o->in2, shift);
3173 tcg_gen_or_i64(o->out, o->in1, o->in2);
3174
3175 /* Produce the CC from only the bits manipulated. */
3176 tcg_gen_andi_i64(cc_dst, o->out, mask);
3177 set_cc_nz_u64(s, cc_dst);
3178 return NO_EXIT;
3179 }
3180
3181 static ExitStatus op_rll32(DisasContext *s, DisasOps *o)
3182 {
3183 TCGv_i32 t1 = tcg_temp_new_i32();
3184 TCGv_i32 t2 = tcg_temp_new_i32();
3185 TCGv_i32 to = tcg_temp_new_i32();
3186 tcg_gen_trunc_i64_i32(t1, o->in1);
3187 tcg_gen_trunc_i64_i32(t2, o->in2);
3188 tcg_gen_rotl_i32(to, t1, t2);
3189 tcg_gen_extu_i32_i64(o->out, to);
3190 tcg_temp_free_i32(t1);
3191 tcg_temp_free_i32(t2);
3192 tcg_temp_free_i32(to);
3193 return NO_EXIT;
3194 }
3195
3196 static ExitStatus op_rll64(DisasContext *s, DisasOps *o)
3197 {
3198 tcg_gen_rotl_i64(o->out, o->in1, o->in2);
3199 return NO_EXIT;
3200 }
3201
3202 static ExitStatus op_sla(DisasContext *s, DisasOps *o)
3203 {
3204 uint64_t sign = 1ull << s->insn->data;
3205 enum cc_op cco = s->insn->data == 31 ? CC_OP_SLA_32 : CC_OP_SLA_64;
3206 gen_op_update2_cc_i64(s, cco, o->in1, o->in2);
3207 tcg_gen_shl_i64(o->out, o->in1, o->in2);
3208 /* The arithmetic left shift is curious in that it does not affect
3209 the sign bit. Copy that over from the source unchanged. */
3210 tcg_gen_andi_i64(o->out, o->out, ~sign);
3211 tcg_gen_andi_i64(o->in1, o->in1, sign);
3212 tcg_gen_or_i64(o->out, o->out, o->in1);
3213 return NO_EXIT;
3214 }
3215
3216 static ExitStatus op_sll(DisasContext *s, DisasOps *o)
3217 {
3218 tcg_gen_shl_i64(o->out, o->in1, o->in2);
3219 return NO_EXIT;
3220 }
3221
3222 static ExitStatus op_sra(DisasContext *s, DisasOps *o)
3223 {
3224 tcg_gen_sar_i64(o->out, o->in1, o->in2);
3225 return NO_EXIT;
3226 }
3227
3228 static ExitStatus op_srl(DisasContext *s, DisasOps *o)
3229 {
3230 tcg_gen_shr_i64(o->out, o->in1, o->in2);
3231 return NO_EXIT;
3232 }
3233
3234 #ifndef CONFIG_USER_ONLY
3235 static ExitStatus op_ssm(DisasContext *s, DisasOps *o)
3236 {
3237 check_privileged(s);
3238 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8);
3239 return NO_EXIT;
3240 }
3241
3242 static ExitStatus op_stnosm(DisasContext *s, DisasOps *o)
3243 {
3244 uint64_t i2 = get_field(s->fields, i2);
3245 TCGv_i64 t;
3246
3247 check_privileged(s);
3248
3249 /* It is important to do what the instruction name says: STORE THEN.
3250 If we let the output hook perform the store then if we fault and
3251 restart, we'll have the wrong SYSTEM MASK in place. */
3252 t = tcg_temp_new_i64();
3253 tcg_gen_shri_i64(t, psw_mask, 56);
3254 tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
3255 tcg_temp_free_i64(t);
3256
3257 if (s->fields->op == 0xac) {
3258 tcg_gen_andi_i64(psw_mask, psw_mask,
3259 (i2 << 56) | 0x00ffffffffffffffull);
3260 } else {
3261 tcg_gen_ori_i64(psw_mask, psw_mask, i2 << 56);
3262 }
3263 return NO_EXIT;
3264 }
3265 #endif
3266
3267 static ExitStatus op_st8(DisasContext *s, DisasOps *o)
3268 {
3269 tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
3270 return NO_EXIT;
3271 }
3272
3273 static ExitStatus op_st16(DisasContext *s, DisasOps *o)
3274 {
3275 tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
3276 return NO_EXIT;
3277 }
3278
3279 static ExitStatus op_st32(DisasContext *s, DisasOps *o)
3280 {
3281 tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s));
3282 return NO_EXIT;
3283 }
3284
3285 static ExitStatus op_st64(DisasContext *s, DisasOps *o)
3286 {
3287 tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
3288 return NO_EXIT;
3289 }
3290
3291 static ExitStatus op_stam(DisasContext *s, DisasOps *o)
3292 {
3293 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3294 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
3295 potential_page_fault(s);
3296 gen_helper_stam(cpu_env, r1, o->in2, r3);
3297 tcg_temp_free_i32(r1);
3298 tcg_temp_free_i32(r3);
3299 return NO_EXIT;
3300 }
3301
3302 static ExitStatus op_stm(DisasContext *s, DisasOps *o)
3303 {
3304 int r1 = get_field(s->fields, r1);
3305 int r3 = get_field(s->fields, r3);
3306 int size = s->insn->data;
3307 TCGv_i64 tsize = tcg_const_i64(size);
3308
3309 while (1) {
3310 if (size == 8) {
3311 tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
3312 } else {
3313 tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s));
3314 }
3315 if (r1 == r3) {
3316 break;
3317 }
3318 tcg_gen_add_i64(o->in2, o->in2, tsize);
3319 r1 = (r1 + 1) & 15;
3320 }
3321
3322 tcg_temp_free_i64(tsize);
3323 return NO_EXIT;
3324 }
3325
3326 static ExitStatus op_stmh(DisasContext *s, DisasOps *o)
3327 {
3328 int r1 = get_field(s->fields, r1);
3329 int r3 = get_field(s->fields, r3);
3330 TCGv_i64 t = tcg_temp_new_i64();
3331 TCGv_i64 t4 = tcg_const_i64(4);
3332 TCGv_i64 t32 = tcg_const_i64(32);
3333
3334 while (1) {
3335 tcg_gen_shl_i64(t, regs[r1], t32);
3336 tcg_gen_qemu_st32(t, o->in2, get_mem_index(s));
3337 if (r1 == r3) {
3338 break;
3339 }
3340 tcg_gen_add_i64(o->in2, o->in2, t4);
3341 r1 = (r1 + 1) & 15;
3342 }
3343
3344 tcg_temp_free_i64(t);
3345 tcg_temp_free_i64(t4);
3346 tcg_temp_free_i64(t32);
3347 return NO_EXIT;
3348 }
3349
3350 static ExitStatus op_sub(DisasContext *s, DisasOps *o)
3351 {
3352 tcg_gen_sub_i64(o->out, o->in1, o->in2);
3353 return NO_EXIT;
3354 }
3355
3356 static ExitStatus op_subb(DisasContext *s, DisasOps *o)
3357 {
3358 TCGv_i64 cc;
3359
3360 assert(!o->g_in2);
3361 tcg_gen_not_i64(o->in2, o->in2);
3362 tcg_gen_add_i64(o->out, o->in1, o->in2);
3363
3364 /* XXX possible optimization point */
3365 gen_op_calc_cc(s);
3366 cc = tcg_temp_new_i64();
3367 tcg_gen_extu_i32_i64(cc, cc_op);
3368 tcg_gen_shri_i64(cc, cc, 1);
3369 tcg_gen_add_i64(o->out, o->out, cc);
3370 tcg_temp_free_i64(cc);
3371 return NO_EXIT;
3372 }
3373
3374 static ExitStatus op_svc(DisasContext *s, DisasOps *o)
3375 {
3376 TCGv_i32 t;
3377
3378 update_psw_addr(s);
3379 gen_op_calc_cc(s);
3380
3381 t = tcg_const_i32(get_field(s->fields, i1) & 0xff);
3382 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code));
3383 tcg_temp_free_i32(t);
3384
3385 t = tcg_const_i32(s->next_pc - s->pc);
3386 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen));
3387 tcg_temp_free_i32(t);
3388
3389 gen_exception(EXCP_SVC);
3390 return EXIT_NORETURN;
3391 }
3392
3393 static ExitStatus op_tr(DisasContext *s, DisasOps *o)
3394 {
3395 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3396 potential_page_fault(s);
3397 gen_helper_tr(cpu_env, l, o->addr1, o->in2);
3398 tcg_temp_free_i32(l);
3399 set_cc_static(s);
3400 return NO_EXIT;
3401 }
3402
3403 static ExitStatus op_unpk(DisasContext *s, DisasOps *o)
3404 {
3405 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3406 potential_page_fault(s);
3407 gen_helper_unpk(cpu_env, l, o->addr1, o->in2);
3408 tcg_temp_free_i32(l);
3409 return NO_EXIT;
3410 }
3411
3412 static ExitStatus op_xc(DisasContext *s, DisasOps *o)
3413 {
3414 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3415 potential_page_fault(s);
3416 gen_helper_xc(cc_op, cpu_env, l, o->addr1, o->in2);
3417 tcg_temp_free_i32(l);
3418 set_cc_static(s);
3419 return NO_EXIT;
3420 }
3421
3422 static ExitStatus op_xor(DisasContext *s, DisasOps *o)
3423 {
3424 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3425 return NO_EXIT;
3426 }
3427
3428 static ExitStatus op_xori(DisasContext *s, DisasOps *o)
3429 {
3430 int shift = s->insn->data & 0xff;
3431 int size = s->insn->data >> 8;
3432 uint64_t mask = ((1ull << size) - 1) << shift;
3433
3434 assert(!o->g_in2);
3435 tcg_gen_shli_i64(o->in2, o->in2, shift);
3436 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3437
3438 /* Produce the CC from only the bits manipulated. */
3439 tcg_gen_andi_i64(cc_dst, o->out, mask);
3440 set_cc_nz_u64(s, cc_dst);
3441 return NO_EXIT;
3442 }
3443
3444 /* ====================================================================== */
3445 /* The "Cc OUTput" generators. Given the generated output (and in some cases
3446 the original inputs), update the various cc data structures in order to
3447 be able to compute the new condition code. */
3448
3449 static void cout_abs32(DisasContext *s, DisasOps *o)
3450 {
3451 gen_op_update1_cc_i64(s, CC_OP_ABS_32, o->out);
3452 }
3453
3454 static void cout_abs64(DisasContext *s, DisasOps *o)
3455 {
3456 gen_op_update1_cc_i64(s, CC_OP_ABS_64, o->out);
3457 }
3458
3459 static void cout_adds32(DisasContext *s, DisasOps *o)
3460 {
3461 gen_op_update3_cc_i64(s, CC_OP_ADD_32, o->in1, o->in2, o->out);
3462 }
3463
3464 static void cout_adds64(DisasContext *s, DisasOps *o)
3465 {
3466 gen_op_update3_cc_i64(s, CC_OP_ADD_64, o->in1, o->in2, o->out);
3467 }
3468
3469 static void cout_addu32(DisasContext *s, DisasOps *o)
3470 {
3471 gen_op_update3_cc_i64(s, CC_OP_ADDU_32, o->in1, o->in2, o->out);
3472 }
3473
3474 static void cout_addu64(DisasContext *s, DisasOps *o)
3475 {
3476 gen_op_update3_cc_i64(s, CC_OP_ADDU_64, o->in1, o->in2, o->out);
3477 }
3478
3479 static void cout_addc32(DisasContext *s, DisasOps *o)
3480 {
3481 gen_op_update3_cc_i64(s, CC_OP_ADDC_32, o->in1, o->in2, o->out);
3482 }
3483
3484 static void cout_addc64(DisasContext *s, DisasOps *o)
3485 {
3486 gen_op_update3_cc_i64(s, CC_OP_ADDC_64, o->in1, o->in2, o->out);
3487 }
3488
3489 static void cout_cmps32(DisasContext *s, DisasOps *o)
3490 {
3491 gen_op_update2_cc_i64(s, CC_OP_LTGT_32, o->in1, o->in2);
3492 }
3493
3494 static void cout_cmps64(DisasContext *s, DisasOps *o)
3495 {
3496 gen_op_update2_cc_i64(s, CC_OP_LTGT_64, o->in1, o->in2);
3497 }
3498
3499 static void cout_cmpu32(DisasContext *s, DisasOps *o)
3500 {
3501 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_32, o->in1, o->in2);
3502 }
3503
3504 static void cout_cmpu64(DisasContext *s, DisasOps *o)
3505 {
3506 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, o->in1, o->in2);
3507 }
3508
3509 static void cout_nabs32(DisasContext *s, DisasOps *o)
3510 {
3511 gen_op_update1_cc_i64(s, CC_OP_NABS_32, o->out);
3512 }
3513
3514 static void cout_nabs64(DisasContext *s, DisasOps *o)
3515 {
3516 gen_op_update1_cc_i64(s, CC_OP_NABS_64, o->out);
3517 }
3518
3519 static void cout_neg32(DisasContext *s, DisasOps *o)
3520 {
3521 gen_op_update1_cc_i64(s, CC_OP_COMP_32, o->out);
3522 }
3523
3524 static void cout_neg64(DisasContext *s, DisasOps *o)
3525 {
3526 gen_op_update1_cc_i64(s, CC_OP_COMP_64, o->out);
3527 }
3528
3529 static void cout_nz32(DisasContext *s, DisasOps *o)
3530 {
3531 tcg_gen_ext32u_i64(cc_dst, o->out);
3532 gen_op_update1_cc_i64(s, CC_OP_NZ, cc_dst);
3533 }
3534
3535 static void cout_nz64(DisasContext *s, DisasOps *o)
3536 {
3537 gen_op_update1_cc_i64(s, CC_OP_NZ, o->out);
3538 }
3539
3540 static void cout_s32(DisasContext *s, DisasOps *o)
3541 {
3542 gen_op_update1_cc_i64(s, CC_OP_LTGT0_32, o->out);
3543 }
3544
3545 static void cout_s64(DisasContext *s, DisasOps *o)
3546 {
3547 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, o->out);
3548 }
3549
3550 static void cout_subs32(DisasContext *s, DisasOps *o)
3551 {
3552 gen_op_update3_cc_i64(s, CC_OP_SUB_32, o->in1, o->in2, o->out);
3553 }
3554
3555 static void cout_subs64(DisasContext *s, DisasOps *o)
3556 {
3557 gen_op_update3_cc_i64(s, CC_OP_SUB_64, o->in1, o->in2, o->out);
3558 }
3559
3560 static void cout_subu32(DisasContext *s, DisasOps *o)
3561 {
3562 gen_op_update3_cc_i64(s, CC_OP_SUBU_32, o->in1, o->in2, o->out);
3563 }
3564
3565 static void cout_subu64(DisasContext *s, DisasOps *o)
3566 {
3567 gen_op_update3_cc_i64(s, CC_OP_SUBU_64, o->in1, o->in2, o->out);
3568 }
3569
3570 static void cout_subb32(DisasContext *s, DisasOps *o)
3571 {
3572 gen_op_update3_cc_i64(s, CC_OP_SUBB_32, o->in1, o->in2, o->out);
3573 }
3574
3575 static void cout_subb64(DisasContext *s, DisasOps *o)
3576 {
3577 gen_op_update3_cc_i64(s, CC_OP_SUBB_64, o->in1, o->in2, o->out);
3578 }
3579
3580 static void cout_tm32(DisasContext *s, DisasOps *o)
3581 {
3582 gen_op_update2_cc_i64(s, CC_OP_TM_32, o->in1, o->in2);
3583 }
3584
3585 static void cout_tm64(DisasContext *s, DisasOps *o)
3586 {
3587 gen_op_update2_cc_i64(s, CC_OP_TM_64, o->in1, o->in2);
3588 }
3589
3590 /* ====================================================================== */
3591 /* The "PREPeration" generators. These initialize the DisasOps.OUT fields
3592 with the TCG register to which we will write. Used in combination with
3593 the "wout" generators, in some cases we need a new temporary, and in
3594 some cases we can write to a TCG global. */
3595
3596 static void prep_new(DisasContext *s, DisasFields *f, DisasOps *o)
3597 {
3598 o->out = tcg_temp_new_i64();
3599 }
3600
3601 static void prep_new_P(DisasContext *s, DisasFields *f, DisasOps *o)
3602 {
3603 o->out = tcg_temp_new_i64();
3604 o->out2 = tcg_temp_new_i64();
3605 }
3606
3607 static void prep_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3608 {
3609 o->out = regs[get_field(f, r1)];
3610 o->g_out = true;
3611 }
3612
3613 static void prep_r1_P(DisasContext *s, DisasFields *f, DisasOps *o)
3614 {
3615 /* ??? Specification exception: r1 must be even. */
3616 int r1 = get_field(f, r1);
3617 o->out = regs[r1];
3618 o->out2 = regs[(r1 + 1) & 15];
3619 o->g_out = o->g_out2 = true;
3620 }
3621
3622 /* ====================================================================== */
3623 /* The "Write OUTput" generators. These generally perform some non-trivial
3624 copy of data to TCG globals, or to main memory. The trivial cases are
3625 generally handled by having a "prep" generator install the TCG global
3626 as the destination of the operation. */
3627
3628 static void wout_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3629 {
3630 store_reg(get_field(f, r1), o->out);
3631 }
3632
3633 static void wout_r1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3634 {
3635 int r1 = get_field(f, r1);
3636 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8);
3637 }
3638
3639 static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3640 {
3641 store_reg32_i64(get_field(f, r1), o->out);
3642 }
3643
3644 static void wout_r1_P32(DisasContext *s, DisasFields *f, DisasOps *o)
3645 {
3646 /* ??? Specification exception: r1 must be even. */
3647 int r1 = get_field(f, r1);
3648 store_reg32_i64(r1, o->out);
3649 store_reg32_i64((r1 + 1) & 15, o->out2);
3650 }
3651
3652 static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3653 {
3654 /* ??? Specification exception: r1 must be even. */
3655 int r1 = get_field(f, r1);
3656 store_reg32_i64((r1 + 1) & 15, o->out);
3657 tcg_gen_shri_i64(o->out, o->out, 32);
3658 store_reg32_i64(r1, o->out);
3659 }
3660
3661 static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3662 {
3663 store_freg32_i64(get_field(f, r1), o->out);
3664 }
3665
3666 static void wout_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3667 {
3668 store_freg(get_field(f, r1), o->out);
3669 }
3670
3671 static void wout_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3672 {
3673 int f1 = get_field(s->fields, r1);
3674 store_freg(f1, o->out);
3675 store_freg((f1 + 2) & 15, o->out2);
3676 }
3677
3678 static void wout_cond_r1r2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3679 {
3680 if (get_field(f, r1) != get_field(f, r2)) {
3681 store_reg32_i64(get_field(f, r1), o->out);
3682 }
3683 }
3684
3685 static void wout_cond_e1e2(DisasContext *s, DisasFields *f, DisasOps *o)
3686 {
3687 if (get_field(f, r1) != get_field(f, r2)) {
3688 store_freg32_i64(get_field(f, r1), o->out);
3689 }
3690 }
3691
3692 static void wout_m1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3693 {
3694 tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s));
3695 }
3696
3697 static void wout_m1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3698 {
3699 tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s));
3700 }
3701
3702 static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3703 {
3704 tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
3705 }
3706
3707 static void wout_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3708 {
3709 tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
3710 }
3711
3712 /* ====================================================================== */
3713 /* The "INput 1" generators. These load the first operand to an insn. */
3714
3715 static void in1_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3716 {
3717 o->in1 = load_reg(get_field(f, r1));
3718 }
3719
3720 static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3721 {
3722 o->in1 = regs[get_field(f, r1)];
3723 o->g_in1 = true;
3724 }
3725
3726 static void in1_r1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3727 {
3728 o->in1 = tcg_temp_new_i64();
3729 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r1)]);
3730 }
3731
3732 static void in1_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3733 {
3734 o->in1 = tcg_temp_new_i64();
3735 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r1)]);
3736 }
3737
3738 static void in1_r1p1(DisasContext *s, DisasFields *f, DisasOps *o)
3739 {
3740 /* ??? Specification exception: r1 must be even. */
3741 int r1 = get_field(f, r1);
3742 o->in1 = load_reg((r1 + 1) & 15);
3743 }
3744
3745 static void in1_r1p1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3746 {
3747 /* ??? Specification exception: r1 must be even. */
3748 int r1 = get_field(f, r1);
3749 o->in1 = tcg_temp_new_i64();
3750 tcg_gen_ext32s_i64(o->in1, regs[(r1 + 1) & 15]);
3751 }
3752
3753 static void in1_r1p1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3754 {
3755 /* ??? Specification exception: r1 must be even. */
3756 int r1 = get_field(f, r1);
3757 o->in1 = tcg_temp_new_i64();
3758 tcg_gen_ext32u_i64(o->in1, regs[(r1 + 1) & 15]);
3759 }
3760
3761 static void in1_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3762 {
3763 /* ??? Specification exception: r1 must be even. */
3764 int r1 = get_field(f, r1);
3765 o->in1 = tcg_temp_new_i64();
3766 tcg_gen_concat32_i64(o->in1, regs[r1 + 1], regs[r1]);
3767 }
3768
3769 static void in1_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3770 {
3771 o->in1 = load_reg(get_field(f, r2));
3772 }
3773
3774 static void in1_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3775 {
3776 o->in1 = load_reg(get_field(f, r3));
3777 }
3778
3779 static void in1_r3_o(DisasContext *s, DisasFields *f, DisasOps *o)
3780 {
3781 o->in1 = regs[get_field(f, r3)];
3782 o->g_in1 = true;
3783 }
3784
3785 static void in1_r3_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3786 {
3787 o->in1 = tcg_temp_new_i64();
3788 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r3)]);
3789 }
3790
3791 static void in1_r3_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3792 {
3793 o->in1 = tcg_temp_new_i64();
3794 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r3)]);
3795 }
3796
3797 static void in1_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3798 {
3799 o->in1 = load_freg32_i64(get_field(f, r1));
3800 }
3801
3802 static void in1_f1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3803 {
3804 o->in1 = fregs[get_field(f, r1)];
3805 o->g_in1 = true;
3806 }
3807
3808 static void in1_la1(DisasContext *s, DisasFields *f, DisasOps *o)
3809 {
3810 o->addr1 = get_address(s, 0, get_field(f, b1), get_field(f, d1));
3811 }
3812
3813 static void in1_m1_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3814 {
3815 in1_la1(s, f, o);
3816 o->in1 = tcg_temp_new_i64();
3817 tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s));
3818 }
3819
3820 static void in1_m1_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3821 {
3822 in1_la1(s, f, o);
3823 o->in1 = tcg_temp_new_i64();
3824 tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s));
3825 }
3826
3827 static void in1_m1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3828 {
3829 in1_la1(s, f, o);
3830 o->in1 = tcg_temp_new_i64();
3831 tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s));
3832 }
3833
3834 static void in1_m1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3835 {
3836 in1_la1(s, f, o);
3837 o->in1 = tcg_temp_new_i64();
3838 tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s));
3839 }
3840
3841 static void in1_m1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3842 {
3843 in1_la1(s, f, o);
3844 o->in1 = tcg_temp_new_i64();
3845 tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s));
3846 }
3847
3848 static void in1_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3849 {
3850 in1_la1(s, f, o);
3851 o->in1 = tcg_temp_new_i64();
3852 tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s));
3853 }
3854
3855 /* ====================================================================== */
3856 /* The "INput 2" generators. These load the second operand to an insn. */
3857
3858 static void in2_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3859 {
3860 o->in2 = load_reg(get_field(f, r2));
3861 }
3862
3863 static void in2_r2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3864 {
3865 o->in2 = regs[get_field(f, r2)];
3866 o->g_in2 = true;
3867 }
3868
3869 static void in2_r2_nz(DisasContext *s, DisasFields *f, DisasOps *o)
3870 {
3871 int r2 = get_field(f, r2);
3872 if (r2 != 0) {
3873 o->in2 = load_reg(r2);
3874 }
3875 }
3876
3877 static void in2_r2_8s(DisasContext *s, DisasFields *f, DisasOps *o)
3878 {
3879 o->in2 = tcg_temp_new_i64();
3880 tcg_gen_ext8s_i64(o->in2, regs[get_field(f, r2)]);
3881 }
3882
3883 static void in2_r2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3884 {
3885 o->in2 = tcg_temp_new_i64();
3886 tcg_gen_ext8u_i64(o->in2, regs[get_field(f, r2)]);
3887 }
3888
3889 static void in2_r2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3890 {
3891 o->in2 = tcg_temp_new_i64();
3892 tcg_gen_ext16s_i64(o->in2, regs[get_field(f, r2)]);
3893 }
3894
3895 static void in2_r2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3896 {
3897 o->in2 = tcg_temp_new_i64();
3898 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r2)]);
3899 }
3900
3901 static void in2_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3902 {
3903 o->in2 = load_reg(get_field(f, r3));
3904 }
3905
3906 static void in2_r2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3907 {
3908 o->in2 = tcg_temp_new_i64();
3909 tcg_gen_ext32s_i64(o->in2, regs[get_field(f, r2)]);
3910 }
3911
3912 static void in2_r2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3913 {
3914 o->in2 = tcg_temp_new_i64();
3915 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r2)]);
3916 }
3917
3918 static void in2_e2(DisasContext *s, DisasFields *f, DisasOps *o)
3919 {
3920 o->in2 = load_freg32_i64(get_field(f, r2));
3921 }
3922
3923 static void in2_f2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3924 {
3925 o->in2 = fregs[get_field(f, r2)];
3926 o->g_in2 = true;
3927 }
3928
3929 static void in2_x2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3930 {
3931 int f2 = get_field(f, r2);
3932 o->in1 = fregs[f2];
3933 o->in2 = fregs[(f2 + 2) & 15];
3934 o->g_in1 = o->g_in2 = true;
3935 }
3936
3937 static void in2_a2(DisasContext *s, DisasFields *f, DisasOps *o)
3938 {
3939 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3940 o->in2 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3941 }
3942
3943 static void in2_ri2(DisasContext *s, DisasFields *f, DisasOps *o)
3944 {
3945 o->in2 = tcg_const_i64(s->pc + (int64_t)get_field(f, i2) * 2);
3946 }
3947
3948 static void in2_sh32(DisasContext *s, DisasFields *f, DisasOps *o)
3949 {
3950 help_l2_shift(s, f, o, 31);
3951 }
3952
3953 static void in2_sh64(DisasContext *s, DisasFields *f, DisasOps *o)
3954 {
3955 help_l2_shift(s, f, o, 63);
3956 }
3957
3958 static void in2_m2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3959 {
3960 in2_a2(s, f, o);
3961 tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s));
3962 }
3963
3964 static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3965 {
3966 in2_a2(s, f, o);
3967 tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
3968 }
3969
3970 static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3971 {
3972 in2_a2(s, f, o);
3973 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3974 }
3975
3976 static void in2_m2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3977 {
3978 in2_a2(s, f, o);
3979 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3980 }
3981
3982 static void in2_m2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3983 {
3984 in2_a2(s, f, o);
3985 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3986 }
3987
3988 static void in2_mri2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3989 {
3990 in2_ri2(s, f, o);
3991 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3992 }
3993
3994 static void in2_mri2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3995 {
3996 in2_ri2(s, f, o);
3997 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3998 }
3999
4000 static void in2_mri2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4001 {
4002 in2_ri2(s, f, o);
4003 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
4004 }
4005
4006 static void in2_mri2_64(DisasContext *s, DisasFields *f, DisasOps *o)
4007 {
4008 in2_ri2(s, f, o);
4009 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
4010 }
4011
4012 static void in2_i2(DisasContext *s, DisasFields *f, DisasOps *o)
4013 {
4014 o->in2 = tcg_const_i64(get_field(f, i2));
4015 }
4016
4017 static void in2_i2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
4018 {
4019 o->in2 = tcg_const_i64((uint8_t)get_field(f, i2));
4020 }
4021
4022 static void in2_i2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
4023 {
4024 o->in2 = tcg_const_i64((uint16_t)get_field(f, i2));
4025 }
4026
4027 static void in2_i2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4028 {
4029 o->in2 = tcg_const_i64((uint32_t)get_field(f, i2));
4030 }
4031
4032 static void in2_i2_16u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
4033 {
4034 uint64_t i2 = (uint16_t)get_field(f, i2);
4035 o->in2 = tcg_const_i64(i2 << s->insn->data);
4036 }
4037
4038 static void in2_i2_32u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
4039 {
4040 uint64_t i2 = (uint32_t)get_field(f, i2);
4041 o->in2 = tcg_const_i64(i2 << s->insn->data);
4042 }
4043
4044 /* ====================================================================== */
4045
4046 /* Find opc within the table of insns. This is formulated as a switch
4047 statement so that (1) we get compile-time notice of cut-paste errors
4048 for duplicated opcodes, and (2) the compiler generates the binary
4049 search tree, rather than us having to post-process the table. */
4050
4051 #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
4052 D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0)
4053
4054 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) insn_ ## NM,
4055
4056 enum DisasInsnEnum {
4057 #include "insn-data.def"
4058 };
4059
4060 #undef D
4061 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) { \
4062 .opc = OPC, \
4063 .fmt = FMT_##FT, \
4064 .fac = FAC_##FC, \
4065 .name = #NM, \
4066 .help_in1 = in1_##I1, \
4067 .help_in2 = in2_##I2, \
4068 .help_prep = prep_##P, \
4069 .help_wout = wout_##W, \
4070 .help_cout = cout_##CC, \
4071 .help_op = op_##OP, \
4072 .data = D \
4073 },
4074
4075 /* Allow 0 to be used for NULL in the table below. */
4076 #define in1_0 NULL
4077 #define in2_0 NULL
4078 #define prep_0 NULL
4079 #define wout_0 NULL
4080 #define cout_0 NULL
4081 #define op_0 NULL
4082
4083 static const DisasInsn insn_info[] = {
4084 #include "insn-data.def"
4085 };
4086
4087 #undef D
4088 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
4089 case OPC: return &insn_info[insn_ ## NM];
4090
4091 static const DisasInsn *lookup_opc(uint16_t opc)
4092 {
4093 switch (opc) {
4094 #include "insn-data.def"
4095 default:
4096 return NULL;
4097 }
4098 }
4099
4100 #undef D
4101 #undef C
4102
4103 /* Extract a field from the insn. The INSN should be left-aligned in
4104 the uint64_t so that we can more easily utilize the big-bit-endian
4105 definitions we extract from the Principals of Operation. */
4106
4107 static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn)
4108 {
4109 uint32_t r, m;
4110
4111 if (f->size == 0) {
4112 return;
4113 }
4114
4115 /* Zero extract the field from the insn. */
4116 r = (insn << f->beg) >> (64 - f->size);
4117
4118 /* Sign-extend, or un-swap the field as necessary. */
4119 switch (f->type) {
4120 case 0: /* unsigned */
4121 break;
4122 case 1: /* signed */
4123 assert(f->size <= 32);
4124 m = 1u << (f->size - 1);
4125 r = (r ^ m) - m;
4126 break;
4127 case 2: /* dl+dh split, signed 20 bit. */
4128 r = ((int8_t)r << 12) | (r >> 8);
4129 break;
4130 default:
4131 abort();
4132 }
4133
4134 /* Validate that the "compressed" encoding we selected above is valid.
4135 I.e. we havn't make two different original fields overlap. */
4136 assert(((o->presentC >> f->indexC) & 1) == 0);
4137 o->presentC |= 1 << f->indexC;
4138 o->presentO |= 1 << f->indexO;
4139
4140 o->c[f->indexC] = r;
4141 }
4142
4143 /* Lookup the insn at the current PC, extracting the operands into O and
4144 returning the info struct for the insn. Returns NULL for invalid insn. */
4145
4146 static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
4147 DisasFields *f)
4148 {
4149 uint64_t insn, pc = s->pc;
4150 int op, op2, ilen;
4151 const DisasInsn *info;
4152
4153 insn = ld_code2(env, pc);
4154 op = (insn >> 8) & 0xff;
4155 ilen = get_ilen(op);
4156 s->next_pc = s->pc + ilen;
4157
4158 switch (ilen) {
4159 case 2:
4160 insn = insn << 48;
4161 break;
4162 case 4:
4163 insn = ld_code4(env, pc) << 32;
4164 break;
4165 case 6:
4166 insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
4167 break;
4168 default:
4169 abort();
4170 }
4171
4172 /* We can't actually determine the insn format until we've looked up
4173 the full insn opcode. Which we can't do without locating the
4174 secondary opcode. Assume by default that OP2 is at bit 40; for
4175 those smaller insns that don't actually have a secondary opcode
4176 this will correctly result in OP2 = 0. */
4177 switch (op) {
4178 case 0x01: /* E */
4179 case 0x80: /* S */
4180 case 0x82: /* S */
4181 case 0x93: /* S */
4182 case 0xb2: /* S, RRF, RRE */
4183 case 0xb3: /* RRE, RRD, RRF */
4184 case 0xb9: /* RRE, RRF */
4185 case 0xe5: /* SSE, SIL */
4186 op2 = (insn << 8) >> 56;
4187 break;
4188 case 0xa5: /* RI */
4189 case 0xa7: /* RI */
4190 case 0xc0: /* RIL */
4191 case 0xc2: /* RIL */
4192 case 0xc4: /* RIL */
4193 case 0xc6: /* RIL */
4194 case 0xc8: /* SSF */
4195 case 0xcc: /* RIL */
4196 op2 = (insn << 12) >> 60;
4197 break;
4198 case 0xd0 ... 0xdf: /* SS */
4199 case 0xe1: /* SS */
4200 case 0xe2: /* SS */
4201 case 0xe8: /* SS */
4202 case 0xe9: /* SS */
4203 case 0xea: /* SS */
4204 case 0xee ... 0xf3: /* SS */
4205 case 0xf8 ... 0xfd: /* SS */
4206 op2 = 0;
4207 break;
4208 default:
4209 op2 = (insn << 40) >> 56;
4210 break;
4211 }
4212
4213 memset(f, 0, sizeof(*f));
4214 f->op = op;
4215 f->op2 = op2;
4216
4217 /* Lookup the instruction. */
4218 info = lookup_opc(op << 8 | op2);
4219
4220 /* If we found it, extract the operands. */
4221 if (info != NULL) {
4222 DisasFormat fmt = info->fmt;
4223 int i;
4224
4225 for (i = 0; i < NUM_C_FIELD; ++i) {
4226 extract_field(f, &format_info[fmt].op[i], insn);
4227 }
4228 }
4229 return info;
4230 }
4231
4232 static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
4233 {
4234 const DisasInsn *insn;
4235 ExitStatus ret = NO_EXIT;
4236 DisasFields f;
4237 DisasOps o;
4238
4239 insn = extract_insn(env, s, &f);
4240
4241 /* If not found, try the old interpreter. This includes ILLOPC. */
4242 if (insn == NULL) {
4243 disas_s390_insn(env, s);
4244 switch (s->is_jmp) {
4245 case DISAS_NEXT:
4246 ret = NO_EXIT;
4247 break;
4248 case DISAS_TB_JUMP:
4249 ret = EXIT_GOTO_TB;
4250 break;
4251 case DISAS_JUMP:
4252 ret = EXIT_PC_UPDATED;
4253 break;
4254 case DISAS_EXCP:
4255 ret = EXIT_NORETURN;
4256 break;
4257 default:
4258 abort();
4259 }
4260
4261 s->pc = s->next_pc;
4262 return ret;
4263 }
4264
4265 /* Set up the strutures we use to communicate with the helpers. */
4266 s->insn = insn;
4267 s->fields = &f;
4268 o.g_out = o.g_out2 = o.g_in1 = o.g_in2 = false;
4269 TCGV_UNUSED_I64(o.out);
4270 TCGV_UNUSED_I64(o.out2);
4271 TCGV_UNUSED_I64(o.in1);
4272 TCGV_UNUSED_I64(o.in2);
4273 TCGV_UNUSED_I64(o.addr1);
4274
4275 /* Implement the instruction. */
4276 if (insn->help_in1) {
4277 insn->help_in1(s, &f, &o);
4278 }
4279 if (insn->help_in2) {
4280 insn->help_in2(s, &f, &o);
4281 }
4282 if (insn->help_prep) {
4283 insn->help_prep(s, &f, &o);
4284 }
4285 if (insn->help_op) {
4286 ret = insn->help_op(s, &o);
4287 }
4288 if (insn->help_wout) {
4289 insn->help_wout(s, &f, &o);
4290 }
4291 if (insn->help_cout) {
4292 insn->help_cout(s, &o);
4293 }
4294
4295 /* Free any temporaries created by the helpers. */
4296 if (!TCGV_IS_UNUSED_I64(o.out) && !o.g_out) {
4297 tcg_temp_free_i64(o.out);
4298 }
4299 if (!TCGV_IS_UNUSED_I64(o.out2) && !o.g_out2) {
4300 tcg_temp_free_i64(o.out2);
4301 }
4302 if (!TCGV_IS_UNUSED_I64(o.in1) && !o.g_in1) {
4303 tcg_temp_free_i64(o.in1);
4304 }
4305 if (!TCGV_IS_UNUSED_I64(o.in2) && !o.g_in2) {
4306 tcg_temp_free_i64(o.in2);
4307 }
4308 if (!TCGV_IS_UNUSED_I64(o.addr1)) {
4309 tcg_temp_free_i64(o.addr1);
4310 }
4311
4312 /* Advance to the next instruction. */
4313 s->pc = s->next_pc;
4314 return ret;
4315 }
4316
4317 static inline void gen_intermediate_code_internal(CPUS390XState *env,
4318 TranslationBlock *tb,
4319 int search_pc)
4320 {
4321 DisasContext dc;
4322 target_ulong pc_start;
4323 uint64_t next_page_start;
4324 uint16_t *gen_opc_end;
4325 int j, lj = -1;
4326 int num_insns, max_insns;
4327 CPUBreakpoint *bp;
4328 ExitStatus status;
4329 bool do_debug;
4330
4331 pc_start = tb->pc;
4332
4333 /* 31-bit mode */
4334 if (!(tb->flags & FLAG_MASK_64)) {
4335 pc_start &= 0x7fffffff;
4336 }
4337
4338 dc.tb = tb;
4339 dc.pc = pc_start;
4340 dc.cc_op = CC_OP_DYNAMIC;
4341 do_debug = dc.singlestep_enabled = env->singlestep_enabled;
4342 dc.is_jmp = DISAS_NEXT;
4343
4344 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
4345
4346 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4347
4348 num_insns = 0;
4349 max_insns = tb->cflags & CF_COUNT_MASK;
4350 if (max_insns == 0) {
4351 max_insns = CF_COUNT_MASK;
4352 }
4353
4354 gen_icount_start();
4355
4356 do {
4357 if (search_pc) {
4358 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4359 if (lj < j) {
4360 lj++;
4361 while (lj < j) {
4362 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4363 }
4364 }
4365 tcg_ctx.gen_opc_pc[lj] = dc.pc;
4366 gen_opc_cc_op[lj] = dc.cc_op;
4367 tcg_ctx.gen_opc_instr_start[lj] = 1;
4368 tcg_ctx.gen_opc_icount[lj] = num_insns;
4369 }
4370 if (++num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
4371 gen_io_start();
4372 }
4373
4374 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4375 tcg_gen_debug_insn_start(dc.pc);
4376 }
4377
4378 status = NO_EXIT;
4379 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
4380 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
4381 if (bp->pc == dc.pc) {
4382 status = EXIT_PC_STALE;
4383 do_debug = true;
4384 break;
4385 }
4386 }
4387 }
4388 if (status == NO_EXIT) {
4389 status = translate_one(env, &dc);
4390 }
4391
4392 /* If we reach a page boundary, are single stepping,
4393 or exhaust instruction count, stop generation. */
4394 if (status == NO_EXIT
4395 && (dc.pc >= next_page_start
4396 || tcg_ctx.gen_opc_ptr >= gen_opc_end
4397 || num_insns >= max_insns
4398 || singlestep
4399 || env->singlestep_enabled)) {
4400 status = EXIT_PC_STALE;
4401 }
4402 } while (status == NO_EXIT);
4403
4404 if (tb->cflags & CF_LAST_IO) {
4405 gen_io_end();
4406 }
4407
4408 switch (status) {
4409 case EXIT_GOTO_TB:
4410 case EXIT_NORETURN:
4411 break;
4412 case EXIT_PC_STALE:
4413 update_psw_addr(&dc);
4414 /* FALLTHRU */
4415 case EXIT_PC_UPDATED:
4416 if (singlestep && dc.cc_op != CC_OP_DYNAMIC) {
4417 gen_op_calc_cc(&dc);
4418 } else {
4419 /* Next TB starts off with CC_OP_DYNAMIC,
4420 so make sure the cc op type is in env */
4421 gen_op_set_cc_op(&dc);
4422 }
4423 if (do_debug) {
4424 gen_exception(EXCP_DEBUG);
4425 } else {
4426 /* Generate the return instruction */
4427 tcg_gen_exit_tb(0);
4428 }
4429 break;
4430 default:
4431 abort();
4432 }
4433
4434 gen_icount_end(tb, num_insns);
4435 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
4436 if (search_pc) {
4437 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4438 lj++;
4439 while (lj <= j) {
4440 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4441 }
4442 } else {
4443 tb->size = dc.pc - pc_start;
4444 tb->icount = num_insns;
4445 }
4446
4447 #if defined(S390X_DEBUG_DISAS)
4448 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
4449 qemu_log("IN: %s\n", lookup_symbol(pc_start));
4450 log_target_disas(env, pc_start, dc.pc - pc_start, 1);
4451 qemu_log("\n");
4452 }
4453 #endif
4454 }
4455
4456 void gen_intermediate_code (CPUS390XState *env, struct TranslationBlock *tb)
4457 {
4458 gen_intermediate_code_internal(env, tb, 0);
4459 }
4460
4461 void gen_intermediate_code_pc (CPUS390XState *env, struct TranslationBlock *tb)
4462 {
4463 gen_intermediate_code_internal(env, tb, 1);
4464 }
4465
4466 void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos)
4467 {
4468 int cc_op;
4469 env->psw.addr = tcg_ctx.gen_opc_pc[pc_pos];
4470 cc_op = gen_opc_cc_op[pc_pos];
4471 if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {
4472 env->cc_op = cc_op;
4473 }
4474 }
Qemu copy for testing