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target-s390: Implement CONVERT FROM LOGICAL
[qemu.git] / target-s390x / translate.c
1 /*
2 * S/390 translation
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* #define DEBUG_INLINE_BRANCHES */
22 #define S390X_DEBUG_DISAS
23 /* #define S390X_DEBUG_DISAS_VERBOSE */
24
25 #ifdef S390X_DEBUG_DISAS_VERBOSE
26 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
27 #else
28 # define LOG_DISAS(...) do { } while (0)
29 #endif
30
31 #include "cpu.h"
32 #include "disas/disas.h"
33 #include "tcg-op.h"
34 #include "qemu/log.h"
35 #include "qemu/host-utils.h"
36
37 /* global register indexes */
38 static TCGv_ptr cpu_env;
39
40 #include "exec/gen-icount.h"
41 #include "helper.h"
42 #define GEN_HELPER 1
43 #include "helper.h"
44
45
46 /* Information that (most) every instruction needs to manipulate. */
47 typedef struct DisasContext DisasContext;
48 typedef struct DisasInsn DisasInsn;
49 typedef struct DisasFields DisasFields;
50
51 struct DisasContext {
52 struct TranslationBlock *tb;
53 const DisasInsn *insn;
54 DisasFields *fields;
55 uint64_t pc, next_pc;
56 enum cc_op cc_op;
57 bool singlestep_enabled;
58 };
59
60 /* Information carried about a condition to be evaluated. */
61 typedef struct {
62 TCGCond cond:8;
63 bool is_64;
64 bool g1;
65 bool g2;
66 union {
67 struct { TCGv_i64 a, b; } s64;
68 struct { TCGv_i32 a, b; } s32;
69 } u;
70 } DisasCompare;
71
72 #define DISAS_EXCP 4
73
74 #ifdef DEBUG_INLINE_BRANCHES
75 static uint64_t inline_branch_hit[CC_OP_MAX];
76 static uint64_t inline_branch_miss[CC_OP_MAX];
77 #endif
78
79 static uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
80 {
81 if (!(s->tb->flags & FLAG_MASK_64)) {
82 if (s->tb->flags & FLAG_MASK_32) {
83 return pc | 0x80000000;
84 }
85 }
86 return pc;
87 }
88
89 void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
90 int flags)
91 {
92 int i;
93
94 if (env->cc_op > 3) {
95 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
96 env->psw.mask, env->psw.addr, cc_name(env->cc_op));
97 } else {
98 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
99 env->psw.mask, env->psw.addr, env->cc_op);
100 }
101
102 for (i = 0; i < 16; i++) {
103 cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
104 if ((i % 4) == 3) {
105 cpu_fprintf(f, "\n");
106 } else {
107 cpu_fprintf(f, " ");
108 }
109 }
110
111 for (i = 0; i < 16; i++) {
112 cpu_fprintf(f, "F%02d=%016" PRIx64, i, env->fregs[i].ll);
113 if ((i % 4) == 3) {
114 cpu_fprintf(f, "\n");
115 } else {
116 cpu_fprintf(f, " ");
117 }
118 }
119
120 #ifndef CONFIG_USER_ONLY
121 for (i = 0; i < 16; i++) {
122 cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
123 if ((i % 4) == 3) {
124 cpu_fprintf(f, "\n");
125 } else {
126 cpu_fprintf(f, " ");
127 }
128 }
129 #endif
130
131 #ifdef DEBUG_INLINE_BRANCHES
132 for (i = 0; i < CC_OP_MAX; i++) {
133 cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
134 inline_branch_miss[i], inline_branch_hit[i]);
135 }
136 #endif
137
138 cpu_fprintf(f, "\n");
139 }
140
141 static TCGv_i64 psw_addr;
142 static TCGv_i64 psw_mask;
143
144 static TCGv_i32 cc_op;
145 static TCGv_i64 cc_src;
146 static TCGv_i64 cc_dst;
147 static TCGv_i64 cc_vr;
148
149 static char cpu_reg_names[32][4];
150 static TCGv_i64 regs[16];
151 static TCGv_i64 fregs[16];
152
153 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
154
155 void s390x_translate_init(void)
156 {
157 int i;
158
159 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
160 psw_addr = tcg_global_mem_new_i64(TCG_AREG0,
161 offsetof(CPUS390XState, psw.addr),
162 "psw_addr");
163 psw_mask = tcg_global_mem_new_i64(TCG_AREG0,
164 offsetof(CPUS390XState, psw.mask),
165 "psw_mask");
166
167 cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUS390XState, cc_op),
168 "cc_op");
169 cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_src),
170 "cc_src");
171 cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_dst),
172 "cc_dst");
173 cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_vr),
174 "cc_vr");
175
176 for (i = 0; i < 16; i++) {
177 snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i);
178 regs[i] = tcg_global_mem_new(TCG_AREG0,
179 offsetof(CPUS390XState, regs[i]),
180 cpu_reg_names[i]);
181 }
182
183 for (i = 0; i < 16; i++) {
184 snprintf(cpu_reg_names[i + 16], sizeof(cpu_reg_names[0]), "f%d", i);
185 fregs[i] = tcg_global_mem_new(TCG_AREG0,
186 offsetof(CPUS390XState, fregs[i].d),
187 cpu_reg_names[i + 16]);
188 }
189
190 /* register helpers */
191 #define GEN_HELPER 2
192 #include "helper.h"
193 }
194
195 static TCGv_i64 load_reg(int reg)
196 {
197 TCGv_i64 r = tcg_temp_new_i64();
198 tcg_gen_mov_i64(r, regs[reg]);
199 return r;
200 }
201
202 static TCGv_i64 load_freg32_i64(int reg)
203 {
204 TCGv_i64 r = tcg_temp_new_i64();
205 tcg_gen_shri_i64(r, fregs[reg], 32);
206 return r;
207 }
208
209 static void store_reg(int reg, TCGv_i64 v)
210 {
211 tcg_gen_mov_i64(regs[reg], v);
212 }
213
214 static void store_freg(int reg, TCGv_i64 v)
215 {
216 tcg_gen_mov_i64(fregs[reg], v);
217 }
218
219 static void store_reg32_i64(int reg, TCGv_i64 v)
220 {
221 /* 32 bit register writes keep the upper half */
222 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
223 }
224
225 static void store_reg32h_i64(int reg, TCGv_i64 v)
226 {
227 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 32, 32);
228 }
229
230 static void store_freg32_i64(int reg, TCGv_i64 v)
231 {
232 tcg_gen_deposit_i64(fregs[reg], fregs[reg], v, 32, 32);
233 }
234
235 static void return_low128(TCGv_i64 dest)
236 {
237 tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl));
238 }
239
240 static void update_psw_addr(DisasContext *s)
241 {
242 /* psw.addr */
243 tcg_gen_movi_i64(psw_addr, s->pc);
244 }
245
246 static void update_cc_op(DisasContext *s)
247 {
248 if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
249 tcg_gen_movi_i32(cc_op, s->cc_op);
250 }
251 }
252
253 static void potential_page_fault(DisasContext *s)
254 {
255 update_psw_addr(s);
256 update_cc_op(s);
257 }
258
259 static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
260 {
261 return (uint64_t)cpu_lduw_code(env, pc);
262 }
263
264 static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
265 {
266 return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
267 }
268
269 static inline uint64_t ld_code6(CPUS390XState *env, uint64_t pc)
270 {
271 return (ld_code2(env, pc) << 32) | ld_code4(env, pc + 2);
272 }
273
274 static int get_mem_index(DisasContext *s)
275 {
276 switch (s->tb->flags & FLAG_MASK_ASC) {
277 case PSW_ASC_PRIMARY >> 32:
278 return 0;
279 case PSW_ASC_SECONDARY >> 32:
280 return 1;
281 case PSW_ASC_HOME >> 32:
282 return 2;
283 default:
284 tcg_abort();
285 break;
286 }
287 }
288
289 static void gen_exception(int excp)
290 {
291 TCGv_i32 tmp = tcg_const_i32(excp);
292 gen_helper_exception(cpu_env, tmp);
293 tcg_temp_free_i32(tmp);
294 }
295
296 static void gen_program_exception(DisasContext *s, int code)
297 {
298 TCGv_i32 tmp;
299
300 /* Remember what pgm exeption this was. */
301 tmp = tcg_const_i32(code);
302 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
303 tcg_temp_free_i32(tmp);
304
305 tmp = tcg_const_i32(s->next_pc - s->pc);
306 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen));
307 tcg_temp_free_i32(tmp);
308
309 /* Advance past instruction. */
310 s->pc = s->next_pc;
311 update_psw_addr(s);
312
313 /* Save off cc. */
314 update_cc_op(s);
315
316 /* Trigger exception. */
317 gen_exception(EXCP_PGM);
318 }
319
320 static inline void gen_illegal_opcode(DisasContext *s)
321 {
322 gen_program_exception(s, PGM_SPECIFICATION);
323 }
324
325 static inline void check_privileged(DisasContext *s)
326 {
327 if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
328 gen_program_exception(s, PGM_PRIVILEGED);
329 }
330 }
331
332 static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
333 {
334 TCGv_i64 tmp;
335
336 /* 31-bitify the immediate part; register contents are dealt with below */
337 if (!(s->tb->flags & FLAG_MASK_64)) {
338 d2 &= 0x7fffffffUL;
339 }
340
341 if (x2) {
342 if (d2) {
343 tmp = tcg_const_i64(d2);
344 tcg_gen_add_i64(tmp, tmp, regs[x2]);
345 } else {
346 tmp = load_reg(x2);
347 }
348 if (b2) {
349 tcg_gen_add_i64(tmp, tmp, regs[b2]);
350 }
351 } else if (b2) {
352 if (d2) {
353 tmp = tcg_const_i64(d2);
354 tcg_gen_add_i64(tmp, tmp, regs[b2]);
355 } else {
356 tmp = load_reg(b2);
357 }
358 } else {
359 tmp = tcg_const_i64(d2);
360 }
361
362 /* 31-bit mode mask if there are values loaded from registers */
363 if (!(s->tb->flags & FLAG_MASK_64) && (x2 || b2)) {
364 tcg_gen_andi_i64(tmp, tmp, 0x7fffffffUL);
365 }
366
367 return tmp;
368 }
369
370 static inline void gen_op_movi_cc(DisasContext *s, uint32_t val)
371 {
372 s->cc_op = CC_OP_CONST0 + val;
373 }
374
375 static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
376 {
377 tcg_gen_discard_i64(cc_src);
378 tcg_gen_mov_i64(cc_dst, dst);
379 tcg_gen_discard_i64(cc_vr);
380 s->cc_op = op;
381 }
382
383 static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
384 TCGv_i64 dst)
385 {
386 tcg_gen_mov_i64(cc_src, src);
387 tcg_gen_mov_i64(cc_dst, dst);
388 tcg_gen_discard_i64(cc_vr);
389 s->cc_op = op;
390 }
391
392 static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
393 TCGv_i64 dst, TCGv_i64 vr)
394 {
395 tcg_gen_mov_i64(cc_src, src);
396 tcg_gen_mov_i64(cc_dst, dst);
397 tcg_gen_mov_i64(cc_vr, vr);
398 s->cc_op = op;
399 }
400
401 static void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
402 {
403 gen_op_update1_cc_i64(s, CC_OP_NZ, val);
404 }
405
406 static void gen_set_cc_nz_f32(DisasContext *s, TCGv_i64 val)
407 {
408 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, val);
409 }
410
411 static void gen_set_cc_nz_f64(DisasContext *s, TCGv_i64 val)
412 {
413 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, val);
414 }
415
416 static void gen_set_cc_nz_f128(DisasContext *s, TCGv_i64 vh, TCGv_i64 vl)
417 {
418 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, vh, vl);
419 }
420
421 /* CC value is in env->cc_op */
422 static void set_cc_static(DisasContext *s)
423 {
424 tcg_gen_discard_i64(cc_src);
425 tcg_gen_discard_i64(cc_dst);
426 tcg_gen_discard_i64(cc_vr);
427 s->cc_op = CC_OP_STATIC;
428 }
429
430 /* calculates cc into cc_op */
431 static void gen_op_calc_cc(DisasContext *s)
432 {
433 TCGv_i32 local_cc_op;
434 TCGv_i64 dummy;
435
436 TCGV_UNUSED_I32(local_cc_op);
437 TCGV_UNUSED_I64(dummy);
438 switch (s->cc_op) {
439 default:
440 dummy = tcg_const_i64(0);
441 /* FALLTHRU */
442 case CC_OP_ADD_64:
443 case CC_OP_ADDU_64:
444 case CC_OP_ADDC_64:
445 case CC_OP_SUB_64:
446 case CC_OP_SUBU_64:
447 case CC_OP_SUBB_64:
448 case CC_OP_ADD_32:
449 case CC_OP_ADDU_32:
450 case CC_OP_ADDC_32:
451 case CC_OP_SUB_32:
452 case CC_OP_SUBU_32:
453 case CC_OP_SUBB_32:
454 local_cc_op = tcg_const_i32(s->cc_op);
455 break;
456 case CC_OP_CONST0:
457 case CC_OP_CONST1:
458 case CC_OP_CONST2:
459 case CC_OP_CONST3:
460 case CC_OP_STATIC:
461 case CC_OP_DYNAMIC:
462 break;
463 }
464
465 switch (s->cc_op) {
466 case CC_OP_CONST0:
467 case CC_OP_CONST1:
468 case CC_OP_CONST2:
469 case CC_OP_CONST3:
470 /* s->cc_op is the cc value */
471 tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
472 break;
473 case CC_OP_STATIC:
474 /* env->cc_op already is the cc value */
475 break;
476 case CC_OP_NZ:
477 case CC_OP_ABS_64:
478 case CC_OP_NABS_64:
479 case CC_OP_ABS_32:
480 case CC_OP_NABS_32:
481 case CC_OP_LTGT0_32:
482 case CC_OP_LTGT0_64:
483 case CC_OP_COMP_32:
484 case CC_OP_COMP_64:
485 case CC_OP_NZ_F32:
486 case CC_OP_NZ_F64:
487 case CC_OP_FLOGR:
488 /* 1 argument */
489 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dummy);
490 break;
491 case CC_OP_ICM:
492 case CC_OP_LTGT_32:
493 case CC_OP_LTGT_64:
494 case CC_OP_LTUGTU_32:
495 case CC_OP_LTUGTU_64:
496 case CC_OP_TM_32:
497 case CC_OP_TM_64:
498 case CC_OP_SLA_32:
499 case CC_OP_SLA_64:
500 case CC_OP_NZ_F128:
501 /* 2 arguments */
502 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
503 break;
504 case CC_OP_ADD_64:
505 case CC_OP_ADDU_64:
506 case CC_OP_ADDC_64:
507 case CC_OP_SUB_64:
508 case CC_OP_SUBU_64:
509 case CC_OP_SUBB_64:
510 case CC_OP_ADD_32:
511 case CC_OP_ADDU_32:
512 case CC_OP_ADDC_32:
513 case CC_OP_SUB_32:
514 case CC_OP_SUBU_32:
515 case CC_OP_SUBB_32:
516 /* 3 arguments */
517 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc_vr);
518 break;
519 case CC_OP_DYNAMIC:
520 /* unknown operation - assume 3 arguments and cc_op in env */
521 gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr);
522 break;
523 default:
524 tcg_abort();
525 }
526
527 if (!TCGV_IS_UNUSED_I32(local_cc_op)) {
528 tcg_temp_free_i32(local_cc_op);
529 }
530 if (!TCGV_IS_UNUSED_I64(dummy)) {
531 tcg_temp_free_i64(dummy);
532 }
533
534 /* We now have cc in cc_op as constant */
535 set_cc_static(s);
536 }
537
538 static int use_goto_tb(DisasContext *s, uint64_t dest)
539 {
540 /* NOTE: we handle the case where the TB spans two pages here */
541 return (((dest & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK)
542 || (dest & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK))
543 && !s->singlestep_enabled
544 && !(s->tb->cflags & CF_LAST_IO));
545 }
546
547 static void account_noninline_branch(DisasContext *s, int cc_op)
548 {
549 #ifdef DEBUG_INLINE_BRANCHES
550 inline_branch_miss[cc_op]++;
551 #endif
552 }
553
554 static void account_inline_branch(DisasContext *s, int cc_op)
555 {
556 #ifdef DEBUG_INLINE_BRANCHES
557 inline_branch_hit[cc_op]++;
558 #endif
559 }
560
561 /* Table of mask values to comparison codes, given a comparison as input.
562 For a true comparison CC=3 will never be set, but we treat this
563 conservatively for possible use when CC=3 indicates overflow. */
564 static const TCGCond ltgt_cond[16] = {
565 TCG_COND_NEVER, TCG_COND_NEVER, /* | | | x */
566 TCG_COND_GT, TCG_COND_NEVER, /* | | GT | x */
567 TCG_COND_LT, TCG_COND_NEVER, /* | LT | | x */
568 TCG_COND_NE, TCG_COND_NEVER, /* | LT | GT | x */
569 TCG_COND_EQ, TCG_COND_NEVER, /* EQ | | | x */
570 TCG_COND_GE, TCG_COND_NEVER, /* EQ | | GT | x */
571 TCG_COND_LE, TCG_COND_NEVER, /* EQ | LT | | x */
572 TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | LT | GT | x */
573 };
574
575 /* Table of mask values to comparison codes, given a logic op as input.
576 For such, only CC=0 and CC=1 should be possible. */
577 static const TCGCond nz_cond[16] = {
578 /* | | x | x */
579 TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER,
580 /* | NE | x | x */
581 TCG_COND_NE, TCG_COND_NE, TCG_COND_NE, TCG_COND_NE,
582 /* EQ | | x | x */
583 TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ,
584 /* EQ | NE | x | x */
585 TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS,
586 };
587
588 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
589 details required to generate a TCG comparison. */
590 static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
591 {
592 TCGCond cond;
593 enum cc_op old_cc_op = s->cc_op;
594
595 if (mask == 15 || mask == 0) {
596 c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER);
597 c->u.s32.a = cc_op;
598 c->u.s32.b = cc_op;
599 c->g1 = c->g2 = true;
600 c->is_64 = false;
601 return;
602 }
603
604 /* Find the TCG condition for the mask + cc op. */
605 switch (old_cc_op) {
606 case CC_OP_LTGT0_32:
607 case CC_OP_LTGT0_64:
608 case CC_OP_LTGT_32:
609 case CC_OP_LTGT_64:
610 cond = ltgt_cond[mask];
611 if (cond == TCG_COND_NEVER) {
612 goto do_dynamic;
613 }
614 account_inline_branch(s, old_cc_op);
615 break;
616
617 case CC_OP_LTUGTU_32:
618 case CC_OP_LTUGTU_64:
619 cond = tcg_unsigned_cond(ltgt_cond[mask]);
620 if (cond == TCG_COND_NEVER) {
621 goto do_dynamic;
622 }
623 account_inline_branch(s, old_cc_op);
624 break;
625
626 case CC_OP_NZ:
627 cond = nz_cond[mask];
628 if (cond == TCG_COND_NEVER) {
629 goto do_dynamic;
630 }
631 account_inline_branch(s, old_cc_op);
632 break;
633
634 case CC_OP_TM_32:
635 case CC_OP_TM_64:
636 switch (mask) {
637 case 8:
638 cond = TCG_COND_EQ;
639 break;
640 case 4 | 2 | 1:
641 cond = TCG_COND_NE;
642 break;
643 default:
644 goto do_dynamic;
645 }
646 account_inline_branch(s, old_cc_op);
647 break;
648
649 case CC_OP_ICM:
650 switch (mask) {
651 case 8:
652 cond = TCG_COND_EQ;
653 break;
654 case 4 | 2 | 1:
655 case 4 | 2:
656 cond = TCG_COND_NE;
657 break;
658 default:
659 goto do_dynamic;
660 }
661 account_inline_branch(s, old_cc_op);
662 break;
663
664 case CC_OP_FLOGR:
665 switch (mask & 0xa) {
666 case 8: /* src == 0 -> no one bit found */
667 cond = TCG_COND_EQ;
668 break;
669 case 2: /* src != 0 -> one bit found */
670 cond = TCG_COND_NE;
671 break;
672 default:
673 goto do_dynamic;
674 }
675 account_inline_branch(s, old_cc_op);
676 break;
677
678 default:
679 do_dynamic:
680 /* Calculate cc value. */
681 gen_op_calc_cc(s);
682 /* FALLTHRU */
683
684 case CC_OP_STATIC:
685 /* Jump based on CC. We'll load up the real cond below;
686 the assignment here merely avoids a compiler warning. */
687 account_noninline_branch(s, old_cc_op);
688 old_cc_op = CC_OP_STATIC;
689 cond = TCG_COND_NEVER;
690 break;
691 }
692
693 /* Load up the arguments of the comparison. */
694 c->is_64 = true;
695 c->g1 = c->g2 = false;
696 switch (old_cc_op) {
697 case CC_OP_LTGT0_32:
698 c->is_64 = false;
699 c->u.s32.a = tcg_temp_new_i32();
700 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_dst);
701 c->u.s32.b = tcg_const_i32(0);
702 break;
703 case CC_OP_LTGT_32:
704 case CC_OP_LTUGTU_32:
705 c->is_64 = false;
706 c->u.s32.a = tcg_temp_new_i32();
707 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_src);
708 c->u.s32.b = tcg_temp_new_i32();
709 tcg_gen_trunc_i64_i32(c->u.s32.b, cc_dst);
710 break;
711
712 case CC_OP_LTGT0_64:
713 case CC_OP_NZ:
714 case CC_OP_FLOGR:
715 c->u.s64.a = cc_dst;
716 c->u.s64.b = tcg_const_i64(0);
717 c->g1 = true;
718 break;
719 case CC_OP_LTGT_64:
720 case CC_OP_LTUGTU_64:
721 c->u.s64.a = cc_src;
722 c->u.s64.b = cc_dst;
723 c->g1 = c->g2 = true;
724 break;
725
726 case CC_OP_TM_32:
727 case CC_OP_TM_64:
728 case CC_OP_ICM:
729 c->u.s64.a = tcg_temp_new_i64();
730 c->u.s64.b = tcg_const_i64(0);
731 tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
732 break;
733
734 case CC_OP_STATIC:
735 c->is_64 = false;
736 c->u.s32.a = cc_op;
737 c->g1 = true;
738 switch (mask) {
739 case 0x8 | 0x4 | 0x2: /* cc != 3 */
740 cond = TCG_COND_NE;
741 c->u.s32.b = tcg_const_i32(3);
742 break;
743 case 0x8 | 0x4 | 0x1: /* cc != 2 */
744 cond = TCG_COND_NE;
745 c->u.s32.b = tcg_const_i32(2);
746 break;
747 case 0x8 | 0x2 | 0x1: /* cc != 1 */
748 cond = TCG_COND_NE;
749 c->u.s32.b = tcg_const_i32(1);
750 break;
751 case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
752 cond = TCG_COND_EQ;
753 c->g1 = false;
754 c->u.s32.a = tcg_temp_new_i32();
755 c->u.s32.b = tcg_const_i32(0);
756 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
757 break;
758 case 0x8 | 0x4: /* cc < 2 */
759 cond = TCG_COND_LTU;
760 c->u.s32.b = tcg_const_i32(2);
761 break;
762 case 0x8: /* cc == 0 */
763 cond = TCG_COND_EQ;
764 c->u.s32.b = tcg_const_i32(0);
765 break;
766 case 0x4 | 0x2 | 0x1: /* cc != 0 */
767 cond = TCG_COND_NE;
768 c->u.s32.b = tcg_const_i32(0);
769 break;
770 case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
771 cond = TCG_COND_NE;
772 c->g1 = false;
773 c->u.s32.a = tcg_temp_new_i32();
774 c->u.s32.b = tcg_const_i32(0);
775 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
776 break;
777 case 0x4: /* cc == 1 */
778 cond = TCG_COND_EQ;
779 c->u.s32.b = tcg_const_i32(1);
780 break;
781 case 0x2 | 0x1: /* cc > 1 */
782 cond = TCG_COND_GTU;
783 c->u.s32.b = tcg_const_i32(1);
784 break;
785 case 0x2: /* cc == 2 */
786 cond = TCG_COND_EQ;
787 c->u.s32.b = tcg_const_i32(2);
788 break;
789 case 0x1: /* cc == 3 */
790 cond = TCG_COND_EQ;
791 c->u.s32.b = tcg_const_i32(3);
792 break;
793 default:
794 /* CC is masked by something else: (8 >> cc) & mask. */
795 cond = TCG_COND_NE;
796 c->g1 = false;
797 c->u.s32.a = tcg_const_i32(8);
798 c->u.s32.b = tcg_const_i32(0);
799 tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op);
800 tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
801 break;
802 }
803 break;
804
805 default:
806 abort();
807 }
808 c->cond = cond;
809 }
810
811 static void free_compare(DisasCompare *c)
812 {
813 if (!c->g1) {
814 if (c->is_64) {
815 tcg_temp_free_i64(c->u.s64.a);
816 } else {
817 tcg_temp_free_i32(c->u.s32.a);
818 }
819 }
820 if (!c->g2) {
821 if (c->is_64) {
822 tcg_temp_free_i64(c->u.s64.b);
823 } else {
824 tcg_temp_free_i32(c->u.s32.b);
825 }
826 }
827 }
828
829 /* ====================================================================== */
830 /* Define the insn format enumeration. */
831 #define F0(N) FMT_##N,
832 #define F1(N, X1) F0(N)
833 #define F2(N, X1, X2) F0(N)
834 #define F3(N, X1, X2, X3) F0(N)
835 #define F4(N, X1, X2, X3, X4) F0(N)
836 #define F5(N, X1, X2, X3, X4, X5) F0(N)
837
838 typedef enum {
839 #include "insn-format.def"
840 } DisasFormat;
841
842 #undef F0
843 #undef F1
844 #undef F2
845 #undef F3
846 #undef F4
847 #undef F5
848
849 /* Define a structure to hold the decoded fields. We'll store each inside
850 an array indexed by an enum. In order to conserve memory, we'll arrange
851 for fields that do not exist at the same time to overlap, thus the "C"
852 for compact. For checking purposes there is an "O" for original index
853 as well that will be applied to availability bitmaps. */
854
855 enum DisasFieldIndexO {
856 FLD_O_r1,
857 FLD_O_r2,
858 FLD_O_r3,
859 FLD_O_m1,
860 FLD_O_m3,
861 FLD_O_m4,
862 FLD_O_b1,
863 FLD_O_b2,
864 FLD_O_b4,
865 FLD_O_d1,
866 FLD_O_d2,
867 FLD_O_d4,
868 FLD_O_x2,
869 FLD_O_l1,
870 FLD_O_l2,
871 FLD_O_i1,
872 FLD_O_i2,
873 FLD_O_i3,
874 FLD_O_i4,
875 FLD_O_i5
876 };
877
878 enum DisasFieldIndexC {
879 FLD_C_r1 = 0,
880 FLD_C_m1 = 0,
881 FLD_C_b1 = 0,
882 FLD_C_i1 = 0,
883
884 FLD_C_r2 = 1,
885 FLD_C_b2 = 1,
886 FLD_C_i2 = 1,
887
888 FLD_C_r3 = 2,
889 FLD_C_m3 = 2,
890 FLD_C_i3 = 2,
891
892 FLD_C_m4 = 3,
893 FLD_C_b4 = 3,
894 FLD_C_i4 = 3,
895 FLD_C_l1 = 3,
896
897 FLD_C_i5 = 4,
898 FLD_C_d1 = 4,
899
900 FLD_C_d2 = 5,
901
902 FLD_C_d4 = 6,
903 FLD_C_x2 = 6,
904 FLD_C_l2 = 6,
905
906 NUM_C_FIELD = 7
907 };
908
909 struct DisasFields {
910 unsigned op:8;
911 unsigned op2:8;
912 unsigned presentC:16;
913 unsigned int presentO;
914 int c[NUM_C_FIELD];
915 };
916
917 /* This is the way fields are to be accessed out of DisasFields. */
918 #define have_field(S, F) have_field1((S), FLD_O_##F)
919 #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
920
921 static bool have_field1(const DisasFields *f, enum DisasFieldIndexO c)
922 {
923 return (f->presentO >> c) & 1;
924 }
925
926 static int get_field1(const DisasFields *f, enum DisasFieldIndexO o,
927 enum DisasFieldIndexC c)
928 {
929 assert(have_field1(f, o));
930 return f->c[c];
931 }
932
933 /* Describe the layout of each field in each format. */
934 typedef struct DisasField {
935 unsigned int beg:8;
936 unsigned int size:8;
937 unsigned int type:2;
938 unsigned int indexC:6;
939 enum DisasFieldIndexO indexO:8;
940 } DisasField;
941
942 typedef struct DisasFormatInfo {
943 DisasField op[NUM_C_FIELD];
944 } DisasFormatInfo;
945
946 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
947 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
948 #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
949 { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
950 #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
951 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
952 { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
953 #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
954 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
955 #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
956 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
957 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
958 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
959 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
960
961 #define F0(N) { { } },
962 #define F1(N, X1) { { X1 } },
963 #define F2(N, X1, X2) { { X1, X2 } },
964 #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
965 #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
966 #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
967
968 static const DisasFormatInfo format_info[] = {
969 #include "insn-format.def"
970 };
971
972 #undef F0
973 #undef F1
974 #undef F2
975 #undef F3
976 #undef F4
977 #undef F5
978 #undef R
979 #undef M
980 #undef BD
981 #undef BXD
982 #undef BDL
983 #undef BXDL
984 #undef I
985 #undef L
986
987 /* Generally, we'll extract operands into this structures, operate upon
988 them, and store them back. See the "in1", "in2", "prep", "wout" sets
989 of routines below for more details. */
990 typedef struct {
991 bool g_out, g_out2, g_in1, g_in2;
992 TCGv_i64 out, out2, in1, in2;
993 TCGv_i64 addr1;
994 } DisasOps;
995
996 /* Return values from translate_one, indicating the state of the TB. */
997 typedef enum {
998 /* Continue the TB. */
999 NO_EXIT,
1000 /* We have emitted one or more goto_tb. No fixup required. */
1001 EXIT_GOTO_TB,
1002 /* We are not using a goto_tb (for whatever reason), but have updated
1003 the PC (for whatever reason), so there's no need to do it again on
1004 exiting the TB. */
1005 EXIT_PC_UPDATED,
1006 /* We are exiting the TB, but have neither emitted a goto_tb, nor
1007 updated the PC for the next instruction to be executed. */
1008 EXIT_PC_STALE,
1009 /* We are ending the TB with a noreturn function call, e.g. longjmp.
1010 No following code will be executed. */
1011 EXIT_NORETURN,
1012 } ExitStatus;
1013
1014 typedef enum DisasFacility {
1015 FAC_Z, /* zarch (default) */
1016 FAC_CASS, /* compare and swap and store */
1017 FAC_CASS2, /* compare and swap and store 2*/
1018 FAC_DFP, /* decimal floating point */
1019 FAC_DFPR, /* decimal floating point rounding */
1020 FAC_DO, /* distinct operands */
1021 FAC_EE, /* execute extensions */
1022 FAC_EI, /* extended immediate */
1023 FAC_FPE, /* floating point extension */
1024 FAC_FPSSH, /* floating point support sign handling */
1025 FAC_FPRGR, /* FPR-GR transfer */
1026 FAC_GIE, /* general instructions extension */
1027 FAC_HFP_MA, /* HFP multiply-and-add/subtract */
1028 FAC_HW, /* high-word */
1029 FAC_IEEEE_SIM, /* IEEE exception sumilation */
1030 FAC_LOC, /* load/store on condition */
1031 FAC_LD, /* long displacement */
1032 FAC_PC, /* population count */
1033 FAC_SCF, /* store clock fast */
1034 FAC_SFLE, /* store facility list extended */
1035 } DisasFacility;
1036
1037 struct DisasInsn {
1038 unsigned opc:16;
1039 DisasFormat fmt:6;
1040 DisasFacility fac:6;
1041
1042 const char *name;
1043
1044 void (*help_in1)(DisasContext *, DisasFields *, DisasOps *);
1045 void (*help_in2)(DisasContext *, DisasFields *, DisasOps *);
1046 void (*help_prep)(DisasContext *, DisasFields *, DisasOps *);
1047 void (*help_wout)(DisasContext *, DisasFields *, DisasOps *);
1048 void (*help_cout)(DisasContext *, DisasOps *);
1049 ExitStatus (*help_op)(DisasContext *, DisasOps *);
1050
1051 uint64_t data;
1052 };
1053
1054 /* ====================================================================== */
1055 /* Miscelaneous helpers, used by several operations. */
1056
1057 static void help_l2_shift(DisasContext *s, DisasFields *f,
1058 DisasOps *o, int mask)
1059 {
1060 int b2 = get_field(f, b2);
1061 int d2 = get_field(f, d2);
1062
1063 if (b2 == 0) {
1064 o->in2 = tcg_const_i64(d2 & mask);
1065 } else {
1066 o->in2 = get_address(s, 0, b2, d2);
1067 tcg_gen_andi_i64(o->in2, o->in2, mask);
1068 }
1069 }
1070
1071 static ExitStatus help_goto_direct(DisasContext *s, uint64_t dest)
1072 {
1073 if (dest == s->next_pc) {
1074 return NO_EXIT;
1075 }
1076 if (use_goto_tb(s, dest)) {
1077 update_cc_op(s);
1078 tcg_gen_goto_tb(0);
1079 tcg_gen_movi_i64(psw_addr, dest);
1080 tcg_gen_exit_tb((tcg_target_long)s->tb);
1081 return EXIT_GOTO_TB;
1082 } else {
1083 tcg_gen_movi_i64(psw_addr, dest);
1084 return EXIT_PC_UPDATED;
1085 }
1086 }
1087
1088 static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
1089 bool is_imm, int imm, TCGv_i64 cdest)
1090 {
1091 ExitStatus ret;
1092 uint64_t dest = s->pc + 2 * imm;
1093 int lab;
1094
1095 /* Take care of the special cases first. */
1096 if (c->cond == TCG_COND_NEVER) {
1097 ret = NO_EXIT;
1098 goto egress;
1099 }
1100 if (is_imm) {
1101 if (dest == s->next_pc) {
1102 /* Branch to next. */
1103 ret = NO_EXIT;
1104 goto egress;
1105 }
1106 if (c->cond == TCG_COND_ALWAYS) {
1107 ret = help_goto_direct(s, dest);
1108 goto egress;
1109 }
1110 } else {
1111 if (TCGV_IS_UNUSED_I64(cdest)) {
1112 /* E.g. bcr %r0 -> no branch. */
1113 ret = NO_EXIT;
1114 goto egress;
1115 }
1116 if (c->cond == TCG_COND_ALWAYS) {
1117 tcg_gen_mov_i64(psw_addr, cdest);
1118 ret = EXIT_PC_UPDATED;
1119 goto egress;
1120 }
1121 }
1122
1123 if (use_goto_tb(s, s->next_pc)) {
1124 if (is_imm && use_goto_tb(s, dest)) {
1125 /* Both exits can use goto_tb. */
1126 update_cc_op(s);
1127
1128 lab = gen_new_label();
1129 if (c->is_64) {
1130 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1131 } else {
1132 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1133 }
1134
1135 /* Branch not taken. */
1136 tcg_gen_goto_tb(0);
1137 tcg_gen_movi_i64(psw_addr, s->next_pc);
1138 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
1139
1140 /* Branch taken. */
1141 gen_set_label(lab);
1142 tcg_gen_goto_tb(1);
1143 tcg_gen_movi_i64(psw_addr, dest);
1144 tcg_gen_exit_tb((tcg_target_long)s->tb + 1);
1145
1146 ret = EXIT_GOTO_TB;
1147 } else {
1148 /* Fallthru can use goto_tb, but taken branch cannot. */
1149 /* Store taken branch destination before the brcond. This
1150 avoids having to allocate a new local temp to hold it.
1151 We'll overwrite this in the not taken case anyway. */
1152 if (!is_imm) {
1153 tcg_gen_mov_i64(psw_addr, cdest);
1154 }
1155
1156 lab = gen_new_label();
1157 if (c->is_64) {
1158 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1159 } else {
1160 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1161 }
1162
1163 /* Branch not taken. */
1164 update_cc_op(s);
1165 tcg_gen_goto_tb(0);
1166 tcg_gen_movi_i64(psw_addr, s->next_pc);
1167 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
1168
1169 gen_set_label(lab);
1170 if (is_imm) {
1171 tcg_gen_movi_i64(psw_addr, dest);
1172 }
1173 ret = EXIT_PC_UPDATED;
1174 }
1175 } else {
1176 /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
1177 Most commonly we're single-stepping or some other condition that
1178 disables all use of goto_tb. Just update the PC and exit. */
1179
1180 TCGv_i64 next = tcg_const_i64(s->next_pc);
1181 if (is_imm) {
1182 cdest = tcg_const_i64(dest);
1183 }
1184
1185 if (c->is_64) {
1186 tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b,
1187 cdest, next);
1188 } else {
1189 TCGv_i32 t0 = tcg_temp_new_i32();
1190 TCGv_i64 t1 = tcg_temp_new_i64();
1191 TCGv_i64 z = tcg_const_i64(0);
1192 tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b);
1193 tcg_gen_extu_i32_i64(t1, t0);
1194 tcg_temp_free_i32(t0);
1195 tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next);
1196 tcg_temp_free_i64(t1);
1197 tcg_temp_free_i64(z);
1198 }
1199
1200 if (is_imm) {
1201 tcg_temp_free_i64(cdest);
1202 }
1203 tcg_temp_free_i64(next);
1204
1205 ret = EXIT_PC_UPDATED;
1206 }
1207
1208 egress:
1209 free_compare(c);
1210 return ret;
1211 }
1212
1213 /* ====================================================================== */
1214 /* The operations. These perform the bulk of the work for any insn,
1215 usually after the operands have been loaded and output initialized. */
1216
1217 static ExitStatus op_abs(DisasContext *s, DisasOps *o)
1218 {
1219 gen_helper_abs_i64(o->out, o->in2);
1220 return NO_EXIT;
1221 }
1222
1223 static ExitStatus op_absf32(DisasContext *s, DisasOps *o)
1224 {
1225 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffull);
1226 return NO_EXIT;
1227 }
1228
1229 static ExitStatus op_absf64(DisasContext *s, DisasOps *o)
1230 {
1231 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull);
1232 return NO_EXIT;
1233 }
1234
1235 static ExitStatus op_absf128(DisasContext *s, DisasOps *o)
1236 {
1237 tcg_gen_andi_i64(o->out, o->in1, 0x7fffffffffffffffull);
1238 tcg_gen_mov_i64(o->out2, o->in2);
1239 return NO_EXIT;
1240 }
1241
1242 static ExitStatus op_add(DisasContext *s, DisasOps *o)
1243 {
1244 tcg_gen_add_i64(o->out, o->in1, o->in2);
1245 return NO_EXIT;
1246 }
1247
1248 static ExitStatus op_addc(DisasContext *s, DisasOps *o)
1249 {
1250 TCGv_i64 cc;
1251
1252 tcg_gen_add_i64(o->out, o->in1, o->in2);
1253
1254 /* XXX possible optimization point */
1255 gen_op_calc_cc(s);
1256 cc = tcg_temp_new_i64();
1257 tcg_gen_extu_i32_i64(cc, cc_op);
1258 tcg_gen_shri_i64(cc, cc, 1);
1259
1260 tcg_gen_add_i64(o->out, o->out, cc);
1261 tcg_temp_free_i64(cc);
1262 return NO_EXIT;
1263 }
1264
1265 static ExitStatus op_aeb(DisasContext *s, DisasOps *o)
1266 {
1267 gen_helper_aeb(o->out, cpu_env, o->in1, o->in2);
1268 return NO_EXIT;
1269 }
1270
1271 static ExitStatus op_adb(DisasContext *s, DisasOps *o)
1272 {
1273 gen_helper_adb(o->out, cpu_env, o->in1, o->in2);
1274 return NO_EXIT;
1275 }
1276
1277 static ExitStatus op_axb(DisasContext *s, DisasOps *o)
1278 {
1279 gen_helper_axb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
1280 return_low128(o->out2);
1281 return NO_EXIT;
1282 }
1283
1284 static ExitStatus op_and(DisasContext *s, DisasOps *o)
1285 {
1286 tcg_gen_and_i64(o->out, o->in1, o->in2);
1287 return NO_EXIT;
1288 }
1289
1290 static ExitStatus op_andi(DisasContext *s, DisasOps *o)
1291 {
1292 int shift = s->insn->data & 0xff;
1293 int size = s->insn->data >> 8;
1294 uint64_t mask = ((1ull << size) - 1) << shift;
1295
1296 assert(!o->g_in2);
1297 tcg_gen_shli_i64(o->in2, o->in2, shift);
1298 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
1299 tcg_gen_and_i64(o->out, o->in1, o->in2);
1300
1301 /* Produce the CC from only the bits manipulated. */
1302 tcg_gen_andi_i64(cc_dst, o->out, mask);
1303 set_cc_nz_u64(s, cc_dst);
1304 return NO_EXIT;
1305 }
1306
1307 static ExitStatus op_bas(DisasContext *s, DisasOps *o)
1308 {
1309 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1310 if (!TCGV_IS_UNUSED_I64(o->in2)) {
1311 tcg_gen_mov_i64(psw_addr, o->in2);
1312 return EXIT_PC_UPDATED;
1313 } else {
1314 return NO_EXIT;
1315 }
1316 }
1317
1318 static ExitStatus op_basi(DisasContext *s, DisasOps *o)
1319 {
1320 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1321 return help_goto_direct(s, s->pc + 2 * get_field(s->fields, i2));
1322 }
1323
1324 static ExitStatus op_bc(DisasContext *s, DisasOps *o)
1325 {
1326 int m1 = get_field(s->fields, m1);
1327 bool is_imm = have_field(s->fields, i2);
1328 int imm = is_imm ? get_field(s->fields, i2) : 0;
1329 DisasCompare c;
1330
1331 disas_jcc(s, &c, m1);
1332 return help_branch(s, &c, is_imm, imm, o->in2);
1333 }
1334
1335 static ExitStatus op_bct32(DisasContext *s, DisasOps *o)
1336 {
1337 int r1 = get_field(s->fields, r1);
1338 bool is_imm = have_field(s->fields, i2);
1339 int imm = is_imm ? get_field(s->fields, i2) : 0;
1340 DisasCompare c;
1341 TCGv_i64 t;
1342
1343 c.cond = TCG_COND_NE;
1344 c.is_64 = false;
1345 c.g1 = false;
1346 c.g2 = false;
1347
1348 t = tcg_temp_new_i64();
1349 tcg_gen_subi_i64(t, regs[r1], 1);
1350 store_reg32_i64(r1, t);
1351 c.u.s32.a = tcg_temp_new_i32();
1352 c.u.s32.b = tcg_const_i32(0);
1353 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
1354 tcg_temp_free_i64(t);
1355
1356 return help_branch(s, &c, is_imm, imm, o->in2);
1357 }
1358
1359 static ExitStatus op_bct64(DisasContext *s, DisasOps *o)
1360 {
1361 int r1 = get_field(s->fields, r1);
1362 bool is_imm = have_field(s->fields, i2);
1363 int imm = is_imm ? get_field(s->fields, i2) : 0;
1364 DisasCompare c;
1365
1366 c.cond = TCG_COND_NE;
1367 c.is_64 = true;
1368 c.g1 = true;
1369 c.g2 = false;
1370
1371 tcg_gen_subi_i64(regs[r1], regs[r1], 1);
1372 c.u.s64.a = regs[r1];
1373 c.u.s64.b = tcg_const_i64(0);
1374
1375 return help_branch(s, &c, is_imm, imm, o->in2);
1376 }
1377
1378 static ExitStatus op_bx32(DisasContext *s, DisasOps *o)
1379 {
1380 int r1 = get_field(s->fields, r1);
1381 int r3 = get_field(s->fields, r3);
1382 bool is_imm = have_field(s->fields, i2);
1383 int imm = is_imm ? get_field(s->fields, i2) : 0;
1384 DisasCompare c;
1385 TCGv_i64 t;
1386
1387 c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT);
1388 c.is_64 = false;
1389 c.g1 = false;
1390 c.g2 = false;
1391
1392 t = tcg_temp_new_i64();
1393 tcg_gen_add_i64(t, regs[r1], regs[r3]);
1394 c.u.s32.a = tcg_temp_new_i32();
1395 c.u.s32.b = tcg_temp_new_i32();
1396 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
1397 tcg_gen_trunc_i64_i32(c.u.s32.b, regs[r3 | 1]);
1398 store_reg32_i64(r1, t);
1399 tcg_temp_free_i64(t);
1400
1401 return help_branch(s, &c, is_imm, imm, o->in2);
1402 }
1403
1404 static ExitStatus op_bx64(DisasContext *s, DisasOps *o)
1405 {
1406 int r1 = get_field(s->fields, r1);
1407 int r3 = get_field(s->fields, r3);
1408 bool is_imm = have_field(s->fields, i2);
1409 int imm = is_imm ? get_field(s->fields, i2) : 0;
1410 DisasCompare c;
1411
1412 c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT);
1413 c.is_64 = true;
1414
1415 if (r1 == (r3 | 1)) {
1416 c.u.s64.b = load_reg(r3 | 1);
1417 c.g2 = false;
1418 } else {
1419 c.u.s64.b = regs[r3 | 1];
1420 c.g2 = true;
1421 }
1422
1423 tcg_gen_add_i64(regs[r1], regs[r1], regs[r3]);
1424 c.u.s64.a = regs[r1];
1425 c.g1 = true;
1426
1427 return help_branch(s, &c, is_imm, imm, o->in2);
1428 }
1429
1430 static ExitStatus op_cj(DisasContext *s, DisasOps *o)
1431 {
1432 int imm, m3 = get_field(s->fields, m3);
1433 bool is_imm;
1434 DisasCompare c;
1435
1436 /* Bit 3 of the m3 field is reserved and should be zero.
1437 Choose to ignore it wrt the ltgt_cond table above. */
1438 c.cond = ltgt_cond[m3 & 14];
1439 if (s->insn->data) {
1440 c.cond = tcg_unsigned_cond(c.cond);
1441 }
1442 c.is_64 = c.g1 = c.g2 = true;
1443 c.u.s64.a = o->in1;
1444 c.u.s64.b = o->in2;
1445
1446 is_imm = have_field(s->fields, i4);
1447 if (is_imm) {
1448 imm = get_field(s->fields, i4);
1449 } else {
1450 imm = 0;
1451 o->out = get_address(s, 0, get_field(s->fields, b4),
1452 get_field(s->fields, d4));
1453 }
1454
1455 return help_branch(s, &c, is_imm, imm, o->out);
1456 }
1457
1458 static ExitStatus op_ceb(DisasContext *s, DisasOps *o)
1459 {
1460 gen_helper_ceb(cc_op, cpu_env, o->in1, o->in2);
1461 set_cc_static(s);
1462 return NO_EXIT;
1463 }
1464
1465 static ExitStatus op_cdb(DisasContext *s, DisasOps *o)
1466 {
1467 gen_helper_cdb(cc_op, cpu_env, o->in1, o->in2);
1468 set_cc_static(s);
1469 return NO_EXIT;
1470 }
1471
1472 static ExitStatus op_cxb(DisasContext *s, DisasOps *o)
1473 {
1474 gen_helper_cxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2);
1475 set_cc_static(s);
1476 return NO_EXIT;
1477 }
1478
1479 static ExitStatus op_cfeb(DisasContext *s, DisasOps *o)
1480 {
1481 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1482 gen_helper_cfeb(o->out, cpu_env, o->in2, m3);
1483 tcg_temp_free_i32(m3);
1484 gen_set_cc_nz_f32(s, o->in2);
1485 return NO_EXIT;
1486 }
1487
1488 static ExitStatus op_cfdb(DisasContext *s, DisasOps *o)
1489 {
1490 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1491 gen_helper_cfdb(o->out, cpu_env, o->in2, m3);
1492 tcg_temp_free_i32(m3);
1493 gen_set_cc_nz_f64(s, o->in2);
1494 return NO_EXIT;
1495 }
1496
1497 static ExitStatus op_cfxb(DisasContext *s, DisasOps *o)
1498 {
1499 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1500 gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m3);
1501 tcg_temp_free_i32(m3);
1502 gen_set_cc_nz_f128(s, o->in1, o->in2);
1503 return NO_EXIT;
1504 }
1505
1506 static ExitStatus op_cgeb(DisasContext *s, DisasOps *o)
1507 {
1508 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1509 gen_helper_cgeb(o->out, cpu_env, o->in2, m3);
1510 tcg_temp_free_i32(m3);
1511 gen_set_cc_nz_f32(s, o->in2);
1512 return NO_EXIT;
1513 }
1514
1515 static ExitStatus op_cgdb(DisasContext *s, DisasOps *o)
1516 {
1517 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1518 gen_helper_cgdb(o->out, cpu_env, o->in2, m3);
1519 tcg_temp_free_i32(m3);
1520 gen_set_cc_nz_f64(s, o->in2);
1521 return NO_EXIT;
1522 }
1523
1524 static ExitStatus op_cgxb(DisasContext *s, DisasOps *o)
1525 {
1526 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1527 gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m3);
1528 tcg_temp_free_i32(m3);
1529 gen_set_cc_nz_f128(s, o->in1, o->in2);
1530 return NO_EXIT;
1531 }
1532
1533 static ExitStatus op_clfeb(DisasContext *s, DisasOps *o)
1534 {
1535 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1536 gen_helper_clfeb(o->out, cpu_env, o->in2, m3);
1537 tcg_temp_free_i32(m3);
1538 gen_set_cc_nz_f32(s, o->in2);
1539 return NO_EXIT;
1540 }
1541
1542 static ExitStatus op_clfdb(DisasContext *s, DisasOps *o)
1543 {
1544 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1545 gen_helper_clfdb(o->out, cpu_env, o->in2, m3);
1546 tcg_temp_free_i32(m3);
1547 gen_set_cc_nz_f64(s, o->in2);
1548 return NO_EXIT;
1549 }
1550
1551 static ExitStatus op_clfxb(DisasContext *s, DisasOps *o)
1552 {
1553 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1554 gen_helper_clfxb(o->out, cpu_env, o->in1, o->in2, m3);
1555 tcg_temp_free_i32(m3);
1556 gen_set_cc_nz_f128(s, o->in1, o->in2);
1557 return NO_EXIT;
1558 }
1559
1560 static ExitStatus op_clgeb(DisasContext *s, DisasOps *o)
1561 {
1562 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1563 gen_helper_clgeb(o->out, cpu_env, o->in2, m3);
1564 tcg_temp_free_i32(m3);
1565 gen_set_cc_nz_f32(s, o->in2);
1566 return NO_EXIT;
1567 }
1568
1569 static ExitStatus op_clgdb(DisasContext *s, DisasOps *o)
1570 {
1571 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1572 gen_helper_clgdb(o->out, cpu_env, o->in2, m3);
1573 tcg_temp_free_i32(m3);
1574 gen_set_cc_nz_f64(s, o->in2);
1575 return NO_EXIT;
1576 }
1577
1578 static ExitStatus op_clgxb(DisasContext *s, DisasOps *o)
1579 {
1580 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1581 gen_helper_clgxb(o->out, cpu_env, o->in1, o->in2, m3);
1582 tcg_temp_free_i32(m3);
1583 gen_set_cc_nz_f128(s, o->in1, o->in2);
1584 return NO_EXIT;
1585 }
1586
1587 static ExitStatus op_cegb(DisasContext *s, DisasOps *o)
1588 {
1589 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1590 gen_helper_cegb(o->out, cpu_env, o->in2, m3);
1591 tcg_temp_free_i32(m3);
1592 return NO_EXIT;
1593 }
1594
1595 static ExitStatus op_cdgb(DisasContext *s, DisasOps *o)
1596 {
1597 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1598 gen_helper_cdgb(o->out, cpu_env, o->in2, m3);
1599 tcg_temp_free_i32(m3);
1600 return NO_EXIT;
1601 }
1602
1603 static ExitStatus op_cxgb(DisasContext *s, DisasOps *o)
1604 {
1605 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1606 gen_helper_cxgb(o->out, cpu_env, o->in2, m3);
1607 tcg_temp_free_i32(m3);
1608 return_low128(o->out2);
1609 return NO_EXIT;
1610 }
1611
1612 static ExitStatus op_celgb(DisasContext *s, DisasOps *o)
1613 {
1614 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1615 gen_helper_celgb(o->out, cpu_env, o->in2, m3);
1616 tcg_temp_free_i32(m3);
1617 return NO_EXIT;
1618 }
1619
1620 static ExitStatus op_cdlgb(DisasContext *s, DisasOps *o)
1621 {
1622 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1623 gen_helper_cdlgb(o->out, cpu_env, o->in2, m3);
1624 tcg_temp_free_i32(m3);
1625 return NO_EXIT;
1626 }
1627
1628 static ExitStatus op_cxlgb(DisasContext *s, DisasOps *o)
1629 {
1630 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1631 gen_helper_cxlgb(o->out, cpu_env, o->in2, m3);
1632 tcg_temp_free_i32(m3);
1633 return_low128(o->out2);
1634 return NO_EXIT;
1635 }
1636
1637 static ExitStatus op_cksm(DisasContext *s, DisasOps *o)
1638 {
1639 int r2 = get_field(s->fields, r2);
1640 TCGv_i64 len = tcg_temp_new_i64();
1641
1642 potential_page_fault(s);
1643 gen_helper_cksm(len, cpu_env, o->in1, o->in2, regs[r2 + 1]);
1644 set_cc_static(s);
1645 return_low128(o->out);
1646
1647 tcg_gen_add_i64(regs[r2], regs[r2], len);
1648 tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len);
1649 tcg_temp_free_i64(len);
1650
1651 return NO_EXIT;
1652 }
1653
1654 static ExitStatus op_clc(DisasContext *s, DisasOps *o)
1655 {
1656 int l = get_field(s->fields, l1);
1657 TCGv_i32 vl;
1658
1659 switch (l + 1) {
1660 case 1:
1661 tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s));
1662 tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s));
1663 break;
1664 case 2:
1665 tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s));
1666 tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s));
1667 break;
1668 case 4:
1669 tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s));
1670 tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s));
1671 break;
1672 case 8:
1673 tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s));
1674 tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
1675 break;
1676 default:
1677 potential_page_fault(s);
1678 vl = tcg_const_i32(l);
1679 gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
1680 tcg_temp_free_i32(vl);
1681 set_cc_static(s);
1682 return NO_EXIT;
1683 }
1684 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
1685 return NO_EXIT;
1686 }
1687
1688 static ExitStatus op_clcle(DisasContext *s, DisasOps *o)
1689 {
1690 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1691 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
1692 potential_page_fault(s);
1693 gen_helper_clcle(cc_op, cpu_env, r1, o->in2, r3);
1694 tcg_temp_free_i32(r1);
1695 tcg_temp_free_i32(r3);
1696 set_cc_static(s);
1697 return NO_EXIT;
1698 }
1699
1700 static ExitStatus op_clm(DisasContext *s, DisasOps *o)
1701 {
1702 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1703 TCGv_i32 t1 = tcg_temp_new_i32();
1704 tcg_gen_trunc_i64_i32(t1, o->in1);
1705 potential_page_fault(s);
1706 gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2);
1707 set_cc_static(s);
1708 tcg_temp_free_i32(t1);
1709 tcg_temp_free_i32(m3);
1710 return NO_EXIT;
1711 }
1712
1713 static ExitStatus op_clst(DisasContext *s, DisasOps *o)
1714 {
1715 potential_page_fault(s);
1716 gen_helper_clst(o->in1, cpu_env, regs[0], o->in1, o->in2);
1717 set_cc_static(s);
1718 return_low128(o->in2);
1719 return NO_EXIT;
1720 }
1721
1722 static ExitStatus op_cs(DisasContext *s, DisasOps *o)
1723 {
1724 int r3 = get_field(s->fields, r3);
1725 potential_page_fault(s);
1726 gen_helper_cs(o->out, cpu_env, o->in1, o->in2, regs[r3]);
1727 set_cc_static(s);
1728 return NO_EXIT;
1729 }
1730
1731 static ExitStatus op_csg(DisasContext *s, DisasOps *o)
1732 {
1733 int r3 = get_field(s->fields, r3);
1734 potential_page_fault(s);
1735 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, regs[r3]);
1736 set_cc_static(s);
1737 return NO_EXIT;
1738 }
1739
1740 #ifndef CONFIG_USER_ONLY
1741 static ExitStatus op_csp(DisasContext *s, DisasOps *o)
1742 {
1743 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1744 check_privileged(s);
1745 gen_helper_csp(cc_op, cpu_env, r1, o->in2);
1746 tcg_temp_free_i32(r1);
1747 set_cc_static(s);
1748 return NO_EXIT;
1749 }
1750 #endif
1751
1752 static ExitStatus op_cds(DisasContext *s, DisasOps *o)
1753 {
1754 int r3 = get_field(s->fields, r3);
1755 TCGv_i64 in3 = tcg_temp_new_i64();
1756 tcg_gen_deposit_i64(in3, regs[r3 + 1], regs[r3], 32, 32);
1757 potential_page_fault(s);
1758 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, in3);
1759 tcg_temp_free_i64(in3);
1760 set_cc_static(s);
1761 return NO_EXIT;
1762 }
1763
1764 static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
1765 {
1766 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1767 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
1768 potential_page_fault(s);
1769 /* XXX rewrite in tcg */
1770 gen_helper_cdsg(cc_op, cpu_env, r1, o->in2, r3);
1771 set_cc_static(s);
1772 return NO_EXIT;
1773 }
1774
1775 static ExitStatus op_cvd(DisasContext *s, DisasOps *o)
1776 {
1777 TCGv_i64 t1 = tcg_temp_new_i64();
1778 TCGv_i32 t2 = tcg_temp_new_i32();
1779 tcg_gen_trunc_i64_i32(t2, o->in1);
1780 gen_helper_cvd(t1, t2);
1781 tcg_temp_free_i32(t2);
1782 tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
1783 tcg_temp_free_i64(t1);
1784 return NO_EXIT;
1785 }
1786
1787 static ExitStatus op_ct(DisasContext *s, DisasOps *o)
1788 {
1789 int m3 = get_field(s->fields, m3);
1790 int lab = gen_new_label();
1791 TCGv_i32 t;
1792 TCGCond c;
1793
1794 /* Bit 3 of the m3 field is reserved and should be zero.
1795 Choose to ignore it wrt the ltgt_cond table above. */
1796 c = tcg_invert_cond(ltgt_cond[m3 & 14]);
1797 if (s->insn->data) {
1798 c = tcg_unsigned_cond(c);
1799 }
1800 tcg_gen_brcond_i64(c, o->in1, o->in2, lab);
1801
1802 /* Set DXC to 0xff. */
1803 t = tcg_temp_new_i32();
1804 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUS390XState, fpc));
1805 tcg_gen_ori_i32(t, t, 0xff00);
1806 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, fpc));
1807 tcg_temp_free_i32(t);
1808
1809 /* Trap. */
1810 gen_program_exception(s, PGM_DATA);
1811
1812 gen_set_label(lab);
1813 return NO_EXIT;
1814 }
1815
1816 #ifndef CONFIG_USER_ONLY
1817 static ExitStatus op_diag(DisasContext *s, DisasOps *o)
1818 {
1819 TCGv_i32 tmp;
1820
1821 check_privileged(s);
1822 potential_page_fault(s);
1823
1824 /* We pretend the format is RX_a so that D2 is the field we want. */
1825 tmp = tcg_const_i32(get_field(s->fields, d2) & 0xfff);
1826 gen_helper_diag(regs[2], cpu_env, tmp, regs[2], regs[1]);
1827 tcg_temp_free_i32(tmp);
1828 return NO_EXIT;
1829 }
1830 #endif
1831
1832 static ExitStatus op_divs32(DisasContext *s, DisasOps *o)
1833 {
1834 gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2);
1835 return_low128(o->out);
1836 return NO_EXIT;
1837 }
1838
1839 static ExitStatus op_divu32(DisasContext *s, DisasOps *o)
1840 {
1841 gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2);
1842 return_low128(o->out);
1843 return NO_EXIT;
1844 }
1845
1846 static ExitStatus op_divs64(DisasContext *s, DisasOps *o)
1847 {
1848 gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2);
1849 return_low128(o->out);
1850 return NO_EXIT;
1851 }
1852
1853 static ExitStatus op_divu64(DisasContext *s, DisasOps *o)
1854 {
1855 gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2);
1856 return_low128(o->out);
1857 return NO_EXIT;
1858 }
1859
1860 static ExitStatus op_deb(DisasContext *s, DisasOps *o)
1861 {
1862 gen_helper_deb(o->out, cpu_env, o->in1, o->in2);
1863 return NO_EXIT;
1864 }
1865
1866 static ExitStatus op_ddb(DisasContext *s, DisasOps *o)
1867 {
1868 gen_helper_ddb(o->out, cpu_env, o->in1, o->in2);
1869 return NO_EXIT;
1870 }
1871
1872 static ExitStatus op_dxb(DisasContext *s, DisasOps *o)
1873 {
1874 gen_helper_dxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
1875 return_low128(o->out2);
1876 return NO_EXIT;
1877 }
1878
1879 static ExitStatus op_ear(DisasContext *s, DisasOps *o)
1880 {
1881 int r2 = get_field(s->fields, r2);
1882 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, aregs[r2]));
1883 return NO_EXIT;
1884 }
1885
1886 static ExitStatus op_efpc(DisasContext *s, DisasOps *o)
1887 {
1888 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, fpc));
1889 return NO_EXIT;
1890 }
1891
1892 static ExitStatus op_ex(DisasContext *s, DisasOps *o)
1893 {
1894 /* ??? Perhaps a better way to implement EXECUTE is to set a bit in
1895 tb->flags, (ab)use the tb->cs_base field as the address of
1896 the template in memory, and grab 8 bits of tb->flags/cflags for
1897 the contents of the register. We would then recognize all this
1898 in gen_intermediate_code_internal, generating code for exactly
1899 one instruction. This new TB then gets executed normally.
1900
1901 On the other hand, this seems to be mostly used for modifying
1902 MVC inside of memcpy, which needs a helper call anyway. So
1903 perhaps this doesn't bear thinking about any further. */
1904
1905 TCGv_i64 tmp;
1906
1907 update_psw_addr(s);
1908 update_cc_op(s);
1909
1910 tmp = tcg_const_i64(s->next_pc);
1911 gen_helper_ex(cc_op, cpu_env, cc_op, o->in1, o->in2, tmp);
1912 tcg_temp_free_i64(tmp);
1913
1914 set_cc_static(s);
1915 return NO_EXIT;
1916 }
1917
1918 static ExitStatus op_flogr(DisasContext *s, DisasOps *o)
1919 {
1920 /* We'll use the original input for cc computation, since we get to
1921 compare that against 0, which ought to be better than comparing
1922 the real output against 64. It also lets cc_dst be a convenient
1923 temporary during our computation. */
1924 gen_op_update1_cc_i64(s, CC_OP_FLOGR, o->in2);
1925
1926 /* R1 = IN ? CLZ(IN) : 64. */
1927 gen_helper_clz(o->out, o->in2);
1928
1929 /* R1+1 = IN & ~(found bit). Note that we may attempt to shift this
1930 value by 64, which is undefined. But since the shift is 64 iff the
1931 input is zero, we still get the correct result after and'ing. */
1932 tcg_gen_movi_i64(o->out2, 0x8000000000000000ull);
1933 tcg_gen_shr_i64(o->out2, o->out2, o->out);
1934 tcg_gen_andc_i64(o->out2, cc_dst, o->out2);
1935 return NO_EXIT;
1936 }
1937
1938 static ExitStatus op_icm(DisasContext *s, DisasOps *o)
1939 {
1940 int m3 = get_field(s->fields, m3);
1941 int pos, len, base = s->insn->data;
1942 TCGv_i64 tmp = tcg_temp_new_i64();
1943 uint64_t ccm;
1944
1945 switch (m3) {
1946 case 0xf:
1947 /* Effectively a 32-bit load. */
1948 tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
1949 len = 32;
1950 goto one_insert;
1951
1952 case 0xc:
1953 case 0x6:
1954 case 0x3:
1955 /* Effectively a 16-bit load. */
1956 tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
1957 len = 16;
1958 goto one_insert;
1959
1960 case 0x8:
1961 case 0x4:
1962 case 0x2:
1963 case 0x1:
1964 /* Effectively an 8-bit load. */
1965 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
1966 len = 8;
1967 goto one_insert;
1968
1969 one_insert:
1970 pos = base + ctz32(m3) * 8;
1971 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len);
1972 ccm = ((1ull << len) - 1) << pos;
1973 break;
1974
1975 default:
1976 /* This is going to be a sequence of loads and inserts. */
1977 pos = base + 32 - 8;
1978 ccm = 0;
1979 while (m3) {
1980 if (m3 & 0x8) {
1981 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
1982 tcg_gen_addi_i64(o->in2, o->in2, 1);
1983 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
1984 ccm |= 0xff << pos;
1985 }
1986 m3 = (m3 << 1) & 0xf;
1987 pos -= 8;
1988 }
1989 break;
1990 }
1991
1992 tcg_gen_movi_i64(tmp, ccm);
1993 gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out);
1994 tcg_temp_free_i64(tmp);
1995 return NO_EXIT;
1996 }
1997
1998 static ExitStatus op_insi(DisasContext *s, DisasOps *o)
1999 {
2000 int shift = s->insn->data & 0xff;
2001 int size = s->insn->data >> 8;
2002 tcg_gen_deposit_i64(o->out, o->in1, o->in2, shift, size);
2003 return NO_EXIT;
2004 }
2005
2006 static ExitStatus op_ipm(DisasContext *s, DisasOps *o)
2007 {
2008 TCGv_i64 t1;
2009
2010 gen_op_calc_cc(s);
2011 tcg_gen_andi_i64(o->out, o->out, ~0xff000000ull);
2012
2013 t1 = tcg_temp_new_i64();
2014 tcg_gen_shli_i64(t1, psw_mask, 20);
2015 tcg_gen_shri_i64(t1, t1, 36);
2016 tcg_gen_or_i64(o->out, o->out, t1);
2017
2018 tcg_gen_extu_i32_i64(t1, cc_op);
2019 tcg_gen_shli_i64(t1, t1, 28);
2020 tcg_gen_or_i64(o->out, o->out, t1);
2021 tcg_temp_free_i64(t1);
2022 return NO_EXIT;
2023 }
2024
2025 #ifndef CONFIG_USER_ONLY
2026 static ExitStatus op_ipte(DisasContext *s, DisasOps *o)
2027 {
2028 check_privileged(s);
2029 gen_helper_ipte(cpu_env, o->in1, o->in2);
2030 return NO_EXIT;
2031 }
2032
2033 static ExitStatus op_iske(DisasContext *s, DisasOps *o)
2034 {
2035 check_privileged(s);
2036 gen_helper_iske(o->out, cpu_env, o->in2);
2037 return NO_EXIT;
2038 }
2039 #endif
2040
2041 static ExitStatus op_ldeb(DisasContext *s, DisasOps *o)
2042 {
2043 gen_helper_ldeb(o->out, cpu_env, o->in2);
2044 return NO_EXIT;
2045 }
2046
2047 static ExitStatus op_ledb(DisasContext *s, DisasOps *o)
2048 {
2049 gen_helper_ledb(o->out, cpu_env, o->in2);
2050 return NO_EXIT;
2051 }
2052
2053 static ExitStatus op_ldxb(DisasContext *s, DisasOps *o)
2054 {
2055 gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2);
2056 return NO_EXIT;
2057 }
2058
2059 static ExitStatus op_lexb(DisasContext *s, DisasOps *o)
2060 {
2061 gen_helper_lexb(o->out, cpu_env, o->in1, o->in2);
2062 return NO_EXIT;
2063 }
2064
2065 static ExitStatus op_lxdb(DisasContext *s, DisasOps *o)
2066 {
2067 gen_helper_lxdb(o->out, cpu_env, o->in2);
2068 return_low128(o->out2);
2069 return NO_EXIT;
2070 }
2071
2072 static ExitStatus op_lxeb(DisasContext *s, DisasOps *o)
2073 {
2074 gen_helper_lxeb(o->out, cpu_env, o->in2);
2075 return_low128(o->out2);
2076 return NO_EXIT;
2077 }
2078
2079 static ExitStatus op_llgt(DisasContext *s, DisasOps *o)
2080 {
2081 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffff);
2082 return NO_EXIT;
2083 }
2084
2085 static ExitStatus op_ld8s(DisasContext *s, DisasOps *o)
2086 {
2087 tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
2088 return NO_EXIT;
2089 }
2090
2091 static ExitStatus op_ld8u(DisasContext *s, DisasOps *o)
2092 {
2093 tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
2094 return NO_EXIT;
2095 }
2096
2097 static ExitStatus op_ld16s(DisasContext *s, DisasOps *o)
2098 {
2099 tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
2100 return NO_EXIT;
2101 }
2102
2103 static ExitStatus op_ld16u(DisasContext *s, DisasOps *o)
2104 {
2105 tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
2106 return NO_EXIT;
2107 }
2108
2109 static ExitStatus op_ld32s(DisasContext *s, DisasOps *o)
2110 {
2111 tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s));
2112 return NO_EXIT;
2113 }
2114
2115 static ExitStatus op_ld32u(DisasContext *s, DisasOps *o)
2116 {
2117 tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
2118 return NO_EXIT;
2119 }
2120
2121 static ExitStatus op_ld64(DisasContext *s, DisasOps *o)
2122 {
2123 tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
2124 return NO_EXIT;
2125 }
2126
2127 static ExitStatus op_loc(DisasContext *s, DisasOps *o)
2128 {
2129 DisasCompare c;
2130
2131 disas_jcc(s, &c, get_field(s->fields, m3));
2132
2133 if (c.is_64) {
2134 tcg_gen_movcond_i64(c.cond, o->out, c.u.s64.a, c.u.s64.b,
2135 o->in2, o->in1);
2136 free_compare(&c);
2137 } else {
2138 TCGv_i32 t32 = tcg_temp_new_i32();
2139 TCGv_i64 t, z;
2140
2141 tcg_gen_setcond_i32(c.cond, t32, c.u.s32.a, c.u.s32.b);
2142 free_compare(&c);
2143
2144 t = tcg_temp_new_i64();
2145 tcg_gen_extu_i32_i64(t, t32);
2146 tcg_temp_free_i32(t32);
2147
2148 z = tcg_const_i64(0);
2149 tcg_gen_movcond_i64(TCG_COND_NE, o->out, t, z, o->in2, o->in1);
2150 tcg_temp_free_i64(t);
2151 tcg_temp_free_i64(z);
2152 }
2153
2154 return NO_EXIT;
2155 }
2156
2157 #ifndef CONFIG_USER_ONLY
2158 static ExitStatus op_lctl(DisasContext *s, DisasOps *o)
2159 {
2160 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2161 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2162 check_privileged(s);
2163 potential_page_fault(s);
2164 gen_helper_lctl(cpu_env, r1, o->in2, r3);
2165 tcg_temp_free_i32(r1);
2166 tcg_temp_free_i32(r3);
2167 return NO_EXIT;
2168 }
2169
2170 static ExitStatus op_lctlg(DisasContext *s, DisasOps *o)
2171 {
2172 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2173 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2174 check_privileged(s);
2175 potential_page_fault(s);
2176 gen_helper_lctlg(cpu_env, r1, o->in2, r3);
2177 tcg_temp_free_i32(r1);
2178 tcg_temp_free_i32(r3);
2179 return NO_EXIT;
2180 }
2181 static ExitStatus op_lra(DisasContext *s, DisasOps *o)
2182 {
2183 check_privileged(s);
2184 potential_page_fault(s);
2185 gen_helper_lra(o->out, cpu_env, o->in2);
2186 set_cc_static(s);
2187 return NO_EXIT;
2188 }
2189
2190 static ExitStatus op_lpsw(DisasContext *s, DisasOps *o)
2191 {
2192 TCGv_i64 t1, t2;
2193
2194 check_privileged(s);
2195
2196 t1 = tcg_temp_new_i64();
2197 t2 = tcg_temp_new_i64();
2198 tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
2199 tcg_gen_addi_i64(o->in2, o->in2, 4);
2200 tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s));
2201 /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
2202 tcg_gen_shli_i64(t1, t1, 32);
2203 gen_helper_load_psw(cpu_env, t1, t2);
2204 tcg_temp_free_i64(t1);
2205 tcg_temp_free_i64(t2);
2206 return EXIT_NORETURN;
2207 }
2208
2209 static ExitStatus op_lpswe(DisasContext *s, DisasOps *o)
2210 {
2211 TCGv_i64 t1, t2;
2212
2213 check_privileged(s);
2214
2215 t1 = tcg_temp_new_i64();
2216 t2 = tcg_temp_new_i64();
2217 tcg_gen_qemu_ld64(t1, o->in2, get_mem_index(s));
2218 tcg_gen_addi_i64(o->in2, o->in2, 8);
2219 tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s));
2220 gen_helper_load_psw(cpu_env, t1, t2);
2221 tcg_temp_free_i64(t1);
2222 tcg_temp_free_i64(t2);
2223 return EXIT_NORETURN;
2224 }
2225 #endif
2226
2227 static ExitStatus op_lam(DisasContext *s, DisasOps *o)
2228 {
2229 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2230 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2231 potential_page_fault(s);
2232 gen_helper_lam(cpu_env, r1, o->in2, r3);
2233 tcg_temp_free_i32(r1);
2234 tcg_temp_free_i32(r3);
2235 return NO_EXIT;
2236 }
2237
2238 static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
2239 {
2240 int r1 = get_field(s->fields, r1);
2241 int r3 = get_field(s->fields, r3);
2242 TCGv_i64 t = tcg_temp_new_i64();
2243 TCGv_i64 t4 = tcg_const_i64(4);
2244
2245 while (1) {
2246 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2247 store_reg32_i64(r1, t);
2248 if (r1 == r3) {
2249 break;
2250 }
2251 tcg_gen_add_i64(o->in2, o->in2, t4);
2252 r1 = (r1 + 1) & 15;
2253 }
2254
2255 tcg_temp_free_i64(t);
2256 tcg_temp_free_i64(t4);
2257 return NO_EXIT;
2258 }
2259
2260 static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
2261 {
2262 int r1 = get_field(s->fields, r1);
2263 int r3 = get_field(s->fields, r3);
2264 TCGv_i64 t = tcg_temp_new_i64();
2265 TCGv_i64 t4 = tcg_const_i64(4);
2266
2267 while (1) {
2268 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2269 store_reg32h_i64(r1, t);
2270 if (r1 == r3) {
2271 break;
2272 }
2273 tcg_gen_add_i64(o->in2, o->in2, t4);
2274 r1 = (r1 + 1) & 15;
2275 }
2276
2277 tcg_temp_free_i64(t);
2278 tcg_temp_free_i64(t4);
2279 return NO_EXIT;
2280 }
2281
2282 static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
2283 {
2284 int r1 = get_field(s->fields, r1);
2285 int r3 = get_field(s->fields, r3);
2286 TCGv_i64 t8 = tcg_const_i64(8);
2287
2288 while (1) {
2289 tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
2290 if (r1 == r3) {
2291 break;
2292 }
2293 tcg_gen_add_i64(o->in2, o->in2, t8);
2294 r1 = (r1 + 1) & 15;
2295 }
2296
2297 tcg_temp_free_i64(t8);
2298 return NO_EXIT;
2299 }
2300
2301 static ExitStatus op_mov2(DisasContext *s, DisasOps *o)
2302 {
2303 o->out = o->in2;
2304 o->g_out = o->g_in2;
2305 TCGV_UNUSED_I64(o->in2);
2306 o->g_in2 = false;
2307 return NO_EXIT;
2308 }
2309
2310 static ExitStatus op_movx(DisasContext *s, DisasOps *o)
2311 {
2312 o->out = o->in1;
2313 o->out2 = o->in2;
2314 o->g_out = o->g_in1;
2315 o->g_out2 = o->g_in2;
2316 TCGV_UNUSED_I64(o->in1);
2317 TCGV_UNUSED_I64(o->in2);
2318 o->g_in1 = o->g_in2 = false;
2319 return NO_EXIT;
2320 }
2321
2322 static ExitStatus op_mvc(DisasContext *s, DisasOps *o)
2323 {
2324 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2325 potential_page_fault(s);
2326 gen_helper_mvc(cpu_env, l, o->addr1, o->in2);
2327 tcg_temp_free_i32(l);
2328 return NO_EXIT;
2329 }
2330
2331 static ExitStatus op_mvcl(DisasContext *s, DisasOps *o)
2332 {
2333 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2334 TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
2335 potential_page_fault(s);
2336 gen_helper_mvcl(cc_op, cpu_env, r1, r2);
2337 tcg_temp_free_i32(r1);
2338 tcg_temp_free_i32(r2);
2339 set_cc_static(s);
2340 return NO_EXIT;
2341 }
2342
2343 static ExitStatus op_mvcle(DisasContext *s, DisasOps *o)
2344 {
2345 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2346 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2347 potential_page_fault(s);
2348 gen_helper_mvcle(cc_op, cpu_env, r1, o->in2, r3);
2349 tcg_temp_free_i32(r1);
2350 tcg_temp_free_i32(r3);
2351 set_cc_static(s);
2352 return NO_EXIT;
2353 }
2354
2355 #ifndef CONFIG_USER_ONLY
2356 static ExitStatus op_mvcp(DisasContext *s, DisasOps *o)
2357 {
2358 int r1 = get_field(s->fields, l1);
2359 check_privileged(s);
2360 potential_page_fault(s);
2361 gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2362 set_cc_static(s);
2363 return NO_EXIT;
2364 }
2365
2366 static ExitStatus op_mvcs(DisasContext *s, DisasOps *o)
2367 {
2368 int r1 = get_field(s->fields, l1);
2369 check_privileged(s);
2370 potential_page_fault(s);
2371 gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2372 set_cc_static(s);
2373 return NO_EXIT;
2374 }
2375 #endif
2376
2377 static ExitStatus op_mvpg(DisasContext *s, DisasOps *o)
2378 {
2379 potential_page_fault(s);
2380 gen_helper_mvpg(cpu_env, regs[0], o->in1, o->in2);
2381 set_cc_static(s);
2382 return NO_EXIT;
2383 }
2384
2385 static ExitStatus op_mvst(DisasContext *s, DisasOps *o)
2386 {
2387 potential_page_fault(s);
2388 gen_helper_mvst(o->in1, cpu_env, regs[0], o->in1, o->in2);
2389 set_cc_static(s);
2390 return_low128(o->in2);
2391 return NO_EXIT;
2392 }
2393
2394 static ExitStatus op_mul(DisasContext *s, DisasOps *o)
2395 {
2396 tcg_gen_mul_i64(o->out, o->in1, o->in2);
2397 return NO_EXIT;
2398 }
2399
2400 static ExitStatus op_mul128(DisasContext *s, DisasOps *o)
2401 {
2402 gen_helper_mul128(o->out, cpu_env, o->in1, o->in2);
2403 return_low128(o->out2);
2404 return NO_EXIT;
2405 }
2406
2407 static ExitStatus op_meeb(DisasContext *s, DisasOps *o)
2408 {
2409 gen_helper_meeb(o->out, cpu_env, o->in1, o->in2);
2410 return NO_EXIT;
2411 }
2412
2413 static ExitStatus op_mdeb(DisasContext *s, DisasOps *o)
2414 {
2415 gen_helper_mdeb(o->out, cpu_env, o->in1, o->in2);
2416 return NO_EXIT;
2417 }
2418
2419 static ExitStatus op_mdb(DisasContext *s, DisasOps *o)
2420 {
2421 gen_helper_mdb(o->out, cpu_env, o->in1, o->in2);
2422 return NO_EXIT;
2423 }
2424
2425 static ExitStatus op_mxb(DisasContext *s, DisasOps *o)
2426 {
2427 gen_helper_mxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2428 return_low128(o->out2);
2429 return NO_EXIT;
2430 }
2431
2432 static ExitStatus op_mxdb(DisasContext *s, DisasOps *o)
2433 {
2434 gen_helper_mxdb(o->out, cpu_env, o->out, o->out2, o->in2);
2435 return_low128(o->out2);
2436 return NO_EXIT;
2437 }
2438
2439 static ExitStatus op_maeb(DisasContext *s, DisasOps *o)
2440 {
2441 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2442 gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3);
2443 tcg_temp_free_i64(r3);
2444 return NO_EXIT;
2445 }
2446
2447 static ExitStatus op_madb(DisasContext *s, DisasOps *o)
2448 {
2449 int r3 = get_field(s->fields, r3);
2450 gen_helper_madb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2451 return NO_EXIT;
2452 }
2453
2454 static ExitStatus op_mseb(DisasContext *s, DisasOps *o)
2455 {
2456 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2457 gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3);
2458 tcg_temp_free_i64(r3);
2459 return NO_EXIT;
2460 }
2461
2462 static ExitStatus op_msdb(DisasContext *s, DisasOps *o)
2463 {
2464 int r3 = get_field(s->fields, r3);
2465 gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2466 return NO_EXIT;
2467 }
2468
2469 static ExitStatus op_nabs(DisasContext *s, DisasOps *o)
2470 {
2471 gen_helper_nabs_i64(o->out, o->in2);
2472 return NO_EXIT;
2473 }
2474
2475 static ExitStatus op_nabsf32(DisasContext *s, DisasOps *o)
2476 {
2477 tcg_gen_ori_i64(o->out, o->in2, 0x80000000ull);
2478 return NO_EXIT;
2479 }
2480
2481 static ExitStatus op_nabsf64(DisasContext *s, DisasOps *o)
2482 {
2483 tcg_gen_ori_i64(o->out, o->in2, 0x8000000000000000ull);
2484 return NO_EXIT;
2485 }
2486
2487 static ExitStatus op_nabsf128(DisasContext *s, DisasOps *o)
2488 {
2489 tcg_gen_ori_i64(o->out, o->in1, 0x8000000000000000ull);
2490 tcg_gen_mov_i64(o->out2, o->in2);
2491 return NO_EXIT;
2492 }
2493
2494 static ExitStatus op_nc(DisasContext *s, DisasOps *o)
2495 {
2496 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2497 potential_page_fault(s);
2498 gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2);
2499 tcg_temp_free_i32(l);
2500 set_cc_static(s);
2501 return NO_EXIT;
2502 }
2503
2504 static ExitStatus op_neg(DisasContext *s, DisasOps *o)
2505 {
2506 tcg_gen_neg_i64(o->out, o->in2);
2507 return NO_EXIT;
2508 }
2509
2510 static ExitStatus op_negf32(DisasContext *s, DisasOps *o)
2511 {
2512 tcg_gen_xori_i64(o->out, o->in2, 0x80000000ull);
2513 return NO_EXIT;
2514 }
2515
2516 static ExitStatus op_negf64(DisasContext *s, DisasOps *o)
2517 {
2518 tcg_gen_xori_i64(o->out, o->in2, 0x8000000000000000ull);
2519 return NO_EXIT;
2520 }
2521
2522 static ExitStatus op_negf128(DisasContext *s, DisasOps *o)
2523 {
2524 tcg_gen_xori_i64(o->out, o->in1, 0x8000000000000000ull);
2525 tcg_gen_mov_i64(o->out2, o->in2);
2526 return NO_EXIT;
2527 }
2528
2529 static ExitStatus op_oc(DisasContext *s, DisasOps *o)
2530 {
2531 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2532 potential_page_fault(s);
2533 gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2);
2534 tcg_temp_free_i32(l);
2535 set_cc_static(s);
2536 return NO_EXIT;
2537 }
2538
2539 static ExitStatus op_or(DisasContext *s, DisasOps *o)
2540 {
2541 tcg_gen_or_i64(o->out, o->in1, o->in2);
2542 return NO_EXIT;
2543 }
2544
2545 static ExitStatus op_ori(DisasContext *s, DisasOps *o)
2546 {
2547 int shift = s->insn->data & 0xff;
2548 int size = s->insn->data >> 8;
2549 uint64_t mask = ((1ull << size) - 1) << shift;
2550
2551 assert(!o->g_in2);
2552 tcg_gen_shli_i64(o->in2, o->in2, shift);
2553 tcg_gen_or_i64(o->out, o->in1, o->in2);
2554
2555 /* Produce the CC from only the bits manipulated. */
2556 tcg_gen_andi_i64(cc_dst, o->out, mask);
2557 set_cc_nz_u64(s, cc_dst);
2558 return NO_EXIT;
2559 }
2560
2561 #ifndef CONFIG_USER_ONLY
2562 static ExitStatus op_ptlb(DisasContext *s, DisasOps *o)
2563 {
2564 check_privileged(s);
2565 gen_helper_ptlb(cpu_env);
2566 return NO_EXIT;
2567 }
2568 #endif
2569
2570 static ExitStatus op_risbg(DisasContext *s, DisasOps *o)
2571 {
2572 int i3 = get_field(s->fields, i3);
2573 int i4 = get_field(s->fields, i4);
2574 int i5 = get_field(s->fields, i5);
2575 int do_zero = i4 & 0x80;
2576 uint64_t mask, imask, pmask;
2577 int pos, len, rot;
2578
2579 /* Adjust the arguments for the specific insn. */
2580 switch (s->fields->op2) {
2581 case 0x55: /* risbg */
2582 i3 &= 63;
2583 i4 &= 63;
2584 pmask = ~0;
2585 break;
2586 case 0x5d: /* risbhg */
2587 i3 &= 31;
2588 i4 &= 31;
2589 pmask = 0xffffffff00000000ull;
2590 break;
2591 case 0x51: /* risblg */
2592 i3 &= 31;
2593 i4 &= 31;
2594 pmask = 0x00000000ffffffffull;
2595 break;
2596 default:
2597 abort();
2598 }
2599
2600 /* MASK is the set of bits to be inserted from R2.
2601 Take care for I3/I4 wraparound. */
2602 mask = pmask >> i3;
2603 if (i3 <= i4) {
2604 mask ^= pmask >> i4 >> 1;
2605 } else {
2606 mask |= ~(pmask >> i4 >> 1);
2607 }
2608 mask &= pmask;
2609
2610 /* IMASK is the set of bits to be kept from R1. In the case of the high/low
2611 insns, we need to keep the other half of the register. */
2612 imask = ~mask | ~pmask;
2613 if (do_zero) {
2614 if (s->fields->op2 == 0x55) {
2615 imask = 0;
2616 } else {
2617 imask = ~pmask;
2618 }
2619 }
2620
2621 /* In some cases we can implement this with deposit, which can be more
2622 efficient on some hosts. */
2623 if (~mask == imask && i3 <= i4) {
2624 if (s->fields->op2 == 0x5d) {
2625 i3 += 32, i4 += 32;
2626 }
2627 /* Note that we rotate the bits to be inserted to the lsb, not to
2628 the position as described in the PoO. */
2629 len = i4 - i3 + 1;
2630 pos = 63 - i4;
2631 rot = (i5 - pos) & 63;
2632 } else {
2633 pos = len = -1;
2634 rot = i5 & 63;
2635 }
2636
2637 /* Rotate the input as necessary. */
2638 tcg_gen_rotli_i64(o->in2, o->in2, rot);
2639
2640 /* Insert the selected bits into the output. */
2641 if (pos >= 0) {
2642 tcg_gen_deposit_i64(o->out, o->out, o->in2, pos, len);
2643 } else if (imask == 0) {
2644 tcg_gen_andi_i64(o->out, o->in2, mask);
2645 } else {
2646 tcg_gen_andi_i64(o->in2, o->in2, mask);
2647 tcg_gen_andi_i64(o->out, o->out, imask);
2648 tcg_gen_or_i64(o->out, o->out, o->in2);
2649 }
2650 return NO_EXIT;
2651 }
2652
2653 static ExitStatus op_rosbg(DisasContext *s, DisasOps *o)
2654 {
2655 int i3 = get_field(s->fields, i3);
2656 int i4 = get_field(s->fields, i4);
2657 int i5 = get_field(s->fields, i5);
2658 uint64_t mask;
2659
2660 /* If this is a test-only form, arrange to discard the result. */
2661 if (i3 & 0x80) {
2662 o->out = tcg_temp_new_i64();
2663 o->g_out = false;
2664 }
2665
2666 i3 &= 63;
2667 i4 &= 63;
2668 i5 &= 63;
2669
2670 /* MASK is the set of bits to be operated on from R2.
2671 Take care for I3/I4 wraparound. */
2672 mask = ~0ull >> i3;
2673 if (i3 <= i4) {
2674 mask ^= ~0ull >> i4 >> 1;
2675 } else {
2676 mask |= ~(~0ull >> i4 >> 1);
2677 }
2678
2679 /* Rotate the input as necessary. */
2680 tcg_gen_rotli_i64(o->in2, o->in2, i5);
2681
2682 /* Operate. */
2683 switch (s->fields->op2) {
2684 case 0x55: /* AND */
2685 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
2686 tcg_gen_and_i64(o->out, o->out, o->in2);
2687 break;
2688 case 0x56: /* OR */
2689 tcg_gen_andi_i64(o->in2, o->in2, mask);
2690 tcg_gen_or_i64(o->out, o->out, o->in2);
2691 break;
2692 case 0x57: /* XOR */
2693 tcg_gen_andi_i64(o->in2, o->in2, mask);
2694 tcg_gen_xor_i64(o->out, o->out, o->in2);
2695 break;
2696 default:
2697 abort();
2698 }
2699
2700 /* Set the CC. */
2701 tcg_gen_andi_i64(cc_dst, o->out, mask);
2702 set_cc_nz_u64(s, cc_dst);
2703 return NO_EXIT;
2704 }
2705
2706 static ExitStatus op_rev16(DisasContext *s, DisasOps *o)
2707 {
2708 tcg_gen_bswap16_i64(o->out, o->in2);
2709 return NO_EXIT;
2710 }
2711
2712 static ExitStatus op_rev32(DisasContext *s, DisasOps *o)
2713 {
2714 tcg_gen_bswap32_i64(o->out, o->in2);
2715 return NO_EXIT;
2716 }
2717
2718 static ExitStatus op_rev64(DisasContext *s, DisasOps *o)
2719 {
2720 tcg_gen_bswap64_i64(o->out, o->in2);
2721 return NO_EXIT;
2722 }
2723
2724 static ExitStatus op_rll32(DisasContext *s, DisasOps *o)
2725 {
2726 TCGv_i32 t1 = tcg_temp_new_i32();
2727 TCGv_i32 t2 = tcg_temp_new_i32();
2728 TCGv_i32 to = tcg_temp_new_i32();
2729 tcg_gen_trunc_i64_i32(t1, o->in1);
2730 tcg_gen_trunc_i64_i32(t2, o->in2);
2731 tcg_gen_rotl_i32(to, t1, t2);
2732 tcg_gen_extu_i32_i64(o->out, to);
2733 tcg_temp_free_i32(t1);
2734 tcg_temp_free_i32(t2);
2735 tcg_temp_free_i32(to);
2736 return NO_EXIT;
2737 }
2738
2739 static ExitStatus op_rll64(DisasContext *s, DisasOps *o)
2740 {
2741 tcg_gen_rotl_i64(o->out, o->in1, o->in2);
2742 return NO_EXIT;
2743 }
2744
2745 #ifndef CONFIG_USER_ONLY
2746 static ExitStatus op_rrbe(DisasContext *s, DisasOps *o)
2747 {
2748 check_privileged(s);
2749 gen_helper_rrbe(cc_op, cpu_env, o->in2);
2750 set_cc_static(s);
2751 return NO_EXIT;
2752 }
2753
2754 static ExitStatus op_sacf(DisasContext *s, DisasOps *o)
2755 {
2756 check_privileged(s);
2757 gen_helper_sacf(cpu_env, o->in2);
2758 /* Addressing mode has changed, so end the block. */
2759 return EXIT_PC_STALE;
2760 }
2761 #endif
2762
2763 static ExitStatus op_sar(DisasContext *s, DisasOps *o)
2764 {
2765 int r1 = get_field(s->fields, r1);
2766 tcg_gen_st32_i64(o->in2, cpu_env, offsetof(CPUS390XState, aregs[r1]));
2767 return NO_EXIT;
2768 }
2769
2770 static ExitStatus op_seb(DisasContext *s, DisasOps *o)
2771 {
2772 gen_helper_seb(o->out, cpu_env, o->in1, o->in2);
2773 return NO_EXIT;
2774 }
2775
2776 static ExitStatus op_sdb(DisasContext *s, DisasOps *o)
2777 {
2778 gen_helper_sdb(o->out, cpu_env, o->in1, o->in2);
2779 return NO_EXIT;
2780 }
2781
2782 static ExitStatus op_sxb(DisasContext *s, DisasOps *o)
2783 {
2784 gen_helper_sxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2785 return_low128(o->out2);
2786 return NO_EXIT;
2787 }
2788
2789 static ExitStatus op_sqeb(DisasContext *s, DisasOps *o)
2790 {
2791 gen_helper_sqeb(o->out, cpu_env, o->in2);
2792 return NO_EXIT;
2793 }
2794
2795 static ExitStatus op_sqdb(DisasContext *s, DisasOps *o)
2796 {
2797 gen_helper_sqdb(o->out, cpu_env, o->in2);
2798 return NO_EXIT;
2799 }
2800
2801 static ExitStatus op_sqxb(DisasContext *s, DisasOps *o)
2802 {
2803 gen_helper_sqxb(o->out, cpu_env, o->in1, o->in2);
2804 return_low128(o->out2);
2805 return NO_EXIT;
2806 }
2807
2808 #ifndef CONFIG_USER_ONLY
2809 static ExitStatus op_servc(DisasContext *s, DisasOps *o)
2810 {
2811 check_privileged(s);
2812 potential_page_fault(s);
2813 gen_helper_servc(cc_op, cpu_env, o->in2, o->in1);
2814 set_cc_static(s);
2815 return NO_EXIT;
2816 }
2817
2818 static ExitStatus op_sigp(DisasContext *s, DisasOps *o)
2819 {
2820 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2821 check_privileged(s);
2822 potential_page_fault(s);
2823 gen_helper_sigp(cc_op, cpu_env, o->in2, r1, o->in1);
2824 tcg_temp_free_i32(r1);
2825 return NO_EXIT;
2826 }
2827 #endif
2828
2829 static ExitStatus op_soc(DisasContext *s, DisasOps *o)
2830 {
2831 DisasCompare c;
2832 TCGv_i64 a;
2833 int lab, r1;
2834
2835 disas_jcc(s, &c, get_field(s->fields, m3));
2836
2837 lab = gen_new_label();
2838 if (c.is_64) {
2839 tcg_gen_brcond_i64(c.cond, c.u.s64.a, c.u.s64.b, lab);
2840 } else {
2841 tcg_gen_brcond_i32(c.cond, c.u.s32.a, c.u.s32.b, lab);
2842 }
2843 free_compare(&c);
2844
2845 r1 = get_field(s->fields, r1);
2846 a = get_address(s, 0, get_field(s->fields, b2), get_field(s->fields, d2));
2847 if (s->insn->data) {
2848 tcg_gen_qemu_st64(regs[r1], a, get_mem_index(s));
2849 } else {
2850 tcg_gen_qemu_st32(regs[r1], a, get_mem_index(s));
2851 }
2852 tcg_temp_free_i64(a);
2853
2854 gen_set_label(lab);
2855 return NO_EXIT;
2856 }
2857
2858 static ExitStatus op_sla(DisasContext *s, DisasOps *o)
2859 {
2860 uint64_t sign = 1ull << s->insn->data;
2861 enum cc_op cco = s->insn->data == 31 ? CC_OP_SLA_32 : CC_OP_SLA_64;
2862 gen_op_update2_cc_i64(s, cco, o->in1, o->in2);
2863 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2864 /* The arithmetic left shift is curious in that it does not affect
2865 the sign bit. Copy that over from the source unchanged. */
2866 tcg_gen_andi_i64(o->out, o->out, ~sign);
2867 tcg_gen_andi_i64(o->in1, o->in1, sign);
2868 tcg_gen_or_i64(o->out, o->out, o->in1);
2869 return NO_EXIT;
2870 }
2871
2872 static ExitStatus op_sll(DisasContext *s, DisasOps *o)
2873 {
2874 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2875 return NO_EXIT;
2876 }
2877
2878 static ExitStatus op_sra(DisasContext *s, DisasOps *o)
2879 {
2880 tcg_gen_sar_i64(o->out, o->in1, o->in2);
2881 return NO_EXIT;
2882 }
2883
2884 static ExitStatus op_srl(DisasContext *s, DisasOps *o)
2885 {
2886 tcg_gen_shr_i64(o->out, o->in1, o->in2);
2887 return NO_EXIT;
2888 }
2889
2890 static ExitStatus op_sfpc(DisasContext *s, DisasOps *o)
2891 {
2892 gen_helper_sfpc(cpu_env, o->in2);
2893 return NO_EXIT;
2894 }
2895
2896 #ifndef CONFIG_USER_ONLY
2897 static ExitStatus op_spka(DisasContext *s, DisasOps *o)
2898 {
2899 check_privileged(s);
2900 tcg_gen_shri_i64(o->in2, o->in2, 4);
2901 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY - 4, 4);
2902 return NO_EXIT;
2903 }
2904
2905 static ExitStatus op_sske(DisasContext *s, DisasOps *o)
2906 {
2907 check_privileged(s);
2908 gen_helper_sske(cpu_env, o->in1, o->in2);
2909 return NO_EXIT;
2910 }
2911
2912 static ExitStatus op_ssm(DisasContext *s, DisasOps *o)
2913 {
2914 check_privileged(s);
2915 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8);
2916 return NO_EXIT;
2917 }
2918
2919 static ExitStatus op_stap(DisasContext *s, DisasOps *o)
2920 {
2921 check_privileged(s);
2922 /* ??? Surely cpu address != cpu number. In any case the previous
2923 version of this stored more than the required half-word, so it
2924 is unlikely this has ever been tested. */
2925 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num));
2926 return NO_EXIT;
2927 }
2928
2929 static ExitStatus op_stck(DisasContext *s, DisasOps *o)
2930 {
2931 gen_helper_stck(o->out, cpu_env);
2932 /* ??? We don't implement clock states. */
2933 gen_op_movi_cc(s, 0);
2934 return NO_EXIT;
2935 }
2936
2937 static ExitStatus op_stcke(DisasContext *s, DisasOps *o)
2938 {
2939 TCGv_i64 c1 = tcg_temp_new_i64();
2940 TCGv_i64 c2 = tcg_temp_new_i64();
2941 gen_helper_stck(c1, cpu_env);
2942 /* Shift the 64-bit value into its place as a zero-extended
2943 104-bit value. Note that "bit positions 64-103 are always
2944 non-zero so that they compare differently to STCK"; we set
2945 the least significant bit to 1. */
2946 tcg_gen_shli_i64(c2, c1, 56);
2947 tcg_gen_shri_i64(c1, c1, 8);
2948 tcg_gen_ori_i64(c2, c2, 0x10000);
2949 tcg_gen_qemu_st64(c1, o->in2, get_mem_index(s));
2950 tcg_gen_addi_i64(o->in2, o->in2, 8);
2951 tcg_gen_qemu_st64(c2, o->in2, get_mem_index(s));
2952 tcg_temp_free_i64(c1);
2953 tcg_temp_free_i64(c2);
2954 /* ??? We don't implement clock states. */
2955 gen_op_movi_cc(s, 0);
2956 return NO_EXIT;
2957 }
2958
2959 static ExitStatus op_sckc(DisasContext *s, DisasOps *o)
2960 {
2961 check_privileged(s);
2962 gen_helper_sckc(cpu_env, o->in2);
2963 return NO_EXIT;
2964 }
2965
2966 static ExitStatus op_stckc(DisasContext *s, DisasOps *o)
2967 {
2968 check_privileged(s);
2969 gen_helper_stckc(o->out, cpu_env);
2970 return NO_EXIT;
2971 }
2972
2973 static ExitStatus op_stctg(DisasContext *s, DisasOps *o)
2974 {
2975 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2976 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2977 check_privileged(s);
2978 potential_page_fault(s);
2979 gen_helper_stctg(cpu_env, r1, o->in2, r3);
2980 tcg_temp_free_i32(r1);
2981 tcg_temp_free_i32(r3);
2982 return NO_EXIT;
2983 }
2984
2985 static ExitStatus op_stctl(DisasContext *s, DisasOps *o)
2986 {
2987 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2988 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2989 check_privileged(s);
2990 potential_page_fault(s);
2991 gen_helper_stctl(cpu_env, r1, o->in2, r3);
2992 tcg_temp_free_i32(r1);
2993 tcg_temp_free_i32(r3);
2994 return NO_EXIT;
2995 }
2996
2997 static ExitStatus op_stidp(DisasContext *s, DisasOps *o)
2998 {
2999 check_privileged(s);
3000 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num));
3001 return NO_EXIT;
3002 }
3003
3004 static ExitStatus op_spt(DisasContext *s, DisasOps *o)
3005 {
3006 check_privileged(s);
3007 gen_helper_spt(cpu_env, o->in2);
3008 return NO_EXIT;
3009 }
3010
3011 static ExitStatus op_stfl(DisasContext *s, DisasOps *o)
3012 {
3013 TCGv_i64 f, a;
3014 /* We really ought to have more complete indication of facilities
3015 that we implement. Address this when STFLE is implemented. */
3016 check_privileged(s);
3017 f = tcg_const_i64(0xc0000000);
3018 a = tcg_const_i64(200);
3019 tcg_gen_qemu_st32(f, a, get_mem_index(s));
3020 tcg_temp_free_i64(f);
3021 tcg_temp_free_i64(a);
3022 return NO_EXIT;
3023 }
3024
3025 static ExitStatus op_stpt(DisasContext *s, DisasOps *o)
3026 {
3027 check_privileged(s);
3028 gen_helper_stpt(o->out, cpu_env);
3029 return NO_EXIT;
3030 }
3031
3032 static ExitStatus op_stsi(DisasContext *s, DisasOps *o)
3033 {
3034 check_privileged(s);
3035 potential_page_fault(s);
3036 gen_helper_stsi(cc_op, cpu_env, o->in2, regs[0], regs[1]);
3037 set_cc_static(s);
3038 return NO_EXIT;
3039 }
3040
3041 static ExitStatus op_spx(DisasContext *s, DisasOps *o)
3042 {
3043 check_privileged(s);
3044 gen_helper_spx(cpu_env, o->in2);
3045 return NO_EXIT;
3046 }
3047
3048 static ExitStatus op_subchannel(DisasContext *s, DisasOps *o)
3049 {
3050 check_privileged(s);
3051 /* Not operational. */
3052 gen_op_movi_cc(s, 3);
3053 return NO_EXIT;
3054 }
3055
3056 static ExitStatus op_stpx(DisasContext *s, DisasOps *o)
3057 {
3058 check_privileged(s);
3059 tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, psa));
3060 tcg_gen_andi_i64(o->out, o->out, 0x7fffe000);
3061 return NO_EXIT;
3062 }
3063
3064 static ExitStatus op_stnosm(DisasContext *s, DisasOps *o)
3065 {
3066 uint64_t i2 = get_field(s->fields, i2);
3067 TCGv_i64 t;
3068
3069 check_privileged(s);
3070
3071 /* It is important to do what the instruction name says: STORE THEN.
3072 If we let the output hook perform the store then if we fault and
3073 restart, we'll have the wrong SYSTEM MASK in place. */
3074 t = tcg_temp_new_i64();
3075 tcg_gen_shri_i64(t, psw_mask, 56);
3076 tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
3077 tcg_temp_free_i64(t);
3078
3079 if (s->fields->op == 0xac) {
3080 tcg_gen_andi_i64(psw_mask, psw_mask,
3081 (i2 << 56) | 0x00ffffffffffffffull);
3082 } else {
3083 tcg_gen_ori_i64(psw_mask, psw_mask, i2 << 56);
3084 }
3085 return NO_EXIT;
3086 }
3087
3088 static ExitStatus op_stura(DisasContext *s, DisasOps *o)
3089 {
3090 check_privileged(s);
3091 potential_page_fault(s);
3092 gen_helper_stura(cpu_env, o->in2, o->in1);
3093 return NO_EXIT;
3094 }
3095 #endif
3096
3097 static ExitStatus op_st8(DisasContext *s, DisasOps *o)
3098 {
3099 tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
3100 return NO_EXIT;
3101 }
3102
3103 static ExitStatus op_st16(DisasContext *s, DisasOps *o)
3104 {
3105 tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
3106 return NO_EXIT;
3107 }
3108
3109 static ExitStatus op_st32(DisasContext *s, DisasOps *o)
3110 {
3111 tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s));
3112 return NO_EXIT;
3113 }
3114
3115 static ExitStatus op_st64(DisasContext *s, DisasOps *o)
3116 {
3117 tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
3118 return NO_EXIT;
3119 }
3120
3121 static ExitStatus op_stam(DisasContext *s, DisasOps *o)
3122 {
3123 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3124 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
3125 potential_page_fault(s);
3126 gen_helper_stam(cpu_env, r1, o->in2, r3);
3127 tcg_temp_free_i32(r1);
3128 tcg_temp_free_i32(r3);
3129 return NO_EXIT;
3130 }
3131
3132 static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
3133 {
3134 int m3 = get_field(s->fields, m3);
3135 int pos, base = s->insn->data;
3136 TCGv_i64 tmp = tcg_temp_new_i64();
3137
3138 pos = base + ctz32(m3) * 8;
3139 switch (m3) {
3140 case 0xf:
3141 /* Effectively a 32-bit store. */
3142 tcg_gen_shri_i64(tmp, o->in1, pos);
3143 tcg_gen_qemu_st32(tmp, o->in2, get_mem_index(s));
3144 break;
3145
3146 case 0xc:
3147 case 0x6:
3148 case 0x3:
3149 /* Effectively a 16-bit store. */
3150 tcg_gen_shri_i64(tmp, o->in1, pos);
3151 tcg_gen_qemu_st16(tmp, o->in2, get_mem_index(s));
3152 break;
3153
3154 case 0x8:
3155 case 0x4:
3156 case 0x2:
3157 case 0x1:
3158 /* Effectively an 8-bit store. */
3159 tcg_gen_shri_i64(tmp, o->in1, pos);
3160 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3161 break;
3162
3163 default:
3164 /* This is going to be a sequence of shifts and stores. */
3165 pos = base + 32 - 8;
3166 while (m3) {
3167 if (m3 & 0x8) {
3168 tcg_gen_shri_i64(tmp, o->in1, pos);
3169 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3170 tcg_gen_addi_i64(o->in2, o->in2, 1);
3171 }
3172 m3 = (m3 << 1) & 0xf;
3173 pos -= 8;
3174 }
3175 break;
3176 }
3177 tcg_temp_free_i64(tmp);
3178 return NO_EXIT;
3179 }
3180
3181 static ExitStatus op_stm(DisasContext *s, DisasOps *o)
3182 {
3183 int r1 = get_field(s->fields, r1);
3184 int r3 = get_field(s->fields, r3);
3185 int size = s->insn->data;
3186 TCGv_i64 tsize = tcg_const_i64(size);
3187
3188 while (1) {
3189 if (size == 8) {
3190 tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
3191 } else {
3192 tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s));
3193 }
3194 if (r1 == r3) {
3195 break;
3196 }
3197 tcg_gen_add_i64(o->in2, o->in2, tsize);
3198 r1 = (r1 + 1) & 15;
3199 }
3200
3201 tcg_temp_free_i64(tsize);
3202 return NO_EXIT;
3203 }
3204
3205 static ExitStatus op_stmh(DisasContext *s, DisasOps *o)
3206 {
3207 int r1 = get_field(s->fields, r1);
3208 int r3 = get_field(s->fields, r3);
3209 TCGv_i64 t = tcg_temp_new_i64();
3210 TCGv_i64 t4 = tcg_const_i64(4);
3211 TCGv_i64 t32 = tcg_const_i64(32);
3212
3213 while (1) {
3214 tcg_gen_shl_i64(t, regs[r1], t32);
3215 tcg_gen_qemu_st32(t, o->in2, get_mem_index(s));
3216 if (r1 == r3) {
3217 break;
3218 }
3219 tcg_gen_add_i64(o->in2, o->in2, t4);
3220 r1 = (r1 + 1) & 15;
3221 }
3222
3223 tcg_temp_free_i64(t);
3224 tcg_temp_free_i64(t4);
3225 tcg_temp_free_i64(t32);
3226 return NO_EXIT;
3227 }
3228
3229 static ExitStatus op_srst(DisasContext *s, DisasOps *o)
3230 {
3231 potential_page_fault(s);
3232 gen_helper_srst(o->in1, cpu_env, regs[0], o->in1, o->in2);
3233 set_cc_static(s);
3234 return_low128(o->in2);
3235 return NO_EXIT;
3236 }
3237
3238 static ExitStatus op_sub(DisasContext *s, DisasOps *o)
3239 {
3240 tcg_gen_sub_i64(o->out, o->in1, o->in2);
3241 return NO_EXIT;
3242 }
3243
3244 static ExitStatus op_subb(DisasContext *s, DisasOps *o)
3245 {
3246 TCGv_i64 cc;
3247
3248 assert(!o->g_in2);
3249 tcg_gen_not_i64(o->in2, o->in2);
3250 tcg_gen_add_i64(o->out, o->in1, o->in2);
3251
3252 /* XXX possible optimization point */
3253 gen_op_calc_cc(s);
3254 cc = tcg_temp_new_i64();
3255 tcg_gen_extu_i32_i64(cc, cc_op);
3256 tcg_gen_shri_i64(cc, cc, 1);
3257 tcg_gen_add_i64(o->out, o->out, cc);
3258 tcg_temp_free_i64(cc);
3259 return NO_EXIT;
3260 }
3261
3262 static ExitStatus op_svc(DisasContext *s, DisasOps *o)
3263 {
3264 TCGv_i32 t;
3265
3266 update_psw_addr(s);
3267 update_cc_op(s);
3268
3269 t = tcg_const_i32(get_field(s->fields, i1) & 0xff);
3270 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code));
3271 tcg_temp_free_i32(t);
3272
3273 t = tcg_const_i32(s->next_pc - s->pc);
3274 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen));
3275 tcg_temp_free_i32(t);
3276
3277 gen_exception(EXCP_SVC);
3278 return EXIT_NORETURN;
3279 }
3280
3281 static ExitStatus op_tceb(DisasContext *s, DisasOps *o)
3282 {
3283 gen_helper_tceb(cc_op, o->in1, o->in2);
3284 set_cc_static(s);
3285 return NO_EXIT;
3286 }
3287
3288 static ExitStatus op_tcdb(DisasContext *s, DisasOps *o)
3289 {
3290 gen_helper_tcdb(cc_op, o->in1, o->in2);
3291 set_cc_static(s);
3292 return NO_EXIT;
3293 }
3294
3295 static ExitStatus op_tcxb(DisasContext *s, DisasOps *o)
3296 {
3297 gen_helper_tcxb(cc_op, o->out, o->out2, o->in2);
3298 set_cc_static(s);
3299 return NO_EXIT;
3300 }
3301
3302 #ifndef CONFIG_USER_ONLY
3303 static ExitStatus op_tprot(DisasContext *s, DisasOps *o)
3304 {
3305 potential_page_fault(s);
3306 gen_helper_tprot(cc_op, o->addr1, o->in2);
3307 set_cc_static(s);
3308 return NO_EXIT;
3309 }
3310 #endif
3311
3312 static ExitStatus op_tr(DisasContext *s, DisasOps *o)
3313 {
3314 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3315 potential_page_fault(s);
3316 gen_helper_tr(cpu_env, l, o->addr1, o->in2);
3317 tcg_temp_free_i32(l);
3318 set_cc_static(s);
3319 return NO_EXIT;
3320 }
3321
3322 static ExitStatus op_unpk(DisasContext *s, DisasOps *o)
3323 {
3324 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3325 potential_page_fault(s);
3326 gen_helper_unpk(cpu_env, l, o->addr1, o->in2);
3327 tcg_temp_free_i32(l);
3328 return NO_EXIT;
3329 }
3330
3331 static ExitStatus op_xc(DisasContext *s, DisasOps *o)
3332 {
3333 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3334 potential_page_fault(s);
3335 gen_helper_xc(cc_op, cpu_env, l, o->addr1, o->in2);
3336 tcg_temp_free_i32(l);
3337 set_cc_static(s);
3338 return NO_EXIT;
3339 }
3340
3341 static ExitStatus op_xor(DisasContext *s, DisasOps *o)
3342 {
3343 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3344 return NO_EXIT;
3345 }
3346
3347 static ExitStatus op_xori(DisasContext *s, DisasOps *o)
3348 {
3349 int shift = s->insn->data & 0xff;
3350 int size = s->insn->data >> 8;
3351 uint64_t mask = ((1ull << size) - 1) << shift;
3352
3353 assert(!o->g_in2);
3354 tcg_gen_shli_i64(o->in2, o->in2, shift);
3355 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3356
3357 /* Produce the CC from only the bits manipulated. */
3358 tcg_gen_andi_i64(cc_dst, o->out, mask);
3359 set_cc_nz_u64(s, cc_dst);
3360 return NO_EXIT;
3361 }
3362
3363 static ExitStatus op_zero(DisasContext *s, DisasOps *o)
3364 {
3365 o->out = tcg_const_i64(0);
3366 return NO_EXIT;
3367 }
3368
3369 static ExitStatus op_zero2(DisasContext *s, DisasOps *o)
3370 {
3371 o->out = tcg_const_i64(0);
3372 o->out2 = o->out;
3373 o->g_out2 = true;
3374 return NO_EXIT;
3375 }
3376
3377 /* ====================================================================== */
3378 /* The "Cc OUTput" generators. Given the generated output (and in some cases
3379 the original inputs), update the various cc data structures in order to
3380 be able to compute the new condition code. */
3381
3382 static void cout_abs32(DisasContext *s, DisasOps *o)
3383 {
3384 gen_op_update1_cc_i64(s, CC_OP_ABS_32, o->out);
3385 }
3386
3387 static void cout_abs64(DisasContext *s, DisasOps *o)
3388 {
3389 gen_op_update1_cc_i64(s, CC_OP_ABS_64, o->out);
3390 }
3391
3392 static void cout_adds32(DisasContext *s, DisasOps *o)
3393 {
3394 gen_op_update3_cc_i64(s, CC_OP_ADD_32, o->in1, o->in2, o->out);
3395 }
3396
3397 static void cout_adds64(DisasContext *s, DisasOps *o)
3398 {
3399 gen_op_update3_cc_i64(s, CC_OP_ADD_64, o->in1, o->in2, o->out);
3400 }
3401
3402 static void cout_addu32(DisasContext *s, DisasOps *o)
3403 {
3404 gen_op_update3_cc_i64(s, CC_OP_ADDU_32, o->in1, o->in2, o->out);
3405 }
3406
3407 static void cout_addu64(DisasContext *s, DisasOps *o)
3408 {
3409 gen_op_update3_cc_i64(s, CC_OP_ADDU_64, o->in1, o->in2, o->out);
3410 }
3411
3412 static void cout_addc32(DisasContext *s, DisasOps *o)
3413 {
3414 gen_op_update3_cc_i64(s, CC_OP_ADDC_32, o->in1, o->in2, o->out);
3415 }
3416
3417 static void cout_addc64(DisasContext *s, DisasOps *o)
3418 {
3419 gen_op_update3_cc_i64(s, CC_OP_ADDC_64, o->in1, o->in2, o->out);
3420 }
3421
3422 static void cout_cmps32(DisasContext *s, DisasOps *o)
3423 {
3424 gen_op_update2_cc_i64(s, CC_OP_LTGT_32, o->in1, o->in2);
3425 }
3426
3427 static void cout_cmps64(DisasContext *s, DisasOps *o)
3428 {
3429 gen_op_update2_cc_i64(s, CC_OP_LTGT_64, o->in1, o->in2);
3430 }
3431
3432 static void cout_cmpu32(DisasContext *s, DisasOps *o)
3433 {
3434 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_32, o->in1, o->in2);
3435 }
3436
3437 static void cout_cmpu64(DisasContext *s, DisasOps *o)
3438 {
3439 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, o->in1, o->in2);
3440 }
3441
3442 static void cout_f32(DisasContext *s, DisasOps *o)
3443 {
3444 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, o->out);
3445 }
3446
3447 static void cout_f64(DisasContext *s, DisasOps *o)
3448 {
3449 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, o->out);
3450 }
3451
3452 static void cout_f128(DisasContext *s, DisasOps *o)
3453 {
3454 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, o->out, o->out2);
3455 }
3456
3457 static void cout_nabs32(DisasContext *s, DisasOps *o)
3458 {
3459 gen_op_update1_cc_i64(s, CC_OP_NABS_32, o->out);
3460 }
3461
3462 static void cout_nabs64(DisasContext *s, DisasOps *o)
3463 {
3464 gen_op_update1_cc_i64(s, CC_OP_NABS_64, o->out);
3465 }
3466
3467 static void cout_neg32(DisasContext *s, DisasOps *o)
3468 {
3469 gen_op_update1_cc_i64(s, CC_OP_COMP_32, o->out);
3470 }
3471
3472 static void cout_neg64(DisasContext *s, DisasOps *o)
3473 {
3474 gen_op_update1_cc_i64(s, CC_OP_COMP_64, o->out);
3475 }
3476
3477 static void cout_nz32(DisasContext *s, DisasOps *o)
3478 {
3479 tcg_gen_ext32u_i64(cc_dst, o->out);
3480 gen_op_update1_cc_i64(s, CC_OP_NZ, cc_dst);
3481 }
3482
3483 static void cout_nz64(DisasContext *s, DisasOps *o)
3484 {
3485 gen_op_update1_cc_i64(s, CC_OP_NZ, o->out);
3486 }
3487
3488 static void cout_s32(DisasContext *s, DisasOps *o)
3489 {
3490 gen_op_update1_cc_i64(s, CC_OP_LTGT0_32, o->out);
3491 }
3492
3493 static void cout_s64(DisasContext *s, DisasOps *o)
3494 {
3495 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, o->out);
3496 }
3497
3498 static void cout_subs32(DisasContext *s, DisasOps *o)
3499 {
3500 gen_op_update3_cc_i64(s, CC_OP_SUB_32, o->in1, o->in2, o->out);
3501 }
3502
3503 static void cout_subs64(DisasContext *s, DisasOps *o)
3504 {
3505 gen_op_update3_cc_i64(s, CC_OP_SUB_64, o->in1, o->in2, o->out);
3506 }
3507
3508 static void cout_subu32(DisasContext *s, DisasOps *o)
3509 {
3510 gen_op_update3_cc_i64(s, CC_OP_SUBU_32, o->in1, o->in2, o->out);
3511 }
3512
3513 static void cout_subu64(DisasContext *s, DisasOps *o)
3514 {
3515 gen_op_update3_cc_i64(s, CC_OP_SUBU_64, o->in1, o->in2, o->out);
3516 }
3517
3518 static void cout_subb32(DisasContext *s, DisasOps *o)
3519 {
3520 gen_op_update3_cc_i64(s, CC_OP_SUBB_32, o->in1, o->in2, o->out);
3521 }
3522
3523 static void cout_subb64(DisasContext *s, DisasOps *o)
3524 {
3525 gen_op_update3_cc_i64(s, CC_OP_SUBB_64, o->in1, o->in2, o->out);
3526 }
3527
3528 static void cout_tm32(DisasContext *s, DisasOps *o)
3529 {
3530 gen_op_update2_cc_i64(s, CC_OP_TM_32, o->in1, o->in2);
3531 }
3532
3533 static void cout_tm64(DisasContext *s, DisasOps *o)
3534 {
3535 gen_op_update2_cc_i64(s, CC_OP_TM_64, o->in1, o->in2);
3536 }
3537
3538 /* ====================================================================== */
3539 /* The "PREPeration" generators. These initialize the DisasOps.OUT fields
3540 with the TCG register to which we will write. Used in combination with
3541 the "wout" generators, in some cases we need a new temporary, and in
3542 some cases we can write to a TCG global. */
3543
3544 static void prep_new(DisasContext *s, DisasFields *f, DisasOps *o)
3545 {
3546 o->out = tcg_temp_new_i64();
3547 }
3548
3549 static void prep_new_P(DisasContext *s, DisasFields *f, DisasOps *o)
3550 {
3551 o->out = tcg_temp_new_i64();
3552 o->out2 = tcg_temp_new_i64();
3553 }
3554
3555 static void prep_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3556 {
3557 o->out = regs[get_field(f, r1)];
3558 o->g_out = true;
3559 }
3560
3561 static void prep_r1_P(DisasContext *s, DisasFields *f, DisasOps *o)
3562 {
3563 /* ??? Specification exception: r1 must be even. */
3564 int r1 = get_field(f, r1);
3565 o->out = regs[r1];
3566 o->out2 = regs[(r1 + 1) & 15];
3567 o->g_out = o->g_out2 = true;
3568 }
3569
3570 static void prep_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3571 {
3572 o->out = fregs[get_field(f, r1)];
3573 o->g_out = true;
3574 }
3575
3576 static void prep_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3577 {
3578 /* ??? Specification exception: r1 must be < 14. */
3579 int r1 = get_field(f, r1);
3580 o->out = fregs[r1];
3581 o->out2 = fregs[(r1 + 2) & 15];
3582 o->g_out = o->g_out2 = true;
3583 }
3584
3585 /* ====================================================================== */
3586 /* The "Write OUTput" generators. These generally perform some non-trivial
3587 copy of data to TCG globals, or to main memory. The trivial cases are
3588 generally handled by having a "prep" generator install the TCG global
3589 as the destination of the operation. */
3590
3591 static void wout_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3592 {
3593 store_reg(get_field(f, r1), o->out);
3594 }
3595
3596 static void wout_r1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3597 {
3598 int r1 = get_field(f, r1);
3599 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8);
3600 }
3601
3602 static void wout_r1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3603 {
3604 int r1 = get_field(f, r1);
3605 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 16);
3606 }
3607
3608 static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3609 {
3610 store_reg32_i64(get_field(f, r1), o->out);
3611 }
3612
3613 static void wout_r1_P32(DisasContext *s, DisasFields *f, DisasOps *o)
3614 {
3615 /* ??? Specification exception: r1 must be even. */
3616 int r1 = get_field(f, r1);
3617 store_reg32_i64(r1, o->out);
3618 store_reg32_i64((r1 + 1) & 15, o->out2);
3619 }
3620
3621 static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3622 {
3623 /* ??? Specification exception: r1 must be even. */
3624 int r1 = get_field(f, r1);
3625 store_reg32_i64((r1 + 1) & 15, o->out);
3626 tcg_gen_shri_i64(o->out, o->out, 32);
3627 store_reg32_i64(r1, o->out);
3628 }
3629
3630 static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3631 {
3632 store_freg32_i64(get_field(f, r1), o->out);
3633 }
3634
3635 static void wout_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3636 {
3637 store_freg(get_field(f, r1), o->out);
3638 }
3639
3640 static void wout_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3641 {
3642 /* ??? Specification exception: r1 must be < 14. */
3643 int f1 = get_field(s->fields, r1);
3644 store_freg(f1, o->out);
3645 store_freg((f1 + 2) & 15, o->out2);
3646 }
3647
3648 static void wout_cond_r1r2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3649 {
3650 if (get_field(f, r1) != get_field(f, r2)) {
3651 store_reg32_i64(get_field(f, r1), o->out);
3652 }
3653 }
3654
3655 static void wout_cond_e1e2(DisasContext *s, DisasFields *f, DisasOps *o)
3656 {
3657 if (get_field(f, r1) != get_field(f, r2)) {
3658 store_freg32_i64(get_field(f, r1), o->out);
3659 }
3660 }
3661
3662 static void wout_m1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3663 {
3664 tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s));
3665 }
3666
3667 static void wout_m1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3668 {
3669 tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s));
3670 }
3671
3672 static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3673 {
3674 tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
3675 }
3676
3677 static void wout_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3678 {
3679 tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
3680 }
3681
3682 static void wout_m2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3683 {
3684 tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s));
3685 }
3686
3687 /* ====================================================================== */
3688 /* The "INput 1" generators. These load the first operand to an insn. */
3689
3690 static void in1_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3691 {
3692 o->in1 = load_reg(get_field(f, r1));
3693 }
3694
3695 static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3696 {
3697 o->in1 = regs[get_field(f, r1)];
3698 o->g_in1 = true;
3699 }
3700
3701 static void in1_r1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3702 {
3703 o->in1 = tcg_temp_new_i64();
3704 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r1)]);
3705 }
3706
3707 static void in1_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3708 {
3709 o->in1 = tcg_temp_new_i64();
3710 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r1)]);
3711 }
3712
3713 static void in1_r1_sr32(DisasContext *s, DisasFields *f, DisasOps *o)
3714 {
3715 o->in1 = tcg_temp_new_i64();
3716 tcg_gen_shri_i64(o->in1, regs[get_field(f, r1)], 32);
3717 }
3718
3719 static void in1_r1p1(DisasContext *s, DisasFields *f, DisasOps *o)
3720 {
3721 /* ??? Specification exception: r1 must be even. */
3722 int r1 = get_field(f, r1);
3723 o->in1 = load_reg((r1 + 1) & 15);
3724 }
3725
3726 static void in1_r1p1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3727 {
3728 /* ??? Specification exception: r1 must be even. */
3729 int r1 = get_field(f, r1);
3730 o->in1 = tcg_temp_new_i64();
3731 tcg_gen_ext32s_i64(o->in1, regs[(r1 + 1) & 15]);
3732 }
3733
3734 static void in1_r1p1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3735 {
3736 /* ??? Specification exception: r1 must be even. */
3737 int r1 = get_field(f, r1);
3738 o->in1 = tcg_temp_new_i64();
3739 tcg_gen_ext32u_i64(o->in1, regs[(r1 + 1) & 15]);
3740 }
3741
3742 static void in1_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3743 {
3744 /* ??? Specification exception: r1 must be even. */
3745 int r1 = get_field(f, r1);
3746 o->in1 = tcg_temp_new_i64();
3747 tcg_gen_concat32_i64(o->in1, regs[r1 + 1], regs[r1]);
3748 }
3749
3750 static void in1_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3751 {
3752 o->in1 = load_reg(get_field(f, r2));
3753 }
3754
3755 static void in1_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3756 {
3757 o->in1 = load_reg(get_field(f, r3));
3758 }
3759
3760 static void in1_r3_o(DisasContext *s, DisasFields *f, DisasOps *o)
3761 {
3762 o->in1 = regs[get_field(f, r3)];
3763 o->g_in1 = true;
3764 }
3765
3766 static void in1_r3_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3767 {
3768 o->in1 = tcg_temp_new_i64();
3769 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r3)]);
3770 }
3771
3772 static void in1_r3_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3773 {
3774 o->in1 = tcg_temp_new_i64();
3775 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r3)]);
3776 }
3777
3778 static void in1_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3779 {
3780 o->in1 = load_freg32_i64(get_field(f, r1));
3781 }
3782
3783 static void in1_f1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3784 {
3785 o->in1 = fregs[get_field(f, r1)];
3786 o->g_in1 = true;
3787 }
3788
3789 static void in1_x1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3790 {
3791 /* ??? Specification exception: r1 must be < 14. */
3792 int r1 = get_field(f, r1);
3793 o->out = fregs[r1];
3794 o->out2 = fregs[(r1 + 2) & 15];
3795 o->g_out = o->g_out2 = true;
3796 }
3797
3798 static void in1_la1(DisasContext *s, DisasFields *f, DisasOps *o)
3799 {
3800 o->addr1 = get_address(s, 0, get_field(f, b1), get_field(f, d1));
3801 }
3802
3803 static void in1_la2(DisasContext *s, DisasFields *f, DisasOps *o)
3804 {
3805 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3806 o->addr1 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3807 }
3808
3809 static void in1_m1_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3810 {
3811 in1_la1(s, f, o);
3812 o->in1 = tcg_temp_new_i64();
3813 tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s));
3814 }
3815
3816 static void in1_m1_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3817 {
3818 in1_la1(s, f, o);
3819 o->in1 = tcg_temp_new_i64();
3820 tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s));
3821 }
3822
3823 static void in1_m1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3824 {
3825 in1_la1(s, f, o);
3826 o->in1 = tcg_temp_new_i64();
3827 tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s));
3828 }
3829
3830 static void in1_m1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3831 {
3832 in1_la1(s, f, o);
3833 o->in1 = tcg_temp_new_i64();
3834 tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s));
3835 }
3836
3837 static void in1_m1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3838 {
3839 in1_la1(s, f, o);
3840 o->in1 = tcg_temp_new_i64();
3841 tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s));
3842 }
3843
3844 static void in1_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3845 {
3846 in1_la1(s, f, o);
3847 o->in1 = tcg_temp_new_i64();
3848 tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s));
3849 }
3850
3851 /* ====================================================================== */
3852 /* The "INput 2" generators. These load the second operand to an insn. */
3853
3854 static void in2_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3855 {
3856 o->in2 = regs[get_field(f, r1)];
3857 o->g_in2 = true;
3858 }
3859
3860 static void in2_r1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3861 {
3862 o->in2 = tcg_temp_new_i64();
3863 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r1)]);
3864 }
3865
3866 static void in2_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3867 {
3868 o->in2 = tcg_temp_new_i64();
3869 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r1)]);
3870 }
3871
3872 static void in2_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3873 {
3874 o->in2 = load_reg(get_field(f, r2));
3875 }
3876
3877 static void in2_r2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3878 {
3879 o->in2 = regs[get_field(f, r2)];
3880 o->g_in2 = true;
3881 }
3882
3883 static void in2_r2_nz(DisasContext *s, DisasFields *f, DisasOps *o)
3884 {
3885 int r2 = get_field(f, r2);
3886 if (r2 != 0) {
3887 o->in2 = load_reg(r2);
3888 }
3889 }
3890
3891 static void in2_r2_8s(DisasContext *s, DisasFields *f, DisasOps *o)
3892 {
3893 o->in2 = tcg_temp_new_i64();
3894 tcg_gen_ext8s_i64(o->in2, regs[get_field(f, r2)]);
3895 }
3896
3897 static void in2_r2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3898 {
3899 o->in2 = tcg_temp_new_i64();
3900 tcg_gen_ext8u_i64(o->in2, regs[get_field(f, r2)]);
3901 }
3902
3903 static void in2_r2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3904 {
3905 o->in2 = tcg_temp_new_i64();
3906 tcg_gen_ext16s_i64(o->in2, regs[get_field(f, r2)]);
3907 }
3908
3909 static void in2_r2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3910 {
3911 o->in2 = tcg_temp_new_i64();
3912 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r2)]);
3913 }
3914
3915 static void in2_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3916 {
3917 o->in2 = load_reg(get_field(f, r3));
3918 }
3919
3920 static void in2_r2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3921 {
3922 o->in2 = tcg_temp_new_i64();
3923 tcg_gen_ext32s_i64(o->in2, regs[get_field(f, r2)]);
3924 }
3925
3926 static void in2_r2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3927 {
3928 o->in2 = tcg_temp_new_i64();
3929 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r2)]);
3930 }
3931
3932 static void in2_e2(DisasContext *s, DisasFields *f, DisasOps *o)
3933 {
3934 o->in2 = load_freg32_i64(get_field(f, r2));
3935 }
3936
3937 static void in2_f2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3938 {
3939 o->in2 = fregs[get_field(f, r2)];
3940 o->g_in2 = true;
3941 }
3942
3943 static void in2_x2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3944 {
3945 /* ??? Specification exception: r1 must be < 14. */
3946 int r2 = get_field(f, r2);
3947 o->in1 = fregs[r2];
3948 o->in2 = fregs[(r2 + 2) & 15];
3949 o->g_in1 = o->g_in2 = true;
3950 }
3951
3952 static void in2_ra2(DisasContext *s, DisasFields *f, DisasOps *o)
3953 {
3954 o->in2 = get_address(s, 0, get_field(f, r2), 0);
3955 }
3956
3957 static void in2_a2(DisasContext *s, DisasFields *f, DisasOps *o)
3958 {
3959 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3960 o->in2 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3961 }
3962
3963 static void in2_ri2(DisasContext *s, DisasFields *f, DisasOps *o)
3964 {
3965 o->in2 = tcg_const_i64(s->pc + (int64_t)get_field(f, i2) * 2);
3966 }
3967
3968 static void in2_sh32(DisasContext *s, DisasFields *f, DisasOps *o)
3969 {
3970 help_l2_shift(s, f, o, 31);
3971 }
3972
3973 static void in2_sh64(DisasContext *s, DisasFields *f, DisasOps *o)
3974 {
3975 help_l2_shift(s, f, o, 63);
3976 }
3977
3978 static void in2_m2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3979 {
3980 in2_a2(s, f, o);
3981 tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s));
3982 }
3983
3984 static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3985 {
3986 in2_a2(s, f, o);
3987 tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
3988 }
3989
3990 static void in2_m2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3991 {
3992 in2_a2(s, f, o);
3993 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3994 }
3995
3996 static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3997 {
3998 in2_a2(s, f, o);
3999 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
4000 }
4001
4002 static void in2_m2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4003 {
4004 in2_a2(s, f, o);
4005 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
4006 }
4007
4008 static void in2_m2_64(DisasContext *s, DisasFields *f, DisasOps *o)
4009 {
4010 in2_a2(s, f, o);
4011 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
4012 }
4013
4014 static void in2_mri2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
4015 {
4016 in2_ri2(s, f, o);
4017 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
4018 }
4019
4020 static void in2_mri2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
4021 {
4022 in2_ri2(s, f, o);
4023 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
4024 }
4025
4026 static void in2_mri2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4027 {
4028 in2_ri2(s, f, o);
4029 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
4030 }
4031
4032 static void in2_mri2_64(DisasContext *s, DisasFields *f, DisasOps *o)
4033 {
4034 in2_ri2(s, f, o);
4035 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
4036 }
4037
4038 static void in2_i2(DisasContext *s, DisasFields *f, DisasOps *o)
4039 {
4040 o->in2 = tcg_const_i64(get_field(f, i2));
4041 }
4042
4043 static void in2_i2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
4044 {
4045 o->in2 = tcg_const_i64((uint8_t)get_field(f, i2));
4046 }
4047
4048 static void in2_i2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
4049 {
4050 o->in2 = tcg_const_i64((uint16_t)get_field(f, i2));
4051 }
4052
4053 static void in2_i2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4054 {
4055 o->in2 = tcg_const_i64((uint32_t)get_field(f, i2));
4056 }
4057
4058 static void in2_i2_16u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
4059 {
4060 uint64_t i2 = (uint16_t)get_field(f, i2);
4061 o->in2 = tcg_const_i64(i2 << s->insn->data);
4062 }
4063
4064 static void in2_i2_32u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
4065 {
4066 uint64_t i2 = (uint32_t)get_field(f, i2);
4067 o->in2 = tcg_const_i64(i2 << s->insn->data);
4068 }
4069
4070 /* ====================================================================== */
4071
4072 /* Find opc within the table of insns. This is formulated as a switch
4073 statement so that (1) we get compile-time notice of cut-paste errors
4074 for duplicated opcodes, and (2) the compiler generates the binary
4075 search tree, rather than us having to post-process the table. */
4076
4077 #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
4078 D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0)
4079
4080 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) insn_ ## NM,
4081
4082 enum DisasInsnEnum {
4083 #include "insn-data.def"
4084 };
4085
4086 #undef D
4087 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) { \
4088 .opc = OPC, \
4089 .fmt = FMT_##FT, \
4090 .fac = FAC_##FC, \
4091 .name = #NM, \
4092 .help_in1 = in1_##I1, \
4093 .help_in2 = in2_##I2, \
4094 .help_prep = prep_##P, \
4095 .help_wout = wout_##W, \
4096 .help_cout = cout_##CC, \
4097 .help_op = op_##OP, \
4098 .data = D \
4099 },
4100
4101 /* Allow 0 to be used for NULL in the table below. */
4102 #define in1_0 NULL
4103 #define in2_0 NULL
4104 #define prep_0 NULL
4105 #define wout_0 NULL
4106 #define cout_0 NULL
4107 #define op_0 NULL
4108
4109 static const DisasInsn insn_info[] = {
4110 #include "insn-data.def"
4111 };
4112
4113 #undef D
4114 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
4115 case OPC: return &insn_info[insn_ ## NM];
4116
4117 static const DisasInsn *lookup_opc(uint16_t opc)
4118 {
4119 switch (opc) {
4120 #include "insn-data.def"
4121 default:
4122 return NULL;
4123 }
4124 }
4125
4126 #undef D
4127 #undef C
4128
4129 /* Extract a field from the insn. The INSN should be left-aligned in
4130 the uint64_t so that we can more easily utilize the big-bit-endian
4131 definitions we extract from the Principals of Operation. */
4132
4133 static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn)
4134 {
4135 uint32_t r, m;
4136
4137 if (f->size == 0) {
4138 return;
4139 }
4140
4141 /* Zero extract the field from the insn. */
4142 r = (insn << f->beg) >> (64 - f->size);
4143
4144 /* Sign-extend, or un-swap the field as necessary. */
4145 switch (f->type) {
4146 case 0: /* unsigned */
4147 break;
4148 case 1: /* signed */
4149 assert(f->size <= 32);
4150 m = 1u << (f->size - 1);
4151 r = (r ^ m) - m;
4152 break;
4153 case 2: /* dl+dh split, signed 20 bit. */
4154 r = ((int8_t)r << 12) | (r >> 8);
4155 break;
4156 default:
4157 abort();
4158 }
4159
4160 /* Validate that the "compressed" encoding we selected above is valid.
4161 I.e. we havn't make two different original fields overlap. */
4162 assert(((o->presentC >> f->indexC) & 1) == 0);
4163 o->presentC |= 1 << f->indexC;
4164 o->presentO |= 1 << f->indexO;
4165
4166 o->c[f->indexC] = r;
4167 }
4168
4169 /* Lookup the insn at the current PC, extracting the operands into O and
4170 returning the info struct for the insn. Returns NULL for invalid insn. */
4171
4172 static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
4173 DisasFields *f)
4174 {
4175 uint64_t insn, pc = s->pc;
4176 int op, op2, ilen;
4177 const DisasInsn *info;
4178
4179 insn = ld_code2(env, pc);
4180 op = (insn >> 8) & 0xff;
4181 ilen = get_ilen(op);
4182 s->next_pc = s->pc + ilen;
4183
4184 switch (ilen) {
4185 case 2:
4186 insn = insn << 48;
4187 break;
4188 case 4:
4189 insn = ld_code4(env, pc) << 32;
4190 break;
4191 case 6:
4192 insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
4193 break;
4194 default:
4195 abort();
4196 }
4197
4198 /* We can't actually determine the insn format until we've looked up
4199 the full insn opcode. Which we can't do without locating the
4200 secondary opcode. Assume by default that OP2 is at bit 40; for
4201 those smaller insns that don't actually have a secondary opcode
4202 this will correctly result in OP2 = 0. */
4203 switch (op) {
4204 case 0x01: /* E */
4205 case 0x80: /* S */
4206 case 0x82: /* S */
4207 case 0x93: /* S */
4208 case 0xb2: /* S, RRF, RRE */
4209 case 0xb3: /* RRE, RRD, RRF */
4210 case 0xb9: /* RRE, RRF */
4211 case 0xe5: /* SSE, SIL */
4212 op2 = (insn << 8) >> 56;
4213 break;
4214 case 0xa5: /* RI */
4215 case 0xa7: /* RI */
4216 case 0xc0: /* RIL */
4217 case 0xc2: /* RIL */
4218 case 0xc4: /* RIL */
4219 case 0xc6: /* RIL */
4220 case 0xc8: /* SSF */
4221 case 0xcc: /* RIL */
4222 op2 = (insn << 12) >> 60;
4223 break;
4224 case 0xd0 ... 0xdf: /* SS */
4225 case 0xe1: /* SS */
4226 case 0xe2: /* SS */
4227 case 0xe8: /* SS */
4228 case 0xe9: /* SS */
4229 case 0xea: /* SS */
4230 case 0xee ... 0xf3: /* SS */
4231 case 0xf8 ... 0xfd: /* SS */
4232 op2 = 0;
4233 break;
4234 default:
4235 op2 = (insn << 40) >> 56;
4236 break;
4237 }
4238
4239 memset(f, 0, sizeof(*f));
4240 f->op = op;
4241 f->op2 = op2;
4242
4243 /* Lookup the instruction. */
4244 info = lookup_opc(op << 8 | op2);
4245
4246 /* If we found it, extract the operands. */
4247 if (info != NULL) {
4248 DisasFormat fmt = info->fmt;
4249 int i;
4250
4251 for (i = 0; i < NUM_C_FIELD; ++i) {
4252 extract_field(f, &format_info[fmt].op[i], insn);
4253 }
4254 }
4255 return info;
4256 }
4257
4258 static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
4259 {
4260 const DisasInsn *insn;
4261 ExitStatus ret = NO_EXIT;
4262 DisasFields f;
4263 DisasOps o;
4264
4265 /* Search for the insn in the table. */
4266 insn = extract_insn(env, s, &f);
4267
4268 /* Not found means unimplemented/illegal opcode. */
4269 if (insn == NULL) {
4270 qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%02x%02x\n",
4271 f.op, f.op2);
4272 gen_illegal_opcode(s);
4273 return EXIT_NORETURN;
4274 }
4275
4276 /* Set up the strutures we use to communicate with the helpers. */
4277 s->insn = insn;
4278 s->fields = &f;
4279 o.g_out = o.g_out2 = o.g_in1 = o.g_in2 = false;
4280 TCGV_UNUSED_I64(o.out);
4281 TCGV_UNUSED_I64(o.out2);
4282 TCGV_UNUSED_I64(o.in1);
4283 TCGV_UNUSED_I64(o.in2);
4284 TCGV_UNUSED_I64(o.addr1);
4285
4286 /* Implement the instruction. */
4287 if (insn->help_in1) {
4288 insn->help_in1(s, &f, &o);
4289 }
4290 if (insn->help_in2) {
4291 insn->help_in2(s, &f, &o);
4292 }
4293 if (insn->help_prep) {
4294 insn->help_prep(s, &f, &o);
4295 }
4296 if (insn->help_op) {
4297 ret = insn->help_op(s, &o);
4298 }
4299 if (insn->help_wout) {
4300 insn->help_wout(s, &f, &o);
4301 }
4302 if (insn->help_cout) {
4303 insn->help_cout(s, &o);
4304 }
4305
4306 /* Free any temporaries created by the helpers. */
4307 if (!TCGV_IS_UNUSED_I64(o.out) && !o.g_out) {
4308 tcg_temp_free_i64(o.out);
4309 }
4310 if (!TCGV_IS_UNUSED_I64(o.out2) && !o.g_out2) {
4311 tcg_temp_free_i64(o.out2);
4312 }
4313 if (!TCGV_IS_UNUSED_I64(o.in1) && !o.g_in1) {
4314 tcg_temp_free_i64(o.in1);
4315 }
4316 if (!TCGV_IS_UNUSED_I64(o.in2) && !o.g_in2) {
4317 tcg_temp_free_i64(o.in2);
4318 }
4319 if (!TCGV_IS_UNUSED_I64(o.addr1)) {
4320 tcg_temp_free_i64(o.addr1);
4321 }
4322
4323 /* Advance to the next instruction. */
4324 s->pc = s->next_pc;
4325 return ret;
4326 }
4327
4328 static inline void gen_intermediate_code_internal(CPUS390XState *env,
4329 TranslationBlock *tb,
4330 int search_pc)
4331 {
4332 DisasContext dc;
4333 target_ulong pc_start;
4334 uint64_t next_page_start;
4335 uint16_t *gen_opc_end;
4336 int j, lj = -1;
4337 int num_insns, max_insns;
4338 CPUBreakpoint *bp;
4339 ExitStatus status;
4340 bool do_debug;
4341
4342 pc_start = tb->pc;
4343
4344 /* 31-bit mode */
4345 if (!(tb->flags & FLAG_MASK_64)) {
4346 pc_start &= 0x7fffffff;
4347 }
4348
4349 dc.tb = tb;
4350 dc.pc = pc_start;
4351 dc.cc_op = CC_OP_DYNAMIC;
4352 do_debug = dc.singlestep_enabled = env->singlestep_enabled;
4353
4354 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
4355
4356 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4357
4358 num_insns = 0;
4359 max_insns = tb->cflags & CF_COUNT_MASK;
4360 if (max_insns == 0) {
4361 max_insns = CF_COUNT_MASK;
4362 }
4363
4364 gen_icount_start();
4365
4366 do {
4367 if (search_pc) {
4368 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4369 if (lj < j) {
4370 lj++;
4371 while (lj < j) {
4372 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4373 }
4374 }
4375 tcg_ctx.gen_opc_pc[lj] = dc.pc;
4376 gen_opc_cc_op[lj] = dc.cc_op;
4377 tcg_ctx.gen_opc_instr_start[lj] = 1;
4378 tcg_ctx.gen_opc_icount[lj] = num_insns;
4379 }
4380 if (++num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
4381 gen_io_start();
4382 }
4383
4384 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4385 tcg_gen_debug_insn_start(dc.pc);
4386 }
4387
4388 status = NO_EXIT;
4389 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
4390 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
4391 if (bp->pc == dc.pc) {
4392 status = EXIT_PC_STALE;
4393 do_debug = true;
4394 break;
4395 }
4396 }
4397 }
4398 if (status == NO_EXIT) {
4399 status = translate_one(env, &dc);
4400 }
4401
4402 /* If we reach a page boundary, are single stepping,
4403 or exhaust instruction count, stop generation. */
4404 if (status == NO_EXIT
4405 && (dc.pc >= next_page_start
4406 || tcg_ctx.gen_opc_ptr >= gen_opc_end
4407 || num_insns >= max_insns
4408 || singlestep
4409 || env->singlestep_enabled)) {
4410 status = EXIT_PC_STALE;
4411 }
4412 } while (status == NO_EXIT);
4413
4414 if (tb->cflags & CF_LAST_IO) {
4415 gen_io_end();
4416 }
4417
4418 switch (status) {
4419 case EXIT_GOTO_TB:
4420 case EXIT_NORETURN:
4421 break;
4422 case EXIT_PC_STALE:
4423 update_psw_addr(&dc);
4424 /* FALLTHRU */
4425 case EXIT_PC_UPDATED:
4426 /* Next TB starts off with CC_OP_DYNAMIC, so make sure the
4427 cc op type is in env */
4428 update_cc_op(&dc);
4429 /* Exit the TB, either by raising a debug exception or by return. */
4430 if (do_debug) {
4431 gen_exception(EXCP_DEBUG);
4432 } else {
4433 tcg_gen_exit_tb(0);
4434 }
4435 break;
4436 default:
4437 abort();
4438 }
4439
4440 gen_icount_end(tb, num_insns);
4441 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
4442 if (search_pc) {
4443 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4444 lj++;
4445 while (lj <= j) {
4446 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4447 }
4448 } else {
4449 tb->size = dc.pc - pc_start;
4450 tb->icount = num_insns;
4451 }
4452
4453 #if defined(S390X_DEBUG_DISAS)
4454 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
4455 qemu_log("IN: %s\n", lookup_symbol(pc_start));
4456 log_target_disas(env, pc_start, dc.pc - pc_start, 1);
4457 qemu_log("\n");
4458 }
4459 #endif
4460 }
4461
4462 void gen_intermediate_code (CPUS390XState *env, struct TranslationBlock *tb)
4463 {
4464 gen_intermediate_code_internal(env, tb, 0);
4465 }
4466
4467 void gen_intermediate_code_pc (CPUS390XState *env, struct TranslationBlock *tb)
4468 {
4469 gen_intermediate_code_internal(env, tb, 1);
4470 }
4471
4472 void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos)
4473 {
4474 int cc_op;
4475 env->psw.addr = tcg_ctx.gen_opc_pc[pc_pos];
4476 cc_op = gen_opc_cc_op[pc_pos];
4477 if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {
4478 env->cc_op = cc_op;
4479 }
4480 }
Qemu copy for testing