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target-s390: Convert EAR, SAR
[qemu.git] / target-s390x / translate.c
1 /*
2 * S/390 translation
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* #define DEBUG_INLINE_BRANCHES */
22 #define S390X_DEBUG_DISAS
23 /* #define S390X_DEBUG_DISAS_VERBOSE */
24
25 #ifdef S390X_DEBUG_DISAS_VERBOSE
26 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
27 #else
28 # define LOG_DISAS(...) do { } while (0)
29 #endif
30
31 #include "cpu.h"
32 #include "disas/disas.h"
33 #include "tcg-op.h"
34 #include "qemu/log.h"
35 #include "qemu/host-utils.h"
36
37 /* global register indexes */
38 static TCGv_ptr cpu_env;
39
40 #include "exec/gen-icount.h"
41 #include "helper.h"
42 #define GEN_HELPER 1
43 #include "helper.h"
44
45
46 /* Information that (most) every instruction needs to manipulate. */
47 typedef struct DisasContext DisasContext;
48 typedef struct DisasInsn DisasInsn;
49 typedef struct DisasFields DisasFields;
50
51 struct DisasContext {
52 struct TranslationBlock *tb;
53 const DisasInsn *insn;
54 DisasFields *fields;
55 uint64_t pc, next_pc;
56 enum cc_op cc_op;
57 bool singlestep_enabled;
58 int is_jmp;
59 };
60
61 /* Information carried about a condition to be evaluated. */
62 typedef struct {
63 TCGCond cond:8;
64 bool is_64;
65 bool g1;
66 bool g2;
67 union {
68 struct { TCGv_i64 a, b; } s64;
69 struct { TCGv_i32 a, b; } s32;
70 } u;
71 } DisasCompare;
72
73 #define DISAS_EXCP 4
74
75 static void gen_op_calc_cc(DisasContext *s);
76
77 #ifdef DEBUG_INLINE_BRANCHES
78 static uint64_t inline_branch_hit[CC_OP_MAX];
79 static uint64_t inline_branch_miss[CC_OP_MAX];
80 #endif
81
82 static inline void debug_insn(uint64_t insn)
83 {
84 LOG_DISAS("insn: 0x%" PRIx64 "\n", insn);
85 }
86
87 static inline uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
88 {
89 if (!(s->tb->flags & FLAG_MASK_64)) {
90 if (s->tb->flags & FLAG_MASK_32) {
91 return pc | 0x80000000;
92 }
93 }
94 return pc;
95 }
96
97 void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
98 int flags)
99 {
100 int i;
101
102 if (env->cc_op > 3) {
103 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
104 env->psw.mask, env->psw.addr, cc_name(env->cc_op));
105 } else {
106 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
107 env->psw.mask, env->psw.addr, env->cc_op);
108 }
109
110 for (i = 0; i < 16; i++) {
111 cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
112 if ((i % 4) == 3) {
113 cpu_fprintf(f, "\n");
114 } else {
115 cpu_fprintf(f, " ");
116 }
117 }
118
119 for (i = 0; i < 16; i++) {
120 cpu_fprintf(f, "F%02d=%016" PRIx64, i, env->fregs[i].ll);
121 if ((i % 4) == 3) {
122 cpu_fprintf(f, "\n");
123 } else {
124 cpu_fprintf(f, " ");
125 }
126 }
127
128 #ifndef CONFIG_USER_ONLY
129 for (i = 0; i < 16; i++) {
130 cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
131 if ((i % 4) == 3) {
132 cpu_fprintf(f, "\n");
133 } else {
134 cpu_fprintf(f, " ");
135 }
136 }
137 #endif
138
139 #ifdef DEBUG_INLINE_BRANCHES
140 for (i = 0; i < CC_OP_MAX; i++) {
141 cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
142 inline_branch_miss[i], inline_branch_hit[i]);
143 }
144 #endif
145
146 cpu_fprintf(f, "\n");
147 }
148
149 static TCGv_i64 psw_addr;
150 static TCGv_i64 psw_mask;
151
152 static TCGv_i32 cc_op;
153 static TCGv_i64 cc_src;
154 static TCGv_i64 cc_dst;
155 static TCGv_i64 cc_vr;
156
157 static char cpu_reg_names[32][4];
158 static TCGv_i64 regs[16];
159 static TCGv_i64 fregs[16];
160
161 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
162
163 void s390x_translate_init(void)
164 {
165 int i;
166
167 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
168 psw_addr = tcg_global_mem_new_i64(TCG_AREG0,
169 offsetof(CPUS390XState, psw.addr),
170 "psw_addr");
171 psw_mask = tcg_global_mem_new_i64(TCG_AREG0,
172 offsetof(CPUS390XState, psw.mask),
173 "psw_mask");
174
175 cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUS390XState, cc_op),
176 "cc_op");
177 cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_src),
178 "cc_src");
179 cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_dst),
180 "cc_dst");
181 cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_vr),
182 "cc_vr");
183
184 for (i = 0; i < 16; i++) {
185 snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i);
186 regs[i] = tcg_global_mem_new(TCG_AREG0,
187 offsetof(CPUS390XState, regs[i]),
188 cpu_reg_names[i]);
189 }
190
191 for (i = 0; i < 16; i++) {
192 snprintf(cpu_reg_names[i + 16], sizeof(cpu_reg_names[0]), "f%d", i);
193 fregs[i] = tcg_global_mem_new(TCG_AREG0,
194 offsetof(CPUS390XState, fregs[i].d),
195 cpu_reg_names[i + 16]);
196 }
197
198 /* register helpers */
199 #define GEN_HELPER 2
200 #include "helper.h"
201 }
202
203 static inline TCGv_i64 load_reg(int reg)
204 {
205 TCGv_i64 r = tcg_temp_new_i64();
206 tcg_gen_mov_i64(r, regs[reg]);
207 return r;
208 }
209
210 static inline TCGv_i64 load_freg(int reg)
211 {
212 TCGv_i64 r = tcg_temp_new_i64();
213 tcg_gen_mov_i64(r, fregs[reg]);
214 return r;
215 }
216
217 static inline TCGv_i32 load_freg32(int reg)
218 {
219 TCGv_i32 r = tcg_temp_new_i32();
220 #if HOST_LONG_BITS == 32
221 tcg_gen_mov_i32(r, TCGV_HIGH(fregs[reg]));
222 #else
223 tcg_gen_shri_i64(MAKE_TCGV_I64(GET_TCGV_I32(r)), fregs[reg], 32);
224 #endif
225 return r;
226 }
227
228 static inline TCGv_i64 load_freg32_i64(int reg)
229 {
230 TCGv_i64 r = tcg_temp_new_i64();
231 tcg_gen_shri_i64(r, fregs[reg], 32);
232 return r;
233 }
234
235 static inline TCGv_i32 load_reg32(int reg)
236 {
237 TCGv_i32 r = tcg_temp_new_i32();
238 tcg_gen_trunc_i64_i32(r, regs[reg]);
239 return r;
240 }
241
242 static inline TCGv_i64 load_reg32_i64(int reg)
243 {
244 TCGv_i64 r = tcg_temp_new_i64();
245 tcg_gen_ext32s_i64(r, regs[reg]);
246 return r;
247 }
248
249 static inline void store_reg(int reg, TCGv_i64 v)
250 {
251 tcg_gen_mov_i64(regs[reg], v);
252 }
253
254 static inline void store_freg(int reg, TCGv_i64 v)
255 {
256 tcg_gen_mov_i64(fregs[reg], v);
257 }
258
259 static inline void store_reg32(int reg, TCGv_i32 v)
260 {
261 /* 32 bit register writes keep the upper half */
262 #if HOST_LONG_BITS == 32
263 tcg_gen_mov_i32(TCGV_LOW(regs[reg]), v);
264 #else
265 tcg_gen_deposit_i64(regs[reg], regs[reg],
266 MAKE_TCGV_I64(GET_TCGV_I32(v)), 0, 32);
267 #endif
268 }
269
270 static inline void store_reg32_i64(int reg, TCGv_i64 v)
271 {
272 /* 32 bit register writes keep the upper half */
273 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
274 }
275
276 static inline void store_reg32h_i64(int reg, TCGv_i64 v)
277 {
278 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 32, 32);
279 }
280
281 static inline void store_freg32(int reg, TCGv_i32 v)
282 {
283 /* 32 bit register writes keep the lower half */
284 #if HOST_LONG_BITS == 32
285 tcg_gen_mov_i32(TCGV_HIGH(fregs[reg]), v);
286 #else
287 tcg_gen_deposit_i64(fregs[reg], fregs[reg],
288 MAKE_TCGV_I64(GET_TCGV_I32(v)), 32, 32);
289 #endif
290 }
291
292 static inline void store_freg32_i64(int reg, TCGv_i64 v)
293 {
294 tcg_gen_deposit_i64(fregs[reg], fregs[reg], v, 32, 32);
295 }
296
297 static inline void return_low128(TCGv_i64 dest)
298 {
299 tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl));
300 }
301
302 static inline void update_psw_addr(DisasContext *s)
303 {
304 /* psw.addr */
305 tcg_gen_movi_i64(psw_addr, s->pc);
306 }
307
308 static inline void potential_page_fault(DisasContext *s)
309 {
310 #ifndef CONFIG_USER_ONLY
311 update_psw_addr(s);
312 gen_op_calc_cc(s);
313 #endif
314 }
315
316 static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
317 {
318 return (uint64_t)cpu_lduw_code(env, pc);
319 }
320
321 static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
322 {
323 return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
324 }
325
326 static inline uint64_t ld_code6(CPUS390XState *env, uint64_t pc)
327 {
328 return (ld_code2(env, pc) << 32) | ld_code4(env, pc + 2);
329 }
330
331 static inline int get_mem_index(DisasContext *s)
332 {
333 switch (s->tb->flags & FLAG_MASK_ASC) {
334 case PSW_ASC_PRIMARY >> 32:
335 return 0;
336 case PSW_ASC_SECONDARY >> 32:
337 return 1;
338 case PSW_ASC_HOME >> 32:
339 return 2;
340 default:
341 tcg_abort();
342 break;
343 }
344 }
345
346 static void gen_exception(int excp)
347 {
348 TCGv_i32 tmp = tcg_const_i32(excp);
349 gen_helper_exception(cpu_env, tmp);
350 tcg_temp_free_i32(tmp);
351 }
352
353 static void gen_program_exception(DisasContext *s, int code)
354 {
355 TCGv_i32 tmp;
356
357 /* Remember what pgm exeption this was. */
358 tmp = tcg_const_i32(code);
359 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
360 tcg_temp_free_i32(tmp);
361
362 tmp = tcg_const_i32(s->next_pc - s->pc);
363 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen));
364 tcg_temp_free_i32(tmp);
365
366 /* Advance past instruction. */
367 s->pc = s->next_pc;
368 update_psw_addr(s);
369
370 /* Save off cc. */
371 gen_op_calc_cc(s);
372
373 /* Trigger exception. */
374 gen_exception(EXCP_PGM);
375
376 /* End TB here. */
377 s->is_jmp = DISAS_EXCP;
378 }
379
380 static inline void gen_illegal_opcode(DisasContext *s)
381 {
382 gen_program_exception(s, PGM_SPECIFICATION);
383 }
384
385 static inline void check_privileged(DisasContext *s)
386 {
387 if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
388 gen_program_exception(s, PGM_PRIVILEGED);
389 }
390 }
391
392 static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
393 {
394 TCGv_i64 tmp;
395
396 /* 31-bitify the immediate part; register contents are dealt with below */
397 if (!(s->tb->flags & FLAG_MASK_64)) {
398 d2 &= 0x7fffffffUL;
399 }
400
401 if (x2) {
402 if (d2) {
403 tmp = tcg_const_i64(d2);
404 tcg_gen_add_i64(tmp, tmp, regs[x2]);
405 } else {
406 tmp = load_reg(x2);
407 }
408 if (b2) {
409 tcg_gen_add_i64(tmp, tmp, regs[b2]);
410 }
411 } else if (b2) {
412 if (d2) {
413 tmp = tcg_const_i64(d2);
414 tcg_gen_add_i64(tmp, tmp, regs[b2]);
415 } else {
416 tmp = load_reg(b2);
417 }
418 } else {
419 tmp = tcg_const_i64(d2);
420 }
421
422 /* 31-bit mode mask if there are values loaded from registers */
423 if (!(s->tb->flags & FLAG_MASK_64) && (x2 || b2)) {
424 tcg_gen_andi_i64(tmp, tmp, 0x7fffffffUL);
425 }
426
427 return tmp;
428 }
429
430 static void gen_op_movi_cc(DisasContext *s, uint32_t val)
431 {
432 s->cc_op = CC_OP_CONST0 + val;
433 }
434
435 static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
436 {
437 tcg_gen_discard_i64(cc_src);
438 tcg_gen_mov_i64(cc_dst, dst);
439 tcg_gen_discard_i64(cc_vr);
440 s->cc_op = op;
441 }
442
443 static void gen_op_update1_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 dst)
444 {
445 tcg_gen_discard_i64(cc_src);
446 tcg_gen_extu_i32_i64(cc_dst, dst);
447 tcg_gen_discard_i64(cc_vr);
448 s->cc_op = op;
449 }
450
451 static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
452 TCGv_i64 dst)
453 {
454 tcg_gen_mov_i64(cc_src, src);
455 tcg_gen_mov_i64(cc_dst, dst);
456 tcg_gen_discard_i64(cc_vr);
457 s->cc_op = op;
458 }
459
460 static void gen_op_update2_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src,
461 TCGv_i32 dst)
462 {
463 tcg_gen_extu_i32_i64(cc_src, src);
464 tcg_gen_extu_i32_i64(cc_dst, dst);
465 tcg_gen_discard_i64(cc_vr);
466 s->cc_op = op;
467 }
468
469 static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
470 TCGv_i64 dst, TCGv_i64 vr)
471 {
472 tcg_gen_mov_i64(cc_src, src);
473 tcg_gen_mov_i64(cc_dst, dst);
474 tcg_gen_mov_i64(cc_vr, vr);
475 s->cc_op = op;
476 }
477
478 static inline void set_cc_nz_u32(DisasContext *s, TCGv_i32 val)
479 {
480 gen_op_update1_cc_i32(s, CC_OP_NZ, val);
481 }
482
483 static inline void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
484 {
485 gen_op_update1_cc_i64(s, CC_OP_NZ, val);
486 }
487
488 static inline void gen_set_cc_nz_f32(DisasContext *s, TCGv_i64 val)
489 {
490 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, val);
491 }
492
493 static inline void gen_set_cc_nz_f64(DisasContext *s, TCGv_i64 val)
494 {
495 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, val);
496 }
497
498 static inline void gen_set_cc_nz_f128(DisasContext *s, TCGv_i64 vh, TCGv_i64 vl)
499 {
500 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, vh, vl);
501 }
502
503 static inline void cmp_32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
504 enum cc_op cond)
505 {
506 gen_op_update2_cc_i32(s, cond, v1, v2);
507 }
508
509 static inline void cmp_64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
510 enum cc_op cond)
511 {
512 gen_op_update2_cc_i64(s, cond, v1, v2);
513 }
514
515 static inline void cmp_s32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
516 {
517 cmp_32(s, v1, v2, CC_OP_LTGT_32);
518 }
519
520 static inline void cmp_u32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
521 {
522 cmp_32(s, v1, v2, CC_OP_LTUGTU_32);
523 }
524
525 static inline void cmp_s32c(DisasContext *s, TCGv_i32 v1, int32_t v2)
526 {
527 /* XXX optimize for the constant? put it in s? */
528 TCGv_i32 tmp = tcg_const_i32(v2);
529 cmp_32(s, v1, tmp, CC_OP_LTGT_32);
530 tcg_temp_free_i32(tmp);
531 }
532
533 static inline void cmp_u32c(DisasContext *s, TCGv_i32 v1, uint32_t v2)
534 {
535 TCGv_i32 tmp = tcg_const_i32(v2);
536 cmp_32(s, v1, tmp, CC_OP_LTUGTU_32);
537 tcg_temp_free_i32(tmp);
538 }
539
540 static inline void cmp_s64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
541 {
542 cmp_64(s, v1, v2, CC_OP_LTGT_64);
543 }
544
545 static inline void cmp_u64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
546 {
547 cmp_64(s, v1, v2, CC_OP_LTUGTU_64);
548 }
549
550 static inline void cmp_s64c(DisasContext *s, TCGv_i64 v1, int64_t v2)
551 {
552 TCGv_i64 tmp = tcg_const_i64(v2);
553 cmp_s64(s, v1, tmp);
554 tcg_temp_free_i64(tmp);
555 }
556
557 static inline void cmp_u64c(DisasContext *s, TCGv_i64 v1, uint64_t v2)
558 {
559 TCGv_i64 tmp = tcg_const_i64(v2);
560 cmp_u64(s, v1, tmp);
561 tcg_temp_free_i64(tmp);
562 }
563
564 static inline void set_cc_s32(DisasContext *s, TCGv_i32 val)
565 {
566 gen_op_update1_cc_i32(s, CC_OP_LTGT0_32, val);
567 }
568
569 static inline void set_cc_s64(DisasContext *s, TCGv_i64 val)
570 {
571 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, val);
572 }
573
574 /* CC value is in env->cc_op */
575 static inline void set_cc_static(DisasContext *s)
576 {
577 tcg_gen_discard_i64(cc_src);
578 tcg_gen_discard_i64(cc_dst);
579 tcg_gen_discard_i64(cc_vr);
580 s->cc_op = CC_OP_STATIC;
581 }
582
583 static inline void gen_op_set_cc_op(DisasContext *s)
584 {
585 if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
586 tcg_gen_movi_i32(cc_op, s->cc_op);
587 }
588 }
589
590 static inline void gen_update_cc_op(DisasContext *s)
591 {
592 gen_op_set_cc_op(s);
593 }
594
595 /* calculates cc into cc_op */
596 static void gen_op_calc_cc(DisasContext *s)
597 {
598 TCGv_i32 local_cc_op = tcg_const_i32(s->cc_op);
599 TCGv_i64 dummy = tcg_const_i64(0);
600
601 switch (s->cc_op) {
602 case CC_OP_CONST0:
603 case CC_OP_CONST1:
604 case CC_OP_CONST2:
605 case CC_OP_CONST3:
606 /* s->cc_op is the cc value */
607 tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
608 break;
609 case CC_OP_STATIC:
610 /* env->cc_op already is the cc value */
611 break;
612 case CC_OP_NZ:
613 case CC_OP_ABS_64:
614 case CC_OP_NABS_64:
615 case CC_OP_ABS_32:
616 case CC_OP_NABS_32:
617 case CC_OP_LTGT0_32:
618 case CC_OP_LTGT0_64:
619 case CC_OP_COMP_32:
620 case CC_OP_COMP_64:
621 case CC_OP_NZ_F32:
622 case CC_OP_NZ_F64:
623 case CC_OP_FLOGR:
624 /* 1 argument */
625 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dummy);
626 break;
627 case CC_OP_ICM:
628 case CC_OP_LTGT_32:
629 case CC_OP_LTGT_64:
630 case CC_OP_LTUGTU_32:
631 case CC_OP_LTUGTU_64:
632 case CC_OP_TM_32:
633 case CC_OP_TM_64:
634 case CC_OP_SLA_32:
635 case CC_OP_SLA_64:
636 case CC_OP_NZ_F128:
637 /* 2 arguments */
638 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
639 break;
640 case CC_OP_ADD_64:
641 case CC_OP_ADDU_64:
642 case CC_OP_ADDC_64:
643 case CC_OP_SUB_64:
644 case CC_OP_SUBU_64:
645 case CC_OP_SUBB_64:
646 case CC_OP_ADD_32:
647 case CC_OP_ADDU_32:
648 case CC_OP_ADDC_32:
649 case CC_OP_SUB_32:
650 case CC_OP_SUBU_32:
651 case CC_OP_SUBB_32:
652 /* 3 arguments */
653 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc_vr);
654 break;
655 case CC_OP_DYNAMIC:
656 /* unknown operation - assume 3 arguments and cc_op in env */
657 gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr);
658 break;
659 default:
660 tcg_abort();
661 }
662
663 tcg_temp_free_i32(local_cc_op);
664 tcg_temp_free_i64(dummy);
665
666 /* We now have cc in cc_op as constant */
667 set_cc_static(s);
668 }
669
670 static inline void decode_rr(DisasContext *s, uint64_t insn, int *r1, int *r2)
671 {
672 debug_insn(insn);
673
674 *r1 = (insn >> 4) & 0xf;
675 *r2 = insn & 0xf;
676 }
677
678 static inline TCGv_i64 decode_rx(DisasContext *s, uint64_t insn, int *r1,
679 int *x2, int *b2, int *d2)
680 {
681 debug_insn(insn);
682
683 *r1 = (insn >> 20) & 0xf;
684 *x2 = (insn >> 16) & 0xf;
685 *b2 = (insn >> 12) & 0xf;
686 *d2 = insn & 0xfff;
687
688 return get_address(s, *x2, *b2, *d2);
689 }
690
691 static inline void decode_rs(DisasContext *s, uint64_t insn, int *r1, int *r3,
692 int *b2, int *d2)
693 {
694 debug_insn(insn);
695
696 *r1 = (insn >> 20) & 0xf;
697 /* aka m3 */
698 *r3 = (insn >> 16) & 0xf;
699 *b2 = (insn >> 12) & 0xf;
700 *d2 = insn & 0xfff;
701 }
702
703 static inline TCGv_i64 decode_si(DisasContext *s, uint64_t insn, int *i2,
704 int *b1, int *d1)
705 {
706 debug_insn(insn);
707
708 *i2 = (insn >> 16) & 0xff;
709 *b1 = (insn >> 12) & 0xf;
710 *d1 = insn & 0xfff;
711
712 return get_address(s, 0, *b1, *d1);
713 }
714
715 static int use_goto_tb(DisasContext *s, uint64_t dest)
716 {
717 /* NOTE: we handle the case where the TB spans two pages here */
718 return (((dest & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK)
719 || (dest & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK))
720 && !s->singlestep_enabled
721 && !(s->tb->cflags & CF_LAST_IO));
722 }
723
724 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong pc)
725 {
726 gen_update_cc_op(s);
727
728 if (use_goto_tb(s, pc)) {
729 tcg_gen_goto_tb(tb_num);
730 tcg_gen_movi_i64(psw_addr, pc);
731 tcg_gen_exit_tb((tcg_target_long)s->tb + tb_num);
732 } else {
733 /* jump to another page: currently not optimized */
734 tcg_gen_movi_i64(psw_addr, pc);
735 tcg_gen_exit_tb(0);
736 }
737 }
738
739 static inline void account_noninline_branch(DisasContext *s, int cc_op)
740 {
741 #ifdef DEBUG_INLINE_BRANCHES
742 inline_branch_miss[cc_op]++;
743 #endif
744 }
745
746 static inline void account_inline_branch(DisasContext *s, int cc_op)
747 {
748 #ifdef DEBUG_INLINE_BRANCHES
749 inline_branch_hit[cc_op]++;
750 #endif
751 }
752
753 /* Table of mask values to comparison codes, given a comparison as input.
754 For a true comparison CC=3 will never be set, but we treat this
755 conservatively for possible use when CC=3 indicates overflow. */
756 static const TCGCond ltgt_cond[16] = {
757 TCG_COND_NEVER, TCG_COND_NEVER, /* | | | x */
758 TCG_COND_GT, TCG_COND_NEVER, /* | | GT | x */
759 TCG_COND_LT, TCG_COND_NEVER, /* | LT | | x */
760 TCG_COND_NE, TCG_COND_NEVER, /* | LT | GT | x */
761 TCG_COND_EQ, TCG_COND_NEVER, /* EQ | | | x */
762 TCG_COND_GE, TCG_COND_NEVER, /* EQ | | GT | x */
763 TCG_COND_LE, TCG_COND_NEVER, /* EQ | LT | | x */
764 TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | LT | GT | x */
765 };
766
767 /* Table of mask values to comparison codes, given a logic op as input.
768 For such, only CC=0 and CC=1 should be possible. */
769 static const TCGCond nz_cond[16] = {
770 /* | | x | x */
771 TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER,
772 /* | NE | x | x */
773 TCG_COND_NE, TCG_COND_NE, TCG_COND_NE, TCG_COND_NE,
774 /* EQ | | x | x */
775 TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ,
776 /* EQ | NE | x | x */
777 TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS,
778 };
779
780 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
781 details required to generate a TCG comparison. */
782 static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
783 {
784 TCGCond cond;
785 enum cc_op old_cc_op = s->cc_op;
786
787 if (mask == 15 || mask == 0) {
788 c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER);
789 c->u.s32.a = cc_op;
790 c->u.s32.b = cc_op;
791 c->g1 = c->g2 = true;
792 c->is_64 = false;
793 return;
794 }
795
796 /* Find the TCG condition for the mask + cc op. */
797 switch (old_cc_op) {
798 case CC_OP_LTGT0_32:
799 case CC_OP_LTGT0_64:
800 case CC_OP_LTGT_32:
801 case CC_OP_LTGT_64:
802 cond = ltgt_cond[mask];
803 if (cond == TCG_COND_NEVER) {
804 goto do_dynamic;
805 }
806 account_inline_branch(s, old_cc_op);
807 break;
808
809 case CC_OP_LTUGTU_32:
810 case CC_OP_LTUGTU_64:
811 cond = tcg_unsigned_cond(ltgt_cond[mask]);
812 if (cond == TCG_COND_NEVER) {
813 goto do_dynamic;
814 }
815 account_inline_branch(s, old_cc_op);
816 break;
817
818 case CC_OP_NZ:
819 cond = nz_cond[mask];
820 if (cond == TCG_COND_NEVER) {
821 goto do_dynamic;
822 }
823 account_inline_branch(s, old_cc_op);
824 break;
825
826 case CC_OP_TM_32:
827 case CC_OP_TM_64:
828 switch (mask) {
829 case 8:
830 cond = TCG_COND_EQ;
831 break;
832 case 4 | 2 | 1:
833 cond = TCG_COND_NE;
834 break;
835 default:
836 goto do_dynamic;
837 }
838 account_inline_branch(s, old_cc_op);
839 break;
840
841 case CC_OP_ICM:
842 switch (mask) {
843 case 8:
844 cond = TCG_COND_EQ;
845 break;
846 case 4 | 2 | 1:
847 case 4 | 2:
848 cond = TCG_COND_NE;
849 break;
850 default:
851 goto do_dynamic;
852 }
853 account_inline_branch(s, old_cc_op);
854 break;
855
856 case CC_OP_FLOGR:
857 switch (mask & 0xa) {
858 case 8: /* src == 0 -> no one bit found */
859 cond = TCG_COND_EQ;
860 break;
861 case 2: /* src != 0 -> one bit found */
862 cond = TCG_COND_NE;
863 break;
864 default:
865 goto do_dynamic;
866 }
867 account_inline_branch(s, old_cc_op);
868 break;
869
870 default:
871 do_dynamic:
872 /* Calculate cc value. */
873 gen_op_calc_cc(s);
874 /* FALLTHRU */
875
876 case CC_OP_STATIC:
877 /* Jump based on CC. We'll load up the real cond below;
878 the assignment here merely avoids a compiler warning. */
879 account_noninline_branch(s, old_cc_op);
880 old_cc_op = CC_OP_STATIC;
881 cond = TCG_COND_NEVER;
882 break;
883 }
884
885 /* Load up the arguments of the comparison. */
886 c->is_64 = true;
887 c->g1 = c->g2 = false;
888 switch (old_cc_op) {
889 case CC_OP_LTGT0_32:
890 c->is_64 = false;
891 c->u.s32.a = tcg_temp_new_i32();
892 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_dst);
893 c->u.s32.b = tcg_const_i32(0);
894 break;
895 case CC_OP_LTGT_32:
896 case CC_OP_LTUGTU_32:
897 c->is_64 = false;
898 c->u.s32.a = tcg_temp_new_i32();
899 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_src);
900 c->u.s32.b = tcg_temp_new_i32();
901 tcg_gen_trunc_i64_i32(c->u.s32.b, cc_dst);
902 break;
903
904 case CC_OP_LTGT0_64:
905 case CC_OP_NZ:
906 case CC_OP_FLOGR:
907 c->u.s64.a = cc_dst;
908 c->u.s64.b = tcg_const_i64(0);
909 c->g1 = true;
910 break;
911 case CC_OP_LTGT_64:
912 case CC_OP_LTUGTU_64:
913 c->u.s64.a = cc_src;
914 c->u.s64.b = cc_dst;
915 c->g1 = c->g2 = true;
916 break;
917
918 case CC_OP_TM_32:
919 case CC_OP_TM_64:
920 case CC_OP_ICM:
921 c->u.s64.a = tcg_temp_new_i64();
922 c->u.s64.b = tcg_const_i64(0);
923 tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
924 break;
925
926 case CC_OP_STATIC:
927 c->is_64 = false;
928 c->u.s32.a = cc_op;
929 c->g1 = true;
930 switch (mask) {
931 case 0x8 | 0x4 | 0x2: /* cc != 3 */
932 cond = TCG_COND_NE;
933 c->u.s32.b = tcg_const_i32(3);
934 break;
935 case 0x8 | 0x4 | 0x1: /* cc != 2 */
936 cond = TCG_COND_NE;
937 c->u.s32.b = tcg_const_i32(2);
938 break;
939 case 0x8 | 0x2 | 0x1: /* cc != 1 */
940 cond = TCG_COND_NE;
941 c->u.s32.b = tcg_const_i32(1);
942 break;
943 case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
944 cond = TCG_COND_EQ;
945 c->g1 = false;
946 c->u.s32.a = tcg_temp_new_i32();
947 c->u.s32.b = tcg_const_i32(0);
948 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
949 break;
950 case 0x8 | 0x4: /* cc < 2 */
951 cond = TCG_COND_LTU;
952 c->u.s32.b = tcg_const_i32(2);
953 break;
954 case 0x8: /* cc == 0 */
955 cond = TCG_COND_EQ;
956 c->u.s32.b = tcg_const_i32(0);
957 break;
958 case 0x4 | 0x2 | 0x1: /* cc != 0 */
959 cond = TCG_COND_NE;
960 c->u.s32.b = tcg_const_i32(0);
961 break;
962 case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
963 cond = TCG_COND_NE;
964 c->g1 = false;
965 c->u.s32.a = tcg_temp_new_i32();
966 c->u.s32.b = tcg_const_i32(0);
967 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
968 break;
969 case 0x4: /* cc == 1 */
970 cond = TCG_COND_EQ;
971 c->u.s32.b = tcg_const_i32(1);
972 break;
973 case 0x2 | 0x1: /* cc > 1 */
974 cond = TCG_COND_GTU;
975 c->u.s32.b = tcg_const_i32(1);
976 break;
977 case 0x2: /* cc == 2 */
978 cond = TCG_COND_EQ;
979 c->u.s32.b = tcg_const_i32(2);
980 break;
981 case 0x1: /* cc == 3 */
982 cond = TCG_COND_EQ;
983 c->u.s32.b = tcg_const_i32(3);
984 break;
985 default:
986 /* CC is masked by something else: (8 >> cc) & mask. */
987 cond = TCG_COND_NE;
988 c->g1 = false;
989 c->u.s32.a = tcg_const_i32(8);
990 c->u.s32.b = tcg_const_i32(0);
991 tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op);
992 tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
993 break;
994 }
995 break;
996
997 default:
998 abort();
999 }
1000 c->cond = cond;
1001 }
1002
1003 static void free_compare(DisasCompare *c)
1004 {
1005 if (!c->g1) {
1006 if (c->is_64) {
1007 tcg_temp_free_i64(c->u.s64.a);
1008 } else {
1009 tcg_temp_free_i32(c->u.s32.a);
1010 }
1011 }
1012 if (!c->g2) {
1013 if (c->is_64) {
1014 tcg_temp_free_i64(c->u.s64.b);
1015 } else {
1016 tcg_temp_free_i32(c->u.s32.b);
1017 }
1018 }
1019 }
1020
1021 static void disas_b2(CPUS390XState *env, DisasContext *s, int op,
1022 uint32_t insn)
1023 {
1024 TCGv_i64 tmp, tmp2, tmp3;
1025 TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
1026 int r1, r2;
1027 #ifndef CONFIG_USER_ONLY
1028 int r3, d2, b2;
1029 #endif
1030
1031 r1 = (insn >> 4) & 0xf;
1032 r2 = insn & 0xf;
1033
1034 LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op, r1, r2);
1035
1036 switch (op) {
1037 case 0x54: /* MVPG R1,R2 [RRE] */
1038 tmp = load_reg(0);
1039 tmp2 = load_reg(r1);
1040 tmp3 = load_reg(r2);
1041 potential_page_fault(s);
1042 gen_helper_mvpg(cpu_env, tmp, tmp2, tmp3);
1043 tcg_temp_free_i64(tmp);
1044 tcg_temp_free_i64(tmp2);
1045 tcg_temp_free_i64(tmp3);
1046 /* XXX check CCO bit and set CC accordingly */
1047 gen_op_movi_cc(s, 0);
1048 break;
1049 case 0x55: /* MVST R1,R2 [RRE] */
1050 tmp32_1 = load_reg32(0);
1051 tmp32_2 = tcg_const_i32(r1);
1052 tmp32_3 = tcg_const_i32(r2);
1053 potential_page_fault(s);
1054 gen_helper_mvst(cpu_env, tmp32_1, tmp32_2, tmp32_3);
1055 tcg_temp_free_i32(tmp32_1);
1056 tcg_temp_free_i32(tmp32_2);
1057 tcg_temp_free_i32(tmp32_3);
1058 gen_op_movi_cc(s, 1);
1059 break;
1060 case 0x5d: /* CLST R1,R2 [RRE] */
1061 tmp32_1 = load_reg32(0);
1062 tmp32_2 = tcg_const_i32(r1);
1063 tmp32_3 = tcg_const_i32(r2);
1064 potential_page_fault(s);
1065 gen_helper_clst(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1066 set_cc_static(s);
1067 tcg_temp_free_i32(tmp32_1);
1068 tcg_temp_free_i32(tmp32_2);
1069 tcg_temp_free_i32(tmp32_3);
1070 break;
1071 case 0x5e: /* SRST R1,R2 [RRE] */
1072 tmp32_1 = load_reg32(0);
1073 tmp32_2 = tcg_const_i32(r1);
1074 tmp32_3 = tcg_const_i32(r2);
1075 potential_page_fault(s);
1076 gen_helper_srst(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1077 set_cc_static(s);
1078 tcg_temp_free_i32(tmp32_1);
1079 tcg_temp_free_i32(tmp32_2);
1080 tcg_temp_free_i32(tmp32_3);
1081 break;
1082
1083 #ifndef CONFIG_USER_ONLY
1084 case 0x02: /* STIDP D2(B2) [S] */
1085 /* Store CPU ID */
1086 check_privileged(s);
1087 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1088 tmp = get_address(s, 0, b2, d2);
1089 potential_page_fault(s);
1090 gen_helper_stidp(cpu_env, tmp);
1091 tcg_temp_free_i64(tmp);
1092 break;
1093 case 0x04: /* SCK D2(B2) [S] */
1094 /* Set Clock */
1095 check_privileged(s);
1096 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1097 tmp = get_address(s, 0, b2, d2);
1098 potential_page_fault(s);
1099 gen_helper_sck(cc_op, tmp);
1100 set_cc_static(s);
1101 tcg_temp_free_i64(tmp);
1102 break;
1103 case 0x05: /* STCK D2(B2) [S] */
1104 /* Store Clock */
1105 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1106 tmp = get_address(s, 0, b2, d2);
1107 potential_page_fault(s);
1108 gen_helper_stck(cc_op, cpu_env, tmp);
1109 set_cc_static(s);
1110 tcg_temp_free_i64(tmp);
1111 break;
1112 case 0x06: /* SCKC D2(B2) [S] */
1113 /* Set Clock Comparator */
1114 check_privileged(s);
1115 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1116 tmp = get_address(s, 0, b2, d2);
1117 potential_page_fault(s);
1118 gen_helper_sckc(cpu_env, tmp);
1119 tcg_temp_free_i64(tmp);
1120 break;
1121 case 0x07: /* STCKC D2(B2) [S] */
1122 /* Store Clock Comparator */
1123 check_privileged(s);
1124 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1125 tmp = get_address(s, 0, b2, d2);
1126 potential_page_fault(s);
1127 gen_helper_stckc(cpu_env, tmp);
1128 tcg_temp_free_i64(tmp);
1129 break;
1130 case 0x08: /* SPT D2(B2) [S] */
1131 /* Set CPU Timer */
1132 check_privileged(s);
1133 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1134 tmp = get_address(s, 0, b2, d2);
1135 potential_page_fault(s);
1136 gen_helper_spt(cpu_env, tmp);
1137 tcg_temp_free_i64(tmp);
1138 break;
1139 case 0x09: /* STPT D2(B2) [S] */
1140 /* Store CPU Timer */
1141 check_privileged(s);
1142 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1143 tmp = get_address(s, 0, b2, d2);
1144 potential_page_fault(s);
1145 gen_helper_stpt(cpu_env, tmp);
1146 tcg_temp_free_i64(tmp);
1147 break;
1148 case 0x0a: /* SPKA D2(B2) [S] */
1149 /* Set PSW Key from Address */
1150 check_privileged(s);
1151 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1152 tmp = get_address(s, 0, b2, d2);
1153 tmp2 = tcg_temp_new_i64();
1154 tcg_gen_andi_i64(tmp2, psw_mask, ~PSW_MASK_KEY);
1155 tcg_gen_shli_i64(tmp, tmp, PSW_SHIFT_KEY - 4);
1156 tcg_gen_or_i64(psw_mask, tmp2, tmp);
1157 tcg_temp_free_i64(tmp2);
1158 tcg_temp_free_i64(tmp);
1159 break;
1160 case 0x0d: /* PTLB [S] */
1161 /* Purge TLB */
1162 check_privileged(s);
1163 gen_helper_ptlb(cpu_env);
1164 break;
1165 case 0x10: /* SPX D2(B2) [S] */
1166 /* Set Prefix Register */
1167 check_privileged(s);
1168 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1169 tmp = get_address(s, 0, b2, d2);
1170 potential_page_fault(s);
1171 gen_helper_spx(cpu_env, tmp);
1172 tcg_temp_free_i64(tmp);
1173 break;
1174 case 0x11: /* STPX D2(B2) [S] */
1175 /* Store Prefix */
1176 check_privileged(s);
1177 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1178 tmp = get_address(s, 0, b2, d2);
1179 tmp2 = tcg_temp_new_i64();
1180 tcg_gen_ld_i64(tmp2, cpu_env, offsetof(CPUS390XState, psa));
1181 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1182 tcg_temp_free_i64(tmp);
1183 tcg_temp_free_i64(tmp2);
1184 break;
1185 case 0x12: /* STAP D2(B2) [S] */
1186 /* Store CPU Address */
1187 check_privileged(s);
1188 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1189 tmp = get_address(s, 0, b2, d2);
1190 tmp2 = tcg_temp_new_i64();
1191 tmp32_1 = tcg_temp_new_i32();
1192 tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, cpu_num));
1193 tcg_gen_extu_i32_i64(tmp2, tmp32_1);
1194 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1195 tcg_temp_free_i64(tmp);
1196 tcg_temp_free_i64(tmp2);
1197 tcg_temp_free_i32(tmp32_1);
1198 break;
1199 case 0x21: /* IPTE R1,R2 [RRE] */
1200 /* Invalidate PTE */
1201 check_privileged(s);
1202 r1 = (insn >> 4) & 0xf;
1203 r2 = insn & 0xf;
1204 tmp = load_reg(r1);
1205 tmp2 = load_reg(r2);
1206 gen_helper_ipte(cpu_env, tmp, tmp2);
1207 tcg_temp_free_i64(tmp);
1208 tcg_temp_free_i64(tmp2);
1209 break;
1210 case 0x29: /* ISKE R1,R2 [RRE] */
1211 /* Insert Storage Key Extended */
1212 check_privileged(s);
1213 r1 = (insn >> 4) & 0xf;
1214 r2 = insn & 0xf;
1215 tmp = load_reg(r2);
1216 tmp2 = tcg_temp_new_i64();
1217 gen_helper_iske(tmp2, cpu_env, tmp);
1218 store_reg(r1, tmp2);
1219 tcg_temp_free_i64(tmp);
1220 tcg_temp_free_i64(tmp2);
1221 break;
1222 case 0x2a: /* RRBE R1,R2 [RRE] */
1223 /* Set Storage Key Extended */
1224 check_privileged(s);
1225 r1 = (insn >> 4) & 0xf;
1226 r2 = insn & 0xf;
1227 tmp32_1 = load_reg32(r1);
1228 tmp = load_reg(r2);
1229 gen_helper_rrbe(cc_op, cpu_env, tmp32_1, tmp);
1230 set_cc_static(s);
1231 tcg_temp_free_i32(tmp32_1);
1232 tcg_temp_free_i64(tmp);
1233 break;
1234 case 0x2b: /* SSKE R1,R2 [RRE] */
1235 /* Set Storage Key Extended */
1236 check_privileged(s);
1237 r1 = (insn >> 4) & 0xf;
1238 r2 = insn & 0xf;
1239 tmp32_1 = load_reg32(r1);
1240 tmp = load_reg(r2);
1241 gen_helper_sske(cpu_env, tmp32_1, tmp);
1242 tcg_temp_free_i32(tmp32_1);
1243 tcg_temp_free_i64(tmp);
1244 break;
1245 case 0x34: /* STCH ? */
1246 /* Store Subchannel */
1247 check_privileged(s);
1248 gen_op_movi_cc(s, 3);
1249 break;
1250 case 0x46: /* STURA R1,R2 [RRE] */
1251 /* Store Using Real Address */
1252 check_privileged(s);
1253 r1 = (insn >> 4) & 0xf;
1254 r2 = insn & 0xf;
1255 tmp32_1 = load_reg32(r1);
1256 tmp = load_reg(r2);
1257 potential_page_fault(s);
1258 gen_helper_stura(cpu_env, tmp, tmp32_1);
1259 tcg_temp_free_i32(tmp32_1);
1260 tcg_temp_free_i64(tmp);
1261 break;
1262 case 0x50: /* CSP R1,R2 [RRE] */
1263 /* Compare And Swap And Purge */
1264 check_privileged(s);
1265 r1 = (insn >> 4) & 0xf;
1266 r2 = insn & 0xf;
1267 tmp32_1 = tcg_const_i32(r1);
1268 tmp32_2 = tcg_const_i32(r2);
1269 gen_helper_csp(cc_op, cpu_env, tmp32_1, tmp32_2);
1270 set_cc_static(s);
1271 tcg_temp_free_i32(tmp32_1);
1272 tcg_temp_free_i32(tmp32_2);
1273 break;
1274 case 0x5f: /* CHSC ? */
1275 /* Channel Subsystem Call */
1276 check_privileged(s);
1277 gen_op_movi_cc(s, 3);
1278 break;
1279 case 0x78: /* STCKE D2(B2) [S] */
1280 /* Store Clock Extended */
1281 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1282 tmp = get_address(s, 0, b2, d2);
1283 potential_page_fault(s);
1284 gen_helper_stcke(cc_op, cpu_env, tmp);
1285 set_cc_static(s);
1286 tcg_temp_free_i64(tmp);
1287 break;
1288 case 0x79: /* SACF D2(B2) [S] */
1289 /* Set Address Space Control Fast */
1290 check_privileged(s);
1291 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1292 tmp = get_address(s, 0, b2, d2);
1293 potential_page_fault(s);
1294 gen_helper_sacf(cpu_env, tmp);
1295 tcg_temp_free_i64(tmp);
1296 /* addressing mode has changed, so end the block */
1297 s->pc = s->next_pc;
1298 update_psw_addr(s);
1299 s->is_jmp = DISAS_JUMP;
1300 break;
1301 case 0x7d: /* STSI D2,(B2) [S] */
1302 check_privileged(s);
1303 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1304 tmp = get_address(s, 0, b2, d2);
1305 tmp32_1 = load_reg32(0);
1306 tmp32_2 = load_reg32(1);
1307 potential_page_fault(s);
1308 gen_helper_stsi(cc_op, cpu_env, tmp, tmp32_1, tmp32_2);
1309 set_cc_static(s);
1310 tcg_temp_free_i64(tmp);
1311 tcg_temp_free_i32(tmp32_1);
1312 tcg_temp_free_i32(tmp32_2);
1313 break;
1314 case 0xb1: /* STFL D2(B2) [S] */
1315 /* Store Facility List (CPU features) at 200 */
1316 check_privileged(s);
1317 tmp2 = tcg_const_i64(0xc0000000);
1318 tmp = tcg_const_i64(200);
1319 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1320 tcg_temp_free_i64(tmp2);
1321 tcg_temp_free_i64(tmp);
1322 break;
1323 case 0xb2: /* LPSWE D2(B2) [S] */
1324 /* Load PSW Extended */
1325 check_privileged(s);
1326 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1327 tmp = get_address(s, 0, b2, d2);
1328 tmp2 = tcg_temp_new_i64();
1329 tmp3 = tcg_temp_new_i64();
1330 tcg_gen_qemu_ld64(tmp2, tmp, get_mem_index(s));
1331 tcg_gen_addi_i64(tmp, tmp, 8);
1332 tcg_gen_qemu_ld64(tmp3, tmp, get_mem_index(s));
1333 gen_helper_load_psw(cpu_env, tmp2, tmp3);
1334 /* we need to keep cc_op intact */
1335 s->is_jmp = DISAS_JUMP;
1336 tcg_temp_free_i64(tmp);
1337 tcg_temp_free_i64(tmp2);
1338 tcg_temp_free_i64(tmp3);
1339 break;
1340 case 0x20: /* SERVC R1,R2 [RRE] */
1341 /* SCLP Service call (PV hypercall) */
1342 check_privileged(s);
1343 potential_page_fault(s);
1344 tmp32_1 = load_reg32(r2);
1345 tmp = load_reg(r1);
1346 gen_helper_servc(cc_op, cpu_env, tmp32_1, tmp);
1347 set_cc_static(s);
1348 tcg_temp_free_i32(tmp32_1);
1349 tcg_temp_free_i64(tmp);
1350 break;
1351 #endif
1352 default:
1353 LOG_DISAS("illegal b2 operation 0x%x\n", op);
1354 gen_illegal_opcode(s);
1355 break;
1356 }
1357 }
1358
1359 static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
1360 {
1361 unsigned char opc;
1362 uint64_t insn;
1363 int op;
1364
1365 opc = cpu_ldub_code(env, s->pc);
1366 LOG_DISAS("opc 0x%x\n", opc);
1367
1368 switch (opc) {
1369 case 0xb2:
1370 insn = ld_code4(env, s->pc);
1371 op = (insn >> 16) & 0xff;
1372 disas_b2(env, s, op, insn);
1373 break;
1374 default:
1375 qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%x\n", opc);
1376 gen_illegal_opcode(s);
1377 break;
1378 }
1379 }
1380
1381 /* ====================================================================== */
1382 /* Define the insn format enumeration. */
1383 #define F0(N) FMT_##N,
1384 #define F1(N, X1) F0(N)
1385 #define F2(N, X1, X2) F0(N)
1386 #define F3(N, X1, X2, X3) F0(N)
1387 #define F4(N, X1, X2, X3, X4) F0(N)
1388 #define F5(N, X1, X2, X3, X4, X5) F0(N)
1389
1390 typedef enum {
1391 #include "insn-format.def"
1392 } DisasFormat;
1393
1394 #undef F0
1395 #undef F1
1396 #undef F2
1397 #undef F3
1398 #undef F4
1399 #undef F5
1400
1401 /* Define a structure to hold the decoded fields. We'll store each inside
1402 an array indexed by an enum. In order to conserve memory, we'll arrange
1403 for fields that do not exist at the same time to overlap, thus the "C"
1404 for compact. For checking purposes there is an "O" for original index
1405 as well that will be applied to availability bitmaps. */
1406
1407 enum DisasFieldIndexO {
1408 FLD_O_r1,
1409 FLD_O_r2,
1410 FLD_O_r3,
1411 FLD_O_m1,
1412 FLD_O_m3,
1413 FLD_O_m4,
1414 FLD_O_b1,
1415 FLD_O_b2,
1416 FLD_O_b4,
1417 FLD_O_d1,
1418 FLD_O_d2,
1419 FLD_O_d4,
1420 FLD_O_x2,
1421 FLD_O_l1,
1422 FLD_O_l2,
1423 FLD_O_i1,
1424 FLD_O_i2,
1425 FLD_O_i3,
1426 FLD_O_i4,
1427 FLD_O_i5
1428 };
1429
1430 enum DisasFieldIndexC {
1431 FLD_C_r1 = 0,
1432 FLD_C_m1 = 0,
1433 FLD_C_b1 = 0,
1434 FLD_C_i1 = 0,
1435
1436 FLD_C_r2 = 1,
1437 FLD_C_b2 = 1,
1438 FLD_C_i2 = 1,
1439
1440 FLD_C_r3 = 2,
1441 FLD_C_m3 = 2,
1442 FLD_C_i3 = 2,
1443
1444 FLD_C_m4 = 3,
1445 FLD_C_b4 = 3,
1446 FLD_C_i4 = 3,
1447 FLD_C_l1 = 3,
1448
1449 FLD_C_i5 = 4,
1450 FLD_C_d1 = 4,
1451
1452 FLD_C_d2 = 5,
1453
1454 FLD_C_d4 = 6,
1455 FLD_C_x2 = 6,
1456 FLD_C_l2 = 6,
1457
1458 NUM_C_FIELD = 7
1459 };
1460
1461 struct DisasFields {
1462 unsigned op:8;
1463 unsigned op2:8;
1464 unsigned presentC:16;
1465 unsigned int presentO;
1466 int c[NUM_C_FIELD];
1467 };
1468
1469 /* This is the way fields are to be accessed out of DisasFields. */
1470 #define have_field(S, F) have_field1((S), FLD_O_##F)
1471 #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
1472
1473 static bool have_field1(const DisasFields *f, enum DisasFieldIndexO c)
1474 {
1475 return (f->presentO >> c) & 1;
1476 }
1477
1478 static int get_field1(const DisasFields *f, enum DisasFieldIndexO o,
1479 enum DisasFieldIndexC c)
1480 {
1481 assert(have_field1(f, o));
1482 return f->c[c];
1483 }
1484
1485 /* Describe the layout of each field in each format. */
1486 typedef struct DisasField {
1487 unsigned int beg:8;
1488 unsigned int size:8;
1489 unsigned int type:2;
1490 unsigned int indexC:6;
1491 enum DisasFieldIndexO indexO:8;
1492 } DisasField;
1493
1494 typedef struct DisasFormatInfo {
1495 DisasField op[NUM_C_FIELD];
1496 } DisasFormatInfo;
1497
1498 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
1499 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
1500 #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1501 { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
1502 #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1503 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1504 { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
1505 #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1506 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1507 #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1508 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1509 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1510 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
1511 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
1512
1513 #define F0(N) { { } },
1514 #define F1(N, X1) { { X1 } },
1515 #define F2(N, X1, X2) { { X1, X2 } },
1516 #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
1517 #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
1518 #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
1519
1520 static const DisasFormatInfo format_info[] = {
1521 #include "insn-format.def"
1522 };
1523
1524 #undef F0
1525 #undef F1
1526 #undef F2
1527 #undef F3
1528 #undef F4
1529 #undef F5
1530 #undef R
1531 #undef M
1532 #undef BD
1533 #undef BXD
1534 #undef BDL
1535 #undef BXDL
1536 #undef I
1537 #undef L
1538
1539 /* Generally, we'll extract operands into this structures, operate upon
1540 them, and store them back. See the "in1", "in2", "prep", "wout" sets
1541 of routines below for more details. */
1542 typedef struct {
1543 bool g_out, g_out2, g_in1, g_in2;
1544 TCGv_i64 out, out2, in1, in2;
1545 TCGv_i64 addr1;
1546 } DisasOps;
1547
1548 /* Return values from translate_one, indicating the state of the TB. */
1549 typedef enum {
1550 /* Continue the TB. */
1551 NO_EXIT,
1552 /* We have emitted one or more goto_tb. No fixup required. */
1553 EXIT_GOTO_TB,
1554 /* We are not using a goto_tb (for whatever reason), but have updated
1555 the PC (for whatever reason), so there's no need to do it again on
1556 exiting the TB. */
1557 EXIT_PC_UPDATED,
1558 /* We are exiting the TB, but have neither emitted a goto_tb, nor
1559 updated the PC for the next instruction to be executed. */
1560 EXIT_PC_STALE,
1561 /* We are ending the TB with a noreturn function call, e.g. longjmp.
1562 No following code will be executed. */
1563 EXIT_NORETURN,
1564 } ExitStatus;
1565
1566 typedef enum DisasFacility {
1567 FAC_Z, /* zarch (default) */
1568 FAC_CASS, /* compare and swap and store */
1569 FAC_CASS2, /* compare and swap and store 2*/
1570 FAC_DFP, /* decimal floating point */
1571 FAC_DFPR, /* decimal floating point rounding */
1572 FAC_DO, /* distinct operands */
1573 FAC_EE, /* execute extensions */
1574 FAC_EI, /* extended immediate */
1575 FAC_FPE, /* floating point extension */
1576 FAC_FPSSH, /* floating point support sign handling */
1577 FAC_FPRGR, /* FPR-GR transfer */
1578 FAC_GIE, /* general instructions extension */
1579 FAC_HFP_MA, /* HFP multiply-and-add/subtract */
1580 FAC_HW, /* high-word */
1581 FAC_IEEEE_SIM, /* IEEE exception sumilation */
1582 FAC_LOC, /* load/store on condition */
1583 FAC_LD, /* long displacement */
1584 FAC_PC, /* population count */
1585 FAC_SCF, /* store clock fast */
1586 FAC_SFLE, /* store facility list extended */
1587 } DisasFacility;
1588
1589 struct DisasInsn {
1590 unsigned opc:16;
1591 DisasFormat fmt:6;
1592 DisasFacility fac:6;
1593
1594 const char *name;
1595
1596 void (*help_in1)(DisasContext *, DisasFields *, DisasOps *);
1597 void (*help_in2)(DisasContext *, DisasFields *, DisasOps *);
1598 void (*help_prep)(DisasContext *, DisasFields *, DisasOps *);
1599 void (*help_wout)(DisasContext *, DisasFields *, DisasOps *);
1600 void (*help_cout)(DisasContext *, DisasOps *);
1601 ExitStatus (*help_op)(DisasContext *, DisasOps *);
1602
1603 uint64_t data;
1604 };
1605
1606 /* ====================================================================== */
1607 /* Miscelaneous helpers, used by several operations. */
1608
1609 static void help_l2_shift(DisasContext *s, DisasFields *f,
1610 DisasOps *o, int mask)
1611 {
1612 int b2 = get_field(f, b2);
1613 int d2 = get_field(f, d2);
1614
1615 if (b2 == 0) {
1616 o->in2 = tcg_const_i64(d2 & mask);
1617 } else {
1618 o->in2 = get_address(s, 0, b2, d2);
1619 tcg_gen_andi_i64(o->in2, o->in2, mask);
1620 }
1621 }
1622
1623 static ExitStatus help_goto_direct(DisasContext *s, uint64_t dest)
1624 {
1625 if (dest == s->next_pc) {
1626 return NO_EXIT;
1627 }
1628 if (use_goto_tb(s, dest)) {
1629 gen_update_cc_op(s);
1630 tcg_gen_goto_tb(0);
1631 tcg_gen_movi_i64(psw_addr, dest);
1632 tcg_gen_exit_tb((tcg_target_long)s->tb);
1633 return EXIT_GOTO_TB;
1634 } else {
1635 tcg_gen_movi_i64(psw_addr, dest);
1636 return EXIT_PC_UPDATED;
1637 }
1638 }
1639
1640 static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
1641 bool is_imm, int imm, TCGv_i64 cdest)
1642 {
1643 ExitStatus ret;
1644 uint64_t dest = s->pc + 2 * imm;
1645 int lab;
1646
1647 /* Take care of the special cases first. */
1648 if (c->cond == TCG_COND_NEVER) {
1649 ret = NO_EXIT;
1650 goto egress;
1651 }
1652 if (is_imm) {
1653 if (dest == s->next_pc) {
1654 /* Branch to next. */
1655 ret = NO_EXIT;
1656 goto egress;
1657 }
1658 if (c->cond == TCG_COND_ALWAYS) {
1659 ret = help_goto_direct(s, dest);
1660 goto egress;
1661 }
1662 } else {
1663 if (TCGV_IS_UNUSED_I64(cdest)) {
1664 /* E.g. bcr %r0 -> no branch. */
1665 ret = NO_EXIT;
1666 goto egress;
1667 }
1668 if (c->cond == TCG_COND_ALWAYS) {
1669 tcg_gen_mov_i64(psw_addr, cdest);
1670 ret = EXIT_PC_UPDATED;
1671 goto egress;
1672 }
1673 }
1674
1675 if (use_goto_tb(s, s->next_pc)) {
1676 if (is_imm && use_goto_tb(s, dest)) {
1677 /* Both exits can use goto_tb. */
1678 gen_update_cc_op(s);
1679
1680 lab = gen_new_label();
1681 if (c->is_64) {
1682 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1683 } else {
1684 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1685 }
1686
1687 /* Branch not taken. */
1688 tcg_gen_goto_tb(0);
1689 tcg_gen_movi_i64(psw_addr, s->next_pc);
1690 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
1691
1692 /* Branch taken. */
1693 gen_set_label(lab);
1694 tcg_gen_goto_tb(1);
1695 tcg_gen_movi_i64(psw_addr, dest);
1696 tcg_gen_exit_tb((tcg_target_long)s->tb + 1);
1697
1698 ret = EXIT_GOTO_TB;
1699 } else {
1700 /* Fallthru can use goto_tb, but taken branch cannot. */
1701 /* Store taken branch destination before the brcond. This
1702 avoids having to allocate a new local temp to hold it.
1703 We'll overwrite this in the not taken case anyway. */
1704 if (!is_imm) {
1705 tcg_gen_mov_i64(psw_addr, cdest);
1706 }
1707
1708 lab = gen_new_label();
1709 if (c->is_64) {
1710 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1711 } else {
1712 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1713 }
1714
1715 /* Branch not taken. */
1716 gen_update_cc_op(s);
1717 tcg_gen_goto_tb(0);
1718 tcg_gen_movi_i64(psw_addr, s->next_pc);
1719 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
1720
1721 gen_set_label(lab);
1722 if (is_imm) {
1723 tcg_gen_movi_i64(psw_addr, dest);
1724 }
1725 ret = EXIT_PC_UPDATED;
1726 }
1727 } else {
1728 /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
1729 Most commonly we're single-stepping or some other condition that
1730 disables all use of goto_tb. Just update the PC and exit. */
1731
1732 TCGv_i64 next = tcg_const_i64(s->next_pc);
1733 if (is_imm) {
1734 cdest = tcg_const_i64(dest);
1735 }
1736
1737 if (c->is_64) {
1738 tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b,
1739 cdest, next);
1740 } else {
1741 TCGv_i32 t0 = tcg_temp_new_i32();
1742 TCGv_i64 t1 = tcg_temp_new_i64();
1743 TCGv_i64 z = tcg_const_i64(0);
1744 tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b);
1745 tcg_gen_extu_i32_i64(t1, t0);
1746 tcg_temp_free_i32(t0);
1747 tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next);
1748 tcg_temp_free_i64(t1);
1749 tcg_temp_free_i64(z);
1750 }
1751
1752 if (is_imm) {
1753 tcg_temp_free_i64(cdest);
1754 }
1755 tcg_temp_free_i64(next);
1756
1757 ret = EXIT_PC_UPDATED;
1758 }
1759
1760 egress:
1761 free_compare(c);
1762 return ret;
1763 }
1764
1765 /* ====================================================================== */
1766 /* The operations. These perform the bulk of the work for any insn,
1767 usually after the operands have been loaded and output initialized. */
1768
1769 static ExitStatus op_abs(DisasContext *s, DisasOps *o)
1770 {
1771 gen_helper_abs_i64(o->out, o->in2);
1772 return NO_EXIT;
1773 }
1774
1775 static ExitStatus op_absf32(DisasContext *s, DisasOps *o)
1776 {
1777 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffull);
1778 return NO_EXIT;
1779 }
1780
1781 static ExitStatus op_absf64(DisasContext *s, DisasOps *o)
1782 {
1783 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull);
1784 return NO_EXIT;
1785 }
1786
1787 static ExitStatus op_absf128(DisasContext *s, DisasOps *o)
1788 {
1789 tcg_gen_andi_i64(o->out, o->in1, 0x7fffffffffffffffull);
1790 tcg_gen_mov_i64(o->out2, o->in2);
1791 return NO_EXIT;
1792 }
1793
1794 static ExitStatus op_add(DisasContext *s, DisasOps *o)
1795 {
1796 tcg_gen_add_i64(o->out, o->in1, o->in2);
1797 return NO_EXIT;
1798 }
1799
1800 static ExitStatus op_addc(DisasContext *s, DisasOps *o)
1801 {
1802 TCGv_i64 cc;
1803
1804 tcg_gen_add_i64(o->out, o->in1, o->in2);
1805
1806 /* XXX possible optimization point */
1807 gen_op_calc_cc(s);
1808 cc = tcg_temp_new_i64();
1809 tcg_gen_extu_i32_i64(cc, cc_op);
1810 tcg_gen_shri_i64(cc, cc, 1);
1811
1812 tcg_gen_add_i64(o->out, o->out, cc);
1813 tcg_temp_free_i64(cc);
1814 return NO_EXIT;
1815 }
1816
1817 static ExitStatus op_aeb(DisasContext *s, DisasOps *o)
1818 {
1819 gen_helper_aeb(o->out, cpu_env, o->in1, o->in2);
1820 return NO_EXIT;
1821 }
1822
1823 static ExitStatus op_adb(DisasContext *s, DisasOps *o)
1824 {
1825 gen_helper_adb(o->out, cpu_env, o->in1, o->in2);
1826 return NO_EXIT;
1827 }
1828
1829 static ExitStatus op_axb(DisasContext *s, DisasOps *o)
1830 {
1831 gen_helper_axb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
1832 return_low128(o->out2);
1833 return NO_EXIT;
1834 }
1835
1836 static ExitStatus op_and(DisasContext *s, DisasOps *o)
1837 {
1838 tcg_gen_and_i64(o->out, o->in1, o->in2);
1839 return NO_EXIT;
1840 }
1841
1842 static ExitStatus op_andi(DisasContext *s, DisasOps *o)
1843 {
1844 int shift = s->insn->data & 0xff;
1845 int size = s->insn->data >> 8;
1846 uint64_t mask = ((1ull << size) - 1) << shift;
1847
1848 assert(!o->g_in2);
1849 tcg_gen_shli_i64(o->in2, o->in2, shift);
1850 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
1851 tcg_gen_and_i64(o->out, o->in1, o->in2);
1852
1853 /* Produce the CC from only the bits manipulated. */
1854 tcg_gen_andi_i64(cc_dst, o->out, mask);
1855 set_cc_nz_u64(s, cc_dst);
1856 return NO_EXIT;
1857 }
1858
1859 static ExitStatus op_bas(DisasContext *s, DisasOps *o)
1860 {
1861 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1862 if (!TCGV_IS_UNUSED_I64(o->in2)) {
1863 tcg_gen_mov_i64(psw_addr, o->in2);
1864 return EXIT_PC_UPDATED;
1865 } else {
1866 return NO_EXIT;
1867 }
1868 }
1869
1870 static ExitStatus op_basi(DisasContext *s, DisasOps *o)
1871 {
1872 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1873 return help_goto_direct(s, s->pc + 2 * get_field(s->fields, i2));
1874 }
1875
1876 static ExitStatus op_bc(DisasContext *s, DisasOps *o)
1877 {
1878 int m1 = get_field(s->fields, m1);
1879 bool is_imm = have_field(s->fields, i2);
1880 int imm = is_imm ? get_field(s->fields, i2) : 0;
1881 DisasCompare c;
1882
1883 disas_jcc(s, &c, m1);
1884 return help_branch(s, &c, is_imm, imm, o->in2);
1885 }
1886
1887 static ExitStatus op_bct32(DisasContext *s, DisasOps *o)
1888 {
1889 int r1 = get_field(s->fields, r1);
1890 bool is_imm = have_field(s->fields, i2);
1891 int imm = is_imm ? get_field(s->fields, i2) : 0;
1892 DisasCompare c;
1893 TCGv_i64 t;
1894
1895 c.cond = TCG_COND_NE;
1896 c.is_64 = false;
1897 c.g1 = false;
1898 c.g2 = false;
1899
1900 t = tcg_temp_new_i64();
1901 tcg_gen_subi_i64(t, regs[r1], 1);
1902 store_reg32_i64(r1, t);
1903 c.u.s32.a = tcg_temp_new_i32();
1904 c.u.s32.b = tcg_const_i32(0);
1905 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
1906 tcg_temp_free_i64(t);
1907
1908 return help_branch(s, &c, is_imm, imm, o->in2);
1909 }
1910
1911 static ExitStatus op_bct64(DisasContext *s, DisasOps *o)
1912 {
1913 int r1 = get_field(s->fields, r1);
1914 bool is_imm = have_field(s->fields, i2);
1915 int imm = is_imm ? get_field(s->fields, i2) : 0;
1916 DisasCompare c;
1917
1918 c.cond = TCG_COND_NE;
1919 c.is_64 = true;
1920 c.g1 = true;
1921 c.g2 = false;
1922
1923 tcg_gen_subi_i64(regs[r1], regs[r1], 1);
1924 c.u.s64.a = regs[r1];
1925 c.u.s64.b = tcg_const_i64(0);
1926
1927 return help_branch(s, &c, is_imm, imm, o->in2);
1928 }
1929
1930 static ExitStatus op_ceb(DisasContext *s, DisasOps *o)
1931 {
1932 gen_helper_ceb(cc_op, cpu_env, o->in1, o->in2);
1933 set_cc_static(s);
1934 return NO_EXIT;
1935 }
1936
1937 static ExitStatus op_cdb(DisasContext *s, DisasOps *o)
1938 {
1939 gen_helper_cdb(cc_op, cpu_env, o->in1, o->in2);
1940 set_cc_static(s);
1941 return NO_EXIT;
1942 }
1943
1944 static ExitStatus op_cxb(DisasContext *s, DisasOps *o)
1945 {
1946 gen_helper_cxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2);
1947 set_cc_static(s);
1948 return NO_EXIT;
1949 }
1950
1951 static ExitStatus op_cfeb(DisasContext *s, DisasOps *o)
1952 {
1953 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1954 gen_helper_cfeb(o->out, cpu_env, o->in2, m3);
1955 tcg_temp_free_i32(m3);
1956 gen_set_cc_nz_f32(s, o->in2);
1957 return NO_EXIT;
1958 }
1959
1960 static ExitStatus op_cfdb(DisasContext *s, DisasOps *o)
1961 {
1962 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1963 gen_helper_cfdb(o->out, cpu_env, o->in2, m3);
1964 tcg_temp_free_i32(m3);
1965 gen_set_cc_nz_f64(s, o->in2);
1966 return NO_EXIT;
1967 }
1968
1969 static ExitStatus op_cfxb(DisasContext *s, DisasOps *o)
1970 {
1971 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1972 gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m3);
1973 tcg_temp_free_i32(m3);
1974 gen_set_cc_nz_f128(s, o->in1, o->in2);
1975 return NO_EXIT;
1976 }
1977
1978 static ExitStatus op_cgeb(DisasContext *s, DisasOps *o)
1979 {
1980 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1981 gen_helper_cgeb(o->out, cpu_env, o->in2, m3);
1982 tcg_temp_free_i32(m3);
1983 gen_set_cc_nz_f32(s, o->in2);
1984 return NO_EXIT;
1985 }
1986
1987 static ExitStatus op_cgdb(DisasContext *s, DisasOps *o)
1988 {
1989 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1990 gen_helper_cgdb(o->out, cpu_env, o->in2, m3);
1991 tcg_temp_free_i32(m3);
1992 gen_set_cc_nz_f64(s, o->in2);
1993 return NO_EXIT;
1994 }
1995
1996 static ExitStatus op_cgxb(DisasContext *s, DisasOps *o)
1997 {
1998 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1999 gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m3);
2000 tcg_temp_free_i32(m3);
2001 gen_set_cc_nz_f128(s, o->in1, o->in2);
2002 return NO_EXIT;
2003 }
2004
2005 static ExitStatus op_cegb(DisasContext *s, DisasOps *o)
2006 {
2007 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
2008 gen_helper_cegb(o->out, cpu_env, o->in2, m3);
2009 tcg_temp_free_i32(m3);
2010 return NO_EXIT;
2011 }
2012
2013 static ExitStatus op_cdgb(DisasContext *s, DisasOps *o)
2014 {
2015 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
2016 gen_helper_cdgb(o->out, cpu_env, o->in2, m3);
2017 tcg_temp_free_i32(m3);
2018 return NO_EXIT;
2019 }
2020
2021 static ExitStatus op_cxgb(DisasContext *s, DisasOps *o)
2022 {
2023 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
2024 gen_helper_cxgb(o->out, cpu_env, o->in2, m3);
2025 tcg_temp_free_i32(m3);
2026 return_low128(o->out2);
2027 return NO_EXIT;
2028 }
2029
2030 static ExitStatus op_cksm(DisasContext *s, DisasOps *o)
2031 {
2032 int r2 = get_field(s->fields, r2);
2033 TCGv_i64 len = tcg_temp_new_i64();
2034
2035 potential_page_fault(s);
2036 gen_helper_cksm(len, cpu_env, o->in1, o->in2, regs[r2 + 1]);
2037 set_cc_static(s);
2038 return_low128(o->out);
2039
2040 tcg_gen_add_i64(regs[r2], regs[r2], len);
2041 tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len);
2042 tcg_temp_free_i64(len);
2043
2044 return NO_EXIT;
2045 }
2046
2047 static ExitStatus op_clc(DisasContext *s, DisasOps *o)
2048 {
2049 int l = get_field(s->fields, l1);
2050 TCGv_i32 vl;
2051
2052 switch (l + 1) {
2053 case 1:
2054 tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s));
2055 tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s));
2056 break;
2057 case 2:
2058 tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s));
2059 tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s));
2060 break;
2061 case 4:
2062 tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s));
2063 tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s));
2064 break;
2065 case 8:
2066 tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s));
2067 tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
2068 break;
2069 default:
2070 potential_page_fault(s);
2071 vl = tcg_const_i32(l);
2072 gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
2073 tcg_temp_free_i32(vl);
2074 set_cc_static(s);
2075 return NO_EXIT;
2076 }
2077 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
2078 return NO_EXIT;
2079 }
2080
2081 static ExitStatus op_clcle(DisasContext *s, DisasOps *o)
2082 {
2083 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2084 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2085 potential_page_fault(s);
2086 gen_helper_clcle(cc_op, cpu_env, r1, o->in2, r3);
2087 tcg_temp_free_i32(r1);
2088 tcg_temp_free_i32(r3);
2089 set_cc_static(s);
2090 return NO_EXIT;
2091 }
2092
2093 static ExitStatus op_clm(DisasContext *s, DisasOps *o)
2094 {
2095 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
2096 TCGv_i32 t1 = tcg_temp_new_i32();
2097 tcg_gen_trunc_i64_i32(t1, o->in1);
2098 potential_page_fault(s);
2099 gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2);
2100 set_cc_static(s);
2101 tcg_temp_free_i32(t1);
2102 tcg_temp_free_i32(m3);
2103 return NO_EXIT;
2104 }
2105
2106 static ExitStatus op_cs(DisasContext *s, DisasOps *o)
2107 {
2108 int r3 = get_field(s->fields, r3);
2109 potential_page_fault(s);
2110 gen_helper_cs(o->out, cpu_env, o->in1, o->in2, regs[r3]);
2111 set_cc_static(s);
2112 return NO_EXIT;
2113 }
2114
2115 static ExitStatus op_csg(DisasContext *s, DisasOps *o)
2116 {
2117 int r3 = get_field(s->fields, r3);
2118 potential_page_fault(s);
2119 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, regs[r3]);
2120 set_cc_static(s);
2121 return NO_EXIT;
2122 }
2123
2124 static ExitStatus op_cds(DisasContext *s, DisasOps *o)
2125 {
2126 int r3 = get_field(s->fields, r3);
2127 TCGv_i64 in3 = tcg_temp_new_i64();
2128 tcg_gen_deposit_i64(in3, regs[r3 + 1], regs[r3], 32, 32);
2129 potential_page_fault(s);
2130 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, in3);
2131 tcg_temp_free_i64(in3);
2132 set_cc_static(s);
2133 return NO_EXIT;
2134 }
2135
2136 static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
2137 {
2138 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2139 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2140 potential_page_fault(s);
2141 /* XXX rewrite in tcg */
2142 gen_helper_cdsg(cc_op, cpu_env, r1, o->in2, r3);
2143 set_cc_static(s);
2144 return NO_EXIT;
2145 }
2146
2147 static ExitStatus op_cvd(DisasContext *s, DisasOps *o)
2148 {
2149 TCGv_i64 t1 = tcg_temp_new_i64();
2150 TCGv_i32 t2 = tcg_temp_new_i32();
2151 tcg_gen_trunc_i64_i32(t2, o->in1);
2152 gen_helper_cvd(t1, t2);
2153 tcg_temp_free_i32(t2);
2154 tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
2155 tcg_temp_free_i64(t1);
2156 return NO_EXIT;
2157 }
2158
2159 #ifndef CONFIG_USER_ONLY
2160 static ExitStatus op_diag(DisasContext *s, DisasOps *o)
2161 {
2162 TCGv_i32 tmp;
2163
2164 check_privileged(s);
2165 potential_page_fault(s);
2166
2167 /* We pretend the format is RX_a so that D2 is the field we want. */
2168 tmp = tcg_const_i32(get_field(s->fields, d2) & 0xfff);
2169 gen_helper_diag(regs[2], cpu_env, tmp, regs[2], regs[1]);
2170 tcg_temp_free_i32(tmp);
2171 return NO_EXIT;
2172 }
2173 #endif
2174
2175 static ExitStatus op_divs32(DisasContext *s, DisasOps *o)
2176 {
2177 gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2);
2178 return_low128(o->out);
2179 return NO_EXIT;
2180 }
2181
2182 static ExitStatus op_divu32(DisasContext *s, DisasOps *o)
2183 {
2184 gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2);
2185 return_low128(o->out);
2186 return NO_EXIT;
2187 }
2188
2189 static ExitStatus op_divs64(DisasContext *s, DisasOps *o)
2190 {
2191 gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2);
2192 return_low128(o->out);
2193 return NO_EXIT;
2194 }
2195
2196 static ExitStatus op_divu64(DisasContext *s, DisasOps *o)
2197 {
2198 gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2);
2199 return_low128(o->out);
2200 return NO_EXIT;
2201 }
2202
2203 static ExitStatus op_deb(DisasContext *s, DisasOps *o)
2204 {
2205 gen_helper_deb(o->out, cpu_env, o->in1, o->in2);
2206 return NO_EXIT;
2207 }
2208
2209 static ExitStatus op_ddb(DisasContext *s, DisasOps *o)
2210 {
2211 gen_helper_ddb(o->out, cpu_env, o->in1, o->in2);
2212 return NO_EXIT;
2213 }
2214
2215 static ExitStatus op_dxb(DisasContext *s, DisasOps *o)
2216 {
2217 gen_helper_dxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2218 return_low128(o->out2);
2219 return NO_EXIT;
2220 }
2221
2222 static ExitStatus op_ear(DisasContext *s, DisasOps *o)
2223 {
2224 int r2 = get_field(s->fields, r2);
2225 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, aregs[r2]));
2226 return NO_EXIT;
2227 }
2228
2229 static ExitStatus op_efpc(DisasContext *s, DisasOps *o)
2230 {
2231 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, fpc));
2232 return NO_EXIT;
2233 }
2234
2235 static ExitStatus op_ex(DisasContext *s, DisasOps *o)
2236 {
2237 /* ??? Perhaps a better way to implement EXECUTE is to set a bit in
2238 tb->flags, (ab)use the tb->cs_base field as the address of
2239 the template in memory, and grab 8 bits of tb->flags/cflags for
2240 the contents of the register. We would then recognize all this
2241 in gen_intermediate_code_internal, generating code for exactly
2242 one instruction. This new TB then gets executed normally.
2243
2244 On the other hand, this seems to be mostly used for modifying
2245 MVC inside of memcpy, which needs a helper call anyway. So
2246 perhaps this doesn't bear thinking about any further. */
2247
2248 TCGv_i64 tmp;
2249
2250 update_psw_addr(s);
2251 gen_op_calc_cc(s);
2252
2253 tmp = tcg_const_i64(s->next_pc);
2254 gen_helper_ex(cc_op, cpu_env, cc_op, o->in1, o->in2, tmp);
2255 tcg_temp_free_i64(tmp);
2256
2257 set_cc_static(s);
2258 return NO_EXIT;
2259 }
2260
2261 static ExitStatus op_flogr(DisasContext *s, DisasOps *o)
2262 {
2263 /* We'll use the original input for cc computation, since we get to
2264 compare that against 0, which ought to be better than comparing
2265 the real output against 64. It also lets cc_dst be a convenient
2266 temporary during our computation. */
2267 gen_op_update1_cc_i64(s, CC_OP_FLOGR, o->in2);
2268
2269 /* R1 = IN ? CLZ(IN) : 64. */
2270 gen_helper_clz(o->out, o->in2);
2271
2272 /* R1+1 = IN & ~(found bit). Note that we may attempt to shift this
2273 value by 64, which is undefined. But since the shift is 64 iff the
2274 input is zero, we still get the correct result after and'ing. */
2275 tcg_gen_movi_i64(o->out2, 0x8000000000000000ull);
2276 tcg_gen_shr_i64(o->out2, o->out2, o->out);
2277 tcg_gen_andc_i64(o->out2, cc_dst, o->out2);
2278 return NO_EXIT;
2279 }
2280
2281 static ExitStatus op_icm(DisasContext *s, DisasOps *o)
2282 {
2283 int m3 = get_field(s->fields, m3);
2284 int pos, len, base = s->insn->data;
2285 TCGv_i64 tmp = tcg_temp_new_i64();
2286 uint64_t ccm;
2287
2288 switch (m3) {
2289 case 0xf:
2290 /* Effectively a 32-bit load. */
2291 tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
2292 len = 32;
2293 goto one_insert;
2294
2295 case 0xc:
2296 case 0x6:
2297 case 0x3:
2298 /* Effectively a 16-bit load. */
2299 tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
2300 len = 16;
2301 goto one_insert;
2302
2303 case 0x8:
2304 case 0x4:
2305 case 0x2:
2306 case 0x1:
2307 /* Effectively an 8-bit load. */
2308 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2309 len = 8;
2310 goto one_insert;
2311
2312 one_insert:
2313 pos = base + ctz32(m3) * 8;
2314 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len);
2315 ccm = ((1ull << len) - 1) << pos;
2316 break;
2317
2318 default:
2319 /* This is going to be a sequence of loads and inserts. */
2320 pos = base + 32 - 8;
2321 ccm = 0;
2322 while (m3) {
2323 if (m3 & 0x8) {
2324 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2325 tcg_gen_addi_i64(o->in2, o->in2, 1);
2326 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
2327 ccm |= 0xff << pos;
2328 }
2329 m3 = (m3 << 1) & 0xf;
2330 pos -= 8;
2331 }
2332 break;
2333 }
2334
2335 tcg_gen_movi_i64(tmp, ccm);
2336 gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out);
2337 tcg_temp_free_i64(tmp);
2338 return NO_EXIT;
2339 }
2340
2341 static ExitStatus op_insi(DisasContext *s, DisasOps *o)
2342 {
2343 int shift = s->insn->data & 0xff;
2344 int size = s->insn->data >> 8;
2345 tcg_gen_deposit_i64(o->out, o->in1, o->in2, shift, size);
2346 return NO_EXIT;
2347 }
2348
2349 static ExitStatus op_ipm(DisasContext *s, DisasOps *o)
2350 {
2351 TCGv_i64 t1;
2352
2353 gen_op_calc_cc(s);
2354 tcg_gen_andi_i64(o->out, o->out, ~0xff000000ull);
2355
2356 t1 = tcg_temp_new_i64();
2357 tcg_gen_shli_i64(t1, psw_mask, 20);
2358 tcg_gen_shri_i64(t1, t1, 36);
2359 tcg_gen_or_i64(o->out, o->out, t1);
2360
2361 tcg_gen_extu_i32_i64(t1, cc_op);
2362 tcg_gen_shli_i64(t1, t1, 28);
2363 tcg_gen_or_i64(o->out, o->out, t1);
2364 tcg_temp_free_i64(t1);
2365 return NO_EXIT;
2366 }
2367
2368 static ExitStatus op_ldeb(DisasContext *s, DisasOps *o)
2369 {
2370 gen_helper_ldeb(o->out, cpu_env, o->in2);
2371 return NO_EXIT;
2372 }
2373
2374 static ExitStatus op_ledb(DisasContext *s, DisasOps *o)
2375 {
2376 gen_helper_ledb(o->out, cpu_env, o->in2);
2377 return NO_EXIT;
2378 }
2379
2380 static ExitStatus op_ldxb(DisasContext *s, DisasOps *o)
2381 {
2382 gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2);
2383 return NO_EXIT;
2384 }
2385
2386 static ExitStatus op_lexb(DisasContext *s, DisasOps *o)
2387 {
2388 gen_helper_lexb(o->out, cpu_env, o->in1, o->in2);
2389 return NO_EXIT;
2390 }
2391
2392 static ExitStatus op_lxdb(DisasContext *s, DisasOps *o)
2393 {
2394 gen_helper_lxdb(o->out, cpu_env, o->in2);
2395 return_low128(o->out2);
2396 return NO_EXIT;
2397 }
2398
2399 static ExitStatus op_lxeb(DisasContext *s, DisasOps *o)
2400 {
2401 gen_helper_lxeb(o->out, cpu_env, o->in2);
2402 return_low128(o->out2);
2403 return NO_EXIT;
2404 }
2405
2406 static ExitStatus op_llgt(DisasContext *s, DisasOps *o)
2407 {
2408 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffff);
2409 return NO_EXIT;
2410 }
2411
2412 static ExitStatus op_ld8s(DisasContext *s, DisasOps *o)
2413 {
2414 tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
2415 return NO_EXIT;
2416 }
2417
2418 static ExitStatus op_ld8u(DisasContext *s, DisasOps *o)
2419 {
2420 tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
2421 return NO_EXIT;
2422 }
2423
2424 static ExitStatus op_ld16s(DisasContext *s, DisasOps *o)
2425 {
2426 tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
2427 return NO_EXIT;
2428 }
2429
2430 static ExitStatus op_ld16u(DisasContext *s, DisasOps *o)
2431 {
2432 tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
2433 return NO_EXIT;
2434 }
2435
2436 static ExitStatus op_ld32s(DisasContext *s, DisasOps *o)
2437 {
2438 tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s));
2439 return NO_EXIT;
2440 }
2441
2442 static ExitStatus op_ld32u(DisasContext *s, DisasOps *o)
2443 {
2444 tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
2445 return NO_EXIT;
2446 }
2447
2448 static ExitStatus op_ld64(DisasContext *s, DisasOps *o)
2449 {
2450 tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
2451 return NO_EXIT;
2452 }
2453
2454 #ifndef CONFIG_USER_ONLY
2455 static ExitStatus op_lctl(DisasContext *s, DisasOps *o)
2456 {
2457 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2458 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2459 check_privileged(s);
2460 potential_page_fault(s);
2461 gen_helper_lctl(cpu_env, r1, o->in2, r3);
2462 tcg_temp_free_i32(r1);
2463 tcg_temp_free_i32(r3);
2464 return NO_EXIT;
2465 }
2466
2467 static ExitStatus op_lctlg(DisasContext *s, DisasOps *o)
2468 {
2469 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2470 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2471 check_privileged(s);
2472 potential_page_fault(s);
2473 gen_helper_lctlg(cpu_env, r1, o->in2, r3);
2474 tcg_temp_free_i32(r1);
2475 tcg_temp_free_i32(r3);
2476 return NO_EXIT;
2477 }
2478 static ExitStatus op_lra(DisasContext *s, DisasOps *o)
2479 {
2480 check_privileged(s);
2481 potential_page_fault(s);
2482 gen_helper_lra(o->out, cpu_env, o->in2);
2483 set_cc_static(s);
2484 return NO_EXIT;
2485 }
2486
2487 static ExitStatus op_lpsw(DisasContext *s, DisasOps *o)
2488 {
2489 TCGv_i64 t1, t2;
2490
2491 check_privileged(s);
2492
2493 t1 = tcg_temp_new_i64();
2494 t2 = tcg_temp_new_i64();
2495 tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
2496 tcg_gen_addi_i64(o->in2, o->in2, 4);
2497 tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s));
2498 /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
2499 tcg_gen_shli_i64(t1, t1, 32);
2500 gen_helper_load_psw(cpu_env, t1, t2);
2501 tcg_temp_free_i64(t1);
2502 tcg_temp_free_i64(t2);
2503 return EXIT_NORETURN;
2504 }
2505 #endif
2506
2507 static ExitStatus op_lam(DisasContext *s, DisasOps *o)
2508 {
2509 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2510 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2511 potential_page_fault(s);
2512 gen_helper_lam(cpu_env, r1, o->in2, r3);
2513 tcg_temp_free_i32(r1);
2514 tcg_temp_free_i32(r3);
2515 return NO_EXIT;
2516 }
2517
2518 static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
2519 {
2520 int r1 = get_field(s->fields, r1);
2521 int r3 = get_field(s->fields, r3);
2522 TCGv_i64 t = tcg_temp_new_i64();
2523 TCGv_i64 t4 = tcg_const_i64(4);
2524
2525 while (1) {
2526 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2527 store_reg32_i64(r1, t);
2528 if (r1 == r3) {
2529 break;
2530 }
2531 tcg_gen_add_i64(o->in2, o->in2, t4);
2532 r1 = (r1 + 1) & 15;
2533 }
2534
2535 tcg_temp_free_i64(t);
2536 tcg_temp_free_i64(t4);
2537 return NO_EXIT;
2538 }
2539
2540 static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
2541 {
2542 int r1 = get_field(s->fields, r1);
2543 int r3 = get_field(s->fields, r3);
2544 TCGv_i64 t = tcg_temp_new_i64();
2545 TCGv_i64 t4 = tcg_const_i64(4);
2546
2547 while (1) {
2548 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2549 store_reg32h_i64(r1, t);
2550 if (r1 == r3) {
2551 break;
2552 }
2553 tcg_gen_add_i64(o->in2, o->in2, t4);
2554 r1 = (r1 + 1) & 15;
2555 }
2556
2557 tcg_temp_free_i64(t);
2558 tcg_temp_free_i64(t4);
2559 return NO_EXIT;
2560 }
2561
2562 static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
2563 {
2564 int r1 = get_field(s->fields, r1);
2565 int r3 = get_field(s->fields, r3);
2566 TCGv_i64 t8 = tcg_const_i64(8);
2567
2568 while (1) {
2569 tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
2570 if (r1 == r3) {
2571 break;
2572 }
2573 tcg_gen_add_i64(o->in2, o->in2, t8);
2574 r1 = (r1 + 1) & 15;
2575 }
2576
2577 tcg_temp_free_i64(t8);
2578 return NO_EXIT;
2579 }
2580
2581 static ExitStatus op_mov2(DisasContext *s, DisasOps *o)
2582 {
2583 o->out = o->in2;
2584 o->g_out = o->g_in2;
2585 TCGV_UNUSED_I64(o->in2);
2586 o->g_in2 = false;
2587 return NO_EXIT;
2588 }
2589
2590 static ExitStatus op_movx(DisasContext *s, DisasOps *o)
2591 {
2592 o->out = o->in1;
2593 o->out2 = o->in2;
2594 o->g_out = o->g_in1;
2595 o->g_out2 = o->g_in2;
2596 TCGV_UNUSED_I64(o->in1);
2597 TCGV_UNUSED_I64(o->in2);
2598 o->g_in1 = o->g_in2 = false;
2599 return NO_EXIT;
2600 }
2601
2602 static ExitStatus op_mvc(DisasContext *s, DisasOps *o)
2603 {
2604 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2605 potential_page_fault(s);
2606 gen_helper_mvc(cpu_env, l, o->addr1, o->in2);
2607 tcg_temp_free_i32(l);
2608 return NO_EXIT;
2609 }
2610
2611 static ExitStatus op_mvcl(DisasContext *s, DisasOps *o)
2612 {
2613 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2614 TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
2615 potential_page_fault(s);
2616 gen_helper_mvcl(cc_op, cpu_env, r1, r2);
2617 tcg_temp_free_i32(r1);
2618 tcg_temp_free_i32(r2);
2619 set_cc_static(s);
2620 return NO_EXIT;
2621 }
2622
2623 static ExitStatus op_mvcle(DisasContext *s, DisasOps *o)
2624 {
2625 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2626 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2627 potential_page_fault(s);
2628 gen_helper_mvcle(cc_op, cpu_env, r1, o->in2, r3);
2629 tcg_temp_free_i32(r1);
2630 tcg_temp_free_i32(r3);
2631 set_cc_static(s);
2632 return NO_EXIT;
2633 }
2634
2635 #ifndef CONFIG_USER_ONLY
2636 static ExitStatus op_mvcp(DisasContext *s, DisasOps *o)
2637 {
2638 int r1 = get_field(s->fields, l1);
2639 check_privileged(s);
2640 potential_page_fault(s);
2641 gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2642 set_cc_static(s);
2643 return NO_EXIT;
2644 }
2645
2646 static ExitStatus op_mvcs(DisasContext *s, DisasOps *o)
2647 {
2648 int r1 = get_field(s->fields, l1);
2649 check_privileged(s);
2650 potential_page_fault(s);
2651 gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2652 set_cc_static(s);
2653 return NO_EXIT;
2654 }
2655 #endif
2656
2657 static ExitStatus op_mul(DisasContext *s, DisasOps *o)
2658 {
2659 tcg_gen_mul_i64(o->out, o->in1, o->in2);
2660 return NO_EXIT;
2661 }
2662
2663 static ExitStatus op_mul128(DisasContext *s, DisasOps *o)
2664 {
2665 gen_helper_mul128(o->out, cpu_env, o->in1, o->in2);
2666 return_low128(o->out2);
2667 return NO_EXIT;
2668 }
2669
2670 static ExitStatus op_meeb(DisasContext *s, DisasOps *o)
2671 {
2672 gen_helper_meeb(o->out, cpu_env, o->in1, o->in2);
2673 return NO_EXIT;
2674 }
2675
2676 static ExitStatus op_mdeb(DisasContext *s, DisasOps *o)
2677 {
2678 gen_helper_mdeb(o->out, cpu_env, o->in1, o->in2);
2679 return NO_EXIT;
2680 }
2681
2682 static ExitStatus op_mdb(DisasContext *s, DisasOps *o)
2683 {
2684 gen_helper_mdb(o->out, cpu_env, o->in1, o->in2);
2685 return NO_EXIT;
2686 }
2687
2688 static ExitStatus op_mxb(DisasContext *s, DisasOps *o)
2689 {
2690 gen_helper_mxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2691 return_low128(o->out2);
2692 return NO_EXIT;
2693 }
2694
2695 static ExitStatus op_mxdb(DisasContext *s, DisasOps *o)
2696 {
2697 gen_helper_mxdb(o->out, cpu_env, o->out, o->out2, o->in2);
2698 return_low128(o->out2);
2699 return NO_EXIT;
2700 }
2701
2702 static ExitStatus op_maeb(DisasContext *s, DisasOps *o)
2703 {
2704 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2705 gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3);
2706 tcg_temp_free_i64(r3);
2707 return NO_EXIT;
2708 }
2709
2710 static ExitStatus op_madb(DisasContext *s, DisasOps *o)
2711 {
2712 int r3 = get_field(s->fields, r3);
2713 gen_helper_madb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2714 return NO_EXIT;
2715 }
2716
2717 static ExitStatus op_mseb(DisasContext *s, DisasOps *o)
2718 {
2719 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2720 gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3);
2721 tcg_temp_free_i64(r3);
2722 return NO_EXIT;
2723 }
2724
2725 static ExitStatus op_msdb(DisasContext *s, DisasOps *o)
2726 {
2727 int r3 = get_field(s->fields, r3);
2728 gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2729 return NO_EXIT;
2730 }
2731
2732 static ExitStatus op_nabs(DisasContext *s, DisasOps *o)
2733 {
2734 gen_helper_nabs_i64(o->out, o->in2);
2735 return NO_EXIT;
2736 }
2737
2738 static ExitStatus op_nabsf32(DisasContext *s, DisasOps *o)
2739 {
2740 tcg_gen_ori_i64(o->out, o->in2, 0x80000000ull);
2741 return NO_EXIT;
2742 }
2743
2744 static ExitStatus op_nabsf64(DisasContext *s, DisasOps *o)
2745 {
2746 tcg_gen_ori_i64(o->out, o->in2, 0x8000000000000000ull);
2747 return NO_EXIT;
2748 }
2749
2750 static ExitStatus op_nabsf128(DisasContext *s, DisasOps *o)
2751 {
2752 tcg_gen_ori_i64(o->out, o->in1, 0x8000000000000000ull);
2753 tcg_gen_mov_i64(o->out2, o->in2);
2754 return NO_EXIT;
2755 }
2756
2757 static ExitStatus op_nc(DisasContext *s, DisasOps *o)
2758 {
2759 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2760 potential_page_fault(s);
2761 gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2);
2762 tcg_temp_free_i32(l);
2763 set_cc_static(s);
2764 return NO_EXIT;
2765 }
2766
2767 static ExitStatus op_neg(DisasContext *s, DisasOps *o)
2768 {
2769 tcg_gen_neg_i64(o->out, o->in2);
2770 return NO_EXIT;
2771 }
2772
2773 static ExitStatus op_negf32(DisasContext *s, DisasOps *o)
2774 {
2775 tcg_gen_xori_i64(o->out, o->in2, 0x80000000ull);
2776 return NO_EXIT;
2777 }
2778
2779 static ExitStatus op_negf64(DisasContext *s, DisasOps *o)
2780 {
2781 tcg_gen_xori_i64(o->out, o->in2, 0x8000000000000000ull);
2782 return NO_EXIT;
2783 }
2784
2785 static ExitStatus op_negf128(DisasContext *s, DisasOps *o)
2786 {
2787 tcg_gen_xori_i64(o->out, o->in1, 0x8000000000000000ull);
2788 tcg_gen_mov_i64(o->out2, o->in2);
2789 return NO_EXIT;
2790 }
2791
2792 static ExitStatus op_oc(DisasContext *s, DisasOps *o)
2793 {
2794 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2795 potential_page_fault(s);
2796 gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2);
2797 tcg_temp_free_i32(l);
2798 set_cc_static(s);
2799 return NO_EXIT;
2800 }
2801
2802 static ExitStatus op_or(DisasContext *s, DisasOps *o)
2803 {
2804 tcg_gen_or_i64(o->out, o->in1, o->in2);
2805 return NO_EXIT;
2806 }
2807
2808 static ExitStatus op_ori(DisasContext *s, DisasOps *o)
2809 {
2810 int shift = s->insn->data & 0xff;
2811 int size = s->insn->data >> 8;
2812 uint64_t mask = ((1ull << size) - 1) << shift;
2813
2814 assert(!o->g_in2);
2815 tcg_gen_shli_i64(o->in2, o->in2, shift);
2816 tcg_gen_or_i64(o->out, o->in1, o->in2);
2817
2818 /* Produce the CC from only the bits manipulated. */
2819 tcg_gen_andi_i64(cc_dst, o->out, mask);
2820 set_cc_nz_u64(s, cc_dst);
2821 return NO_EXIT;
2822 }
2823
2824 static ExitStatus op_rev16(DisasContext *s, DisasOps *o)
2825 {
2826 tcg_gen_bswap16_i64(o->out, o->in2);
2827 return NO_EXIT;
2828 }
2829
2830 static ExitStatus op_rev32(DisasContext *s, DisasOps *o)
2831 {
2832 tcg_gen_bswap32_i64(o->out, o->in2);
2833 return NO_EXIT;
2834 }
2835
2836 static ExitStatus op_rev64(DisasContext *s, DisasOps *o)
2837 {
2838 tcg_gen_bswap64_i64(o->out, o->in2);
2839 return NO_EXIT;
2840 }
2841
2842 static ExitStatus op_rll32(DisasContext *s, DisasOps *o)
2843 {
2844 TCGv_i32 t1 = tcg_temp_new_i32();
2845 TCGv_i32 t2 = tcg_temp_new_i32();
2846 TCGv_i32 to = tcg_temp_new_i32();
2847 tcg_gen_trunc_i64_i32(t1, o->in1);
2848 tcg_gen_trunc_i64_i32(t2, o->in2);
2849 tcg_gen_rotl_i32(to, t1, t2);
2850 tcg_gen_extu_i32_i64(o->out, to);
2851 tcg_temp_free_i32(t1);
2852 tcg_temp_free_i32(t2);
2853 tcg_temp_free_i32(to);
2854 return NO_EXIT;
2855 }
2856
2857 static ExitStatus op_rll64(DisasContext *s, DisasOps *o)
2858 {
2859 tcg_gen_rotl_i64(o->out, o->in1, o->in2);
2860 return NO_EXIT;
2861 }
2862
2863 static ExitStatus op_sar(DisasContext *s, DisasOps *o)
2864 {
2865 int r1 = get_field(s->fields, r1);
2866 tcg_gen_st32_i64(o->in2, cpu_env, offsetof(CPUS390XState, aregs[r1]));
2867 return NO_EXIT;
2868 }
2869
2870 static ExitStatus op_seb(DisasContext *s, DisasOps *o)
2871 {
2872 gen_helper_seb(o->out, cpu_env, o->in1, o->in2);
2873 return NO_EXIT;
2874 }
2875
2876 static ExitStatus op_sdb(DisasContext *s, DisasOps *o)
2877 {
2878 gen_helper_sdb(o->out, cpu_env, o->in1, o->in2);
2879 return NO_EXIT;
2880 }
2881
2882 static ExitStatus op_sxb(DisasContext *s, DisasOps *o)
2883 {
2884 gen_helper_sxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2885 return_low128(o->out2);
2886 return NO_EXIT;
2887 }
2888
2889 static ExitStatus op_sqeb(DisasContext *s, DisasOps *o)
2890 {
2891 gen_helper_sqeb(o->out, cpu_env, o->in2);
2892 return NO_EXIT;
2893 }
2894
2895 static ExitStatus op_sqdb(DisasContext *s, DisasOps *o)
2896 {
2897 gen_helper_sqdb(o->out, cpu_env, o->in2);
2898 return NO_EXIT;
2899 }
2900
2901 static ExitStatus op_sqxb(DisasContext *s, DisasOps *o)
2902 {
2903 gen_helper_sqxb(o->out, cpu_env, o->in1, o->in2);
2904 return_low128(o->out2);
2905 return NO_EXIT;
2906 }
2907
2908 #ifndef CONFIG_USER_ONLY
2909 static ExitStatus op_sigp(DisasContext *s, DisasOps *o)
2910 {
2911 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2912 check_privileged(s);
2913 potential_page_fault(s);
2914 gen_helper_sigp(cc_op, cpu_env, o->in2, r1, o->in1);
2915 tcg_temp_free_i32(r1);
2916 return NO_EXIT;
2917 }
2918 #endif
2919
2920 static ExitStatus op_sla(DisasContext *s, DisasOps *o)
2921 {
2922 uint64_t sign = 1ull << s->insn->data;
2923 enum cc_op cco = s->insn->data == 31 ? CC_OP_SLA_32 : CC_OP_SLA_64;
2924 gen_op_update2_cc_i64(s, cco, o->in1, o->in2);
2925 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2926 /* The arithmetic left shift is curious in that it does not affect
2927 the sign bit. Copy that over from the source unchanged. */
2928 tcg_gen_andi_i64(o->out, o->out, ~sign);
2929 tcg_gen_andi_i64(o->in1, o->in1, sign);
2930 tcg_gen_or_i64(o->out, o->out, o->in1);
2931 return NO_EXIT;
2932 }
2933
2934 static ExitStatus op_sll(DisasContext *s, DisasOps *o)
2935 {
2936 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2937 return NO_EXIT;
2938 }
2939
2940 static ExitStatus op_sra(DisasContext *s, DisasOps *o)
2941 {
2942 tcg_gen_sar_i64(o->out, o->in1, o->in2);
2943 return NO_EXIT;
2944 }
2945
2946 static ExitStatus op_srl(DisasContext *s, DisasOps *o)
2947 {
2948 tcg_gen_shr_i64(o->out, o->in1, o->in2);
2949 return NO_EXIT;
2950 }
2951
2952 static ExitStatus op_sfpc(DisasContext *s, DisasOps *o)
2953 {
2954 gen_helper_sfpc(cpu_env, o->in2);
2955 return NO_EXIT;
2956 }
2957
2958 #ifndef CONFIG_USER_ONLY
2959 static ExitStatus op_ssm(DisasContext *s, DisasOps *o)
2960 {
2961 check_privileged(s);
2962 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8);
2963 return NO_EXIT;
2964 }
2965
2966 static ExitStatus op_stctg(DisasContext *s, DisasOps *o)
2967 {
2968 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2969 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2970 check_privileged(s);
2971 potential_page_fault(s);
2972 gen_helper_stctg(cpu_env, r1, o->in2, r3);
2973 tcg_temp_free_i32(r1);
2974 tcg_temp_free_i32(r3);
2975 return NO_EXIT;
2976 }
2977
2978 static ExitStatus op_stctl(DisasContext *s, DisasOps *o)
2979 {
2980 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2981 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2982 check_privileged(s);
2983 potential_page_fault(s);
2984 gen_helper_stctl(cpu_env, r1, o->in2, r3);
2985 tcg_temp_free_i32(r1);
2986 tcg_temp_free_i32(r3);
2987 return NO_EXIT;
2988 }
2989
2990 static ExitStatus op_stnosm(DisasContext *s, DisasOps *o)
2991 {
2992 uint64_t i2 = get_field(s->fields, i2);
2993 TCGv_i64 t;
2994
2995 check_privileged(s);
2996
2997 /* It is important to do what the instruction name says: STORE THEN.
2998 If we let the output hook perform the store then if we fault and
2999 restart, we'll have the wrong SYSTEM MASK in place. */
3000 t = tcg_temp_new_i64();
3001 tcg_gen_shri_i64(t, psw_mask, 56);
3002 tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
3003 tcg_temp_free_i64(t);
3004
3005 if (s->fields->op == 0xac) {
3006 tcg_gen_andi_i64(psw_mask, psw_mask,
3007 (i2 << 56) | 0x00ffffffffffffffull);
3008 } else {
3009 tcg_gen_ori_i64(psw_mask, psw_mask, i2 << 56);
3010 }
3011 return NO_EXIT;
3012 }
3013 #endif
3014
3015 static ExitStatus op_st8(DisasContext *s, DisasOps *o)
3016 {
3017 tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
3018 return NO_EXIT;
3019 }
3020
3021 static ExitStatus op_st16(DisasContext *s, DisasOps *o)
3022 {
3023 tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
3024 return NO_EXIT;
3025 }
3026
3027 static ExitStatus op_st32(DisasContext *s, DisasOps *o)
3028 {
3029 tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s));
3030 return NO_EXIT;
3031 }
3032
3033 static ExitStatus op_st64(DisasContext *s, DisasOps *o)
3034 {
3035 tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
3036 return NO_EXIT;
3037 }
3038
3039 static ExitStatus op_stam(DisasContext *s, DisasOps *o)
3040 {
3041 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3042 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
3043 potential_page_fault(s);
3044 gen_helper_stam(cpu_env, r1, o->in2, r3);
3045 tcg_temp_free_i32(r1);
3046 tcg_temp_free_i32(r3);
3047 return NO_EXIT;
3048 }
3049
3050 static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
3051 {
3052 int m3 = get_field(s->fields, m3);
3053 int pos, base = s->insn->data;
3054 TCGv_i64 tmp = tcg_temp_new_i64();
3055
3056 pos = base + ctz32(m3) * 8;
3057 switch (m3) {
3058 case 0xf:
3059 /* Effectively a 32-bit store. */
3060 tcg_gen_shri_i64(tmp, o->in1, pos);
3061 tcg_gen_qemu_st32(tmp, o->in2, get_mem_index(s));
3062 break;
3063
3064 case 0xc:
3065 case 0x6:
3066 case 0x3:
3067 /* Effectively a 16-bit store. */
3068 tcg_gen_shri_i64(tmp, o->in1, pos);
3069 tcg_gen_qemu_st16(tmp, o->in2, get_mem_index(s));
3070 break;
3071
3072 case 0x8:
3073 case 0x4:
3074 case 0x2:
3075 case 0x1:
3076 /* Effectively an 8-bit store. */
3077 tcg_gen_shri_i64(tmp, o->in1, pos);
3078 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3079 break;
3080
3081 default:
3082 /* This is going to be a sequence of shifts and stores. */
3083 pos = base + 32 - 8;
3084 while (m3) {
3085 if (m3 & 0x8) {
3086 tcg_gen_shri_i64(tmp, o->in1, pos);
3087 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3088 tcg_gen_addi_i64(o->in2, o->in2, 1);
3089 }
3090 m3 = (m3 << 1) & 0xf;
3091 pos -= 8;
3092 }
3093 break;
3094 }
3095 tcg_temp_free_i64(tmp);
3096 return NO_EXIT;
3097 }
3098
3099 static ExitStatus op_stm(DisasContext *s, DisasOps *o)
3100 {
3101 int r1 = get_field(s->fields, r1);
3102 int r3 = get_field(s->fields, r3);
3103 int size = s->insn->data;
3104 TCGv_i64 tsize = tcg_const_i64(size);
3105
3106 while (1) {
3107 if (size == 8) {
3108 tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
3109 } else {
3110 tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s));
3111 }
3112 if (r1 == r3) {
3113 break;
3114 }
3115 tcg_gen_add_i64(o->in2, o->in2, tsize);
3116 r1 = (r1 + 1) & 15;
3117 }
3118
3119 tcg_temp_free_i64(tsize);
3120 return NO_EXIT;
3121 }
3122
3123 static ExitStatus op_stmh(DisasContext *s, DisasOps *o)
3124 {
3125 int r1 = get_field(s->fields, r1);
3126 int r3 = get_field(s->fields, r3);
3127 TCGv_i64 t = tcg_temp_new_i64();
3128 TCGv_i64 t4 = tcg_const_i64(4);
3129 TCGv_i64 t32 = tcg_const_i64(32);
3130
3131 while (1) {
3132 tcg_gen_shl_i64(t, regs[r1], t32);
3133 tcg_gen_qemu_st32(t, o->in2, get_mem_index(s));
3134 if (r1 == r3) {
3135 break;
3136 }
3137 tcg_gen_add_i64(o->in2, o->in2, t4);
3138 r1 = (r1 + 1) & 15;
3139 }
3140
3141 tcg_temp_free_i64(t);
3142 tcg_temp_free_i64(t4);
3143 tcg_temp_free_i64(t32);
3144 return NO_EXIT;
3145 }
3146
3147 static ExitStatus op_sub(DisasContext *s, DisasOps *o)
3148 {
3149 tcg_gen_sub_i64(o->out, o->in1, o->in2);
3150 return NO_EXIT;
3151 }
3152
3153 static ExitStatus op_subb(DisasContext *s, DisasOps *o)
3154 {
3155 TCGv_i64 cc;
3156
3157 assert(!o->g_in2);
3158 tcg_gen_not_i64(o->in2, o->in2);
3159 tcg_gen_add_i64(o->out, o->in1, o->in2);
3160
3161 /* XXX possible optimization point */
3162 gen_op_calc_cc(s);
3163 cc = tcg_temp_new_i64();
3164 tcg_gen_extu_i32_i64(cc, cc_op);
3165 tcg_gen_shri_i64(cc, cc, 1);
3166 tcg_gen_add_i64(o->out, o->out, cc);
3167 tcg_temp_free_i64(cc);
3168 return NO_EXIT;
3169 }
3170
3171 static ExitStatus op_svc(DisasContext *s, DisasOps *o)
3172 {
3173 TCGv_i32 t;
3174
3175 update_psw_addr(s);
3176 gen_op_calc_cc(s);
3177
3178 t = tcg_const_i32(get_field(s->fields, i1) & 0xff);
3179 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code));
3180 tcg_temp_free_i32(t);
3181
3182 t = tcg_const_i32(s->next_pc - s->pc);
3183 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen));
3184 tcg_temp_free_i32(t);
3185
3186 gen_exception(EXCP_SVC);
3187 return EXIT_NORETURN;
3188 }
3189
3190 static ExitStatus op_tceb(DisasContext *s, DisasOps *o)
3191 {
3192 gen_helper_tceb(cc_op, o->in1, o->in2);
3193 set_cc_static(s);
3194 return NO_EXIT;
3195 }
3196
3197 static ExitStatus op_tcdb(DisasContext *s, DisasOps *o)
3198 {
3199 gen_helper_tcdb(cc_op, o->in1, o->in2);
3200 set_cc_static(s);
3201 return NO_EXIT;
3202 }
3203
3204 static ExitStatus op_tcxb(DisasContext *s, DisasOps *o)
3205 {
3206 gen_helper_tcxb(cc_op, o->out, o->out2, o->in2);
3207 set_cc_static(s);
3208 return NO_EXIT;
3209 }
3210
3211 #ifndef CONFIG_USER_ONLY
3212 static ExitStatus op_tprot(DisasContext *s, DisasOps *o)
3213 {
3214 potential_page_fault(s);
3215 gen_helper_tprot(cc_op, o->addr1, o->in2);
3216 set_cc_static(s);
3217 return NO_EXIT;
3218 }
3219 #endif
3220
3221 static ExitStatus op_tr(DisasContext *s, DisasOps *o)
3222 {
3223 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3224 potential_page_fault(s);
3225 gen_helper_tr(cpu_env, l, o->addr1, o->in2);
3226 tcg_temp_free_i32(l);
3227 set_cc_static(s);
3228 return NO_EXIT;
3229 }
3230
3231 static ExitStatus op_unpk(DisasContext *s, DisasOps *o)
3232 {
3233 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3234 potential_page_fault(s);
3235 gen_helper_unpk(cpu_env, l, o->addr1, o->in2);
3236 tcg_temp_free_i32(l);
3237 return NO_EXIT;
3238 }
3239
3240 static ExitStatus op_xc(DisasContext *s, DisasOps *o)
3241 {
3242 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3243 potential_page_fault(s);
3244 gen_helper_xc(cc_op, cpu_env, l, o->addr1, o->in2);
3245 tcg_temp_free_i32(l);
3246 set_cc_static(s);
3247 return NO_EXIT;
3248 }
3249
3250 static ExitStatus op_xor(DisasContext *s, DisasOps *o)
3251 {
3252 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3253 return NO_EXIT;
3254 }
3255
3256 static ExitStatus op_xori(DisasContext *s, DisasOps *o)
3257 {
3258 int shift = s->insn->data & 0xff;
3259 int size = s->insn->data >> 8;
3260 uint64_t mask = ((1ull << size) - 1) << shift;
3261
3262 assert(!o->g_in2);
3263 tcg_gen_shli_i64(o->in2, o->in2, shift);
3264 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3265
3266 /* Produce the CC from only the bits manipulated. */
3267 tcg_gen_andi_i64(cc_dst, o->out, mask);
3268 set_cc_nz_u64(s, cc_dst);
3269 return NO_EXIT;
3270 }
3271
3272 static ExitStatus op_zero(DisasContext *s, DisasOps *o)
3273 {
3274 o->out = tcg_const_i64(0);
3275 return NO_EXIT;
3276 }
3277
3278 static ExitStatus op_zero2(DisasContext *s, DisasOps *o)
3279 {
3280 o->out = tcg_const_i64(0);
3281 o->out2 = o->out;
3282 o->g_out2 = true;
3283 return NO_EXIT;
3284 }
3285
3286 /* ====================================================================== */
3287 /* The "Cc OUTput" generators. Given the generated output (and in some cases
3288 the original inputs), update the various cc data structures in order to
3289 be able to compute the new condition code. */
3290
3291 static void cout_abs32(DisasContext *s, DisasOps *o)
3292 {
3293 gen_op_update1_cc_i64(s, CC_OP_ABS_32, o->out);
3294 }
3295
3296 static void cout_abs64(DisasContext *s, DisasOps *o)
3297 {
3298 gen_op_update1_cc_i64(s, CC_OP_ABS_64, o->out);
3299 }
3300
3301 static void cout_adds32(DisasContext *s, DisasOps *o)
3302 {
3303 gen_op_update3_cc_i64(s, CC_OP_ADD_32, o->in1, o->in2, o->out);
3304 }
3305
3306 static void cout_adds64(DisasContext *s, DisasOps *o)
3307 {
3308 gen_op_update3_cc_i64(s, CC_OP_ADD_64, o->in1, o->in2, o->out);
3309 }
3310
3311 static void cout_addu32(DisasContext *s, DisasOps *o)
3312 {
3313 gen_op_update3_cc_i64(s, CC_OP_ADDU_32, o->in1, o->in2, o->out);
3314 }
3315
3316 static void cout_addu64(DisasContext *s, DisasOps *o)
3317 {
3318 gen_op_update3_cc_i64(s, CC_OP_ADDU_64, o->in1, o->in2, o->out);
3319 }
3320
3321 static void cout_addc32(DisasContext *s, DisasOps *o)
3322 {
3323 gen_op_update3_cc_i64(s, CC_OP_ADDC_32, o->in1, o->in2, o->out);
3324 }
3325
3326 static void cout_addc64(DisasContext *s, DisasOps *o)
3327 {
3328 gen_op_update3_cc_i64(s, CC_OP_ADDC_64, o->in1, o->in2, o->out);
3329 }
3330
3331 static void cout_cmps32(DisasContext *s, DisasOps *o)
3332 {
3333 gen_op_update2_cc_i64(s, CC_OP_LTGT_32, o->in1, o->in2);
3334 }
3335
3336 static void cout_cmps64(DisasContext *s, DisasOps *o)
3337 {
3338 gen_op_update2_cc_i64(s, CC_OP_LTGT_64, o->in1, o->in2);
3339 }
3340
3341 static void cout_cmpu32(DisasContext *s, DisasOps *o)
3342 {
3343 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_32, o->in1, o->in2);
3344 }
3345
3346 static void cout_cmpu64(DisasContext *s, DisasOps *o)
3347 {
3348 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, o->in1, o->in2);
3349 }
3350
3351 static void cout_f32(DisasContext *s, DisasOps *o)
3352 {
3353 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, o->out);
3354 }
3355
3356 static void cout_f64(DisasContext *s, DisasOps *o)
3357 {
3358 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, o->out);
3359 }
3360
3361 static void cout_f128(DisasContext *s, DisasOps *o)
3362 {
3363 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, o->out, o->out2);
3364 }
3365
3366 static void cout_nabs32(DisasContext *s, DisasOps *o)
3367 {
3368 gen_op_update1_cc_i64(s, CC_OP_NABS_32, o->out);
3369 }
3370
3371 static void cout_nabs64(DisasContext *s, DisasOps *o)
3372 {
3373 gen_op_update1_cc_i64(s, CC_OP_NABS_64, o->out);
3374 }
3375
3376 static void cout_neg32(DisasContext *s, DisasOps *o)
3377 {
3378 gen_op_update1_cc_i64(s, CC_OP_COMP_32, o->out);
3379 }
3380
3381 static void cout_neg64(DisasContext *s, DisasOps *o)
3382 {
3383 gen_op_update1_cc_i64(s, CC_OP_COMP_64, o->out);
3384 }
3385
3386 static void cout_nz32(DisasContext *s, DisasOps *o)
3387 {
3388 tcg_gen_ext32u_i64(cc_dst, o->out);
3389 gen_op_update1_cc_i64(s, CC_OP_NZ, cc_dst);
3390 }
3391
3392 static void cout_nz64(DisasContext *s, DisasOps *o)
3393 {
3394 gen_op_update1_cc_i64(s, CC_OP_NZ, o->out);
3395 }
3396
3397 static void cout_s32(DisasContext *s, DisasOps *o)
3398 {
3399 gen_op_update1_cc_i64(s, CC_OP_LTGT0_32, o->out);
3400 }
3401
3402 static void cout_s64(DisasContext *s, DisasOps *o)
3403 {
3404 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, o->out);
3405 }
3406
3407 static void cout_subs32(DisasContext *s, DisasOps *o)
3408 {
3409 gen_op_update3_cc_i64(s, CC_OP_SUB_32, o->in1, o->in2, o->out);
3410 }
3411
3412 static void cout_subs64(DisasContext *s, DisasOps *o)
3413 {
3414 gen_op_update3_cc_i64(s, CC_OP_SUB_64, o->in1, o->in2, o->out);
3415 }
3416
3417 static void cout_subu32(DisasContext *s, DisasOps *o)
3418 {
3419 gen_op_update3_cc_i64(s, CC_OP_SUBU_32, o->in1, o->in2, o->out);
3420 }
3421
3422 static void cout_subu64(DisasContext *s, DisasOps *o)
3423 {
3424 gen_op_update3_cc_i64(s, CC_OP_SUBU_64, o->in1, o->in2, o->out);
3425 }
3426
3427 static void cout_subb32(DisasContext *s, DisasOps *o)
3428 {
3429 gen_op_update3_cc_i64(s, CC_OP_SUBB_32, o->in1, o->in2, o->out);
3430 }
3431
3432 static void cout_subb64(DisasContext *s, DisasOps *o)
3433 {
3434 gen_op_update3_cc_i64(s, CC_OP_SUBB_64, o->in1, o->in2, o->out);
3435 }
3436
3437 static void cout_tm32(DisasContext *s, DisasOps *o)
3438 {
3439 gen_op_update2_cc_i64(s, CC_OP_TM_32, o->in1, o->in2);
3440 }
3441
3442 static void cout_tm64(DisasContext *s, DisasOps *o)
3443 {
3444 gen_op_update2_cc_i64(s, CC_OP_TM_64, o->in1, o->in2);
3445 }
3446
3447 /* ====================================================================== */
3448 /* The "PREPeration" generators. These initialize the DisasOps.OUT fields
3449 with the TCG register to which we will write. Used in combination with
3450 the "wout" generators, in some cases we need a new temporary, and in
3451 some cases we can write to a TCG global. */
3452
3453 static void prep_new(DisasContext *s, DisasFields *f, DisasOps *o)
3454 {
3455 o->out = tcg_temp_new_i64();
3456 }
3457
3458 static void prep_new_P(DisasContext *s, DisasFields *f, DisasOps *o)
3459 {
3460 o->out = tcg_temp_new_i64();
3461 o->out2 = tcg_temp_new_i64();
3462 }
3463
3464 static void prep_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3465 {
3466 o->out = regs[get_field(f, r1)];
3467 o->g_out = true;
3468 }
3469
3470 static void prep_r1_P(DisasContext *s, DisasFields *f, DisasOps *o)
3471 {
3472 /* ??? Specification exception: r1 must be even. */
3473 int r1 = get_field(f, r1);
3474 o->out = regs[r1];
3475 o->out2 = regs[(r1 + 1) & 15];
3476 o->g_out = o->g_out2 = true;
3477 }
3478
3479 static void prep_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3480 {
3481 o->out = fregs[get_field(f, r1)];
3482 o->g_out = true;
3483 }
3484
3485 static void prep_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3486 {
3487 /* ??? Specification exception: r1 must be < 14. */
3488 int r1 = get_field(f, r1);
3489 o->out = fregs[r1];
3490 o->out2 = fregs[(r1 + 2) & 15];
3491 o->g_out = o->g_out2 = true;
3492 }
3493
3494 /* ====================================================================== */
3495 /* The "Write OUTput" generators. These generally perform some non-trivial
3496 copy of data to TCG globals, or to main memory. The trivial cases are
3497 generally handled by having a "prep" generator install the TCG global
3498 as the destination of the operation. */
3499
3500 static void wout_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3501 {
3502 store_reg(get_field(f, r1), o->out);
3503 }
3504
3505 static void wout_r1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3506 {
3507 int r1 = get_field(f, r1);
3508 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8);
3509 }
3510
3511 static void wout_r1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3512 {
3513 int r1 = get_field(f, r1);
3514 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 16);
3515 }
3516
3517 static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3518 {
3519 store_reg32_i64(get_field(f, r1), o->out);
3520 }
3521
3522 static void wout_r1_P32(DisasContext *s, DisasFields *f, DisasOps *o)
3523 {
3524 /* ??? Specification exception: r1 must be even. */
3525 int r1 = get_field(f, r1);
3526 store_reg32_i64(r1, o->out);
3527 store_reg32_i64((r1 + 1) & 15, o->out2);
3528 }
3529
3530 static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3531 {
3532 /* ??? Specification exception: r1 must be even. */
3533 int r1 = get_field(f, r1);
3534 store_reg32_i64((r1 + 1) & 15, o->out);
3535 tcg_gen_shri_i64(o->out, o->out, 32);
3536 store_reg32_i64(r1, o->out);
3537 }
3538
3539 static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3540 {
3541 store_freg32_i64(get_field(f, r1), o->out);
3542 }
3543
3544 static void wout_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3545 {
3546 store_freg(get_field(f, r1), o->out);
3547 }
3548
3549 static void wout_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3550 {
3551 /* ??? Specification exception: r1 must be < 14. */
3552 int f1 = get_field(s->fields, r1);
3553 store_freg(f1, o->out);
3554 store_freg((f1 + 2) & 15, o->out2);
3555 }
3556
3557 static void wout_cond_r1r2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3558 {
3559 if (get_field(f, r1) != get_field(f, r2)) {
3560 store_reg32_i64(get_field(f, r1), o->out);
3561 }
3562 }
3563
3564 static void wout_cond_e1e2(DisasContext *s, DisasFields *f, DisasOps *o)
3565 {
3566 if (get_field(f, r1) != get_field(f, r2)) {
3567 store_freg32_i64(get_field(f, r1), o->out);
3568 }
3569 }
3570
3571 static void wout_m1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3572 {
3573 tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s));
3574 }
3575
3576 static void wout_m1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3577 {
3578 tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s));
3579 }
3580
3581 static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3582 {
3583 tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
3584 }
3585
3586 static void wout_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3587 {
3588 tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
3589 }
3590
3591 static void wout_m2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3592 {
3593 tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s));
3594 }
3595
3596 /* ====================================================================== */
3597 /* The "INput 1" generators. These load the first operand to an insn. */
3598
3599 static void in1_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3600 {
3601 o->in1 = load_reg(get_field(f, r1));
3602 }
3603
3604 static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3605 {
3606 o->in1 = regs[get_field(f, r1)];
3607 o->g_in1 = true;
3608 }
3609
3610 static void in1_r1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3611 {
3612 o->in1 = tcg_temp_new_i64();
3613 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r1)]);
3614 }
3615
3616 static void in1_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3617 {
3618 o->in1 = tcg_temp_new_i64();
3619 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r1)]);
3620 }
3621
3622 static void in1_r1_sr32(DisasContext *s, DisasFields *f, DisasOps *o)
3623 {
3624 o->in1 = tcg_temp_new_i64();
3625 tcg_gen_shri_i64(o->in1, regs[get_field(f, r1)], 32);
3626 }
3627
3628 static void in1_r1p1(DisasContext *s, DisasFields *f, DisasOps *o)
3629 {
3630 /* ??? Specification exception: r1 must be even. */
3631 int r1 = get_field(f, r1);
3632 o->in1 = load_reg((r1 + 1) & 15);
3633 }
3634
3635 static void in1_r1p1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3636 {
3637 /* ??? Specification exception: r1 must be even. */
3638 int r1 = get_field(f, r1);
3639 o->in1 = tcg_temp_new_i64();
3640 tcg_gen_ext32s_i64(o->in1, regs[(r1 + 1) & 15]);
3641 }
3642
3643 static void in1_r1p1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3644 {
3645 /* ??? Specification exception: r1 must be even. */
3646 int r1 = get_field(f, r1);
3647 o->in1 = tcg_temp_new_i64();
3648 tcg_gen_ext32u_i64(o->in1, regs[(r1 + 1) & 15]);
3649 }
3650
3651 static void in1_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3652 {
3653 /* ??? Specification exception: r1 must be even. */
3654 int r1 = get_field(f, r1);
3655 o->in1 = tcg_temp_new_i64();
3656 tcg_gen_concat32_i64(o->in1, regs[r1 + 1], regs[r1]);
3657 }
3658
3659 static void in1_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3660 {
3661 o->in1 = load_reg(get_field(f, r2));
3662 }
3663
3664 static void in1_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3665 {
3666 o->in1 = load_reg(get_field(f, r3));
3667 }
3668
3669 static void in1_r3_o(DisasContext *s, DisasFields *f, DisasOps *o)
3670 {
3671 o->in1 = regs[get_field(f, r3)];
3672 o->g_in1 = true;
3673 }
3674
3675 static void in1_r3_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3676 {
3677 o->in1 = tcg_temp_new_i64();
3678 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r3)]);
3679 }
3680
3681 static void in1_r3_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3682 {
3683 o->in1 = tcg_temp_new_i64();
3684 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r3)]);
3685 }
3686
3687 static void in1_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3688 {
3689 o->in1 = load_freg32_i64(get_field(f, r1));
3690 }
3691
3692 static void in1_f1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3693 {
3694 o->in1 = fregs[get_field(f, r1)];
3695 o->g_in1 = true;
3696 }
3697
3698 static void in1_x1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3699 {
3700 /* ??? Specification exception: r1 must be < 14. */
3701 int r1 = get_field(f, r1);
3702 o->out = fregs[r1];
3703 o->out2 = fregs[(r1 + 2) & 15];
3704 o->g_out = o->g_out2 = true;
3705 }
3706
3707 static void in1_la1(DisasContext *s, DisasFields *f, DisasOps *o)
3708 {
3709 o->addr1 = get_address(s, 0, get_field(f, b1), get_field(f, d1));
3710 }
3711
3712 static void in1_la2(DisasContext *s, DisasFields *f, DisasOps *o)
3713 {
3714 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3715 o->addr1 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3716 }
3717
3718 static void in1_m1_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3719 {
3720 in1_la1(s, f, o);
3721 o->in1 = tcg_temp_new_i64();
3722 tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s));
3723 }
3724
3725 static void in1_m1_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3726 {
3727 in1_la1(s, f, o);
3728 o->in1 = tcg_temp_new_i64();
3729 tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s));
3730 }
3731
3732 static void in1_m1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3733 {
3734 in1_la1(s, f, o);
3735 o->in1 = tcg_temp_new_i64();
3736 tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s));
3737 }
3738
3739 static void in1_m1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3740 {
3741 in1_la1(s, f, o);
3742 o->in1 = tcg_temp_new_i64();
3743 tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s));
3744 }
3745
3746 static void in1_m1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3747 {
3748 in1_la1(s, f, o);
3749 o->in1 = tcg_temp_new_i64();
3750 tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s));
3751 }
3752
3753 static void in1_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3754 {
3755 in1_la1(s, f, o);
3756 o->in1 = tcg_temp_new_i64();
3757 tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s));
3758 }
3759
3760 /* ====================================================================== */
3761 /* The "INput 2" generators. These load the second operand to an insn. */
3762
3763 static void in2_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3764 {
3765 o->in2 = regs[get_field(f, r1)];
3766 o->g_in2 = true;
3767 }
3768
3769 static void in2_r1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3770 {
3771 o->in2 = tcg_temp_new_i64();
3772 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r1)]);
3773 }
3774
3775 static void in2_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3776 {
3777 o->in2 = tcg_temp_new_i64();
3778 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r1)]);
3779 }
3780
3781 static void in2_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3782 {
3783 o->in2 = load_reg(get_field(f, r2));
3784 }
3785
3786 static void in2_r2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3787 {
3788 o->in2 = regs[get_field(f, r2)];
3789 o->g_in2 = true;
3790 }
3791
3792 static void in2_r2_nz(DisasContext *s, DisasFields *f, DisasOps *o)
3793 {
3794 int r2 = get_field(f, r2);
3795 if (r2 != 0) {
3796 o->in2 = load_reg(r2);
3797 }
3798 }
3799
3800 static void in2_r2_8s(DisasContext *s, DisasFields *f, DisasOps *o)
3801 {
3802 o->in2 = tcg_temp_new_i64();
3803 tcg_gen_ext8s_i64(o->in2, regs[get_field(f, r2)]);
3804 }
3805
3806 static void in2_r2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3807 {
3808 o->in2 = tcg_temp_new_i64();
3809 tcg_gen_ext8u_i64(o->in2, regs[get_field(f, r2)]);
3810 }
3811
3812 static void in2_r2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3813 {
3814 o->in2 = tcg_temp_new_i64();
3815 tcg_gen_ext16s_i64(o->in2, regs[get_field(f, r2)]);
3816 }
3817
3818 static void in2_r2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3819 {
3820 o->in2 = tcg_temp_new_i64();
3821 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r2)]);
3822 }
3823
3824 static void in2_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3825 {
3826 o->in2 = load_reg(get_field(f, r3));
3827 }
3828
3829 static void in2_r2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3830 {
3831 o->in2 = tcg_temp_new_i64();
3832 tcg_gen_ext32s_i64(o->in2, regs[get_field(f, r2)]);
3833 }
3834
3835 static void in2_r2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3836 {
3837 o->in2 = tcg_temp_new_i64();
3838 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r2)]);
3839 }
3840
3841 static void in2_e2(DisasContext *s, DisasFields *f, DisasOps *o)
3842 {
3843 o->in2 = load_freg32_i64(get_field(f, r2));
3844 }
3845
3846 static void in2_f2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3847 {
3848 o->in2 = fregs[get_field(f, r2)];
3849 o->g_in2 = true;
3850 }
3851
3852 static void in2_x2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3853 {
3854 /* ??? Specification exception: r1 must be < 14. */
3855 int r2 = get_field(f, r2);
3856 o->in1 = fregs[r2];
3857 o->in2 = fregs[(r2 + 2) & 15];
3858 o->g_in1 = o->g_in2 = true;
3859 }
3860
3861 static void in2_ra2(DisasContext *s, DisasFields *f, DisasOps *o)
3862 {
3863 o->in2 = get_address(s, 0, get_field(f, r2), 0);
3864 }
3865
3866 static void in2_a2(DisasContext *s, DisasFields *f, DisasOps *o)
3867 {
3868 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3869 o->in2 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3870 }
3871
3872 static void in2_ri2(DisasContext *s, DisasFields *f, DisasOps *o)
3873 {
3874 o->in2 = tcg_const_i64(s->pc + (int64_t)get_field(f, i2) * 2);
3875 }
3876
3877 static void in2_sh32(DisasContext *s, DisasFields *f, DisasOps *o)
3878 {
3879 help_l2_shift(s, f, o, 31);
3880 }
3881
3882 static void in2_sh64(DisasContext *s, DisasFields *f, DisasOps *o)
3883 {
3884 help_l2_shift(s, f, o, 63);
3885 }
3886
3887 static void in2_m2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3888 {
3889 in2_a2(s, f, o);
3890 tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s));
3891 }
3892
3893 static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3894 {
3895 in2_a2(s, f, o);
3896 tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
3897 }
3898
3899 static void in2_m2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3900 {
3901 in2_a2(s, f, o);
3902 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3903 }
3904
3905 static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3906 {
3907 in2_a2(s, f, o);
3908 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3909 }
3910
3911 static void in2_m2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3912 {
3913 in2_a2(s, f, o);
3914 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3915 }
3916
3917 static void in2_m2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3918 {
3919 in2_a2(s, f, o);
3920 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3921 }
3922
3923 static void in2_mri2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3924 {
3925 in2_ri2(s, f, o);
3926 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3927 }
3928
3929 static void in2_mri2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3930 {
3931 in2_ri2(s, f, o);
3932 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3933 }
3934
3935 static void in2_mri2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3936 {
3937 in2_ri2(s, f, o);
3938 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3939 }
3940
3941 static void in2_mri2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3942 {
3943 in2_ri2(s, f, o);
3944 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3945 }
3946
3947 static void in2_i2(DisasContext *s, DisasFields *f, DisasOps *o)
3948 {
3949 o->in2 = tcg_const_i64(get_field(f, i2));
3950 }
3951
3952 static void in2_i2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3953 {
3954 o->in2 = tcg_const_i64((uint8_t)get_field(f, i2));
3955 }
3956
3957 static void in2_i2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3958 {
3959 o->in2 = tcg_const_i64((uint16_t)get_field(f, i2));
3960 }
3961
3962 static void in2_i2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3963 {
3964 o->in2 = tcg_const_i64((uint32_t)get_field(f, i2));
3965 }
3966
3967 static void in2_i2_16u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
3968 {
3969 uint64_t i2 = (uint16_t)get_field(f, i2);
3970 o->in2 = tcg_const_i64(i2 << s->insn->data);
3971 }
3972
3973 static void in2_i2_32u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
3974 {
3975 uint64_t i2 = (uint32_t)get_field(f, i2);
3976 o->in2 = tcg_const_i64(i2 << s->insn->data);
3977 }
3978
3979 /* ====================================================================== */
3980
3981 /* Find opc within the table of insns. This is formulated as a switch
3982 statement so that (1) we get compile-time notice of cut-paste errors
3983 for duplicated opcodes, and (2) the compiler generates the binary
3984 search tree, rather than us having to post-process the table. */
3985
3986 #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
3987 D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0)
3988
3989 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) insn_ ## NM,
3990
3991 enum DisasInsnEnum {
3992 #include "insn-data.def"
3993 };
3994
3995 #undef D
3996 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) { \
3997 .opc = OPC, \
3998 .fmt = FMT_##FT, \
3999 .fac = FAC_##FC, \
4000 .name = #NM, \
4001 .help_in1 = in1_##I1, \
4002 .help_in2 = in2_##I2, \
4003 .help_prep = prep_##P, \
4004 .help_wout = wout_##W, \
4005 .help_cout = cout_##CC, \
4006 .help_op = op_##OP, \
4007 .data = D \
4008 },
4009
4010 /* Allow 0 to be used for NULL in the table below. */
4011 #define in1_0 NULL
4012 #define in2_0 NULL
4013 #define prep_0 NULL
4014 #define wout_0 NULL
4015 #define cout_0 NULL
4016 #define op_0 NULL
4017
4018 static const DisasInsn insn_info[] = {
4019 #include "insn-data.def"
4020 };
4021
4022 #undef D
4023 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
4024 case OPC: return &insn_info[insn_ ## NM];
4025
4026 static const DisasInsn *lookup_opc(uint16_t opc)
4027 {
4028 switch (opc) {
4029 #include "insn-data.def"
4030 default:
4031 return NULL;
4032 }
4033 }
4034
4035 #undef D
4036 #undef C
4037
4038 /* Extract a field from the insn. The INSN should be left-aligned in
4039 the uint64_t so that we can more easily utilize the big-bit-endian
4040 definitions we extract from the Principals of Operation. */
4041
4042 static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn)
4043 {
4044 uint32_t r, m;
4045
4046 if (f->size == 0) {
4047 return;
4048 }
4049
4050 /* Zero extract the field from the insn. */
4051 r = (insn << f->beg) >> (64 - f->size);
4052
4053 /* Sign-extend, or un-swap the field as necessary. */
4054 switch (f->type) {
4055 case 0: /* unsigned */
4056 break;
4057 case 1: /* signed */
4058 assert(f->size <= 32);
4059 m = 1u << (f->size - 1);
4060 r = (r ^ m) - m;
4061 break;
4062 case 2: /* dl+dh split, signed 20 bit. */
4063 r = ((int8_t)r << 12) | (r >> 8);
4064 break;
4065 default:
4066 abort();
4067 }
4068
4069 /* Validate that the "compressed" encoding we selected above is valid.
4070 I.e. we havn't make two different original fields overlap. */
4071 assert(((o->presentC >> f->indexC) & 1) == 0);
4072 o->presentC |= 1 << f->indexC;
4073 o->presentO |= 1 << f->indexO;
4074
4075 o->c[f->indexC] = r;
4076 }
4077
4078 /* Lookup the insn at the current PC, extracting the operands into O and
4079 returning the info struct for the insn. Returns NULL for invalid insn. */
4080
4081 static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
4082 DisasFields *f)
4083 {
4084 uint64_t insn, pc = s->pc;
4085 int op, op2, ilen;
4086 const DisasInsn *info;
4087
4088 insn = ld_code2(env, pc);
4089 op = (insn >> 8) & 0xff;
4090 ilen = get_ilen(op);
4091 s->next_pc = s->pc + ilen;
4092
4093 switch (ilen) {
4094 case 2:
4095 insn = insn << 48;
4096 break;
4097 case 4:
4098 insn = ld_code4(env, pc) << 32;
4099 break;
4100 case 6:
4101 insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
4102 break;
4103 default:
4104 abort();
4105 }
4106
4107 /* We can't actually determine the insn format until we've looked up
4108 the full insn opcode. Which we can't do without locating the
4109 secondary opcode. Assume by default that OP2 is at bit 40; for
4110 those smaller insns that don't actually have a secondary opcode
4111 this will correctly result in OP2 = 0. */
4112 switch (op) {
4113 case 0x01: /* E */
4114 case 0x80: /* S */
4115 case 0x82: /* S */
4116 case 0x93: /* S */
4117 case 0xb2: /* S, RRF, RRE */
4118 case 0xb3: /* RRE, RRD, RRF */
4119 case 0xb9: /* RRE, RRF */
4120 case 0xe5: /* SSE, SIL */
4121 op2 = (insn << 8) >> 56;
4122 break;
4123 case 0xa5: /* RI */
4124 case 0xa7: /* RI */
4125 case 0xc0: /* RIL */
4126 case 0xc2: /* RIL */
4127 case 0xc4: /* RIL */
4128 case 0xc6: /* RIL */
4129 case 0xc8: /* SSF */
4130 case 0xcc: /* RIL */
4131 op2 = (insn << 12) >> 60;
4132 break;
4133 case 0xd0 ... 0xdf: /* SS */
4134 case 0xe1: /* SS */
4135 case 0xe2: /* SS */
4136 case 0xe8: /* SS */
4137 case 0xe9: /* SS */
4138 case 0xea: /* SS */
4139 case 0xee ... 0xf3: /* SS */
4140 case 0xf8 ... 0xfd: /* SS */
4141 op2 = 0;
4142 break;
4143 default:
4144 op2 = (insn << 40) >> 56;
4145 break;
4146 }
4147
4148 memset(f, 0, sizeof(*f));
4149 f->op = op;
4150 f->op2 = op2;
4151
4152 /* Lookup the instruction. */
4153 info = lookup_opc(op << 8 | op2);
4154
4155 /* If we found it, extract the operands. */
4156 if (info != NULL) {
4157 DisasFormat fmt = info->fmt;
4158 int i;
4159
4160 for (i = 0; i < NUM_C_FIELD; ++i) {
4161 extract_field(f, &format_info[fmt].op[i], insn);
4162 }
4163 }
4164 return info;
4165 }
4166
4167 static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
4168 {
4169 const DisasInsn *insn;
4170 ExitStatus ret = NO_EXIT;
4171 DisasFields f;
4172 DisasOps o;
4173
4174 insn = extract_insn(env, s, &f);
4175
4176 /* If not found, try the old interpreter. This includes ILLOPC. */
4177 if (insn == NULL) {
4178 disas_s390_insn(env, s);
4179 switch (s->is_jmp) {
4180 case DISAS_NEXT:
4181 ret = NO_EXIT;
4182 break;
4183 case DISAS_TB_JUMP:
4184 ret = EXIT_GOTO_TB;
4185 break;
4186 case DISAS_JUMP:
4187 ret = EXIT_PC_UPDATED;
4188 break;
4189 case DISAS_EXCP:
4190 ret = EXIT_NORETURN;
4191 break;
4192 default:
4193 abort();
4194 }
4195
4196 s->pc = s->next_pc;
4197 return ret;
4198 }
4199
4200 /* Set up the strutures we use to communicate with the helpers. */
4201 s->insn = insn;
4202 s->fields = &f;
4203 o.g_out = o.g_out2 = o.g_in1 = o.g_in2 = false;
4204 TCGV_UNUSED_I64(o.out);
4205 TCGV_UNUSED_I64(o.out2);
4206 TCGV_UNUSED_I64(o.in1);
4207 TCGV_UNUSED_I64(o.in2);
4208 TCGV_UNUSED_I64(o.addr1);
4209
4210 /* Implement the instruction. */
4211 if (insn->help_in1) {
4212 insn->help_in1(s, &f, &o);
4213 }
4214 if (insn->help_in2) {
4215 insn->help_in2(s, &f, &o);
4216 }
4217 if (insn->help_prep) {
4218 insn->help_prep(s, &f, &o);
4219 }
4220 if (insn->help_op) {
4221 ret = insn->help_op(s, &o);
4222 }
4223 if (insn->help_wout) {
4224 insn->help_wout(s, &f, &o);
4225 }
4226 if (insn->help_cout) {
4227 insn->help_cout(s, &o);
4228 }
4229
4230 /* Free any temporaries created by the helpers. */
4231 if (!TCGV_IS_UNUSED_I64(o.out) && !o.g_out) {
4232 tcg_temp_free_i64(o.out);
4233 }
4234 if (!TCGV_IS_UNUSED_I64(o.out2) && !o.g_out2) {
4235 tcg_temp_free_i64(o.out2);
4236 }
4237 if (!TCGV_IS_UNUSED_I64(o.in1) && !o.g_in1) {
4238 tcg_temp_free_i64(o.in1);
4239 }
4240 if (!TCGV_IS_UNUSED_I64(o.in2) && !o.g_in2) {
4241 tcg_temp_free_i64(o.in2);
4242 }
4243 if (!TCGV_IS_UNUSED_I64(o.addr1)) {
4244 tcg_temp_free_i64(o.addr1);
4245 }
4246
4247 /* Advance to the next instruction. */
4248 s->pc = s->next_pc;
4249 return ret;
4250 }
4251
4252 static inline void gen_intermediate_code_internal(CPUS390XState *env,
4253 TranslationBlock *tb,
4254 int search_pc)
4255 {
4256 DisasContext dc;
4257 target_ulong pc_start;
4258 uint64_t next_page_start;
4259 uint16_t *gen_opc_end;
4260 int j, lj = -1;
4261 int num_insns, max_insns;
4262 CPUBreakpoint *bp;
4263 ExitStatus status;
4264 bool do_debug;
4265
4266 pc_start = tb->pc;
4267
4268 /* 31-bit mode */
4269 if (!(tb->flags & FLAG_MASK_64)) {
4270 pc_start &= 0x7fffffff;
4271 }
4272
4273 dc.tb = tb;
4274 dc.pc = pc_start;
4275 dc.cc_op = CC_OP_DYNAMIC;
4276 do_debug = dc.singlestep_enabled = env->singlestep_enabled;
4277 dc.is_jmp = DISAS_NEXT;
4278
4279 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
4280
4281 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4282
4283 num_insns = 0;
4284 max_insns = tb->cflags & CF_COUNT_MASK;
4285 if (max_insns == 0) {
4286 max_insns = CF_COUNT_MASK;
4287 }
4288
4289 gen_icount_start();
4290
4291 do {
4292 if (search_pc) {
4293 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4294 if (lj < j) {
4295 lj++;
4296 while (lj < j) {
4297 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4298 }
4299 }
4300 tcg_ctx.gen_opc_pc[lj] = dc.pc;
4301 gen_opc_cc_op[lj] = dc.cc_op;
4302 tcg_ctx.gen_opc_instr_start[lj] = 1;
4303 tcg_ctx.gen_opc_icount[lj] = num_insns;
4304 }
4305 if (++num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
4306 gen_io_start();
4307 }
4308
4309 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4310 tcg_gen_debug_insn_start(dc.pc);
4311 }
4312
4313 status = NO_EXIT;
4314 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
4315 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
4316 if (bp->pc == dc.pc) {
4317 status = EXIT_PC_STALE;
4318 do_debug = true;
4319 break;
4320 }
4321 }
4322 }
4323 if (status == NO_EXIT) {
4324 status = translate_one(env, &dc);
4325 }
4326
4327 /* If we reach a page boundary, are single stepping,
4328 or exhaust instruction count, stop generation. */
4329 if (status == NO_EXIT
4330 && (dc.pc >= next_page_start
4331 || tcg_ctx.gen_opc_ptr >= gen_opc_end
4332 || num_insns >= max_insns
4333 || singlestep
4334 || env->singlestep_enabled)) {
4335 status = EXIT_PC_STALE;
4336 }
4337 } while (status == NO_EXIT);
4338
4339 if (tb->cflags & CF_LAST_IO) {
4340 gen_io_end();
4341 }
4342
4343 switch (status) {
4344 case EXIT_GOTO_TB:
4345 case EXIT_NORETURN:
4346 break;
4347 case EXIT_PC_STALE:
4348 update_psw_addr(&dc);
4349 /* FALLTHRU */
4350 case EXIT_PC_UPDATED:
4351 if (singlestep && dc.cc_op != CC_OP_DYNAMIC) {
4352 gen_op_calc_cc(&dc);
4353 } else {
4354 /* Next TB starts off with CC_OP_DYNAMIC,
4355 so make sure the cc op type is in env */
4356 gen_op_set_cc_op(&dc);
4357 }
4358 if (do_debug) {
4359 gen_exception(EXCP_DEBUG);
4360 } else {
4361 /* Generate the return instruction */
4362 tcg_gen_exit_tb(0);
4363 }
4364 break;
4365 default:
4366 abort();
4367 }
4368
4369 gen_icount_end(tb, num_insns);
4370 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
4371 if (search_pc) {
4372 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4373 lj++;
4374 while (lj <= j) {
4375 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4376 }
4377 } else {
4378 tb->size = dc.pc - pc_start;
4379 tb->icount = num_insns;
4380 }
4381
4382 #if defined(S390X_DEBUG_DISAS)
4383 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
4384 qemu_log("IN: %s\n", lookup_symbol(pc_start));
4385 log_target_disas(env, pc_start, dc.pc - pc_start, 1);
4386 qemu_log("\n");
4387 }
4388 #endif
4389 }
4390
4391 void gen_intermediate_code (CPUS390XState *env, struct TranslationBlock *tb)
4392 {
4393 gen_intermediate_code_internal(env, tb, 0);
4394 }
4395
4396 void gen_intermediate_code_pc (CPUS390XState *env, struct TranslationBlock *tb)
4397 {
4398 gen_intermediate_code_internal(env, tb, 1);
4399 }
4400
4401 void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos)
4402 {
4403 int cc_op;
4404 env->psw.addr = tcg_ctx.gen_opc_pc[pc_pos];
4405 cc_op = gen_opc_cc_op[pc_pos];
4406 if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {
4407 env->cc_op = cc_op;
4408 }
4409 }
Qemu copy for testing