4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 /* #define DEBUG_INLINE_BRANCHES */
22 #define S390X_DEBUG_DISAS
23 /* #define S390X_DEBUG_DISAS_VERBOSE */
25 #ifdef S390X_DEBUG_DISAS_VERBOSE
26 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
28 # define LOG_DISAS(...) do { } while (0)
32 #include "disas/disas.h"
35 #include "qemu/host-utils.h"
37 /* global register indexes */
38 static TCGv_ptr cpu_env
;
40 #include "exec/gen-icount.h"
46 /* Information that (most) every instruction needs to manipulate. */
47 typedef struct DisasContext DisasContext
;
48 typedef struct DisasInsn DisasInsn
;
49 typedef struct DisasFields DisasFields
;
52 struct TranslationBlock
*tb
;
53 const DisasInsn
*insn
;
57 bool singlestep_enabled
;
60 /* Information carried about a condition to be evaluated. */
67 struct { TCGv_i64 a
, b
; } s64
;
68 struct { TCGv_i32 a
, b
; } s32
;
74 #ifdef DEBUG_INLINE_BRANCHES
75 static uint64_t inline_branch_hit
[CC_OP_MAX
];
76 static uint64_t inline_branch_miss
[CC_OP_MAX
];
79 static uint64_t pc_to_link_info(DisasContext
*s
, uint64_t pc
)
81 if (!(s
->tb
->flags
& FLAG_MASK_64
)) {
82 if (s
->tb
->flags
& FLAG_MASK_32
) {
83 return pc
| 0x80000000;
89 void cpu_dump_state(CPUS390XState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
95 cpu_fprintf(f
, "PSW=mask %016" PRIx64
" addr %016" PRIx64
" cc %15s\n",
96 env
->psw
.mask
, env
->psw
.addr
, cc_name(env
->cc_op
));
98 cpu_fprintf(f
, "PSW=mask %016" PRIx64
" addr %016" PRIx64
" cc %02x\n",
99 env
->psw
.mask
, env
->psw
.addr
, env
->cc_op
);
102 for (i
= 0; i
< 16; i
++) {
103 cpu_fprintf(f
, "R%02d=%016" PRIx64
, i
, env
->regs
[i
]);
105 cpu_fprintf(f
, "\n");
111 for (i
= 0; i
< 16; i
++) {
112 cpu_fprintf(f
, "F%02d=%016" PRIx64
, i
, env
->fregs
[i
].ll
);
114 cpu_fprintf(f
, "\n");
120 #ifndef CONFIG_USER_ONLY
121 for (i
= 0; i
< 16; i
++) {
122 cpu_fprintf(f
, "C%02d=%016" PRIx64
, i
, env
->cregs
[i
]);
124 cpu_fprintf(f
, "\n");
131 #ifdef DEBUG_INLINE_BRANCHES
132 for (i
= 0; i
< CC_OP_MAX
; i
++) {
133 cpu_fprintf(f
, " %15s = %10ld\t%10ld\n", cc_name(i
),
134 inline_branch_miss
[i
], inline_branch_hit
[i
]);
138 cpu_fprintf(f
, "\n");
141 static TCGv_i64 psw_addr
;
142 static TCGv_i64 psw_mask
;
144 static TCGv_i32 cc_op
;
145 static TCGv_i64 cc_src
;
146 static TCGv_i64 cc_dst
;
147 static TCGv_i64 cc_vr
;
149 static char cpu_reg_names
[32][4];
150 static TCGv_i64 regs
[16];
151 static TCGv_i64 fregs
[16];
153 static uint8_t gen_opc_cc_op
[OPC_BUF_SIZE
];
155 void s390x_translate_init(void)
159 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
160 psw_addr
= tcg_global_mem_new_i64(TCG_AREG0
,
161 offsetof(CPUS390XState
, psw
.addr
),
163 psw_mask
= tcg_global_mem_new_i64(TCG_AREG0
,
164 offsetof(CPUS390XState
, psw
.mask
),
167 cc_op
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUS390XState
, cc_op
),
169 cc_src
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUS390XState
, cc_src
),
171 cc_dst
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUS390XState
, cc_dst
),
173 cc_vr
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUS390XState
, cc_vr
),
176 for (i
= 0; i
< 16; i
++) {
177 snprintf(cpu_reg_names
[i
], sizeof(cpu_reg_names
[0]), "r%d", i
);
178 regs
[i
] = tcg_global_mem_new(TCG_AREG0
,
179 offsetof(CPUS390XState
, regs
[i
]),
183 for (i
= 0; i
< 16; i
++) {
184 snprintf(cpu_reg_names
[i
+ 16], sizeof(cpu_reg_names
[0]), "f%d", i
);
185 fregs
[i
] = tcg_global_mem_new(TCG_AREG0
,
186 offsetof(CPUS390XState
, fregs
[i
].d
),
187 cpu_reg_names
[i
+ 16]);
190 /* register helpers */
195 static TCGv_i64
load_reg(int reg
)
197 TCGv_i64 r
= tcg_temp_new_i64();
198 tcg_gen_mov_i64(r
, regs
[reg
]);
202 static TCGv_i64
load_freg32_i64(int reg
)
204 TCGv_i64 r
= tcg_temp_new_i64();
205 tcg_gen_shri_i64(r
, fregs
[reg
], 32);
209 static void store_reg(int reg
, TCGv_i64 v
)
211 tcg_gen_mov_i64(regs
[reg
], v
);
214 static void store_freg(int reg
, TCGv_i64 v
)
216 tcg_gen_mov_i64(fregs
[reg
], v
);
219 static void store_reg32_i64(int reg
, TCGv_i64 v
)
221 /* 32 bit register writes keep the upper half */
222 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
], v
, 0, 32);
225 static void store_reg32h_i64(int reg
, TCGv_i64 v
)
227 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
], v
, 32, 32);
230 static void store_freg32_i64(int reg
, TCGv_i64 v
)
232 tcg_gen_deposit_i64(fregs
[reg
], fregs
[reg
], v
, 32, 32);
235 static void return_low128(TCGv_i64 dest
)
237 tcg_gen_ld_i64(dest
, cpu_env
, offsetof(CPUS390XState
, retxl
));
240 static void update_psw_addr(DisasContext
*s
)
243 tcg_gen_movi_i64(psw_addr
, s
->pc
);
246 static void update_cc_op(DisasContext
*s
)
248 if (s
->cc_op
!= CC_OP_DYNAMIC
&& s
->cc_op
!= CC_OP_STATIC
) {
249 tcg_gen_movi_i32(cc_op
, s
->cc_op
);
253 static void potential_page_fault(DisasContext
*s
)
259 static inline uint64_t ld_code2(CPUS390XState
*env
, uint64_t pc
)
261 return (uint64_t)cpu_lduw_code(env
, pc
);
264 static inline uint64_t ld_code4(CPUS390XState
*env
, uint64_t pc
)
266 return (uint64_t)(uint32_t)cpu_ldl_code(env
, pc
);
269 static inline uint64_t ld_code6(CPUS390XState
*env
, uint64_t pc
)
271 return (ld_code2(env
, pc
) << 32) | ld_code4(env
, pc
+ 2);
274 static int get_mem_index(DisasContext
*s
)
276 switch (s
->tb
->flags
& FLAG_MASK_ASC
) {
277 case PSW_ASC_PRIMARY
>> 32:
279 case PSW_ASC_SECONDARY
>> 32:
281 case PSW_ASC_HOME
>> 32:
289 static void gen_exception(int excp
)
291 TCGv_i32 tmp
= tcg_const_i32(excp
);
292 gen_helper_exception(cpu_env
, tmp
);
293 tcg_temp_free_i32(tmp
);
296 static void gen_program_exception(DisasContext
*s
, int code
)
300 /* Remember what pgm exeption this was. */
301 tmp
= tcg_const_i32(code
);
302 tcg_gen_st_i32(tmp
, cpu_env
, offsetof(CPUS390XState
, int_pgm_code
));
303 tcg_temp_free_i32(tmp
);
305 tmp
= tcg_const_i32(s
->next_pc
- s
->pc
);
306 tcg_gen_st_i32(tmp
, cpu_env
, offsetof(CPUS390XState
, int_pgm_ilen
));
307 tcg_temp_free_i32(tmp
);
309 /* Advance past instruction. */
316 /* Trigger exception. */
317 gen_exception(EXCP_PGM
);
320 static inline void gen_illegal_opcode(DisasContext
*s
)
322 gen_program_exception(s
, PGM_SPECIFICATION
);
325 static inline void check_privileged(DisasContext
*s
)
327 if (s
->tb
->flags
& (PSW_MASK_PSTATE
>> 32)) {
328 gen_program_exception(s
, PGM_PRIVILEGED
);
332 static TCGv_i64
get_address(DisasContext
*s
, int x2
, int b2
, int d2
)
336 /* 31-bitify the immediate part; register contents are dealt with below */
337 if (!(s
->tb
->flags
& FLAG_MASK_64
)) {
343 tmp
= tcg_const_i64(d2
);
344 tcg_gen_add_i64(tmp
, tmp
, regs
[x2
]);
349 tcg_gen_add_i64(tmp
, tmp
, regs
[b2
]);
353 tmp
= tcg_const_i64(d2
);
354 tcg_gen_add_i64(tmp
, tmp
, regs
[b2
]);
359 tmp
= tcg_const_i64(d2
);
362 /* 31-bit mode mask if there are values loaded from registers */
363 if (!(s
->tb
->flags
& FLAG_MASK_64
) && (x2
|| b2
)) {
364 tcg_gen_andi_i64(tmp
, tmp
, 0x7fffffffUL
);
370 static inline void gen_op_movi_cc(DisasContext
*s
, uint32_t val
)
372 s
->cc_op
= CC_OP_CONST0
+ val
;
375 static void gen_op_update1_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 dst
)
377 tcg_gen_discard_i64(cc_src
);
378 tcg_gen_mov_i64(cc_dst
, dst
);
379 tcg_gen_discard_i64(cc_vr
);
383 static void gen_op_update2_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 src
,
386 tcg_gen_mov_i64(cc_src
, src
);
387 tcg_gen_mov_i64(cc_dst
, dst
);
388 tcg_gen_discard_i64(cc_vr
);
392 static void gen_op_update3_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 src
,
393 TCGv_i64 dst
, TCGv_i64 vr
)
395 tcg_gen_mov_i64(cc_src
, src
);
396 tcg_gen_mov_i64(cc_dst
, dst
);
397 tcg_gen_mov_i64(cc_vr
, vr
);
401 static void set_cc_nz_u64(DisasContext
*s
, TCGv_i64 val
)
403 gen_op_update1_cc_i64(s
, CC_OP_NZ
, val
);
406 static void gen_set_cc_nz_f32(DisasContext
*s
, TCGv_i64 val
)
408 gen_op_update1_cc_i64(s
, CC_OP_NZ_F32
, val
);
411 static void gen_set_cc_nz_f64(DisasContext
*s
, TCGv_i64 val
)
413 gen_op_update1_cc_i64(s
, CC_OP_NZ_F64
, val
);
416 static void gen_set_cc_nz_f128(DisasContext
*s
, TCGv_i64 vh
, TCGv_i64 vl
)
418 gen_op_update2_cc_i64(s
, CC_OP_NZ_F128
, vh
, vl
);
421 /* CC value is in env->cc_op */
422 static void set_cc_static(DisasContext
*s
)
424 tcg_gen_discard_i64(cc_src
);
425 tcg_gen_discard_i64(cc_dst
);
426 tcg_gen_discard_i64(cc_vr
);
427 s
->cc_op
= CC_OP_STATIC
;
430 /* calculates cc into cc_op */
431 static void gen_op_calc_cc(DisasContext
*s
)
433 TCGv_i32 local_cc_op
;
436 TCGV_UNUSED_I32(local_cc_op
);
437 TCGV_UNUSED_I64(dummy
);
440 dummy
= tcg_const_i64(0);
454 local_cc_op
= tcg_const_i32(s
->cc_op
);
470 /* s->cc_op is the cc value */
471 tcg_gen_movi_i32(cc_op
, s
->cc_op
- CC_OP_CONST0
);
474 /* env->cc_op already is the cc value */
489 gen_helper_calc_cc(cc_op
, cpu_env
, local_cc_op
, dummy
, cc_dst
, dummy
);
494 case CC_OP_LTUGTU_32
:
495 case CC_OP_LTUGTU_64
:
502 gen_helper_calc_cc(cc_op
, cpu_env
, local_cc_op
, cc_src
, cc_dst
, dummy
);
517 gen_helper_calc_cc(cc_op
, cpu_env
, local_cc_op
, cc_src
, cc_dst
, cc_vr
);
520 /* unknown operation - assume 3 arguments and cc_op in env */
521 gen_helper_calc_cc(cc_op
, cpu_env
, cc_op
, cc_src
, cc_dst
, cc_vr
);
527 if (!TCGV_IS_UNUSED_I32(local_cc_op
)) {
528 tcg_temp_free_i32(local_cc_op
);
530 if (!TCGV_IS_UNUSED_I64(dummy
)) {
531 tcg_temp_free_i64(dummy
);
534 /* We now have cc in cc_op as constant */
538 static int use_goto_tb(DisasContext
*s
, uint64_t dest
)
540 /* NOTE: we handle the case where the TB spans two pages here */
541 return (((dest
& TARGET_PAGE_MASK
) == (s
->tb
->pc
& TARGET_PAGE_MASK
)
542 || (dest
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
))
543 && !s
->singlestep_enabled
544 && !(s
->tb
->cflags
& CF_LAST_IO
));
547 static void account_noninline_branch(DisasContext
*s
, int cc_op
)
549 #ifdef DEBUG_INLINE_BRANCHES
550 inline_branch_miss
[cc_op
]++;
554 static void account_inline_branch(DisasContext
*s
, int cc_op
)
556 #ifdef DEBUG_INLINE_BRANCHES
557 inline_branch_hit
[cc_op
]++;
561 /* Table of mask values to comparison codes, given a comparison as input.
562 For a true comparison CC=3 will never be set, but we treat this
563 conservatively for possible use when CC=3 indicates overflow. */
564 static const TCGCond ltgt_cond
[16] = {
565 TCG_COND_NEVER
, TCG_COND_NEVER
, /* | | | x */
566 TCG_COND_GT
, TCG_COND_NEVER
, /* | | GT | x */
567 TCG_COND_LT
, TCG_COND_NEVER
, /* | LT | | x */
568 TCG_COND_NE
, TCG_COND_NEVER
, /* | LT | GT | x */
569 TCG_COND_EQ
, TCG_COND_NEVER
, /* EQ | | | x */
570 TCG_COND_GE
, TCG_COND_NEVER
, /* EQ | | GT | x */
571 TCG_COND_LE
, TCG_COND_NEVER
, /* EQ | LT | | x */
572 TCG_COND_ALWAYS
, TCG_COND_ALWAYS
, /* EQ | LT | GT | x */
575 /* Table of mask values to comparison codes, given a logic op as input.
576 For such, only CC=0 and CC=1 should be possible. */
577 static const TCGCond nz_cond
[16] = {
579 TCG_COND_NEVER
, TCG_COND_NEVER
, TCG_COND_NEVER
, TCG_COND_NEVER
,
581 TCG_COND_NE
, TCG_COND_NE
, TCG_COND_NE
, TCG_COND_NE
,
583 TCG_COND_EQ
, TCG_COND_EQ
, TCG_COND_EQ
, TCG_COND_EQ
,
584 /* EQ | NE | x | x */
585 TCG_COND_ALWAYS
, TCG_COND_ALWAYS
, TCG_COND_ALWAYS
, TCG_COND_ALWAYS
,
588 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
589 details required to generate a TCG comparison. */
590 static void disas_jcc(DisasContext
*s
, DisasCompare
*c
, uint32_t mask
)
593 enum cc_op old_cc_op
= s
->cc_op
;
595 if (mask
== 15 || mask
== 0) {
596 c
->cond
= (mask
? TCG_COND_ALWAYS
: TCG_COND_NEVER
);
599 c
->g1
= c
->g2
= true;
604 /* Find the TCG condition for the mask + cc op. */
610 cond
= ltgt_cond
[mask
];
611 if (cond
== TCG_COND_NEVER
) {
614 account_inline_branch(s
, old_cc_op
);
617 case CC_OP_LTUGTU_32
:
618 case CC_OP_LTUGTU_64
:
619 cond
= tcg_unsigned_cond(ltgt_cond
[mask
]);
620 if (cond
== TCG_COND_NEVER
) {
623 account_inline_branch(s
, old_cc_op
);
627 cond
= nz_cond
[mask
];
628 if (cond
== TCG_COND_NEVER
) {
631 account_inline_branch(s
, old_cc_op
);
646 account_inline_branch(s
, old_cc_op
);
661 account_inline_branch(s
, old_cc_op
);
665 switch (mask
& 0xa) {
666 case 8: /* src == 0 -> no one bit found */
669 case 2: /* src != 0 -> one bit found */
675 account_inline_branch(s
, old_cc_op
);
680 /* Calculate cc value. */
685 /* Jump based on CC. We'll load up the real cond below;
686 the assignment here merely avoids a compiler warning. */
687 account_noninline_branch(s
, old_cc_op
);
688 old_cc_op
= CC_OP_STATIC
;
689 cond
= TCG_COND_NEVER
;
693 /* Load up the arguments of the comparison. */
695 c
->g1
= c
->g2
= false;
699 c
->u
.s32
.a
= tcg_temp_new_i32();
700 tcg_gen_trunc_i64_i32(c
->u
.s32
.a
, cc_dst
);
701 c
->u
.s32
.b
= tcg_const_i32(0);
704 case CC_OP_LTUGTU_32
:
706 c
->u
.s32
.a
= tcg_temp_new_i32();
707 tcg_gen_trunc_i64_i32(c
->u
.s32
.a
, cc_src
);
708 c
->u
.s32
.b
= tcg_temp_new_i32();
709 tcg_gen_trunc_i64_i32(c
->u
.s32
.b
, cc_dst
);
716 c
->u
.s64
.b
= tcg_const_i64(0);
720 case CC_OP_LTUGTU_64
:
723 c
->g1
= c
->g2
= true;
729 c
->u
.s64
.a
= tcg_temp_new_i64();
730 c
->u
.s64
.b
= tcg_const_i64(0);
731 tcg_gen_and_i64(c
->u
.s64
.a
, cc_src
, cc_dst
);
739 case 0x8 | 0x4 | 0x2: /* cc != 3 */
741 c
->u
.s32
.b
= tcg_const_i32(3);
743 case 0x8 | 0x4 | 0x1: /* cc != 2 */
745 c
->u
.s32
.b
= tcg_const_i32(2);
747 case 0x8 | 0x2 | 0x1: /* cc != 1 */
749 c
->u
.s32
.b
= tcg_const_i32(1);
751 case 0x8 | 0x2: /* cc == 0 ||Â cc == 2 => (cc & 1) == 0 */
754 c
->u
.s32
.a
= tcg_temp_new_i32();
755 c
->u
.s32
.b
= tcg_const_i32(0);
756 tcg_gen_andi_i32(c
->u
.s32
.a
, cc_op
, 1);
758 case 0x8 | 0x4: /* cc < 2 */
760 c
->u
.s32
.b
= tcg_const_i32(2);
762 case 0x8: /* cc == 0 */
764 c
->u
.s32
.b
= tcg_const_i32(0);
766 case 0x4 | 0x2 | 0x1: /* cc != 0 */
768 c
->u
.s32
.b
= tcg_const_i32(0);
770 case 0x4 | 0x1: /* cc == 1 ||Â cc == 3 => (cc & 1) != 0 */
773 c
->u
.s32
.a
= tcg_temp_new_i32();
774 c
->u
.s32
.b
= tcg_const_i32(0);
775 tcg_gen_andi_i32(c
->u
.s32
.a
, cc_op
, 1);
777 case 0x4: /* cc == 1 */
779 c
->u
.s32
.b
= tcg_const_i32(1);
781 case 0x2 | 0x1: /* cc > 1 */
783 c
->u
.s32
.b
= tcg_const_i32(1);
785 case 0x2: /* cc == 2 */
787 c
->u
.s32
.b
= tcg_const_i32(2);
789 case 0x1: /* cc == 3 */
791 c
->u
.s32
.b
= tcg_const_i32(3);
794 /* CC is masked by something else: (8 >> cc) & mask. */
797 c
->u
.s32
.a
= tcg_const_i32(8);
798 c
->u
.s32
.b
= tcg_const_i32(0);
799 tcg_gen_shr_i32(c
->u
.s32
.a
, c
->u
.s32
.a
, cc_op
);
800 tcg_gen_andi_i32(c
->u
.s32
.a
, c
->u
.s32
.a
, mask
);
811 static void free_compare(DisasCompare
*c
)
815 tcg_temp_free_i64(c
->u
.s64
.a
);
817 tcg_temp_free_i32(c
->u
.s32
.a
);
822 tcg_temp_free_i64(c
->u
.s64
.b
);
824 tcg_temp_free_i32(c
->u
.s32
.b
);
829 /* ====================================================================== */
830 /* Define the insn format enumeration. */
831 #define F0(N) FMT_##N,
832 #define F1(N, X1) F0(N)
833 #define F2(N, X1, X2) F0(N)
834 #define F3(N, X1, X2, X3) F0(N)
835 #define F4(N, X1, X2, X3, X4) F0(N)
836 #define F5(N, X1, X2, X3, X4, X5) F0(N)
839 #include "insn-format.def"
849 /* Define a structure to hold the decoded fields. We'll store each inside
850 an array indexed by an enum. In order to conserve memory, we'll arrange
851 for fields that do not exist at the same time to overlap, thus the "C"
852 for compact. For checking purposes there is an "O" for original index
853 as well that will be applied to availability bitmaps. */
855 enum DisasFieldIndexO
{
878 enum DisasFieldIndexC
{
912 unsigned presentC
:16;
913 unsigned int presentO
;
917 /* This is the way fields are to be accessed out of DisasFields. */
918 #define have_field(S, F) have_field1((S), FLD_O_##F)
919 #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
921 static bool have_field1(const DisasFields
*f
, enum DisasFieldIndexO c
)
923 return (f
->presentO
>> c
) & 1;
926 static int get_field1(const DisasFields
*f
, enum DisasFieldIndexO o
,
927 enum DisasFieldIndexC c
)
929 assert(have_field1(f
, o
));
933 /* Describe the layout of each field in each format. */
934 typedef struct DisasField
{
938 unsigned int indexC
:6;
939 enum DisasFieldIndexO indexO
:8;
942 typedef struct DisasFormatInfo
{
943 DisasField op
[NUM_C_FIELD
];
946 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
947 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
948 #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
949 { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
950 #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
951 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
952 { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
953 #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
954 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
955 #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
956 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
957 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
958 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
959 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
961 #define F0(N) { { } },
962 #define F1(N, X1) { { X1 } },
963 #define F2(N, X1, X2) { { X1, X2 } },
964 #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
965 #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
966 #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
968 static const DisasFormatInfo format_info
[] = {
969 #include "insn-format.def"
987 /* Generally, we'll extract operands into this structures, operate upon
988 them, and store them back. See the "in1", "in2", "prep", "wout" sets
989 of routines below for more details. */
991 bool g_out
, g_out2
, g_in1
, g_in2
;
992 TCGv_i64 out
, out2
, in1
, in2
;
996 /* Return values from translate_one, indicating the state of the TB. */
998 /* Continue the TB. */
1000 /* We have emitted one or more goto_tb. No fixup required. */
1002 /* We are not using a goto_tb (for whatever reason), but have updated
1003 the PC (for whatever reason), so there's no need to do it again on
1006 /* We are exiting the TB, but have neither emitted a goto_tb, nor
1007 updated the PC for the next instruction to be executed. */
1009 /* We are ending the TB with a noreturn function call, e.g. longjmp.
1010 No following code will be executed. */
1014 typedef enum DisasFacility
{
1015 FAC_Z
, /* zarch (default) */
1016 FAC_CASS
, /* compare and swap and store */
1017 FAC_CASS2
, /* compare and swap and store 2*/
1018 FAC_DFP
, /* decimal floating point */
1019 FAC_DFPR
, /* decimal floating point rounding */
1020 FAC_DO
, /* distinct operands */
1021 FAC_EE
, /* execute extensions */
1022 FAC_EI
, /* extended immediate */
1023 FAC_FPE
, /* floating point extension */
1024 FAC_FPSSH
, /* floating point support sign handling */
1025 FAC_FPRGR
, /* FPR-GR transfer */
1026 FAC_GIE
, /* general instructions extension */
1027 FAC_HFP_MA
, /* HFP multiply-and-add/subtract */
1028 FAC_HW
, /* high-word */
1029 FAC_IEEEE_SIM
, /* IEEE exception sumilation */
1030 FAC_LOC
, /* load/store on condition */
1031 FAC_LD
, /* long displacement */
1032 FAC_PC
, /* population count */
1033 FAC_SCF
, /* store clock fast */
1034 FAC_SFLE
, /* store facility list extended */
1040 DisasFacility fac
:6;
1044 void (*help_in1
)(DisasContext
*, DisasFields
*, DisasOps
*);
1045 void (*help_in2
)(DisasContext
*, DisasFields
*, DisasOps
*);
1046 void (*help_prep
)(DisasContext
*, DisasFields
*, DisasOps
*);
1047 void (*help_wout
)(DisasContext
*, DisasFields
*, DisasOps
*);
1048 void (*help_cout
)(DisasContext
*, DisasOps
*);
1049 ExitStatus (*help_op
)(DisasContext
*, DisasOps
*);
1054 /* ====================================================================== */
1055 /* Miscelaneous helpers, used by several operations. */
1057 static void help_l2_shift(DisasContext
*s
, DisasFields
*f
,
1058 DisasOps
*o
, int mask
)
1060 int b2
= get_field(f
, b2
);
1061 int d2
= get_field(f
, d2
);
1064 o
->in2
= tcg_const_i64(d2
& mask
);
1066 o
->in2
= get_address(s
, 0, b2
, d2
);
1067 tcg_gen_andi_i64(o
->in2
, o
->in2
, mask
);
1071 static ExitStatus
help_goto_direct(DisasContext
*s
, uint64_t dest
)
1073 if (dest
== s
->next_pc
) {
1076 if (use_goto_tb(s
, dest
)) {
1079 tcg_gen_movi_i64(psw_addr
, dest
);
1080 tcg_gen_exit_tb((tcg_target_long
)s
->tb
);
1081 return EXIT_GOTO_TB
;
1083 tcg_gen_movi_i64(psw_addr
, dest
);
1084 return EXIT_PC_UPDATED
;
1088 static ExitStatus
help_branch(DisasContext
*s
, DisasCompare
*c
,
1089 bool is_imm
, int imm
, TCGv_i64 cdest
)
1092 uint64_t dest
= s
->pc
+ 2 * imm
;
1095 /* Take care of the special cases first. */
1096 if (c
->cond
== TCG_COND_NEVER
) {
1101 if (dest
== s
->next_pc
) {
1102 /* Branch to next. */
1106 if (c
->cond
== TCG_COND_ALWAYS
) {
1107 ret
= help_goto_direct(s
, dest
);
1111 if (TCGV_IS_UNUSED_I64(cdest
)) {
1112 /* E.g. bcr %r0 -> no branch. */
1116 if (c
->cond
== TCG_COND_ALWAYS
) {
1117 tcg_gen_mov_i64(psw_addr
, cdest
);
1118 ret
= EXIT_PC_UPDATED
;
1123 if (use_goto_tb(s
, s
->next_pc
)) {
1124 if (is_imm
&& use_goto_tb(s
, dest
)) {
1125 /* Both exits can use goto_tb. */
1128 lab
= gen_new_label();
1130 tcg_gen_brcond_i64(c
->cond
, c
->u
.s64
.a
, c
->u
.s64
.b
, lab
);
1132 tcg_gen_brcond_i32(c
->cond
, c
->u
.s32
.a
, c
->u
.s32
.b
, lab
);
1135 /* Branch not taken. */
1137 tcg_gen_movi_i64(psw_addr
, s
->next_pc
);
1138 tcg_gen_exit_tb((tcg_target_long
)s
->tb
+ 0);
1143 tcg_gen_movi_i64(psw_addr
, dest
);
1144 tcg_gen_exit_tb((tcg_target_long
)s
->tb
+ 1);
1148 /* Fallthru can use goto_tb, but taken branch cannot. */
1149 /* Store taken branch destination before the brcond. This
1150 avoids having to allocate a new local temp to hold it.
1151 We'll overwrite this in the not taken case anyway. */
1153 tcg_gen_mov_i64(psw_addr
, cdest
);
1156 lab
= gen_new_label();
1158 tcg_gen_brcond_i64(c
->cond
, c
->u
.s64
.a
, c
->u
.s64
.b
, lab
);
1160 tcg_gen_brcond_i32(c
->cond
, c
->u
.s32
.a
, c
->u
.s32
.b
, lab
);
1163 /* Branch not taken. */
1166 tcg_gen_movi_i64(psw_addr
, s
->next_pc
);
1167 tcg_gen_exit_tb((tcg_target_long
)s
->tb
+ 0);
1171 tcg_gen_movi_i64(psw_addr
, dest
);
1173 ret
= EXIT_PC_UPDATED
;
1176 /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
1177 Most commonly we're single-stepping or some other condition that
1178 disables all use of goto_tb. Just update the PC and exit. */
1180 TCGv_i64 next
= tcg_const_i64(s
->next_pc
);
1182 cdest
= tcg_const_i64(dest
);
1186 tcg_gen_movcond_i64(c
->cond
, psw_addr
, c
->u
.s64
.a
, c
->u
.s64
.b
,
1189 TCGv_i32 t0
= tcg_temp_new_i32();
1190 TCGv_i64 t1
= tcg_temp_new_i64();
1191 TCGv_i64 z
= tcg_const_i64(0);
1192 tcg_gen_setcond_i32(c
->cond
, t0
, c
->u
.s32
.a
, c
->u
.s32
.b
);
1193 tcg_gen_extu_i32_i64(t1
, t0
);
1194 tcg_temp_free_i32(t0
);
1195 tcg_gen_movcond_i64(TCG_COND_NE
, psw_addr
, t1
, z
, cdest
, next
);
1196 tcg_temp_free_i64(t1
);
1197 tcg_temp_free_i64(z
);
1201 tcg_temp_free_i64(cdest
);
1203 tcg_temp_free_i64(next
);
1205 ret
= EXIT_PC_UPDATED
;
1213 /* ====================================================================== */
1214 /* The operations. These perform the bulk of the work for any insn,
1215 usually after the operands have been loaded and output initialized. */
1217 static ExitStatus
op_abs(DisasContext
*s
, DisasOps
*o
)
1219 gen_helper_abs_i64(o
->out
, o
->in2
);
1223 static ExitStatus
op_absf32(DisasContext
*s
, DisasOps
*o
)
1225 tcg_gen_andi_i64(o
->out
, o
->in2
, 0x7fffffffull
);
1229 static ExitStatus
op_absf64(DisasContext
*s
, DisasOps
*o
)
1231 tcg_gen_andi_i64(o
->out
, o
->in2
, 0x7fffffffffffffffull
);
1235 static ExitStatus
op_absf128(DisasContext
*s
, DisasOps
*o
)
1237 tcg_gen_andi_i64(o
->out
, o
->in1
, 0x7fffffffffffffffull
);
1238 tcg_gen_mov_i64(o
->out2
, o
->in2
);
1242 static ExitStatus
op_add(DisasContext
*s
, DisasOps
*o
)
1244 tcg_gen_add_i64(o
->out
, o
->in1
, o
->in2
);
1248 static ExitStatus
op_addc(DisasContext
*s
, DisasOps
*o
)
1252 tcg_gen_add_i64(o
->out
, o
->in1
, o
->in2
);
1254 /* XXX possible optimization point */
1256 cc
= tcg_temp_new_i64();
1257 tcg_gen_extu_i32_i64(cc
, cc_op
);
1258 tcg_gen_shri_i64(cc
, cc
, 1);
1260 tcg_gen_add_i64(o
->out
, o
->out
, cc
);
1261 tcg_temp_free_i64(cc
);
1265 static ExitStatus
op_aeb(DisasContext
*s
, DisasOps
*o
)
1267 gen_helper_aeb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
1271 static ExitStatus
op_adb(DisasContext
*s
, DisasOps
*o
)
1273 gen_helper_adb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
1277 static ExitStatus
op_axb(DisasContext
*s
, DisasOps
*o
)
1279 gen_helper_axb(o
->out
, cpu_env
, o
->out
, o
->out2
, o
->in1
, o
->in2
);
1280 return_low128(o
->out2
);
1284 static ExitStatus
op_and(DisasContext
*s
, DisasOps
*o
)
1286 tcg_gen_and_i64(o
->out
, o
->in1
, o
->in2
);
1290 static ExitStatus
op_andi(DisasContext
*s
, DisasOps
*o
)
1292 int shift
= s
->insn
->data
& 0xff;
1293 int size
= s
->insn
->data
>> 8;
1294 uint64_t mask
= ((1ull << size
) - 1) << shift
;
1297 tcg_gen_shli_i64(o
->in2
, o
->in2
, shift
);
1298 tcg_gen_ori_i64(o
->in2
, o
->in2
, ~mask
);
1299 tcg_gen_and_i64(o
->out
, o
->in1
, o
->in2
);
1301 /* Produce the CC from only the bits manipulated. */
1302 tcg_gen_andi_i64(cc_dst
, o
->out
, mask
);
1303 set_cc_nz_u64(s
, cc_dst
);
1307 static ExitStatus
op_bas(DisasContext
*s
, DisasOps
*o
)
1309 tcg_gen_movi_i64(o
->out
, pc_to_link_info(s
, s
->next_pc
));
1310 if (!TCGV_IS_UNUSED_I64(o
->in2
)) {
1311 tcg_gen_mov_i64(psw_addr
, o
->in2
);
1312 return EXIT_PC_UPDATED
;
1318 static ExitStatus
op_basi(DisasContext
*s
, DisasOps
*o
)
1320 tcg_gen_movi_i64(o
->out
, pc_to_link_info(s
, s
->next_pc
));
1321 return help_goto_direct(s
, s
->pc
+ 2 * get_field(s
->fields
, i2
));
1324 static ExitStatus
op_bc(DisasContext
*s
, DisasOps
*o
)
1326 int m1
= get_field(s
->fields
, m1
);
1327 bool is_imm
= have_field(s
->fields
, i2
);
1328 int imm
= is_imm
? get_field(s
->fields
, i2
) : 0;
1331 disas_jcc(s
, &c
, m1
);
1332 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
1335 static ExitStatus
op_bct32(DisasContext
*s
, DisasOps
*o
)
1337 int r1
= get_field(s
->fields
, r1
);
1338 bool is_imm
= have_field(s
->fields
, i2
);
1339 int imm
= is_imm
? get_field(s
->fields
, i2
) : 0;
1343 c
.cond
= TCG_COND_NE
;
1348 t
= tcg_temp_new_i64();
1349 tcg_gen_subi_i64(t
, regs
[r1
], 1);
1350 store_reg32_i64(r1
, t
);
1351 c
.u
.s32
.a
= tcg_temp_new_i32();
1352 c
.u
.s32
.b
= tcg_const_i32(0);
1353 tcg_gen_trunc_i64_i32(c
.u
.s32
.a
, t
);
1354 tcg_temp_free_i64(t
);
1356 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
1359 static ExitStatus
op_bct64(DisasContext
*s
, DisasOps
*o
)
1361 int r1
= get_field(s
->fields
, r1
);
1362 bool is_imm
= have_field(s
->fields
, i2
);
1363 int imm
= is_imm
? get_field(s
->fields
, i2
) : 0;
1366 c
.cond
= TCG_COND_NE
;
1371 tcg_gen_subi_i64(regs
[r1
], regs
[r1
], 1);
1372 c
.u
.s64
.a
= regs
[r1
];
1373 c
.u
.s64
.b
= tcg_const_i64(0);
1375 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
1378 static ExitStatus
op_bx32(DisasContext
*s
, DisasOps
*o
)
1380 int r1
= get_field(s
->fields
, r1
);
1381 int r3
= get_field(s
->fields
, r3
);
1382 bool is_imm
= have_field(s
->fields
, i2
);
1383 int imm
= is_imm
? get_field(s
->fields
, i2
) : 0;
1387 c
.cond
= (s
->insn
->data
? TCG_COND_LE
: TCG_COND_GT
);
1392 t
= tcg_temp_new_i64();
1393 tcg_gen_add_i64(t
, regs
[r1
], regs
[r3
]);
1394 c
.u
.s32
.a
= tcg_temp_new_i32();
1395 c
.u
.s32
.b
= tcg_temp_new_i32();
1396 tcg_gen_trunc_i64_i32(c
.u
.s32
.a
, t
);
1397 tcg_gen_trunc_i64_i32(c
.u
.s32
.b
, regs
[r3
| 1]);
1398 store_reg32_i64(r1
, t
);
1399 tcg_temp_free_i64(t
);
1401 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
1404 static ExitStatus
op_bx64(DisasContext
*s
, DisasOps
*o
)
1406 int r1
= get_field(s
->fields
, r1
);
1407 int r3
= get_field(s
->fields
, r3
);
1408 bool is_imm
= have_field(s
->fields
, i2
);
1409 int imm
= is_imm
? get_field(s
->fields
, i2
) : 0;
1412 c
.cond
= (s
->insn
->data
? TCG_COND_LE
: TCG_COND_GT
);
1415 if (r1
== (r3
| 1)) {
1416 c
.u
.s64
.b
= load_reg(r3
| 1);
1419 c
.u
.s64
.b
= regs
[r3
| 1];
1423 tcg_gen_add_i64(regs
[r1
], regs
[r1
], regs
[r3
]);
1424 c
.u
.s64
.a
= regs
[r1
];
1427 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
1430 static ExitStatus
op_cj(DisasContext
*s
, DisasOps
*o
)
1432 int imm
, m3
= get_field(s
->fields
, m3
);
1436 /* Bit 3 of the m3 field is reserved and should be zero.
1437 Choose to ignore it wrt the ltgt_cond table above. */
1438 c
.cond
= ltgt_cond
[m3
& 14];
1439 if (s
->insn
->data
) {
1440 c
.cond
= tcg_unsigned_cond(c
.cond
);
1442 c
.is_64
= c
.g1
= c
.g2
= true;
1446 is_imm
= have_field(s
->fields
, i4
);
1448 imm
= get_field(s
->fields
, i4
);
1451 o
->out
= get_address(s
, 0, get_field(s
->fields
, b4
),
1452 get_field(s
->fields
, d4
));
1455 return help_branch(s
, &c
, is_imm
, imm
, o
->out
);
1458 static ExitStatus
op_ceb(DisasContext
*s
, DisasOps
*o
)
1460 gen_helper_ceb(cc_op
, cpu_env
, o
->in1
, o
->in2
);
1465 static ExitStatus
op_cdb(DisasContext
*s
, DisasOps
*o
)
1467 gen_helper_cdb(cc_op
, cpu_env
, o
->in1
, o
->in2
);
1472 static ExitStatus
op_cxb(DisasContext
*s
, DisasOps
*o
)
1474 gen_helper_cxb(cc_op
, cpu_env
, o
->out
, o
->out2
, o
->in1
, o
->in2
);
1479 static ExitStatus
op_cfeb(DisasContext
*s
, DisasOps
*o
)
1481 TCGv_i32 m3
= tcg_const_i32(get_field(s
->fields
, m3
));
1482 gen_helper_cfeb(o
->out
, cpu_env
, o
->in2
, m3
);
1483 tcg_temp_free_i32(m3
);
1484 gen_set_cc_nz_f32(s
, o
->in2
);
1488 static ExitStatus
op_cfdb(DisasContext
*s
, DisasOps
*o
)
1490 TCGv_i32 m3
= tcg_const_i32(get_field(s
->fields
, m3
));
1491 gen_helper_cfdb(o
->out
, cpu_env
, o
->in2
, m3
);
1492 tcg_temp_free_i32(m3
);
1493 gen_set_cc_nz_f64(s
, o
->in2
);
1497 static ExitStatus
op_cfxb(DisasContext
*s
, DisasOps
*o
)
1499 TCGv_i32 m3
= tcg_const_i32(get_field(s
->fields
, m3
));
1500 gen_helper_cfxb(o
->out
, cpu_env
, o
->in1
, o
->in2
, m3
);
1501 tcg_temp_free_i32(m3
);
1502 gen_set_cc_nz_f128(s
, o
->in1
, o
->in2
);
1506 static ExitStatus
op_cgeb(DisasContext
*s
, DisasOps
*o
)
1508 TCGv_i32 m3
= tcg_const_i32(get_field(s
->fields
, m3
));
1509 gen_helper_cgeb(o
->out
, cpu_env
, o
->in2
, m3
);
1510 tcg_temp_free_i32(m3
);
1511 gen_set_cc_nz_f32(s
, o
->in2
);
1515 static ExitStatus
op_cgdb(DisasContext
*s
, DisasOps
*o
)
1517 TCGv_i32 m3
= tcg_const_i32(get_field(s
->fields
, m3
));
1518 gen_helper_cgdb(o
->out
, cpu_env
, o
->in2
, m3
);
1519 tcg_temp_free_i32(m3
);
1520 gen_set_cc_nz_f64(s
, o
->in2
);
1524 static ExitStatus
op_cgxb(DisasContext
*s
, DisasOps
*o
)
1526 TCGv_i32 m3
= tcg_const_i32(get_field(s
->fields
, m3
));
1527 gen_helper_cgxb(o
->out
, cpu_env
, o
->in1
, o
->in2
, m3
);
1528 tcg_temp_free_i32(m3
);
1529 gen_set_cc_nz_f128(s
, o
->in1
, o
->in2
);
1533 static ExitStatus
op_cegb(DisasContext
*s
, DisasOps
*o
)
1535 TCGv_i32 m3
= tcg_const_i32(get_field(s
->fields
, m3
));
1536 gen_helper_cegb(o
->out
, cpu_env
, o
->in2
, m3
);
1537 tcg_temp_free_i32(m3
);
1541 static ExitStatus
op_cdgb(DisasContext
*s
, DisasOps
*o
)
1543 TCGv_i32 m3
= tcg_const_i32(get_field(s
->fields
, m3
));
1544 gen_helper_cdgb(o
->out
, cpu_env
, o
->in2
, m3
);
1545 tcg_temp_free_i32(m3
);
1549 static ExitStatus
op_cxgb(DisasContext
*s
, DisasOps
*o
)
1551 TCGv_i32 m3
= tcg_const_i32(get_field(s
->fields
, m3
));
1552 gen_helper_cxgb(o
->out
, cpu_env
, o
->in2
, m3
);
1553 tcg_temp_free_i32(m3
);
1554 return_low128(o
->out2
);
1558 static ExitStatus
op_cksm(DisasContext
*s
, DisasOps
*o
)
1560 int r2
= get_field(s
->fields
, r2
);
1561 TCGv_i64 len
= tcg_temp_new_i64();
1563 potential_page_fault(s
);
1564 gen_helper_cksm(len
, cpu_env
, o
->in1
, o
->in2
, regs
[r2
+ 1]);
1566 return_low128(o
->out
);
1568 tcg_gen_add_i64(regs
[r2
], regs
[r2
], len
);
1569 tcg_gen_sub_i64(regs
[r2
+ 1], regs
[r2
+ 1], len
);
1570 tcg_temp_free_i64(len
);
1575 static ExitStatus
op_clc(DisasContext
*s
, DisasOps
*o
)
1577 int l
= get_field(s
->fields
, l1
);
1582 tcg_gen_qemu_ld8u(cc_src
, o
->addr1
, get_mem_index(s
));
1583 tcg_gen_qemu_ld8u(cc_dst
, o
->in2
, get_mem_index(s
));
1586 tcg_gen_qemu_ld16u(cc_src
, o
->addr1
, get_mem_index(s
));
1587 tcg_gen_qemu_ld16u(cc_dst
, o
->in2
, get_mem_index(s
));
1590 tcg_gen_qemu_ld32u(cc_src
, o
->addr1
, get_mem_index(s
));
1591 tcg_gen_qemu_ld32u(cc_dst
, o
->in2
, get_mem_index(s
));
1594 tcg_gen_qemu_ld64(cc_src
, o
->addr1
, get_mem_index(s
));
1595 tcg_gen_qemu_ld64(cc_dst
, o
->in2
, get_mem_index(s
));
1598 potential_page_fault(s
);
1599 vl
= tcg_const_i32(l
);
1600 gen_helper_clc(cc_op
, cpu_env
, vl
, o
->addr1
, o
->in2
);
1601 tcg_temp_free_i32(vl
);
1605 gen_op_update2_cc_i64(s
, CC_OP_LTUGTU_64
, cc_src
, cc_dst
);
1609 static ExitStatus
op_clcle(DisasContext
*s
, DisasOps
*o
)
1611 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
1612 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
1613 potential_page_fault(s
);
1614 gen_helper_clcle(cc_op
, cpu_env
, r1
, o
->in2
, r3
);
1615 tcg_temp_free_i32(r1
);
1616 tcg_temp_free_i32(r3
);
1621 static ExitStatus
op_clm(DisasContext
*s
, DisasOps
*o
)
1623 TCGv_i32 m3
= tcg_const_i32(get_field(s
->fields
, m3
));
1624 TCGv_i32 t1
= tcg_temp_new_i32();
1625 tcg_gen_trunc_i64_i32(t1
, o
->in1
);
1626 potential_page_fault(s
);
1627 gen_helper_clm(cc_op
, cpu_env
, t1
, m3
, o
->in2
);
1629 tcg_temp_free_i32(t1
);
1630 tcg_temp_free_i32(m3
);
1634 static ExitStatus
op_clst(DisasContext
*s
, DisasOps
*o
)
1636 potential_page_fault(s
);
1637 gen_helper_clst(o
->in1
, cpu_env
, regs
[0], o
->in1
, o
->in2
);
1639 return_low128(o
->in2
);
1643 static ExitStatus
op_cs(DisasContext
*s
, DisasOps
*o
)
1645 int r3
= get_field(s
->fields
, r3
);
1646 potential_page_fault(s
);
1647 gen_helper_cs(o
->out
, cpu_env
, o
->in1
, o
->in2
, regs
[r3
]);
1652 static ExitStatus
op_csg(DisasContext
*s
, DisasOps
*o
)
1654 int r3
= get_field(s
->fields
, r3
);
1655 potential_page_fault(s
);
1656 gen_helper_csg(o
->out
, cpu_env
, o
->in1
, o
->in2
, regs
[r3
]);
1661 #ifndef CONFIG_USER_ONLY
1662 static ExitStatus
op_csp(DisasContext
*s
, DisasOps
*o
)
1664 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
1665 check_privileged(s
);
1666 gen_helper_csp(cc_op
, cpu_env
, r1
, o
->in2
);
1667 tcg_temp_free_i32(r1
);
1673 static ExitStatus
op_cds(DisasContext
*s
, DisasOps
*o
)
1675 int r3
= get_field(s
->fields
, r3
);
1676 TCGv_i64 in3
= tcg_temp_new_i64();
1677 tcg_gen_deposit_i64(in3
, regs
[r3
+ 1], regs
[r3
], 32, 32);
1678 potential_page_fault(s
);
1679 gen_helper_csg(o
->out
, cpu_env
, o
->in1
, o
->in2
, in3
);
1680 tcg_temp_free_i64(in3
);
1685 static ExitStatus
op_cdsg(DisasContext
*s
, DisasOps
*o
)
1687 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
1688 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
1689 potential_page_fault(s
);
1690 /* XXX rewrite in tcg */
1691 gen_helper_cdsg(cc_op
, cpu_env
, r1
, o
->in2
, r3
);
1696 static ExitStatus
op_cvd(DisasContext
*s
, DisasOps
*o
)
1698 TCGv_i64 t1
= tcg_temp_new_i64();
1699 TCGv_i32 t2
= tcg_temp_new_i32();
1700 tcg_gen_trunc_i64_i32(t2
, o
->in1
);
1701 gen_helper_cvd(t1
, t2
);
1702 tcg_temp_free_i32(t2
);
1703 tcg_gen_qemu_st64(t1
, o
->in2
, get_mem_index(s
));
1704 tcg_temp_free_i64(t1
);
1708 static ExitStatus
op_ct(DisasContext
*s
, DisasOps
*o
)
1710 int m3
= get_field(s
->fields
, m3
);
1711 int lab
= gen_new_label();
1715 /* Bit 3 of the m3 field is reserved and should be zero.
1716 Choose to ignore it wrt the ltgt_cond table above. */
1717 c
= tcg_invert_cond(ltgt_cond
[m3
& 14]);
1718 if (s
->insn
->data
) {
1719 c
= tcg_unsigned_cond(c
);
1721 tcg_gen_brcond_i64(c
, o
->in1
, o
->in2
, lab
);
1723 /* Set DXC to 0xff. */
1724 t
= tcg_temp_new_i32();
1725 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUS390XState
, fpc
));
1726 tcg_gen_ori_i32(t
, t
, 0xff00);
1727 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUS390XState
, fpc
));
1728 tcg_temp_free_i32(t
);
1731 gen_program_exception(s
, PGM_DATA
);
1737 #ifndef CONFIG_USER_ONLY
1738 static ExitStatus
op_diag(DisasContext
*s
, DisasOps
*o
)
1742 check_privileged(s
);
1743 potential_page_fault(s
);
1745 /* We pretend the format is RX_a so that D2 is the field we want. */
1746 tmp
= tcg_const_i32(get_field(s
->fields
, d2
) & 0xfff);
1747 gen_helper_diag(regs
[2], cpu_env
, tmp
, regs
[2], regs
[1]);
1748 tcg_temp_free_i32(tmp
);
1753 static ExitStatus
op_divs32(DisasContext
*s
, DisasOps
*o
)
1755 gen_helper_divs32(o
->out2
, cpu_env
, o
->in1
, o
->in2
);
1756 return_low128(o
->out
);
1760 static ExitStatus
op_divu32(DisasContext
*s
, DisasOps
*o
)
1762 gen_helper_divu32(o
->out2
, cpu_env
, o
->in1
, o
->in2
);
1763 return_low128(o
->out
);
1767 static ExitStatus
op_divs64(DisasContext
*s
, DisasOps
*o
)
1769 gen_helper_divs64(o
->out2
, cpu_env
, o
->in1
, o
->in2
);
1770 return_low128(o
->out
);
1774 static ExitStatus
op_divu64(DisasContext
*s
, DisasOps
*o
)
1776 gen_helper_divu64(o
->out2
, cpu_env
, o
->out
, o
->out2
, o
->in2
);
1777 return_low128(o
->out
);
1781 static ExitStatus
op_deb(DisasContext
*s
, DisasOps
*o
)
1783 gen_helper_deb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
1787 static ExitStatus
op_ddb(DisasContext
*s
, DisasOps
*o
)
1789 gen_helper_ddb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
1793 static ExitStatus
op_dxb(DisasContext
*s
, DisasOps
*o
)
1795 gen_helper_dxb(o
->out
, cpu_env
, o
->out
, o
->out2
, o
->in1
, o
->in2
);
1796 return_low128(o
->out2
);
1800 static ExitStatus
op_ear(DisasContext
*s
, DisasOps
*o
)
1802 int r2
= get_field(s
->fields
, r2
);
1803 tcg_gen_ld32u_i64(o
->out
, cpu_env
, offsetof(CPUS390XState
, aregs
[r2
]));
1807 static ExitStatus
op_efpc(DisasContext
*s
, DisasOps
*o
)
1809 tcg_gen_ld32u_i64(o
->out
, cpu_env
, offsetof(CPUS390XState
, fpc
));
1813 static ExitStatus
op_ex(DisasContext
*s
, DisasOps
*o
)
1815 /* ??? Perhaps a better way to implement EXECUTE is to set a bit in
1816 tb->flags, (ab)use the tb->cs_base field as the address of
1817 the template in memory, and grab 8 bits of tb->flags/cflags for
1818 the contents of the register. We would then recognize all this
1819 in gen_intermediate_code_internal, generating code for exactly
1820 one instruction. This new TB then gets executed normally.
1822 On the other hand, this seems to be mostly used for modifying
1823 MVC inside of memcpy, which needs a helper call anyway. So
1824 perhaps this doesn't bear thinking about any further. */
1831 tmp
= tcg_const_i64(s
->next_pc
);
1832 gen_helper_ex(cc_op
, cpu_env
, cc_op
, o
->in1
, o
->in2
, tmp
);
1833 tcg_temp_free_i64(tmp
);
1839 static ExitStatus
op_flogr(DisasContext
*s
, DisasOps
*o
)
1841 /* We'll use the original input for cc computation, since we get to
1842 compare that against 0, which ought to be better than comparing
1843 the real output against 64. It also lets cc_dst be a convenient
1844 temporary during our computation. */
1845 gen_op_update1_cc_i64(s
, CC_OP_FLOGR
, o
->in2
);
1847 /* R1 = IN ? CLZ(IN) : 64. */
1848 gen_helper_clz(o
->out
, o
->in2
);
1850 /* R1+1 = IN & ~(found bit). Note that we may attempt to shift this
1851 value by 64, which is undefined. But since the shift is 64 iff the
1852 input is zero, we still get the correct result after and'ing. */
1853 tcg_gen_movi_i64(o
->out2
, 0x8000000000000000ull
);
1854 tcg_gen_shr_i64(o
->out2
, o
->out2
, o
->out
);
1855 tcg_gen_andc_i64(o
->out2
, cc_dst
, o
->out2
);
1859 static ExitStatus
op_icm(DisasContext
*s
, DisasOps
*o
)
1861 int m3
= get_field(s
->fields
, m3
);
1862 int pos
, len
, base
= s
->insn
->data
;
1863 TCGv_i64 tmp
= tcg_temp_new_i64();
1868 /* Effectively a 32-bit load. */
1869 tcg_gen_qemu_ld32u(tmp
, o
->in2
, get_mem_index(s
));
1876 /* Effectively a 16-bit load. */
1877 tcg_gen_qemu_ld16u(tmp
, o
->in2
, get_mem_index(s
));
1885 /* Effectively an 8-bit load. */
1886 tcg_gen_qemu_ld8u(tmp
, o
->in2
, get_mem_index(s
));
1891 pos
= base
+ ctz32(m3
) * 8;
1892 tcg_gen_deposit_i64(o
->out
, o
->out
, tmp
, pos
, len
);
1893 ccm
= ((1ull << len
) - 1) << pos
;
1897 /* This is going to be a sequence of loads and inserts. */
1898 pos
= base
+ 32 - 8;
1902 tcg_gen_qemu_ld8u(tmp
, o
->in2
, get_mem_index(s
));
1903 tcg_gen_addi_i64(o
->in2
, o
->in2
, 1);
1904 tcg_gen_deposit_i64(o
->out
, o
->out
, tmp
, pos
, 8);
1907 m3
= (m3
<< 1) & 0xf;
1913 tcg_gen_movi_i64(tmp
, ccm
);
1914 gen_op_update2_cc_i64(s
, CC_OP_ICM
, tmp
, o
->out
);
1915 tcg_temp_free_i64(tmp
);
1919 static ExitStatus
op_insi(DisasContext
*s
, DisasOps
*o
)
1921 int shift
= s
->insn
->data
& 0xff;
1922 int size
= s
->insn
->data
>> 8;
1923 tcg_gen_deposit_i64(o
->out
, o
->in1
, o
->in2
, shift
, size
);
1927 static ExitStatus
op_ipm(DisasContext
*s
, DisasOps
*o
)
1932 tcg_gen_andi_i64(o
->out
, o
->out
, ~0xff000000ull
);
1934 t1
= tcg_temp_new_i64();
1935 tcg_gen_shli_i64(t1
, psw_mask
, 20);
1936 tcg_gen_shri_i64(t1
, t1
, 36);
1937 tcg_gen_or_i64(o
->out
, o
->out
, t1
);
1939 tcg_gen_extu_i32_i64(t1
, cc_op
);
1940 tcg_gen_shli_i64(t1
, t1
, 28);
1941 tcg_gen_or_i64(o
->out
, o
->out
, t1
);
1942 tcg_temp_free_i64(t1
);
1946 #ifndef CONFIG_USER_ONLY
1947 static ExitStatus
op_ipte(DisasContext
*s
, DisasOps
*o
)
1949 check_privileged(s
);
1950 gen_helper_ipte(cpu_env
, o
->in1
, o
->in2
);
1954 static ExitStatus
op_iske(DisasContext
*s
, DisasOps
*o
)
1956 check_privileged(s
);
1957 gen_helper_iske(o
->out
, cpu_env
, o
->in2
);
1962 static ExitStatus
op_ldeb(DisasContext
*s
, DisasOps
*o
)
1964 gen_helper_ldeb(o
->out
, cpu_env
, o
->in2
);
1968 static ExitStatus
op_ledb(DisasContext
*s
, DisasOps
*o
)
1970 gen_helper_ledb(o
->out
, cpu_env
, o
->in2
);
1974 static ExitStatus
op_ldxb(DisasContext
*s
, DisasOps
*o
)
1976 gen_helper_ldxb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
1980 static ExitStatus
op_lexb(DisasContext
*s
, DisasOps
*o
)
1982 gen_helper_lexb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
1986 static ExitStatus
op_lxdb(DisasContext
*s
, DisasOps
*o
)
1988 gen_helper_lxdb(o
->out
, cpu_env
, o
->in2
);
1989 return_low128(o
->out2
);
1993 static ExitStatus
op_lxeb(DisasContext
*s
, DisasOps
*o
)
1995 gen_helper_lxeb(o
->out
, cpu_env
, o
->in2
);
1996 return_low128(o
->out2
);
2000 static ExitStatus
op_llgt(DisasContext
*s
, DisasOps
*o
)
2002 tcg_gen_andi_i64(o
->out
, o
->in2
, 0x7fffffff);
2006 static ExitStatus
op_ld8s(DisasContext
*s
, DisasOps
*o
)
2008 tcg_gen_qemu_ld8s(o
->out
, o
->in2
, get_mem_index(s
));
2012 static ExitStatus
op_ld8u(DisasContext
*s
, DisasOps
*o
)
2014 tcg_gen_qemu_ld8u(o
->out
, o
->in2
, get_mem_index(s
));
2018 static ExitStatus
op_ld16s(DisasContext
*s
, DisasOps
*o
)
2020 tcg_gen_qemu_ld16s(o
->out
, o
->in2
, get_mem_index(s
));
2024 static ExitStatus
op_ld16u(DisasContext
*s
, DisasOps
*o
)
2026 tcg_gen_qemu_ld16u(o
->out
, o
->in2
, get_mem_index(s
));
2030 static ExitStatus
op_ld32s(DisasContext
*s
, DisasOps
*o
)
2032 tcg_gen_qemu_ld32s(o
->out
, o
->in2
, get_mem_index(s
));
2036 static ExitStatus
op_ld32u(DisasContext
*s
, DisasOps
*o
)
2038 tcg_gen_qemu_ld32u(o
->out
, o
->in2
, get_mem_index(s
));
2042 static ExitStatus
op_ld64(DisasContext
*s
, DisasOps
*o
)
2044 tcg_gen_qemu_ld64(o
->out
, o
->in2
, get_mem_index(s
));
2048 #ifndef CONFIG_USER_ONLY
2049 static ExitStatus
op_lctl(DisasContext
*s
, DisasOps
*o
)
2051 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2052 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
2053 check_privileged(s
);
2054 potential_page_fault(s
);
2055 gen_helper_lctl(cpu_env
, r1
, o
->in2
, r3
);
2056 tcg_temp_free_i32(r1
);
2057 tcg_temp_free_i32(r3
);
2061 static ExitStatus
op_lctlg(DisasContext
*s
, DisasOps
*o
)
2063 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2064 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
2065 check_privileged(s
);
2066 potential_page_fault(s
);
2067 gen_helper_lctlg(cpu_env
, r1
, o
->in2
, r3
);
2068 tcg_temp_free_i32(r1
);
2069 tcg_temp_free_i32(r3
);
2072 static ExitStatus
op_lra(DisasContext
*s
, DisasOps
*o
)
2074 check_privileged(s
);
2075 potential_page_fault(s
);
2076 gen_helper_lra(o
->out
, cpu_env
, o
->in2
);
2081 static ExitStatus
op_lpsw(DisasContext
*s
, DisasOps
*o
)
2085 check_privileged(s
);
2087 t1
= tcg_temp_new_i64();
2088 t2
= tcg_temp_new_i64();
2089 tcg_gen_qemu_ld32u(t1
, o
->in2
, get_mem_index(s
));
2090 tcg_gen_addi_i64(o
->in2
, o
->in2
, 4);
2091 tcg_gen_qemu_ld32u(t2
, o
->in2
, get_mem_index(s
));
2092 /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
2093 tcg_gen_shli_i64(t1
, t1
, 32);
2094 gen_helper_load_psw(cpu_env
, t1
, t2
);
2095 tcg_temp_free_i64(t1
);
2096 tcg_temp_free_i64(t2
);
2097 return EXIT_NORETURN
;
2100 static ExitStatus
op_lpswe(DisasContext
*s
, DisasOps
*o
)
2104 check_privileged(s
);
2106 t1
= tcg_temp_new_i64();
2107 t2
= tcg_temp_new_i64();
2108 tcg_gen_qemu_ld64(t1
, o
->in2
, get_mem_index(s
));
2109 tcg_gen_addi_i64(o
->in2
, o
->in2
, 8);
2110 tcg_gen_qemu_ld64(t2
, o
->in2
, get_mem_index(s
));
2111 gen_helper_load_psw(cpu_env
, t1
, t2
);
2112 tcg_temp_free_i64(t1
);
2113 tcg_temp_free_i64(t2
);
2114 return EXIT_NORETURN
;
2118 static ExitStatus
op_lam(DisasContext
*s
, DisasOps
*o
)
2120 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2121 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
2122 potential_page_fault(s
);
2123 gen_helper_lam(cpu_env
, r1
, o
->in2
, r3
);
2124 tcg_temp_free_i32(r1
);
2125 tcg_temp_free_i32(r3
);
2129 static ExitStatus
op_lm32(DisasContext
*s
, DisasOps
*o
)
2131 int r1
= get_field(s
->fields
, r1
);
2132 int r3
= get_field(s
->fields
, r3
);
2133 TCGv_i64 t
= tcg_temp_new_i64();
2134 TCGv_i64 t4
= tcg_const_i64(4);
2137 tcg_gen_qemu_ld32u(t
, o
->in2
, get_mem_index(s
));
2138 store_reg32_i64(r1
, t
);
2142 tcg_gen_add_i64(o
->in2
, o
->in2
, t4
);
2146 tcg_temp_free_i64(t
);
2147 tcg_temp_free_i64(t4
);
2151 static ExitStatus
op_lmh(DisasContext
*s
, DisasOps
*o
)
2153 int r1
= get_field(s
->fields
, r1
);
2154 int r3
= get_field(s
->fields
, r3
);
2155 TCGv_i64 t
= tcg_temp_new_i64();
2156 TCGv_i64 t4
= tcg_const_i64(4);
2159 tcg_gen_qemu_ld32u(t
, o
->in2
, get_mem_index(s
));
2160 store_reg32h_i64(r1
, t
);
2164 tcg_gen_add_i64(o
->in2
, o
->in2
, t4
);
2168 tcg_temp_free_i64(t
);
2169 tcg_temp_free_i64(t4
);
2173 static ExitStatus
op_lm64(DisasContext
*s
, DisasOps
*o
)
2175 int r1
= get_field(s
->fields
, r1
);
2176 int r3
= get_field(s
->fields
, r3
);
2177 TCGv_i64 t8
= tcg_const_i64(8);
2180 tcg_gen_qemu_ld64(regs
[r1
], o
->in2
, get_mem_index(s
));
2184 tcg_gen_add_i64(o
->in2
, o
->in2
, t8
);
2188 tcg_temp_free_i64(t8
);
2192 static ExitStatus
op_mov2(DisasContext
*s
, DisasOps
*o
)
2195 o
->g_out
= o
->g_in2
;
2196 TCGV_UNUSED_I64(o
->in2
);
2201 static ExitStatus
op_movx(DisasContext
*s
, DisasOps
*o
)
2205 o
->g_out
= o
->g_in1
;
2206 o
->g_out2
= o
->g_in2
;
2207 TCGV_UNUSED_I64(o
->in1
);
2208 TCGV_UNUSED_I64(o
->in2
);
2209 o
->g_in1
= o
->g_in2
= false;
2213 static ExitStatus
op_mvc(DisasContext
*s
, DisasOps
*o
)
2215 TCGv_i32 l
= tcg_const_i32(get_field(s
->fields
, l1
));
2216 potential_page_fault(s
);
2217 gen_helper_mvc(cpu_env
, l
, o
->addr1
, o
->in2
);
2218 tcg_temp_free_i32(l
);
2222 static ExitStatus
op_mvcl(DisasContext
*s
, DisasOps
*o
)
2224 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2225 TCGv_i32 r2
= tcg_const_i32(get_field(s
->fields
, r2
));
2226 potential_page_fault(s
);
2227 gen_helper_mvcl(cc_op
, cpu_env
, r1
, r2
);
2228 tcg_temp_free_i32(r1
);
2229 tcg_temp_free_i32(r2
);
2234 static ExitStatus
op_mvcle(DisasContext
*s
, DisasOps
*o
)
2236 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2237 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
2238 potential_page_fault(s
);
2239 gen_helper_mvcle(cc_op
, cpu_env
, r1
, o
->in2
, r3
);
2240 tcg_temp_free_i32(r1
);
2241 tcg_temp_free_i32(r3
);
2246 #ifndef CONFIG_USER_ONLY
2247 static ExitStatus
op_mvcp(DisasContext
*s
, DisasOps
*o
)
2249 int r1
= get_field(s
->fields
, l1
);
2250 check_privileged(s
);
2251 potential_page_fault(s
);
2252 gen_helper_mvcp(cc_op
, cpu_env
, regs
[r1
], o
->addr1
, o
->in2
);
2257 static ExitStatus
op_mvcs(DisasContext
*s
, DisasOps
*o
)
2259 int r1
= get_field(s
->fields
, l1
);
2260 check_privileged(s
);
2261 potential_page_fault(s
);
2262 gen_helper_mvcs(cc_op
, cpu_env
, regs
[r1
], o
->addr1
, o
->in2
);
2268 static ExitStatus
op_mvpg(DisasContext
*s
, DisasOps
*o
)
2270 potential_page_fault(s
);
2271 gen_helper_mvpg(cpu_env
, regs
[0], o
->in1
, o
->in2
);
2276 static ExitStatus
op_mvst(DisasContext
*s
, DisasOps
*o
)
2278 potential_page_fault(s
);
2279 gen_helper_mvst(o
->in1
, cpu_env
, regs
[0], o
->in1
, o
->in2
);
2281 return_low128(o
->in2
);
2285 static ExitStatus
op_mul(DisasContext
*s
, DisasOps
*o
)
2287 tcg_gen_mul_i64(o
->out
, o
->in1
, o
->in2
);
2291 static ExitStatus
op_mul128(DisasContext
*s
, DisasOps
*o
)
2293 gen_helper_mul128(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2294 return_low128(o
->out2
);
2298 static ExitStatus
op_meeb(DisasContext
*s
, DisasOps
*o
)
2300 gen_helper_meeb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2304 static ExitStatus
op_mdeb(DisasContext
*s
, DisasOps
*o
)
2306 gen_helper_mdeb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2310 static ExitStatus
op_mdb(DisasContext
*s
, DisasOps
*o
)
2312 gen_helper_mdb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2316 static ExitStatus
op_mxb(DisasContext
*s
, DisasOps
*o
)
2318 gen_helper_mxb(o
->out
, cpu_env
, o
->out
, o
->out2
, o
->in1
, o
->in2
);
2319 return_low128(o
->out2
);
2323 static ExitStatus
op_mxdb(DisasContext
*s
, DisasOps
*o
)
2325 gen_helper_mxdb(o
->out
, cpu_env
, o
->out
, o
->out2
, o
->in2
);
2326 return_low128(o
->out2
);
2330 static ExitStatus
op_maeb(DisasContext
*s
, DisasOps
*o
)
2332 TCGv_i64 r3
= load_freg32_i64(get_field(s
->fields
, r3
));
2333 gen_helper_maeb(o
->out
, cpu_env
, o
->in1
, o
->in2
, r3
);
2334 tcg_temp_free_i64(r3
);
2338 static ExitStatus
op_madb(DisasContext
*s
, DisasOps
*o
)
2340 int r3
= get_field(s
->fields
, r3
);
2341 gen_helper_madb(o
->out
, cpu_env
, o
->in1
, o
->in2
, fregs
[r3
]);
2345 static ExitStatus
op_mseb(DisasContext
*s
, DisasOps
*o
)
2347 TCGv_i64 r3
= load_freg32_i64(get_field(s
->fields
, r3
));
2348 gen_helper_mseb(o
->out
, cpu_env
, o
->in1
, o
->in2
, r3
);
2349 tcg_temp_free_i64(r3
);
2353 static ExitStatus
op_msdb(DisasContext
*s
, DisasOps
*o
)
2355 int r3
= get_field(s
->fields
, r3
);
2356 gen_helper_msdb(o
->out
, cpu_env
, o
->in1
, o
->in2
, fregs
[r3
]);
2360 static ExitStatus
op_nabs(DisasContext
*s
, DisasOps
*o
)
2362 gen_helper_nabs_i64(o
->out
, o
->in2
);
2366 static ExitStatus
op_nabsf32(DisasContext
*s
, DisasOps
*o
)
2368 tcg_gen_ori_i64(o
->out
, o
->in2
, 0x80000000ull
);
2372 static ExitStatus
op_nabsf64(DisasContext
*s
, DisasOps
*o
)
2374 tcg_gen_ori_i64(o
->out
, o
->in2
, 0x8000000000000000ull
);
2378 static ExitStatus
op_nabsf128(DisasContext
*s
, DisasOps
*o
)
2380 tcg_gen_ori_i64(o
->out
, o
->in1
, 0x8000000000000000ull
);
2381 tcg_gen_mov_i64(o
->out2
, o
->in2
);
2385 static ExitStatus
op_nc(DisasContext
*s
, DisasOps
*o
)
2387 TCGv_i32 l
= tcg_const_i32(get_field(s
->fields
, l1
));
2388 potential_page_fault(s
);
2389 gen_helper_nc(cc_op
, cpu_env
, l
, o
->addr1
, o
->in2
);
2390 tcg_temp_free_i32(l
);
2395 static ExitStatus
op_neg(DisasContext
*s
, DisasOps
*o
)
2397 tcg_gen_neg_i64(o
->out
, o
->in2
);
2401 static ExitStatus
op_negf32(DisasContext
*s
, DisasOps
*o
)
2403 tcg_gen_xori_i64(o
->out
, o
->in2
, 0x80000000ull
);
2407 static ExitStatus
op_negf64(DisasContext
*s
, DisasOps
*o
)
2409 tcg_gen_xori_i64(o
->out
, o
->in2
, 0x8000000000000000ull
);
2413 static ExitStatus
op_negf128(DisasContext
*s
, DisasOps
*o
)
2415 tcg_gen_xori_i64(o
->out
, o
->in1
, 0x8000000000000000ull
);
2416 tcg_gen_mov_i64(o
->out2
, o
->in2
);
2420 static ExitStatus
op_oc(DisasContext
*s
, DisasOps
*o
)
2422 TCGv_i32 l
= tcg_const_i32(get_field(s
->fields
, l1
));
2423 potential_page_fault(s
);
2424 gen_helper_oc(cc_op
, cpu_env
, l
, o
->addr1
, o
->in2
);
2425 tcg_temp_free_i32(l
);
2430 static ExitStatus
op_or(DisasContext
*s
, DisasOps
*o
)
2432 tcg_gen_or_i64(o
->out
, o
->in1
, o
->in2
);
2436 static ExitStatus
op_ori(DisasContext
*s
, DisasOps
*o
)
2438 int shift
= s
->insn
->data
& 0xff;
2439 int size
= s
->insn
->data
>> 8;
2440 uint64_t mask
= ((1ull << size
) - 1) << shift
;
2443 tcg_gen_shli_i64(o
->in2
, o
->in2
, shift
);
2444 tcg_gen_or_i64(o
->out
, o
->in1
, o
->in2
);
2446 /* Produce the CC from only the bits manipulated. */
2447 tcg_gen_andi_i64(cc_dst
, o
->out
, mask
);
2448 set_cc_nz_u64(s
, cc_dst
);
2452 #ifndef CONFIG_USER_ONLY
2453 static ExitStatus
op_ptlb(DisasContext
*s
, DisasOps
*o
)
2455 check_privileged(s
);
2456 gen_helper_ptlb(cpu_env
);
2461 static ExitStatus
op_risbg(DisasContext
*s
, DisasOps
*o
)
2463 int i3
= get_field(s
->fields
, i3
);
2464 int i4
= get_field(s
->fields
, i4
);
2465 int i5
= get_field(s
->fields
, i5
);
2466 int do_zero
= i4
& 0x80;
2467 uint64_t mask
, imask
, pmask
;
2470 /* Adjust the arguments for the specific insn. */
2471 switch (s
->fields
->op2
) {
2472 case 0x55: /* risbg */
2477 case 0x5d: /* risbhg */
2480 pmask
= 0xffffffff00000000ull
;
2482 case 0x51: /* risblg */
2485 pmask
= 0x00000000ffffffffull
;
2491 /* MASK is the set of bits to be inserted from R2.
2492 Take care for I3/I4 wraparound. */
2495 mask
^= pmask
>> i4
>> 1;
2497 mask
|= ~(pmask
>> i4
>> 1);
2501 /* IMASK is the set of bits to be kept from R1. In the case of the high/low
2502 insns, we need to keep the other half of the register. */
2503 imask
= ~mask
| ~pmask
;
2505 if (s
->fields
->op2
== 0x55) {
2512 /* In some cases we can implement this with deposit, which can be more
2513 efficient on some hosts. */
2514 if (~mask
== imask
&& i3
<= i4
) {
2515 if (s
->fields
->op2
== 0x5d) {
2518 /* Note that we rotate the bits to be inserted to the lsb, not to
2519 the position as described in the PoO. */
2522 rot
= (i5
- pos
) & 63;
2528 /* Rotate the input as necessary. */
2529 tcg_gen_rotli_i64(o
->in2
, o
->in2
, rot
);
2531 /* Insert the selected bits into the output. */
2533 tcg_gen_deposit_i64(o
->out
, o
->out
, o
->in2
, pos
, len
);
2534 } else if (imask
== 0) {
2535 tcg_gen_andi_i64(o
->out
, o
->in2
, mask
);
2537 tcg_gen_andi_i64(o
->in2
, o
->in2
, mask
);
2538 tcg_gen_andi_i64(o
->out
, o
->out
, imask
);
2539 tcg_gen_or_i64(o
->out
, o
->out
, o
->in2
);
2544 static ExitStatus
op_rosbg(DisasContext
*s
, DisasOps
*o
)
2546 int i3
= get_field(s
->fields
, i3
);
2547 int i4
= get_field(s
->fields
, i4
);
2548 int i5
= get_field(s
->fields
, i5
);
2551 /* If this is a test-only form, arrange to discard the result. */
2553 o
->out
= tcg_temp_new_i64();
2561 /* MASK is the set of bits to be operated on from R2.
2562 Take care for I3/I4 wraparound. */
2565 mask
^= ~0ull >> i4
>> 1;
2567 mask
|= ~(~0ull >> i4
>> 1);
2570 /* Rotate the input as necessary. */
2571 tcg_gen_rotli_i64(o
->in2
, o
->in2
, i5
);
2574 switch (s
->fields
->op2
) {
2575 case 0x55: /* AND */
2576 tcg_gen_ori_i64(o
->in2
, o
->in2
, ~mask
);
2577 tcg_gen_and_i64(o
->out
, o
->out
, o
->in2
);
2580 tcg_gen_andi_i64(o
->in2
, o
->in2
, mask
);
2581 tcg_gen_or_i64(o
->out
, o
->out
, o
->in2
);
2583 case 0x57: /* XOR */
2584 tcg_gen_andi_i64(o
->in2
, o
->in2
, mask
);
2585 tcg_gen_xor_i64(o
->out
, o
->out
, o
->in2
);
2592 tcg_gen_andi_i64(cc_dst
, o
->out
, mask
);
2593 set_cc_nz_u64(s
, cc_dst
);
2597 static ExitStatus
op_rev16(DisasContext
*s
, DisasOps
*o
)
2599 tcg_gen_bswap16_i64(o
->out
, o
->in2
);
2603 static ExitStatus
op_rev32(DisasContext
*s
, DisasOps
*o
)
2605 tcg_gen_bswap32_i64(o
->out
, o
->in2
);
2609 static ExitStatus
op_rev64(DisasContext
*s
, DisasOps
*o
)
2611 tcg_gen_bswap64_i64(o
->out
, o
->in2
);
2615 static ExitStatus
op_rll32(DisasContext
*s
, DisasOps
*o
)
2617 TCGv_i32 t1
= tcg_temp_new_i32();
2618 TCGv_i32 t2
= tcg_temp_new_i32();
2619 TCGv_i32 to
= tcg_temp_new_i32();
2620 tcg_gen_trunc_i64_i32(t1
, o
->in1
);
2621 tcg_gen_trunc_i64_i32(t2
, o
->in2
);
2622 tcg_gen_rotl_i32(to
, t1
, t2
);
2623 tcg_gen_extu_i32_i64(o
->out
, to
);
2624 tcg_temp_free_i32(t1
);
2625 tcg_temp_free_i32(t2
);
2626 tcg_temp_free_i32(to
);
2630 static ExitStatus
op_rll64(DisasContext
*s
, DisasOps
*o
)
2632 tcg_gen_rotl_i64(o
->out
, o
->in1
, o
->in2
);
2636 #ifndef CONFIG_USER_ONLY
2637 static ExitStatus
op_rrbe(DisasContext
*s
, DisasOps
*o
)
2639 check_privileged(s
);
2640 gen_helper_rrbe(cc_op
, cpu_env
, o
->in2
);
2645 static ExitStatus
op_sacf(DisasContext
*s
, DisasOps
*o
)
2647 check_privileged(s
);
2648 gen_helper_sacf(cpu_env
, o
->in2
);
2649 /* Addressing mode has changed, so end the block. */
2650 return EXIT_PC_STALE
;
2654 static ExitStatus
op_sar(DisasContext
*s
, DisasOps
*o
)
2656 int r1
= get_field(s
->fields
, r1
);
2657 tcg_gen_st32_i64(o
->in2
, cpu_env
, offsetof(CPUS390XState
, aregs
[r1
]));
2661 static ExitStatus
op_seb(DisasContext
*s
, DisasOps
*o
)
2663 gen_helper_seb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2667 static ExitStatus
op_sdb(DisasContext
*s
, DisasOps
*o
)
2669 gen_helper_sdb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2673 static ExitStatus
op_sxb(DisasContext
*s
, DisasOps
*o
)
2675 gen_helper_sxb(o
->out
, cpu_env
, o
->out
, o
->out2
, o
->in1
, o
->in2
);
2676 return_low128(o
->out2
);
2680 static ExitStatus
op_sqeb(DisasContext
*s
, DisasOps
*o
)
2682 gen_helper_sqeb(o
->out
, cpu_env
, o
->in2
);
2686 static ExitStatus
op_sqdb(DisasContext
*s
, DisasOps
*o
)
2688 gen_helper_sqdb(o
->out
, cpu_env
, o
->in2
);
2692 static ExitStatus
op_sqxb(DisasContext
*s
, DisasOps
*o
)
2694 gen_helper_sqxb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2695 return_low128(o
->out2
);
2699 #ifndef CONFIG_USER_ONLY
2700 static ExitStatus
op_servc(DisasContext
*s
, DisasOps
*o
)
2702 check_privileged(s
);
2703 potential_page_fault(s
);
2704 gen_helper_servc(cc_op
, cpu_env
, o
->in2
, o
->in1
);
2709 static ExitStatus
op_sigp(DisasContext
*s
, DisasOps
*o
)
2711 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2712 check_privileged(s
);
2713 potential_page_fault(s
);
2714 gen_helper_sigp(cc_op
, cpu_env
, o
->in2
, r1
, o
->in1
);
2715 tcg_temp_free_i32(r1
);
2720 static ExitStatus
op_sla(DisasContext
*s
, DisasOps
*o
)
2722 uint64_t sign
= 1ull << s
->insn
->data
;
2723 enum cc_op cco
= s
->insn
->data
== 31 ? CC_OP_SLA_32
: CC_OP_SLA_64
;
2724 gen_op_update2_cc_i64(s
, cco
, o
->in1
, o
->in2
);
2725 tcg_gen_shl_i64(o
->out
, o
->in1
, o
->in2
);
2726 /* The arithmetic left shift is curious in that it does not affect
2727 the sign bit. Copy that over from the source unchanged. */
2728 tcg_gen_andi_i64(o
->out
, o
->out
, ~sign
);
2729 tcg_gen_andi_i64(o
->in1
, o
->in1
, sign
);
2730 tcg_gen_or_i64(o
->out
, o
->out
, o
->in1
);
2734 static ExitStatus
op_sll(DisasContext
*s
, DisasOps
*o
)
2736 tcg_gen_shl_i64(o
->out
, o
->in1
, o
->in2
);
2740 static ExitStatus
op_sra(DisasContext
*s
, DisasOps
*o
)
2742 tcg_gen_sar_i64(o
->out
, o
->in1
, o
->in2
);
2746 static ExitStatus
op_srl(DisasContext
*s
, DisasOps
*o
)
2748 tcg_gen_shr_i64(o
->out
, o
->in1
, o
->in2
);
2752 static ExitStatus
op_sfpc(DisasContext
*s
, DisasOps
*o
)
2754 gen_helper_sfpc(cpu_env
, o
->in2
);
2758 #ifndef CONFIG_USER_ONLY
2759 static ExitStatus
op_spka(DisasContext
*s
, DisasOps
*o
)
2761 check_privileged(s
);
2762 tcg_gen_shri_i64(o
->in2
, o
->in2
, 4);
2763 tcg_gen_deposit_i64(psw_mask
, psw_mask
, o
->in2
, PSW_SHIFT_KEY
- 4, 4);
2767 static ExitStatus
op_sske(DisasContext
*s
, DisasOps
*o
)
2769 check_privileged(s
);
2770 gen_helper_sske(cpu_env
, o
->in1
, o
->in2
);
2774 static ExitStatus
op_ssm(DisasContext
*s
, DisasOps
*o
)
2776 check_privileged(s
);
2777 tcg_gen_deposit_i64(psw_mask
, psw_mask
, o
->in2
, 56, 8);
2781 static ExitStatus
op_stap(DisasContext
*s
, DisasOps
*o
)
2783 check_privileged(s
);
2784 /* ??? Surely cpu address != cpu number. In any case the previous
2785 version of this stored more than the required half-word, so it
2786 is unlikely this has ever been tested. */
2787 tcg_gen_ld32u_i64(o
->out
, cpu_env
, offsetof(CPUS390XState
, cpu_num
));
2791 static ExitStatus
op_stck(DisasContext
*s
, DisasOps
*o
)
2793 gen_helper_stck(o
->out
, cpu_env
);
2794 /* ??? We don't implement clock states. */
2795 gen_op_movi_cc(s
, 0);
2799 static ExitStatus
op_stcke(DisasContext
*s
, DisasOps
*o
)
2801 TCGv_i64 c1
= tcg_temp_new_i64();
2802 TCGv_i64 c2
= tcg_temp_new_i64();
2803 gen_helper_stck(c1
, cpu_env
);
2804 /* Shift the 64-bit value into its place as a zero-extended
2805 104-bit value. Note that "bit positions 64-103 are always
2806 non-zero so that they compare differently to STCK"; we set
2807 the least significant bit to 1. */
2808 tcg_gen_shli_i64(c2
, c1
, 56);
2809 tcg_gen_shri_i64(c1
, c1
, 8);
2810 tcg_gen_ori_i64(c2
, c2
, 0x10000);
2811 tcg_gen_qemu_st64(c1
, o
->in2
, get_mem_index(s
));
2812 tcg_gen_addi_i64(o
->in2
, o
->in2
, 8);
2813 tcg_gen_qemu_st64(c2
, o
->in2
, get_mem_index(s
));
2814 tcg_temp_free_i64(c1
);
2815 tcg_temp_free_i64(c2
);
2816 /* ??? We don't implement clock states. */
2817 gen_op_movi_cc(s
, 0);
2821 static ExitStatus
op_sckc(DisasContext
*s
, DisasOps
*o
)
2823 check_privileged(s
);
2824 gen_helper_sckc(cpu_env
, o
->in2
);
2828 static ExitStatus
op_stckc(DisasContext
*s
, DisasOps
*o
)
2830 check_privileged(s
);
2831 gen_helper_stckc(o
->out
, cpu_env
);
2835 static ExitStatus
op_stctg(DisasContext
*s
, DisasOps
*o
)
2837 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2838 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
2839 check_privileged(s
);
2840 potential_page_fault(s
);
2841 gen_helper_stctg(cpu_env
, r1
, o
->in2
, r3
);
2842 tcg_temp_free_i32(r1
);
2843 tcg_temp_free_i32(r3
);
2847 static ExitStatus
op_stctl(DisasContext
*s
, DisasOps
*o
)
2849 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2850 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
2851 check_privileged(s
);
2852 potential_page_fault(s
);
2853 gen_helper_stctl(cpu_env
, r1
, o
->in2
, r3
);
2854 tcg_temp_free_i32(r1
);
2855 tcg_temp_free_i32(r3
);
2859 static ExitStatus
op_stidp(DisasContext
*s
, DisasOps
*o
)
2861 check_privileged(s
);
2862 tcg_gen_ld32u_i64(o
->out
, cpu_env
, offsetof(CPUS390XState
, cpu_num
));
2866 static ExitStatus
op_spt(DisasContext
*s
, DisasOps
*o
)
2868 check_privileged(s
);
2869 gen_helper_spt(cpu_env
, o
->in2
);
2873 static ExitStatus
op_stfl(DisasContext
*s
, DisasOps
*o
)
2876 /* We really ought to have more complete indication of facilities
2877 that we implement. Address this when STFLE is implemented. */
2878 check_privileged(s
);
2879 f
= tcg_const_i64(0xc0000000);
2880 a
= tcg_const_i64(200);
2881 tcg_gen_qemu_st32(f
, a
, get_mem_index(s
));
2882 tcg_temp_free_i64(f
);
2883 tcg_temp_free_i64(a
);
2887 static ExitStatus
op_stpt(DisasContext
*s
, DisasOps
*o
)
2889 check_privileged(s
);
2890 gen_helper_stpt(o
->out
, cpu_env
);
2894 static ExitStatus
op_stsi(DisasContext
*s
, DisasOps
*o
)
2896 check_privileged(s
);
2897 potential_page_fault(s
);
2898 gen_helper_stsi(cc_op
, cpu_env
, o
->in2
, regs
[0], regs
[1]);
2903 static ExitStatus
op_spx(DisasContext
*s
, DisasOps
*o
)
2905 check_privileged(s
);
2906 gen_helper_spx(cpu_env
, o
->in2
);
2910 static ExitStatus
op_subchannel(DisasContext
*s
, DisasOps
*o
)
2912 check_privileged(s
);
2913 /* Not operational. */
2914 gen_op_movi_cc(s
, 3);
2918 static ExitStatus
op_stpx(DisasContext
*s
, DisasOps
*o
)
2920 check_privileged(s
);
2921 tcg_gen_ld_i64(o
->out
, cpu_env
, offsetof(CPUS390XState
, psa
));
2922 tcg_gen_andi_i64(o
->out
, o
->out
, 0x7fffe000);
2926 static ExitStatus
op_stnosm(DisasContext
*s
, DisasOps
*o
)
2928 uint64_t i2
= get_field(s
->fields
, i2
);
2931 check_privileged(s
);
2933 /* It is important to do what the instruction name says: STORE THEN.
2934 If we let the output hook perform the store then if we fault and
2935 restart, we'll have the wrong SYSTEM MASK in place. */
2936 t
= tcg_temp_new_i64();
2937 tcg_gen_shri_i64(t
, psw_mask
, 56);
2938 tcg_gen_qemu_st8(t
, o
->addr1
, get_mem_index(s
));
2939 tcg_temp_free_i64(t
);
2941 if (s
->fields
->op
== 0xac) {
2942 tcg_gen_andi_i64(psw_mask
, psw_mask
,
2943 (i2
<< 56) | 0x00ffffffffffffffull
);
2945 tcg_gen_ori_i64(psw_mask
, psw_mask
, i2
<< 56);
2950 static ExitStatus
op_stura(DisasContext
*s
, DisasOps
*o
)
2952 check_privileged(s
);
2953 potential_page_fault(s
);
2954 gen_helper_stura(cpu_env
, o
->in2
, o
->in1
);
2959 static ExitStatus
op_st8(DisasContext
*s
, DisasOps
*o
)
2961 tcg_gen_qemu_st8(o
->in1
, o
->in2
, get_mem_index(s
));
2965 static ExitStatus
op_st16(DisasContext
*s
, DisasOps
*o
)
2967 tcg_gen_qemu_st16(o
->in1
, o
->in2
, get_mem_index(s
));
2971 static ExitStatus
op_st32(DisasContext
*s
, DisasOps
*o
)
2973 tcg_gen_qemu_st32(o
->in1
, o
->in2
, get_mem_index(s
));
2977 static ExitStatus
op_st64(DisasContext
*s
, DisasOps
*o
)
2979 tcg_gen_qemu_st64(o
->in1
, o
->in2
, get_mem_index(s
));
2983 static ExitStatus
op_stam(DisasContext
*s
, DisasOps
*o
)
2985 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2986 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
2987 potential_page_fault(s
);
2988 gen_helper_stam(cpu_env
, r1
, o
->in2
, r3
);
2989 tcg_temp_free_i32(r1
);
2990 tcg_temp_free_i32(r3
);
2994 static ExitStatus
op_stcm(DisasContext
*s
, DisasOps
*o
)
2996 int m3
= get_field(s
->fields
, m3
);
2997 int pos
, base
= s
->insn
->data
;
2998 TCGv_i64 tmp
= tcg_temp_new_i64();
3000 pos
= base
+ ctz32(m3
) * 8;
3003 /* Effectively a 32-bit store. */
3004 tcg_gen_shri_i64(tmp
, o
->in1
, pos
);
3005 tcg_gen_qemu_st32(tmp
, o
->in2
, get_mem_index(s
));
3011 /* Effectively a 16-bit store. */
3012 tcg_gen_shri_i64(tmp
, o
->in1
, pos
);
3013 tcg_gen_qemu_st16(tmp
, o
->in2
, get_mem_index(s
));
3020 /* Effectively an 8-bit store. */
3021 tcg_gen_shri_i64(tmp
, o
->in1
, pos
);
3022 tcg_gen_qemu_st8(tmp
, o
->in2
, get_mem_index(s
));
3026 /* This is going to be a sequence of shifts and stores. */
3027 pos
= base
+ 32 - 8;
3030 tcg_gen_shri_i64(tmp
, o
->in1
, pos
);
3031 tcg_gen_qemu_st8(tmp
, o
->in2
, get_mem_index(s
));
3032 tcg_gen_addi_i64(o
->in2
, o
->in2
, 1);
3034 m3
= (m3
<< 1) & 0xf;
3039 tcg_temp_free_i64(tmp
);
3043 static ExitStatus
op_stm(DisasContext
*s
, DisasOps
*o
)
3045 int r1
= get_field(s
->fields
, r1
);
3046 int r3
= get_field(s
->fields
, r3
);
3047 int size
= s
->insn
->data
;
3048 TCGv_i64 tsize
= tcg_const_i64(size
);
3052 tcg_gen_qemu_st64(regs
[r1
], o
->in2
, get_mem_index(s
));
3054 tcg_gen_qemu_st32(regs
[r1
], o
->in2
, get_mem_index(s
));
3059 tcg_gen_add_i64(o
->in2
, o
->in2
, tsize
);
3063 tcg_temp_free_i64(tsize
);
3067 static ExitStatus
op_stmh(DisasContext
*s
, DisasOps
*o
)
3069 int r1
= get_field(s
->fields
, r1
);
3070 int r3
= get_field(s
->fields
, r3
);
3071 TCGv_i64 t
= tcg_temp_new_i64();
3072 TCGv_i64 t4
= tcg_const_i64(4);
3073 TCGv_i64 t32
= tcg_const_i64(32);
3076 tcg_gen_shl_i64(t
, regs
[r1
], t32
);
3077 tcg_gen_qemu_st32(t
, o
->in2
, get_mem_index(s
));
3081 tcg_gen_add_i64(o
->in2
, o
->in2
, t4
);
3085 tcg_temp_free_i64(t
);
3086 tcg_temp_free_i64(t4
);
3087 tcg_temp_free_i64(t32
);
3091 static ExitStatus
op_srst(DisasContext
*s
, DisasOps
*o
)
3093 potential_page_fault(s
);
3094 gen_helper_srst(o
->in1
, cpu_env
, regs
[0], o
->in1
, o
->in2
);
3096 return_low128(o
->in2
);
3100 static ExitStatus
op_sub(DisasContext
*s
, DisasOps
*o
)
3102 tcg_gen_sub_i64(o
->out
, o
->in1
, o
->in2
);
3106 static ExitStatus
op_subb(DisasContext
*s
, DisasOps
*o
)
3111 tcg_gen_not_i64(o
->in2
, o
->in2
);
3112 tcg_gen_add_i64(o
->out
, o
->in1
, o
->in2
);
3114 /* XXX possible optimization point */
3116 cc
= tcg_temp_new_i64();
3117 tcg_gen_extu_i32_i64(cc
, cc_op
);
3118 tcg_gen_shri_i64(cc
, cc
, 1);
3119 tcg_gen_add_i64(o
->out
, o
->out
, cc
);
3120 tcg_temp_free_i64(cc
);
3124 static ExitStatus
op_svc(DisasContext
*s
, DisasOps
*o
)
3131 t
= tcg_const_i32(get_field(s
->fields
, i1
) & 0xff);
3132 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUS390XState
, int_svc_code
));
3133 tcg_temp_free_i32(t
);
3135 t
= tcg_const_i32(s
->next_pc
- s
->pc
);
3136 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUS390XState
, int_svc_ilen
));
3137 tcg_temp_free_i32(t
);
3139 gen_exception(EXCP_SVC
);
3140 return EXIT_NORETURN
;
3143 static ExitStatus
op_tceb(DisasContext
*s
, DisasOps
*o
)
3145 gen_helper_tceb(cc_op
, o
->in1
, o
->in2
);
3150 static ExitStatus
op_tcdb(DisasContext
*s
, DisasOps
*o
)
3152 gen_helper_tcdb(cc_op
, o
->in1
, o
->in2
);
3157 static ExitStatus
op_tcxb(DisasContext
*s
, DisasOps
*o
)
3159 gen_helper_tcxb(cc_op
, o
->out
, o
->out2
, o
->in2
);
3164 #ifndef CONFIG_USER_ONLY
3165 static ExitStatus
op_tprot(DisasContext
*s
, DisasOps
*o
)
3167 potential_page_fault(s
);
3168 gen_helper_tprot(cc_op
, o
->addr1
, o
->in2
);
3174 static ExitStatus
op_tr(DisasContext
*s
, DisasOps
*o
)
3176 TCGv_i32 l
= tcg_const_i32(get_field(s
->fields
, l1
));
3177 potential_page_fault(s
);
3178 gen_helper_tr(cpu_env
, l
, o
->addr1
, o
->in2
);
3179 tcg_temp_free_i32(l
);
3184 static ExitStatus
op_unpk(DisasContext
*s
, DisasOps
*o
)
3186 TCGv_i32 l
= tcg_const_i32(get_field(s
->fields
, l1
));
3187 potential_page_fault(s
);
3188 gen_helper_unpk(cpu_env
, l
, o
->addr1
, o
->in2
);
3189 tcg_temp_free_i32(l
);
3193 static ExitStatus
op_xc(DisasContext
*s
, DisasOps
*o
)
3195 TCGv_i32 l
= tcg_const_i32(get_field(s
->fields
, l1
));
3196 potential_page_fault(s
);
3197 gen_helper_xc(cc_op
, cpu_env
, l
, o
->addr1
, o
->in2
);
3198 tcg_temp_free_i32(l
);
3203 static ExitStatus
op_xor(DisasContext
*s
, DisasOps
*o
)
3205 tcg_gen_xor_i64(o
->out
, o
->in1
, o
->in2
);
3209 static ExitStatus
op_xori(DisasContext
*s
, DisasOps
*o
)
3211 int shift
= s
->insn
->data
& 0xff;
3212 int size
= s
->insn
->data
>> 8;
3213 uint64_t mask
= ((1ull << size
) - 1) << shift
;
3216 tcg_gen_shli_i64(o
->in2
, o
->in2
, shift
);
3217 tcg_gen_xor_i64(o
->out
, o
->in1
, o
->in2
);
3219 /* Produce the CC from only the bits manipulated. */
3220 tcg_gen_andi_i64(cc_dst
, o
->out
, mask
);
3221 set_cc_nz_u64(s
, cc_dst
);
3225 static ExitStatus
op_zero(DisasContext
*s
, DisasOps
*o
)
3227 o
->out
= tcg_const_i64(0);
3231 static ExitStatus
op_zero2(DisasContext
*s
, DisasOps
*o
)
3233 o
->out
= tcg_const_i64(0);
3239 /* ====================================================================== */
3240 /* The "Cc OUTput" generators. Given the generated output (and in some cases
3241 the original inputs), update the various cc data structures in order to
3242 be able to compute the new condition code. */
3244 static void cout_abs32(DisasContext
*s
, DisasOps
*o
)
3246 gen_op_update1_cc_i64(s
, CC_OP_ABS_32
, o
->out
);
3249 static void cout_abs64(DisasContext
*s
, DisasOps
*o
)
3251 gen_op_update1_cc_i64(s
, CC_OP_ABS_64
, o
->out
);
3254 static void cout_adds32(DisasContext
*s
, DisasOps
*o
)
3256 gen_op_update3_cc_i64(s
, CC_OP_ADD_32
, o
->in1
, o
->in2
, o
->out
);
3259 static void cout_adds64(DisasContext
*s
, DisasOps
*o
)
3261 gen_op_update3_cc_i64(s
, CC_OP_ADD_64
, o
->in1
, o
->in2
, o
->out
);
3264 static void cout_addu32(DisasContext
*s
, DisasOps
*o
)
3266 gen_op_update3_cc_i64(s
, CC_OP_ADDU_32
, o
->in1
, o
->in2
, o
->out
);
3269 static void cout_addu64(DisasContext
*s
, DisasOps
*o
)
3271 gen_op_update3_cc_i64(s
, CC_OP_ADDU_64
, o
->in1
, o
->in2
, o
->out
);
3274 static void cout_addc32(DisasContext
*s
, DisasOps
*o
)
3276 gen_op_update3_cc_i64(s
, CC_OP_ADDC_32
, o
->in1
, o
->in2
, o
->out
);
3279 static void cout_addc64(DisasContext
*s
, DisasOps
*o
)
3281 gen_op_update3_cc_i64(s
, CC_OP_ADDC_64
, o
->in1
, o
->in2
, o
->out
);
3284 static void cout_cmps32(DisasContext
*s
, DisasOps
*o
)
3286 gen_op_update2_cc_i64(s
, CC_OP_LTGT_32
, o
->in1
, o
->in2
);
3289 static void cout_cmps64(DisasContext
*s
, DisasOps
*o
)
3291 gen_op_update2_cc_i64(s
, CC_OP_LTGT_64
, o
->in1
, o
->in2
);
3294 static void cout_cmpu32(DisasContext
*s
, DisasOps
*o
)
3296 gen_op_update2_cc_i64(s
, CC_OP_LTUGTU_32
, o
->in1
, o
->in2
);
3299 static void cout_cmpu64(DisasContext
*s
, DisasOps
*o
)
3301 gen_op_update2_cc_i64(s
, CC_OP_LTUGTU_64
, o
->in1
, o
->in2
);
3304 static void cout_f32(DisasContext
*s
, DisasOps
*o
)
3306 gen_op_update1_cc_i64(s
, CC_OP_NZ_F32
, o
->out
);
3309 static void cout_f64(DisasContext
*s
, DisasOps
*o
)
3311 gen_op_update1_cc_i64(s
, CC_OP_NZ_F64
, o
->out
);
3314 static void cout_f128(DisasContext
*s
, DisasOps
*o
)
3316 gen_op_update2_cc_i64(s
, CC_OP_NZ_F128
, o
->out
, o
->out2
);
3319 static void cout_nabs32(DisasContext
*s
, DisasOps
*o
)
3321 gen_op_update1_cc_i64(s
, CC_OP_NABS_32
, o
->out
);
3324 static void cout_nabs64(DisasContext
*s
, DisasOps
*o
)
3326 gen_op_update1_cc_i64(s
, CC_OP_NABS_64
, o
->out
);
3329 static void cout_neg32(DisasContext
*s
, DisasOps
*o
)
3331 gen_op_update1_cc_i64(s
, CC_OP_COMP_32
, o
->out
);
3334 static void cout_neg64(DisasContext
*s
, DisasOps
*o
)
3336 gen_op_update1_cc_i64(s
, CC_OP_COMP_64
, o
->out
);
3339 static void cout_nz32(DisasContext
*s
, DisasOps
*o
)
3341 tcg_gen_ext32u_i64(cc_dst
, o
->out
);
3342 gen_op_update1_cc_i64(s
, CC_OP_NZ
, cc_dst
);
3345 static void cout_nz64(DisasContext
*s
, DisasOps
*o
)
3347 gen_op_update1_cc_i64(s
, CC_OP_NZ
, o
->out
);
3350 static void cout_s32(DisasContext
*s
, DisasOps
*o
)
3352 gen_op_update1_cc_i64(s
, CC_OP_LTGT0_32
, o
->out
);
3355 static void cout_s64(DisasContext
*s
, DisasOps
*o
)
3357 gen_op_update1_cc_i64(s
, CC_OP_LTGT0_64
, o
->out
);
3360 static void cout_subs32(DisasContext
*s
, DisasOps
*o
)
3362 gen_op_update3_cc_i64(s
, CC_OP_SUB_32
, o
->in1
, o
->in2
, o
->out
);
3365 static void cout_subs64(DisasContext
*s
, DisasOps
*o
)
3367 gen_op_update3_cc_i64(s
, CC_OP_SUB_64
, o
->in1
, o
->in2
, o
->out
);
3370 static void cout_subu32(DisasContext
*s
, DisasOps
*o
)
3372 gen_op_update3_cc_i64(s
, CC_OP_SUBU_32
, o
->in1
, o
->in2
, o
->out
);
3375 static void cout_subu64(DisasContext
*s
, DisasOps
*o
)
3377 gen_op_update3_cc_i64(s
, CC_OP_SUBU_64
, o
->in1
, o
->in2
, o
->out
);
3380 static void cout_subb32(DisasContext
*s
, DisasOps
*o
)
3382 gen_op_update3_cc_i64(s
, CC_OP_SUBB_32
, o
->in1
, o
->in2
, o
->out
);
3385 static void cout_subb64(DisasContext
*s
, DisasOps
*o
)
3387 gen_op_update3_cc_i64(s
, CC_OP_SUBB_64
, o
->in1
, o
->in2
, o
->out
);
3390 static void cout_tm32(DisasContext
*s
, DisasOps
*o
)
3392 gen_op_update2_cc_i64(s
, CC_OP_TM_32
, o
->in1
, o
->in2
);
3395 static void cout_tm64(DisasContext
*s
, DisasOps
*o
)
3397 gen_op_update2_cc_i64(s
, CC_OP_TM_64
, o
->in1
, o
->in2
);
3400 /* ====================================================================== */
3401 /* The "PREPeration" generators. These initialize the DisasOps.OUT fields
3402 with the TCG register to which we will write. Used in combination with
3403 the "wout" generators, in some cases we need a new temporary, and in
3404 some cases we can write to a TCG global. */
3406 static void prep_new(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3408 o
->out
= tcg_temp_new_i64();
3411 static void prep_new_P(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3413 o
->out
= tcg_temp_new_i64();
3414 o
->out2
= tcg_temp_new_i64();
3417 static void prep_r1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3419 o
->out
= regs
[get_field(f
, r1
)];
3423 static void prep_r1_P(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3425 /* ??? Specification exception: r1 must be even. */
3426 int r1
= get_field(f
, r1
);
3428 o
->out2
= regs
[(r1
+ 1) & 15];
3429 o
->g_out
= o
->g_out2
= true;
3432 static void prep_f1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3434 o
->out
= fregs
[get_field(f
, r1
)];
3438 static void prep_x1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3440 /* ??? Specification exception: r1 must be < 14. */
3441 int r1
= get_field(f
, r1
);
3443 o
->out2
= fregs
[(r1
+ 2) & 15];
3444 o
->g_out
= o
->g_out2
= true;
3447 /* ====================================================================== */
3448 /* The "Write OUTput" generators. These generally perform some non-trivial
3449 copy of data to TCG globals, or to main memory. The trivial cases are
3450 generally handled by having a "prep" generator install the TCG global
3451 as the destination of the operation. */
3453 static void wout_r1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3455 store_reg(get_field(f
, r1
), o
->out
);
3458 static void wout_r1_8(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3460 int r1
= get_field(f
, r1
);
3461 tcg_gen_deposit_i64(regs
[r1
], regs
[r1
], o
->out
, 0, 8);
3464 static void wout_r1_16(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3466 int r1
= get_field(f
, r1
);
3467 tcg_gen_deposit_i64(regs
[r1
], regs
[r1
], o
->out
, 0, 16);
3470 static void wout_r1_32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3472 store_reg32_i64(get_field(f
, r1
), o
->out
);
3475 static void wout_r1_P32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3477 /* ??? Specification exception: r1 must be even. */
3478 int r1
= get_field(f
, r1
);
3479 store_reg32_i64(r1
, o
->out
);
3480 store_reg32_i64((r1
+ 1) & 15, o
->out2
);
3483 static void wout_r1_D32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3485 /* ??? Specification exception: r1 must be even. */
3486 int r1
= get_field(f
, r1
);
3487 store_reg32_i64((r1
+ 1) & 15, o
->out
);
3488 tcg_gen_shri_i64(o
->out
, o
->out
, 32);
3489 store_reg32_i64(r1
, o
->out
);
3492 static void wout_e1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3494 store_freg32_i64(get_field(f
, r1
), o
->out
);
3497 static void wout_f1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3499 store_freg(get_field(f
, r1
), o
->out
);
3502 static void wout_x1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3504 /* ??? Specification exception: r1 must be < 14. */
3505 int f1
= get_field(s
->fields
, r1
);
3506 store_freg(f1
, o
->out
);
3507 store_freg((f1
+ 2) & 15, o
->out2
);
3510 static void wout_cond_r1r2_32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3512 if (get_field(f
, r1
) != get_field(f
, r2
)) {
3513 store_reg32_i64(get_field(f
, r1
), o
->out
);
3517 static void wout_cond_e1e2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3519 if (get_field(f
, r1
) != get_field(f
, r2
)) {
3520 store_freg32_i64(get_field(f
, r1
), o
->out
);
3524 static void wout_m1_8(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3526 tcg_gen_qemu_st8(o
->out
, o
->addr1
, get_mem_index(s
));
3529 static void wout_m1_16(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3531 tcg_gen_qemu_st16(o
->out
, o
->addr1
, get_mem_index(s
));
3534 static void wout_m1_32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3536 tcg_gen_qemu_st32(o
->out
, o
->addr1
, get_mem_index(s
));
3539 static void wout_m1_64(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3541 tcg_gen_qemu_st64(o
->out
, o
->addr1
, get_mem_index(s
));
3544 static void wout_m2_32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3546 tcg_gen_qemu_st32(o
->out
, o
->in2
, get_mem_index(s
));
3549 /* ====================================================================== */
3550 /* The "INput 1" generators. These load the first operand to an insn. */
3552 static void in1_r1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3554 o
->in1
= load_reg(get_field(f
, r1
));
3557 static void in1_r1_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3559 o
->in1
= regs
[get_field(f
, r1
)];
3563 static void in1_r1_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3565 o
->in1
= tcg_temp_new_i64();
3566 tcg_gen_ext32s_i64(o
->in1
, regs
[get_field(f
, r1
)]);
3569 static void in1_r1_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3571 o
->in1
= tcg_temp_new_i64();
3572 tcg_gen_ext32u_i64(o
->in1
, regs
[get_field(f
, r1
)]);
3575 static void in1_r1_sr32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3577 o
->in1
= tcg_temp_new_i64();
3578 tcg_gen_shri_i64(o
->in1
, regs
[get_field(f
, r1
)], 32);
3581 static void in1_r1p1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3583 /* ??? Specification exception: r1 must be even. */
3584 int r1
= get_field(f
, r1
);
3585 o
->in1
= load_reg((r1
+ 1) & 15);
3588 static void in1_r1p1_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3590 /* ??? Specification exception: r1 must be even. */
3591 int r1
= get_field(f
, r1
);
3592 o
->in1
= tcg_temp_new_i64();
3593 tcg_gen_ext32s_i64(o
->in1
, regs
[(r1
+ 1) & 15]);
3596 static void in1_r1p1_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3598 /* ??? Specification exception: r1 must be even. */
3599 int r1
= get_field(f
, r1
);
3600 o
->in1
= tcg_temp_new_i64();
3601 tcg_gen_ext32u_i64(o
->in1
, regs
[(r1
+ 1) & 15]);
3604 static void in1_r1_D32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3606 /* ??? Specification exception: r1 must be even. */
3607 int r1
= get_field(f
, r1
);
3608 o
->in1
= tcg_temp_new_i64();
3609 tcg_gen_concat32_i64(o
->in1
, regs
[r1
+ 1], regs
[r1
]);
3612 static void in1_r2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3614 o
->in1
= load_reg(get_field(f
, r2
));
3617 static void in1_r3(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3619 o
->in1
= load_reg(get_field(f
, r3
));
3622 static void in1_r3_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3624 o
->in1
= regs
[get_field(f
, r3
)];
3628 static void in1_r3_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3630 o
->in1
= tcg_temp_new_i64();
3631 tcg_gen_ext32s_i64(o
->in1
, regs
[get_field(f
, r3
)]);
3634 static void in1_r3_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3636 o
->in1
= tcg_temp_new_i64();
3637 tcg_gen_ext32u_i64(o
->in1
, regs
[get_field(f
, r3
)]);
3640 static void in1_e1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3642 o
->in1
= load_freg32_i64(get_field(f
, r1
));
3645 static void in1_f1_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3647 o
->in1
= fregs
[get_field(f
, r1
)];
3651 static void in1_x1_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3653 /* ??? Specification exception: r1 must be < 14. */
3654 int r1
= get_field(f
, r1
);
3656 o
->out2
= fregs
[(r1
+ 2) & 15];
3657 o
->g_out
= o
->g_out2
= true;
3660 static void in1_la1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3662 o
->addr1
= get_address(s
, 0, get_field(f
, b1
), get_field(f
, d1
));
3665 static void in1_la2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3667 int x2
= have_field(f
, x2
) ? get_field(f
, x2
) : 0;
3668 o
->addr1
= get_address(s
, x2
, get_field(f
, b2
), get_field(f
, d2
));
3671 static void in1_m1_8u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3674 o
->in1
= tcg_temp_new_i64();
3675 tcg_gen_qemu_ld8u(o
->in1
, o
->addr1
, get_mem_index(s
));
3678 static void in1_m1_16s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3681 o
->in1
= tcg_temp_new_i64();
3682 tcg_gen_qemu_ld16s(o
->in1
, o
->addr1
, get_mem_index(s
));
3685 static void in1_m1_16u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3688 o
->in1
= tcg_temp_new_i64();
3689 tcg_gen_qemu_ld16u(o
->in1
, o
->addr1
, get_mem_index(s
));
3692 static void in1_m1_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3695 o
->in1
= tcg_temp_new_i64();
3696 tcg_gen_qemu_ld32s(o
->in1
, o
->addr1
, get_mem_index(s
));
3699 static void in1_m1_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3702 o
->in1
= tcg_temp_new_i64();
3703 tcg_gen_qemu_ld32u(o
->in1
, o
->addr1
, get_mem_index(s
));
3706 static void in1_m1_64(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3709 o
->in1
= tcg_temp_new_i64();
3710 tcg_gen_qemu_ld64(o
->in1
, o
->addr1
, get_mem_index(s
));
3713 /* ====================================================================== */
3714 /* The "INput 2" generators. These load the second operand to an insn. */
3716 static void in2_r1_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3718 o
->in2
= regs
[get_field(f
, r1
)];
3722 static void in2_r1_16u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3724 o
->in2
= tcg_temp_new_i64();
3725 tcg_gen_ext16u_i64(o
->in2
, regs
[get_field(f
, r1
)]);
3728 static void in2_r1_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3730 o
->in2
= tcg_temp_new_i64();
3731 tcg_gen_ext32u_i64(o
->in2
, regs
[get_field(f
, r1
)]);
3734 static void in2_r2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3736 o
->in2
= load_reg(get_field(f
, r2
));
3739 static void in2_r2_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3741 o
->in2
= regs
[get_field(f
, r2
)];
3745 static void in2_r2_nz(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3747 int r2
= get_field(f
, r2
);
3749 o
->in2
= load_reg(r2
);
3753 static void in2_r2_8s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3755 o
->in2
= tcg_temp_new_i64();
3756 tcg_gen_ext8s_i64(o
->in2
, regs
[get_field(f
, r2
)]);
3759 static void in2_r2_8u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3761 o
->in2
= tcg_temp_new_i64();
3762 tcg_gen_ext8u_i64(o
->in2
, regs
[get_field(f
, r2
)]);
3765 static void in2_r2_16s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3767 o
->in2
= tcg_temp_new_i64();
3768 tcg_gen_ext16s_i64(o
->in2
, regs
[get_field(f
, r2
)]);
3771 static void in2_r2_16u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3773 o
->in2
= tcg_temp_new_i64();
3774 tcg_gen_ext16u_i64(o
->in2
, regs
[get_field(f
, r2
)]);
3777 static void in2_r3(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3779 o
->in2
= load_reg(get_field(f
, r3
));
3782 static void in2_r2_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3784 o
->in2
= tcg_temp_new_i64();
3785 tcg_gen_ext32s_i64(o
->in2
, regs
[get_field(f
, r2
)]);
3788 static void in2_r2_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3790 o
->in2
= tcg_temp_new_i64();
3791 tcg_gen_ext32u_i64(o
->in2
, regs
[get_field(f
, r2
)]);
3794 static void in2_e2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3796 o
->in2
= load_freg32_i64(get_field(f
, r2
));
3799 static void in2_f2_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3801 o
->in2
= fregs
[get_field(f
, r2
)];
3805 static void in2_x2_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3807 /* ??? Specification exception: r1 must be < 14. */
3808 int r2
= get_field(f
, r2
);
3810 o
->in2
= fregs
[(r2
+ 2) & 15];
3811 o
->g_in1
= o
->g_in2
= true;
3814 static void in2_ra2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3816 o
->in2
= get_address(s
, 0, get_field(f
, r2
), 0);
3819 static void in2_a2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3821 int x2
= have_field(f
, x2
) ? get_field(f
, x2
) : 0;
3822 o
->in2
= get_address(s
, x2
, get_field(f
, b2
), get_field(f
, d2
));
3825 static void in2_ri2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3827 o
->in2
= tcg_const_i64(s
->pc
+ (int64_t)get_field(f
, i2
) * 2);
3830 static void in2_sh32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3832 help_l2_shift(s
, f
, o
, 31);
3835 static void in2_sh64(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3837 help_l2_shift(s
, f
, o
, 63);
3840 static void in2_m2_8u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3843 tcg_gen_qemu_ld8u(o
->in2
, o
->in2
, get_mem_index(s
));
3846 static void in2_m2_16s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3849 tcg_gen_qemu_ld16s(o
->in2
, o
->in2
, get_mem_index(s
));
3852 static void in2_m2_16u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3855 tcg_gen_qemu_ld16u(o
->in2
, o
->in2
, get_mem_index(s
));
3858 static void in2_m2_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3861 tcg_gen_qemu_ld32s(o
->in2
, o
->in2
, get_mem_index(s
));
3864 static void in2_m2_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3867 tcg_gen_qemu_ld32u(o
->in2
, o
->in2
, get_mem_index(s
));
3870 static void in2_m2_64(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3873 tcg_gen_qemu_ld64(o
->in2
, o
->in2
, get_mem_index(s
));
3876 static void in2_mri2_16u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3879 tcg_gen_qemu_ld16u(o
->in2
, o
->in2
, get_mem_index(s
));
3882 static void in2_mri2_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3885 tcg_gen_qemu_ld32s(o
->in2
, o
->in2
, get_mem_index(s
));
3888 static void in2_mri2_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3891 tcg_gen_qemu_ld32u(o
->in2
, o
->in2
, get_mem_index(s
));
3894 static void in2_mri2_64(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3897 tcg_gen_qemu_ld64(o
->in2
, o
->in2
, get_mem_index(s
));
3900 static void in2_i2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3902 o
->in2
= tcg_const_i64(get_field(f
, i2
));
3905 static void in2_i2_8u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3907 o
->in2
= tcg_const_i64((uint8_t)get_field(f
, i2
));
3910 static void in2_i2_16u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3912 o
->in2
= tcg_const_i64((uint16_t)get_field(f
, i2
));
3915 static void in2_i2_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3917 o
->in2
= tcg_const_i64((uint32_t)get_field(f
, i2
));
3920 static void in2_i2_16u_shl(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3922 uint64_t i2
= (uint16_t)get_field(f
, i2
);
3923 o
->in2
= tcg_const_i64(i2
<< s
->insn
->data
);
3926 static void in2_i2_32u_shl(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3928 uint64_t i2
= (uint32_t)get_field(f
, i2
);
3929 o
->in2
= tcg_const_i64(i2
<< s
->insn
->data
);
3932 /* ====================================================================== */
3934 /* Find opc within the table of insns. This is formulated as a switch
3935 statement so that (1) we get compile-time notice of cut-paste errors
3936 for duplicated opcodes, and (2) the compiler generates the binary
3937 search tree, rather than us having to post-process the table. */
3939 #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
3940 D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0)
3942 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) insn_ ## NM,
3944 enum DisasInsnEnum
{
3945 #include "insn-data.def"
3949 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) { \
3954 .help_in1 = in1_##I1, \
3955 .help_in2 = in2_##I2, \
3956 .help_prep = prep_##P, \
3957 .help_wout = wout_##W, \
3958 .help_cout = cout_##CC, \
3959 .help_op = op_##OP, \
3963 /* Allow 0 to be used for NULL in the table below. */
3971 static const DisasInsn insn_info
[] = {
3972 #include "insn-data.def"
3976 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
3977 case OPC: return &insn_info[insn_ ## NM];
3979 static const DisasInsn
*lookup_opc(uint16_t opc
)
3982 #include "insn-data.def"
3991 /* Extract a field from the insn. The INSN should be left-aligned in
3992 the uint64_t so that we can more easily utilize the big-bit-endian
3993 definitions we extract from the Principals of Operation. */
3995 static void extract_field(DisasFields
*o
, const DisasField
*f
, uint64_t insn
)
4003 /* Zero extract the field from the insn. */
4004 r
= (insn
<< f
->beg
) >> (64 - f
->size
);
4006 /* Sign-extend, or un-swap the field as necessary. */
4008 case 0: /* unsigned */
4010 case 1: /* signed */
4011 assert(f
->size
<= 32);
4012 m
= 1u << (f
->size
- 1);
4015 case 2: /* dl+dh split, signed 20 bit. */
4016 r
= ((int8_t)r
<< 12) | (r
>> 8);
4022 /* Validate that the "compressed" encoding we selected above is valid.
4023 I.e. we havn't make two different original fields overlap. */
4024 assert(((o
->presentC
>> f
->indexC
) & 1) == 0);
4025 o
->presentC
|= 1 << f
->indexC
;
4026 o
->presentO
|= 1 << f
->indexO
;
4028 o
->c
[f
->indexC
] = r
;
4031 /* Lookup the insn at the current PC, extracting the operands into O and
4032 returning the info struct for the insn. Returns NULL for invalid insn. */
4034 static const DisasInsn
*extract_insn(CPUS390XState
*env
, DisasContext
*s
,
4037 uint64_t insn
, pc
= s
->pc
;
4039 const DisasInsn
*info
;
4041 insn
= ld_code2(env
, pc
);
4042 op
= (insn
>> 8) & 0xff;
4043 ilen
= get_ilen(op
);
4044 s
->next_pc
= s
->pc
+ ilen
;
4051 insn
= ld_code4(env
, pc
) << 32;
4054 insn
= (insn
<< 48) | (ld_code4(env
, pc
+ 2) << 16);
4060 /* We can't actually determine the insn format until we've looked up
4061 the full insn opcode. Which we can't do without locating the
4062 secondary opcode. Assume by default that OP2 is at bit 40; for
4063 those smaller insns that don't actually have a secondary opcode
4064 this will correctly result in OP2 = 0. */
4070 case 0xb2: /* S, RRF, RRE */
4071 case 0xb3: /* RRE, RRD, RRF */
4072 case 0xb9: /* RRE, RRF */
4073 case 0xe5: /* SSE, SIL */
4074 op2
= (insn
<< 8) >> 56;
4078 case 0xc0: /* RIL */
4079 case 0xc2: /* RIL */
4080 case 0xc4: /* RIL */
4081 case 0xc6: /* RIL */
4082 case 0xc8: /* SSF */
4083 case 0xcc: /* RIL */
4084 op2
= (insn
<< 12) >> 60;
4086 case 0xd0 ... 0xdf: /* SS */
4092 case 0xee ... 0xf3: /* SS */
4093 case 0xf8 ... 0xfd: /* SS */
4097 op2
= (insn
<< 40) >> 56;
4101 memset(f
, 0, sizeof(*f
));
4105 /* Lookup the instruction. */
4106 info
= lookup_opc(op
<< 8 | op2
);
4108 /* If we found it, extract the operands. */
4110 DisasFormat fmt
= info
->fmt
;
4113 for (i
= 0; i
< NUM_C_FIELD
; ++i
) {
4114 extract_field(f
, &format_info
[fmt
].op
[i
], insn
);
4120 static ExitStatus
translate_one(CPUS390XState
*env
, DisasContext
*s
)
4122 const DisasInsn
*insn
;
4123 ExitStatus ret
= NO_EXIT
;
4127 /* Search for the insn in the table. */
4128 insn
= extract_insn(env
, s
, &f
);
4130 /* Not found means unimplemented/illegal opcode. */
4132 qemu_log_mask(LOG_UNIMP
, "unimplemented opcode 0x%02x%02x\n",
4134 gen_illegal_opcode(s
);
4135 return EXIT_NORETURN
;
4138 /* Set up the strutures we use to communicate with the helpers. */
4141 o
.g_out
= o
.g_out2
= o
.g_in1
= o
.g_in2
= false;
4142 TCGV_UNUSED_I64(o
.out
);
4143 TCGV_UNUSED_I64(o
.out2
);
4144 TCGV_UNUSED_I64(o
.in1
);
4145 TCGV_UNUSED_I64(o
.in2
);
4146 TCGV_UNUSED_I64(o
.addr1
);
4148 /* Implement the instruction. */
4149 if (insn
->help_in1
) {
4150 insn
->help_in1(s
, &f
, &o
);
4152 if (insn
->help_in2
) {
4153 insn
->help_in2(s
, &f
, &o
);
4155 if (insn
->help_prep
) {
4156 insn
->help_prep(s
, &f
, &o
);
4158 if (insn
->help_op
) {
4159 ret
= insn
->help_op(s
, &o
);
4161 if (insn
->help_wout
) {
4162 insn
->help_wout(s
, &f
, &o
);
4164 if (insn
->help_cout
) {
4165 insn
->help_cout(s
, &o
);
4168 /* Free any temporaries created by the helpers. */
4169 if (!TCGV_IS_UNUSED_I64(o
.out
) && !o
.g_out
) {
4170 tcg_temp_free_i64(o
.out
);
4172 if (!TCGV_IS_UNUSED_I64(o
.out2
) && !o
.g_out2
) {
4173 tcg_temp_free_i64(o
.out2
);
4175 if (!TCGV_IS_UNUSED_I64(o
.in1
) && !o
.g_in1
) {
4176 tcg_temp_free_i64(o
.in1
);
4178 if (!TCGV_IS_UNUSED_I64(o
.in2
) && !o
.g_in2
) {
4179 tcg_temp_free_i64(o
.in2
);
4181 if (!TCGV_IS_UNUSED_I64(o
.addr1
)) {
4182 tcg_temp_free_i64(o
.addr1
);
4185 /* Advance to the next instruction. */
4190 static inline void gen_intermediate_code_internal(CPUS390XState
*env
,
4191 TranslationBlock
*tb
,
4195 target_ulong pc_start
;
4196 uint64_t next_page_start
;
4197 uint16_t *gen_opc_end
;
4199 int num_insns
, max_insns
;
4207 if (!(tb
->flags
& FLAG_MASK_64
)) {
4208 pc_start
&= 0x7fffffff;
4213 dc
.cc_op
= CC_OP_DYNAMIC
;
4214 do_debug
= dc
.singlestep_enabled
= env
->singlestep_enabled
;
4216 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
4218 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
4221 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
4222 if (max_insns
== 0) {
4223 max_insns
= CF_COUNT_MASK
;
4230 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
4234 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
4237 tcg_ctx
.gen_opc_pc
[lj
] = dc
.pc
;
4238 gen_opc_cc_op
[lj
] = dc
.cc_op
;
4239 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
4240 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
4242 if (++num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
4246 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
4247 tcg_gen_debug_insn_start(dc
.pc
);
4251 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
4252 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
4253 if (bp
->pc
== dc
.pc
) {
4254 status
= EXIT_PC_STALE
;
4260 if (status
== NO_EXIT
) {
4261 status
= translate_one(env
, &dc
);
4264 /* If we reach a page boundary, are single stepping,
4265 or exhaust instruction count, stop generation. */
4266 if (status
== NO_EXIT
4267 && (dc
.pc
>= next_page_start
4268 || tcg_ctx
.gen_opc_ptr
>= gen_opc_end
4269 || num_insns
>= max_insns
4271 || env
->singlestep_enabled
)) {
4272 status
= EXIT_PC_STALE
;
4274 } while (status
== NO_EXIT
);
4276 if (tb
->cflags
& CF_LAST_IO
) {
4285 update_psw_addr(&dc
);
4287 case EXIT_PC_UPDATED
:
4288 /* Next TB starts off with CC_OP_DYNAMIC, so make sure the
4289 cc op type is in env */
4291 /* Exit the TB, either by raising a debug exception or by return. */
4293 gen_exception(EXCP_DEBUG
);
4302 gen_icount_end(tb
, num_insns
);
4303 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
4305 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
4308 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
4311 tb
->size
= dc
.pc
- pc_start
;
4312 tb
->icount
= num_insns
;
4315 #if defined(S390X_DEBUG_DISAS)
4316 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
4317 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
4318 log_target_disas(env
, pc_start
, dc
.pc
- pc_start
, 1);
4324 void gen_intermediate_code (CPUS390XState
*env
, struct TranslationBlock
*tb
)
4326 gen_intermediate_code_internal(env
, tb
, 0);
4329 void gen_intermediate_code_pc (CPUS390XState
*env
, struct TranslationBlock
*tb
)
4331 gen_intermediate_code_internal(env
, tb
, 1);
4334 void restore_state_to_opc(CPUS390XState
*env
, TranslationBlock
*tb
, int pc_pos
)
4337 env
->psw
.addr
= tcg_ctx
.gen_opc_pc
[pc_pos
];
4338 cc_op
= gen_opc_cc_op
[pc_pos
];
4339 if ((cc_op
!= CC_OP_DYNAMIC
) && (cc_op
!= CC_OP_STATIC
)) {