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[qemu.git] / target-s390x / translate.c
1 /*
2 * S/390 translation
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* #define DEBUG_INLINE_BRANCHES */
22 #define S390X_DEBUG_DISAS
23 /* #define S390X_DEBUG_DISAS_VERBOSE */
24
25 #ifdef S390X_DEBUG_DISAS_VERBOSE
26 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
27 #else
28 # define LOG_DISAS(...) do { } while (0)
29 #endif
30
31 #include "cpu.h"
32 #include "disas/disas.h"
33 #include "tcg-op.h"
34 #include "qemu/log.h"
35 #include "qemu/host-utils.h"
36
37 /* global register indexes */
38 static TCGv_ptr cpu_env;
39
40 #include "exec/gen-icount.h"
41 #include "helper.h"
42 #define GEN_HELPER 1
43 #include "helper.h"
44
45
46 /* Information that (most) every instruction needs to manipulate. */
47 typedef struct DisasContext DisasContext;
48 typedef struct DisasInsn DisasInsn;
49 typedef struct DisasFields DisasFields;
50
51 struct DisasContext {
52 struct TranslationBlock *tb;
53 const DisasInsn *insn;
54 DisasFields *fields;
55 uint64_t pc, next_pc;
56 enum cc_op cc_op;
57 bool singlestep_enabled;
58 int is_jmp;
59 };
60
61 /* Information carried about a condition to be evaluated. */
62 typedef struct {
63 TCGCond cond:8;
64 bool is_64;
65 bool g1;
66 bool g2;
67 union {
68 struct { TCGv_i64 a, b; } s64;
69 struct { TCGv_i32 a, b; } s32;
70 } u;
71 } DisasCompare;
72
73 #define DISAS_EXCP 4
74
75 static void gen_op_calc_cc(DisasContext *s);
76
77 #ifdef DEBUG_INLINE_BRANCHES
78 static uint64_t inline_branch_hit[CC_OP_MAX];
79 static uint64_t inline_branch_miss[CC_OP_MAX];
80 #endif
81
82 static inline void debug_insn(uint64_t insn)
83 {
84 LOG_DISAS("insn: 0x%" PRIx64 "\n", insn);
85 }
86
87 static inline uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
88 {
89 if (!(s->tb->flags & FLAG_MASK_64)) {
90 if (s->tb->flags & FLAG_MASK_32) {
91 return pc | 0x80000000;
92 }
93 }
94 return pc;
95 }
96
97 void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
98 int flags)
99 {
100 int i;
101
102 if (env->cc_op > 3) {
103 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
104 env->psw.mask, env->psw.addr, cc_name(env->cc_op));
105 } else {
106 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
107 env->psw.mask, env->psw.addr, env->cc_op);
108 }
109
110 for (i = 0; i < 16; i++) {
111 cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
112 if ((i % 4) == 3) {
113 cpu_fprintf(f, "\n");
114 } else {
115 cpu_fprintf(f, " ");
116 }
117 }
118
119 for (i = 0; i < 16; i++) {
120 cpu_fprintf(f, "F%02d=%016" PRIx64, i, env->fregs[i].ll);
121 if ((i % 4) == 3) {
122 cpu_fprintf(f, "\n");
123 } else {
124 cpu_fprintf(f, " ");
125 }
126 }
127
128 #ifndef CONFIG_USER_ONLY
129 for (i = 0; i < 16; i++) {
130 cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
131 if ((i % 4) == 3) {
132 cpu_fprintf(f, "\n");
133 } else {
134 cpu_fprintf(f, " ");
135 }
136 }
137 #endif
138
139 #ifdef DEBUG_INLINE_BRANCHES
140 for (i = 0; i < CC_OP_MAX; i++) {
141 cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
142 inline_branch_miss[i], inline_branch_hit[i]);
143 }
144 #endif
145
146 cpu_fprintf(f, "\n");
147 }
148
149 static TCGv_i64 psw_addr;
150 static TCGv_i64 psw_mask;
151
152 static TCGv_i32 cc_op;
153 static TCGv_i64 cc_src;
154 static TCGv_i64 cc_dst;
155 static TCGv_i64 cc_vr;
156
157 static char cpu_reg_names[32][4];
158 static TCGv_i64 regs[16];
159 static TCGv_i64 fregs[16];
160
161 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
162
163 void s390x_translate_init(void)
164 {
165 int i;
166
167 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
168 psw_addr = tcg_global_mem_new_i64(TCG_AREG0,
169 offsetof(CPUS390XState, psw.addr),
170 "psw_addr");
171 psw_mask = tcg_global_mem_new_i64(TCG_AREG0,
172 offsetof(CPUS390XState, psw.mask),
173 "psw_mask");
174
175 cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUS390XState, cc_op),
176 "cc_op");
177 cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_src),
178 "cc_src");
179 cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_dst),
180 "cc_dst");
181 cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_vr),
182 "cc_vr");
183
184 for (i = 0; i < 16; i++) {
185 snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i);
186 regs[i] = tcg_global_mem_new(TCG_AREG0,
187 offsetof(CPUS390XState, regs[i]),
188 cpu_reg_names[i]);
189 }
190
191 for (i = 0; i < 16; i++) {
192 snprintf(cpu_reg_names[i + 16], sizeof(cpu_reg_names[0]), "f%d", i);
193 fregs[i] = tcg_global_mem_new(TCG_AREG0,
194 offsetof(CPUS390XState, fregs[i].d),
195 cpu_reg_names[i + 16]);
196 }
197
198 /* register helpers */
199 #define GEN_HELPER 2
200 #include "helper.h"
201 }
202
203 static inline TCGv_i64 load_reg(int reg)
204 {
205 TCGv_i64 r = tcg_temp_new_i64();
206 tcg_gen_mov_i64(r, regs[reg]);
207 return r;
208 }
209
210 static inline TCGv_i64 load_freg(int reg)
211 {
212 TCGv_i64 r = tcg_temp_new_i64();
213 tcg_gen_mov_i64(r, fregs[reg]);
214 return r;
215 }
216
217 static inline TCGv_i32 load_freg32(int reg)
218 {
219 TCGv_i32 r = tcg_temp_new_i32();
220 #if HOST_LONG_BITS == 32
221 tcg_gen_mov_i32(r, TCGV_HIGH(fregs[reg]));
222 #else
223 tcg_gen_shri_i64(MAKE_TCGV_I64(GET_TCGV_I32(r)), fregs[reg], 32);
224 #endif
225 return r;
226 }
227
228 static inline TCGv_i64 load_freg32_i64(int reg)
229 {
230 TCGv_i64 r = tcg_temp_new_i64();
231 tcg_gen_shri_i64(r, fregs[reg], 32);
232 return r;
233 }
234
235 static inline TCGv_i32 load_reg32(int reg)
236 {
237 TCGv_i32 r = tcg_temp_new_i32();
238 tcg_gen_trunc_i64_i32(r, regs[reg]);
239 return r;
240 }
241
242 static inline TCGv_i64 load_reg32_i64(int reg)
243 {
244 TCGv_i64 r = tcg_temp_new_i64();
245 tcg_gen_ext32s_i64(r, regs[reg]);
246 return r;
247 }
248
249 static inline void store_reg(int reg, TCGv_i64 v)
250 {
251 tcg_gen_mov_i64(regs[reg], v);
252 }
253
254 static inline void store_freg(int reg, TCGv_i64 v)
255 {
256 tcg_gen_mov_i64(fregs[reg], v);
257 }
258
259 static inline void store_reg32(int reg, TCGv_i32 v)
260 {
261 /* 32 bit register writes keep the upper half */
262 #if HOST_LONG_BITS == 32
263 tcg_gen_mov_i32(TCGV_LOW(regs[reg]), v);
264 #else
265 tcg_gen_deposit_i64(regs[reg], regs[reg],
266 MAKE_TCGV_I64(GET_TCGV_I32(v)), 0, 32);
267 #endif
268 }
269
270 static inline void store_reg32_i64(int reg, TCGv_i64 v)
271 {
272 /* 32 bit register writes keep the upper half */
273 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
274 }
275
276 static inline void store_reg32h_i64(int reg, TCGv_i64 v)
277 {
278 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 32, 32);
279 }
280
281 static inline void store_freg32(int reg, TCGv_i32 v)
282 {
283 /* 32 bit register writes keep the lower half */
284 #if HOST_LONG_BITS == 32
285 tcg_gen_mov_i32(TCGV_HIGH(fregs[reg]), v);
286 #else
287 tcg_gen_deposit_i64(fregs[reg], fregs[reg],
288 MAKE_TCGV_I64(GET_TCGV_I32(v)), 32, 32);
289 #endif
290 }
291
292 static inline void store_freg32_i64(int reg, TCGv_i64 v)
293 {
294 tcg_gen_deposit_i64(fregs[reg], fregs[reg], v, 32, 32);
295 }
296
297 static inline void return_low128(TCGv_i64 dest)
298 {
299 tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl));
300 }
301
302 static inline void update_psw_addr(DisasContext *s)
303 {
304 /* psw.addr */
305 tcg_gen_movi_i64(psw_addr, s->pc);
306 }
307
308 static inline void potential_page_fault(DisasContext *s)
309 {
310 #ifndef CONFIG_USER_ONLY
311 update_psw_addr(s);
312 gen_op_calc_cc(s);
313 #endif
314 }
315
316 static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
317 {
318 return (uint64_t)cpu_lduw_code(env, pc);
319 }
320
321 static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
322 {
323 return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
324 }
325
326 static inline uint64_t ld_code6(CPUS390XState *env, uint64_t pc)
327 {
328 return (ld_code2(env, pc) << 32) | ld_code4(env, pc + 2);
329 }
330
331 static inline int get_mem_index(DisasContext *s)
332 {
333 switch (s->tb->flags & FLAG_MASK_ASC) {
334 case PSW_ASC_PRIMARY >> 32:
335 return 0;
336 case PSW_ASC_SECONDARY >> 32:
337 return 1;
338 case PSW_ASC_HOME >> 32:
339 return 2;
340 default:
341 tcg_abort();
342 break;
343 }
344 }
345
346 static void gen_exception(int excp)
347 {
348 TCGv_i32 tmp = tcg_const_i32(excp);
349 gen_helper_exception(cpu_env, tmp);
350 tcg_temp_free_i32(tmp);
351 }
352
353 static void gen_program_exception(DisasContext *s, int code)
354 {
355 TCGv_i32 tmp;
356
357 /* Remember what pgm exeption this was. */
358 tmp = tcg_const_i32(code);
359 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
360 tcg_temp_free_i32(tmp);
361
362 tmp = tcg_const_i32(s->next_pc - s->pc);
363 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen));
364 tcg_temp_free_i32(tmp);
365
366 /* Advance past instruction. */
367 s->pc = s->next_pc;
368 update_psw_addr(s);
369
370 /* Save off cc. */
371 gen_op_calc_cc(s);
372
373 /* Trigger exception. */
374 gen_exception(EXCP_PGM);
375
376 /* End TB here. */
377 s->is_jmp = DISAS_EXCP;
378 }
379
380 static inline void gen_illegal_opcode(DisasContext *s)
381 {
382 gen_program_exception(s, PGM_SPECIFICATION);
383 }
384
385 static inline void check_privileged(DisasContext *s)
386 {
387 if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
388 gen_program_exception(s, PGM_PRIVILEGED);
389 }
390 }
391
392 static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
393 {
394 TCGv_i64 tmp;
395
396 /* 31-bitify the immediate part; register contents are dealt with below */
397 if (!(s->tb->flags & FLAG_MASK_64)) {
398 d2 &= 0x7fffffffUL;
399 }
400
401 if (x2) {
402 if (d2) {
403 tmp = tcg_const_i64(d2);
404 tcg_gen_add_i64(tmp, tmp, regs[x2]);
405 } else {
406 tmp = load_reg(x2);
407 }
408 if (b2) {
409 tcg_gen_add_i64(tmp, tmp, regs[b2]);
410 }
411 } else if (b2) {
412 if (d2) {
413 tmp = tcg_const_i64(d2);
414 tcg_gen_add_i64(tmp, tmp, regs[b2]);
415 } else {
416 tmp = load_reg(b2);
417 }
418 } else {
419 tmp = tcg_const_i64(d2);
420 }
421
422 /* 31-bit mode mask if there are values loaded from registers */
423 if (!(s->tb->flags & FLAG_MASK_64) && (x2 || b2)) {
424 tcg_gen_andi_i64(tmp, tmp, 0x7fffffffUL);
425 }
426
427 return tmp;
428 }
429
430 static inline void gen_op_movi_cc(DisasContext *s, uint32_t val)
431 {
432 s->cc_op = CC_OP_CONST0 + val;
433 }
434
435 static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
436 {
437 tcg_gen_discard_i64(cc_src);
438 tcg_gen_mov_i64(cc_dst, dst);
439 tcg_gen_discard_i64(cc_vr);
440 s->cc_op = op;
441 }
442
443 static void gen_op_update1_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 dst)
444 {
445 tcg_gen_discard_i64(cc_src);
446 tcg_gen_extu_i32_i64(cc_dst, dst);
447 tcg_gen_discard_i64(cc_vr);
448 s->cc_op = op;
449 }
450
451 static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
452 TCGv_i64 dst)
453 {
454 tcg_gen_mov_i64(cc_src, src);
455 tcg_gen_mov_i64(cc_dst, dst);
456 tcg_gen_discard_i64(cc_vr);
457 s->cc_op = op;
458 }
459
460 static void gen_op_update2_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src,
461 TCGv_i32 dst)
462 {
463 tcg_gen_extu_i32_i64(cc_src, src);
464 tcg_gen_extu_i32_i64(cc_dst, dst);
465 tcg_gen_discard_i64(cc_vr);
466 s->cc_op = op;
467 }
468
469 static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
470 TCGv_i64 dst, TCGv_i64 vr)
471 {
472 tcg_gen_mov_i64(cc_src, src);
473 tcg_gen_mov_i64(cc_dst, dst);
474 tcg_gen_mov_i64(cc_vr, vr);
475 s->cc_op = op;
476 }
477
478 static inline void set_cc_nz_u32(DisasContext *s, TCGv_i32 val)
479 {
480 gen_op_update1_cc_i32(s, CC_OP_NZ, val);
481 }
482
483 static inline void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
484 {
485 gen_op_update1_cc_i64(s, CC_OP_NZ, val);
486 }
487
488 static inline void gen_set_cc_nz_f32(DisasContext *s, TCGv_i64 val)
489 {
490 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, val);
491 }
492
493 static inline void gen_set_cc_nz_f64(DisasContext *s, TCGv_i64 val)
494 {
495 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, val);
496 }
497
498 static inline void gen_set_cc_nz_f128(DisasContext *s, TCGv_i64 vh, TCGv_i64 vl)
499 {
500 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, vh, vl);
501 }
502
503 static inline void cmp_32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
504 enum cc_op cond)
505 {
506 gen_op_update2_cc_i32(s, cond, v1, v2);
507 }
508
509 static inline void cmp_64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
510 enum cc_op cond)
511 {
512 gen_op_update2_cc_i64(s, cond, v1, v2);
513 }
514
515 static inline void cmp_s32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
516 {
517 cmp_32(s, v1, v2, CC_OP_LTGT_32);
518 }
519
520 static inline void cmp_u32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
521 {
522 cmp_32(s, v1, v2, CC_OP_LTUGTU_32);
523 }
524
525 static inline void cmp_s32c(DisasContext *s, TCGv_i32 v1, int32_t v2)
526 {
527 /* XXX optimize for the constant? put it in s? */
528 TCGv_i32 tmp = tcg_const_i32(v2);
529 cmp_32(s, v1, tmp, CC_OP_LTGT_32);
530 tcg_temp_free_i32(tmp);
531 }
532
533 static inline void cmp_u32c(DisasContext *s, TCGv_i32 v1, uint32_t v2)
534 {
535 TCGv_i32 tmp = tcg_const_i32(v2);
536 cmp_32(s, v1, tmp, CC_OP_LTUGTU_32);
537 tcg_temp_free_i32(tmp);
538 }
539
540 static inline void cmp_s64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
541 {
542 cmp_64(s, v1, v2, CC_OP_LTGT_64);
543 }
544
545 static inline void cmp_u64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
546 {
547 cmp_64(s, v1, v2, CC_OP_LTUGTU_64);
548 }
549
550 static inline void cmp_s64c(DisasContext *s, TCGv_i64 v1, int64_t v2)
551 {
552 TCGv_i64 tmp = tcg_const_i64(v2);
553 cmp_s64(s, v1, tmp);
554 tcg_temp_free_i64(tmp);
555 }
556
557 static inline void cmp_u64c(DisasContext *s, TCGv_i64 v1, uint64_t v2)
558 {
559 TCGv_i64 tmp = tcg_const_i64(v2);
560 cmp_u64(s, v1, tmp);
561 tcg_temp_free_i64(tmp);
562 }
563
564 static inline void set_cc_s32(DisasContext *s, TCGv_i32 val)
565 {
566 gen_op_update1_cc_i32(s, CC_OP_LTGT0_32, val);
567 }
568
569 static inline void set_cc_s64(DisasContext *s, TCGv_i64 val)
570 {
571 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, val);
572 }
573
574 /* CC value is in env->cc_op */
575 static inline void set_cc_static(DisasContext *s)
576 {
577 tcg_gen_discard_i64(cc_src);
578 tcg_gen_discard_i64(cc_dst);
579 tcg_gen_discard_i64(cc_vr);
580 s->cc_op = CC_OP_STATIC;
581 }
582
583 static inline void gen_op_set_cc_op(DisasContext *s)
584 {
585 if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
586 tcg_gen_movi_i32(cc_op, s->cc_op);
587 }
588 }
589
590 static inline void gen_update_cc_op(DisasContext *s)
591 {
592 gen_op_set_cc_op(s);
593 }
594
595 /* calculates cc into cc_op */
596 static void gen_op_calc_cc(DisasContext *s)
597 {
598 TCGv_i32 local_cc_op = tcg_const_i32(s->cc_op);
599 TCGv_i64 dummy = tcg_const_i64(0);
600
601 switch (s->cc_op) {
602 case CC_OP_CONST0:
603 case CC_OP_CONST1:
604 case CC_OP_CONST2:
605 case CC_OP_CONST3:
606 /* s->cc_op is the cc value */
607 tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
608 break;
609 case CC_OP_STATIC:
610 /* env->cc_op already is the cc value */
611 break;
612 case CC_OP_NZ:
613 case CC_OP_ABS_64:
614 case CC_OP_NABS_64:
615 case CC_OP_ABS_32:
616 case CC_OP_NABS_32:
617 case CC_OP_LTGT0_32:
618 case CC_OP_LTGT0_64:
619 case CC_OP_COMP_32:
620 case CC_OP_COMP_64:
621 case CC_OP_NZ_F32:
622 case CC_OP_NZ_F64:
623 case CC_OP_FLOGR:
624 /* 1 argument */
625 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dummy);
626 break;
627 case CC_OP_ICM:
628 case CC_OP_LTGT_32:
629 case CC_OP_LTGT_64:
630 case CC_OP_LTUGTU_32:
631 case CC_OP_LTUGTU_64:
632 case CC_OP_TM_32:
633 case CC_OP_TM_64:
634 case CC_OP_SLA_32:
635 case CC_OP_SLA_64:
636 case CC_OP_NZ_F128:
637 /* 2 arguments */
638 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
639 break;
640 case CC_OP_ADD_64:
641 case CC_OP_ADDU_64:
642 case CC_OP_ADDC_64:
643 case CC_OP_SUB_64:
644 case CC_OP_SUBU_64:
645 case CC_OP_SUBB_64:
646 case CC_OP_ADD_32:
647 case CC_OP_ADDU_32:
648 case CC_OP_ADDC_32:
649 case CC_OP_SUB_32:
650 case CC_OP_SUBU_32:
651 case CC_OP_SUBB_32:
652 /* 3 arguments */
653 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc_vr);
654 break;
655 case CC_OP_DYNAMIC:
656 /* unknown operation - assume 3 arguments and cc_op in env */
657 gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr);
658 break;
659 default:
660 tcg_abort();
661 }
662
663 tcg_temp_free_i32(local_cc_op);
664 tcg_temp_free_i64(dummy);
665
666 /* We now have cc in cc_op as constant */
667 set_cc_static(s);
668 }
669
670 static inline void decode_rr(DisasContext *s, uint64_t insn, int *r1, int *r2)
671 {
672 debug_insn(insn);
673
674 *r1 = (insn >> 4) & 0xf;
675 *r2 = insn & 0xf;
676 }
677
678 static inline TCGv_i64 decode_rx(DisasContext *s, uint64_t insn, int *r1,
679 int *x2, int *b2, int *d2)
680 {
681 debug_insn(insn);
682
683 *r1 = (insn >> 20) & 0xf;
684 *x2 = (insn >> 16) & 0xf;
685 *b2 = (insn >> 12) & 0xf;
686 *d2 = insn & 0xfff;
687
688 return get_address(s, *x2, *b2, *d2);
689 }
690
691 static inline void decode_rs(DisasContext *s, uint64_t insn, int *r1, int *r3,
692 int *b2, int *d2)
693 {
694 debug_insn(insn);
695
696 *r1 = (insn >> 20) & 0xf;
697 /* aka m3 */
698 *r3 = (insn >> 16) & 0xf;
699 *b2 = (insn >> 12) & 0xf;
700 *d2 = insn & 0xfff;
701 }
702
703 static inline TCGv_i64 decode_si(DisasContext *s, uint64_t insn, int *i2,
704 int *b1, int *d1)
705 {
706 debug_insn(insn);
707
708 *i2 = (insn >> 16) & 0xff;
709 *b1 = (insn >> 12) & 0xf;
710 *d1 = insn & 0xfff;
711
712 return get_address(s, 0, *b1, *d1);
713 }
714
715 static int use_goto_tb(DisasContext *s, uint64_t dest)
716 {
717 /* NOTE: we handle the case where the TB spans two pages here */
718 return (((dest & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK)
719 || (dest & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK))
720 && !s->singlestep_enabled
721 && !(s->tb->cflags & CF_LAST_IO));
722 }
723
724 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong pc)
725 {
726 gen_update_cc_op(s);
727
728 if (use_goto_tb(s, pc)) {
729 tcg_gen_goto_tb(tb_num);
730 tcg_gen_movi_i64(psw_addr, pc);
731 tcg_gen_exit_tb((tcg_target_long)s->tb + tb_num);
732 } else {
733 /* jump to another page: currently not optimized */
734 tcg_gen_movi_i64(psw_addr, pc);
735 tcg_gen_exit_tb(0);
736 }
737 }
738
739 static inline void account_noninline_branch(DisasContext *s, int cc_op)
740 {
741 #ifdef DEBUG_INLINE_BRANCHES
742 inline_branch_miss[cc_op]++;
743 #endif
744 }
745
746 static inline void account_inline_branch(DisasContext *s, int cc_op)
747 {
748 #ifdef DEBUG_INLINE_BRANCHES
749 inline_branch_hit[cc_op]++;
750 #endif
751 }
752
753 /* Table of mask values to comparison codes, given a comparison as input.
754 For a true comparison CC=3 will never be set, but we treat this
755 conservatively for possible use when CC=3 indicates overflow. */
756 static const TCGCond ltgt_cond[16] = {
757 TCG_COND_NEVER, TCG_COND_NEVER, /* | | | x */
758 TCG_COND_GT, TCG_COND_NEVER, /* | | GT | x */
759 TCG_COND_LT, TCG_COND_NEVER, /* | LT | | x */
760 TCG_COND_NE, TCG_COND_NEVER, /* | LT | GT | x */
761 TCG_COND_EQ, TCG_COND_NEVER, /* EQ | | | x */
762 TCG_COND_GE, TCG_COND_NEVER, /* EQ | | GT | x */
763 TCG_COND_LE, TCG_COND_NEVER, /* EQ | LT | | x */
764 TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | LT | GT | x */
765 };
766
767 /* Table of mask values to comparison codes, given a logic op as input.
768 For such, only CC=0 and CC=1 should be possible. */
769 static const TCGCond nz_cond[16] = {
770 /* | | x | x */
771 TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER,
772 /* | NE | x | x */
773 TCG_COND_NE, TCG_COND_NE, TCG_COND_NE, TCG_COND_NE,
774 /* EQ | | x | x */
775 TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ,
776 /* EQ | NE | x | x */
777 TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS,
778 };
779
780 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
781 details required to generate a TCG comparison. */
782 static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
783 {
784 TCGCond cond;
785 enum cc_op old_cc_op = s->cc_op;
786
787 if (mask == 15 || mask == 0) {
788 c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER);
789 c->u.s32.a = cc_op;
790 c->u.s32.b = cc_op;
791 c->g1 = c->g2 = true;
792 c->is_64 = false;
793 return;
794 }
795
796 /* Find the TCG condition for the mask + cc op. */
797 switch (old_cc_op) {
798 case CC_OP_LTGT0_32:
799 case CC_OP_LTGT0_64:
800 case CC_OP_LTGT_32:
801 case CC_OP_LTGT_64:
802 cond = ltgt_cond[mask];
803 if (cond == TCG_COND_NEVER) {
804 goto do_dynamic;
805 }
806 account_inline_branch(s, old_cc_op);
807 break;
808
809 case CC_OP_LTUGTU_32:
810 case CC_OP_LTUGTU_64:
811 cond = tcg_unsigned_cond(ltgt_cond[mask]);
812 if (cond == TCG_COND_NEVER) {
813 goto do_dynamic;
814 }
815 account_inline_branch(s, old_cc_op);
816 break;
817
818 case CC_OP_NZ:
819 cond = nz_cond[mask];
820 if (cond == TCG_COND_NEVER) {
821 goto do_dynamic;
822 }
823 account_inline_branch(s, old_cc_op);
824 break;
825
826 case CC_OP_TM_32:
827 case CC_OP_TM_64:
828 switch (mask) {
829 case 8:
830 cond = TCG_COND_EQ;
831 break;
832 case 4 | 2 | 1:
833 cond = TCG_COND_NE;
834 break;
835 default:
836 goto do_dynamic;
837 }
838 account_inline_branch(s, old_cc_op);
839 break;
840
841 case CC_OP_ICM:
842 switch (mask) {
843 case 8:
844 cond = TCG_COND_EQ;
845 break;
846 case 4 | 2 | 1:
847 case 4 | 2:
848 cond = TCG_COND_NE;
849 break;
850 default:
851 goto do_dynamic;
852 }
853 account_inline_branch(s, old_cc_op);
854 break;
855
856 case CC_OP_FLOGR:
857 switch (mask & 0xa) {
858 case 8: /* src == 0 -> no one bit found */
859 cond = TCG_COND_EQ;
860 break;
861 case 2: /* src != 0 -> one bit found */
862 cond = TCG_COND_NE;
863 break;
864 default:
865 goto do_dynamic;
866 }
867 account_inline_branch(s, old_cc_op);
868 break;
869
870 default:
871 do_dynamic:
872 /* Calculate cc value. */
873 gen_op_calc_cc(s);
874 /* FALLTHRU */
875
876 case CC_OP_STATIC:
877 /* Jump based on CC. We'll load up the real cond below;
878 the assignment here merely avoids a compiler warning. */
879 account_noninline_branch(s, old_cc_op);
880 old_cc_op = CC_OP_STATIC;
881 cond = TCG_COND_NEVER;
882 break;
883 }
884
885 /* Load up the arguments of the comparison. */
886 c->is_64 = true;
887 c->g1 = c->g2 = false;
888 switch (old_cc_op) {
889 case CC_OP_LTGT0_32:
890 c->is_64 = false;
891 c->u.s32.a = tcg_temp_new_i32();
892 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_dst);
893 c->u.s32.b = tcg_const_i32(0);
894 break;
895 case CC_OP_LTGT_32:
896 case CC_OP_LTUGTU_32:
897 c->is_64 = false;
898 c->u.s32.a = tcg_temp_new_i32();
899 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_src);
900 c->u.s32.b = tcg_temp_new_i32();
901 tcg_gen_trunc_i64_i32(c->u.s32.b, cc_dst);
902 break;
903
904 case CC_OP_LTGT0_64:
905 case CC_OP_NZ:
906 case CC_OP_FLOGR:
907 c->u.s64.a = cc_dst;
908 c->u.s64.b = tcg_const_i64(0);
909 c->g1 = true;
910 break;
911 case CC_OP_LTGT_64:
912 case CC_OP_LTUGTU_64:
913 c->u.s64.a = cc_src;
914 c->u.s64.b = cc_dst;
915 c->g1 = c->g2 = true;
916 break;
917
918 case CC_OP_TM_32:
919 case CC_OP_TM_64:
920 case CC_OP_ICM:
921 c->u.s64.a = tcg_temp_new_i64();
922 c->u.s64.b = tcg_const_i64(0);
923 tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
924 break;
925
926 case CC_OP_STATIC:
927 c->is_64 = false;
928 c->u.s32.a = cc_op;
929 c->g1 = true;
930 switch (mask) {
931 case 0x8 | 0x4 | 0x2: /* cc != 3 */
932 cond = TCG_COND_NE;
933 c->u.s32.b = tcg_const_i32(3);
934 break;
935 case 0x8 | 0x4 | 0x1: /* cc != 2 */
936 cond = TCG_COND_NE;
937 c->u.s32.b = tcg_const_i32(2);
938 break;
939 case 0x8 | 0x2 | 0x1: /* cc != 1 */
940 cond = TCG_COND_NE;
941 c->u.s32.b = tcg_const_i32(1);
942 break;
943 case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
944 cond = TCG_COND_EQ;
945 c->g1 = false;
946 c->u.s32.a = tcg_temp_new_i32();
947 c->u.s32.b = tcg_const_i32(0);
948 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
949 break;
950 case 0x8 | 0x4: /* cc < 2 */
951 cond = TCG_COND_LTU;
952 c->u.s32.b = tcg_const_i32(2);
953 break;
954 case 0x8: /* cc == 0 */
955 cond = TCG_COND_EQ;
956 c->u.s32.b = tcg_const_i32(0);
957 break;
958 case 0x4 | 0x2 | 0x1: /* cc != 0 */
959 cond = TCG_COND_NE;
960 c->u.s32.b = tcg_const_i32(0);
961 break;
962 case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
963 cond = TCG_COND_NE;
964 c->g1 = false;
965 c->u.s32.a = tcg_temp_new_i32();
966 c->u.s32.b = tcg_const_i32(0);
967 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
968 break;
969 case 0x4: /* cc == 1 */
970 cond = TCG_COND_EQ;
971 c->u.s32.b = tcg_const_i32(1);
972 break;
973 case 0x2 | 0x1: /* cc > 1 */
974 cond = TCG_COND_GTU;
975 c->u.s32.b = tcg_const_i32(1);
976 break;
977 case 0x2: /* cc == 2 */
978 cond = TCG_COND_EQ;
979 c->u.s32.b = tcg_const_i32(2);
980 break;
981 case 0x1: /* cc == 3 */
982 cond = TCG_COND_EQ;
983 c->u.s32.b = tcg_const_i32(3);
984 break;
985 default:
986 /* CC is masked by something else: (8 >> cc) & mask. */
987 cond = TCG_COND_NE;
988 c->g1 = false;
989 c->u.s32.a = tcg_const_i32(8);
990 c->u.s32.b = tcg_const_i32(0);
991 tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op);
992 tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
993 break;
994 }
995 break;
996
997 default:
998 abort();
999 }
1000 c->cond = cond;
1001 }
1002
1003 static void free_compare(DisasCompare *c)
1004 {
1005 if (!c->g1) {
1006 if (c->is_64) {
1007 tcg_temp_free_i64(c->u.s64.a);
1008 } else {
1009 tcg_temp_free_i32(c->u.s32.a);
1010 }
1011 }
1012 if (!c->g2) {
1013 if (c->is_64) {
1014 tcg_temp_free_i64(c->u.s64.b);
1015 } else {
1016 tcg_temp_free_i32(c->u.s32.b);
1017 }
1018 }
1019 }
1020
1021 static void disas_b2(CPUS390XState *env, DisasContext *s, int op,
1022 uint32_t insn)
1023 {
1024 #ifndef CONFIG_USER_ONLY
1025 TCGv_i64 tmp, tmp2, tmp3;
1026 TCGv_i32 tmp32_1, tmp32_2;
1027 int r1, r2;
1028 int r3, d2, b2;
1029
1030 r1 = (insn >> 4) & 0xf;
1031 r2 = insn & 0xf;
1032
1033 LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op, r1, r2);
1034
1035 switch (op) {
1036 case 0x21: /* IPTE R1,R2 [RRE] */
1037 /* Invalidate PTE */
1038 check_privileged(s);
1039 r1 = (insn >> 4) & 0xf;
1040 r2 = insn & 0xf;
1041 tmp = load_reg(r1);
1042 tmp2 = load_reg(r2);
1043 gen_helper_ipte(cpu_env, tmp, tmp2);
1044 tcg_temp_free_i64(tmp);
1045 tcg_temp_free_i64(tmp2);
1046 break;
1047 case 0x29: /* ISKE R1,R2 [RRE] */
1048 /* Insert Storage Key Extended */
1049 check_privileged(s);
1050 r1 = (insn >> 4) & 0xf;
1051 r2 = insn & 0xf;
1052 tmp = load_reg(r2);
1053 tmp2 = tcg_temp_new_i64();
1054 gen_helper_iske(tmp2, cpu_env, tmp);
1055 store_reg(r1, tmp2);
1056 tcg_temp_free_i64(tmp);
1057 tcg_temp_free_i64(tmp2);
1058 break;
1059 case 0x2a: /* RRBE R1,R2 [RRE] */
1060 /* Set Storage Key Extended */
1061 check_privileged(s);
1062 r1 = (insn >> 4) & 0xf;
1063 r2 = insn & 0xf;
1064 tmp32_1 = load_reg32(r1);
1065 tmp = load_reg(r2);
1066 gen_helper_rrbe(cc_op, cpu_env, tmp32_1, tmp);
1067 set_cc_static(s);
1068 tcg_temp_free_i32(tmp32_1);
1069 tcg_temp_free_i64(tmp);
1070 break;
1071 case 0x2b: /* SSKE R1,R2 [RRE] */
1072 /* Set Storage Key Extended */
1073 check_privileged(s);
1074 r1 = (insn >> 4) & 0xf;
1075 r2 = insn & 0xf;
1076 tmp32_1 = load_reg32(r1);
1077 tmp = load_reg(r2);
1078 gen_helper_sske(cpu_env, tmp32_1, tmp);
1079 tcg_temp_free_i32(tmp32_1);
1080 tcg_temp_free_i64(tmp);
1081 break;
1082 case 0x34: /* STCH ? */
1083 /* Store Subchannel */
1084 check_privileged(s);
1085 gen_op_movi_cc(s, 3);
1086 break;
1087 case 0x46: /* STURA R1,R2 [RRE] */
1088 /* Store Using Real Address */
1089 check_privileged(s);
1090 r1 = (insn >> 4) & 0xf;
1091 r2 = insn & 0xf;
1092 tmp32_1 = load_reg32(r1);
1093 tmp = load_reg(r2);
1094 potential_page_fault(s);
1095 gen_helper_stura(cpu_env, tmp, tmp32_1);
1096 tcg_temp_free_i32(tmp32_1);
1097 tcg_temp_free_i64(tmp);
1098 break;
1099 case 0x50: /* CSP R1,R2 [RRE] */
1100 /* Compare And Swap And Purge */
1101 check_privileged(s);
1102 r1 = (insn >> 4) & 0xf;
1103 r2 = insn & 0xf;
1104 tmp32_1 = tcg_const_i32(r1);
1105 tmp32_2 = tcg_const_i32(r2);
1106 gen_helper_csp(cc_op, cpu_env, tmp32_1, tmp32_2);
1107 set_cc_static(s);
1108 tcg_temp_free_i32(tmp32_1);
1109 tcg_temp_free_i32(tmp32_2);
1110 break;
1111 case 0x5f: /* CHSC ? */
1112 /* Channel Subsystem Call */
1113 check_privileged(s);
1114 gen_op_movi_cc(s, 3);
1115 break;
1116 case 0x78: /* STCKE D2(B2) [S] */
1117 /* Store Clock Extended */
1118 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1119 tmp = get_address(s, 0, b2, d2);
1120 potential_page_fault(s);
1121 gen_helper_stcke(cc_op, cpu_env, tmp);
1122 set_cc_static(s);
1123 tcg_temp_free_i64(tmp);
1124 break;
1125 case 0x79: /* SACF D2(B2) [S] */
1126 /* Set Address Space Control Fast */
1127 check_privileged(s);
1128 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1129 tmp = get_address(s, 0, b2, d2);
1130 potential_page_fault(s);
1131 gen_helper_sacf(cpu_env, tmp);
1132 tcg_temp_free_i64(tmp);
1133 /* addressing mode has changed, so end the block */
1134 s->pc = s->next_pc;
1135 update_psw_addr(s);
1136 s->is_jmp = DISAS_JUMP;
1137 break;
1138 case 0x7d: /* STSI D2,(B2) [S] */
1139 check_privileged(s);
1140 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1141 tmp = get_address(s, 0, b2, d2);
1142 tmp32_1 = load_reg32(0);
1143 tmp32_2 = load_reg32(1);
1144 potential_page_fault(s);
1145 gen_helper_stsi(cc_op, cpu_env, tmp, tmp32_1, tmp32_2);
1146 set_cc_static(s);
1147 tcg_temp_free_i64(tmp);
1148 tcg_temp_free_i32(tmp32_1);
1149 tcg_temp_free_i32(tmp32_2);
1150 break;
1151 case 0xb1: /* STFL D2(B2) [S] */
1152 /* Store Facility List (CPU features) at 200 */
1153 check_privileged(s);
1154 tmp2 = tcg_const_i64(0xc0000000);
1155 tmp = tcg_const_i64(200);
1156 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1157 tcg_temp_free_i64(tmp2);
1158 tcg_temp_free_i64(tmp);
1159 break;
1160 case 0xb2: /* LPSWE D2(B2) [S] */
1161 /* Load PSW Extended */
1162 check_privileged(s);
1163 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1164 tmp = get_address(s, 0, b2, d2);
1165 tmp2 = tcg_temp_new_i64();
1166 tmp3 = tcg_temp_new_i64();
1167 tcg_gen_qemu_ld64(tmp2, tmp, get_mem_index(s));
1168 tcg_gen_addi_i64(tmp, tmp, 8);
1169 tcg_gen_qemu_ld64(tmp3, tmp, get_mem_index(s));
1170 gen_helper_load_psw(cpu_env, tmp2, tmp3);
1171 /* we need to keep cc_op intact */
1172 s->is_jmp = DISAS_JUMP;
1173 tcg_temp_free_i64(tmp);
1174 tcg_temp_free_i64(tmp2);
1175 tcg_temp_free_i64(tmp3);
1176 break;
1177 case 0x20: /* SERVC R1,R2 [RRE] */
1178 /* SCLP Service call (PV hypercall) */
1179 check_privileged(s);
1180 potential_page_fault(s);
1181 tmp32_1 = load_reg32(r2);
1182 tmp = load_reg(r1);
1183 gen_helper_servc(cc_op, cpu_env, tmp32_1, tmp);
1184 set_cc_static(s);
1185 tcg_temp_free_i32(tmp32_1);
1186 tcg_temp_free_i64(tmp);
1187 break;
1188 default:
1189 #endif
1190 LOG_DISAS("illegal b2 operation 0x%x\n", op);
1191 gen_illegal_opcode(s);
1192 #ifndef CONFIG_USER_ONLY
1193 break;
1194 }
1195 #endif
1196 }
1197
1198 static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
1199 {
1200 unsigned char opc;
1201 uint64_t insn;
1202 int op;
1203
1204 opc = cpu_ldub_code(env, s->pc);
1205 LOG_DISAS("opc 0x%x\n", opc);
1206
1207 switch (opc) {
1208 case 0xb2:
1209 insn = ld_code4(env, s->pc);
1210 op = (insn >> 16) & 0xff;
1211 disas_b2(env, s, op, insn);
1212 break;
1213 default:
1214 qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%x\n", opc);
1215 gen_illegal_opcode(s);
1216 break;
1217 }
1218 }
1219
1220 /* ====================================================================== */
1221 /* Define the insn format enumeration. */
1222 #define F0(N) FMT_##N,
1223 #define F1(N, X1) F0(N)
1224 #define F2(N, X1, X2) F0(N)
1225 #define F3(N, X1, X2, X3) F0(N)
1226 #define F4(N, X1, X2, X3, X4) F0(N)
1227 #define F5(N, X1, X2, X3, X4, X5) F0(N)
1228
1229 typedef enum {
1230 #include "insn-format.def"
1231 } DisasFormat;
1232
1233 #undef F0
1234 #undef F1
1235 #undef F2
1236 #undef F3
1237 #undef F4
1238 #undef F5
1239
1240 /* Define a structure to hold the decoded fields. We'll store each inside
1241 an array indexed by an enum. In order to conserve memory, we'll arrange
1242 for fields that do not exist at the same time to overlap, thus the "C"
1243 for compact. For checking purposes there is an "O" for original index
1244 as well that will be applied to availability bitmaps. */
1245
1246 enum DisasFieldIndexO {
1247 FLD_O_r1,
1248 FLD_O_r2,
1249 FLD_O_r3,
1250 FLD_O_m1,
1251 FLD_O_m3,
1252 FLD_O_m4,
1253 FLD_O_b1,
1254 FLD_O_b2,
1255 FLD_O_b4,
1256 FLD_O_d1,
1257 FLD_O_d2,
1258 FLD_O_d4,
1259 FLD_O_x2,
1260 FLD_O_l1,
1261 FLD_O_l2,
1262 FLD_O_i1,
1263 FLD_O_i2,
1264 FLD_O_i3,
1265 FLD_O_i4,
1266 FLD_O_i5
1267 };
1268
1269 enum DisasFieldIndexC {
1270 FLD_C_r1 = 0,
1271 FLD_C_m1 = 0,
1272 FLD_C_b1 = 0,
1273 FLD_C_i1 = 0,
1274
1275 FLD_C_r2 = 1,
1276 FLD_C_b2 = 1,
1277 FLD_C_i2 = 1,
1278
1279 FLD_C_r3 = 2,
1280 FLD_C_m3 = 2,
1281 FLD_C_i3 = 2,
1282
1283 FLD_C_m4 = 3,
1284 FLD_C_b4 = 3,
1285 FLD_C_i4 = 3,
1286 FLD_C_l1 = 3,
1287
1288 FLD_C_i5 = 4,
1289 FLD_C_d1 = 4,
1290
1291 FLD_C_d2 = 5,
1292
1293 FLD_C_d4 = 6,
1294 FLD_C_x2 = 6,
1295 FLD_C_l2 = 6,
1296
1297 NUM_C_FIELD = 7
1298 };
1299
1300 struct DisasFields {
1301 unsigned op:8;
1302 unsigned op2:8;
1303 unsigned presentC:16;
1304 unsigned int presentO;
1305 int c[NUM_C_FIELD];
1306 };
1307
1308 /* This is the way fields are to be accessed out of DisasFields. */
1309 #define have_field(S, F) have_field1((S), FLD_O_##F)
1310 #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
1311
1312 static bool have_field1(const DisasFields *f, enum DisasFieldIndexO c)
1313 {
1314 return (f->presentO >> c) & 1;
1315 }
1316
1317 static int get_field1(const DisasFields *f, enum DisasFieldIndexO o,
1318 enum DisasFieldIndexC c)
1319 {
1320 assert(have_field1(f, o));
1321 return f->c[c];
1322 }
1323
1324 /* Describe the layout of each field in each format. */
1325 typedef struct DisasField {
1326 unsigned int beg:8;
1327 unsigned int size:8;
1328 unsigned int type:2;
1329 unsigned int indexC:6;
1330 enum DisasFieldIndexO indexO:8;
1331 } DisasField;
1332
1333 typedef struct DisasFormatInfo {
1334 DisasField op[NUM_C_FIELD];
1335 } DisasFormatInfo;
1336
1337 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
1338 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
1339 #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1340 { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
1341 #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1342 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1343 { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
1344 #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1345 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1346 #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1347 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1348 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1349 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
1350 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
1351
1352 #define F0(N) { { } },
1353 #define F1(N, X1) { { X1 } },
1354 #define F2(N, X1, X2) { { X1, X2 } },
1355 #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
1356 #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
1357 #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
1358
1359 static const DisasFormatInfo format_info[] = {
1360 #include "insn-format.def"
1361 };
1362
1363 #undef F0
1364 #undef F1
1365 #undef F2
1366 #undef F3
1367 #undef F4
1368 #undef F5
1369 #undef R
1370 #undef M
1371 #undef BD
1372 #undef BXD
1373 #undef BDL
1374 #undef BXDL
1375 #undef I
1376 #undef L
1377
1378 /* Generally, we'll extract operands into this structures, operate upon
1379 them, and store them back. See the "in1", "in2", "prep", "wout" sets
1380 of routines below for more details. */
1381 typedef struct {
1382 bool g_out, g_out2, g_in1, g_in2;
1383 TCGv_i64 out, out2, in1, in2;
1384 TCGv_i64 addr1;
1385 } DisasOps;
1386
1387 /* Return values from translate_one, indicating the state of the TB. */
1388 typedef enum {
1389 /* Continue the TB. */
1390 NO_EXIT,
1391 /* We have emitted one or more goto_tb. No fixup required. */
1392 EXIT_GOTO_TB,
1393 /* We are not using a goto_tb (for whatever reason), but have updated
1394 the PC (for whatever reason), so there's no need to do it again on
1395 exiting the TB. */
1396 EXIT_PC_UPDATED,
1397 /* We are exiting the TB, but have neither emitted a goto_tb, nor
1398 updated the PC for the next instruction to be executed. */
1399 EXIT_PC_STALE,
1400 /* We are ending the TB with a noreturn function call, e.g. longjmp.
1401 No following code will be executed. */
1402 EXIT_NORETURN,
1403 } ExitStatus;
1404
1405 typedef enum DisasFacility {
1406 FAC_Z, /* zarch (default) */
1407 FAC_CASS, /* compare and swap and store */
1408 FAC_CASS2, /* compare and swap and store 2*/
1409 FAC_DFP, /* decimal floating point */
1410 FAC_DFPR, /* decimal floating point rounding */
1411 FAC_DO, /* distinct operands */
1412 FAC_EE, /* execute extensions */
1413 FAC_EI, /* extended immediate */
1414 FAC_FPE, /* floating point extension */
1415 FAC_FPSSH, /* floating point support sign handling */
1416 FAC_FPRGR, /* FPR-GR transfer */
1417 FAC_GIE, /* general instructions extension */
1418 FAC_HFP_MA, /* HFP multiply-and-add/subtract */
1419 FAC_HW, /* high-word */
1420 FAC_IEEEE_SIM, /* IEEE exception sumilation */
1421 FAC_LOC, /* load/store on condition */
1422 FAC_LD, /* long displacement */
1423 FAC_PC, /* population count */
1424 FAC_SCF, /* store clock fast */
1425 FAC_SFLE, /* store facility list extended */
1426 } DisasFacility;
1427
1428 struct DisasInsn {
1429 unsigned opc:16;
1430 DisasFormat fmt:6;
1431 DisasFacility fac:6;
1432
1433 const char *name;
1434
1435 void (*help_in1)(DisasContext *, DisasFields *, DisasOps *);
1436 void (*help_in2)(DisasContext *, DisasFields *, DisasOps *);
1437 void (*help_prep)(DisasContext *, DisasFields *, DisasOps *);
1438 void (*help_wout)(DisasContext *, DisasFields *, DisasOps *);
1439 void (*help_cout)(DisasContext *, DisasOps *);
1440 ExitStatus (*help_op)(DisasContext *, DisasOps *);
1441
1442 uint64_t data;
1443 };
1444
1445 /* ====================================================================== */
1446 /* Miscelaneous helpers, used by several operations. */
1447
1448 static void help_l2_shift(DisasContext *s, DisasFields *f,
1449 DisasOps *o, int mask)
1450 {
1451 int b2 = get_field(f, b2);
1452 int d2 = get_field(f, d2);
1453
1454 if (b2 == 0) {
1455 o->in2 = tcg_const_i64(d2 & mask);
1456 } else {
1457 o->in2 = get_address(s, 0, b2, d2);
1458 tcg_gen_andi_i64(o->in2, o->in2, mask);
1459 }
1460 }
1461
1462 static ExitStatus help_goto_direct(DisasContext *s, uint64_t dest)
1463 {
1464 if (dest == s->next_pc) {
1465 return NO_EXIT;
1466 }
1467 if (use_goto_tb(s, dest)) {
1468 gen_update_cc_op(s);
1469 tcg_gen_goto_tb(0);
1470 tcg_gen_movi_i64(psw_addr, dest);
1471 tcg_gen_exit_tb((tcg_target_long)s->tb);
1472 return EXIT_GOTO_TB;
1473 } else {
1474 tcg_gen_movi_i64(psw_addr, dest);
1475 return EXIT_PC_UPDATED;
1476 }
1477 }
1478
1479 static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
1480 bool is_imm, int imm, TCGv_i64 cdest)
1481 {
1482 ExitStatus ret;
1483 uint64_t dest = s->pc + 2 * imm;
1484 int lab;
1485
1486 /* Take care of the special cases first. */
1487 if (c->cond == TCG_COND_NEVER) {
1488 ret = NO_EXIT;
1489 goto egress;
1490 }
1491 if (is_imm) {
1492 if (dest == s->next_pc) {
1493 /* Branch to next. */
1494 ret = NO_EXIT;
1495 goto egress;
1496 }
1497 if (c->cond == TCG_COND_ALWAYS) {
1498 ret = help_goto_direct(s, dest);
1499 goto egress;
1500 }
1501 } else {
1502 if (TCGV_IS_UNUSED_I64(cdest)) {
1503 /* E.g. bcr %r0 -> no branch. */
1504 ret = NO_EXIT;
1505 goto egress;
1506 }
1507 if (c->cond == TCG_COND_ALWAYS) {
1508 tcg_gen_mov_i64(psw_addr, cdest);
1509 ret = EXIT_PC_UPDATED;
1510 goto egress;
1511 }
1512 }
1513
1514 if (use_goto_tb(s, s->next_pc)) {
1515 if (is_imm && use_goto_tb(s, dest)) {
1516 /* Both exits can use goto_tb. */
1517 gen_update_cc_op(s);
1518
1519 lab = gen_new_label();
1520 if (c->is_64) {
1521 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1522 } else {
1523 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1524 }
1525
1526 /* Branch not taken. */
1527 tcg_gen_goto_tb(0);
1528 tcg_gen_movi_i64(psw_addr, s->next_pc);
1529 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
1530
1531 /* Branch taken. */
1532 gen_set_label(lab);
1533 tcg_gen_goto_tb(1);
1534 tcg_gen_movi_i64(psw_addr, dest);
1535 tcg_gen_exit_tb((tcg_target_long)s->tb + 1);
1536
1537 ret = EXIT_GOTO_TB;
1538 } else {
1539 /* Fallthru can use goto_tb, but taken branch cannot. */
1540 /* Store taken branch destination before the brcond. This
1541 avoids having to allocate a new local temp to hold it.
1542 We'll overwrite this in the not taken case anyway. */
1543 if (!is_imm) {
1544 tcg_gen_mov_i64(psw_addr, cdest);
1545 }
1546
1547 lab = gen_new_label();
1548 if (c->is_64) {
1549 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1550 } else {
1551 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1552 }
1553
1554 /* Branch not taken. */
1555 gen_update_cc_op(s);
1556 tcg_gen_goto_tb(0);
1557 tcg_gen_movi_i64(psw_addr, s->next_pc);
1558 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
1559
1560 gen_set_label(lab);
1561 if (is_imm) {
1562 tcg_gen_movi_i64(psw_addr, dest);
1563 }
1564 ret = EXIT_PC_UPDATED;
1565 }
1566 } else {
1567 /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
1568 Most commonly we're single-stepping or some other condition that
1569 disables all use of goto_tb. Just update the PC and exit. */
1570
1571 TCGv_i64 next = tcg_const_i64(s->next_pc);
1572 if (is_imm) {
1573 cdest = tcg_const_i64(dest);
1574 }
1575
1576 if (c->is_64) {
1577 tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b,
1578 cdest, next);
1579 } else {
1580 TCGv_i32 t0 = tcg_temp_new_i32();
1581 TCGv_i64 t1 = tcg_temp_new_i64();
1582 TCGv_i64 z = tcg_const_i64(0);
1583 tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b);
1584 tcg_gen_extu_i32_i64(t1, t0);
1585 tcg_temp_free_i32(t0);
1586 tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next);
1587 tcg_temp_free_i64(t1);
1588 tcg_temp_free_i64(z);
1589 }
1590
1591 if (is_imm) {
1592 tcg_temp_free_i64(cdest);
1593 }
1594 tcg_temp_free_i64(next);
1595
1596 ret = EXIT_PC_UPDATED;
1597 }
1598
1599 egress:
1600 free_compare(c);
1601 return ret;
1602 }
1603
1604 /* ====================================================================== */
1605 /* The operations. These perform the bulk of the work for any insn,
1606 usually after the operands have been loaded and output initialized. */
1607
1608 static ExitStatus op_abs(DisasContext *s, DisasOps *o)
1609 {
1610 gen_helper_abs_i64(o->out, o->in2);
1611 return NO_EXIT;
1612 }
1613
1614 static ExitStatus op_absf32(DisasContext *s, DisasOps *o)
1615 {
1616 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffull);
1617 return NO_EXIT;
1618 }
1619
1620 static ExitStatus op_absf64(DisasContext *s, DisasOps *o)
1621 {
1622 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull);
1623 return NO_EXIT;
1624 }
1625
1626 static ExitStatus op_absf128(DisasContext *s, DisasOps *o)
1627 {
1628 tcg_gen_andi_i64(o->out, o->in1, 0x7fffffffffffffffull);
1629 tcg_gen_mov_i64(o->out2, o->in2);
1630 return NO_EXIT;
1631 }
1632
1633 static ExitStatus op_add(DisasContext *s, DisasOps *o)
1634 {
1635 tcg_gen_add_i64(o->out, o->in1, o->in2);
1636 return NO_EXIT;
1637 }
1638
1639 static ExitStatus op_addc(DisasContext *s, DisasOps *o)
1640 {
1641 TCGv_i64 cc;
1642
1643 tcg_gen_add_i64(o->out, o->in1, o->in2);
1644
1645 /* XXX possible optimization point */
1646 gen_op_calc_cc(s);
1647 cc = tcg_temp_new_i64();
1648 tcg_gen_extu_i32_i64(cc, cc_op);
1649 tcg_gen_shri_i64(cc, cc, 1);
1650
1651 tcg_gen_add_i64(o->out, o->out, cc);
1652 tcg_temp_free_i64(cc);
1653 return NO_EXIT;
1654 }
1655
1656 static ExitStatus op_aeb(DisasContext *s, DisasOps *o)
1657 {
1658 gen_helper_aeb(o->out, cpu_env, o->in1, o->in2);
1659 return NO_EXIT;
1660 }
1661
1662 static ExitStatus op_adb(DisasContext *s, DisasOps *o)
1663 {
1664 gen_helper_adb(o->out, cpu_env, o->in1, o->in2);
1665 return NO_EXIT;
1666 }
1667
1668 static ExitStatus op_axb(DisasContext *s, DisasOps *o)
1669 {
1670 gen_helper_axb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
1671 return_low128(o->out2);
1672 return NO_EXIT;
1673 }
1674
1675 static ExitStatus op_and(DisasContext *s, DisasOps *o)
1676 {
1677 tcg_gen_and_i64(o->out, o->in1, o->in2);
1678 return NO_EXIT;
1679 }
1680
1681 static ExitStatus op_andi(DisasContext *s, DisasOps *o)
1682 {
1683 int shift = s->insn->data & 0xff;
1684 int size = s->insn->data >> 8;
1685 uint64_t mask = ((1ull << size) - 1) << shift;
1686
1687 assert(!o->g_in2);
1688 tcg_gen_shli_i64(o->in2, o->in2, shift);
1689 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
1690 tcg_gen_and_i64(o->out, o->in1, o->in2);
1691
1692 /* Produce the CC from only the bits manipulated. */
1693 tcg_gen_andi_i64(cc_dst, o->out, mask);
1694 set_cc_nz_u64(s, cc_dst);
1695 return NO_EXIT;
1696 }
1697
1698 static ExitStatus op_bas(DisasContext *s, DisasOps *o)
1699 {
1700 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1701 if (!TCGV_IS_UNUSED_I64(o->in2)) {
1702 tcg_gen_mov_i64(psw_addr, o->in2);
1703 return EXIT_PC_UPDATED;
1704 } else {
1705 return NO_EXIT;
1706 }
1707 }
1708
1709 static ExitStatus op_basi(DisasContext *s, DisasOps *o)
1710 {
1711 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1712 return help_goto_direct(s, s->pc + 2 * get_field(s->fields, i2));
1713 }
1714
1715 static ExitStatus op_bc(DisasContext *s, DisasOps *o)
1716 {
1717 int m1 = get_field(s->fields, m1);
1718 bool is_imm = have_field(s->fields, i2);
1719 int imm = is_imm ? get_field(s->fields, i2) : 0;
1720 DisasCompare c;
1721
1722 disas_jcc(s, &c, m1);
1723 return help_branch(s, &c, is_imm, imm, o->in2);
1724 }
1725
1726 static ExitStatus op_bct32(DisasContext *s, DisasOps *o)
1727 {
1728 int r1 = get_field(s->fields, r1);
1729 bool is_imm = have_field(s->fields, i2);
1730 int imm = is_imm ? get_field(s->fields, i2) : 0;
1731 DisasCompare c;
1732 TCGv_i64 t;
1733
1734 c.cond = TCG_COND_NE;
1735 c.is_64 = false;
1736 c.g1 = false;
1737 c.g2 = false;
1738
1739 t = tcg_temp_new_i64();
1740 tcg_gen_subi_i64(t, regs[r1], 1);
1741 store_reg32_i64(r1, t);
1742 c.u.s32.a = tcg_temp_new_i32();
1743 c.u.s32.b = tcg_const_i32(0);
1744 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
1745 tcg_temp_free_i64(t);
1746
1747 return help_branch(s, &c, is_imm, imm, o->in2);
1748 }
1749
1750 static ExitStatus op_bct64(DisasContext *s, DisasOps *o)
1751 {
1752 int r1 = get_field(s->fields, r1);
1753 bool is_imm = have_field(s->fields, i2);
1754 int imm = is_imm ? get_field(s->fields, i2) : 0;
1755 DisasCompare c;
1756
1757 c.cond = TCG_COND_NE;
1758 c.is_64 = true;
1759 c.g1 = true;
1760 c.g2 = false;
1761
1762 tcg_gen_subi_i64(regs[r1], regs[r1], 1);
1763 c.u.s64.a = regs[r1];
1764 c.u.s64.b = tcg_const_i64(0);
1765
1766 return help_branch(s, &c, is_imm, imm, o->in2);
1767 }
1768
1769 static ExitStatus op_ceb(DisasContext *s, DisasOps *o)
1770 {
1771 gen_helper_ceb(cc_op, cpu_env, o->in1, o->in2);
1772 set_cc_static(s);
1773 return NO_EXIT;
1774 }
1775
1776 static ExitStatus op_cdb(DisasContext *s, DisasOps *o)
1777 {
1778 gen_helper_cdb(cc_op, cpu_env, o->in1, o->in2);
1779 set_cc_static(s);
1780 return NO_EXIT;
1781 }
1782
1783 static ExitStatus op_cxb(DisasContext *s, DisasOps *o)
1784 {
1785 gen_helper_cxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2);
1786 set_cc_static(s);
1787 return NO_EXIT;
1788 }
1789
1790 static ExitStatus op_cfeb(DisasContext *s, DisasOps *o)
1791 {
1792 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1793 gen_helper_cfeb(o->out, cpu_env, o->in2, m3);
1794 tcg_temp_free_i32(m3);
1795 gen_set_cc_nz_f32(s, o->in2);
1796 return NO_EXIT;
1797 }
1798
1799 static ExitStatus op_cfdb(DisasContext *s, DisasOps *o)
1800 {
1801 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1802 gen_helper_cfdb(o->out, cpu_env, o->in2, m3);
1803 tcg_temp_free_i32(m3);
1804 gen_set_cc_nz_f64(s, o->in2);
1805 return NO_EXIT;
1806 }
1807
1808 static ExitStatus op_cfxb(DisasContext *s, DisasOps *o)
1809 {
1810 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1811 gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m3);
1812 tcg_temp_free_i32(m3);
1813 gen_set_cc_nz_f128(s, o->in1, o->in2);
1814 return NO_EXIT;
1815 }
1816
1817 static ExitStatus op_cgeb(DisasContext *s, DisasOps *o)
1818 {
1819 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1820 gen_helper_cgeb(o->out, cpu_env, o->in2, m3);
1821 tcg_temp_free_i32(m3);
1822 gen_set_cc_nz_f32(s, o->in2);
1823 return NO_EXIT;
1824 }
1825
1826 static ExitStatus op_cgdb(DisasContext *s, DisasOps *o)
1827 {
1828 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1829 gen_helper_cgdb(o->out, cpu_env, o->in2, m3);
1830 tcg_temp_free_i32(m3);
1831 gen_set_cc_nz_f64(s, o->in2);
1832 return NO_EXIT;
1833 }
1834
1835 static ExitStatus op_cgxb(DisasContext *s, DisasOps *o)
1836 {
1837 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1838 gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m3);
1839 tcg_temp_free_i32(m3);
1840 gen_set_cc_nz_f128(s, o->in1, o->in2);
1841 return NO_EXIT;
1842 }
1843
1844 static ExitStatus op_cegb(DisasContext *s, DisasOps *o)
1845 {
1846 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1847 gen_helper_cegb(o->out, cpu_env, o->in2, m3);
1848 tcg_temp_free_i32(m3);
1849 return NO_EXIT;
1850 }
1851
1852 static ExitStatus op_cdgb(DisasContext *s, DisasOps *o)
1853 {
1854 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1855 gen_helper_cdgb(o->out, cpu_env, o->in2, m3);
1856 tcg_temp_free_i32(m3);
1857 return NO_EXIT;
1858 }
1859
1860 static ExitStatus op_cxgb(DisasContext *s, DisasOps *o)
1861 {
1862 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1863 gen_helper_cxgb(o->out, cpu_env, o->in2, m3);
1864 tcg_temp_free_i32(m3);
1865 return_low128(o->out2);
1866 return NO_EXIT;
1867 }
1868
1869 static ExitStatus op_cksm(DisasContext *s, DisasOps *o)
1870 {
1871 int r2 = get_field(s->fields, r2);
1872 TCGv_i64 len = tcg_temp_new_i64();
1873
1874 potential_page_fault(s);
1875 gen_helper_cksm(len, cpu_env, o->in1, o->in2, regs[r2 + 1]);
1876 set_cc_static(s);
1877 return_low128(o->out);
1878
1879 tcg_gen_add_i64(regs[r2], regs[r2], len);
1880 tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len);
1881 tcg_temp_free_i64(len);
1882
1883 return NO_EXIT;
1884 }
1885
1886 static ExitStatus op_clc(DisasContext *s, DisasOps *o)
1887 {
1888 int l = get_field(s->fields, l1);
1889 TCGv_i32 vl;
1890
1891 switch (l + 1) {
1892 case 1:
1893 tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s));
1894 tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s));
1895 break;
1896 case 2:
1897 tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s));
1898 tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s));
1899 break;
1900 case 4:
1901 tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s));
1902 tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s));
1903 break;
1904 case 8:
1905 tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s));
1906 tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
1907 break;
1908 default:
1909 potential_page_fault(s);
1910 vl = tcg_const_i32(l);
1911 gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
1912 tcg_temp_free_i32(vl);
1913 set_cc_static(s);
1914 return NO_EXIT;
1915 }
1916 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
1917 return NO_EXIT;
1918 }
1919
1920 static ExitStatus op_clcle(DisasContext *s, DisasOps *o)
1921 {
1922 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1923 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
1924 potential_page_fault(s);
1925 gen_helper_clcle(cc_op, cpu_env, r1, o->in2, r3);
1926 tcg_temp_free_i32(r1);
1927 tcg_temp_free_i32(r3);
1928 set_cc_static(s);
1929 return NO_EXIT;
1930 }
1931
1932 static ExitStatus op_clm(DisasContext *s, DisasOps *o)
1933 {
1934 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1935 TCGv_i32 t1 = tcg_temp_new_i32();
1936 tcg_gen_trunc_i64_i32(t1, o->in1);
1937 potential_page_fault(s);
1938 gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2);
1939 set_cc_static(s);
1940 tcg_temp_free_i32(t1);
1941 tcg_temp_free_i32(m3);
1942 return NO_EXIT;
1943 }
1944
1945 static ExitStatus op_clst(DisasContext *s, DisasOps *o)
1946 {
1947 potential_page_fault(s);
1948 gen_helper_clst(o->in1, cpu_env, regs[0], o->in1, o->in2);
1949 set_cc_static(s);
1950 return_low128(o->in2);
1951 return NO_EXIT;
1952 }
1953
1954 static ExitStatus op_cs(DisasContext *s, DisasOps *o)
1955 {
1956 int r3 = get_field(s->fields, r3);
1957 potential_page_fault(s);
1958 gen_helper_cs(o->out, cpu_env, o->in1, o->in2, regs[r3]);
1959 set_cc_static(s);
1960 return NO_EXIT;
1961 }
1962
1963 static ExitStatus op_csg(DisasContext *s, DisasOps *o)
1964 {
1965 int r3 = get_field(s->fields, r3);
1966 potential_page_fault(s);
1967 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, regs[r3]);
1968 set_cc_static(s);
1969 return NO_EXIT;
1970 }
1971
1972 static ExitStatus op_cds(DisasContext *s, DisasOps *o)
1973 {
1974 int r3 = get_field(s->fields, r3);
1975 TCGv_i64 in3 = tcg_temp_new_i64();
1976 tcg_gen_deposit_i64(in3, regs[r3 + 1], regs[r3], 32, 32);
1977 potential_page_fault(s);
1978 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, in3);
1979 tcg_temp_free_i64(in3);
1980 set_cc_static(s);
1981 return NO_EXIT;
1982 }
1983
1984 static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
1985 {
1986 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1987 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
1988 potential_page_fault(s);
1989 /* XXX rewrite in tcg */
1990 gen_helper_cdsg(cc_op, cpu_env, r1, o->in2, r3);
1991 set_cc_static(s);
1992 return NO_EXIT;
1993 }
1994
1995 static ExitStatus op_cvd(DisasContext *s, DisasOps *o)
1996 {
1997 TCGv_i64 t1 = tcg_temp_new_i64();
1998 TCGv_i32 t2 = tcg_temp_new_i32();
1999 tcg_gen_trunc_i64_i32(t2, o->in1);
2000 gen_helper_cvd(t1, t2);
2001 tcg_temp_free_i32(t2);
2002 tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
2003 tcg_temp_free_i64(t1);
2004 return NO_EXIT;
2005 }
2006
2007 #ifndef CONFIG_USER_ONLY
2008 static ExitStatus op_diag(DisasContext *s, DisasOps *o)
2009 {
2010 TCGv_i32 tmp;
2011
2012 check_privileged(s);
2013 potential_page_fault(s);
2014
2015 /* We pretend the format is RX_a so that D2 is the field we want. */
2016 tmp = tcg_const_i32(get_field(s->fields, d2) & 0xfff);
2017 gen_helper_diag(regs[2], cpu_env, tmp, regs[2], regs[1]);
2018 tcg_temp_free_i32(tmp);
2019 return NO_EXIT;
2020 }
2021 #endif
2022
2023 static ExitStatus op_divs32(DisasContext *s, DisasOps *o)
2024 {
2025 gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2);
2026 return_low128(o->out);
2027 return NO_EXIT;
2028 }
2029
2030 static ExitStatus op_divu32(DisasContext *s, DisasOps *o)
2031 {
2032 gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2);
2033 return_low128(o->out);
2034 return NO_EXIT;
2035 }
2036
2037 static ExitStatus op_divs64(DisasContext *s, DisasOps *o)
2038 {
2039 gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2);
2040 return_low128(o->out);
2041 return NO_EXIT;
2042 }
2043
2044 static ExitStatus op_divu64(DisasContext *s, DisasOps *o)
2045 {
2046 gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2);
2047 return_low128(o->out);
2048 return NO_EXIT;
2049 }
2050
2051 static ExitStatus op_deb(DisasContext *s, DisasOps *o)
2052 {
2053 gen_helper_deb(o->out, cpu_env, o->in1, o->in2);
2054 return NO_EXIT;
2055 }
2056
2057 static ExitStatus op_ddb(DisasContext *s, DisasOps *o)
2058 {
2059 gen_helper_ddb(o->out, cpu_env, o->in1, o->in2);
2060 return NO_EXIT;
2061 }
2062
2063 static ExitStatus op_dxb(DisasContext *s, DisasOps *o)
2064 {
2065 gen_helper_dxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2066 return_low128(o->out2);
2067 return NO_EXIT;
2068 }
2069
2070 static ExitStatus op_ear(DisasContext *s, DisasOps *o)
2071 {
2072 int r2 = get_field(s->fields, r2);
2073 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, aregs[r2]));
2074 return NO_EXIT;
2075 }
2076
2077 static ExitStatus op_efpc(DisasContext *s, DisasOps *o)
2078 {
2079 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, fpc));
2080 return NO_EXIT;
2081 }
2082
2083 static ExitStatus op_ex(DisasContext *s, DisasOps *o)
2084 {
2085 /* ??? Perhaps a better way to implement EXECUTE is to set a bit in
2086 tb->flags, (ab)use the tb->cs_base field as the address of
2087 the template in memory, and grab 8 bits of tb->flags/cflags for
2088 the contents of the register. We would then recognize all this
2089 in gen_intermediate_code_internal, generating code for exactly
2090 one instruction. This new TB then gets executed normally.
2091
2092 On the other hand, this seems to be mostly used for modifying
2093 MVC inside of memcpy, which needs a helper call anyway. So
2094 perhaps this doesn't bear thinking about any further. */
2095
2096 TCGv_i64 tmp;
2097
2098 update_psw_addr(s);
2099 gen_op_calc_cc(s);
2100
2101 tmp = tcg_const_i64(s->next_pc);
2102 gen_helper_ex(cc_op, cpu_env, cc_op, o->in1, o->in2, tmp);
2103 tcg_temp_free_i64(tmp);
2104
2105 set_cc_static(s);
2106 return NO_EXIT;
2107 }
2108
2109 static ExitStatus op_flogr(DisasContext *s, DisasOps *o)
2110 {
2111 /* We'll use the original input for cc computation, since we get to
2112 compare that against 0, which ought to be better than comparing
2113 the real output against 64. It also lets cc_dst be a convenient
2114 temporary during our computation. */
2115 gen_op_update1_cc_i64(s, CC_OP_FLOGR, o->in2);
2116
2117 /* R1 = IN ? CLZ(IN) : 64. */
2118 gen_helper_clz(o->out, o->in2);
2119
2120 /* R1+1 = IN & ~(found bit). Note that we may attempt to shift this
2121 value by 64, which is undefined. But since the shift is 64 iff the
2122 input is zero, we still get the correct result after and'ing. */
2123 tcg_gen_movi_i64(o->out2, 0x8000000000000000ull);
2124 tcg_gen_shr_i64(o->out2, o->out2, o->out);
2125 tcg_gen_andc_i64(o->out2, cc_dst, o->out2);
2126 return NO_EXIT;
2127 }
2128
2129 static ExitStatus op_icm(DisasContext *s, DisasOps *o)
2130 {
2131 int m3 = get_field(s->fields, m3);
2132 int pos, len, base = s->insn->data;
2133 TCGv_i64 tmp = tcg_temp_new_i64();
2134 uint64_t ccm;
2135
2136 switch (m3) {
2137 case 0xf:
2138 /* Effectively a 32-bit load. */
2139 tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
2140 len = 32;
2141 goto one_insert;
2142
2143 case 0xc:
2144 case 0x6:
2145 case 0x3:
2146 /* Effectively a 16-bit load. */
2147 tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
2148 len = 16;
2149 goto one_insert;
2150
2151 case 0x8:
2152 case 0x4:
2153 case 0x2:
2154 case 0x1:
2155 /* Effectively an 8-bit load. */
2156 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2157 len = 8;
2158 goto one_insert;
2159
2160 one_insert:
2161 pos = base + ctz32(m3) * 8;
2162 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len);
2163 ccm = ((1ull << len) - 1) << pos;
2164 break;
2165
2166 default:
2167 /* This is going to be a sequence of loads and inserts. */
2168 pos = base + 32 - 8;
2169 ccm = 0;
2170 while (m3) {
2171 if (m3 & 0x8) {
2172 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2173 tcg_gen_addi_i64(o->in2, o->in2, 1);
2174 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
2175 ccm |= 0xff << pos;
2176 }
2177 m3 = (m3 << 1) & 0xf;
2178 pos -= 8;
2179 }
2180 break;
2181 }
2182
2183 tcg_gen_movi_i64(tmp, ccm);
2184 gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out);
2185 tcg_temp_free_i64(tmp);
2186 return NO_EXIT;
2187 }
2188
2189 static ExitStatus op_insi(DisasContext *s, DisasOps *o)
2190 {
2191 int shift = s->insn->data & 0xff;
2192 int size = s->insn->data >> 8;
2193 tcg_gen_deposit_i64(o->out, o->in1, o->in2, shift, size);
2194 return NO_EXIT;
2195 }
2196
2197 static ExitStatus op_ipm(DisasContext *s, DisasOps *o)
2198 {
2199 TCGv_i64 t1;
2200
2201 gen_op_calc_cc(s);
2202 tcg_gen_andi_i64(o->out, o->out, ~0xff000000ull);
2203
2204 t1 = tcg_temp_new_i64();
2205 tcg_gen_shli_i64(t1, psw_mask, 20);
2206 tcg_gen_shri_i64(t1, t1, 36);
2207 tcg_gen_or_i64(o->out, o->out, t1);
2208
2209 tcg_gen_extu_i32_i64(t1, cc_op);
2210 tcg_gen_shli_i64(t1, t1, 28);
2211 tcg_gen_or_i64(o->out, o->out, t1);
2212 tcg_temp_free_i64(t1);
2213 return NO_EXIT;
2214 }
2215
2216 static ExitStatus op_ldeb(DisasContext *s, DisasOps *o)
2217 {
2218 gen_helper_ldeb(o->out, cpu_env, o->in2);
2219 return NO_EXIT;
2220 }
2221
2222 static ExitStatus op_ledb(DisasContext *s, DisasOps *o)
2223 {
2224 gen_helper_ledb(o->out, cpu_env, o->in2);
2225 return NO_EXIT;
2226 }
2227
2228 static ExitStatus op_ldxb(DisasContext *s, DisasOps *o)
2229 {
2230 gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2);
2231 return NO_EXIT;
2232 }
2233
2234 static ExitStatus op_lexb(DisasContext *s, DisasOps *o)
2235 {
2236 gen_helper_lexb(o->out, cpu_env, o->in1, o->in2);
2237 return NO_EXIT;
2238 }
2239
2240 static ExitStatus op_lxdb(DisasContext *s, DisasOps *o)
2241 {
2242 gen_helper_lxdb(o->out, cpu_env, o->in2);
2243 return_low128(o->out2);
2244 return NO_EXIT;
2245 }
2246
2247 static ExitStatus op_lxeb(DisasContext *s, DisasOps *o)
2248 {
2249 gen_helper_lxeb(o->out, cpu_env, o->in2);
2250 return_low128(o->out2);
2251 return NO_EXIT;
2252 }
2253
2254 static ExitStatus op_llgt(DisasContext *s, DisasOps *o)
2255 {
2256 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffff);
2257 return NO_EXIT;
2258 }
2259
2260 static ExitStatus op_ld8s(DisasContext *s, DisasOps *o)
2261 {
2262 tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
2263 return NO_EXIT;
2264 }
2265
2266 static ExitStatus op_ld8u(DisasContext *s, DisasOps *o)
2267 {
2268 tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
2269 return NO_EXIT;
2270 }
2271
2272 static ExitStatus op_ld16s(DisasContext *s, DisasOps *o)
2273 {
2274 tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
2275 return NO_EXIT;
2276 }
2277
2278 static ExitStatus op_ld16u(DisasContext *s, DisasOps *o)
2279 {
2280 tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
2281 return NO_EXIT;
2282 }
2283
2284 static ExitStatus op_ld32s(DisasContext *s, DisasOps *o)
2285 {
2286 tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s));
2287 return NO_EXIT;
2288 }
2289
2290 static ExitStatus op_ld32u(DisasContext *s, DisasOps *o)
2291 {
2292 tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
2293 return NO_EXIT;
2294 }
2295
2296 static ExitStatus op_ld64(DisasContext *s, DisasOps *o)
2297 {
2298 tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
2299 return NO_EXIT;
2300 }
2301
2302 #ifndef CONFIG_USER_ONLY
2303 static ExitStatus op_lctl(DisasContext *s, DisasOps *o)
2304 {
2305 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2306 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2307 check_privileged(s);
2308 potential_page_fault(s);
2309 gen_helper_lctl(cpu_env, r1, o->in2, r3);
2310 tcg_temp_free_i32(r1);
2311 tcg_temp_free_i32(r3);
2312 return NO_EXIT;
2313 }
2314
2315 static ExitStatus op_lctlg(DisasContext *s, DisasOps *o)
2316 {
2317 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2318 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2319 check_privileged(s);
2320 potential_page_fault(s);
2321 gen_helper_lctlg(cpu_env, r1, o->in2, r3);
2322 tcg_temp_free_i32(r1);
2323 tcg_temp_free_i32(r3);
2324 return NO_EXIT;
2325 }
2326 static ExitStatus op_lra(DisasContext *s, DisasOps *o)
2327 {
2328 check_privileged(s);
2329 potential_page_fault(s);
2330 gen_helper_lra(o->out, cpu_env, o->in2);
2331 set_cc_static(s);
2332 return NO_EXIT;
2333 }
2334
2335 static ExitStatus op_lpsw(DisasContext *s, DisasOps *o)
2336 {
2337 TCGv_i64 t1, t2;
2338
2339 check_privileged(s);
2340
2341 t1 = tcg_temp_new_i64();
2342 t2 = tcg_temp_new_i64();
2343 tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
2344 tcg_gen_addi_i64(o->in2, o->in2, 4);
2345 tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s));
2346 /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
2347 tcg_gen_shli_i64(t1, t1, 32);
2348 gen_helper_load_psw(cpu_env, t1, t2);
2349 tcg_temp_free_i64(t1);
2350 tcg_temp_free_i64(t2);
2351 return EXIT_NORETURN;
2352 }
2353 #endif
2354
2355 static ExitStatus op_lam(DisasContext *s, DisasOps *o)
2356 {
2357 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2358 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2359 potential_page_fault(s);
2360 gen_helper_lam(cpu_env, r1, o->in2, r3);
2361 tcg_temp_free_i32(r1);
2362 tcg_temp_free_i32(r3);
2363 return NO_EXIT;
2364 }
2365
2366 static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
2367 {
2368 int r1 = get_field(s->fields, r1);
2369 int r3 = get_field(s->fields, r3);
2370 TCGv_i64 t = tcg_temp_new_i64();
2371 TCGv_i64 t4 = tcg_const_i64(4);
2372
2373 while (1) {
2374 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2375 store_reg32_i64(r1, t);
2376 if (r1 == r3) {
2377 break;
2378 }
2379 tcg_gen_add_i64(o->in2, o->in2, t4);
2380 r1 = (r1 + 1) & 15;
2381 }
2382
2383 tcg_temp_free_i64(t);
2384 tcg_temp_free_i64(t4);
2385 return NO_EXIT;
2386 }
2387
2388 static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
2389 {
2390 int r1 = get_field(s->fields, r1);
2391 int r3 = get_field(s->fields, r3);
2392 TCGv_i64 t = tcg_temp_new_i64();
2393 TCGv_i64 t4 = tcg_const_i64(4);
2394
2395 while (1) {
2396 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2397 store_reg32h_i64(r1, t);
2398 if (r1 == r3) {
2399 break;
2400 }
2401 tcg_gen_add_i64(o->in2, o->in2, t4);
2402 r1 = (r1 + 1) & 15;
2403 }
2404
2405 tcg_temp_free_i64(t);
2406 tcg_temp_free_i64(t4);
2407 return NO_EXIT;
2408 }
2409
2410 static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
2411 {
2412 int r1 = get_field(s->fields, r1);
2413 int r3 = get_field(s->fields, r3);
2414 TCGv_i64 t8 = tcg_const_i64(8);
2415
2416 while (1) {
2417 tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
2418 if (r1 == r3) {
2419 break;
2420 }
2421 tcg_gen_add_i64(o->in2, o->in2, t8);
2422 r1 = (r1 + 1) & 15;
2423 }
2424
2425 tcg_temp_free_i64(t8);
2426 return NO_EXIT;
2427 }
2428
2429 static ExitStatus op_mov2(DisasContext *s, DisasOps *o)
2430 {
2431 o->out = o->in2;
2432 o->g_out = o->g_in2;
2433 TCGV_UNUSED_I64(o->in2);
2434 o->g_in2 = false;
2435 return NO_EXIT;
2436 }
2437
2438 static ExitStatus op_movx(DisasContext *s, DisasOps *o)
2439 {
2440 o->out = o->in1;
2441 o->out2 = o->in2;
2442 o->g_out = o->g_in1;
2443 o->g_out2 = o->g_in2;
2444 TCGV_UNUSED_I64(o->in1);
2445 TCGV_UNUSED_I64(o->in2);
2446 o->g_in1 = o->g_in2 = false;
2447 return NO_EXIT;
2448 }
2449
2450 static ExitStatus op_mvc(DisasContext *s, DisasOps *o)
2451 {
2452 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2453 potential_page_fault(s);
2454 gen_helper_mvc(cpu_env, l, o->addr1, o->in2);
2455 tcg_temp_free_i32(l);
2456 return NO_EXIT;
2457 }
2458
2459 static ExitStatus op_mvcl(DisasContext *s, DisasOps *o)
2460 {
2461 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2462 TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
2463 potential_page_fault(s);
2464 gen_helper_mvcl(cc_op, cpu_env, r1, r2);
2465 tcg_temp_free_i32(r1);
2466 tcg_temp_free_i32(r2);
2467 set_cc_static(s);
2468 return NO_EXIT;
2469 }
2470
2471 static ExitStatus op_mvcle(DisasContext *s, DisasOps *o)
2472 {
2473 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2474 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2475 potential_page_fault(s);
2476 gen_helper_mvcle(cc_op, cpu_env, r1, o->in2, r3);
2477 tcg_temp_free_i32(r1);
2478 tcg_temp_free_i32(r3);
2479 set_cc_static(s);
2480 return NO_EXIT;
2481 }
2482
2483 #ifndef CONFIG_USER_ONLY
2484 static ExitStatus op_mvcp(DisasContext *s, DisasOps *o)
2485 {
2486 int r1 = get_field(s->fields, l1);
2487 check_privileged(s);
2488 potential_page_fault(s);
2489 gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2490 set_cc_static(s);
2491 return NO_EXIT;
2492 }
2493
2494 static ExitStatus op_mvcs(DisasContext *s, DisasOps *o)
2495 {
2496 int r1 = get_field(s->fields, l1);
2497 check_privileged(s);
2498 potential_page_fault(s);
2499 gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2500 set_cc_static(s);
2501 return NO_EXIT;
2502 }
2503 #endif
2504
2505 static ExitStatus op_mvpg(DisasContext *s, DisasOps *o)
2506 {
2507 potential_page_fault(s);
2508 gen_helper_mvpg(cpu_env, regs[0], o->in1, o->in2);
2509 set_cc_static(s);
2510 return NO_EXIT;
2511 }
2512
2513 static ExitStatus op_mvst(DisasContext *s, DisasOps *o)
2514 {
2515 potential_page_fault(s);
2516 gen_helper_mvst(o->in1, cpu_env, regs[0], o->in1, o->in2);
2517 set_cc_static(s);
2518 return_low128(o->in2);
2519 return NO_EXIT;
2520 }
2521
2522 static ExitStatus op_mul(DisasContext *s, DisasOps *o)
2523 {
2524 tcg_gen_mul_i64(o->out, o->in1, o->in2);
2525 return NO_EXIT;
2526 }
2527
2528 static ExitStatus op_mul128(DisasContext *s, DisasOps *o)
2529 {
2530 gen_helper_mul128(o->out, cpu_env, o->in1, o->in2);
2531 return_low128(o->out2);
2532 return NO_EXIT;
2533 }
2534
2535 static ExitStatus op_meeb(DisasContext *s, DisasOps *o)
2536 {
2537 gen_helper_meeb(o->out, cpu_env, o->in1, o->in2);
2538 return NO_EXIT;
2539 }
2540
2541 static ExitStatus op_mdeb(DisasContext *s, DisasOps *o)
2542 {
2543 gen_helper_mdeb(o->out, cpu_env, o->in1, o->in2);
2544 return NO_EXIT;
2545 }
2546
2547 static ExitStatus op_mdb(DisasContext *s, DisasOps *o)
2548 {
2549 gen_helper_mdb(o->out, cpu_env, o->in1, o->in2);
2550 return NO_EXIT;
2551 }
2552
2553 static ExitStatus op_mxb(DisasContext *s, DisasOps *o)
2554 {
2555 gen_helper_mxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2556 return_low128(o->out2);
2557 return NO_EXIT;
2558 }
2559
2560 static ExitStatus op_mxdb(DisasContext *s, DisasOps *o)
2561 {
2562 gen_helper_mxdb(o->out, cpu_env, o->out, o->out2, o->in2);
2563 return_low128(o->out2);
2564 return NO_EXIT;
2565 }
2566
2567 static ExitStatus op_maeb(DisasContext *s, DisasOps *o)
2568 {
2569 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2570 gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3);
2571 tcg_temp_free_i64(r3);
2572 return NO_EXIT;
2573 }
2574
2575 static ExitStatus op_madb(DisasContext *s, DisasOps *o)
2576 {
2577 int r3 = get_field(s->fields, r3);
2578 gen_helper_madb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2579 return NO_EXIT;
2580 }
2581
2582 static ExitStatus op_mseb(DisasContext *s, DisasOps *o)
2583 {
2584 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2585 gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3);
2586 tcg_temp_free_i64(r3);
2587 return NO_EXIT;
2588 }
2589
2590 static ExitStatus op_msdb(DisasContext *s, DisasOps *o)
2591 {
2592 int r3 = get_field(s->fields, r3);
2593 gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2594 return NO_EXIT;
2595 }
2596
2597 static ExitStatus op_nabs(DisasContext *s, DisasOps *o)
2598 {
2599 gen_helper_nabs_i64(o->out, o->in2);
2600 return NO_EXIT;
2601 }
2602
2603 static ExitStatus op_nabsf32(DisasContext *s, DisasOps *o)
2604 {
2605 tcg_gen_ori_i64(o->out, o->in2, 0x80000000ull);
2606 return NO_EXIT;
2607 }
2608
2609 static ExitStatus op_nabsf64(DisasContext *s, DisasOps *o)
2610 {
2611 tcg_gen_ori_i64(o->out, o->in2, 0x8000000000000000ull);
2612 return NO_EXIT;
2613 }
2614
2615 static ExitStatus op_nabsf128(DisasContext *s, DisasOps *o)
2616 {
2617 tcg_gen_ori_i64(o->out, o->in1, 0x8000000000000000ull);
2618 tcg_gen_mov_i64(o->out2, o->in2);
2619 return NO_EXIT;
2620 }
2621
2622 static ExitStatus op_nc(DisasContext *s, DisasOps *o)
2623 {
2624 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2625 potential_page_fault(s);
2626 gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2);
2627 tcg_temp_free_i32(l);
2628 set_cc_static(s);
2629 return NO_EXIT;
2630 }
2631
2632 static ExitStatus op_neg(DisasContext *s, DisasOps *o)
2633 {
2634 tcg_gen_neg_i64(o->out, o->in2);
2635 return NO_EXIT;
2636 }
2637
2638 static ExitStatus op_negf32(DisasContext *s, DisasOps *o)
2639 {
2640 tcg_gen_xori_i64(o->out, o->in2, 0x80000000ull);
2641 return NO_EXIT;
2642 }
2643
2644 static ExitStatus op_negf64(DisasContext *s, DisasOps *o)
2645 {
2646 tcg_gen_xori_i64(o->out, o->in2, 0x8000000000000000ull);
2647 return NO_EXIT;
2648 }
2649
2650 static ExitStatus op_negf128(DisasContext *s, DisasOps *o)
2651 {
2652 tcg_gen_xori_i64(o->out, o->in1, 0x8000000000000000ull);
2653 tcg_gen_mov_i64(o->out2, o->in2);
2654 return NO_EXIT;
2655 }
2656
2657 static ExitStatus op_oc(DisasContext *s, DisasOps *o)
2658 {
2659 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2660 potential_page_fault(s);
2661 gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2);
2662 tcg_temp_free_i32(l);
2663 set_cc_static(s);
2664 return NO_EXIT;
2665 }
2666
2667 static ExitStatus op_or(DisasContext *s, DisasOps *o)
2668 {
2669 tcg_gen_or_i64(o->out, o->in1, o->in2);
2670 return NO_EXIT;
2671 }
2672
2673 static ExitStatus op_ori(DisasContext *s, DisasOps *o)
2674 {
2675 int shift = s->insn->data & 0xff;
2676 int size = s->insn->data >> 8;
2677 uint64_t mask = ((1ull << size) - 1) << shift;
2678
2679 assert(!o->g_in2);
2680 tcg_gen_shli_i64(o->in2, o->in2, shift);
2681 tcg_gen_or_i64(o->out, o->in1, o->in2);
2682
2683 /* Produce the CC from only the bits manipulated. */
2684 tcg_gen_andi_i64(cc_dst, o->out, mask);
2685 set_cc_nz_u64(s, cc_dst);
2686 return NO_EXIT;
2687 }
2688
2689 #ifndef CONFIG_USER_ONLY
2690 static ExitStatus op_ptlb(DisasContext *s, DisasOps *o)
2691 {
2692 check_privileged(s);
2693 gen_helper_ptlb(cpu_env);
2694 return NO_EXIT;
2695 }
2696 #endif
2697
2698 static ExitStatus op_rev16(DisasContext *s, DisasOps *o)
2699 {
2700 tcg_gen_bswap16_i64(o->out, o->in2);
2701 return NO_EXIT;
2702 }
2703
2704 static ExitStatus op_rev32(DisasContext *s, DisasOps *o)
2705 {
2706 tcg_gen_bswap32_i64(o->out, o->in2);
2707 return NO_EXIT;
2708 }
2709
2710 static ExitStatus op_rev64(DisasContext *s, DisasOps *o)
2711 {
2712 tcg_gen_bswap64_i64(o->out, o->in2);
2713 return NO_EXIT;
2714 }
2715
2716 static ExitStatus op_rll32(DisasContext *s, DisasOps *o)
2717 {
2718 TCGv_i32 t1 = tcg_temp_new_i32();
2719 TCGv_i32 t2 = tcg_temp_new_i32();
2720 TCGv_i32 to = tcg_temp_new_i32();
2721 tcg_gen_trunc_i64_i32(t1, o->in1);
2722 tcg_gen_trunc_i64_i32(t2, o->in2);
2723 tcg_gen_rotl_i32(to, t1, t2);
2724 tcg_gen_extu_i32_i64(o->out, to);
2725 tcg_temp_free_i32(t1);
2726 tcg_temp_free_i32(t2);
2727 tcg_temp_free_i32(to);
2728 return NO_EXIT;
2729 }
2730
2731 static ExitStatus op_rll64(DisasContext *s, DisasOps *o)
2732 {
2733 tcg_gen_rotl_i64(o->out, o->in1, o->in2);
2734 return NO_EXIT;
2735 }
2736
2737 static ExitStatus op_sar(DisasContext *s, DisasOps *o)
2738 {
2739 int r1 = get_field(s->fields, r1);
2740 tcg_gen_st32_i64(o->in2, cpu_env, offsetof(CPUS390XState, aregs[r1]));
2741 return NO_EXIT;
2742 }
2743
2744 static ExitStatus op_seb(DisasContext *s, DisasOps *o)
2745 {
2746 gen_helper_seb(o->out, cpu_env, o->in1, o->in2);
2747 return NO_EXIT;
2748 }
2749
2750 static ExitStatus op_sdb(DisasContext *s, DisasOps *o)
2751 {
2752 gen_helper_sdb(o->out, cpu_env, o->in1, o->in2);
2753 return NO_EXIT;
2754 }
2755
2756 static ExitStatus op_sxb(DisasContext *s, DisasOps *o)
2757 {
2758 gen_helper_sxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2759 return_low128(o->out2);
2760 return NO_EXIT;
2761 }
2762
2763 static ExitStatus op_sqeb(DisasContext *s, DisasOps *o)
2764 {
2765 gen_helper_sqeb(o->out, cpu_env, o->in2);
2766 return NO_EXIT;
2767 }
2768
2769 static ExitStatus op_sqdb(DisasContext *s, DisasOps *o)
2770 {
2771 gen_helper_sqdb(o->out, cpu_env, o->in2);
2772 return NO_EXIT;
2773 }
2774
2775 static ExitStatus op_sqxb(DisasContext *s, DisasOps *o)
2776 {
2777 gen_helper_sqxb(o->out, cpu_env, o->in1, o->in2);
2778 return_low128(o->out2);
2779 return NO_EXIT;
2780 }
2781
2782 #ifndef CONFIG_USER_ONLY
2783 static ExitStatus op_sigp(DisasContext *s, DisasOps *o)
2784 {
2785 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2786 check_privileged(s);
2787 potential_page_fault(s);
2788 gen_helper_sigp(cc_op, cpu_env, o->in2, r1, o->in1);
2789 tcg_temp_free_i32(r1);
2790 return NO_EXIT;
2791 }
2792 #endif
2793
2794 static ExitStatus op_sla(DisasContext *s, DisasOps *o)
2795 {
2796 uint64_t sign = 1ull << s->insn->data;
2797 enum cc_op cco = s->insn->data == 31 ? CC_OP_SLA_32 : CC_OP_SLA_64;
2798 gen_op_update2_cc_i64(s, cco, o->in1, o->in2);
2799 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2800 /* The arithmetic left shift is curious in that it does not affect
2801 the sign bit. Copy that over from the source unchanged. */
2802 tcg_gen_andi_i64(o->out, o->out, ~sign);
2803 tcg_gen_andi_i64(o->in1, o->in1, sign);
2804 tcg_gen_or_i64(o->out, o->out, o->in1);
2805 return NO_EXIT;
2806 }
2807
2808 static ExitStatus op_sll(DisasContext *s, DisasOps *o)
2809 {
2810 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2811 return NO_EXIT;
2812 }
2813
2814 static ExitStatus op_sra(DisasContext *s, DisasOps *o)
2815 {
2816 tcg_gen_sar_i64(o->out, o->in1, o->in2);
2817 return NO_EXIT;
2818 }
2819
2820 static ExitStatus op_srl(DisasContext *s, DisasOps *o)
2821 {
2822 tcg_gen_shr_i64(o->out, o->in1, o->in2);
2823 return NO_EXIT;
2824 }
2825
2826 static ExitStatus op_sfpc(DisasContext *s, DisasOps *o)
2827 {
2828 gen_helper_sfpc(cpu_env, o->in2);
2829 return NO_EXIT;
2830 }
2831
2832 #ifndef CONFIG_USER_ONLY
2833 static ExitStatus op_spka(DisasContext *s, DisasOps *o)
2834 {
2835 check_privileged(s);
2836 tcg_gen_shri_i64(o->in2, o->in2, 4);
2837 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY - 4, 4);
2838 return NO_EXIT;
2839 }
2840
2841 static ExitStatus op_ssm(DisasContext *s, DisasOps *o)
2842 {
2843 check_privileged(s);
2844 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8);
2845 return NO_EXIT;
2846 }
2847
2848 static ExitStatus op_stap(DisasContext *s, DisasOps *o)
2849 {
2850 check_privileged(s);
2851 /* ??? Surely cpu address != cpu number. In any case the previous
2852 version of this stored more than the required half-word, so it
2853 is unlikely this has ever been tested. */
2854 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num));
2855 return NO_EXIT;
2856 }
2857
2858 static ExitStatus op_stck(DisasContext *s, DisasOps *o)
2859 {
2860 gen_helper_stck(o->out, cpu_env);
2861 /* ??? We don't implement clock states. */
2862 gen_op_movi_cc(s, 0);
2863 return NO_EXIT;
2864 }
2865
2866 static ExitStatus op_sckc(DisasContext *s, DisasOps *o)
2867 {
2868 check_privileged(s);
2869 gen_helper_sckc(cpu_env, o->in2);
2870 return NO_EXIT;
2871 }
2872
2873 static ExitStatus op_stckc(DisasContext *s, DisasOps *o)
2874 {
2875 check_privileged(s);
2876 gen_helper_stckc(o->out, cpu_env);
2877 return NO_EXIT;
2878 }
2879
2880 static ExitStatus op_stctg(DisasContext *s, DisasOps *o)
2881 {
2882 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2883 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2884 check_privileged(s);
2885 potential_page_fault(s);
2886 gen_helper_stctg(cpu_env, r1, o->in2, r3);
2887 tcg_temp_free_i32(r1);
2888 tcg_temp_free_i32(r3);
2889 return NO_EXIT;
2890 }
2891
2892 static ExitStatus op_stctl(DisasContext *s, DisasOps *o)
2893 {
2894 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2895 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2896 check_privileged(s);
2897 potential_page_fault(s);
2898 gen_helper_stctl(cpu_env, r1, o->in2, r3);
2899 tcg_temp_free_i32(r1);
2900 tcg_temp_free_i32(r3);
2901 return NO_EXIT;
2902 }
2903
2904 static ExitStatus op_stidp(DisasContext *s, DisasOps *o)
2905 {
2906 check_privileged(s);
2907 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num));
2908 return NO_EXIT;
2909 }
2910
2911 static ExitStatus op_spt(DisasContext *s, DisasOps *o)
2912 {
2913 check_privileged(s);
2914 gen_helper_spt(cpu_env, o->in2);
2915 return NO_EXIT;
2916 }
2917
2918 static ExitStatus op_stpt(DisasContext *s, DisasOps *o)
2919 {
2920 check_privileged(s);
2921 gen_helper_stpt(o->out, cpu_env);
2922 return NO_EXIT;
2923 }
2924
2925 static ExitStatus op_spx(DisasContext *s, DisasOps *o)
2926 {
2927 check_privileged(s);
2928 gen_helper_spx(cpu_env, o->in2);
2929 return NO_EXIT;
2930 }
2931
2932 static ExitStatus op_stpx(DisasContext *s, DisasOps *o)
2933 {
2934 check_privileged(s);
2935 tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, psa));
2936 tcg_gen_andi_i64(o->out, o->out, 0x7fffe000);
2937 return NO_EXIT;
2938 }
2939
2940 static ExitStatus op_stnosm(DisasContext *s, DisasOps *o)
2941 {
2942 uint64_t i2 = get_field(s->fields, i2);
2943 TCGv_i64 t;
2944
2945 check_privileged(s);
2946
2947 /* It is important to do what the instruction name says: STORE THEN.
2948 If we let the output hook perform the store then if we fault and
2949 restart, we'll have the wrong SYSTEM MASK in place. */
2950 t = tcg_temp_new_i64();
2951 tcg_gen_shri_i64(t, psw_mask, 56);
2952 tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
2953 tcg_temp_free_i64(t);
2954
2955 if (s->fields->op == 0xac) {
2956 tcg_gen_andi_i64(psw_mask, psw_mask,
2957 (i2 << 56) | 0x00ffffffffffffffull);
2958 } else {
2959 tcg_gen_ori_i64(psw_mask, psw_mask, i2 << 56);
2960 }
2961 return NO_EXIT;
2962 }
2963 #endif
2964
2965 static ExitStatus op_st8(DisasContext *s, DisasOps *o)
2966 {
2967 tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
2968 return NO_EXIT;
2969 }
2970
2971 static ExitStatus op_st16(DisasContext *s, DisasOps *o)
2972 {
2973 tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
2974 return NO_EXIT;
2975 }
2976
2977 static ExitStatus op_st32(DisasContext *s, DisasOps *o)
2978 {
2979 tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s));
2980 return NO_EXIT;
2981 }
2982
2983 static ExitStatus op_st64(DisasContext *s, DisasOps *o)
2984 {
2985 tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
2986 return NO_EXIT;
2987 }
2988
2989 static ExitStatus op_stam(DisasContext *s, DisasOps *o)
2990 {
2991 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2992 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2993 potential_page_fault(s);
2994 gen_helper_stam(cpu_env, r1, o->in2, r3);
2995 tcg_temp_free_i32(r1);
2996 tcg_temp_free_i32(r3);
2997 return NO_EXIT;
2998 }
2999
3000 static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
3001 {
3002 int m3 = get_field(s->fields, m3);
3003 int pos, base = s->insn->data;
3004 TCGv_i64 tmp = tcg_temp_new_i64();
3005
3006 pos = base + ctz32(m3) * 8;
3007 switch (m3) {
3008 case 0xf:
3009 /* Effectively a 32-bit store. */
3010 tcg_gen_shri_i64(tmp, o->in1, pos);
3011 tcg_gen_qemu_st32(tmp, o->in2, get_mem_index(s));
3012 break;
3013
3014 case 0xc:
3015 case 0x6:
3016 case 0x3:
3017 /* Effectively a 16-bit store. */
3018 tcg_gen_shri_i64(tmp, o->in1, pos);
3019 tcg_gen_qemu_st16(tmp, o->in2, get_mem_index(s));
3020 break;
3021
3022 case 0x8:
3023 case 0x4:
3024 case 0x2:
3025 case 0x1:
3026 /* Effectively an 8-bit store. */
3027 tcg_gen_shri_i64(tmp, o->in1, pos);
3028 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3029 break;
3030
3031 default:
3032 /* This is going to be a sequence of shifts and stores. */
3033 pos = base + 32 - 8;
3034 while (m3) {
3035 if (m3 & 0x8) {
3036 tcg_gen_shri_i64(tmp, o->in1, pos);
3037 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3038 tcg_gen_addi_i64(o->in2, o->in2, 1);
3039 }
3040 m3 = (m3 << 1) & 0xf;
3041 pos -= 8;
3042 }
3043 break;
3044 }
3045 tcg_temp_free_i64(tmp);
3046 return NO_EXIT;
3047 }
3048
3049 static ExitStatus op_stm(DisasContext *s, DisasOps *o)
3050 {
3051 int r1 = get_field(s->fields, r1);
3052 int r3 = get_field(s->fields, r3);
3053 int size = s->insn->data;
3054 TCGv_i64 tsize = tcg_const_i64(size);
3055
3056 while (1) {
3057 if (size == 8) {
3058 tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
3059 } else {
3060 tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s));
3061 }
3062 if (r1 == r3) {
3063 break;
3064 }
3065 tcg_gen_add_i64(o->in2, o->in2, tsize);
3066 r1 = (r1 + 1) & 15;
3067 }
3068
3069 tcg_temp_free_i64(tsize);
3070 return NO_EXIT;
3071 }
3072
3073 static ExitStatus op_stmh(DisasContext *s, DisasOps *o)
3074 {
3075 int r1 = get_field(s->fields, r1);
3076 int r3 = get_field(s->fields, r3);
3077 TCGv_i64 t = tcg_temp_new_i64();
3078 TCGv_i64 t4 = tcg_const_i64(4);
3079 TCGv_i64 t32 = tcg_const_i64(32);
3080
3081 while (1) {
3082 tcg_gen_shl_i64(t, regs[r1], t32);
3083 tcg_gen_qemu_st32(t, o->in2, get_mem_index(s));
3084 if (r1 == r3) {
3085 break;
3086 }
3087 tcg_gen_add_i64(o->in2, o->in2, t4);
3088 r1 = (r1 + 1) & 15;
3089 }
3090
3091 tcg_temp_free_i64(t);
3092 tcg_temp_free_i64(t4);
3093 tcg_temp_free_i64(t32);
3094 return NO_EXIT;
3095 }
3096
3097 static ExitStatus op_srst(DisasContext *s, DisasOps *o)
3098 {
3099 potential_page_fault(s);
3100 gen_helper_srst(o->in1, cpu_env, regs[0], o->in1, o->in2);
3101 set_cc_static(s);
3102 return_low128(o->in2);
3103 return NO_EXIT;
3104 }
3105
3106 static ExitStatus op_sub(DisasContext *s, DisasOps *o)
3107 {
3108 tcg_gen_sub_i64(o->out, o->in1, o->in2);
3109 return NO_EXIT;
3110 }
3111
3112 static ExitStatus op_subb(DisasContext *s, DisasOps *o)
3113 {
3114 TCGv_i64 cc;
3115
3116 assert(!o->g_in2);
3117 tcg_gen_not_i64(o->in2, o->in2);
3118 tcg_gen_add_i64(o->out, o->in1, o->in2);
3119
3120 /* XXX possible optimization point */
3121 gen_op_calc_cc(s);
3122 cc = tcg_temp_new_i64();
3123 tcg_gen_extu_i32_i64(cc, cc_op);
3124 tcg_gen_shri_i64(cc, cc, 1);
3125 tcg_gen_add_i64(o->out, o->out, cc);
3126 tcg_temp_free_i64(cc);
3127 return NO_EXIT;
3128 }
3129
3130 static ExitStatus op_svc(DisasContext *s, DisasOps *o)
3131 {
3132 TCGv_i32 t;
3133
3134 update_psw_addr(s);
3135 gen_op_calc_cc(s);
3136
3137 t = tcg_const_i32(get_field(s->fields, i1) & 0xff);
3138 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code));
3139 tcg_temp_free_i32(t);
3140
3141 t = tcg_const_i32(s->next_pc - s->pc);
3142 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen));
3143 tcg_temp_free_i32(t);
3144
3145 gen_exception(EXCP_SVC);
3146 return EXIT_NORETURN;
3147 }
3148
3149 static ExitStatus op_tceb(DisasContext *s, DisasOps *o)
3150 {
3151 gen_helper_tceb(cc_op, o->in1, o->in2);
3152 set_cc_static(s);
3153 return NO_EXIT;
3154 }
3155
3156 static ExitStatus op_tcdb(DisasContext *s, DisasOps *o)
3157 {
3158 gen_helper_tcdb(cc_op, o->in1, o->in2);
3159 set_cc_static(s);
3160 return NO_EXIT;
3161 }
3162
3163 static ExitStatus op_tcxb(DisasContext *s, DisasOps *o)
3164 {
3165 gen_helper_tcxb(cc_op, o->out, o->out2, o->in2);
3166 set_cc_static(s);
3167 return NO_EXIT;
3168 }
3169
3170 #ifndef CONFIG_USER_ONLY
3171 static ExitStatus op_tprot(DisasContext *s, DisasOps *o)
3172 {
3173 potential_page_fault(s);
3174 gen_helper_tprot(cc_op, o->addr1, o->in2);
3175 set_cc_static(s);
3176 return NO_EXIT;
3177 }
3178 #endif
3179
3180 static ExitStatus op_tr(DisasContext *s, DisasOps *o)
3181 {
3182 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3183 potential_page_fault(s);
3184 gen_helper_tr(cpu_env, l, o->addr1, o->in2);
3185 tcg_temp_free_i32(l);
3186 set_cc_static(s);
3187 return NO_EXIT;
3188 }
3189
3190 static ExitStatus op_unpk(DisasContext *s, DisasOps *o)
3191 {
3192 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3193 potential_page_fault(s);
3194 gen_helper_unpk(cpu_env, l, o->addr1, o->in2);
3195 tcg_temp_free_i32(l);
3196 return NO_EXIT;
3197 }
3198
3199 static ExitStatus op_xc(DisasContext *s, DisasOps *o)
3200 {
3201 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3202 potential_page_fault(s);
3203 gen_helper_xc(cc_op, cpu_env, l, o->addr1, o->in2);
3204 tcg_temp_free_i32(l);
3205 set_cc_static(s);
3206 return NO_EXIT;
3207 }
3208
3209 static ExitStatus op_xor(DisasContext *s, DisasOps *o)
3210 {
3211 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3212 return NO_EXIT;
3213 }
3214
3215 static ExitStatus op_xori(DisasContext *s, DisasOps *o)
3216 {
3217 int shift = s->insn->data & 0xff;
3218 int size = s->insn->data >> 8;
3219 uint64_t mask = ((1ull << size) - 1) << shift;
3220
3221 assert(!o->g_in2);
3222 tcg_gen_shli_i64(o->in2, o->in2, shift);
3223 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3224
3225 /* Produce the CC from only the bits manipulated. */
3226 tcg_gen_andi_i64(cc_dst, o->out, mask);
3227 set_cc_nz_u64(s, cc_dst);
3228 return NO_EXIT;
3229 }
3230
3231 static ExitStatus op_zero(DisasContext *s, DisasOps *o)
3232 {
3233 o->out = tcg_const_i64(0);
3234 return NO_EXIT;
3235 }
3236
3237 static ExitStatus op_zero2(DisasContext *s, DisasOps *o)
3238 {
3239 o->out = tcg_const_i64(0);
3240 o->out2 = o->out;
3241 o->g_out2 = true;
3242 return NO_EXIT;
3243 }
3244
3245 /* ====================================================================== */
3246 /* The "Cc OUTput" generators. Given the generated output (and in some cases
3247 the original inputs), update the various cc data structures in order to
3248 be able to compute the new condition code. */
3249
3250 static void cout_abs32(DisasContext *s, DisasOps *o)
3251 {
3252 gen_op_update1_cc_i64(s, CC_OP_ABS_32, o->out);
3253 }
3254
3255 static void cout_abs64(DisasContext *s, DisasOps *o)
3256 {
3257 gen_op_update1_cc_i64(s, CC_OP_ABS_64, o->out);
3258 }
3259
3260 static void cout_adds32(DisasContext *s, DisasOps *o)
3261 {
3262 gen_op_update3_cc_i64(s, CC_OP_ADD_32, o->in1, o->in2, o->out);
3263 }
3264
3265 static void cout_adds64(DisasContext *s, DisasOps *o)
3266 {
3267 gen_op_update3_cc_i64(s, CC_OP_ADD_64, o->in1, o->in2, o->out);
3268 }
3269
3270 static void cout_addu32(DisasContext *s, DisasOps *o)
3271 {
3272 gen_op_update3_cc_i64(s, CC_OP_ADDU_32, o->in1, o->in2, o->out);
3273 }
3274
3275 static void cout_addu64(DisasContext *s, DisasOps *o)
3276 {
3277 gen_op_update3_cc_i64(s, CC_OP_ADDU_64, o->in1, o->in2, o->out);
3278 }
3279
3280 static void cout_addc32(DisasContext *s, DisasOps *o)
3281 {
3282 gen_op_update3_cc_i64(s, CC_OP_ADDC_32, o->in1, o->in2, o->out);
3283 }
3284
3285 static void cout_addc64(DisasContext *s, DisasOps *o)
3286 {
3287 gen_op_update3_cc_i64(s, CC_OP_ADDC_64, o->in1, o->in2, o->out);
3288 }
3289
3290 static void cout_cmps32(DisasContext *s, DisasOps *o)
3291 {
3292 gen_op_update2_cc_i64(s, CC_OP_LTGT_32, o->in1, o->in2);
3293 }
3294
3295 static void cout_cmps64(DisasContext *s, DisasOps *o)
3296 {
3297 gen_op_update2_cc_i64(s, CC_OP_LTGT_64, o->in1, o->in2);
3298 }
3299
3300 static void cout_cmpu32(DisasContext *s, DisasOps *o)
3301 {
3302 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_32, o->in1, o->in2);
3303 }
3304
3305 static void cout_cmpu64(DisasContext *s, DisasOps *o)
3306 {
3307 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, o->in1, o->in2);
3308 }
3309
3310 static void cout_f32(DisasContext *s, DisasOps *o)
3311 {
3312 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, o->out);
3313 }
3314
3315 static void cout_f64(DisasContext *s, DisasOps *o)
3316 {
3317 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, o->out);
3318 }
3319
3320 static void cout_f128(DisasContext *s, DisasOps *o)
3321 {
3322 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, o->out, o->out2);
3323 }
3324
3325 static void cout_nabs32(DisasContext *s, DisasOps *o)
3326 {
3327 gen_op_update1_cc_i64(s, CC_OP_NABS_32, o->out);
3328 }
3329
3330 static void cout_nabs64(DisasContext *s, DisasOps *o)
3331 {
3332 gen_op_update1_cc_i64(s, CC_OP_NABS_64, o->out);
3333 }
3334
3335 static void cout_neg32(DisasContext *s, DisasOps *o)
3336 {
3337 gen_op_update1_cc_i64(s, CC_OP_COMP_32, o->out);
3338 }
3339
3340 static void cout_neg64(DisasContext *s, DisasOps *o)
3341 {
3342 gen_op_update1_cc_i64(s, CC_OP_COMP_64, o->out);
3343 }
3344
3345 static void cout_nz32(DisasContext *s, DisasOps *o)
3346 {
3347 tcg_gen_ext32u_i64(cc_dst, o->out);
3348 gen_op_update1_cc_i64(s, CC_OP_NZ, cc_dst);
3349 }
3350
3351 static void cout_nz64(DisasContext *s, DisasOps *o)
3352 {
3353 gen_op_update1_cc_i64(s, CC_OP_NZ, o->out);
3354 }
3355
3356 static void cout_s32(DisasContext *s, DisasOps *o)
3357 {
3358 gen_op_update1_cc_i64(s, CC_OP_LTGT0_32, o->out);
3359 }
3360
3361 static void cout_s64(DisasContext *s, DisasOps *o)
3362 {
3363 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, o->out);
3364 }
3365
3366 static void cout_subs32(DisasContext *s, DisasOps *o)
3367 {
3368 gen_op_update3_cc_i64(s, CC_OP_SUB_32, o->in1, o->in2, o->out);
3369 }
3370
3371 static void cout_subs64(DisasContext *s, DisasOps *o)
3372 {
3373 gen_op_update3_cc_i64(s, CC_OP_SUB_64, o->in1, o->in2, o->out);
3374 }
3375
3376 static void cout_subu32(DisasContext *s, DisasOps *o)
3377 {
3378 gen_op_update3_cc_i64(s, CC_OP_SUBU_32, o->in1, o->in2, o->out);
3379 }
3380
3381 static void cout_subu64(DisasContext *s, DisasOps *o)
3382 {
3383 gen_op_update3_cc_i64(s, CC_OP_SUBU_64, o->in1, o->in2, o->out);
3384 }
3385
3386 static void cout_subb32(DisasContext *s, DisasOps *o)
3387 {
3388 gen_op_update3_cc_i64(s, CC_OP_SUBB_32, o->in1, o->in2, o->out);
3389 }
3390
3391 static void cout_subb64(DisasContext *s, DisasOps *o)
3392 {
3393 gen_op_update3_cc_i64(s, CC_OP_SUBB_64, o->in1, o->in2, o->out);
3394 }
3395
3396 static void cout_tm32(DisasContext *s, DisasOps *o)
3397 {
3398 gen_op_update2_cc_i64(s, CC_OP_TM_32, o->in1, o->in2);
3399 }
3400
3401 static void cout_tm64(DisasContext *s, DisasOps *o)
3402 {
3403 gen_op_update2_cc_i64(s, CC_OP_TM_64, o->in1, o->in2);
3404 }
3405
3406 /* ====================================================================== */
3407 /* The "PREPeration" generators. These initialize the DisasOps.OUT fields
3408 with the TCG register to which we will write. Used in combination with
3409 the "wout" generators, in some cases we need a new temporary, and in
3410 some cases we can write to a TCG global. */
3411
3412 static void prep_new(DisasContext *s, DisasFields *f, DisasOps *o)
3413 {
3414 o->out = tcg_temp_new_i64();
3415 }
3416
3417 static void prep_new_P(DisasContext *s, DisasFields *f, DisasOps *o)
3418 {
3419 o->out = tcg_temp_new_i64();
3420 o->out2 = tcg_temp_new_i64();
3421 }
3422
3423 static void prep_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3424 {
3425 o->out = regs[get_field(f, r1)];
3426 o->g_out = true;
3427 }
3428
3429 static void prep_r1_P(DisasContext *s, DisasFields *f, DisasOps *o)
3430 {
3431 /* ??? Specification exception: r1 must be even. */
3432 int r1 = get_field(f, r1);
3433 o->out = regs[r1];
3434 o->out2 = regs[(r1 + 1) & 15];
3435 o->g_out = o->g_out2 = true;
3436 }
3437
3438 static void prep_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3439 {
3440 o->out = fregs[get_field(f, r1)];
3441 o->g_out = true;
3442 }
3443
3444 static void prep_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3445 {
3446 /* ??? Specification exception: r1 must be < 14. */
3447 int r1 = get_field(f, r1);
3448 o->out = fregs[r1];
3449 o->out2 = fregs[(r1 + 2) & 15];
3450 o->g_out = o->g_out2 = true;
3451 }
3452
3453 /* ====================================================================== */
3454 /* The "Write OUTput" generators. These generally perform some non-trivial
3455 copy of data to TCG globals, or to main memory. The trivial cases are
3456 generally handled by having a "prep" generator install the TCG global
3457 as the destination of the operation. */
3458
3459 static void wout_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3460 {
3461 store_reg(get_field(f, r1), o->out);
3462 }
3463
3464 static void wout_r1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3465 {
3466 int r1 = get_field(f, r1);
3467 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8);
3468 }
3469
3470 static void wout_r1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3471 {
3472 int r1 = get_field(f, r1);
3473 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 16);
3474 }
3475
3476 static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3477 {
3478 store_reg32_i64(get_field(f, r1), o->out);
3479 }
3480
3481 static void wout_r1_P32(DisasContext *s, DisasFields *f, DisasOps *o)
3482 {
3483 /* ??? Specification exception: r1 must be even. */
3484 int r1 = get_field(f, r1);
3485 store_reg32_i64(r1, o->out);
3486 store_reg32_i64((r1 + 1) & 15, o->out2);
3487 }
3488
3489 static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3490 {
3491 /* ??? Specification exception: r1 must be even. */
3492 int r1 = get_field(f, r1);
3493 store_reg32_i64((r1 + 1) & 15, o->out);
3494 tcg_gen_shri_i64(o->out, o->out, 32);
3495 store_reg32_i64(r1, o->out);
3496 }
3497
3498 static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3499 {
3500 store_freg32_i64(get_field(f, r1), o->out);
3501 }
3502
3503 static void wout_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3504 {
3505 store_freg(get_field(f, r1), o->out);
3506 }
3507
3508 static void wout_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3509 {
3510 /* ??? Specification exception: r1 must be < 14. */
3511 int f1 = get_field(s->fields, r1);
3512 store_freg(f1, o->out);
3513 store_freg((f1 + 2) & 15, o->out2);
3514 }
3515
3516 static void wout_cond_r1r2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3517 {
3518 if (get_field(f, r1) != get_field(f, r2)) {
3519 store_reg32_i64(get_field(f, r1), o->out);
3520 }
3521 }
3522
3523 static void wout_cond_e1e2(DisasContext *s, DisasFields *f, DisasOps *o)
3524 {
3525 if (get_field(f, r1) != get_field(f, r2)) {
3526 store_freg32_i64(get_field(f, r1), o->out);
3527 }
3528 }
3529
3530 static void wout_m1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3531 {
3532 tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s));
3533 }
3534
3535 static void wout_m1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3536 {
3537 tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s));
3538 }
3539
3540 static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3541 {
3542 tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
3543 }
3544
3545 static void wout_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3546 {
3547 tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
3548 }
3549
3550 static void wout_m2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3551 {
3552 tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s));
3553 }
3554
3555 /* ====================================================================== */
3556 /* The "INput 1" generators. These load the first operand to an insn. */
3557
3558 static void in1_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3559 {
3560 o->in1 = load_reg(get_field(f, r1));
3561 }
3562
3563 static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3564 {
3565 o->in1 = regs[get_field(f, r1)];
3566 o->g_in1 = true;
3567 }
3568
3569 static void in1_r1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3570 {
3571 o->in1 = tcg_temp_new_i64();
3572 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r1)]);
3573 }
3574
3575 static void in1_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3576 {
3577 o->in1 = tcg_temp_new_i64();
3578 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r1)]);
3579 }
3580
3581 static void in1_r1_sr32(DisasContext *s, DisasFields *f, DisasOps *o)
3582 {
3583 o->in1 = tcg_temp_new_i64();
3584 tcg_gen_shri_i64(o->in1, regs[get_field(f, r1)], 32);
3585 }
3586
3587 static void in1_r1p1(DisasContext *s, DisasFields *f, DisasOps *o)
3588 {
3589 /* ??? Specification exception: r1 must be even. */
3590 int r1 = get_field(f, r1);
3591 o->in1 = load_reg((r1 + 1) & 15);
3592 }
3593
3594 static void in1_r1p1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3595 {
3596 /* ??? Specification exception: r1 must be even. */
3597 int r1 = get_field(f, r1);
3598 o->in1 = tcg_temp_new_i64();
3599 tcg_gen_ext32s_i64(o->in1, regs[(r1 + 1) & 15]);
3600 }
3601
3602 static void in1_r1p1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3603 {
3604 /* ??? Specification exception: r1 must be even. */
3605 int r1 = get_field(f, r1);
3606 o->in1 = tcg_temp_new_i64();
3607 tcg_gen_ext32u_i64(o->in1, regs[(r1 + 1) & 15]);
3608 }
3609
3610 static void in1_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3611 {
3612 /* ??? Specification exception: r1 must be even. */
3613 int r1 = get_field(f, r1);
3614 o->in1 = tcg_temp_new_i64();
3615 tcg_gen_concat32_i64(o->in1, regs[r1 + 1], regs[r1]);
3616 }
3617
3618 static void in1_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3619 {
3620 o->in1 = load_reg(get_field(f, r2));
3621 }
3622
3623 static void in1_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3624 {
3625 o->in1 = load_reg(get_field(f, r3));
3626 }
3627
3628 static void in1_r3_o(DisasContext *s, DisasFields *f, DisasOps *o)
3629 {
3630 o->in1 = regs[get_field(f, r3)];
3631 o->g_in1 = true;
3632 }
3633
3634 static void in1_r3_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3635 {
3636 o->in1 = tcg_temp_new_i64();
3637 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r3)]);
3638 }
3639
3640 static void in1_r3_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3641 {
3642 o->in1 = tcg_temp_new_i64();
3643 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r3)]);
3644 }
3645
3646 static void in1_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3647 {
3648 o->in1 = load_freg32_i64(get_field(f, r1));
3649 }
3650
3651 static void in1_f1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3652 {
3653 o->in1 = fregs[get_field(f, r1)];
3654 o->g_in1 = true;
3655 }
3656
3657 static void in1_x1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3658 {
3659 /* ??? Specification exception: r1 must be < 14. */
3660 int r1 = get_field(f, r1);
3661 o->out = fregs[r1];
3662 o->out2 = fregs[(r1 + 2) & 15];
3663 o->g_out = o->g_out2 = true;
3664 }
3665
3666 static void in1_la1(DisasContext *s, DisasFields *f, DisasOps *o)
3667 {
3668 o->addr1 = get_address(s, 0, get_field(f, b1), get_field(f, d1));
3669 }
3670
3671 static void in1_la2(DisasContext *s, DisasFields *f, DisasOps *o)
3672 {
3673 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3674 o->addr1 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3675 }
3676
3677 static void in1_m1_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3678 {
3679 in1_la1(s, f, o);
3680 o->in1 = tcg_temp_new_i64();
3681 tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s));
3682 }
3683
3684 static void in1_m1_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3685 {
3686 in1_la1(s, f, o);
3687 o->in1 = tcg_temp_new_i64();
3688 tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s));
3689 }
3690
3691 static void in1_m1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3692 {
3693 in1_la1(s, f, o);
3694 o->in1 = tcg_temp_new_i64();
3695 tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s));
3696 }
3697
3698 static void in1_m1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3699 {
3700 in1_la1(s, f, o);
3701 o->in1 = tcg_temp_new_i64();
3702 tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s));
3703 }
3704
3705 static void in1_m1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3706 {
3707 in1_la1(s, f, o);
3708 o->in1 = tcg_temp_new_i64();
3709 tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s));
3710 }
3711
3712 static void in1_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3713 {
3714 in1_la1(s, f, o);
3715 o->in1 = tcg_temp_new_i64();
3716 tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s));
3717 }
3718
3719 /* ====================================================================== */
3720 /* The "INput 2" generators. These load the second operand to an insn. */
3721
3722 static void in2_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3723 {
3724 o->in2 = regs[get_field(f, r1)];
3725 o->g_in2 = true;
3726 }
3727
3728 static void in2_r1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3729 {
3730 o->in2 = tcg_temp_new_i64();
3731 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r1)]);
3732 }
3733
3734 static void in2_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3735 {
3736 o->in2 = tcg_temp_new_i64();
3737 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r1)]);
3738 }
3739
3740 static void in2_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3741 {
3742 o->in2 = load_reg(get_field(f, r2));
3743 }
3744
3745 static void in2_r2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3746 {
3747 o->in2 = regs[get_field(f, r2)];
3748 o->g_in2 = true;
3749 }
3750
3751 static void in2_r2_nz(DisasContext *s, DisasFields *f, DisasOps *o)
3752 {
3753 int r2 = get_field(f, r2);
3754 if (r2 != 0) {
3755 o->in2 = load_reg(r2);
3756 }
3757 }
3758
3759 static void in2_r2_8s(DisasContext *s, DisasFields *f, DisasOps *o)
3760 {
3761 o->in2 = tcg_temp_new_i64();
3762 tcg_gen_ext8s_i64(o->in2, regs[get_field(f, r2)]);
3763 }
3764
3765 static void in2_r2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3766 {
3767 o->in2 = tcg_temp_new_i64();
3768 tcg_gen_ext8u_i64(o->in2, regs[get_field(f, r2)]);
3769 }
3770
3771 static void in2_r2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3772 {
3773 o->in2 = tcg_temp_new_i64();
3774 tcg_gen_ext16s_i64(o->in2, regs[get_field(f, r2)]);
3775 }
3776
3777 static void in2_r2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3778 {
3779 o->in2 = tcg_temp_new_i64();
3780 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r2)]);
3781 }
3782
3783 static void in2_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3784 {
3785 o->in2 = load_reg(get_field(f, r3));
3786 }
3787
3788 static void in2_r2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3789 {
3790 o->in2 = tcg_temp_new_i64();
3791 tcg_gen_ext32s_i64(o->in2, regs[get_field(f, r2)]);
3792 }
3793
3794 static void in2_r2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3795 {
3796 o->in2 = tcg_temp_new_i64();
3797 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r2)]);
3798 }
3799
3800 static void in2_e2(DisasContext *s, DisasFields *f, DisasOps *o)
3801 {
3802 o->in2 = load_freg32_i64(get_field(f, r2));
3803 }
3804
3805 static void in2_f2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3806 {
3807 o->in2 = fregs[get_field(f, r2)];
3808 o->g_in2 = true;
3809 }
3810
3811 static void in2_x2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3812 {
3813 /* ??? Specification exception: r1 must be < 14. */
3814 int r2 = get_field(f, r2);
3815 o->in1 = fregs[r2];
3816 o->in2 = fregs[(r2 + 2) & 15];
3817 o->g_in1 = o->g_in2 = true;
3818 }
3819
3820 static void in2_ra2(DisasContext *s, DisasFields *f, DisasOps *o)
3821 {
3822 o->in2 = get_address(s, 0, get_field(f, r2), 0);
3823 }
3824
3825 static void in2_a2(DisasContext *s, DisasFields *f, DisasOps *o)
3826 {
3827 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3828 o->in2 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3829 }
3830
3831 static void in2_ri2(DisasContext *s, DisasFields *f, DisasOps *o)
3832 {
3833 o->in2 = tcg_const_i64(s->pc + (int64_t)get_field(f, i2) * 2);
3834 }
3835
3836 static void in2_sh32(DisasContext *s, DisasFields *f, DisasOps *o)
3837 {
3838 help_l2_shift(s, f, o, 31);
3839 }
3840
3841 static void in2_sh64(DisasContext *s, DisasFields *f, DisasOps *o)
3842 {
3843 help_l2_shift(s, f, o, 63);
3844 }
3845
3846 static void in2_m2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3847 {
3848 in2_a2(s, f, o);
3849 tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s));
3850 }
3851
3852 static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3853 {
3854 in2_a2(s, f, o);
3855 tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
3856 }
3857
3858 static void in2_m2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3859 {
3860 in2_a2(s, f, o);
3861 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3862 }
3863
3864 static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3865 {
3866 in2_a2(s, f, o);
3867 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3868 }
3869
3870 static void in2_m2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3871 {
3872 in2_a2(s, f, o);
3873 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3874 }
3875
3876 static void in2_m2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3877 {
3878 in2_a2(s, f, o);
3879 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3880 }
3881
3882 static void in2_mri2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3883 {
3884 in2_ri2(s, f, o);
3885 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3886 }
3887
3888 static void in2_mri2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3889 {
3890 in2_ri2(s, f, o);
3891 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3892 }
3893
3894 static void in2_mri2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3895 {
3896 in2_ri2(s, f, o);
3897 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3898 }
3899
3900 static void in2_mri2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3901 {
3902 in2_ri2(s, f, o);
3903 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3904 }
3905
3906 static void in2_i2(DisasContext *s, DisasFields *f, DisasOps *o)
3907 {
3908 o->in2 = tcg_const_i64(get_field(f, i2));
3909 }
3910
3911 static void in2_i2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3912 {
3913 o->in2 = tcg_const_i64((uint8_t)get_field(f, i2));
3914 }
3915
3916 static void in2_i2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3917 {
3918 o->in2 = tcg_const_i64((uint16_t)get_field(f, i2));
3919 }
3920
3921 static void in2_i2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3922 {
3923 o->in2 = tcg_const_i64((uint32_t)get_field(f, i2));
3924 }
3925
3926 static void in2_i2_16u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
3927 {
3928 uint64_t i2 = (uint16_t)get_field(f, i2);
3929 o->in2 = tcg_const_i64(i2 << s->insn->data);
3930 }
3931
3932 static void in2_i2_32u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
3933 {
3934 uint64_t i2 = (uint32_t)get_field(f, i2);
3935 o->in2 = tcg_const_i64(i2 << s->insn->data);
3936 }
3937
3938 /* ====================================================================== */
3939
3940 /* Find opc within the table of insns. This is formulated as a switch
3941 statement so that (1) we get compile-time notice of cut-paste errors
3942 for duplicated opcodes, and (2) the compiler generates the binary
3943 search tree, rather than us having to post-process the table. */
3944
3945 #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
3946 D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0)
3947
3948 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) insn_ ## NM,
3949
3950 enum DisasInsnEnum {
3951 #include "insn-data.def"
3952 };
3953
3954 #undef D
3955 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) { \
3956 .opc = OPC, \
3957 .fmt = FMT_##FT, \
3958 .fac = FAC_##FC, \
3959 .name = #NM, \
3960 .help_in1 = in1_##I1, \
3961 .help_in2 = in2_##I2, \
3962 .help_prep = prep_##P, \
3963 .help_wout = wout_##W, \
3964 .help_cout = cout_##CC, \
3965 .help_op = op_##OP, \
3966 .data = D \
3967 },
3968
3969 /* Allow 0 to be used for NULL in the table below. */
3970 #define in1_0 NULL
3971 #define in2_0 NULL
3972 #define prep_0 NULL
3973 #define wout_0 NULL
3974 #define cout_0 NULL
3975 #define op_0 NULL
3976
3977 static const DisasInsn insn_info[] = {
3978 #include "insn-data.def"
3979 };
3980
3981 #undef D
3982 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
3983 case OPC: return &insn_info[insn_ ## NM];
3984
3985 static const DisasInsn *lookup_opc(uint16_t opc)
3986 {
3987 switch (opc) {
3988 #include "insn-data.def"
3989 default:
3990 return NULL;
3991 }
3992 }
3993
3994 #undef D
3995 #undef C
3996
3997 /* Extract a field from the insn. The INSN should be left-aligned in
3998 the uint64_t so that we can more easily utilize the big-bit-endian
3999 definitions we extract from the Principals of Operation. */
4000
4001 static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn)
4002 {
4003 uint32_t r, m;
4004
4005 if (f->size == 0) {
4006 return;
4007 }
4008
4009 /* Zero extract the field from the insn. */
4010 r = (insn << f->beg) >> (64 - f->size);
4011
4012 /* Sign-extend, or un-swap the field as necessary. */
4013 switch (f->type) {
4014 case 0: /* unsigned */
4015 break;
4016 case 1: /* signed */
4017 assert(f->size <= 32);
4018 m = 1u << (f->size - 1);
4019 r = (r ^ m) - m;
4020 break;
4021 case 2: /* dl+dh split, signed 20 bit. */
4022 r = ((int8_t)r << 12) | (r >> 8);
4023 break;
4024 default:
4025 abort();
4026 }
4027
4028 /* Validate that the "compressed" encoding we selected above is valid.
4029 I.e. we havn't make two different original fields overlap. */
4030 assert(((o->presentC >> f->indexC) & 1) == 0);
4031 o->presentC |= 1 << f->indexC;
4032 o->presentO |= 1 << f->indexO;
4033
4034 o->c[f->indexC] = r;
4035 }
4036
4037 /* Lookup the insn at the current PC, extracting the operands into O and
4038 returning the info struct for the insn. Returns NULL for invalid insn. */
4039
4040 static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
4041 DisasFields *f)
4042 {
4043 uint64_t insn, pc = s->pc;
4044 int op, op2, ilen;
4045 const DisasInsn *info;
4046
4047 insn = ld_code2(env, pc);
4048 op = (insn >> 8) & 0xff;
4049 ilen = get_ilen(op);
4050 s->next_pc = s->pc + ilen;
4051
4052 switch (ilen) {
4053 case 2:
4054 insn = insn << 48;
4055 break;
4056 case 4:
4057 insn = ld_code4(env, pc) << 32;
4058 break;
4059 case 6:
4060 insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
4061 break;
4062 default:
4063 abort();
4064 }
4065
4066 /* We can't actually determine the insn format until we've looked up
4067 the full insn opcode. Which we can't do without locating the
4068 secondary opcode. Assume by default that OP2 is at bit 40; for
4069 those smaller insns that don't actually have a secondary opcode
4070 this will correctly result in OP2 = 0. */
4071 switch (op) {
4072 case 0x01: /* E */
4073 case 0x80: /* S */
4074 case 0x82: /* S */
4075 case 0x93: /* S */
4076 case 0xb2: /* S, RRF, RRE */
4077 case 0xb3: /* RRE, RRD, RRF */
4078 case 0xb9: /* RRE, RRF */
4079 case 0xe5: /* SSE, SIL */
4080 op2 = (insn << 8) >> 56;
4081 break;
4082 case 0xa5: /* RI */
4083 case 0xa7: /* RI */
4084 case 0xc0: /* RIL */
4085 case 0xc2: /* RIL */
4086 case 0xc4: /* RIL */
4087 case 0xc6: /* RIL */
4088 case 0xc8: /* SSF */
4089 case 0xcc: /* RIL */
4090 op2 = (insn << 12) >> 60;
4091 break;
4092 case 0xd0 ... 0xdf: /* SS */
4093 case 0xe1: /* SS */
4094 case 0xe2: /* SS */
4095 case 0xe8: /* SS */
4096 case 0xe9: /* SS */
4097 case 0xea: /* SS */
4098 case 0xee ... 0xf3: /* SS */
4099 case 0xf8 ... 0xfd: /* SS */
4100 op2 = 0;
4101 break;
4102 default:
4103 op2 = (insn << 40) >> 56;
4104 break;
4105 }
4106
4107 memset(f, 0, sizeof(*f));
4108 f->op = op;
4109 f->op2 = op2;
4110
4111 /* Lookup the instruction. */
4112 info = lookup_opc(op << 8 | op2);
4113
4114 /* If we found it, extract the operands. */
4115 if (info != NULL) {
4116 DisasFormat fmt = info->fmt;
4117 int i;
4118
4119 for (i = 0; i < NUM_C_FIELD; ++i) {
4120 extract_field(f, &format_info[fmt].op[i], insn);
4121 }
4122 }
4123 return info;
4124 }
4125
4126 static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
4127 {
4128 const DisasInsn *insn;
4129 ExitStatus ret = NO_EXIT;
4130 DisasFields f;
4131 DisasOps o;
4132
4133 insn = extract_insn(env, s, &f);
4134
4135 /* If not found, try the old interpreter. This includes ILLOPC. */
4136 if (insn == NULL) {
4137 disas_s390_insn(env, s);
4138 switch (s->is_jmp) {
4139 case DISAS_NEXT:
4140 ret = NO_EXIT;
4141 break;
4142 case DISAS_TB_JUMP:
4143 ret = EXIT_GOTO_TB;
4144 break;
4145 case DISAS_JUMP:
4146 ret = EXIT_PC_UPDATED;
4147 break;
4148 case DISAS_EXCP:
4149 ret = EXIT_NORETURN;
4150 break;
4151 default:
4152 abort();
4153 }
4154
4155 s->pc = s->next_pc;
4156 return ret;
4157 }
4158
4159 /* Set up the strutures we use to communicate with the helpers. */
4160 s->insn = insn;
4161 s->fields = &f;
4162 o.g_out = o.g_out2 = o.g_in1 = o.g_in2 = false;
4163 TCGV_UNUSED_I64(o.out);
4164 TCGV_UNUSED_I64(o.out2);
4165 TCGV_UNUSED_I64(o.in1);
4166 TCGV_UNUSED_I64(o.in2);
4167 TCGV_UNUSED_I64(o.addr1);
4168
4169 /* Implement the instruction. */
4170 if (insn->help_in1) {
4171 insn->help_in1(s, &f, &o);
4172 }
4173 if (insn->help_in2) {
4174 insn->help_in2(s, &f, &o);
4175 }
4176 if (insn->help_prep) {
4177 insn->help_prep(s, &f, &o);
4178 }
4179 if (insn->help_op) {
4180 ret = insn->help_op(s, &o);
4181 }
4182 if (insn->help_wout) {
4183 insn->help_wout(s, &f, &o);
4184 }
4185 if (insn->help_cout) {
4186 insn->help_cout(s, &o);
4187 }
4188
4189 /* Free any temporaries created by the helpers. */
4190 if (!TCGV_IS_UNUSED_I64(o.out) && !o.g_out) {
4191 tcg_temp_free_i64(o.out);
4192 }
4193 if (!TCGV_IS_UNUSED_I64(o.out2) && !o.g_out2) {
4194 tcg_temp_free_i64(o.out2);
4195 }
4196 if (!TCGV_IS_UNUSED_I64(o.in1) && !o.g_in1) {
4197 tcg_temp_free_i64(o.in1);
4198 }
4199 if (!TCGV_IS_UNUSED_I64(o.in2) && !o.g_in2) {
4200 tcg_temp_free_i64(o.in2);
4201 }
4202 if (!TCGV_IS_UNUSED_I64(o.addr1)) {
4203 tcg_temp_free_i64(o.addr1);
4204 }
4205
4206 /* Advance to the next instruction. */
4207 s->pc = s->next_pc;
4208 return ret;
4209 }
4210
4211 static inline void gen_intermediate_code_internal(CPUS390XState *env,
4212 TranslationBlock *tb,
4213 int search_pc)
4214 {
4215 DisasContext dc;
4216 target_ulong pc_start;
4217 uint64_t next_page_start;
4218 uint16_t *gen_opc_end;
4219 int j, lj = -1;
4220 int num_insns, max_insns;
4221 CPUBreakpoint *bp;
4222 ExitStatus status;
4223 bool do_debug;
4224
4225 pc_start = tb->pc;
4226
4227 /* 31-bit mode */
4228 if (!(tb->flags & FLAG_MASK_64)) {
4229 pc_start &= 0x7fffffff;
4230 }
4231
4232 dc.tb = tb;
4233 dc.pc = pc_start;
4234 dc.cc_op = CC_OP_DYNAMIC;
4235 do_debug = dc.singlestep_enabled = env->singlestep_enabled;
4236 dc.is_jmp = DISAS_NEXT;
4237
4238 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
4239
4240 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4241
4242 num_insns = 0;
4243 max_insns = tb->cflags & CF_COUNT_MASK;
4244 if (max_insns == 0) {
4245 max_insns = CF_COUNT_MASK;
4246 }
4247
4248 gen_icount_start();
4249
4250 do {
4251 if (search_pc) {
4252 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4253 if (lj < j) {
4254 lj++;
4255 while (lj < j) {
4256 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4257 }
4258 }
4259 tcg_ctx.gen_opc_pc[lj] = dc.pc;
4260 gen_opc_cc_op[lj] = dc.cc_op;
4261 tcg_ctx.gen_opc_instr_start[lj] = 1;
4262 tcg_ctx.gen_opc_icount[lj] = num_insns;
4263 }
4264 if (++num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
4265 gen_io_start();
4266 }
4267
4268 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4269 tcg_gen_debug_insn_start(dc.pc);
4270 }
4271
4272 status = NO_EXIT;
4273 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
4274 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
4275 if (bp->pc == dc.pc) {
4276 status = EXIT_PC_STALE;
4277 do_debug = true;
4278 break;
4279 }
4280 }
4281 }
4282 if (status == NO_EXIT) {
4283 status = translate_one(env, &dc);
4284 }
4285
4286 /* If we reach a page boundary, are single stepping,
4287 or exhaust instruction count, stop generation. */
4288 if (status == NO_EXIT
4289 && (dc.pc >= next_page_start
4290 || tcg_ctx.gen_opc_ptr >= gen_opc_end
4291 || num_insns >= max_insns
4292 || singlestep
4293 || env->singlestep_enabled)) {
4294 status = EXIT_PC_STALE;
4295 }
4296 } while (status == NO_EXIT);
4297
4298 if (tb->cflags & CF_LAST_IO) {
4299 gen_io_end();
4300 }
4301
4302 switch (status) {
4303 case EXIT_GOTO_TB:
4304 case EXIT_NORETURN:
4305 break;
4306 case EXIT_PC_STALE:
4307 update_psw_addr(&dc);
4308 /* FALLTHRU */
4309 case EXIT_PC_UPDATED:
4310 if (singlestep && dc.cc_op != CC_OP_DYNAMIC) {
4311 gen_op_calc_cc(&dc);
4312 } else {
4313 /* Next TB starts off with CC_OP_DYNAMIC,
4314 so make sure the cc op type is in env */
4315 gen_op_set_cc_op(&dc);
4316 }
4317 if (do_debug) {
4318 gen_exception(EXCP_DEBUG);
4319 } else {
4320 /* Generate the return instruction */
4321 tcg_gen_exit_tb(0);
4322 }
4323 break;
4324 default:
4325 abort();
4326 }
4327
4328 gen_icount_end(tb, num_insns);
4329 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
4330 if (search_pc) {
4331 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4332 lj++;
4333 while (lj <= j) {
4334 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4335 }
4336 } else {
4337 tb->size = dc.pc - pc_start;
4338 tb->icount = num_insns;
4339 }
4340
4341 #if defined(S390X_DEBUG_DISAS)
4342 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
4343 qemu_log("IN: %s\n", lookup_symbol(pc_start));
4344 log_target_disas(env, pc_start, dc.pc - pc_start, 1);
4345 qemu_log("\n");
4346 }
4347 #endif
4348 }
4349
4350 void gen_intermediate_code (CPUS390XState *env, struct TranslationBlock *tb)
4351 {
4352 gen_intermediate_code_internal(env, tb, 0);
4353 }
4354
4355 void gen_intermediate_code_pc (CPUS390XState *env, struct TranslationBlock *tb)
4356 {
4357 gen_intermediate_code_internal(env, tb, 1);
4358 }
4359
4360 void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos)
4361 {
4362 int cc_op;
4363 env->psw.addr = tcg_ctx.gen_opc_pc[pc_pos];
4364 cc_op = gen_opc_cc_op[pc_pos];
4365 if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {
4366 env->cc_op = cc_op;
4367 }
4368 }
Qemu copy for testing