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[qemu.git] / target-s390x / translate.c
1 /*
2 * S/390 translation
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* #define DEBUG_INLINE_BRANCHES */
22 #define S390X_DEBUG_DISAS
23 /* #define S390X_DEBUG_DISAS_VERBOSE */
24
25 #ifdef S390X_DEBUG_DISAS_VERBOSE
26 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
27 #else
28 # define LOG_DISAS(...) do { } while (0)
29 #endif
30
31 #include "cpu.h"
32 #include "disas/disas.h"
33 #include "tcg-op.h"
34 #include "qemu/log.h"
35 #include "qemu/host-utils.h"
36
37 /* global register indexes */
38 static TCGv_ptr cpu_env;
39
40 #include "exec/gen-icount.h"
41 #include "helper.h"
42 #define GEN_HELPER 1
43 #include "helper.h"
44
45
46 /* Information that (most) every instruction needs to manipulate. */
47 typedef struct DisasContext DisasContext;
48 typedef struct DisasInsn DisasInsn;
49 typedef struct DisasFields DisasFields;
50
51 struct DisasContext {
52 struct TranslationBlock *tb;
53 const DisasInsn *insn;
54 DisasFields *fields;
55 uint64_t pc, next_pc;
56 enum cc_op cc_op;
57 bool singlestep_enabled;
58 int is_jmp;
59 };
60
61 /* Information carried about a condition to be evaluated. */
62 typedef struct {
63 TCGCond cond:8;
64 bool is_64;
65 bool g1;
66 bool g2;
67 union {
68 struct { TCGv_i64 a, b; } s64;
69 struct { TCGv_i32 a, b; } s32;
70 } u;
71 } DisasCompare;
72
73 #define DISAS_EXCP 4
74
75 static void gen_op_calc_cc(DisasContext *s);
76
77 #ifdef DEBUG_INLINE_BRANCHES
78 static uint64_t inline_branch_hit[CC_OP_MAX];
79 static uint64_t inline_branch_miss[CC_OP_MAX];
80 #endif
81
82 static inline void debug_insn(uint64_t insn)
83 {
84 LOG_DISAS("insn: 0x%" PRIx64 "\n", insn);
85 }
86
87 static inline uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
88 {
89 if (!(s->tb->flags & FLAG_MASK_64)) {
90 if (s->tb->flags & FLAG_MASK_32) {
91 return pc | 0x80000000;
92 }
93 }
94 return pc;
95 }
96
97 void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
98 int flags)
99 {
100 int i;
101
102 if (env->cc_op > 3) {
103 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
104 env->psw.mask, env->psw.addr, cc_name(env->cc_op));
105 } else {
106 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
107 env->psw.mask, env->psw.addr, env->cc_op);
108 }
109
110 for (i = 0; i < 16; i++) {
111 cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
112 if ((i % 4) == 3) {
113 cpu_fprintf(f, "\n");
114 } else {
115 cpu_fprintf(f, " ");
116 }
117 }
118
119 for (i = 0; i < 16; i++) {
120 cpu_fprintf(f, "F%02d=%016" PRIx64, i, env->fregs[i].ll);
121 if ((i % 4) == 3) {
122 cpu_fprintf(f, "\n");
123 } else {
124 cpu_fprintf(f, " ");
125 }
126 }
127
128 #ifndef CONFIG_USER_ONLY
129 for (i = 0; i < 16; i++) {
130 cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
131 if ((i % 4) == 3) {
132 cpu_fprintf(f, "\n");
133 } else {
134 cpu_fprintf(f, " ");
135 }
136 }
137 #endif
138
139 #ifdef DEBUG_INLINE_BRANCHES
140 for (i = 0; i < CC_OP_MAX; i++) {
141 cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
142 inline_branch_miss[i], inline_branch_hit[i]);
143 }
144 #endif
145
146 cpu_fprintf(f, "\n");
147 }
148
149 static TCGv_i64 psw_addr;
150 static TCGv_i64 psw_mask;
151
152 static TCGv_i32 cc_op;
153 static TCGv_i64 cc_src;
154 static TCGv_i64 cc_dst;
155 static TCGv_i64 cc_vr;
156
157 static char cpu_reg_names[32][4];
158 static TCGv_i64 regs[16];
159 static TCGv_i64 fregs[16];
160
161 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
162
163 void s390x_translate_init(void)
164 {
165 int i;
166
167 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
168 psw_addr = tcg_global_mem_new_i64(TCG_AREG0,
169 offsetof(CPUS390XState, psw.addr),
170 "psw_addr");
171 psw_mask = tcg_global_mem_new_i64(TCG_AREG0,
172 offsetof(CPUS390XState, psw.mask),
173 "psw_mask");
174
175 cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUS390XState, cc_op),
176 "cc_op");
177 cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_src),
178 "cc_src");
179 cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_dst),
180 "cc_dst");
181 cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_vr),
182 "cc_vr");
183
184 for (i = 0; i < 16; i++) {
185 snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i);
186 regs[i] = tcg_global_mem_new(TCG_AREG0,
187 offsetof(CPUS390XState, regs[i]),
188 cpu_reg_names[i]);
189 }
190
191 for (i = 0; i < 16; i++) {
192 snprintf(cpu_reg_names[i + 16], sizeof(cpu_reg_names[0]), "f%d", i);
193 fregs[i] = tcg_global_mem_new(TCG_AREG0,
194 offsetof(CPUS390XState, fregs[i].d),
195 cpu_reg_names[i + 16]);
196 }
197
198 /* register helpers */
199 #define GEN_HELPER 2
200 #include "helper.h"
201 }
202
203 static inline TCGv_i64 load_reg(int reg)
204 {
205 TCGv_i64 r = tcg_temp_new_i64();
206 tcg_gen_mov_i64(r, regs[reg]);
207 return r;
208 }
209
210 static inline TCGv_i64 load_freg(int reg)
211 {
212 TCGv_i64 r = tcg_temp_new_i64();
213 tcg_gen_mov_i64(r, fregs[reg]);
214 return r;
215 }
216
217 static inline TCGv_i32 load_freg32(int reg)
218 {
219 TCGv_i32 r = tcg_temp_new_i32();
220 #if HOST_LONG_BITS == 32
221 tcg_gen_mov_i32(r, TCGV_HIGH(fregs[reg]));
222 #else
223 tcg_gen_shri_i64(MAKE_TCGV_I64(GET_TCGV_I32(r)), fregs[reg], 32);
224 #endif
225 return r;
226 }
227
228 static inline TCGv_i64 load_freg32_i64(int reg)
229 {
230 TCGv_i64 r = tcg_temp_new_i64();
231 tcg_gen_shri_i64(r, fregs[reg], 32);
232 return r;
233 }
234
235 static inline TCGv_i32 load_reg32(int reg)
236 {
237 TCGv_i32 r = tcg_temp_new_i32();
238 tcg_gen_trunc_i64_i32(r, regs[reg]);
239 return r;
240 }
241
242 static inline TCGv_i64 load_reg32_i64(int reg)
243 {
244 TCGv_i64 r = tcg_temp_new_i64();
245 tcg_gen_ext32s_i64(r, regs[reg]);
246 return r;
247 }
248
249 static inline void store_reg(int reg, TCGv_i64 v)
250 {
251 tcg_gen_mov_i64(regs[reg], v);
252 }
253
254 static inline void store_freg(int reg, TCGv_i64 v)
255 {
256 tcg_gen_mov_i64(fregs[reg], v);
257 }
258
259 static inline void store_reg32(int reg, TCGv_i32 v)
260 {
261 /* 32 bit register writes keep the upper half */
262 #if HOST_LONG_BITS == 32
263 tcg_gen_mov_i32(TCGV_LOW(regs[reg]), v);
264 #else
265 tcg_gen_deposit_i64(regs[reg], regs[reg],
266 MAKE_TCGV_I64(GET_TCGV_I32(v)), 0, 32);
267 #endif
268 }
269
270 static inline void store_reg32_i64(int reg, TCGv_i64 v)
271 {
272 /* 32 bit register writes keep the upper half */
273 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
274 }
275
276 static inline void store_reg32h_i64(int reg, TCGv_i64 v)
277 {
278 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 32, 32);
279 }
280
281 static inline void store_freg32(int reg, TCGv_i32 v)
282 {
283 /* 32 bit register writes keep the lower half */
284 #if HOST_LONG_BITS == 32
285 tcg_gen_mov_i32(TCGV_HIGH(fregs[reg]), v);
286 #else
287 tcg_gen_deposit_i64(fregs[reg], fregs[reg],
288 MAKE_TCGV_I64(GET_TCGV_I32(v)), 32, 32);
289 #endif
290 }
291
292 static inline void store_freg32_i64(int reg, TCGv_i64 v)
293 {
294 tcg_gen_deposit_i64(fregs[reg], fregs[reg], v, 32, 32);
295 }
296
297 static inline void return_low128(TCGv_i64 dest)
298 {
299 tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl));
300 }
301
302 static inline void update_psw_addr(DisasContext *s)
303 {
304 /* psw.addr */
305 tcg_gen_movi_i64(psw_addr, s->pc);
306 }
307
308 static inline void potential_page_fault(DisasContext *s)
309 {
310 #ifndef CONFIG_USER_ONLY
311 update_psw_addr(s);
312 gen_op_calc_cc(s);
313 #endif
314 }
315
316 static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
317 {
318 return (uint64_t)cpu_lduw_code(env, pc);
319 }
320
321 static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
322 {
323 return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
324 }
325
326 static inline uint64_t ld_code6(CPUS390XState *env, uint64_t pc)
327 {
328 return (ld_code2(env, pc) << 32) | ld_code4(env, pc + 2);
329 }
330
331 static inline int get_mem_index(DisasContext *s)
332 {
333 switch (s->tb->flags & FLAG_MASK_ASC) {
334 case PSW_ASC_PRIMARY >> 32:
335 return 0;
336 case PSW_ASC_SECONDARY >> 32:
337 return 1;
338 case PSW_ASC_HOME >> 32:
339 return 2;
340 default:
341 tcg_abort();
342 break;
343 }
344 }
345
346 static void gen_exception(int excp)
347 {
348 TCGv_i32 tmp = tcg_const_i32(excp);
349 gen_helper_exception(cpu_env, tmp);
350 tcg_temp_free_i32(tmp);
351 }
352
353 static void gen_program_exception(DisasContext *s, int code)
354 {
355 TCGv_i32 tmp;
356
357 /* Remember what pgm exeption this was. */
358 tmp = tcg_const_i32(code);
359 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
360 tcg_temp_free_i32(tmp);
361
362 tmp = tcg_const_i32(s->next_pc - s->pc);
363 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen));
364 tcg_temp_free_i32(tmp);
365
366 /* Advance past instruction. */
367 s->pc = s->next_pc;
368 update_psw_addr(s);
369
370 /* Save off cc. */
371 gen_op_calc_cc(s);
372
373 /* Trigger exception. */
374 gen_exception(EXCP_PGM);
375
376 /* End TB here. */
377 s->is_jmp = DISAS_EXCP;
378 }
379
380 static inline void gen_illegal_opcode(DisasContext *s)
381 {
382 gen_program_exception(s, PGM_SPECIFICATION);
383 }
384
385 static inline void check_privileged(DisasContext *s)
386 {
387 if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
388 gen_program_exception(s, PGM_PRIVILEGED);
389 }
390 }
391
392 static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
393 {
394 TCGv_i64 tmp;
395
396 /* 31-bitify the immediate part; register contents are dealt with below */
397 if (!(s->tb->flags & FLAG_MASK_64)) {
398 d2 &= 0x7fffffffUL;
399 }
400
401 if (x2) {
402 if (d2) {
403 tmp = tcg_const_i64(d2);
404 tcg_gen_add_i64(tmp, tmp, regs[x2]);
405 } else {
406 tmp = load_reg(x2);
407 }
408 if (b2) {
409 tcg_gen_add_i64(tmp, tmp, regs[b2]);
410 }
411 } else if (b2) {
412 if (d2) {
413 tmp = tcg_const_i64(d2);
414 tcg_gen_add_i64(tmp, tmp, regs[b2]);
415 } else {
416 tmp = load_reg(b2);
417 }
418 } else {
419 tmp = tcg_const_i64(d2);
420 }
421
422 /* 31-bit mode mask if there are values loaded from registers */
423 if (!(s->tb->flags & FLAG_MASK_64) && (x2 || b2)) {
424 tcg_gen_andi_i64(tmp, tmp, 0x7fffffffUL);
425 }
426
427 return tmp;
428 }
429
430 static inline void gen_op_movi_cc(DisasContext *s, uint32_t val)
431 {
432 s->cc_op = CC_OP_CONST0 + val;
433 }
434
435 static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
436 {
437 tcg_gen_discard_i64(cc_src);
438 tcg_gen_mov_i64(cc_dst, dst);
439 tcg_gen_discard_i64(cc_vr);
440 s->cc_op = op;
441 }
442
443 static void gen_op_update1_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 dst)
444 {
445 tcg_gen_discard_i64(cc_src);
446 tcg_gen_extu_i32_i64(cc_dst, dst);
447 tcg_gen_discard_i64(cc_vr);
448 s->cc_op = op;
449 }
450
451 static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
452 TCGv_i64 dst)
453 {
454 tcg_gen_mov_i64(cc_src, src);
455 tcg_gen_mov_i64(cc_dst, dst);
456 tcg_gen_discard_i64(cc_vr);
457 s->cc_op = op;
458 }
459
460 static void gen_op_update2_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src,
461 TCGv_i32 dst)
462 {
463 tcg_gen_extu_i32_i64(cc_src, src);
464 tcg_gen_extu_i32_i64(cc_dst, dst);
465 tcg_gen_discard_i64(cc_vr);
466 s->cc_op = op;
467 }
468
469 static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
470 TCGv_i64 dst, TCGv_i64 vr)
471 {
472 tcg_gen_mov_i64(cc_src, src);
473 tcg_gen_mov_i64(cc_dst, dst);
474 tcg_gen_mov_i64(cc_vr, vr);
475 s->cc_op = op;
476 }
477
478 static inline void set_cc_nz_u32(DisasContext *s, TCGv_i32 val)
479 {
480 gen_op_update1_cc_i32(s, CC_OP_NZ, val);
481 }
482
483 static inline void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
484 {
485 gen_op_update1_cc_i64(s, CC_OP_NZ, val);
486 }
487
488 static inline void gen_set_cc_nz_f32(DisasContext *s, TCGv_i64 val)
489 {
490 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, val);
491 }
492
493 static inline void gen_set_cc_nz_f64(DisasContext *s, TCGv_i64 val)
494 {
495 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, val);
496 }
497
498 static inline void gen_set_cc_nz_f128(DisasContext *s, TCGv_i64 vh, TCGv_i64 vl)
499 {
500 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, vh, vl);
501 }
502
503 static inline void cmp_32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
504 enum cc_op cond)
505 {
506 gen_op_update2_cc_i32(s, cond, v1, v2);
507 }
508
509 static inline void cmp_64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
510 enum cc_op cond)
511 {
512 gen_op_update2_cc_i64(s, cond, v1, v2);
513 }
514
515 static inline void cmp_s32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
516 {
517 cmp_32(s, v1, v2, CC_OP_LTGT_32);
518 }
519
520 static inline void cmp_u32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
521 {
522 cmp_32(s, v1, v2, CC_OP_LTUGTU_32);
523 }
524
525 static inline void cmp_s32c(DisasContext *s, TCGv_i32 v1, int32_t v2)
526 {
527 /* XXX optimize for the constant? put it in s? */
528 TCGv_i32 tmp = tcg_const_i32(v2);
529 cmp_32(s, v1, tmp, CC_OP_LTGT_32);
530 tcg_temp_free_i32(tmp);
531 }
532
533 static inline void cmp_u32c(DisasContext *s, TCGv_i32 v1, uint32_t v2)
534 {
535 TCGv_i32 tmp = tcg_const_i32(v2);
536 cmp_32(s, v1, tmp, CC_OP_LTUGTU_32);
537 tcg_temp_free_i32(tmp);
538 }
539
540 static inline void cmp_s64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
541 {
542 cmp_64(s, v1, v2, CC_OP_LTGT_64);
543 }
544
545 static inline void cmp_u64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
546 {
547 cmp_64(s, v1, v2, CC_OP_LTUGTU_64);
548 }
549
550 static inline void cmp_s64c(DisasContext *s, TCGv_i64 v1, int64_t v2)
551 {
552 TCGv_i64 tmp = tcg_const_i64(v2);
553 cmp_s64(s, v1, tmp);
554 tcg_temp_free_i64(tmp);
555 }
556
557 static inline void cmp_u64c(DisasContext *s, TCGv_i64 v1, uint64_t v2)
558 {
559 TCGv_i64 tmp = tcg_const_i64(v2);
560 cmp_u64(s, v1, tmp);
561 tcg_temp_free_i64(tmp);
562 }
563
564 static inline void set_cc_s32(DisasContext *s, TCGv_i32 val)
565 {
566 gen_op_update1_cc_i32(s, CC_OP_LTGT0_32, val);
567 }
568
569 static inline void set_cc_s64(DisasContext *s, TCGv_i64 val)
570 {
571 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, val);
572 }
573
574 /* CC value is in env->cc_op */
575 static inline void set_cc_static(DisasContext *s)
576 {
577 tcg_gen_discard_i64(cc_src);
578 tcg_gen_discard_i64(cc_dst);
579 tcg_gen_discard_i64(cc_vr);
580 s->cc_op = CC_OP_STATIC;
581 }
582
583 static inline void gen_op_set_cc_op(DisasContext *s)
584 {
585 if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
586 tcg_gen_movi_i32(cc_op, s->cc_op);
587 }
588 }
589
590 static inline void gen_update_cc_op(DisasContext *s)
591 {
592 gen_op_set_cc_op(s);
593 }
594
595 /* calculates cc into cc_op */
596 static void gen_op_calc_cc(DisasContext *s)
597 {
598 TCGv_i32 local_cc_op = tcg_const_i32(s->cc_op);
599 TCGv_i64 dummy = tcg_const_i64(0);
600
601 switch (s->cc_op) {
602 case CC_OP_CONST0:
603 case CC_OP_CONST1:
604 case CC_OP_CONST2:
605 case CC_OP_CONST3:
606 /* s->cc_op is the cc value */
607 tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
608 break;
609 case CC_OP_STATIC:
610 /* env->cc_op already is the cc value */
611 break;
612 case CC_OP_NZ:
613 case CC_OP_ABS_64:
614 case CC_OP_NABS_64:
615 case CC_OP_ABS_32:
616 case CC_OP_NABS_32:
617 case CC_OP_LTGT0_32:
618 case CC_OP_LTGT0_64:
619 case CC_OP_COMP_32:
620 case CC_OP_COMP_64:
621 case CC_OP_NZ_F32:
622 case CC_OP_NZ_F64:
623 case CC_OP_FLOGR:
624 /* 1 argument */
625 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dummy);
626 break;
627 case CC_OP_ICM:
628 case CC_OP_LTGT_32:
629 case CC_OP_LTGT_64:
630 case CC_OP_LTUGTU_32:
631 case CC_OP_LTUGTU_64:
632 case CC_OP_TM_32:
633 case CC_OP_TM_64:
634 case CC_OP_SLA_32:
635 case CC_OP_SLA_64:
636 case CC_OP_NZ_F128:
637 /* 2 arguments */
638 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
639 break;
640 case CC_OP_ADD_64:
641 case CC_OP_ADDU_64:
642 case CC_OP_ADDC_64:
643 case CC_OP_SUB_64:
644 case CC_OP_SUBU_64:
645 case CC_OP_SUBB_64:
646 case CC_OP_ADD_32:
647 case CC_OP_ADDU_32:
648 case CC_OP_ADDC_32:
649 case CC_OP_SUB_32:
650 case CC_OP_SUBU_32:
651 case CC_OP_SUBB_32:
652 /* 3 arguments */
653 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc_vr);
654 break;
655 case CC_OP_DYNAMIC:
656 /* unknown operation - assume 3 arguments and cc_op in env */
657 gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr);
658 break;
659 default:
660 tcg_abort();
661 }
662
663 tcg_temp_free_i32(local_cc_op);
664 tcg_temp_free_i64(dummy);
665
666 /* We now have cc in cc_op as constant */
667 set_cc_static(s);
668 }
669
670 static inline void decode_rr(DisasContext *s, uint64_t insn, int *r1, int *r2)
671 {
672 debug_insn(insn);
673
674 *r1 = (insn >> 4) & 0xf;
675 *r2 = insn & 0xf;
676 }
677
678 static inline TCGv_i64 decode_rx(DisasContext *s, uint64_t insn, int *r1,
679 int *x2, int *b2, int *d2)
680 {
681 debug_insn(insn);
682
683 *r1 = (insn >> 20) & 0xf;
684 *x2 = (insn >> 16) & 0xf;
685 *b2 = (insn >> 12) & 0xf;
686 *d2 = insn & 0xfff;
687
688 return get_address(s, *x2, *b2, *d2);
689 }
690
691 static inline void decode_rs(DisasContext *s, uint64_t insn, int *r1, int *r3,
692 int *b2, int *d2)
693 {
694 debug_insn(insn);
695
696 *r1 = (insn >> 20) & 0xf;
697 /* aka m3 */
698 *r3 = (insn >> 16) & 0xf;
699 *b2 = (insn >> 12) & 0xf;
700 *d2 = insn & 0xfff;
701 }
702
703 static inline TCGv_i64 decode_si(DisasContext *s, uint64_t insn, int *i2,
704 int *b1, int *d1)
705 {
706 debug_insn(insn);
707
708 *i2 = (insn >> 16) & 0xff;
709 *b1 = (insn >> 12) & 0xf;
710 *d1 = insn & 0xfff;
711
712 return get_address(s, 0, *b1, *d1);
713 }
714
715 static int use_goto_tb(DisasContext *s, uint64_t dest)
716 {
717 /* NOTE: we handle the case where the TB spans two pages here */
718 return (((dest & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK)
719 || (dest & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK))
720 && !s->singlestep_enabled
721 && !(s->tb->cflags & CF_LAST_IO));
722 }
723
724 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong pc)
725 {
726 gen_update_cc_op(s);
727
728 if (use_goto_tb(s, pc)) {
729 tcg_gen_goto_tb(tb_num);
730 tcg_gen_movi_i64(psw_addr, pc);
731 tcg_gen_exit_tb((tcg_target_long)s->tb + tb_num);
732 } else {
733 /* jump to another page: currently not optimized */
734 tcg_gen_movi_i64(psw_addr, pc);
735 tcg_gen_exit_tb(0);
736 }
737 }
738
739 static inline void account_noninline_branch(DisasContext *s, int cc_op)
740 {
741 #ifdef DEBUG_INLINE_BRANCHES
742 inline_branch_miss[cc_op]++;
743 #endif
744 }
745
746 static inline void account_inline_branch(DisasContext *s, int cc_op)
747 {
748 #ifdef DEBUG_INLINE_BRANCHES
749 inline_branch_hit[cc_op]++;
750 #endif
751 }
752
753 /* Table of mask values to comparison codes, given a comparison as input.
754 For a true comparison CC=3 will never be set, but we treat this
755 conservatively for possible use when CC=3 indicates overflow. */
756 static const TCGCond ltgt_cond[16] = {
757 TCG_COND_NEVER, TCG_COND_NEVER, /* | | | x */
758 TCG_COND_GT, TCG_COND_NEVER, /* | | GT | x */
759 TCG_COND_LT, TCG_COND_NEVER, /* | LT | | x */
760 TCG_COND_NE, TCG_COND_NEVER, /* | LT | GT | x */
761 TCG_COND_EQ, TCG_COND_NEVER, /* EQ | | | x */
762 TCG_COND_GE, TCG_COND_NEVER, /* EQ | | GT | x */
763 TCG_COND_LE, TCG_COND_NEVER, /* EQ | LT | | x */
764 TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | LT | GT | x */
765 };
766
767 /* Table of mask values to comparison codes, given a logic op as input.
768 For such, only CC=0 and CC=1 should be possible. */
769 static const TCGCond nz_cond[16] = {
770 /* | | x | x */
771 TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER,
772 /* | NE | x | x */
773 TCG_COND_NE, TCG_COND_NE, TCG_COND_NE, TCG_COND_NE,
774 /* EQ | | x | x */
775 TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ,
776 /* EQ | NE | x | x */
777 TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS,
778 };
779
780 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
781 details required to generate a TCG comparison. */
782 static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
783 {
784 TCGCond cond;
785 enum cc_op old_cc_op = s->cc_op;
786
787 if (mask == 15 || mask == 0) {
788 c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER);
789 c->u.s32.a = cc_op;
790 c->u.s32.b = cc_op;
791 c->g1 = c->g2 = true;
792 c->is_64 = false;
793 return;
794 }
795
796 /* Find the TCG condition for the mask + cc op. */
797 switch (old_cc_op) {
798 case CC_OP_LTGT0_32:
799 case CC_OP_LTGT0_64:
800 case CC_OP_LTGT_32:
801 case CC_OP_LTGT_64:
802 cond = ltgt_cond[mask];
803 if (cond == TCG_COND_NEVER) {
804 goto do_dynamic;
805 }
806 account_inline_branch(s, old_cc_op);
807 break;
808
809 case CC_OP_LTUGTU_32:
810 case CC_OP_LTUGTU_64:
811 cond = tcg_unsigned_cond(ltgt_cond[mask]);
812 if (cond == TCG_COND_NEVER) {
813 goto do_dynamic;
814 }
815 account_inline_branch(s, old_cc_op);
816 break;
817
818 case CC_OP_NZ:
819 cond = nz_cond[mask];
820 if (cond == TCG_COND_NEVER) {
821 goto do_dynamic;
822 }
823 account_inline_branch(s, old_cc_op);
824 break;
825
826 case CC_OP_TM_32:
827 case CC_OP_TM_64:
828 switch (mask) {
829 case 8:
830 cond = TCG_COND_EQ;
831 break;
832 case 4 | 2 | 1:
833 cond = TCG_COND_NE;
834 break;
835 default:
836 goto do_dynamic;
837 }
838 account_inline_branch(s, old_cc_op);
839 break;
840
841 case CC_OP_ICM:
842 switch (mask) {
843 case 8:
844 cond = TCG_COND_EQ;
845 break;
846 case 4 | 2 | 1:
847 case 4 | 2:
848 cond = TCG_COND_NE;
849 break;
850 default:
851 goto do_dynamic;
852 }
853 account_inline_branch(s, old_cc_op);
854 break;
855
856 case CC_OP_FLOGR:
857 switch (mask & 0xa) {
858 case 8: /* src == 0 -> no one bit found */
859 cond = TCG_COND_EQ;
860 break;
861 case 2: /* src != 0 -> one bit found */
862 cond = TCG_COND_NE;
863 break;
864 default:
865 goto do_dynamic;
866 }
867 account_inline_branch(s, old_cc_op);
868 break;
869
870 default:
871 do_dynamic:
872 /* Calculate cc value. */
873 gen_op_calc_cc(s);
874 /* FALLTHRU */
875
876 case CC_OP_STATIC:
877 /* Jump based on CC. We'll load up the real cond below;
878 the assignment here merely avoids a compiler warning. */
879 account_noninline_branch(s, old_cc_op);
880 old_cc_op = CC_OP_STATIC;
881 cond = TCG_COND_NEVER;
882 break;
883 }
884
885 /* Load up the arguments of the comparison. */
886 c->is_64 = true;
887 c->g1 = c->g2 = false;
888 switch (old_cc_op) {
889 case CC_OP_LTGT0_32:
890 c->is_64 = false;
891 c->u.s32.a = tcg_temp_new_i32();
892 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_dst);
893 c->u.s32.b = tcg_const_i32(0);
894 break;
895 case CC_OP_LTGT_32:
896 case CC_OP_LTUGTU_32:
897 c->is_64 = false;
898 c->u.s32.a = tcg_temp_new_i32();
899 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_src);
900 c->u.s32.b = tcg_temp_new_i32();
901 tcg_gen_trunc_i64_i32(c->u.s32.b, cc_dst);
902 break;
903
904 case CC_OP_LTGT0_64:
905 case CC_OP_NZ:
906 case CC_OP_FLOGR:
907 c->u.s64.a = cc_dst;
908 c->u.s64.b = tcg_const_i64(0);
909 c->g1 = true;
910 break;
911 case CC_OP_LTGT_64:
912 case CC_OP_LTUGTU_64:
913 c->u.s64.a = cc_src;
914 c->u.s64.b = cc_dst;
915 c->g1 = c->g2 = true;
916 break;
917
918 case CC_OP_TM_32:
919 case CC_OP_TM_64:
920 case CC_OP_ICM:
921 c->u.s64.a = tcg_temp_new_i64();
922 c->u.s64.b = tcg_const_i64(0);
923 tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
924 break;
925
926 case CC_OP_STATIC:
927 c->is_64 = false;
928 c->u.s32.a = cc_op;
929 c->g1 = true;
930 switch (mask) {
931 case 0x8 | 0x4 | 0x2: /* cc != 3 */
932 cond = TCG_COND_NE;
933 c->u.s32.b = tcg_const_i32(3);
934 break;
935 case 0x8 | 0x4 | 0x1: /* cc != 2 */
936 cond = TCG_COND_NE;
937 c->u.s32.b = tcg_const_i32(2);
938 break;
939 case 0x8 | 0x2 | 0x1: /* cc != 1 */
940 cond = TCG_COND_NE;
941 c->u.s32.b = tcg_const_i32(1);
942 break;
943 case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
944 cond = TCG_COND_EQ;
945 c->g1 = false;
946 c->u.s32.a = tcg_temp_new_i32();
947 c->u.s32.b = tcg_const_i32(0);
948 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
949 break;
950 case 0x8 | 0x4: /* cc < 2 */
951 cond = TCG_COND_LTU;
952 c->u.s32.b = tcg_const_i32(2);
953 break;
954 case 0x8: /* cc == 0 */
955 cond = TCG_COND_EQ;
956 c->u.s32.b = tcg_const_i32(0);
957 break;
958 case 0x4 | 0x2 | 0x1: /* cc != 0 */
959 cond = TCG_COND_NE;
960 c->u.s32.b = tcg_const_i32(0);
961 break;
962 case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
963 cond = TCG_COND_NE;
964 c->g1 = false;
965 c->u.s32.a = tcg_temp_new_i32();
966 c->u.s32.b = tcg_const_i32(0);
967 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
968 break;
969 case 0x4: /* cc == 1 */
970 cond = TCG_COND_EQ;
971 c->u.s32.b = tcg_const_i32(1);
972 break;
973 case 0x2 | 0x1: /* cc > 1 */
974 cond = TCG_COND_GTU;
975 c->u.s32.b = tcg_const_i32(1);
976 break;
977 case 0x2: /* cc == 2 */
978 cond = TCG_COND_EQ;
979 c->u.s32.b = tcg_const_i32(2);
980 break;
981 case 0x1: /* cc == 3 */
982 cond = TCG_COND_EQ;
983 c->u.s32.b = tcg_const_i32(3);
984 break;
985 default:
986 /* CC is masked by something else: (8 >> cc) & mask. */
987 cond = TCG_COND_NE;
988 c->g1 = false;
989 c->u.s32.a = tcg_const_i32(8);
990 c->u.s32.b = tcg_const_i32(0);
991 tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op);
992 tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
993 break;
994 }
995 break;
996
997 default:
998 abort();
999 }
1000 c->cond = cond;
1001 }
1002
1003 static void free_compare(DisasCompare *c)
1004 {
1005 if (!c->g1) {
1006 if (c->is_64) {
1007 tcg_temp_free_i64(c->u.s64.a);
1008 } else {
1009 tcg_temp_free_i32(c->u.s32.a);
1010 }
1011 }
1012 if (!c->g2) {
1013 if (c->is_64) {
1014 tcg_temp_free_i64(c->u.s64.b);
1015 } else {
1016 tcg_temp_free_i32(c->u.s32.b);
1017 }
1018 }
1019 }
1020
1021 static void disas_b2(CPUS390XState *env, DisasContext *s, int op,
1022 uint32_t insn)
1023 {
1024 #ifndef CONFIG_USER_ONLY
1025 TCGv_i64 tmp, tmp2, tmp3;
1026 TCGv_i32 tmp32_1, tmp32_2;
1027 int r1, r2;
1028 int r3, d2, b2;
1029
1030 r1 = (insn >> 4) & 0xf;
1031 r2 = insn & 0xf;
1032
1033 LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op, r1, r2);
1034
1035 switch (op) {
1036 case 0x02: /* STIDP D2(B2) [S] */
1037 /* Store CPU ID */
1038 check_privileged(s);
1039 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1040 tmp = get_address(s, 0, b2, d2);
1041 potential_page_fault(s);
1042 gen_helper_stidp(cpu_env, tmp);
1043 tcg_temp_free_i64(tmp);
1044 break;
1045 case 0x04: /* SCK D2(B2) [S] */
1046 /* Set Clock */
1047 check_privileged(s);
1048 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1049 tmp = get_address(s, 0, b2, d2);
1050 potential_page_fault(s);
1051 gen_helper_sck(cc_op, tmp);
1052 set_cc_static(s);
1053 tcg_temp_free_i64(tmp);
1054 break;
1055 case 0x05: /* STCK D2(B2) [S] */
1056 /* Store Clock */
1057 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1058 tmp = get_address(s, 0, b2, d2);
1059 potential_page_fault(s);
1060 gen_helper_stck(cc_op, cpu_env, tmp);
1061 set_cc_static(s);
1062 tcg_temp_free_i64(tmp);
1063 break;
1064 case 0x06: /* SCKC D2(B2) [S] */
1065 /* Set Clock Comparator */
1066 check_privileged(s);
1067 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1068 tmp = get_address(s, 0, b2, d2);
1069 potential_page_fault(s);
1070 gen_helper_sckc(cpu_env, tmp);
1071 tcg_temp_free_i64(tmp);
1072 break;
1073 case 0x07: /* STCKC D2(B2) [S] */
1074 /* Store Clock Comparator */
1075 check_privileged(s);
1076 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1077 tmp = get_address(s, 0, b2, d2);
1078 potential_page_fault(s);
1079 gen_helper_stckc(cpu_env, tmp);
1080 tcg_temp_free_i64(tmp);
1081 break;
1082 case 0x08: /* SPT D2(B2) [S] */
1083 /* Set CPU Timer */
1084 check_privileged(s);
1085 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1086 tmp = get_address(s, 0, b2, d2);
1087 potential_page_fault(s);
1088 gen_helper_spt(cpu_env, tmp);
1089 tcg_temp_free_i64(tmp);
1090 break;
1091 case 0x09: /* STPT D2(B2) [S] */
1092 /* Store CPU Timer */
1093 check_privileged(s);
1094 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1095 tmp = get_address(s, 0, b2, d2);
1096 potential_page_fault(s);
1097 gen_helper_stpt(cpu_env, tmp);
1098 tcg_temp_free_i64(tmp);
1099 break;
1100 case 0x0a: /* SPKA D2(B2) [S] */
1101 /* Set PSW Key from Address */
1102 check_privileged(s);
1103 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1104 tmp = get_address(s, 0, b2, d2);
1105 tmp2 = tcg_temp_new_i64();
1106 tcg_gen_andi_i64(tmp2, psw_mask, ~PSW_MASK_KEY);
1107 tcg_gen_shli_i64(tmp, tmp, PSW_SHIFT_KEY - 4);
1108 tcg_gen_or_i64(psw_mask, tmp2, tmp);
1109 tcg_temp_free_i64(tmp2);
1110 tcg_temp_free_i64(tmp);
1111 break;
1112 case 0x0d: /* PTLB [S] */
1113 /* Purge TLB */
1114 check_privileged(s);
1115 gen_helper_ptlb(cpu_env);
1116 break;
1117 case 0x10: /* SPX D2(B2) [S] */
1118 /* Set Prefix Register */
1119 check_privileged(s);
1120 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1121 tmp = get_address(s, 0, b2, d2);
1122 potential_page_fault(s);
1123 gen_helper_spx(cpu_env, tmp);
1124 tcg_temp_free_i64(tmp);
1125 break;
1126 case 0x11: /* STPX D2(B2) [S] */
1127 /* Store Prefix */
1128 check_privileged(s);
1129 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1130 tmp = get_address(s, 0, b2, d2);
1131 tmp2 = tcg_temp_new_i64();
1132 tcg_gen_ld_i64(tmp2, cpu_env, offsetof(CPUS390XState, psa));
1133 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1134 tcg_temp_free_i64(tmp);
1135 tcg_temp_free_i64(tmp2);
1136 break;
1137 case 0x12: /* STAP D2(B2) [S] */
1138 /* Store CPU Address */
1139 check_privileged(s);
1140 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1141 tmp = get_address(s, 0, b2, d2);
1142 tmp2 = tcg_temp_new_i64();
1143 tmp32_1 = tcg_temp_new_i32();
1144 tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, cpu_num));
1145 tcg_gen_extu_i32_i64(tmp2, tmp32_1);
1146 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1147 tcg_temp_free_i64(tmp);
1148 tcg_temp_free_i64(tmp2);
1149 tcg_temp_free_i32(tmp32_1);
1150 break;
1151 case 0x21: /* IPTE R1,R2 [RRE] */
1152 /* Invalidate PTE */
1153 check_privileged(s);
1154 r1 = (insn >> 4) & 0xf;
1155 r2 = insn & 0xf;
1156 tmp = load_reg(r1);
1157 tmp2 = load_reg(r2);
1158 gen_helper_ipte(cpu_env, tmp, tmp2);
1159 tcg_temp_free_i64(tmp);
1160 tcg_temp_free_i64(tmp2);
1161 break;
1162 case 0x29: /* ISKE R1,R2 [RRE] */
1163 /* Insert Storage Key Extended */
1164 check_privileged(s);
1165 r1 = (insn >> 4) & 0xf;
1166 r2 = insn & 0xf;
1167 tmp = load_reg(r2);
1168 tmp2 = tcg_temp_new_i64();
1169 gen_helper_iske(tmp2, cpu_env, tmp);
1170 store_reg(r1, tmp2);
1171 tcg_temp_free_i64(tmp);
1172 tcg_temp_free_i64(tmp2);
1173 break;
1174 case 0x2a: /* RRBE R1,R2 [RRE] */
1175 /* Set Storage Key Extended */
1176 check_privileged(s);
1177 r1 = (insn >> 4) & 0xf;
1178 r2 = insn & 0xf;
1179 tmp32_1 = load_reg32(r1);
1180 tmp = load_reg(r2);
1181 gen_helper_rrbe(cc_op, cpu_env, tmp32_1, tmp);
1182 set_cc_static(s);
1183 tcg_temp_free_i32(tmp32_1);
1184 tcg_temp_free_i64(tmp);
1185 break;
1186 case 0x2b: /* SSKE R1,R2 [RRE] */
1187 /* Set Storage Key Extended */
1188 check_privileged(s);
1189 r1 = (insn >> 4) & 0xf;
1190 r2 = insn & 0xf;
1191 tmp32_1 = load_reg32(r1);
1192 tmp = load_reg(r2);
1193 gen_helper_sske(cpu_env, tmp32_1, tmp);
1194 tcg_temp_free_i32(tmp32_1);
1195 tcg_temp_free_i64(tmp);
1196 break;
1197 case 0x34: /* STCH ? */
1198 /* Store Subchannel */
1199 check_privileged(s);
1200 gen_op_movi_cc(s, 3);
1201 break;
1202 case 0x46: /* STURA R1,R2 [RRE] */
1203 /* Store Using Real Address */
1204 check_privileged(s);
1205 r1 = (insn >> 4) & 0xf;
1206 r2 = insn & 0xf;
1207 tmp32_1 = load_reg32(r1);
1208 tmp = load_reg(r2);
1209 potential_page_fault(s);
1210 gen_helper_stura(cpu_env, tmp, tmp32_1);
1211 tcg_temp_free_i32(tmp32_1);
1212 tcg_temp_free_i64(tmp);
1213 break;
1214 case 0x50: /* CSP R1,R2 [RRE] */
1215 /* Compare And Swap And Purge */
1216 check_privileged(s);
1217 r1 = (insn >> 4) & 0xf;
1218 r2 = insn & 0xf;
1219 tmp32_1 = tcg_const_i32(r1);
1220 tmp32_2 = tcg_const_i32(r2);
1221 gen_helper_csp(cc_op, cpu_env, tmp32_1, tmp32_2);
1222 set_cc_static(s);
1223 tcg_temp_free_i32(tmp32_1);
1224 tcg_temp_free_i32(tmp32_2);
1225 break;
1226 case 0x5f: /* CHSC ? */
1227 /* Channel Subsystem Call */
1228 check_privileged(s);
1229 gen_op_movi_cc(s, 3);
1230 break;
1231 case 0x78: /* STCKE D2(B2) [S] */
1232 /* Store Clock Extended */
1233 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1234 tmp = get_address(s, 0, b2, d2);
1235 potential_page_fault(s);
1236 gen_helper_stcke(cc_op, cpu_env, tmp);
1237 set_cc_static(s);
1238 tcg_temp_free_i64(tmp);
1239 break;
1240 case 0x79: /* SACF D2(B2) [S] */
1241 /* Set Address Space Control Fast */
1242 check_privileged(s);
1243 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1244 tmp = get_address(s, 0, b2, d2);
1245 potential_page_fault(s);
1246 gen_helper_sacf(cpu_env, tmp);
1247 tcg_temp_free_i64(tmp);
1248 /* addressing mode has changed, so end the block */
1249 s->pc = s->next_pc;
1250 update_psw_addr(s);
1251 s->is_jmp = DISAS_JUMP;
1252 break;
1253 case 0x7d: /* STSI D2,(B2) [S] */
1254 check_privileged(s);
1255 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1256 tmp = get_address(s, 0, b2, d2);
1257 tmp32_1 = load_reg32(0);
1258 tmp32_2 = load_reg32(1);
1259 potential_page_fault(s);
1260 gen_helper_stsi(cc_op, cpu_env, tmp, tmp32_1, tmp32_2);
1261 set_cc_static(s);
1262 tcg_temp_free_i64(tmp);
1263 tcg_temp_free_i32(tmp32_1);
1264 tcg_temp_free_i32(tmp32_2);
1265 break;
1266 case 0xb1: /* STFL D2(B2) [S] */
1267 /* Store Facility List (CPU features) at 200 */
1268 check_privileged(s);
1269 tmp2 = tcg_const_i64(0xc0000000);
1270 tmp = tcg_const_i64(200);
1271 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1272 tcg_temp_free_i64(tmp2);
1273 tcg_temp_free_i64(tmp);
1274 break;
1275 case 0xb2: /* LPSWE D2(B2) [S] */
1276 /* Load PSW Extended */
1277 check_privileged(s);
1278 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1279 tmp = get_address(s, 0, b2, d2);
1280 tmp2 = tcg_temp_new_i64();
1281 tmp3 = tcg_temp_new_i64();
1282 tcg_gen_qemu_ld64(tmp2, tmp, get_mem_index(s));
1283 tcg_gen_addi_i64(tmp, tmp, 8);
1284 tcg_gen_qemu_ld64(tmp3, tmp, get_mem_index(s));
1285 gen_helper_load_psw(cpu_env, tmp2, tmp3);
1286 /* we need to keep cc_op intact */
1287 s->is_jmp = DISAS_JUMP;
1288 tcg_temp_free_i64(tmp);
1289 tcg_temp_free_i64(tmp2);
1290 tcg_temp_free_i64(tmp3);
1291 break;
1292 case 0x20: /* SERVC R1,R2 [RRE] */
1293 /* SCLP Service call (PV hypercall) */
1294 check_privileged(s);
1295 potential_page_fault(s);
1296 tmp32_1 = load_reg32(r2);
1297 tmp = load_reg(r1);
1298 gen_helper_servc(cc_op, cpu_env, tmp32_1, tmp);
1299 set_cc_static(s);
1300 tcg_temp_free_i32(tmp32_1);
1301 tcg_temp_free_i64(tmp);
1302 break;
1303 default:
1304 #endif
1305 LOG_DISAS("illegal b2 operation 0x%x\n", op);
1306 gen_illegal_opcode(s);
1307 #ifndef CONFIG_USER_ONLY
1308 break;
1309 }
1310 #endif
1311 }
1312
1313 static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
1314 {
1315 unsigned char opc;
1316 uint64_t insn;
1317 int op;
1318
1319 opc = cpu_ldub_code(env, s->pc);
1320 LOG_DISAS("opc 0x%x\n", opc);
1321
1322 switch (opc) {
1323 case 0xb2:
1324 insn = ld_code4(env, s->pc);
1325 op = (insn >> 16) & 0xff;
1326 disas_b2(env, s, op, insn);
1327 break;
1328 default:
1329 qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%x\n", opc);
1330 gen_illegal_opcode(s);
1331 break;
1332 }
1333 }
1334
1335 /* ====================================================================== */
1336 /* Define the insn format enumeration. */
1337 #define F0(N) FMT_##N,
1338 #define F1(N, X1) F0(N)
1339 #define F2(N, X1, X2) F0(N)
1340 #define F3(N, X1, X2, X3) F0(N)
1341 #define F4(N, X1, X2, X3, X4) F0(N)
1342 #define F5(N, X1, X2, X3, X4, X5) F0(N)
1343
1344 typedef enum {
1345 #include "insn-format.def"
1346 } DisasFormat;
1347
1348 #undef F0
1349 #undef F1
1350 #undef F2
1351 #undef F3
1352 #undef F4
1353 #undef F5
1354
1355 /* Define a structure to hold the decoded fields. We'll store each inside
1356 an array indexed by an enum. In order to conserve memory, we'll arrange
1357 for fields that do not exist at the same time to overlap, thus the "C"
1358 for compact. For checking purposes there is an "O" for original index
1359 as well that will be applied to availability bitmaps. */
1360
1361 enum DisasFieldIndexO {
1362 FLD_O_r1,
1363 FLD_O_r2,
1364 FLD_O_r3,
1365 FLD_O_m1,
1366 FLD_O_m3,
1367 FLD_O_m4,
1368 FLD_O_b1,
1369 FLD_O_b2,
1370 FLD_O_b4,
1371 FLD_O_d1,
1372 FLD_O_d2,
1373 FLD_O_d4,
1374 FLD_O_x2,
1375 FLD_O_l1,
1376 FLD_O_l2,
1377 FLD_O_i1,
1378 FLD_O_i2,
1379 FLD_O_i3,
1380 FLD_O_i4,
1381 FLD_O_i5
1382 };
1383
1384 enum DisasFieldIndexC {
1385 FLD_C_r1 = 0,
1386 FLD_C_m1 = 0,
1387 FLD_C_b1 = 0,
1388 FLD_C_i1 = 0,
1389
1390 FLD_C_r2 = 1,
1391 FLD_C_b2 = 1,
1392 FLD_C_i2 = 1,
1393
1394 FLD_C_r3 = 2,
1395 FLD_C_m3 = 2,
1396 FLD_C_i3 = 2,
1397
1398 FLD_C_m4 = 3,
1399 FLD_C_b4 = 3,
1400 FLD_C_i4 = 3,
1401 FLD_C_l1 = 3,
1402
1403 FLD_C_i5 = 4,
1404 FLD_C_d1 = 4,
1405
1406 FLD_C_d2 = 5,
1407
1408 FLD_C_d4 = 6,
1409 FLD_C_x2 = 6,
1410 FLD_C_l2 = 6,
1411
1412 NUM_C_FIELD = 7
1413 };
1414
1415 struct DisasFields {
1416 unsigned op:8;
1417 unsigned op2:8;
1418 unsigned presentC:16;
1419 unsigned int presentO;
1420 int c[NUM_C_FIELD];
1421 };
1422
1423 /* This is the way fields are to be accessed out of DisasFields. */
1424 #define have_field(S, F) have_field1((S), FLD_O_##F)
1425 #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
1426
1427 static bool have_field1(const DisasFields *f, enum DisasFieldIndexO c)
1428 {
1429 return (f->presentO >> c) & 1;
1430 }
1431
1432 static int get_field1(const DisasFields *f, enum DisasFieldIndexO o,
1433 enum DisasFieldIndexC c)
1434 {
1435 assert(have_field1(f, o));
1436 return f->c[c];
1437 }
1438
1439 /* Describe the layout of each field in each format. */
1440 typedef struct DisasField {
1441 unsigned int beg:8;
1442 unsigned int size:8;
1443 unsigned int type:2;
1444 unsigned int indexC:6;
1445 enum DisasFieldIndexO indexO:8;
1446 } DisasField;
1447
1448 typedef struct DisasFormatInfo {
1449 DisasField op[NUM_C_FIELD];
1450 } DisasFormatInfo;
1451
1452 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
1453 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
1454 #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1455 { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
1456 #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1457 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1458 { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
1459 #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1460 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1461 #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1462 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1463 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1464 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
1465 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
1466
1467 #define F0(N) { { } },
1468 #define F1(N, X1) { { X1 } },
1469 #define F2(N, X1, X2) { { X1, X2 } },
1470 #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
1471 #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
1472 #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
1473
1474 static const DisasFormatInfo format_info[] = {
1475 #include "insn-format.def"
1476 };
1477
1478 #undef F0
1479 #undef F1
1480 #undef F2
1481 #undef F3
1482 #undef F4
1483 #undef F5
1484 #undef R
1485 #undef M
1486 #undef BD
1487 #undef BXD
1488 #undef BDL
1489 #undef BXDL
1490 #undef I
1491 #undef L
1492
1493 /* Generally, we'll extract operands into this structures, operate upon
1494 them, and store them back. See the "in1", "in2", "prep", "wout" sets
1495 of routines below for more details. */
1496 typedef struct {
1497 bool g_out, g_out2, g_in1, g_in2;
1498 TCGv_i64 out, out2, in1, in2;
1499 TCGv_i64 addr1;
1500 } DisasOps;
1501
1502 /* Return values from translate_one, indicating the state of the TB. */
1503 typedef enum {
1504 /* Continue the TB. */
1505 NO_EXIT,
1506 /* We have emitted one or more goto_tb. No fixup required. */
1507 EXIT_GOTO_TB,
1508 /* We are not using a goto_tb (for whatever reason), but have updated
1509 the PC (for whatever reason), so there's no need to do it again on
1510 exiting the TB. */
1511 EXIT_PC_UPDATED,
1512 /* We are exiting the TB, but have neither emitted a goto_tb, nor
1513 updated the PC for the next instruction to be executed. */
1514 EXIT_PC_STALE,
1515 /* We are ending the TB with a noreturn function call, e.g. longjmp.
1516 No following code will be executed. */
1517 EXIT_NORETURN,
1518 } ExitStatus;
1519
1520 typedef enum DisasFacility {
1521 FAC_Z, /* zarch (default) */
1522 FAC_CASS, /* compare and swap and store */
1523 FAC_CASS2, /* compare and swap and store 2*/
1524 FAC_DFP, /* decimal floating point */
1525 FAC_DFPR, /* decimal floating point rounding */
1526 FAC_DO, /* distinct operands */
1527 FAC_EE, /* execute extensions */
1528 FAC_EI, /* extended immediate */
1529 FAC_FPE, /* floating point extension */
1530 FAC_FPSSH, /* floating point support sign handling */
1531 FAC_FPRGR, /* FPR-GR transfer */
1532 FAC_GIE, /* general instructions extension */
1533 FAC_HFP_MA, /* HFP multiply-and-add/subtract */
1534 FAC_HW, /* high-word */
1535 FAC_IEEEE_SIM, /* IEEE exception sumilation */
1536 FAC_LOC, /* load/store on condition */
1537 FAC_LD, /* long displacement */
1538 FAC_PC, /* population count */
1539 FAC_SCF, /* store clock fast */
1540 FAC_SFLE, /* store facility list extended */
1541 } DisasFacility;
1542
1543 struct DisasInsn {
1544 unsigned opc:16;
1545 DisasFormat fmt:6;
1546 DisasFacility fac:6;
1547
1548 const char *name;
1549
1550 void (*help_in1)(DisasContext *, DisasFields *, DisasOps *);
1551 void (*help_in2)(DisasContext *, DisasFields *, DisasOps *);
1552 void (*help_prep)(DisasContext *, DisasFields *, DisasOps *);
1553 void (*help_wout)(DisasContext *, DisasFields *, DisasOps *);
1554 void (*help_cout)(DisasContext *, DisasOps *);
1555 ExitStatus (*help_op)(DisasContext *, DisasOps *);
1556
1557 uint64_t data;
1558 };
1559
1560 /* ====================================================================== */
1561 /* Miscelaneous helpers, used by several operations. */
1562
1563 static void help_l2_shift(DisasContext *s, DisasFields *f,
1564 DisasOps *o, int mask)
1565 {
1566 int b2 = get_field(f, b2);
1567 int d2 = get_field(f, d2);
1568
1569 if (b2 == 0) {
1570 o->in2 = tcg_const_i64(d2 & mask);
1571 } else {
1572 o->in2 = get_address(s, 0, b2, d2);
1573 tcg_gen_andi_i64(o->in2, o->in2, mask);
1574 }
1575 }
1576
1577 static ExitStatus help_goto_direct(DisasContext *s, uint64_t dest)
1578 {
1579 if (dest == s->next_pc) {
1580 return NO_EXIT;
1581 }
1582 if (use_goto_tb(s, dest)) {
1583 gen_update_cc_op(s);
1584 tcg_gen_goto_tb(0);
1585 tcg_gen_movi_i64(psw_addr, dest);
1586 tcg_gen_exit_tb((tcg_target_long)s->tb);
1587 return EXIT_GOTO_TB;
1588 } else {
1589 tcg_gen_movi_i64(psw_addr, dest);
1590 return EXIT_PC_UPDATED;
1591 }
1592 }
1593
1594 static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
1595 bool is_imm, int imm, TCGv_i64 cdest)
1596 {
1597 ExitStatus ret;
1598 uint64_t dest = s->pc + 2 * imm;
1599 int lab;
1600
1601 /* Take care of the special cases first. */
1602 if (c->cond == TCG_COND_NEVER) {
1603 ret = NO_EXIT;
1604 goto egress;
1605 }
1606 if (is_imm) {
1607 if (dest == s->next_pc) {
1608 /* Branch to next. */
1609 ret = NO_EXIT;
1610 goto egress;
1611 }
1612 if (c->cond == TCG_COND_ALWAYS) {
1613 ret = help_goto_direct(s, dest);
1614 goto egress;
1615 }
1616 } else {
1617 if (TCGV_IS_UNUSED_I64(cdest)) {
1618 /* E.g. bcr %r0 -> no branch. */
1619 ret = NO_EXIT;
1620 goto egress;
1621 }
1622 if (c->cond == TCG_COND_ALWAYS) {
1623 tcg_gen_mov_i64(psw_addr, cdest);
1624 ret = EXIT_PC_UPDATED;
1625 goto egress;
1626 }
1627 }
1628
1629 if (use_goto_tb(s, s->next_pc)) {
1630 if (is_imm && use_goto_tb(s, dest)) {
1631 /* Both exits can use goto_tb. */
1632 gen_update_cc_op(s);
1633
1634 lab = gen_new_label();
1635 if (c->is_64) {
1636 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1637 } else {
1638 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1639 }
1640
1641 /* Branch not taken. */
1642 tcg_gen_goto_tb(0);
1643 tcg_gen_movi_i64(psw_addr, s->next_pc);
1644 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
1645
1646 /* Branch taken. */
1647 gen_set_label(lab);
1648 tcg_gen_goto_tb(1);
1649 tcg_gen_movi_i64(psw_addr, dest);
1650 tcg_gen_exit_tb((tcg_target_long)s->tb + 1);
1651
1652 ret = EXIT_GOTO_TB;
1653 } else {
1654 /* Fallthru can use goto_tb, but taken branch cannot. */
1655 /* Store taken branch destination before the brcond. This
1656 avoids having to allocate a new local temp to hold it.
1657 We'll overwrite this in the not taken case anyway. */
1658 if (!is_imm) {
1659 tcg_gen_mov_i64(psw_addr, cdest);
1660 }
1661
1662 lab = gen_new_label();
1663 if (c->is_64) {
1664 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1665 } else {
1666 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1667 }
1668
1669 /* Branch not taken. */
1670 gen_update_cc_op(s);
1671 tcg_gen_goto_tb(0);
1672 tcg_gen_movi_i64(psw_addr, s->next_pc);
1673 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
1674
1675 gen_set_label(lab);
1676 if (is_imm) {
1677 tcg_gen_movi_i64(psw_addr, dest);
1678 }
1679 ret = EXIT_PC_UPDATED;
1680 }
1681 } else {
1682 /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
1683 Most commonly we're single-stepping or some other condition that
1684 disables all use of goto_tb. Just update the PC and exit. */
1685
1686 TCGv_i64 next = tcg_const_i64(s->next_pc);
1687 if (is_imm) {
1688 cdest = tcg_const_i64(dest);
1689 }
1690
1691 if (c->is_64) {
1692 tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b,
1693 cdest, next);
1694 } else {
1695 TCGv_i32 t0 = tcg_temp_new_i32();
1696 TCGv_i64 t1 = tcg_temp_new_i64();
1697 TCGv_i64 z = tcg_const_i64(0);
1698 tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b);
1699 tcg_gen_extu_i32_i64(t1, t0);
1700 tcg_temp_free_i32(t0);
1701 tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next);
1702 tcg_temp_free_i64(t1);
1703 tcg_temp_free_i64(z);
1704 }
1705
1706 if (is_imm) {
1707 tcg_temp_free_i64(cdest);
1708 }
1709 tcg_temp_free_i64(next);
1710
1711 ret = EXIT_PC_UPDATED;
1712 }
1713
1714 egress:
1715 free_compare(c);
1716 return ret;
1717 }
1718
1719 /* ====================================================================== */
1720 /* The operations. These perform the bulk of the work for any insn,
1721 usually after the operands have been loaded and output initialized. */
1722
1723 static ExitStatus op_abs(DisasContext *s, DisasOps *o)
1724 {
1725 gen_helper_abs_i64(o->out, o->in2);
1726 return NO_EXIT;
1727 }
1728
1729 static ExitStatus op_absf32(DisasContext *s, DisasOps *o)
1730 {
1731 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffull);
1732 return NO_EXIT;
1733 }
1734
1735 static ExitStatus op_absf64(DisasContext *s, DisasOps *o)
1736 {
1737 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull);
1738 return NO_EXIT;
1739 }
1740
1741 static ExitStatus op_absf128(DisasContext *s, DisasOps *o)
1742 {
1743 tcg_gen_andi_i64(o->out, o->in1, 0x7fffffffffffffffull);
1744 tcg_gen_mov_i64(o->out2, o->in2);
1745 return NO_EXIT;
1746 }
1747
1748 static ExitStatus op_add(DisasContext *s, DisasOps *o)
1749 {
1750 tcg_gen_add_i64(o->out, o->in1, o->in2);
1751 return NO_EXIT;
1752 }
1753
1754 static ExitStatus op_addc(DisasContext *s, DisasOps *o)
1755 {
1756 TCGv_i64 cc;
1757
1758 tcg_gen_add_i64(o->out, o->in1, o->in2);
1759
1760 /* XXX possible optimization point */
1761 gen_op_calc_cc(s);
1762 cc = tcg_temp_new_i64();
1763 tcg_gen_extu_i32_i64(cc, cc_op);
1764 tcg_gen_shri_i64(cc, cc, 1);
1765
1766 tcg_gen_add_i64(o->out, o->out, cc);
1767 tcg_temp_free_i64(cc);
1768 return NO_EXIT;
1769 }
1770
1771 static ExitStatus op_aeb(DisasContext *s, DisasOps *o)
1772 {
1773 gen_helper_aeb(o->out, cpu_env, o->in1, o->in2);
1774 return NO_EXIT;
1775 }
1776
1777 static ExitStatus op_adb(DisasContext *s, DisasOps *o)
1778 {
1779 gen_helper_adb(o->out, cpu_env, o->in1, o->in2);
1780 return NO_EXIT;
1781 }
1782
1783 static ExitStatus op_axb(DisasContext *s, DisasOps *o)
1784 {
1785 gen_helper_axb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
1786 return_low128(o->out2);
1787 return NO_EXIT;
1788 }
1789
1790 static ExitStatus op_and(DisasContext *s, DisasOps *o)
1791 {
1792 tcg_gen_and_i64(o->out, o->in1, o->in2);
1793 return NO_EXIT;
1794 }
1795
1796 static ExitStatus op_andi(DisasContext *s, DisasOps *o)
1797 {
1798 int shift = s->insn->data & 0xff;
1799 int size = s->insn->data >> 8;
1800 uint64_t mask = ((1ull << size) - 1) << shift;
1801
1802 assert(!o->g_in2);
1803 tcg_gen_shli_i64(o->in2, o->in2, shift);
1804 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
1805 tcg_gen_and_i64(o->out, o->in1, o->in2);
1806
1807 /* Produce the CC from only the bits manipulated. */
1808 tcg_gen_andi_i64(cc_dst, o->out, mask);
1809 set_cc_nz_u64(s, cc_dst);
1810 return NO_EXIT;
1811 }
1812
1813 static ExitStatus op_bas(DisasContext *s, DisasOps *o)
1814 {
1815 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1816 if (!TCGV_IS_UNUSED_I64(o->in2)) {
1817 tcg_gen_mov_i64(psw_addr, o->in2);
1818 return EXIT_PC_UPDATED;
1819 } else {
1820 return NO_EXIT;
1821 }
1822 }
1823
1824 static ExitStatus op_basi(DisasContext *s, DisasOps *o)
1825 {
1826 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1827 return help_goto_direct(s, s->pc + 2 * get_field(s->fields, i2));
1828 }
1829
1830 static ExitStatus op_bc(DisasContext *s, DisasOps *o)
1831 {
1832 int m1 = get_field(s->fields, m1);
1833 bool is_imm = have_field(s->fields, i2);
1834 int imm = is_imm ? get_field(s->fields, i2) : 0;
1835 DisasCompare c;
1836
1837 disas_jcc(s, &c, m1);
1838 return help_branch(s, &c, is_imm, imm, o->in2);
1839 }
1840
1841 static ExitStatus op_bct32(DisasContext *s, DisasOps *o)
1842 {
1843 int r1 = get_field(s->fields, r1);
1844 bool is_imm = have_field(s->fields, i2);
1845 int imm = is_imm ? get_field(s->fields, i2) : 0;
1846 DisasCompare c;
1847 TCGv_i64 t;
1848
1849 c.cond = TCG_COND_NE;
1850 c.is_64 = false;
1851 c.g1 = false;
1852 c.g2 = false;
1853
1854 t = tcg_temp_new_i64();
1855 tcg_gen_subi_i64(t, regs[r1], 1);
1856 store_reg32_i64(r1, t);
1857 c.u.s32.a = tcg_temp_new_i32();
1858 c.u.s32.b = tcg_const_i32(0);
1859 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
1860 tcg_temp_free_i64(t);
1861
1862 return help_branch(s, &c, is_imm, imm, o->in2);
1863 }
1864
1865 static ExitStatus op_bct64(DisasContext *s, DisasOps *o)
1866 {
1867 int r1 = get_field(s->fields, r1);
1868 bool is_imm = have_field(s->fields, i2);
1869 int imm = is_imm ? get_field(s->fields, i2) : 0;
1870 DisasCompare c;
1871
1872 c.cond = TCG_COND_NE;
1873 c.is_64 = true;
1874 c.g1 = true;
1875 c.g2 = false;
1876
1877 tcg_gen_subi_i64(regs[r1], regs[r1], 1);
1878 c.u.s64.a = regs[r1];
1879 c.u.s64.b = tcg_const_i64(0);
1880
1881 return help_branch(s, &c, is_imm, imm, o->in2);
1882 }
1883
1884 static ExitStatus op_ceb(DisasContext *s, DisasOps *o)
1885 {
1886 gen_helper_ceb(cc_op, cpu_env, o->in1, o->in2);
1887 set_cc_static(s);
1888 return NO_EXIT;
1889 }
1890
1891 static ExitStatus op_cdb(DisasContext *s, DisasOps *o)
1892 {
1893 gen_helper_cdb(cc_op, cpu_env, o->in1, o->in2);
1894 set_cc_static(s);
1895 return NO_EXIT;
1896 }
1897
1898 static ExitStatus op_cxb(DisasContext *s, DisasOps *o)
1899 {
1900 gen_helper_cxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2);
1901 set_cc_static(s);
1902 return NO_EXIT;
1903 }
1904
1905 static ExitStatus op_cfeb(DisasContext *s, DisasOps *o)
1906 {
1907 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1908 gen_helper_cfeb(o->out, cpu_env, o->in2, m3);
1909 tcg_temp_free_i32(m3);
1910 gen_set_cc_nz_f32(s, o->in2);
1911 return NO_EXIT;
1912 }
1913
1914 static ExitStatus op_cfdb(DisasContext *s, DisasOps *o)
1915 {
1916 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1917 gen_helper_cfdb(o->out, cpu_env, o->in2, m3);
1918 tcg_temp_free_i32(m3);
1919 gen_set_cc_nz_f64(s, o->in2);
1920 return NO_EXIT;
1921 }
1922
1923 static ExitStatus op_cfxb(DisasContext *s, DisasOps *o)
1924 {
1925 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1926 gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m3);
1927 tcg_temp_free_i32(m3);
1928 gen_set_cc_nz_f128(s, o->in1, o->in2);
1929 return NO_EXIT;
1930 }
1931
1932 static ExitStatus op_cgeb(DisasContext *s, DisasOps *o)
1933 {
1934 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1935 gen_helper_cgeb(o->out, cpu_env, o->in2, m3);
1936 tcg_temp_free_i32(m3);
1937 gen_set_cc_nz_f32(s, o->in2);
1938 return NO_EXIT;
1939 }
1940
1941 static ExitStatus op_cgdb(DisasContext *s, DisasOps *o)
1942 {
1943 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1944 gen_helper_cgdb(o->out, cpu_env, o->in2, m3);
1945 tcg_temp_free_i32(m3);
1946 gen_set_cc_nz_f64(s, o->in2);
1947 return NO_EXIT;
1948 }
1949
1950 static ExitStatus op_cgxb(DisasContext *s, DisasOps *o)
1951 {
1952 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1953 gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m3);
1954 tcg_temp_free_i32(m3);
1955 gen_set_cc_nz_f128(s, o->in1, o->in2);
1956 return NO_EXIT;
1957 }
1958
1959 static ExitStatus op_cegb(DisasContext *s, DisasOps *o)
1960 {
1961 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1962 gen_helper_cegb(o->out, cpu_env, o->in2, m3);
1963 tcg_temp_free_i32(m3);
1964 return NO_EXIT;
1965 }
1966
1967 static ExitStatus op_cdgb(DisasContext *s, DisasOps *o)
1968 {
1969 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1970 gen_helper_cdgb(o->out, cpu_env, o->in2, m3);
1971 tcg_temp_free_i32(m3);
1972 return NO_EXIT;
1973 }
1974
1975 static ExitStatus op_cxgb(DisasContext *s, DisasOps *o)
1976 {
1977 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1978 gen_helper_cxgb(o->out, cpu_env, o->in2, m3);
1979 tcg_temp_free_i32(m3);
1980 return_low128(o->out2);
1981 return NO_EXIT;
1982 }
1983
1984 static ExitStatus op_cksm(DisasContext *s, DisasOps *o)
1985 {
1986 int r2 = get_field(s->fields, r2);
1987 TCGv_i64 len = tcg_temp_new_i64();
1988
1989 potential_page_fault(s);
1990 gen_helper_cksm(len, cpu_env, o->in1, o->in2, regs[r2 + 1]);
1991 set_cc_static(s);
1992 return_low128(o->out);
1993
1994 tcg_gen_add_i64(regs[r2], regs[r2], len);
1995 tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len);
1996 tcg_temp_free_i64(len);
1997
1998 return NO_EXIT;
1999 }
2000
2001 static ExitStatus op_clc(DisasContext *s, DisasOps *o)
2002 {
2003 int l = get_field(s->fields, l1);
2004 TCGv_i32 vl;
2005
2006 switch (l + 1) {
2007 case 1:
2008 tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s));
2009 tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s));
2010 break;
2011 case 2:
2012 tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s));
2013 tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s));
2014 break;
2015 case 4:
2016 tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s));
2017 tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s));
2018 break;
2019 case 8:
2020 tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s));
2021 tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
2022 break;
2023 default:
2024 potential_page_fault(s);
2025 vl = tcg_const_i32(l);
2026 gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
2027 tcg_temp_free_i32(vl);
2028 set_cc_static(s);
2029 return NO_EXIT;
2030 }
2031 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
2032 return NO_EXIT;
2033 }
2034
2035 static ExitStatus op_clcle(DisasContext *s, DisasOps *o)
2036 {
2037 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2038 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2039 potential_page_fault(s);
2040 gen_helper_clcle(cc_op, cpu_env, r1, o->in2, r3);
2041 tcg_temp_free_i32(r1);
2042 tcg_temp_free_i32(r3);
2043 set_cc_static(s);
2044 return NO_EXIT;
2045 }
2046
2047 static ExitStatus op_clm(DisasContext *s, DisasOps *o)
2048 {
2049 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
2050 TCGv_i32 t1 = tcg_temp_new_i32();
2051 tcg_gen_trunc_i64_i32(t1, o->in1);
2052 potential_page_fault(s);
2053 gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2);
2054 set_cc_static(s);
2055 tcg_temp_free_i32(t1);
2056 tcg_temp_free_i32(m3);
2057 return NO_EXIT;
2058 }
2059
2060 static ExitStatus op_clst(DisasContext *s, DisasOps *o)
2061 {
2062 potential_page_fault(s);
2063 gen_helper_clst(o->in1, cpu_env, regs[0], o->in1, o->in2);
2064 set_cc_static(s);
2065 return_low128(o->in2);
2066 return NO_EXIT;
2067 }
2068
2069 static ExitStatus op_cs(DisasContext *s, DisasOps *o)
2070 {
2071 int r3 = get_field(s->fields, r3);
2072 potential_page_fault(s);
2073 gen_helper_cs(o->out, cpu_env, o->in1, o->in2, regs[r3]);
2074 set_cc_static(s);
2075 return NO_EXIT;
2076 }
2077
2078 static ExitStatus op_csg(DisasContext *s, DisasOps *o)
2079 {
2080 int r3 = get_field(s->fields, r3);
2081 potential_page_fault(s);
2082 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, regs[r3]);
2083 set_cc_static(s);
2084 return NO_EXIT;
2085 }
2086
2087 static ExitStatus op_cds(DisasContext *s, DisasOps *o)
2088 {
2089 int r3 = get_field(s->fields, r3);
2090 TCGv_i64 in3 = tcg_temp_new_i64();
2091 tcg_gen_deposit_i64(in3, regs[r3 + 1], regs[r3], 32, 32);
2092 potential_page_fault(s);
2093 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, in3);
2094 tcg_temp_free_i64(in3);
2095 set_cc_static(s);
2096 return NO_EXIT;
2097 }
2098
2099 static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
2100 {
2101 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2102 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2103 potential_page_fault(s);
2104 /* XXX rewrite in tcg */
2105 gen_helper_cdsg(cc_op, cpu_env, r1, o->in2, r3);
2106 set_cc_static(s);
2107 return NO_EXIT;
2108 }
2109
2110 static ExitStatus op_cvd(DisasContext *s, DisasOps *o)
2111 {
2112 TCGv_i64 t1 = tcg_temp_new_i64();
2113 TCGv_i32 t2 = tcg_temp_new_i32();
2114 tcg_gen_trunc_i64_i32(t2, o->in1);
2115 gen_helper_cvd(t1, t2);
2116 tcg_temp_free_i32(t2);
2117 tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
2118 tcg_temp_free_i64(t1);
2119 return NO_EXIT;
2120 }
2121
2122 #ifndef CONFIG_USER_ONLY
2123 static ExitStatus op_diag(DisasContext *s, DisasOps *o)
2124 {
2125 TCGv_i32 tmp;
2126
2127 check_privileged(s);
2128 potential_page_fault(s);
2129
2130 /* We pretend the format is RX_a so that D2 is the field we want. */
2131 tmp = tcg_const_i32(get_field(s->fields, d2) & 0xfff);
2132 gen_helper_diag(regs[2], cpu_env, tmp, regs[2], regs[1]);
2133 tcg_temp_free_i32(tmp);
2134 return NO_EXIT;
2135 }
2136 #endif
2137
2138 static ExitStatus op_divs32(DisasContext *s, DisasOps *o)
2139 {
2140 gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2);
2141 return_low128(o->out);
2142 return NO_EXIT;
2143 }
2144
2145 static ExitStatus op_divu32(DisasContext *s, DisasOps *o)
2146 {
2147 gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2);
2148 return_low128(o->out);
2149 return NO_EXIT;
2150 }
2151
2152 static ExitStatus op_divs64(DisasContext *s, DisasOps *o)
2153 {
2154 gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2);
2155 return_low128(o->out);
2156 return NO_EXIT;
2157 }
2158
2159 static ExitStatus op_divu64(DisasContext *s, DisasOps *o)
2160 {
2161 gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2);
2162 return_low128(o->out);
2163 return NO_EXIT;
2164 }
2165
2166 static ExitStatus op_deb(DisasContext *s, DisasOps *o)
2167 {
2168 gen_helper_deb(o->out, cpu_env, o->in1, o->in2);
2169 return NO_EXIT;
2170 }
2171
2172 static ExitStatus op_ddb(DisasContext *s, DisasOps *o)
2173 {
2174 gen_helper_ddb(o->out, cpu_env, o->in1, o->in2);
2175 return NO_EXIT;
2176 }
2177
2178 static ExitStatus op_dxb(DisasContext *s, DisasOps *o)
2179 {
2180 gen_helper_dxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2181 return_low128(o->out2);
2182 return NO_EXIT;
2183 }
2184
2185 static ExitStatus op_ear(DisasContext *s, DisasOps *o)
2186 {
2187 int r2 = get_field(s->fields, r2);
2188 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, aregs[r2]));
2189 return NO_EXIT;
2190 }
2191
2192 static ExitStatus op_efpc(DisasContext *s, DisasOps *o)
2193 {
2194 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, fpc));
2195 return NO_EXIT;
2196 }
2197
2198 static ExitStatus op_ex(DisasContext *s, DisasOps *o)
2199 {
2200 /* ??? Perhaps a better way to implement EXECUTE is to set a bit in
2201 tb->flags, (ab)use the tb->cs_base field as the address of
2202 the template in memory, and grab 8 bits of tb->flags/cflags for
2203 the contents of the register. We would then recognize all this
2204 in gen_intermediate_code_internal, generating code for exactly
2205 one instruction. This new TB then gets executed normally.
2206
2207 On the other hand, this seems to be mostly used for modifying
2208 MVC inside of memcpy, which needs a helper call anyway. So
2209 perhaps this doesn't bear thinking about any further. */
2210
2211 TCGv_i64 tmp;
2212
2213 update_psw_addr(s);
2214 gen_op_calc_cc(s);
2215
2216 tmp = tcg_const_i64(s->next_pc);
2217 gen_helper_ex(cc_op, cpu_env, cc_op, o->in1, o->in2, tmp);
2218 tcg_temp_free_i64(tmp);
2219
2220 set_cc_static(s);
2221 return NO_EXIT;
2222 }
2223
2224 static ExitStatus op_flogr(DisasContext *s, DisasOps *o)
2225 {
2226 /* We'll use the original input for cc computation, since we get to
2227 compare that against 0, which ought to be better than comparing
2228 the real output against 64. It also lets cc_dst be a convenient
2229 temporary during our computation. */
2230 gen_op_update1_cc_i64(s, CC_OP_FLOGR, o->in2);
2231
2232 /* R1 = IN ? CLZ(IN) : 64. */
2233 gen_helper_clz(o->out, o->in2);
2234
2235 /* R1+1 = IN & ~(found bit). Note that we may attempt to shift this
2236 value by 64, which is undefined. But since the shift is 64 iff the
2237 input is zero, we still get the correct result after and'ing. */
2238 tcg_gen_movi_i64(o->out2, 0x8000000000000000ull);
2239 tcg_gen_shr_i64(o->out2, o->out2, o->out);
2240 tcg_gen_andc_i64(o->out2, cc_dst, o->out2);
2241 return NO_EXIT;
2242 }
2243
2244 static ExitStatus op_icm(DisasContext *s, DisasOps *o)
2245 {
2246 int m3 = get_field(s->fields, m3);
2247 int pos, len, base = s->insn->data;
2248 TCGv_i64 tmp = tcg_temp_new_i64();
2249 uint64_t ccm;
2250
2251 switch (m3) {
2252 case 0xf:
2253 /* Effectively a 32-bit load. */
2254 tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
2255 len = 32;
2256 goto one_insert;
2257
2258 case 0xc:
2259 case 0x6:
2260 case 0x3:
2261 /* Effectively a 16-bit load. */
2262 tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
2263 len = 16;
2264 goto one_insert;
2265
2266 case 0x8:
2267 case 0x4:
2268 case 0x2:
2269 case 0x1:
2270 /* Effectively an 8-bit load. */
2271 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2272 len = 8;
2273 goto one_insert;
2274
2275 one_insert:
2276 pos = base + ctz32(m3) * 8;
2277 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len);
2278 ccm = ((1ull << len) - 1) << pos;
2279 break;
2280
2281 default:
2282 /* This is going to be a sequence of loads and inserts. */
2283 pos = base + 32 - 8;
2284 ccm = 0;
2285 while (m3) {
2286 if (m3 & 0x8) {
2287 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2288 tcg_gen_addi_i64(o->in2, o->in2, 1);
2289 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
2290 ccm |= 0xff << pos;
2291 }
2292 m3 = (m3 << 1) & 0xf;
2293 pos -= 8;
2294 }
2295 break;
2296 }
2297
2298 tcg_gen_movi_i64(tmp, ccm);
2299 gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out);
2300 tcg_temp_free_i64(tmp);
2301 return NO_EXIT;
2302 }
2303
2304 static ExitStatus op_insi(DisasContext *s, DisasOps *o)
2305 {
2306 int shift = s->insn->data & 0xff;
2307 int size = s->insn->data >> 8;
2308 tcg_gen_deposit_i64(o->out, o->in1, o->in2, shift, size);
2309 return NO_EXIT;
2310 }
2311
2312 static ExitStatus op_ipm(DisasContext *s, DisasOps *o)
2313 {
2314 TCGv_i64 t1;
2315
2316 gen_op_calc_cc(s);
2317 tcg_gen_andi_i64(o->out, o->out, ~0xff000000ull);
2318
2319 t1 = tcg_temp_new_i64();
2320 tcg_gen_shli_i64(t1, psw_mask, 20);
2321 tcg_gen_shri_i64(t1, t1, 36);
2322 tcg_gen_or_i64(o->out, o->out, t1);
2323
2324 tcg_gen_extu_i32_i64(t1, cc_op);
2325 tcg_gen_shli_i64(t1, t1, 28);
2326 tcg_gen_or_i64(o->out, o->out, t1);
2327 tcg_temp_free_i64(t1);
2328 return NO_EXIT;
2329 }
2330
2331 static ExitStatus op_ldeb(DisasContext *s, DisasOps *o)
2332 {
2333 gen_helper_ldeb(o->out, cpu_env, o->in2);
2334 return NO_EXIT;
2335 }
2336
2337 static ExitStatus op_ledb(DisasContext *s, DisasOps *o)
2338 {
2339 gen_helper_ledb(o->out, cpu_env, o->in2);
2340 return NO_EXIT;
2341 }
2342
2343 static ExitStatus op_ldxb(DisasContext *s, DisasOps *o)
2344 {
2345 gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2);
2346 return NO_EXIT;
2347 }
2348
2349 static ExitStatus op_lexb(DisasContext *s, DisasOps *o)
2350 {
2351 gen_helper_lexb(o->out, cpu_env, o->in1, o->in2);
2352 return NO_EXIT;
2353 }
2354
2355 static ExitStatus op_lxdb(DisasContext *s, DisasOps *o)
2356 {
2357 gen_helper_lxdb(o->out, cpu_env, o->in2);
2358 return_low128(o->out2);
2359 return NO_EXIT;
2360 }
2361
2362 static ExitStatus op_lxeb(DisasContext *s, DisasOps *o)
2363 {
2364 gen_helper_lxeb(o->out, cpu_env, o->in2);
2365 return_low128(o->out2);
2366 return NO_EXIT;
2367 }
2368
2369 static ExitStatus op_llgt(DisasContext *s, DisasOps *o)
2370 {
2371 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffff);
2372 return NO_EXIT;
2373 }
2374
2375 static ExitStatus op_ld8s(DisasContext *s, DisasOps *o)
2376 {
2377 tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
2378 return NO_EXIT;
2379 }
2380
2381 static ExitStatus op_ld8u(DisasContext *s, DisasOps *o)
2382 {
2383 tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
2384 return NO_EXIT;
2385 }
2386
2387 static ExitStatus op_ld16s(DisasContext *s, DisasOps *o)
2388 {
2389 tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
2390 return NO_EXIT;
2391 }
2392
2393 static ExitStatus op_ld16u(DisasContext *s, DisasOps *o)
2394 {
2395 tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
2396 return NO_EXIT;
2397 }
2398
2399 static ExitStatus op_ld32s(DisasContext *s, DisasOps *o)
2400 {
2401 tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s));
2402 return NO_EXIT;
2403 }
2404
2405 static ExitStatus op_ld32u(DisasContext *s, DisasOps *o)
2406 {
2407 tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
2408 return NO_EXIT;
2409 }
2410
2411 static ExitStatus op_ld64(DisasContext *s, DisasOps *o)
2412 {
2413 tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
2414 return NO_EXIT;
2415 }
2416
2417 #ifndef CONFIG_USER_ONLY
2418 static ExitStatus op_lctl(DisasContext *s, DisasOps *o)
2419 {
2420 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2421 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2422 check_privileged(s);
2423 potential_page_fault(s);
2424 gen_helper_lctl(cpu_env, r1, o->in2, r3);
2425 tcg_temp_free_i32(r1);
2426 tcg_temp_free_i32(r3);
2427 return NO_EXIT;
2428 }
2429
2430 static ExitStatus op_lctlg(DisasContext *s, DisasOps *o)
2431 {
2432 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2433 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2434 check_privileged(s);
2435 potential_page_fault(s);
2436 gen_helper_lctlg(cpu_env, r1, o->in2, r3);
2437 tcg_temp_free_i32(r1);
2438 tcg_temp_free_i32(r3);
2439 return NO_EXIT;
2440 }
2441 static ExitStatus op_lra(DisasContext *s, DisasOps *o)
2442 {
2443 check_privileged(s);
2444 potential_page_fault(s);
2445 gen_helper_lra(o->out, cpu_env, o->in2);
2446 set_cc_static(s);
2447 return NO_EXIT;
2448 }
2449
2450 static ExitStatus op_lpsw(DisasContext *s, DisasOps *o)
2451 {
2452 TCGv_i64 t1, t2;
2453
2454 check_privileged(s);
2455
2456 t1 = tcg_temp_new_i64();
2457 t2 = tcg_temp_new_i64();
2458 tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
2459 tcg_gen_addi_i64(o->in2, o->in2, 4);
2460 tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s));
2461 /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
2462 tcg_gen_shli_i64(t1, t1, 32);
2463 gen_helper_load_psw(cpu_env, t1, t2);
2464 tcg_temp_free_i64(t1);
2465 tcg_temp_free_i64(t2);
2466 return EXIT_NORETURN;
2467 }
2468 #endif
2469
2470 static ExitStatus op_lam(DisasContext *s, DisasOps *o)
2471 {
2472 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2473 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2474 potential_page_fault(s);
2475 gen_helper_lam(cpu_env, r1, o->in2, r3);
2476 tcg_temp_free_i32(r1);
2477 tcg_temp_free_i32(r3);
2478 return NO_EXIT;
2479 }
2480
2481 static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
2482 {
2483 int r1 = get_field(s->fields, r1);
2484 int r3 = get_field(s->fields, r3);
2485 TCGv_i64 t = tcg_temp_new_i64();
2486 TCGv_i64 t4 = tcg_const_i64(4);
2487
2488 while (1) {
2489 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2490 store_reg32_i64(r1, t);
2491 if (r1 == r3) {
2492 break;
2493 }
2494 tcg_gen_add_i64(o->in2, o->in2, t4);
2495 r1 = (r1 + 1) & 15;
2496 }
2497
2498 tcg_temp_free_i64(t);
2499 tcg_temp_free_i64(t4);
2500 return NO_EXIT;
2501 }
2502
2503 static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
2504 {
2505 int r1 = get_field(s->fields, r1);
2506 int r3 = get_field(s->fields, r3);
2507 TCGv_i64 t = tcg_temp_new_i64();
2508 TCGv_i64 t4 = tcg_const_i64(4);
2509
2510 while (1) {
2511 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2512 store_reg32h_i64(r1, t);
2513 if (r1 == r3) {
2514 break;
2515 }
2516 tcg_gen_add_i64(o->in2, o->in2, t4);
2517 r1 = (r1 + 1) & 15;
2518 }
2519
2520 tcg_temp_free_i64(t);
2521 tcg_temp_free_i64(t4);
2522 return NO_EXIT;
2523 }
2524
2525 static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
2526 {
2527 int r1 = get_field(s->fields, r1);
2528 int r3 = get_field(s->fields, r3);
2529 TCGv_i64 t8 = tcg_const_i64(8);
2530
2531 while (1) {
2532 tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
2533 if (r1 == r3) {
2534 break;
2535 }
2536 tcg_gen_add_i64(o->in2, o->in2, t8);
2537 r1 = (r1 + 1) & 15;
2538 }
2539
2540 tcg_temp_free_i64(t8);
2541 return NO_EXIT;
2542 }
2543
2544 static ExitStatus op_mov2(DisasContext *s, DisasOps *o)
2545 {
2546 o->out = o->in2;
2547 o->g_out = o->g_in2;
2548 TCGV_UNUSED_I64(o->in2);
2549 o->g_in2 = false;
2550 return NO_EXIT;
2551 }
2552
2553 static ExitStatus op_movx(DisasContext *s, DisasOps *o)
2554 {
2555 o->out = o->in1;
2556 o->out2 = o->in2;
2557 o->g_out = o->g_in1;
2558 o->g_out2 = o->g_in2;
2559 TCGV_UNUSED_I64(o->in1);
2560 TCGV_UNUSED_I64(o->in2);
2561 o->g_in1 = o->g_in2 = false;
2562 return NO_EXIT;
2563 }
2564
2565 static ExitStatus op_mvc(DisasContext *s, DisasOps *o)
2566 {
2567 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2568 potential_page_fault(s);
2569 gen_helper_mvc(cpu_env, l, o->addr1, o->in2);
2570 tcg_temp_free_i32(l);
2571 return NO_EXIT;
2572 }
2573
2574 static ExitStatus op_mvcl(DisasContext *s, DisasOps *o)
2575 {
2576 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2577 TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
2578 potential_page_fault(s);
2579 gen_helper_mvcl(cc_op, cpu_env, r1, r2);
2580 tcg_temp_free_i32(r1);
2581 tcg_temp_free_i32(r2);
2582 set_cc_static(s);
2583 return NO_EXIT;
2584 }
2585
2586 static ExitStatus op_mvcle(DisasContext *s, DisasOps *o)
2587 {
2588 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2589 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2590 potential_page_fault(s);
2591 gen_helper_mvcle(cc_op, cpu_env, r1, o->in2, r3);
2592 tcg_temp_free_i32(r1);
2593 tcg_temp_free_i32(r3);
2594 set_cc_static(s);
2595 return NO_EXIT;
2596 }
2597
2598 #ifndef CONFIG_USER_ONLY
2599 static ExitStatus op_mvcp(DisasContext *s, DisasOps *o)
2600 {
2601 int r1 = get_field(s->fields, l1);
2602 check_privileged(s);
2603 potential_page_fault(s);
2604 gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2605 set_cc_static(s);
2606 return NO_EXIT;
2607 }
2608
2609 static ExitStatus op_mvcs(DisasContext *s, DisasOps *o)
2610 {
2611 int r1 = get_field(s->fields, l1);
2612 check_privileged(s);
2613 potential_page_fault(s);
2614 gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2615 set_cc_static(s);
2616 return NO_EXIT;
2617 }
2618 #endif
2619
2620 static ExitStatus op_mvpg(DisasContext *s, DisasOps *o)
2621 {
2622 potential_page_fault(s);
2623 gen_helper_mvpg(cpu_env, regs[0], o->in1, o->in2);
2624 set_cc_static(s);
2625 return NO_EXIT;
2626 }
2627
2628 static ExitStatus op_mvst(DisasContext *s, DisasOps *o)
2629 {
2630 potential_page_fault(s);
2631 gen_helper_mvst(o->in1, cpu_env, regs[0], o->in1, o->in2);
2632 set_cc_static(s);
2633 return_low128(o->in2);
2634 return NO_EXIT;
2635 }
2636
2637 static ExitStatus op_mul(DisasContext *s, DisasOps *o)
2638 {
2639 tcg_gen_mul_i64(o->out, o->in1, o->in2);
2640 return NO_EXIT;
2641 }
2642
2643 static ExitStatus op_mul128(DisasContext *s, DisasOps *o)
2644 {
2645 gen_helper_mul128(o->out, cpu_env, o->in1, o->in2);
2646 return_low128(o->out2);
2647 return NO_EXIT;
2648 }
2649
2650 static ExitStatus op_meeb(DisasContext *s, DisasOps *o)
2651 {
2652 gen_helper_meeb(o->out, cpu_env, o->in1, o->in2);
2653 return NO_EXIT;
2654 }
2655
2656 static ExitStatus op_mdeb(DisasContext *s, DisasOps *o)
2657 {
2658 gen_helper_mdeb(o->out, cpu_env, o->in1, o->in2);
2659 return NO_EXIT;
2660 }
2661
2662 static ExitStatus op_mdb(DisasContext *s, DisasOps *o)
2663 {
2664 gen_helper_mdb(o->out, cpu_env, o->in1, o->in2);
2665 return NO_EXIT;
2666 }
2667
2668 static ExitStatus op_mxb(DisasContext *s, DisasOps *o)
2669 {
2670 gen_helper_mxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2671 return_low128(o->out2);
2672 return NO_EXIT;
2673 }
2674
2675 static ExitStatus op_mxdb(DisasContext *s, DisasOps *o)
2676 {
2677 gen_helper_mxdb(o->out, cpu_env, o->out, o->out2, o->in2);
2678 return_low128(o->out2);
2679 return NO_EXIT;
2680 }
2681
2682 static ExitStatus op_maeb(DisasContext *s, DisasOps *o)
2683 {
2684 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2685 gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3);
2686 tcg_temp_free_i64(r3);
2687 return NO_EXIT;
2688 }
2689
2690 static ExitStatus op_madb(DisasContext *s, DisasOps *o)
2691 {
2692 int r3 = get_field(s->fields, r3);
2693 gen_helper_madb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2694 return NO_EXIT;
2695 }
2696
2697 static ExitStatus op_mseb(DisasContext *s, DisasOps *o)
2698 {
2699 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2700 gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3);
2701 tcg_temp_free_i64(r3);
2702 return NO_EXIT;
2703 }
2704
2705 static ExitStatus op_msdb(DisasContext *s, DisasOps *o)
2706 {
2707 int r3 = get_field(s->fields, r3);
2708 gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2709 return NO_EXIT;
2710 }
2711
2712 static ExitStatus op_nabs(DisasContext *s, DisasOps *o)
2713 {
2714 gen_helper_nabs_i64(o->out, o->in2);
2715 return NO_EXIT;
2716 }
2717
2718 static ExitStatus op_nabsf32(DisasContext *s, DisasOps *o)
2719 {
2720 tcg_gen_ori_i64(o->out, o->in2, 0x80000000ull);
2721 return NO_EXIT;
2722 }
2723
2724 static ExitStatus op_nabsf64(DisasContext *s, DisasOps *o)
2725 {
2726 tcg_gen_ori_i64(o->out, o->in2, 0x8000000000000000ull);
2727 return NO_EXIT;
2728 }
2729
2730 static ExitStatus op_nabsf128(DisasContext *s, DisasOps *o)
2731 {
2732 tcg_gen_ori_i64(o->out, o->in1, 0x8000000000000000ull);
2733 tcg_gen_mov_i64(o->out2, o->in2);
2734 return NO_EXIT;
2735 }
2736
2737 static ExitStatus op_nc(DisasContext *s, DisasOps *o)
2738 {
2739 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2740 potential_page_fault(s);
2741 gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2);
2742 tcg_temp_free_i32(l);
2743 set_cc_static(s);
2744 return NO_EXIT;
2745 }
2746
2747 static ExitStatus op_neg(DisasContext *s, DisasOps *o)
2748 {
2749 tcg_gen_neg_i64(o->out, o->in2);
2750 return NO_EXIT;
2751 }
2752
2753 static ExitStatus op_negf32(DisasContext *s, DisasOps *o)
2754 {
2755 tcg_gen_xori_i64(o->out, o->in2, 0x80000000ull);
2756 return NO_EXIT;
2757 }
2758
2759 static ExitStatus op_negf64(DisasContext *s, DisasOps *o)
2760 {
2761 tcg_gen_xori_i64(o->out, o->in2, 0x8000000000000000ull);
2762 return NO_EXIT;
2763 }
2764
2765 static ExitStatus op_negf128(DisasContext *s, DisasOps *o)
2766 {
2767 tcg_gen_xori_i64(o->out, o->in1, 0x8000000000000000ull);
2768 tcg_gen_mov_i64(o->out2, o->in2);
2769 return NO_EXIT;
2770 }
2771
2772 static ExitStatus op_oc(DisasContext *s, DisasOps *o)
2773 {
2774 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2775 potential_page_fault(s);
2776 gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2);
2777 tcg_temp_free_i32(l);
2778 set_cc_static(s);
2779 return NO_EXIT;
2780 }
2781
2782 static ExitStatus op_or(DisasContext *s, DisasOps *o)
2783 {
2784 tcg_gen_or_i64(o->out, o->in1, o->in2);
2785 return NO_EXIT;
2786 }
2787
2788 static ExitStatus op_ori(DisasContext *s, DisasOps *o)
2789 {
2790 int shift = s->insn->data & 0xff;
2791 int size = s->insn->data >> 8;
2792 uint64_t mask = ((1ull << size) - 1) << shift;
2793
2794 assert(!o->g_in2);
2795 tcg_gen_shli_i64(o->in2, o->in2, shift);
2796 tcg_gen_or_i64(o->out, o->in1, o->in2);
2797
2798 /* Produce the CC from only the bits manipulated. */
2799 tcg_gen_andi_i64(cc_dst, o->out, mask);
2800 set_cc_nz_u64(s, cc_dst);
2801 return NO_EXIT;
2802 }
2803
2804 static ExitStatus op_rev16(DisasContext *s, DisasOps *o)
2805 {
2806 tcg_gen_bswap16_i64(o->out, o->in2);
2807 return NO_EXIT;
2808 }
2809
2810 static ExitStatus op_rev32(DisasContext *s, DisasOps *o)
2811 {
2812 tcg_gen_bswap32_i64(o->out, o->in2);
2813 return NO_EXIT;
2814 }
2815
2816 static ExitStatus op_rev64(DisasContext *s, DisasOps *o)
2817 {
2818 tcg_gen_bswap64_i64(o->out, o->in2);
2819 return NO_EXIT;
2820 }
2821
2822 static ExitStatus op_rll32(DisasContext *s, DisasOps *o)
2823 {
2824 TCGv_i32 t1 = tcg_temp_new_i32();
2825 TCGv_i32 t2 = tcg_temp_new_i32();
2826 TCGv_i32 to = tcg_temp_new_i32();
2827 tcg_gen_trunc_i64_i32(t1, o->in1);
2828 tcg_gen_trunc_i64_i32(t2, o->in2);
2829 tcg_gen_rotl_i32(to, t1, t2);
2830 tcg_gen_extu_i32_i64(o->out, to);
2831 tcg_temp_free_i32(t1);
2832 tcg_temp_free_i32(t2);
2833 tcg_temp_free_i32(to);
2834 return NO_EXIT;
2835 }
2836
2837 static ExitStatus op_rll64(DisasContext *s, DisasOps *o)
2838 {
2839 tcg_gen_rotl_i64(o->out, o->in1, o->in2);
2840 return NO_EXIT;
2841 }
2842
2843 static ExitStatus op_sar(DisasContext *s, DisasOps *o)
2844 {
2845 int r1 = get_field(s->fields, r1);
2846 tcg_gen_st32_i64(o->in2, cpu_env, offsetof(CPUS390XState, aregs[r1]));
2847 return NO_EXIT;
2848 }
2849
2850 static ExitStatus op_seb(DisasContext *s, DisasOps *o)
2851 {
2852 gen_helper_seb(o->out, cpu_env, o->in1, o->in2);
2853 return NO_EXIT;
2854 }
2855
2856 static ExitStatus op_sdb(DisasContext *s, DisasOps *o)
2857 {
2858 gen_helper_sdb(o->out, cpu_env, o->in1, o->in2);
2859 return NO_EXIT;
2860 }
2861
2862 static ExitStatus op_sxb(DisasContext *s, DisasOps *o)
2863 {
2864 gen_helper_sxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2865 return_low128(o->out2);
2866 return NO_EXIT;
2867 }
2868
2869 static ExitStatus op_sqeb(DisasContext *s, DisasOps *o)
2870 {
2871 gen_helper_sqeb(o->out, cpu_env, o->in2);
2872 return NO_EXIT;
2873 }
2874
2875 static ExitStatus op_sqdb(DisasContext *s, DisasOps *o)
2876 {
2877 gen_helper_sqdb(o->out, cpu_env, o->in2);
2878 return NO_EXIT;
2879 }
2880
2881 static ExitStatus op_sqxb(DisasContext *s, DisasOps *o)
2882 {
2883 gen_helper_sqxb(o->out, cpu_env, o->in1, o->in2);
2884 return_low128(o->out2);
2885 return NO_EXIT;
2886 }
2887
2888 #ifndef CONFIG_USER_ONLY
2889 static ExitStatus op_sigp(DisasContext *s, DisasOps *o)
2890 {
2891 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2892 check_privileged(s);
2893 potential_page_fault(s);
2894 gen_helper_sigp(cc_op, cpu_env, o->in2, r1, o->in1);
2895 tcg_temp_free_i32(r1);
2896 return NO_EXIT;
2897 }
2898 #endif
2899
2900 static ExitStatus op_sla(DisasContext *s, DisasOps *o)
2901 {
2902 uint64_t sign = 1ull << s->insn->data;
2903 enum cc_op cco = s->insn->data == 31 ? CC_OP_SLA_32 : CC_OP_SLA_64;
2904 gen_op_update2_cc_i64(s, cco, o->in1, o->in2);
2905 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2906 /* The arithmetic left shift is curious in that it does not affect
2907 the sign bit. Copy that over from the source unchanged. */
2908 tcg_gen_andi_i64(o->out, o->out, ~sign);
2909 tcg_gen_andi_i64(o->in1, o->in1, sign);
2910 tcg_gen_or_i64(o->out, o->out, o->in1);
2911 return NO_EXIT;
2912 }
2913
2914 static ExitStatus op_sll(DisasContext *s, DisasOps *o)
2915 {
2916 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2917 return NO_EXIT;
2918 }
2919
2920 static ExitStatus op_sra(DisasContext *s, DisasOps *o)
2921 {
2922 tcg_gen_sar_i64(o->out, o->in1, o->in2);
2923 return NO_EXIT;
2924 }
2925
2926 static ExitStatus op_srl(DisasContext *s, DisasOps *o)
2927 {
2928 tcg_gen_shr_i64(o->out, o->in1, o->in2);
2929 return NO_EXIT;
2930 }
2931
2932 static ExitStatus op_sfpc(DisasContext *s, DisasOps *o)
2933 {
2934 gen_helper_sfpc(cpu_env, o->in2);
2935 return NO_EXIT;
2936 }
2937
2938 #ifndef CONFIG_USER_ONLY
2939 static ExitStatus op_ssm(DisasContext *s, DisasOps *o)
2940 {
2941 check_privileged(s);
2942 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8);
2943 return NO_EXIT;
2944 }
2945
2946 static ExitStatus op_stctg(DisasContext *s, DisasOps *o)
2947 {
2948 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2949 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2950 check_privileged(s);
2951 potential_page_fault(s);
2952 gen_helper_stctg(cpu_env, r1, o->in2, r3);
2953 tcg_temp_free_i32(r1);
2954 tcg_temp_free_i32(r3);
2955 return NO_EXIT;
2956 }
2957
2958 static ExitStatus op_stctl(DisasContext *s, DisasOps *o)
2959 {
2960 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2961 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2962 check_privileged(s);
2963 potential_page_fault(s);
2964 gen_helper_stctl(cpu_env, r1, o->in2, r3);
2965 tcg_temp_free_i32(r1);
2966 tcg_temp_free_i32(r3);
2967 return NO_EXIT;
2968 }
2969
2970 static ExitStatus op_stnosm(DisasContext *s, DisasOps *o)
2971 {
2972 uint64_t i2 = get_field(s->fields, i2);
2973 TCGv_i64 t;
2974
2975 check_privileged(s);
2976
2977 /* It is important to do what the instruction name says: STORE THEN.
2978 If we let the output hook perform the store then if we fault and
2979 restart, we'll have the wrong SYSTEM MASK in place. */
2980 t = tcg_temp_new_i64();
2981 tcg_gen_shri_i64(t, psw_mask, 56);
2982 tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
2983 tcg_temp_free_i64(t);
2984
2985 if (s->fields->op == 0xac) {
2986 tcg_gen_andi_i64(psw_mask, psw_mask,
2987 (i2 << 56) | 0x00ffffffffffffffull);
2988 } else {
2989 tcg_gen_ori_i64(psw_mask, psw_mask, i2 << 56);
2990 }
2991 return NO_EXIT;
2992 }
2993 #endif
2994
2995 static ExitStatus op_st8(DisasContext *s, DisasOps *o)
2996 {
2997 tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
2998 return NO_EXIT;
2999 }
3000
3001 static ExitStatus op_st16(DisasContext *s, DisasOps *o)
3002 {
3003 tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
3004 return NO_EXIT;
3005 }
3006
3007 static ExitStatus op_st32(DisasContext *s, DisasOps *o)
3008 {
3009 tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s));
3010 return NO_EXIT;
3011 }
3012
3013 static ExitStatus op_st64(DisasContext *s, DisasOps *o)
3014 {
3015 tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
3016 return NO_EXIT;
3017 }
3018
3019 static ExitStatus op_stam(DisasContext *s, DisasOps *o)
3020 {
3021 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3022 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
3023 potential_page_fault(s);
3024 gen_helper_stam(cpu_env, r1, o->in2, r3);
3025 tcg_temp_free_i32(r1);
3026 tcg_temp_free_i32(r3);
3027 return NO_EXIT;
3028 }
3029
3030 static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
3031 {
3032 int m3 = get_field(s->fields, m3);
3033 int pos, base = s->insn->data;
3034 TCGv_i64 tmp = tcg_temp_new_i64();
3035
3036 pos = base + ctz32(m3) * 8;
3037 switch (m3) {
3038 case 0xf:
3039 /* Effectively a 32-bit store. */
3040 tcg_gen_shri_i64(tmp, o->in1, pos);
3041 tcg_gen_qemu_st32(tmp, o->in2, get_mem_index(s));
3042 break;
3043
3044 case 0xc:
3045 case 0x6:
3046 case 0x3:
3047 /* Effectively a 16-bit store. */
3048 tcg_gen_shri_i64(tmp, o->in1, pos);
3049 tcg_gen_qemu_st16(tmp, o->in2, get_mem_index(s));
3050 break;
3051
3052 case 0x8:
3053 case 0x4:
3054 case 0x2:
3055 case 0x1:
3056 /* Effectively an 8-bit store. */
3057 tcg_gen_shri_i64(tmp, o->in1, pos);
3058 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3059 break;
3060
3061 default:
3062 /* This is going to be a sequence of shifts and stores. */
3063 pos = base + 32 - 8;
3064 while (m3) {
3065 if (m3 & 0x8) {
3066 tcg_gen_shri_i64(tmp, o->in1, pos);
3067 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3068 tcg_gen_addi_i64(o->in2, o->in2, 1);
3069 }
3070 m3 = (m3 << 1) & 0xf;
3071 pos -= 8;
3072 }
3073 break;
3074 }
3075 tcg_temp_free_i64(tmp);
3076 return NO_EXIT;
3077 }
3078
3079 static ExitStatus op_stm(DisasContext *s, DisasOps *o)
3080 {
3081 int r1 = get_field(s->fields, r1);
3082 int r3 = get_field(s->fields, r3);
3083 int size = s->insn->data;
3084 TCGv_i64 tsize = tcg_const_i64(size);
3085
3086 while (1) {
3087 if (size == 8) {
3088 tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
3089 } else {
3090 tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s));
3091 }
3092 if (r1 == r3) {
3093 break;
3094 }
3095 tcg_gen_add_i64(o->in2, o->in2, tsize);
3096 r1 = (r1 + 1) & 15;
3097 }
3098
3099 tcg_temp_free_i64(tsize);
3100 return NO_EXIT;
3101 }
3102
3103 static ExitStatus op_stmh(DisasContext *s, DisasOps *o)
3104 {
3105 int r1 = get_field(s->fields, r1);
3106 int r3 = get_field(s->fields, r3);
3107 TCGv_i64 t = tcg_temp_new_i64();
3108 TCGv_i64 t4 = tcg_const_i64(4);
3109 TCGv_i64 t32 = tcg_const_i64(32);
3110
3111 while (1) {
3112 tcg_gen_shl_i64(t, regs[r1], t32);
3113 tcg_gen_qemu_st32(t, o->in2, get_mem_index(s));
3114 if (r1 == r3) {
3115 break;
3116 }
3117 tcg_gen_add_i64(o->in2, o->in2, t4);
3118 r1 = (r1 + 1) & 15;
3119 }
3120
3121 tcg_temp_free_i64(t);
3122 tcg_temp_free_i64(t4);
3123 tcg_temp_free_i64(t32);
3124 return NO_EXIT;
3125 }
3126
3127 static ExitStatus op_srst(DisasContext *s, DisasOps *o)
3128 {
3129 potential_page_fault(s);
3130 gen_helper_srst(o->in1, cpu_env, regs[0], o->in1, o->in2);
3131 set_cc_static(s);
3132 return_low128(o->in2);
3133 return NO_EXIT;
3134 }
3135
3136 static ExitStatus op_sub(DisasContext *s, DisasOps *o)
3137 {
3138 tcg_gen_sub_i64(o->out, o->in1, o->in2);
3139 return NO_EXIT;
3140 }
3141
3142 static ExitStatus op_subb(DisasContext *s, DisasOps *o)
3143 {
3144 TCGv_i64 cc;
3145
3146 assert(!o->g_in2);
3147 tcg_gen_not_i64(o->in2, o->in2);
3148 tcg_gen_add_i64(o->out, o->in1, o->in2);
3149
3150 /* XXX possible optimization point */
3151 gen_op_calc_cc(s);
3152 cc = tcg_temp_new_i64();
3153 tcg_gen_extu_i32_i64(cc, cc_op);
3154 tcg_gen_shri_i64(cc, cc, 1);
3155 tcg_gen_add_i64(o->out, o->out, cc);
3156 tcg_temp_free_i64(cc);
3157 return NO_EXIT;
3158 }
3159
3160 static ExitStatus op_svc(DisasContext *s, DisasOps *o)
3161 {
3162 TCGv_i32 t;
3163
3164 update_psw_addr(s);
3165 gen_op_calc_cc(s);
3166
3167 t = tcg_const_i32(get_field(s->fields, i1) & 0xff);
3168 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code));
3169 tcg_temp_free_i32(t);
3170
3171 t = tcg_const_i32(s->next_pc - s->pc);
3172 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen));
3173 tcg_temp_free_i32(t);
3174
3175 gen_exception(EXCP_SVC);
3176 return EXIT_NORETURN;
3177 }
3178
3179 static ExitStatus op_tceb(DisasContext *s, DisasOps *o)
3180 {
3181 gen_helper_tceb(cc_op, o->in1, o->in2);
3182 set_cc_static(s);
3183 return NO_EXIT;
3184 }
3185
3186 static ExitStatus op_tcdb(DisasContext *s, DisasOps *o)
3187 {
3188 gen_helper_tcdb(cc_op, o->in1, o->in2);
3189 set_cc_static(s);
3190 return NO_EXIT;
3191 }
3192
3193 static ExitStatus op_tcxb(DisasContext *s, DisasOps *o)
3194 {
3195 gen_helper_tcxb(cc_op, o->out, o->out2, o->in2);
3196 set_cc_static(s);
3197 return NO_EXIT;
3198 }
3199
3200 #ifndef CONFIG_USER_ONLY
3201 static ExitStatus op_tprot(DisasContext *s, DisasOps *o)
3202 {
3203 potential_page_fault(s);
3204 gen_helper_tprot(cc_op, o->addr1, o->in2);
3205 set_cc_static(s);
3206 return NO_EXIT;
3207 }
3208 #endif
3209
3210 static ExitStatus op_tr(DisasContext *s, DisasOps *o)
3211 {
3212 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3213 potential_page_fault(s);
3214 gen_helper_tr(cpu_env, l, o->addr1, o->in2);
3215 tcg_temp_free_i32(l);
3216 set_cc_static(s);
3217 return NO_EXIT;
3218 }
3219
3220 static ExitStatus op_unpk(DisasContext *s, DisasOps *o)
3221 {
3222 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3223 potential_page_fault(s);
3224 gen_helper_unpk(cpu_env, l, o->addr1, o->in2);
3225 tcg_temp_free_i32(l);
3226 return NO_EXIT;
3227 }
3228
3229 static ExitStatus op_xc(DisasContext *s, DisasOps *o)
3230 {
3231 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3232 potential_page_fault(s);
3233 gen_helper_xc(cc_op, cpu_env, l, o->addr1, o->in2);
3234 tcg_temp_free_i32(l);
3235 set_cc_static(s);
3236 return NO_EXIT;
3237 }
3238
3239 static ExitStatus op_xor(DisasContext *s, DisasOps *o)
3240 {
3241 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3242 return NO_EXIT;
3243 }
3244
3245 static ExitStatus op_xori(DisasContext *s, DisasOps *o)
3246 {
3247 int shift = s->insn->data & 0xff;
3248 int size = s->insn->data >> 8;
3249 uint64_t mask = ((1ull << size) - 1) << shift;
3250
3251 assert(!o->g_in2);
3252 tcg_gen_shli_i64(o->in2, o->in2, shift);
3253 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3254
3255 /* Produce the CC from only the bits manipulated. */
3256 tcg_gen_andi_i64(cc_dst, o->out, mask);
3257 set_cc_nz_u64(s, cc_dst);
3258 return NO_EXIT;
3259 }
3260
3261 static ExitStatus op_zero(DisasContext *s, DisasOps *o)
3262 {
3263 o->out = tcg_const_i64(0);
3264 return NO_EXIT;
3265 }
3266
3267 static ExitStatus op_zero2(DisasContext *s, DisasOps *o)
3268 {
3269 o->out = tcg_const_i64(0);
3270 o->out2 = o->out;
3271 o->g_out2 = true;
3272 return NO_EXIT;
3273 }
3274
3275 /* ====================================================================== */
3276 /* The "Cc OUTput" generators. Given the generated output (and in some cases
3277 the original inputs), update the various cc data structures in order to
3278 be able to compute the new condition code. */
3279
3280 static void cout_abs32(DisasContext *s, DisasOps *o)
3281 {
3282 gen_op_update1_cc_i64(s, CC_OP_ABS_32, o->out);
3283 }
3284
3285 static void cout_abs64(DisasContext *s, DisasOps *o)
3286 {
3287 gen_op_update1_cc_i64(s, CC_OP_ABS_64, o->out);
3288 }
3289
3290 static void cout_adds32(DisasContext *s, DisasOps *o)
3291 {
3292 gen_op_update3_cc_i64(s, CC_OP_ADD_32, o->in1, o->in2, o->out);
3293 }
3294
3295 static void cout_adds64(DisasContext *s, DisasOps *o)
3296 {
3297 gen_op_update3_cc_i64(s, CC_OP_ADD_64, o->in1, o->in2, o->out);
3298 }
3299
3300 static void cout_addu32(DisasContext *s, DisasOps *o)
3301 {
3302 gen_op_update3_cc_i64(s, CC_OP_ADDU_32, o->in1, o->in2, o->out);
3303 }
3304
3305 static void cout_addu64(DisasContext *s, DisasOps *o)
3306 {
3307 gen_op_update3_cc_i64(s, CC_OP_ADDU_64, o->in1, o->in2, o->out);
3308 }
3309
3310 static void cout_addc32(DisasContext *s, DisasOps *o)
3311 {
3312 gen_op_update3_cc_i64(s, CC_OP_ADDC_32, o->in1, o->in2, o->out);
3313 }
3314
3315 static void cout_addc64(DisasContext *s, DisasOps *o)
3316 {
3317 gen_op_update3_cc_i64(s, CC_OP_ADDC_64, o->in1, o->in2, o->out);
3318 }
3319
3320 static void cout_cmps32(DisasContext *s, DisasOps *o)
3321 {
3322 gen_op_update2_cc_i64(s, CC_OP_LTGT_32, o->in1, o->in2);
3323 }
3324
3325 static void cout_cmps64(DisasContext *s, DisasOps *o)
3326 {
3327 gen_op_update2_cc_i64(s, CC_OP_LTGT_64, o->in1, o->in2);
3328 }
3329
3330 static void cout_cmpu32(DisasContext *s, DisasOps *o)
3331 {
3332 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_32, o->in1, o->in2);
3333 }
3334
3335 static void cout_cmpu64(DisasContext *s, DisasOps *o)
3336 {
3337 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, o->in1, o->in2);
3338 }
3339
3340 static void cout_f32(DisasContext *s, DisasOps *o)
3341 {
3342 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, o->out);
3343 }
3344
3345 static void cout_f64(DisasContext *s, DisasOps *o)
3346 {
3347 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, o->out);
3348 }
3349
3350 static void cout_f128(DisasContext *s, DisasOps *o)
3351 {
3352 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, o->out, o->out2);
3353 }
3354
3355 static void cout_nabs32(DisasContext *s, DisasOps *o)
3356 {
3357 gen_op_update1_cc_i64(s, CC_OP_NABS_32, o->out);
3358 }
3359
3360 static void cout_nabs64(DisasContext *s, DisasOps *o)
3361 {
3362 gen_op_update1_cc_i64(s, CC_OP_NABS_64, o->out);
3363 }
3364
3365 static void cout_neg32(DisasContext *s, DisasOps *o)
3366 {
3367 gen_op_update1_cc_i64(s, CC_OP_COMP_32, o->out);
3368 }
3369
3370 static void cout_neg64(DisasContext *s, DisasOps *o)
3371 {
3372 gen_op_update1_cc_i64(s, CC_OP_COMP_64, o->out);
3373 }
3374
3375 static void cout_nz32(DisasContext *s, DisasOps *o)
3376 {
3377 tcg_gen_ext32u_i64(cc_dst, o->out);
3378 gen_op_update1_cc_i64(s, CC_OP_NZ, cc_dst);
3379 }
3380
3381 static void cout_nz64(DisasContext *s, DisasOps *o)
3382 {
3383 gen_op_update1_cc_i64(s, CC_OP_NZ, o->out);
3384 }
3385
3386 static void cout_s32(DisasContext *s, DisasOps *o)
3387 {
3388 gen_op_update1_cc_i64(s, CC_OP_LTGT0_32, o->out);
3389 }
3390
3391 static void cout_s64(DisasContext *s, DisasOps *o)
3392 {
3393 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, o->out);
3394 }
3395
3396 static void cout_subs32(DisasContext *s, DisasOps *o)
3397 {
3398 gen_op_update3_cc_i64(s, CC_OP_SUB_32, o->in1, o->in2, o->out);
3399 }
3400
3401 static void cout_subs64(DisasContext *s, DisasOps *o)
3402 {
3403 gen_op_update3_cc_i64(s, CC_OP_SUB_64, o->in1, o->in2, o->out);
3404 }
3405
3406 static void cout_subu32(DisasContext *s, DisasOps *o)
3407 {
3408 gen_op_update3_cc_i64(s, CC_OP_SUBU_32, o->in1, o->in2, o->out);
3409 }
3410
3411 static void cout_subu64(DisasContext *s, DisasOps *o)
3412 {
3413 gen_op_update3_cc_i64(s, CC_OP_SUBU_64, o->in1, o->in2, o->out);
3414 }
3415
3416 static void cout_subb32(DisasContext *s, DisasOps *o)
3417 {
3418 gen_op_update3_cc_i64(s, CC_OP_SUBB_32, o->in1, o->in2, o->out);
3419 }
3420
3421 static void cout_subb64(DisasContext *s, DisasOps *o)
3422 {
3423 gen_op_update3_cc_i64(s, CC_OP_SUBB_64, o->in1, o->in2, o->out);
3424 }
3425
3426 static void cout_tm32(DisasContext *s, DisasOps *o)
3427 {
3428 gen_op_update2_cc_i64(s, CC_OP_TM_32, o->in1, o->in2);
3429 }
3430
3431 static void cout_tm64(DisasContext *s, DisasOps *o)
3432 {
3433 gen_op_update2_cc_i64(s, CC_OP_TM_64, o->in1, o->in2);
3434 }
3435
3436 /* ====================================================================== */
3437 /* The "PREPeration" generators. These initialize the DisasOps.OUT fields
3438 with the TCG register to which we will write. Used in combination with
3439 the "wout" generators, in some cases we need a new temporary, and in
3440 some cases we can write to a TCG global. */
3441
3442 static void prep_new(DisasContext *s, DisasFields *f, DisasOps *o)
3443 {
3444 o->out = tcg_temp_new_i64();
3445 }
3446
3447 static void prep_new_P(DisasContext *s, DisasFields *f, DisasOps *o)
3448 {
3449 o->out = tcg_temp_new_i64();
3450 o->out2 = tcg_temp_new_i64();
3451 }
3452
3453 static void prep_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3454 {
3455 o->out = regs[get_field(f, r1)];
3456 o->g_out = true;
3457 }
3458
3459 static void prep_r1_P(DisasContext *s, DisasFields *f, DisasOps *o)
3460 {
3461 /* ??? Specification exception: r1 must be even. */
3462 int r1 = get_field(f, r1);
3463 o->out = regs[r1];
3464 o->out2 = regs[(r1 + 1) & 15];
3465 o->g_out = o->g_out2 = true;
3466 }
3467
3468 static void prep_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3469 {
3470 o->out = fregs[get_field(f, r1)];
3471 o->g_out = true;
3472 }
3473
3474 static void prep_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3475 {
3476 /* ??? Specification exception: r1 must be < 14. */
3477 int r1 = get_field(f, r1);
3478 o->out = fregs[r1];
3479 o->out2 = fregs[(r1 + 2) & 15];
3480 o->g_out = o->g_out2 = true;
3481 }
3482
3483 /* ====================================================================== */
3484 /* The "Write OUTput" generators. These generally perform some non-trivial
3485 copy of data to TCG globals, or to main memory. The trivial cases are
3486 generally handled by having a "prep" generator install the TCG global
3487 as the destination of the operation. */
3488
3489 static void wout_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3490 {
3491 store_reg(get_field(f, r1), o->out);
3492 }
3493
3494 static void wout_r1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3495 {
3496 int r1 = get_field(f, r1);
3497 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8);
3498 }
3499
3500 static void wout_r1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3501 {
3502 int r1 = get_field(f, r1);
3503 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 16);
3504 }
3505
3506 static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3507 {
3508 store_reg32_i64(get_field(f, r1), o->out);
3509 }
3510
3511 static void wout_r1_P32(DisasContext *s, DisasFields *f, DisasOps *o)
3512 {
3513 /* ??? Specification exception: r1 must be even. */
3514 int r1 = get_field(f, r1);
3515 store_reg32_i64(r1, o->out);
3516 store_reg32_i64((r1 + 1) & 15, o->out2);
3517 }
3518
3519 static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3520 {
3521 /* ??? Specification exception: r1 must be even. */
3522 int r1 = get_field(f, r1);
3523 store_reg32_i64((r1 + 1) & 15, o->out);
3524 tcg_gen_shri_i64(o->out, o->out, 32);
3525 store_reg32_i64(r1, o->out);
3526 }
3527
3528 static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3529 {
3530 store_freg32_i64(get_field(f, r1), o->out);
3531 }
3532
3533 static void wout_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3534 {
3535 store_freg(get_field(f, r1), o->out);
3536 }
3537
3538 static void wout_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3539 {
3540 /* ??? Specification exception: r1 must be < 14. */
3541 int f1 = get_field(s->fields, r1);
3542 store_freg(f1, o->out);
3543 store_freg((f1 + 2) & 15, o->out2);
3544 }
3545
3546 static void wout_cond_r1r2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3547 {
3548 if (get_field(f, r1) != get_field(f, r2)) {
3549 store_reg32_i64(get_field(f, r1), o->out);
3550 }
3551 }
3552
3553 static void wout_cond_e1e2(DisasContext *s, DisasFields *f, DisasOps *o)
3554 {
3555 if (get_field(f, r1) != get_field(f, r2)) {
3556 store_freg32_i64(get_field(f, r1), o->out);
3557 }
3558 }
3559
3560 static void wout_m1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3561 {
3562 tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s));
3563 }
3564
3565 static void wout_m1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3566 {
3567 tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s));
3568 }
3569
3570 static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3571 {
3572 tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
3573 }
3574
3575 static void wout_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3576 {
3577 tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
3578 }
3579
3580 static void wout_m2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3581 {
3582 tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s));
3583 }
3584
3585 /* ====================================================================== */
3586 /* The "INput 1" generators. These load the first operand to an insn. */
3587
3588 static void in1_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3589 {
3590 o->in1 = load_reg(get_field(f, r1));
3591 }
3592
3593 static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3594 {
3595 o->in1 = regs[get_field(f, r1)];
3596 o->g_in1 = true;
3597 }
3598
3599 static void in1_r1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3600 {
3601 o->in1 = tcg_temp_new_i64();
3602 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r1)]);
3603 }
3604
3605 static void in1_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3606 {
3607 o->in1 = tcg_temp_new_i64();
3608 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r1)]);
3609 }
3610
3611 static void in1_r1_sr32(DisasContext *s, DisasFields *f, DisasOps *o)
3612 {
3613 o->in1 = tcg_temp_new_i64();
3614 tcg_gen_shri_i64(o->in1, regs[get_field(f, r1)], 32);
3615 }
3616
3617 static void in1_r1p1(DisasContext *s, DisasFields *f, DisasOps *o)
3618 {
3619 /* ??? Specification exception: r1 must be even. */
3620 int r1 = get_field(f, r1);
3621 o->in1 = load_reg((r1 + 1) & 15);
3622 }
3623
3624 static void in1_r1p1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3625 {
3626 /* ??? Specification exception: r1 must be even. */
3627 int r1 = get_field(f, r1);
3628 o->in1 = tcg_temp_new_i64();
3629 tcg_gen_ext32s_i64(o->in1, regs[(r1 + 1) & 15]);
3630 }
3631
3632 static void in1_r1p1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3633 {
3634 /* ??? Specification exception: r1 must be even. */
3635 int r1 = get_field(f, r1);
3636 o->in1 = tcg_temp_new_i64();
3637 tcg_gen_ext32u_i64(o->in1, regs[(r1 + 1) & 15]);
3638 }
3639
3640 static void in1_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3641 {
3642 /* ??? Specification exception: r1 must be even. */
3643 int r1 = get_field(f, r1);
3644 o->in1 = tcg_temp_new_i64();
3645 tcg_gen_concat32_i64(o->in1, regs[r1 + 1], regs[r1]);
3646 }
3647
3648 static void in1_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3649 {
3650 o->in1 = load_reg(get_field(f, r2));
3651 }
3652
3653 static void in1_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3654 {
3655 o->in1 = load_reg(get_field(f, r3));
3656 }
3657
3658 static void in1_r3_o(DisasContext *s, DisasFields *f, DisasOps *o)
3659 {
3660 o->in1 = regs[get_field(f, r3)];
3661 o->g_in1 = true;
3662 }
3663
3664 static void in1_r3_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3665 {
3666 o->in1 = tcg_temp_new_i64();
3667 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r3)]);
3668 }
3669
3670 static void in1_r3_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3671 {
3672 o->in1 = tcg_temp_new_i64();
3673 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r3)]);
3674 }
3675
3676 static void in1_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3677 {
3678 o->in1 = load_freg32_i64(get_field(f, r1));
3679 }
3680
3681 static void in1_f1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3682 {
3683 o->in1 = fregs[get_field(f, r1)];
3684 o->g_in1 = true;
3685 }
3686
3687 static void in1_x1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3688 {
3689 /* ??? Specification exception: r1 must be < 14. */
3690 int r1 = get_field(f, r1);
3691 o->out = fregs[r1];
3692 o->out2 = fregs[(r1 + 2) & 15];
3693 o->g_out = o->g_out2 = true;
3694 }
3695
3696 static void in1_la1(DisasContext *s, DisasFields *f, DisasOps *o)
3697 {
3698 o->addr1 = get_address(s, 0, get_field(f, b1), get_field(f, d1));
3699 }
3700
3701 static void in1_la2(DisasContext *s, DisasFields *f, DisasOps *o)
3702 {
3703 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3704 o->addr1 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3705 }
3706
3707 static void in1_m1_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3708 {
3709 in1_la1(s, f, o);
3710 o->in1 = tcg_temp_new_i64();
3711 tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s));
3712 }
3713
3714 static void in1_m1_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3715 {
3716 in1_la1(s, f, o);
3717 o->in1 = tcg_temp_new_i64();
3718 tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s));
3719 }
3720
3721 static void in1_m1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3722 {
3723 in1_la1(s, f, o);
3724 o->in1 = tcg_temp_new_i64();
3725 tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s));
3726 }
3727
3728 static void in1_m1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3729 {
3730 in1_la1(s, f, o);
3731 o->in1 = tcg_temp_new_i64();
3732 tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s));
3733 }
3734
3735 static void in1_m1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3736 {
3737 in1_la1(s, f, o);
3738 o->in1 = tcg_temp_new_i64();
3739 tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s));
3740 }
3741
3742 static void in1_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3743 {
3744 in1_la1(s, f, o);
3745 o->in1 = tcg_temp_new_i64();
3746 tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s));
3747 }
3748
3749 /* ====================================================================== */
3750 /* The "INput 2" generators. These load the second operand to an insn. */
3751
3752 static void in2_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3753 {
3754 o->in2 = regs[get_field(f, r1)];
3755 o->g_in2 = true;
3756 }
3757
3758 static void in2_r1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3759 {
3760 o->in2 = tcg_temp_new_i64();
3761 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r1)]);
3762 }
3763
3764 static void in2_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3765 {
3766 o->in2 = tcg_temp_new_i64();
3767 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r1)]);
3768 }
3769
3770 static void in2_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3771 {
3772 o->in2 = load_reg(get_field(f, r2));
3773 }
3774
3775 static void in2_r2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3776 {
3777 o->in2 = regs[get_field(f, r2)];
3778 o->g_in2 = true;
3779 }
3780
3781 static void in2_r2_nz(DisasContext *s, DisasFields *f, DisasOps *o)
3782 {
3783 int r2 = get_field(f, r2);
3784 if (r2 != 0) {
3785 o->in2 = load_reg(r2);
3786 }
3787 }
3788
3789 static void in2_r2_8s(DisasContext *s, DisasFields *f, DisasOps *o)
3790 {
3791 o->in2 = tcg_temp_new_i64();
3792 tcg_gen_ext8s_i64(o->in2, regs[get_field(f, r2)]);
3793 }
3794
3795 static void in2_r2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3796 {
3797 o->in2 = tcg_temp_new_i64();
3798 tcg_gen_ext8u_i64(o->in2, regs[get_field(f, r2)]);
3799 }
3800
3801 static void in2_r2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3802 {
3803 o->in2 = tcg_temp_new_i64();
3804 tcg_gen_ext16s_i64(o->in2, regs[get_field(f, r2)]);
3805 }
3806
3807 static void in2_r2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3808 {
3809 o->in2 = tcg_temp_new_i64();
3810 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r2)]);
3811 }
3812
3813 static void in2_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3814 {
3815 o->in2 = load_reg(get_field(f, r3));
3816 }
3817
3818 static void in2_r2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3819 {
3820 o->in2 = tcg_temp_new_i64();
3821 tcg_gen_ext32s_i64(o->in2, regs[get_field(f, r2)]);
3822 }
3823
3824 static void in2_r2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3825 {
3826 o->in2 = tcg_temp_new_i64();
3827 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r2)]);
3828 }
3829
3830 static void in2_e2(DisasContext *s, DisasFields *f, DisasOps *o)
3831 {
3832 o->in2 = load_freg32_i64(get_field(f, r2));
3833 }
3834
3835 static void in2_f2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3836 {
3837 o->in2 = fregs[get_field(f, r2)];
3838 o->g_in2 = true;
3839 }
3840
3841 static void in2_x2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3842 {
3843 /* ??? Specification exception: r1 must be < 14. */
3844 int r2 = get_field(f, r2);
3845 o->in1 = fregs[r2];
3846 o->in2 = fregs[(r2 + 2) & 15];
3847 o->g_in1 = o->g_in2 = true;
3848 }
3849
3850 static void in2_ra2(DisasContext *s, DisasFields *f, DisasOps *o)
3851 {
3852 o->in2 = get_address(s, 0, get_field(f, r2), 0);
3853 }
3854
3855 static void in2_a2(DisasContext *s, DisasFields *f, DisasOps *o)
3856 {
3857 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3858 o->in2 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3859 }
3860
3861 static void in2_ri2(DisasContext *s, DisasFields *f, DisasOps *o)
3862 {
3863 o->in2 = tcg_const_i64(s->pc + (int64_t)get_field(f, i2) * 2);
3864 }
3865
3866 static void in2_sh32(DisasContext *s, DisasFields *f, DisasOps *o)
3867 {
3868 help_l2_shift(s, f, o, 31);
3869 }
3870
3871 static void in2_sh64(DisasContext *s, DisasFields *f, DisasOps *o)
3872 {
3873 help_l2_shift(s, f, o, 63);
3874 }
3875
3876 static void in2_m2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3877 {
3878 in2_a2(s, f, o);
3879 tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s));
3880 }
3881
3882 static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3883 {
3884 in2_a2(s, f, o);
3885 tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
3886 }
3887
3888 static void in2_m2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3889 {
3890 in2_a2(s, f, o);
3891 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3892 }
3893
3894 static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3895 {
3896 in2_a2(s, f, o);
3897 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3898 }
3899
3900 static void in2_m2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3901 {
3902 in2_a2(s, f, o);
3903 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3904 }
3905
3906 static void in2_m2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3907 {
3908 in2_a2(s, f, o);
3909 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3910 }
3911
3912 static void in2_mri2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3913 {
3914 in2_ri2(s, f, o);
3915 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3916 }
3917
3918 static void in2_mri2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3919 {
3920 in2_ri2(s, f, o);
3921 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3922 }
3923
3924 static void in2_mri2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3925 {
3926 in2_ri2(s, f, o);
3927 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3928 }
3929
3930 static void in2_mri2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3931 {
3932 in2_ri2(s, f, o);
3933 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3934 }
3935
3936 static void in2_i2(DisasContext *s, DisasFields *f, DisasOps *o)
3937 {
3938 o->in2 = tcg_const_i64(get_field(f, i2));
3939 }
3940
3941 static void in2_i2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3942 {
3943 o->in2 = tcg_const_i64((uint8_t)get_field(f, i2));
3944 }
3945
3946 static void in2_i2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3947 {
3948 o->in2 = tcg_const_i64((uint16_t)get_field(f, i2));
3949 }
3950
3951 static void in2_i2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3952 {
3953 o->in2 = tcg_const_i64((uint32_t)get_field(f, i2));
3954 }
3955
3956 static void in2_i2_16u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
3957 {
3958 uint64_t i2 = (uint16_t)get_field(f, i2);
3959 o->in2 = tcg_const_i64(i2 << s->insn->data);
3960 }
3961
3962 static void in2_i2_32u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
3963 {
3964 uint64_t i2 = (uint32_t)get_field(f, i2);
3965 o->in2 = tcg_const_i64(i2 << s->insn->data);
3966 }
3967
3968 /* ====================================================================== */
3969
3970 /* Find opc within the table of insns. This is formulated as a switch
3971 statement so that (1) we get compile-time notice of cut-paste errors
3972 for duplicated opcodes, and (2) the compiler generates the binary
3973 search tree, rather than us having to post-process the table. */
3974
3975 #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
3976 D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0)
3977
3978 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) insn_ ## NM,
3979
3980 enum DisasInsnEnum {
3981 #include "insn-data.def"
3982 };
3983
3984 #undef D
3985 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) { \
3986 .opc = OPC, \
3987 .fmt = FMT_##FT, \
3988 .fac = FAC_##FC, \
3989 .name = #NM, \
3990 .help_in1 = in1_##I1, \
3991 .help_in2 = in2_##I2, \
3992 .help_prep = prep_##P, \
3993 .help_wout = wout_##W, \
3994 .help_cout = cout_##CC, \
3995 .help_op = op_##OP, \
3996 .data = D \
3997 },
3998
3999 /* Allow 0 to be used for NULL in the table below. */
4000 #define in1_0 NULL
4001 #define in2_0 NULL
4002 #define prep_0 NULL
4003 #define wout_0 NULL
4004 #define cout_0 NULL
4005 #define op_0 NULL
4006
4007 static const DisasInsn insn_info[] = {
4008 #include "insn-data.def"
4009 };
4010
4011 #undef D
4012 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
4013 case OPC: return &insn_info[insn_ ## NM];
4014
4015 static const DisasInsn *lookup_opc(uint16_t opc)
4016 {
4017 switch (opc) {
4018 #include "insn-data.def"
4019 default:
4020 return NULL;
4021 }
4022 }
4023
4024 #undef D
4025 #undef C
4026
4027 /* Extract a field from the insn. The INSN should be left-aligned in
4028 the uint64_t so that we can more easily utilize the big-bit-endian
4029 definitions we extract from the Principals of Operation. */
4030
4031 static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn)
4032 {
4033 uint32_t r, m;
4034
4035 if (f->size == 0) {
4036 return;
4037 }
4038
4039 /* Zero extract the field from the insn. */
4040 r = (insn << f->beg) >> (64 - f->size);
4041
4042 /* Sign-extend, or un-swap the field as necessary. */
4043 switch (f->type) {
4044 case 0: /* unsigned */
4045 break;
4046 case 1: /* signed */
4047 assert(f->size <= 32);
4048 m = 1u << (f->size - 1);
4049 r = (r ^ m) - m;
4050 break;
4051 case 2: /* dl+dh split, signed 20 bit. */
4052 r = ((int8_t)r << 12) | (r >> 8);
4053 break;
4054 default:
4055 abort();
4056 }
4057
4058 /* Validate that the "compressed" encoding we selected above is valid.
4059 I.e. we havn't make two different original fields overlap. */
4060 assert(((o->presentC >> f->indexC) & 1) == 0);
4061 o->presentC |= 1 << f->indexC;
4062 o->presentO |= 1 << f->indexO;
4063
4064 o->c[f->indexC] = r;
4065 }
4066
4067 /* Lookup the insn at the current PC, extracting the operands into O and
4068 returning the info struct for the insn. Returns NULL for invalid insn. */
4069
4070 static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
4071 DisasFields *f)
4072 {
4073 uint64_t insn, pc = s->pc;
4074 int op, op2, ilen;
4075 const DisasInsn *info;
4076
4077 insn = ld_code2(env, pc);
4078 op = (insn >> 8) & 0xff;
4079 ilen = get_ilen(op);
4080 s->next_pc = s->pc + ilen;
4081
4082 switch (ilen) {
4083 case 2:
4084 insn = insn << 48;
4085 break;
4086 case 4:
4087 insn = ld_code4(env, pc) << 32;
4088 break;
4089 case 6:
4090 insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
4091 break;
4092 default:
4093 abort();
4094 }
4095
4096 /* We can't actually determine the insn format until we've looked up
4097 the full insn opcode. Which we can't do without locating the
4098 secondary opcode. Assume by default that OP2 is at bit 40; for
4099 those smaller insns that don't actually have a secondary opcode
4100 this will correctly result in OP2 = 0. */
4101 switch (op) {
4102 case 0x01: /* E */
4103 case 0x80: /* S */
4104 case 0x82: /* S */
4105 case 0x93: /* S */
4106 case 0xb2: /* S, RRF, RRE */
4107 case 0xb3: /* RRE, RRD, RRF */
4108 case 0xb9: /* RRE, RRF */
4109 case 0xe5: /* SSE, SIL */
4110 op2 = (insn << 8) >> 56;
4111 break;
4112 case 0xa5: /* RI */
4113 case 0xa7: /* RI */
4114 case 0xc0: /* RIL */
4115 case 0xc2: /* RIL */
4116 case 0xc4: /* RIL */
4117 case 0xc6: /* RIL */
4118 case 0xc8: /* SSF */
4119 case 0xcc: /* RIL */
4120 op2 = (insn << 12) >> 60;
4121 break;
4122 case 0xd0 ... 0xdf: /* SS */
4123 case 0xe1: /* SS */
4124 case 0xe2: /* SS */
4125 case 0xe8: /* SS */
4126 case 0xe9: /* SS */
4127 case 0xea: /* SS */
4128 case 0xee ... 0xf3: /* SS */
4129 case 0xf8 ... 0xfd: /* SS */
4130 op2 = 0;
4131 break;
4132 default:
4133 op2 = (insn << 40) >> 56;
4134 break;
4135 }
4136
4137 memset(f, 0, sizeof(*f));
4138 f->op = op;
4139 f->op2 = op2;
4140
4141 /* Lookup the instruction. */
4142 info = lookup_opc(op << 8 | op2);
4143
4144 /* If we found it, extract the operands. */
4145 if (info != NULL) {
4146 DisasFormat fmt = info->fmt;
4147 int i;
4148
4149 for (i = 0; i < NUM_C_FIELD; ++i) {
4150 extract_field(f, &format_info[fmt].op[i], insn);
4151 }
4152 }
4153 return info;
4154 }
4155
4156 static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
4157 {
4158 const DisasInsn *insn;
4159 ExitStatus ret = NO_EXIT;
4160 DisasFields f;
4161 DisasOps o;
4162
4163 insn = extract_insn(env, s, &f);
4164
4165 /* If not found, try the old interpreter. This includes ILLOPC. */
4166 if (insn == NULL) {
4167 disas_s390_insn(env, s);
4168 switch (s->is_jmp) {
4169 case DISAS_NEXT:
4170 ret = NO_EXIT;
4171 break;
4172 case DISAS_TB_JUMP:
4173 ret = EXIT_GOTO_TB;
4174 break;
4175 case DISAS_JUMP:
4176 ret = EXIT_PC_UPDATED;
4177 break;
4178 case DISAS_EXCP:
4179 ret = EXIT_NORETURN;
4180 break;
4181 default:
4182 abort();
4183 }
4184
4185 s->pc = s->next_pc;
4186 return ret;
4187 }
4188
4189 /* Set up the strutures we use to communicate with the helpers. */
4190 s->insn = insn;
4191 s->fields = &f;
4192 o.g_out = o.g_out2 = o.g_in1 = o.g_in2 = false;
4193 TCGV_UNUSED_I64(o.out);
4194 TCGV_UNUSED_I64(o.out2);
4195 TCGV_UNUSED_I64(o.in1);
4196 TCGV_UNUSED_I64(o.in2);
4197 TCGV_UNUSED_I64(o.addr1);
4198
4199 /* Implement the instruction. */
4200 if (insn->help_in1) {
4201 insn->help_in1(s, &f, &o);
4202 }
4203 if (insn->help_in2) {
4204 insn->help_in2(s, &f, &o);
4205 }
4206 if (insn->help_prep) {
4207 insn->help_prep(s, &f, &o);
4208 }
4209 if (insn->help_op) {
4210 ret = insn->help_op(s, &o);
4211 }
4212 if (insn->help_wout) {
4213 insn->help_wout(s, &f, &o);
4214 }
4215 if (insn->help_cout) {
4216 insn->help_cout(s, &o);
4217 }
4218
4219 /* Free any temporaries created by the helpers. */
4220 if (!TCGV_IS_UNUSED_I64(o.out) && !o.g_out) {
4221 tcg_temp_free_i64(o.out);
4222 }
4223 if (!TCGV_IS_UNUSED_I64(o.out2) && !o.g_out2) {
4224 tcg_temp_free_i64(o.out2);
4225 }
4226 if (!TCGV_IS_UNUSED_I64(o.in1) && !o.g_in1) {
4227 tcg_temp_free_i64(o.in1);
4228 }
4229 if (!TCGV_IS_UNUSED_I64(o.in2) && !o.g_in2) {
4230 tcg_temp_free_i64(o.in2);
4231 }
4232 if (!TCGV_IS_UNUSED_I64(o.addr1)) {
4233 tcg_temp_free_i64(o.addr1);
4234 }
4235
4236 /* Advance to the next instruction. */
4237 s->pc = s->next_pc;
4238 return ret;
4239 }
4240
4241 static inline void gen_intermediate_code_internal(CPUS390XState *env,
4242 TranslationBlock *tb,
4243 int search_pc)
4244 {
4245 DisasContext dc;
4246 target_ulong pc_start;
4247 uint64_t next_page_start;
4248 uint16_t *gen_opc_end;
4249 int j, lj = -1;
4250 int num_insns, max_insns;
4251 CPUBreakpoint *bp;
4252 ExitStatus status;
4253 bool do_debug;
4254
4255 pc_start = tb->pc;
4256
4257 /* 31-bit mode */
4258 if (!(tb->flags & FLAG_MASK_64)) {
4259 pc_start &= 0x7fffffff;
4260 }
4261
4262 dc.tb = tb;
4263 dc.pc = pc_start;
4264 dc.cc_op = CC_OP_DYNAMIC;
4265 do_debug = dc.singlestep_enabled = env->singlestep_enabled;
4266 dc.is_jmp = DISAS_NEXT;
4267
4268 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
4269
4270 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4271
4272 num_insns = 0;
4273 max_insns = tb->cflags & CF_COUNT_MASK;
4274 if (max_insns == 0) {
4275 max_insns = CF_COUNT_MASK;
4276 }
4277
4278 gen_icount_start();
4279
4280 do {
4281 if (search_pc) {
4282 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4283 if (lj < j) {
4284 lj++;
4285 while (lj < j) {
4286 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4287 }
4288 }
4289 tcg_ctx.gen_opc_pc[lj] = dc.pc;
4290 gen_opc_cc_op[lj] = dc.cc_op;
4291 tcg_ctx.gen_opc_instr_start[lj] = 1;
4292 tcg_ctx.gen_opc_icount[lj] = num_insns;
4293 }
4294 if (++num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
4295 gen_io_start();
4296 }
4297
4298 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4299 tcg_gen_debug_insn_start(dc.pc);
4300 }
4301
4302 status = NO_EXIT;
4303 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
4304 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
4305 if (bp->pc == dc.pc) {
4306 status = EXIT_PC_STALE;
4307 do_debug = true;
4308 break;
4309 }
4310 }
4311 }
4312 if (status == NO_EXIT) {
4313 status = translate_one(env, &dc);
4314 }
4315
4316 /* If we reach a page boundary, are single stepping,
4317 or exhaust instruction count, stop generation. */
4318 if (status == NO_EXIT
4319 && (dc.pc >= next_page_start
4320 || tcg_ctx.gen_opc_ptr >= gen_opc_end
4321 || num_insns >= max_insns
4322 || singlestep
4323 || env->singlestep_enabled)) {
4324 status = EXIT_PC_STALE;
4325 }
4326 } while (status == NO_EXIT);
4327
4328 if (tb->cflags & CF_LAST_IO) {
4329 gen_io_end();
4330 }
4331
4332 switch (status) {
4333 case EXIT_GOTO_TB:
4334 case EXIT_NORETURN:
4335 break;
4336 case EXIT_PC_STALE:
4337 update_psw_addr(&dc);
4338 /* FALLTHRU */
4339 case EXIT_PC_UPDATED:
4340 if (singlestep && dc.cc_op != CC_OP_DYNAMIC) {
4341 gen_op_calc_cc(&dc);
4342 } else {
4343 /* Next TB starts off with CC_OP_DYNAMIC,
4344 so make sure the cc op type is in env */
4345 gen_op_set_cc_op(&dc);
4346 }
4347 if (do_debug) {
4348 gen_exception(EXCP_DEBUG);
4349 } else {
4350 /* Generate the return instruction */
4351 tcg_gen_exit_tb(0);
4352 }
4353 break;
4354 default:
4355 abort();
4356 }
4357
4358 gen_icount_end(tb, num_insns);
4359 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
4360 if (search_pc) {
4361 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4362 lj++;
4363 while (lj <= j) {
4364 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4365 }
4366 } else {
4367 tb->size = dc.pc - pc_start;
4368 tb->icount = num_insns;
4369 }
4370
4371 #if defined(S390X_DEBUG_DISAS)
4372 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
4373 qemu_log("IN: %s\n", lookup_symbol(pc_start));
4374 log_target_disas(env, pc_start, dc.pc - pc_start, 1);
4375 qemu_log("\n");
4376 }
4377 #endif
4378 }
4379
4380 void gen_intermediate_code (CPUS390XState *env, struct TranslationBlock *tb)
4381 {
4382 gen_intermediate_code_internal(env, tb, 0);
4383 }
4384
4385 void gen_intermediate_code_pc (CPUS390XState *env, struct TranslationBlock *tb)
4386 {
4387 gen_intermediate_code_internal(env, tb, 1);
4388 }
4389
4390 void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos)
4391 {
4392 int cc_op;
4393 env->psw.addr = tcg_ctx.gen_opc_pc[pc_pos];
4394 cc_op = gen_opc_cc_op[pc_pos];
4395 if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {
4396 env->cc_op = cc_op;
4397 }
4398 }
Qemu copy for testing