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target-s390: Implement R[NOX]SBG
[qemu.git] / target-s390x / translate.c
1 /*
2 * S/390 translation
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* #define DEBUG_INLINE_BRANCHES */
22 #define S390X_DEBUG_DISAS
23 /* #define S390X_DEBUG_DISAS_VERBOSE */
24
25 #ifdef S390X_DEBUG_DISAS_VERBOSE
26 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
27 #else
28 # define LOG_DISAS(...) do { } while (0)
29 #endif
30
31 #include "cpu.h"
32 #include "disas/disas.h"
33 #include "tcg-op.h"
34 #include "qemu/log.h"
35 #include "qemu/host-utils.h"
36
37 /* global register indexes */
38 static TCGv_ptr cpu_env;
39
40 #include "exec/gen-icount.h"
41 #include "helper.h"
42 #define GEN_HELPER 1
43 #include "helper.h"
44
45
46 /* Information that (most) every instruction needs to manipulate. */
47 typedef struct DisasContext DisasContext;
48 typedef struct DisasInsn DisasInsn;
49 typedef struct DisasFields DisasFields;
50
51 struct DisasContext {
52 struct TranslationBlock *tb;
53 const DisasInsn *insn;
54 DisasFields *fields;
55 uint64_t pc, next_pc;
56 enum cc_op cc_op;
57 bool singlestep_enabled;
58 };
59
60 /* Information carried about a condition to be evaluated. */
61 typedef struct {
62 TCGCond cond:8;
63 bool is_64;
64 bool g1;
65 bool g2;
66 union {
67 struct { TCGv_i64 a, b; } s64;
68 struct { TCGv_i32 a, b; } s32;
69 } u;
70 } DisasCompare;
71
72 #define DISAS_EXCP 4
73
74 #ifdef DEBUG_INLINE_BRANCHES
75 static uint64_t inline_branch_hit[CC_OP_MAX];
76 static uint64_t inline_branch_miss[CC_OP_MAX];
77 #endif
78
79 static uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
80 {
81 if (!(s->tb->flags & FLAG_MASK_64)) {
82 if (s->tb->flags & FLAG_MASK_32) {
83 return pc | 0x80000000;
84 }
85 }
86 return pc;
87 }
88
89 void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
90 int flags)
91 {
92 int i;
93
94 if (env->cc_op > 3) {
95 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
96 env->psw.mask, env->psw.addr, cc_name(env->cc_op));
97 } else {
98 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
99 env->psw.mask, env->psw.addr, env->cc_op);
100 }
101
102 for (i = 0; i < 16; i++) {
103 cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
104 if ((i % 4) == 3) {
105 cpu_fprintf(f, "\n");
106 } else {
107 cpu_fprintf(f, " ");
108 }
109 }
110
111 for (i = 0; i < 16; i++) {
112 cpu_fprintf(f, "F%02d=%016" PRIx64, i, env->fregs[i].ll);
113 if ((i % 4) == 3) {
114 cpu_fprintf(f, "\n");
115 } else {
116 cpu_fprintf(f, " ");
117 }
118 }
119
120 #ifndef CONFIG_USER_ONLY
121 for (i = 0; i < 16; i++) {
122 cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
123 if ((i % 4) == 3) {
124 cpu_fprintf(f, "\n");
125 } else {
126 cpu_fprintf(f, " ");
127 }
128 }
129 #endif
130
131 #ifdef DEBUG_INLINE_BRANCHES
132 for (i = 0; i < CC_OP_MAX; i++) {
133 cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
134 inline_branch_miss[i], inline_branch_hit[i]);
135 }
136 #endif
137
138 cpu_fprintf(f, "\n");
139 }
140
141 static TCGv_i64 psw_addr;
142 static TCGv_i64 psw_mask;
143
144 static TCGv_i32 cc_op;
145 static TCGv_i64 cc_src;
146 static TCGv_i64 cc_dst;
147 static TCGv_i64 cc_vr;
148
149 static char cpu_reg_names[32][4];
150 static TCGv_i64 regs[16];
151 static TCGv_i64 fregs[16];
152
153 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
154
155 void s390x_translate_init(void)
156 {
157 int i;
158
159 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
160 psw_addr = tcg_global_mem_new_i64(TCG_AREG0,
161 offsetof(CPUS390XState, psw.addr),
162 "psw_addr");
163 psw_mask = tcg_global_mem_new_i64(TCG_AREG0,
164 offsetof(CPUS390XState, psw.mask),
165 "psw_mask");
166
167 cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUS390XState, cc_op),
168 "cc_op");
169 cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_src),
170 "cc_src");
171 cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_dst),
172 "cc_dst");
173 cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_vr),
174 "cc_vr");
175
176 for (i = 0; i < 16; i++) {
177 snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i);
178 regs[i] = tcg_global_mem_new(TCG_AREG0,
179 offsetof(CPUS390XState, regs[i]),
180 cpu_reg_names[i]);
181 }
182
183 for (i = 0; i < 16; i++) {
184 snprintf(cpu_reg_names[i + 16], sizeof(cpu_reg_names[0]), "f%d", i);
185 fregs[i] = tcg_global_mem_new(TCG_AREG0,
186 offsetof(CPUS390XState, fregs[i].d),
187 cpu_reg_names[i + 16]);
188 }
189
190 /* register helpers */
191 #define GEN_HELPER 2
192 #include "helper.h"
193 }
194
195 static TCGv_i64 load_reg(int reg)
196 {
197 TCGv_i64 r = tcg_temp_new_i64();
198 tcg_gen_mov_i64(r, regs[reg]);
199 return r;
200 }
201
202 static TCGv_i64 load_freg32_i64(int reg)
203 {
204 TCGv_i64 r = tcg_temp_new_i64();
205 tcg_gen_shri_i64(r, fregs[reg], 32);
206 return r;
207 }
208
209 static void store_reg(int reg, TCGv_i64 v)
210 {
211 tcg_gen_mov_i64(regs[reg], v);
212 }
213
214 static void store_freg(int reg, TCGv_i64 v)
215 {
216 tcg_gen_mov_i64(fregs[reg], v);
217 }
218
219 static void store_reg32_i64(int reg, TCGv_i64 v)
220 {
221 /* 32 bit register writes keep the upper half */
222 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
223 }
224
225 static void store_reg32h_i64(int reg, TCGv_i64 v)
226 {
227 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 32, 32);
228 }
229
230 static void store_freg32_i64(int reg, TCGv_i64 v)
231 {
232 tcg_gen_deposit_i64(fregs[reg], fregs[reg], v, 32, 32);
233 }
234
235 static void return_low128(TCGv_i64 dest)
236 {
237 tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl));
238 }
239
240 static void update_psw_addr(DisasContext *s)
241 {
242 /* psw.addr */
243 tcg_gen_movi_i64(psw_addr, s->pc);
244 }
245
246 static void update_cc_op(DisasContext *s)
247 {
248 if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
249 tcg_gen_movi_i32(cc_op, s->cc_op);
250 }
251 }
252
253 static void potential_page_fault(DisasContext *s)
254 {
255 update_psw_addr(s);
256 update_cc_op(s);
257 }
258
259 static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
260 {
261 return (uint64_t)cpu_lduw_code(env, pc);
262 }
263
264 static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
265 {
266 return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
267 }
268
269 static inline uint64_t ld_code6(CPUS390XState *env, uint64_t pc)
270 {
271 return (ld_code2(env, pc) << 32) | ld_code4(env, pc + 2);
272 }
273
274 static int get_mem_index(DisasContext *s)
275 {
276 switch (s->tb->flags & FLAG_MASK_ASC) {
277 case PSW_ASC_PRIMARY >> 32:
278 return 0;
279 case PSW_ASC_SECONDARY >> 32:
280 return 1;
281 case PSW_ASC_HOME >> 32:
282 return 2;
283 default:
284 tcg_abort();
285 break;
286 }
287 }
288
289 static void gen_exception(int excp)
290 {
291 TCGv_i32 tmp = tcg_const_i32(excp);
292 gen_helper_exception(cpu_env, tmp);
293 tcg_temp_free_i32(tmp);
294 }
295
296 static void gen_program_exception(DisasContext *s, int code)
297 {
298 TCGv_i32 tmp;
299
300 /* Remember what pgm exeption this was. */
301 tmp = tcg_const_i32(code);
302 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
303 tcg_temp_free_i32(tmp);
304
305 tmp = tcg_const_i32(s->next_pc - s->pc);
306 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen));
307 tcg_temp_free_i32(tmp);
308
309 /* Advance past instruction. */
310 s->pc = s->next_pc;
311 update_psw_addr(s);
312
313 /* Save off cc. */
314 update_cc_op(s);
315
316 /* Trigger exception. */
317 gen_exception(EXCP_PGM);
318 }
319
320 static inline void gen_illegal_opcode(DisasContext *s)
321 {
322 gen_program_exception(s, PGM_SPECIFICATION);
323 }
324
325 static inline void check_privileged(DisasContext *s)
326 {
327 if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
328 gen_program_exception(s, PGM_PRIVILEGED);
329 }
330 }
331
332 static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
333 {
334 TCGv_i64 tmp;
335
336 /* 31-bitify the immediate part; register contents are dealt with below */
337 if (!(s->tb->flags & FLAG_MASK_64)) {
338 d2 &= 0x7fffffffUL;
339 }
340
341 if (x2) {
342 if (d2) {
343 tmp = tcg_const_i64(d2);
344 tcg_gen_add_i64(tmp, tmp, regs[x2]);
345 } else {
346 tmp = load_reg(x2);
347 }
348 if (b2) {
349 tcg_gen_add_i64(tmp, tmp, regs[b2]);
350 }
351 } else if (b2) {
352 if (d2) {
353 tmp = tcg_const_i64(d2);
354 tcg_gen_add_i64(tmp, tmp, regs[b2]);
355 } else {
356 tmp = load_reg(b2);
357 }
358 } else {
359 tmp = tcg_const_i64(d2);
360 }
361
362 /* 31-bit mode mask if there are values loaded from registers */
363 if (!(s->tb->flags & FLAG_MASK_64) && (x2 || b2)) {
364 tcg_gen_andi_i64(tmp, tmp, 0x7fffffffUL);
365 }
366
367 return tmp;
368 }
369
370 static inline void gen_op_movi_cc(DisasContext *s, uint32_t val)
371 {
372 s->cc_op = CC_OP_CONST0 + val;
373 }
374
375 static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
376 {
377 tcg_gen_discard_i64(cc_src);
378 tcg_gen_mov_i64(cc_dst, dst);
379 tcg_gen_discard_i64(cc_vr);
380 s->cc_op = op;
381 }
382
383 static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
384 TCGv_i64 dst)
385 {
386 tcg_gen_mov_i64(cc_src, src);
387 tcg_gen_mov_i64(cc_dst, dst);
388 tcg_gen_discard_i64(cc_vr);
389 s->cc_op = op;
390 }
391
392 static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
393 TCGv_i64 dst, TCGv_i64 vr)
394 {
395 tcg_gen_mov_i64(cc_src, src);
396 tcg_gen_mov_i64(cc_dst, dst);
397 tcg_gen_mov_i64(cc_vr, vr);
398 s->cc_op = op;
399 }
400
401 static void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
402 {
403 gen_op_update1_cc_i64(s, CC_OP_NZ, val);
404 }
405
406 static void gen_set_cc_nz_f32(DisasContext *s, TCGv_i64 val)
407 {
408 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, val);
409 }
410
411 static void gen_set_cc_nz_f64(DisasContext *s, TCGv_i64 val)
412 {
413 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, val);
414 }
415
416 static void gen_set_cc_nz_f128(DisasContext *s, TCGv_i64 vh, TCGv_i64 vl)
417 {
418 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, vh, vl);
419 }
420
421 /* CC value is in env->cc_op */
422 static void set_cc_static(DisasContext *s)
423 {
424 tcg_gen_discard_i64(cc_src);
425 tcg_gen_discard_i64(cc_dst);
426 tcg_gen_discard_i64(cc_vr);
427 s->cc_op = CC_OP_STATIC;
428 }
429
430 /* calculates cc into cc_op */
431 static void gen_op_calc_cc(DisasContext *s)
432 {
433 TCGv_i32 local_cc_op;
434 TCGv_i64 dummy;
435
436 TCGV_UNUSED_I32(local_cc_op);
437 TCGV_UNUSED_I64(dummy);
438 switch (s->cc_op) {
439 default:
440 dummy = tcg_const_i64(0);
441 /* FALLTHRU */
442 case CC_OP_ADD_64:
443 case CC_OP_ADDU_64:
444 case CC_OP_ADDC_64:
445 case CC_OP_SUB_64:
446 case CC_OP_SUBU_64:
447 case CC_OP_SUBB_64:
448 case CC_OP_ADD_32:
449 case CC_OP_ADDU_32:
450 case CC_OP_ADDC_32:
451 case CC_OP_SUB_32:
452 case CC_OP_SUBU_32:
453 case CC_OP_SUBB_32:
454 local_cc_op = tcg_const_i32(s->cc_op);
455 break;
456 case CC_OP_CONST0:
457 case CC_OP_CONST1:
458 case CC_OP_CONST2:
459 case CC_OP_CONST3:
460 case CC_OP_STATIC:
461 case CC_OP_DYNAMIC:
462 break;
463 }
464
465 switch (s->cc_op) {
466 case CC_OP_CONST0:
467 case CC_OP_CONST1:
468 case CC_OP_CONST2:
469 case CC_OP_CONST3:
470 /* s->cc_op is the cc value */
471 tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
472 break;
473 case CC_OP_STATIC:
474 /* env->cc_op already is the cc value */
475 break;
476 case CC_OP_NZ:
477 case CC_OP_ABS_64:
478 case CC_OP_NABS_64:
479 case CC_OP_ABS_32:
480 case CC_OP_NABS_32:
481 case CC_OP_LTGT0_32:
482 case CC_OP_LTGT0_64:
483 case CC_OP_COMP_32:
484 case CC_OP_COMP_64:
485 case CC_OP_NZ_F32:
486 case CC_OP_NZ_F64:
487 case CC_OP_FLOGR:
488 /* 1 argument */
489 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dummy);
490 break;
491 case CC_OP_ICM:
492 case CC_OP_LTGT_32:
493 case CC_OP_LTGT_64:
494 case CC_OP_LTUGTU_32:
495 case CC_OP_LTUGTU_64:
496 case CC_OP_TM_32:
497 case CC_OP_TM_64:
498 case CC_OP_SLA_32:
499 case CC_OP_SLA_64:
500 case CC_OP_NZ_F128:
501 /* 2 arguments */
502 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
503 break;
504 case CC_OP_ADD_64:
505 case CC_OP_ADDU_64:
506 case CC_OP_ADDC_64:
507 case CC_OP_SUB_64:
508 case CC_OP_SUBU_64:
509 case CC_OP_SUBB_64:
510 case CC_OP_ADD_32:
511 case CC_OP_ADDU_32:
512 case CC_OP_ADDC_32:
513 case CC_OP_SUB_32:
514 case CC_OP_SUBU_32:
515 case CC_OP_SUBB_32:
516 /* 3 arguments */
517 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc_vr);
518 break;
519 case CC_OP_DYNAMIC:
520 /* unknown operation - assume 3 arguments and cc_op in env */
521 gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr);
522 break;
523 default:
524 tcg_abort();
525 }
526
527 if (!TCGV_IS_UNUSED_I32(local_cc_op)) {
528 tcg_temp_free_i32(local_cc_op);
529 }
530 if (!TCGV_IS_UNUSED_I64(dummy)) {
531 tcg_temp_free_i64(dummy);
532 }
533
534 /* We now have cc in cc_op as constant */
535 set_cc_static(s);
536 }
537
538 static int use_goto_tb(DisasContext *s, uint64_t dest)
539 {
540 /* NOTE: we handle the case where the TB spans two pages here */
541 return (((dest & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK)
542 || (dest & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK))
543 && !s->singlestep_enabled
544 && !(s->tb->cflags & CF_LAST_IO));
545 }
546
547 static void account_noninline_branch(DisasContext *s, int cc_op)
548 {
549 #ifdef DEBUG_INLINE_BRANCHES
550 inline_branch_miss[cc_op]++;
551 #endif
552 }
553
554 static void account_inline_branch(DisasContext *s, int cc_op)
555 {
556 #ifdef DEBUG_INLINE_BRANCHES
557 inline_branch_hit[cc_op]++;
558 #endif
559 }
560
561 /* Table of mask values to comparison codes, given a comparison as input.
562 For a true comparison CC=3 will never be set, but we treat this
563 conservatively for possible use when CC=3 indicates overflow. */
564 static const TCGCond ltgt_cond[16] = {
565 TCG_COND_NEVER, TCG_COND_NEVER, /* | | | x */
566 TCG_COND_GT, TCG_COND_NEVER, /* | | GT | x */
567 TCG_COND_LT, TCG_COND_NEVER, /* | LT | | x */
568 TCG_COND_NE, TCG_COND_NEVER, /* | LT | GT | x */
569 TCG_COND_EQ, TCG_COND_NEVER, /* EQ | | | x */
570 TCG_COND_GE, TCG_COND_NEVER, /* EQ | | GT | x */
571 TCG_COND_LE, TCG_COND_NEVER, /* EQ | LT | | x */
572 TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | LT | GT | x */
573 };
574
575 /* Table of mask values to comparison codes, given a logic op as input.
576 For such, only CC=0 and CC=1 should be possible. */
577 static const TCGCond nz_cond[16] = {
578 /* | | x | x */
579 TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER,
580 /* | NE | x | x */
581 TCG_COND_NE, TCG_COND_NE, TCG_COND_NE, TCG_COND_NE,
582 /* EQ | | x | x */
583 TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ,
584 /* EQ | NE | x | x */
585 TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS,
586 };
587
588 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
589 details required to generate a TCG comparison. */
590 static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
591 {
592 TCGCond cond;
593 enum cc_op old_cc_op = s->cc_op;
594
595 if (mask == 15 || mask == 0) {
596 c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER);
597 c->u.s32.a = cc_op;
598 c->u.s32.b = cc_op;
599 c->g1 = c->g2 = true;
600 c->is_64 = false;
601 return;
602 }
603
604 /* Find the TCG condition for the mask + cc op. */
605 switch (old_cc_op) {
606 case CC_OP_LTGT0_32:
607 case CC_OP_LTGT0_64:
608 case CC_OP_LTGT_32:
609 case CC_OP_LTGT_64:
610 cond = ltgt_cond[mask];
611 if (cond == TCG_COND_NEVER) {
612 goto do_dynamic;
613 }
614 account_inline_branch(s, old_cc_op);
615 break;
616
617 case CC_OP_LTUGTU_32:
618 case CC_OP_LTUGTU_64:
619 cond = tcg_unsigned_cond(ltgt_cond[mask]);
620 if (cond == TCG_COND_NEVER) {
621 goto do_dynamic;
622 }
623 account_inline_branch(s, old_cc_op);
624 break;
625
626 case CC_OP_NZ:
627 cond = nz_cond[mask];
628 if (cond == TCG_COND_NEVER) {
629 goto do_dynamic;
630 }
631 account_inline_branch(s, old_cc_op);
632 break;
633
634 case CC_OP_TM_32:
635 case CC_OP_TM_64:
636 switch (mask) {
637 case 8:
638 cond = TCG_COND_EQ;
639 break;
640 case 4 | 2 | 1:
641 cond = TCG_COND_NE;
642 break;
643 default:
644 goto do_dynamic;
645 }
646 account_inline_branch(s, old_cc_op);
647 break;
648
649 case CC_OP_ICM:
650 switch (mask) {
651 case 8:
652 cond = TCG_COND_EQ;
653 break;
654 case 4 | 2 | 1:
655 case 4 | 2:
656 cond = TCG_COND_NE;
657 break;
658 default:
659 goto do_dynamic;
660 }
661 account_inline_branch(s, old_cc_op);
662 break;
663
664 case CC_OP_FLOGR:
665 switch (mask & 0xa) {
666 case 8: /* src == 0 -> no one bit found */
667 cond = TCG_COND_EQ;
668 break;
669 case 2: /* src != 0 -> one bit found */
670 cond = TCG_COND_NE;
671 break;
672 default:
673 goto do_dynamic;
674 }
675 account_inline_branch(s, old_cc_op);
676 break;
677
678 default:
679 do_dynamic:
680 /* Calculate cc value. */
681 gen_op_calc_cc(s);
682 /* FALLTHRU */
683
684 case CC_OP_STATIC:
685 /* Jump based on CC. We'll load up the real cond below;
686 the assignment here merely avoids a compiler warning. */
687 account_noninline_branch(s, old_cc_op);
688 old_cc_op = CC_OP_STATIC;
689 cond = TCG_COND_NEVER;
690 break;
691 }
692
693 /* Load up the arguments of the comparison. */
694 c->is_64 = true;
695 c->g1 = c->g2 = false;
696 switch (old_cc_op) {
697 case CC_OP_LTGT0_32:
698 c->is_64 = false;
699 c->u.s32.a = tcg_temp_new_i32();
700 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_dst);
701 c->u.s32.b = tcg_const_i32(0);
702 break;
703 case CC_OP_LTGT_32:
704 case CC_OP_LTUGTU_32:
705 c->is_64 = false;
706 c->u.s32.a = tcg_temp_new_i32();
707 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_src);
708 c->u.s32.b = tcg_temp_new_i32();
709 tcg_gen_trunc_i64_i32(c->u.s32.b, cc_dst);
710 break;
711
712 case CC_OP_LTGT0_64:
713 case CC_OP_NZ:
714 case CC_OP_FLOGR:
715 c->u.s64.a = cc_dst;
716 c->u.s64.b = tcg_const_i64(0);
717 c->g1 = true;
718 break;
719 case CC_OP_LTGT_64:
720 case CC_OP_LTUGTU_64:
721 c->u.s64.a = cc_src;
722 c->u.s64.b = cc_dst;
723 c->g1 = c->g2 = true;
724 break;
725
726 case CC_OP_TM_32:
727 case CC_OP_TM_64:
728 case CC_OP_ICM:
729 c->u.s64.a = tcg_temp_new_i64();
730 c->u.s64.b = tcg_const_i64(0);
731 tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
732 break;
733
734 case CC_OP_STATIC:
735 c->is_64 = false;
736 c->u.s32.a = cc_op;
737 c->g1 = true;
738 switch (mask) {
739 case 0x8 | 0x4 | 0x2: /* cc != 3 */
740 cond = TCG_COND_NE;
741 c->u.s32.b = tcg_const_i32(3);
742 break;
743 case 0x8 | 0x4 | 0x1: /* cc != 2 */
744 cond = TCG_COND_NE;
745 c->u.s32.b = tcg_const_i32(2);
746 break;
747 case 0x8 | 0x2 | 0x1: /* cc != 1 */
748 cond = TCG_COND_NE;
749 c->u.s32.b = tcg_const_i32(1);
750 break;
751 case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
752 cond = TCG_COND_EQ;
753 c->g1 = false;
754 c->u.s32.a = tcg_temp_new_i32();
755 c->u.s32.b = tcg_const_i32(0);
756 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
757 break;
758 case 0x8 | 0x4: /* cc < 2 */
759 cond = TCG_COND_LTU;
760 c->u.s32.b = tcg_const_i32(2);
761 break;
762 case 0x8: /* cc == 0 */
763 cond = TCG_COND_EQ;
764 c->u.s32.b = tcg_const_i32(0);
765 break;
766 case 0x4 | 0x2 | 0x1: /* cc != 0 */
767 cond = TCG_COND_NE;
768 c->u.s32.b = tcg_const_i32(0);
769 break;
770 case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
771 cond = TCG_COND_NE;
772 c->g1 = false;
773 c->u.s32.a = tcg_temp_new_i32();
774 c->u.s32.b = tcg_const_i32(0);
775 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
776 break;
777 case 0x4: /* cc == 1 */
778 cond = TCG_COND_EQ;
779 c->u.s32.b = tcg_const_i32(1);
780 break;
781 case 0x2 | 0x1: /* cc > 1 */
782 cond = TCG_COND_GTU;
783 c->u.s32.b = tcg_const_i32(1);
784 break;
785 case 0x2: /* cc == 2 */
786 cond = TCG_COND_EQ;
787 c->u.s32.b = tcg_const_i32(2);
788 break;
789 case 0x1: /* cc == 3 */
790 cond = TCG_COND_EQ;
791 c->u.s32.b = tcg_const_i32(3);
792 break;
793 default:
794 /* CC is masked by something else: (8 >> cc) & mask. */
795 cond = TCG_COND_NE;
796 c->g1 = false;
797 c->u.s32.a = tcg_const_i32(8);
798 c->u.s32.b = tcg_const_i32(0);
799 tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op);
800 tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
801 break;
802 }
803 break;
804
805 default:
806 abort();
807 }
808 c->cond = cond;
809 }
810
811 static void free_compare(DisasCompare *c)
812 {
813 if (!c->g1) {
814 if (c->is_64) {
815 tcg_temp_free_i64(c->u.s64.a);
816 } else {
817 tcg_temp_free_i32(c->u.s32.a);
818 }
819 }
820 if (!c->g2) {
821 if (c->is_64) {
822 tcg_temp_free_i64(c->u.s64.b);
823 } else {
824 tcg_temp_free_i32(c->u.s32.b);
825 }
826 }
827 }
828
829 /* ====================================================================== */
830 /* Define the insn format enumeration. */
831 #define F0(N) FMT_##N,
832 #define F1(N, X1) F0(N)
833 #define F2(N, X1, X2) F0(N)
834 #define F3(N, X1, X2, X3) F0(N)
835 #define F4(N, X1, X2, X3, X4) F0(N)
836 #define F5(N, X1, X2, X3, X4, X5) F0(N)
837
838 typedef enum {
839 #include "insn-format.def"
840 } DisasFormat;
841
842 #undef F0
843 #undef F1
844 #undef F2
845 #undef F3
846 #undef F4
847 #undef F5
848
849 /* Define a structure to hold the decoded fields. We'll store each inside
850 an array indexed by an enum. In order to conserve memory, we'll arrange
851 for fields that do not exist at the same time to overlap, thus the "C"
852 for compact. For checking purposes there is an "O" for original index
853 as well that will be applied to availability bitmaps. */
854
855 enum DisasFieldIndexO {
856 FLD_O_r1,
857 FLD_O_r2,
858 FLD_O_r3,
859 FLD_O_m1,
860 FLD_O_m3,
861 FLD_O_m4,
862 FLD_O_b1,
863 FLD_O_b2,
864 FLD_O_b4,
865 FLD_O_d1,
866 FLD_O_d2,
867 FLD_O_d4,
868 FLD_O_x2,
869 FLD_O_l1,
870 FLD_O_l2,
871 FLD_O_i1,
872 FLD_O_i2,
873 FLD_O_i3,
874 FLD_O_i4,
875 FLD_O_i5
876 };
877
878 enum DisasFieldIndexC {
879 FLD_C_r1 = 0,
880 FLD_C_m1 = 0,
881 FLD_C_b1 = 0,
882 FLD_C_i1 = 0,
883
884 FLD_C_r2 = 1,
885 FLD_C_b2 = 1,
886 FLD_C_i2 = 1,
887
888 FLD_C_r3 = 2,
889 FLD_C_m3 = 2,
890 FLD_C_i3 = 2,
891
892 FLD_C_m4 = 3,
893 FLD_C_b4 = 3,
894 FLD_C_i4 = 3,
895 FLD_C_l1 = 3,
896
897 FLD_C_i5 = 4,
898 FLD_C_d1 = 4,
899
900 FLD_C_d2 = 5,
901
902 FLD_C_d4 = 6,
903 FLD_C_x2 = 6,
904 FLD_C_l2 = 6,
905
906 NUM_C_FIELD = 7
907 };
908
909 struct DisasFields {
910 unsigned op:8;
911 unsigned op2:8;
912 unsigned presentC:16;
913 unsigned int presentO;
914 int c[NUM_C_FIELD];
915 };
916
917 /* This is the way fields are to be accessed out of DisasFields. */
918 #define have_field(S, F) have_field1((S), FLD_O_##F)
919 #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
920
921 static bool have_field1(const DisasFields *f, enum DisasFieldIndexO c)
922 {
923 return (f->presentO >> c) & 1;
924 }
925
926 static int get_field1(const DisasFields *f, enum DisasFieldIndexO o,
927 enum DisasFieldIndexC c)
928 {
929 assert(have_field1(f, o));
930 return f->c[c];
931 }
932
933 /* Describe the layout of each field in each format. */
934 typedef struct DisasField {
935 unsigned int beg:8;
936 unsigned int size:8;
937 unsigned int type:2;
938 unsigned int indexC:6;
939 enum DisasFieldIndexO indexO:8;
940 } DisasField;
941
942 typedef struct DisasFormatInfo {
943 DisasField op[NUM_C_FIELD];
944 } DisasFormatInfo;
945
946 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
947 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
948 #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
949 { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
950 #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
951 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
952 { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
953 #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
954 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
955 #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
956 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
957 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
958 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
959 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
960
961 #define F0(N) { { } },
962 #define F1(N, X1) { { X1 } },
963 #define F2(N, X1, X2) { { X1, X2 } },
964 #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
965 #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
966 #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
967
968 static const DisasFormatInfo format_info[] = {
969 #include "insn-format.def"
970 };
971
972 #undef F0
973 #undef F1
974 #undef F2
975 #undef F3
976 #undef F4
977 #undef F5
978 #undef R
979 #undef M
980 #undef BD
981 #undef BXD
982 #undef BDL
983 #undef BXDL
984 #undef I
985 #undef L
986
987 /* Generally, we'll extract operands into this structures, operate upon
988 them, and store them back. See the "in1", "in2", "prep", "wout" sets
989 of routines below for more details. */
990 typedef struct {
991 bool g_out, g_out2, g_in1, g_in2;
992 TCGv_i64 out, out2, in1, in2;
993 TCGv_i64 addr1;
994 } DisasOps;
995
996 /* Return values from translate_one, indicating the state of the TB. */
997 typedef enum {
998 /* Continue the TB. */
999 NO_EXIT,
1000 /* We have emitted one or more goto_tb. No fixup required. */
1001 EXIT_GOTO_TB,
1002 /* We are not using a goto_tb (for whatever reason), but have updated
1003 the PC (for whatever reason), so there's no need to do it again on
1004 exiting the TB. */
1005 EXIT_PC_UPDATED,
1006 /* We are exiting the TB, but have neither emitted a goto_tb, nor
1007 updated the PC for the next instruction to be executed. */
1008 EXIT_PC_STALE,
1009 /* We are ending the TB with a noreturn function call, e.g. longjmp.
1010 No following code will be executed. */
1011 EXIT_NORETURN,
1012 } ExitStatus;
1013
1014 typedef enum DisasFacility {
1015 FAC_Z, /* zarch (default) */
1016 FAC_CASS, /* compare and swap and store */
1017 FAC_CASS2, /* compare and swap and store 2*/
1018 FAC_DFP, /* decimal floating point */
1019 FAC_DFPR, /* decimal floating point rounding */
1020 FAC_DO, /* distinct operands */
1021 FAC_EE, /* execute extensions */
1022 FAC_EI, /* extended immediate */
1023 FAC_FPE, /* floating point extension */
1024 FAC_FPSSH, /* floating point support sign handling */
1025 FAC_FPRGR, /* FPR-GR transfer */
1026 FAC_GIE, /* general instructions extension */
1027 FAC_HFP_MA, /* HFP multiply-and-add/subtract */
1028 FAC_HW, /* high-word */
1029 FAC_IEEEE_SIM, /* IEEE exception sumilation */
1030 FAC_LOC, /* load/store on condition */
1031 FAC_LD, /* long displacement */
1032 FAC_PC, /* population count */
1033 FAC_SCF, /* store clock fast */
1034 FAC_SFLE, /* store facility list extended */
1035 } DisasFacility;
1036
1037 struct DisasInsn {
1038 unsigned opc:16;
1039 DisasFormat fmt:6;
1040 DisasFacility fac:6;
1041
1042 const char *name;
1043
1044 void (*help_in1)(DisasContext *, DisasFields *, DisasOps *);
1045 void (*help_in2)(DisasContext *, DisasFields *, DisasOps *);
1046 void (*help_prep)(DisasContext *, DisasFields *, DisasOps *);
1047 void (*help_wout)(DisasContext *, DisasFields *, DisasOps *);
1048 void (*help_cout)(DisasContext *, DisasOps *);
1049 ExitStatus (*help_op)(DisasContext *, DisasOps *);
1050
1051 uint64_t data;
1052 };
1053
1054 /* ====================================================================== */
1055 /* Miscelaneous helpers, used by several operations. */
1056
1057 static void help_l2_shift(DisasContext *s, DisasFields *f,
1058 DisasOps *o, int mask)
1059 {
1060 int b2 = get_field(f, b2);
1061 int d2 = get_field(f, d2);
1062
1063 if (b2 == 0) {
1064 o->in2 = tcg_const_i64(d2 & mask);
1065 } else {
1066 o->in2 = get_address(s, 0, b2, d2);
1067 tcg_gen_andi_i64(o->in2, o->in2, mask);
1068 }
1069 }
1070
1071 static ExitStatus help_goto_direct(DisasContext *s, uint64_t dest)
1072 {
1073 if (dest == s->next_pc) {
1074 return NO_EXIT;
1075 }
1076 if (use_goto_tb(s, dest)) {
1077 update_cc_op(s);
1078 tcg_gen_goto_tb(0);
1079 tcg_gen_movi_i64(psw_addr, dest);
1080 tcg_gen_exit_tb((tcg_target_long)s->tb);
1081 return EXIT_GOTO_TB;
1082 } else {
1083 tcg_gen_movi_i64(psw_addr, dest);
1084 return EXIT_PC_UPDATED;
1085 }
1086 }
1087
1088 static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
1089 bool is_imm, int imm, TCGv_i64 cdest)
1090 {
1091 ExitStatus ret;
1092 uint64_t dest = s->pc + 2 * imm;
1093 int lab;
1094
1095 /* Take care of the special cases first. */
1096 if (c->cond == TCG_COND_NEVER) {
1097 ret = NO_EXIT;
1098 goto egress;
1099 }
1100 if (is_imm) {
1101 if (dest == s->next_pc) {
1102 /* Branch to next. */
1103 ret = NO_EXIT;
1104 goto egress;
1105 }
1106 if (c->cond == TCG_COND_ALWAYS) {
1107 ret = help_goto_direct(s, dest);
1108 goto egress;
1109 }
1110 } else {
1111 if (TCGV_IS_UNUSED_I64(cdest)) {
1112 /* E.g. bcr %r0 -> no branch. */
1113 ret = NO_EXIT;
1114 goto egress;
1115 }
1116 if (c->cond == TCG_COND_ALWAYS) {
1117 tcg_gen_mov_i64(psw_addr, cdest);
1118 ret = EXIT_PC_UPDATED;
1119 goto egress;
1120 }
1121 }
1122
1123 if (use_goto_tb(s, s->next_pc)) {
1124 if (is_imm && use_goto_tb(s, dest)) {
1125 /* Both exits can use goto_tb. */
1126 update_cc_op(s);
1127
1128 lab = gen_new_label();
1129 if (c->is_64) {
1130 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1131 } else {
1132 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1133 }
1134
1135 /* Branch not taken. */
1136 tcg_gen_goto_tb(0);
1137 tcg_gen_movi_i64(psw_addr, s->next_pc);
1138 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
1139
1140 /* Branch taken. */
1141 gen_set_label(lab);
1142 tcg_gen_goto_tb(1);
1143 tcg_gen_movi_i64(psw_addr, dest);
1144 tcg_gen_exit_tb((tcg_target_long)s->tb + 1);
1145
1146 ret = EXIT_GOTO_TB;
1147 } else {
1148 /* Fallthru can use goto_tb, but taken branch cannot. */
1149 /* Store taken branch destination before the brcond. This
1150 avoids having to allocate a new local temp to hold it.
1151 We'll overwrite this in the not taken case anyway. */
1152 if (!is_imm) {
1153 tcg_gen_mov_i64(psw_addr, cdest);
1154 }
1155
1156 lab = gen_new_label();
1157 if (c->is_64) {
1158 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1159 } else {
1160 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1161 }
1162
1163 /* Branch not taken. */
1164 update_cc_op(s);
1165 tcg_gen_goto_tb(0);
1166 tcg_gen_movi_i64(psw_addr, s->next_pc);
1167 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
1168
1169 gen_set_label(lab);
1170 if (is_imm) {
1171 tcg_gen_movi_i64(psw_addr, dest);
1172 }
1173 ret = EXIT_PC_UPDATED;
1174 }
1175 } else {
1176 /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
1177 Most commonly we're single-stepping or some other condition that
1178 disables all use of goto_tb. Just update the PC and exit. */
1179
1180 TCGv_i64 next = tcg_const_i64(s->next_pc);
1181 if (is_imm) {
1182 cdest = tcg_const_i64(dest);
1183 }
1184
1185 if (c->is_64) {
1186 tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b,
1187 cdest, next);
1188 } else {
1189 TCGv_i32 t0 = tcg_temp_new_i32();
1190 TCGv_i64 t1 = tcg_temp_new_i64();
1191 TCGv_i64 z = tcg_const_i64(0);
1192 tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b);
1193 tcg_gen_extu_i32_i64(t1, t0);
1194 tcg_temp_free_i32(t0);
1195 tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next);
1196 tcg_temp_free_i64(t1);
1197 tcg_temp_free_i64(z);
1198 }
1199
1200 if (is_imm) {
1201 tcg_temp_free_i64(cdest);
1202 }
1203 tcg_temp_free_i64(next);
1204
1205 ret = EXIT_PC_UPDATED;
1206 }
1207
1208 egress:
1209 free_compare(c);
1210 return ret;
1211 }
1212
1213 /* ====================================================================== */
1214 /* The operations. These perform the bulk of the work for any insn,
1215 usually after the operands have been loaded and output initialized. */
1216
1217 static ExitStatus op_abs(DisasContext *s, DisasOps *o)
1218 {
1219 gen_helper_abs_i64(o->out, o->in2);
1220 return NO_EXIT;
1221 }
1222
1223 static ExitStatus op_absf32(DisasContext *s, DisasOps *o)
1224 {
1225 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffull);
1226 return NO_EXIT;
1227 }
1228
1229 static ExitStatus op_absf64(DisasContext *s, DisasOps *o)
1230 {
1231 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull);
1232 return NO_EXIT;
1233 }
1234
1235 static ExitStatus op_absf128(DisasContext *s, DisasOps *o)
1236 {
1237 tcg_gen_andi_i64(o->out, o->in1, 0x7fffffffffffffffull);
1238 tcg_gen_mov_i64(o->out2, o->in2);
1239 return NO_EXIT;
1240 }
1241
1242 static ExitStatus op_add(DisasContext *s, DisasOps *o)
1243 {
1244 tcg_gen_add_i64(o->out, o->in1, o->in2);
1245 return NO_EXIT;
1246 }
1247
1248 static ExitStatus op_addc(DisasContext *s, DisasOps *o)
1249 {
1250 TCGv_i64 cc;
1251
1252 tcg_gen_add_i64(o->out, o->in1, o->in2);
1253
1254 /* XXX possible optimization point */
1255 gen_op_calc_cc(s);
1256 cc = tcg_temp_new_i64();
1257 tcg_gen_extu_i32_i64(cc, cc_op);
1258 tcg_gen_shri_i64(cc, cc, 1);
1259
1260 tcg_gen_add_i64(o->out, o->out, cc);
1261 tcg_temp_free_i64(cc);
1262 return NO_EXIT;
1263 }
1264
1265 static ExitStatus op_aeb(DisasContext *s, DisasOps *o)
1266 {
1267 gen_helper_aeb(o->out, cpu_env, o->in1, o->in2);
1268 return NO_EXIT;
1269 }
1270
1271 static ExitStatus op_adb(DisasContext *s, DisasOps *o)
1272 {
1273 gen_helper_adb(o->out, cpu_env, o->in1, o->in2);
1274 return NO_EXIT;
1275 }
1276
1277 static ExitStatus op_axb(DisasContext *s, DisasOps *o)
1278 {
1279 gen_helper_axb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
1280 return_low128(o->out2);
1281 return NO_EXIT;
1282 }
1283
1284 static ExitStatus op_and(DisasContext *s, DisasOps *o)
1285 {
1286 tcg_gen_and_i64(o->out, o->in1, o->in2);
1287 return NO_EXIT;
1288 }
1289
1290 static ExitStatus op_andi(DisasContext *s, DisasOps *o)
1291 {
1292 int shift = s->insn->data & 0xff;
1293 int size = s->insn->data >> 8;
1294 uint64_t mask = ((1ull << size) - 1) << shift;
1295
1296 assert(!o->g_in2);
1297 tcg_gen_shli_i64(o->in2, o->in2, shift);
1298 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
1299 tcg_gen_and_i64(o->out, o->in1, o->in2);
1300
1301 /* Produce the CC from only the bits manipulated. */
1302 tcg_gen_andi_i64(cc_dst, o->out, mask);
1303 set_cc_nz_u64(s, cc_dst);
1304 return NO_EXIT;
1305 }
1306
1307 static ExitStatus op_bas(DisasContext *s, DisasOps *o)
1308 {
1309 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1310 if (!TCGV_IS_UNUSED_I64(o->in2)) {
1311 tcg_gen_mov_i64(psw_addr, o->in2);
1312 return EXIT_PC_UPDATED;
1313 } else {
1314 return NO_EXIT;
1315 }
1316 }
1317
1318 static ExitStatus op_basi(DisasContext *s, DisasOps *o)
1319 {
1320 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1321 return help_goto_direct(s, s->pc + 2 * get_field(s->fields, i2));
1322 }
1323
1324 static ExitStatus op_bc(DisasContext *s, DisasOps *o)
1325 {
1326 int m1 = get_field(s->fields, m1);
1327 bool is_imm = have_field(s->fields, i2);
1328 int imm = is_imm ? get_field(s->fields, i2) : 0;
1329 DisasCompare c;
1330
1331 disas_jcc(s, &c, m1);
1332 return help_branch(s, &c, is_imm, imm, o->in2);
1333 }
1334
1335 static ExitStatus op_bct32(DisasContext *s, DisasOps *o)
1336 {
1337 int r1 = get_field(s->fields, r1);
1338 bool is_imm = have_field(s->fields, i2);
1339 int imm = is_imm ? get_field(s->fields, i2) : 0;
1340 DisasCompare c;
1341 TCGv_i64 t;
1342
1343 c.cond = TCG_COND_NE;
1344 c.is_64 = false;
1345 c.g1 = false;
1346 c.g2 = false;
1347
1348 t = tcg_temp_new_i64();
1349 tcg_gen_subi_i64(t, regs[r1], 1);
1350 store_reg32_i64(r1, t);
1351 c.u.s32.a = tcg_temp_new_i32();
1352 c.u.s32.b = tcg_const_i32(0);
1353 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
1354 tcg_temp_free_i64(t);
1355
1356 return help_branch(s, &c, is_imm, imm, o->in2);
1357 }
1358
1359 static ExitStatus op_bct64(DisasContext *s, DisasOps *o)
1360 {
1361 int r1 = get_field(s->fields, r1);
1362 bool is_imm = have_field(s->fields, i2);
1363 int imm = is_imm ? get_field(s->fields, i2) : 0;
1364 DisasCompare c;
1365
1366 c.cond = TCG_COND_NE;
1367 c.is_64 = true;
1368 c.g1 = true;
1369 c.g2 = false;
1370
1371 tcg_gen_subi_i64(regs[r1], regs[r1], 1);
1372 c.u.s64.a = regs[r1];
1373 c.u.s64.b = tcg_const_i64(0);
1374
1375 return help_branch(s, &c, is_imm, imm, o->in2);
1376 }
1377
1378 static ExitStatus op_bx32(DisasContext *s, DisasOps *o)
1379 {
1380 int r1 = get_field(s->fields, r1);
1381 int r3 = get_field(s->fields, r3);
1382 bool is_imm = have_field(s->fields, i2);
1383 int imm = is_imm ? get_field(s->fields, i2) : 0;
1384 DisasCompare c;
1385 TCGv_i64 t;
1386
1387 c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT);
1388 c.is_64 = false;
1389 c.g1 = false;
1390 c.g2 = false;
1391
1392 t = tcg_temp_new_i64();
1393 tcg_gen_add_i64(t, regs[r1], regs[r3]);
1394 c.u.s32.a = tcg_temp_new_i32();
1395 c.u.s32.b = tcg_temp_new_i32();
1396 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
1397 tcg_gen_trunc_i64_i32(c.u.s32.b, regs[r3 | 1]);
1398 store_reg32_i64(r1, t);
1399 tcg_temp_free_i64(t);
1400
1401 return help_branch(s, &c, is_imm, imm, o->in2);
1402 }
1403
1404 static ExitStatus op_bx64(DisasContext *s, DisasOps *o)
1405 {
1406 int r1 = get_field(s->fields, r1);
1407 int r3 = get_field(s->fields, r3);
1408 bool is_imm = have_field(s->fields, i2);
1409 int imm = is_imm ? get_field(s->fields, i2) : 0;
1410 DisasCompare c;
1411
1412 c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT);
1413 c.is_64 = true;
1414
1415 if (r1 == (r3 | 1)) {
1416 c.u.s64.b = load_reg(r3 | 1);
1417 c.g2 = false;
1418 } else {
1419 c.u.s64.b = regs[r3 | 1];
1420 c.g2 = true;
1421 }
1422
1423 tcg_gen_add_i64(regs[r1], regs[r1], regs[r3]);
1424 c.u.s64.a = regs[r1];
1425 c.g1 = true;
1426
1427 return help_branch(s, &c, is_imm, imm, o->in2);
1428 }
1429
1430 static ExitStatus op_cj(DisasContext *s, DisasOps *o)
1431 {
1432 int imm, m3 = get_field(s->fields, m3);
1433 bool is_imm;
1434 DisasCompare c;
1435
1436 /* Bit 3 of the m3 field is reserved and should be zero.
1437 Choose to ignore it wrt the ltgt_cond table above. */
1438 c.cond = ltgt_cond[m3 & 14];
1439 if (s->insn->data) {
1440 c.cond = tcg_unsigned_cond(c.cond);
1441 }
1442 c.is_64 = c.g1 = c.g2 = true;
1443 c.u.s64.a = o->in1;
1444 c.u.s64.b = o->in2;
1445
1446 is_imm = have_field(s->fields, i4);
1447 if (is_imm) {
1448 imm = get_field(s->fields, i4);
1449 } else {
1450 imm = 0;
1451 o->out = get_address(s, 0, get_field(s->fields, b4),
1452 get_field(s->fields, d4));
1453 }
1454
1455 return help_branch(s, &c, is_imm, imm, o->out);
1456 }
1457
1458 static ExitStatus op_ceb(DisasContext *s, DisasOps *o)
1459 {
1460 gen_helper_ceb(cc_op, cpu_env, o->in1, o->in2);
1461 set_cc_static(s);
1462 return NO_EXIT;
1463 }
1464
1465 static ExitStatus op_cdb(DisasContext *s, DisasOps *o)
1466 {
1467 gen_helper_cdb(cc_op, cpu_env, o->in1, o->in2);
1468 set_cc_static(s);
1469 return NO_EXIT;
1470 }
1471
1472 static ExitStatus op_cxb(DisasContext *s, DisasOps *o)
1473 {
1474 gen_helper_cxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2);
1475 set_cc_static(s);
1476 return NO_EXIT;
1477 }
1478
1479 static ExitStatus op_cfeb(DisasContext *s, DisasOps *o)
1480 {
1481 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1482 gen_helper_cfeb(o->out, cpu_env, o->in2, m3);
1483 tcg_temp_free_i32(m3);
1484 gen_set_cc_nz_f32(s, o->in2);
1485 return NO_EXIT;
1486 }
1487
1488 static ExitStatus op_cfdb(DisasContext *s, DisasOps *o)
1489 {
1490 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1491 gen_helper_cfdb(o->out, cpu_env, o->in2, m3);
1492 tcg_temp_free_i32(m3);
1493 gen_set_cc_nz_f64(s, o->in2);
1494 return NO_EXIT;
1495 }
1496
1497 static ExitStatus op_cfxb(DisasContext *s, DisasOps *o)
1498 {
1499 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1500 gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m3);
1501 tcg_temp_free_i32(m3);
1502 gen_set_cc_nz_f128(s, o->in1, o->in2);
1503 return NO_EXIT;
1504 }
1505
1506 static ExitStatus op_cgeb(DisasContext *s, DisasOps *o)
1507 {
1508 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1509 gen_helper_cgeb(o->out, cpu_env, o->in2, m3);
1510 tcg_temp_free_i32(m3);
1511 gen_set_cc_nz_f32(s, o->in2);
1512 return NO_EXIT;
1513 }
1514
1515 static ExitStatus op_cgdb(DisasContext *s, DisasOps *o)
1516 {
1517 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1518 gen_helper_cgdb(o->out, cpu_env, o->in2, m3);
1519 tcg_temp_free_i32(m3);
1520 gen_set_cc_nz_f64(s, o->in2);
1521 return NO_EXIT;
1522 }
1523
1524 static ExitStatus op_cgxb(DisasContext *s, DisasOps *o)
1525 {
1526 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1527 gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m3);
1528 tcg_temp_free_i32(m3);
1529 gen_set_cc_nz_f128(s, o->in1, o->in2);
1530 return NO_EXIT;
1531 }
1532
1533 static ExitStatus op_cegb(DisasContext *s, DisasOps *o)
1534 {
1535 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1536 gen_helper_cegb(o->out, cpu_env, o->in2, m3);
1537 tcg_temp_free_i32(m3);
1538 return NO_EXIT;
1539 }
1540
1541 static ExitStatus op_cdgb(DisasContext *s, DisasOps *o)
1542 {
1543 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1544 gen_helper_cdgb(o->out, cpu_env, o->in2, m3);
1545 tcg_temp_free_i32(m3);
1546 return NO_EXIT;
1547 }
1548
1549 static ExitStatus op_cxgb(DisasContext *s, DisasOps *o)
1550 {
1551 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1552 gen_helper_cxgb(o->out, cpu_env, o->in2, m3);
1553 tcg_temp_free_i32(m3);
1554 return_low128(o->out2);
1555 return NO_EXIT;
1556 }
1557
1558 static ExitStatus op_cksm(DisasContext *s, DisasOps *o)
1559 {
1560 int r2 = get_field(s->fields, r2);
1561 TCGv_i64 len = tcg_temp_new_i64();
1562
1563 potential_page_fault(s);
1564 gen_helper_cksm(len, cpu_env, o->in1, o->in2, regs[r2 + 1]);
1565 set_cc_static(s);
1566 return_low128(o->out);
1567
1568 tcg_gen_add_i64(regs[r2], regs[r2], len);
1569 tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len);
1570 tcg_temp_free_i64(len);
1571
1572 return NO_EXIT;
1573 }
1574
1575 static ExitStatus op_clc(DisasContext *s, DisasOps *o)
1576 {
1577 int l = get_field(s->fields, l1);
1578 TCGv_i32 vl;
1579
1580 switch (l + 1) {
1581 case 1:
1582 tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s));
1583 tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s));
1584 break;
1585 case 2:
1586 tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s));
1587 tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s));
1588 break;
1589 case 4:
1590 tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s));
1591 tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s));
1592 break;
1593 case 8:
1594 tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s));
1595 tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
1596 break;
1597 default:
1598 potential_page_fault(s);
1599 vl = tcg_const_i32(l);
1600 gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
1601 tcg_temp_free_i32(vl);
1602 set_cc_static(s);
1603 return NO_EXIT;
1604 }
1605 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
1606 return NO_EXIT;
1607 }
1608
1609 static ExitStatus op_clcle(DisasContext *s, DisasOps *o)
1610 {
1611 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1612 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
1613 potential_page_fault(s);
1614 gen_helper_clcle(cc_op, cpu_env, r1, o->in2, r3);
1615 tcg_temp_free_i32(r1);
1616 tcg_temp_free_i32(r3);
1617 set_cc_static(s);
1618 return NO_EXIT;
1619 }
1620
1621 static ExitStatus op_clm(DisasContext *s, DisasOps *o)
1622 {
1623 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1624 TCGv_i32 t1 = tcg_temp_new_i32();
1625 tcg_gen_trunc_i64_i32(t1, o->in1);
1626 potential_page_fault(s);
1627 gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2);
1628 set_cc_static(s);
1629 tcg_temp_free_i32(t1);
1630 tcg_temp_free_i32(m3);
1631 return NO_EXIT;
1632 }
1633
1634 static ExitStatus op_clst(DisasContext *s, DisasOps *o)
1635 {
1636 potential_page_fault(s);
1637 gen_helper_clst(o->in1, cpu_env, regs[0], o->in1, o->in2);
1638 set_cc_static(s);
1639 return_low128(o->in2);
1640 return NO_EXIT;
1641 }
1642
1643 static ExitStatus op_cs(DisasContext *s, DisasOps *o)
1644 {
1645 int r3 = get_field(s->fields, r3);
1646 potential_page_fault(s);
1647 gen_helper_cs(o->out, cpu_env, o->in1, o->in2, regs[r3]);
1648 set_cc_static(s);
1649 return NO_EXIT;
1650 }
1651
1652 static ExitStatus op_csg(DisasContext *s, DisasOps *o)
1653 {
1654 int r3 = get_field(s->fields, r3);
1655 potential_page_fault(s);
1656 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, regs[r3]);
1657 set_cc_static(s);
1658 return NO_EXIT;
1659 }
1660
1661 #ifndef CONFIG_USER_ONLY
1662 static ExitStatus op_csp(DisasContext *s, DisasOps *o)
1663 {
1664 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1665 check_privileged(s);
1666 gen_helper_csp(cc_op, cpu_env, r1, o->in2);
1667 tcg_temp_free_i32(r1);
1668 set_cc_static(s);
1669 return NO_EXIT;
1670 }
1671 #endif
1672
1673 static ExitStatus op_cds(DisasContext *s, DisasOps *o)
1674 {
1675 int r3 = get_field(s->fields, r3);
1676 TCGv_i64 in3 = tcg_temp_new_i64();
1677 tcg_gen_deposit_i64(in3, regs[r3 + 1], regs[r3], 32, 32);
1678 potential_page_fault(s);
1679 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, in3);
1680 tcg_temp_free_i64(in3);
1681 set_cc_static(s);
1682 return NO_EXIT;
1683 }
1684
1685 static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
1686 {
1687 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1688 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
1689 potential_page_fault(s);
1690 /* XXX rewrite in tcg */
1691 gen_helper_cdsg(cc_op, cpu_env, r1, o->in2, r3);
1692 set_cc_static(s);
1693 return NO_EXIT;
1694 }
1695
1696 static ExitStatus op_cvd(DisasContext *s, DisasOps *o)
1697 {
1698 TCGv_i64 t1 = tcg_temp_new_i64();
1699 TCGv_i32 t2 = tcg_temp_new_i32();
1700 tcg_gen_trunc_i64_i32(t2, o->in1);
1701 gen_helper_cvd(t1, t2);
1702 tcg_temp_free_i32(t2);
1703 tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
1704 tcg_temp_free_i64(t1);
1705 return NO_EXIT;
1706 }
1707
1708 #ifndef CONFIG_USER_ONLY
1709 static ExitStatus op_diag(DisasContext *s, DisasOps *o)
1710 {
1711 TCGv_i32 tmp;
1712
1713 check_privileged(s);
1714 potential_page_fault(s);
1715
1716 /* We pretend the format is RX_a so that D2 is the field we want. */
1717 tmp = tcg_const_i32(get_field(s->fields, d2) & 0xfff);
1718 gen_helper_diag(regs[2], cpu_env, tmp, regs[2], regs[1]);
1719 tcg_temp_free_i32(tmp);
1720 return NO_EXIT;
1721 }
1722 #endif
1723
1724 static ExitStatus op_divs32(DisasContext *s, DisasOps *o)
1725 {
1726 gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2);
1727 return_low128(o->out);
1728 return NO_EXIT;
1729 }
1730
1731 static ExitStatus op_divu32(DisasContext *s, DisasOps *o)
1732 {
1733 gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2);
1734 return_low128(o->out);
1735 return NO_EXIT;
1736 }
1737
1738 static ExitStatus op_divs64(DisasContext *s, DisasOps *o)
1739 {
1740 gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2);
1741 return_low128(o->out);
1742 return NO_EXIT;
1743 }
1744
1745 static ExitStatus op_divu64(DisasContext *s, DisasOps *o)
1746 {
1747 gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2);
1748 return_low128(o->out);
1749 return NO_EXIT;
1750 }
1751
1752 static ExitStatus op_deb(DisasContext *s, DisasOps *o)
1753 {
1754 gen_helper_deb(o->out, cpu_env, o->in1, o->in2);
1755 return NO_EXIT;
1756 }
1757
1758 static ExitStatus op_ddb(DisasContext *s, DisasOps *o)
1759 {
1760 gen_helper_ddb(o->out, cpu_env, o->in1, o->in2);
1761 return NO_EXIT;
1762 }
1763
1764 static ExitStatus op_dxb(DisasContext *s, DisasOps *o)
1765 {
1766 gen_helper_dxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
1767 return_low128(o->out2);
1768 return NO_EXIT;
1769 }
1770
1771 static ExitStatus op_ear(DisasContext *s, DisasOps *o)
1772 {
1773 int r2 = get_field(s->fields, r2);
1774 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, aregs[r2]));
1775 return NO_EXIT;
1776 }
1777
1778 static ExitStatus op_efpc(DisasContext *s, DisasOps *o)
1779 {
1780 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, fpc));
1781 return NO_EXIT;
1782 }
1783
1784 static ExitStatus op_ex(DisasContext *s, DisasOps *o)
1785 {
1786 /* ??? Perhaps a better way to implement EXECUTE is to set a bit in
1787 tb->flags, (ab)use the tb->cs_base field as the address of
1788 the template in memory, and grab 8 bits of tb->flags/cflags for
1789 the contents of the register. We would then recognize all this
1790 in gen_intermediate_code_internal, generating code for exactly
1791 one instruction. This new TB then gets executed normally.
1792
1793 On the other hand, this seems to be mostly used for modifying
1794 MVC inside of memcpy, which needs a helper call anyway. So
1795 perhaps this doesn't bear thinking about any further. */
1796
1797 TCGv_i64 tmp;
1798
1799 update_psw_addr(s);
1800 update_cc_op(s);
1801
1802 tmp = tcg_const_i64(s->next_pc);
1803 gen_helper_ex(cc_op, cpu_env, cc_op, o->in1, o->in2, tmp);
1804 tcg_temp_free_i64(tmp);
1805
1806 set_cc_static(s);
1807 return NO_EXIT;
1808 }
1809
1810 static ExitStatus op_flogr(DisasContext *s, DisasOps *o)
1811 {
1812 /* We'll use the original input for cc computation, since we get to
1813 compare that against 0, which ought to be better than comparing
1814 the real output against 64. It also lets cc_dst be a convenient
1815 temporary during our computation. */
1816 gen_op_update1_cc_i64(s, CC_OP_FLOGR, o->in2);
1817
1818 /* R1 = IN ? CLZ(IN) : 64. */
1819 gen_helper_clz(o->out, o->in2);
1820
1821 /* R1+1 = IN & ~(found bit). Note that we may attempt to shift this
1822 value by 64, which is undefined. But since the shift is 64 iff the
1823 input is zero, we still get the correct result after and'ing. */
1824 tcg_gen_movi_i64(o->out2, 0x8000000000000000ull);
1825 tcg_gen_shr_i64(o->out2, o->out2, o->out);
1826 tcg_gen_andc_i64(o->out2, cc_dst, o->out2);
1827 return NO_EXIT;
1828 }
1829
1830 static ExitStatus op_icm(DisasContext *s, DisasOps *o)
1831 {
1832 int m3 = get_field(s->fields, m3);
1833 int pos, len, base = s->insn->data;
1834 TCGv_i64 tmp = tcg_temp_new_i64();
1835 uint64_t ccm;
1836
1837 switch (m3) {
1838 case 0xf:
1839 /* Effectively a 32-bit load. */
1840 tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
1841 len = 32;
1842 goto one_insert;
1843
1844 case 0xc:
1845 case 0x6:
1846 case 0x3:
1847 /* Effectively a 16-bit load. */
1848 tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
1849 len = 16;
1850 goto one_insert;
1851
1852 case 0x8:
1853 case 0x4:
1854 case 0x2:
1855 case 0x1:
1856 /* Effectively an 8-bit load. */
1857 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
1858 len = 8;
1859 goto one_insert;
1860
1861 one_insert:
1862 pos = base + ctz32(m3) * 8;
1863 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len);
1864 ccm = ((1ull << len) - 1) << pos;
1865 break;
1866
1867 default:
1868 /* This is going to be a sequence of loads and inserts. */
1869 pos = base + 32 - 8;
1870 ccm = 0;
1871 while (m3) {
1872 if (m3 & 0x8) {
1873 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
1874 tcg_gen_addi_i64(o->in2, o->in2, 1);
1875 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
1876 ccm |= 0xff << pos;
1877 }
1878 m3 = (m3 << 1) & 0xf;
1879 pos -= 8;
1880 }
1881 break;
1882 }
1883
1884 tcg_gen_movi_i64(tmp, ccm);
1885 gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out);
1886 tcg_temp_free_i64(tmp);
1887 return NO_EXIT;
1888 }
1889
1890 static ExitStatus op_insi(DisasContext *s, DisasOps *o)
1891 {
1892 int shift = s->insn->data & 0xff;
1893 int size = s->insn->data >> 8;
1894 tcg_gen_deposit_i64(o->out, o->in1, o->in2, shift, size);
1895 return NO_EXIT;
1896 }
1897
1898 static ExitStatus op_ipm(DisasContext *s, DisasOps *o)
1899 {
1900 TCGv_i64 t1;
1901
1902 gen_op_calc_cc(s);
1903 tcg_gen_andi_i64(o->out, o->out, ~0xff000000ull);
1904
1905 t1 = tcg_temp_new_i64();
1906 tcg_gen_shli_i64(t1, psw_mask, 20);
1907 tcg_gen_shri_i64(t1, t1, 36);
1908 tcg_gen_or_i64(o->out, o->out, t1);
1909
1910 tcg_gen_extu_i32_i64(t1, cc_op);
1911 tcg_gen_shli_i64(t1, t1, 28);
1912 tcg_gen_or_i64(o->out, o->out, t1);
1913 tcg_temp_free_i64(t1);
1914 return NO_EXIT;
1915 }
1916
1917 #ifndef CONFIG_USER_ONLY
1918 static ExitStatus op_ipte(DisasContext *s, DisasOps *o)
1919 {
1920 check_privileged(s);
1921 gen_helper_ipte(cpu_env, o->in1, o->in2);
1922 return NO_EXIT;
1923 }
1924
1925 static ExitStatus op_iske(DisasContext *s, DisasOps *o)
1926 {
1927 check_privileged(s);
1928 gen_helper_iske(o->out, cpu_env, o->in2);
1929 return NO_EXIT;
1930 }
1931 #endif
1932
1933 static ExitStatus op_ldeb(DisasContext *s, DisasOps *o)
1934 {
1935 gen_helper_ldeb(o->out, cpu_env, o->in2);
1936 return NO_EXIT;
1937 }
1938
1939 static ExitStatus op_ledb(DisasContext *s, DisasOps *o)
1940 {
1941 gen_helper_ledb(o->out, cpu_env, o->in2);
1942 return NO_EXIT;
1943 }
1944
1945 static ExitStatus op_ldxb(DisasContext *s, DisasOps *o)
1946 {
1947 gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2);
1948 return NO_EXIT;
1949 }
1950
1951 static ExitStatus op_lexb(DisasContext *s, DisasOps *o)
1952 {
1953 gen_helper_lexb(o->out, cpu_env, o->in1, o->in2);
1954 return NO_EXIT;
1955 }
1956
1957 static ExitStatus op_lxdb(DisasContext *s, DisasOps *o)
1958 {
1959 gen_helper_lxdb(o->out, cpu_env, o->in2);
1960 return_low128(o->out2);
1961 return NO_EXIT;
1962 }
1963
1964 static ExitStatus op_lxeb(DisasContext *s, DisasOps *o)
1965 {
1966 gen_helper_lxeb(o->out, cpu_env, o->in2);
1967 return_low128(o->out2);
1968 return NO_EXIT;
1969 }
1970
1971 static ExitStatus op_llgt(DisasContext *s, DisasOps *o)
1972 {
1973 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffff);
1974 return NO_EXIT;
1975 }
1976
1977 static ExitStatus op_ld8s(DisasContext *s, DisasOps *o)
1978 {
1979 tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
1980 return NO_EXIT;
1981 }
1982
1983 static ExitStatus op_ld8u(DisasContext *s, DisasOps *o)
1984 {
1985 tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
1986 return NO_EXIT;
1987 }
1988
1989 static ExitStatus op_ld16s(DisasContext *s, DisasOps *o)
1990 {
1991 tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
1992 return NO_EXIT;
1993 }
1994
1995 static ExitStatus op_ld16u(DisasContext *s, DisasOps *o)
1996 {
1997 tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
1998 return NO_EXIT;
1999 }
2000
2001 static ExitStatus op_ld32s(DisasContext *s, DisasOps *o)
2002 {
2003 tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s));
2004 return NO_EXIT;
2005 }
2006
2007 static ExitStatus op_ld32u(DisasContext *s, DisasOps *o)
2008 {
2009 tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
2010 return NO_EXIT;
2011 }
2012
2013 static ExitStatus op_ld64(DisasContext *s, DisasOps *o)
2014 {
2015 tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
2016 return NO_EXIT;
2017 }
2018
2019 #ifndef CONFIG_USER_ONLY
2020 static ExitStatus op_lctl(DisasContext *s, DisasOps *o)
2021 {
2022 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2023 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2024 check_privileged(s);
2025 potential_page_fault(s);
2026 gen_helper_lctl(cpu_env, r1, o->in2, r3);
2027 tcg_temp_free_i32(r1);
2028 tcg_temp_free_i32(r3);
2029 return NO_EXIT;
2030 }
2031
2032 static ExitStatus op_lctlg(DisasContext *s, DisasOps *o)
2033 {
2034 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2035 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2036 check_privileged(s);
2037 potential_page_fault(s);
2038 gen_helper_lctlg(cpu_env, r1, o->in2, r3);
2039 tcg_temp_free_i32(r1);
2040 tcg_temp_free_i32(r3);
2041 return NO_EXIT;
2042 }
2043 static ExitStatus op_lra(DisasContext *s, DisasOps *o)
2044 {
2045 check_privileged(s);
2046 potential_page_fault(s);
2047 gen_helper_lra(o->out, cpu_env, o->in2);
2048 set_cc_static(s);
2049 return NO_EXIT;
2050 }
2051
2052 static ExitStatus op_lpsw(DisasContext *s, DisasOps *o)
2053 {
2054 TCGv_i64 t1, t2;
2055
2056 check_privileged(s);
2057
2058 t1 = tcg_temp_new_i64();
2059 t2 = tcg_temp_new_i64();
2060 tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
2061 tcg_gen_addi_i64(o->in2, o->in2, 4);
2062 tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s));
2063 /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
2064 tcg_gen_shli_i64(t1, t1, 32);
2065 gen_helper_load_psw(cpu_env, t1, t2);
2066 tcg_temp_free_i64(t1);
2067 tcg_temp_free_i64(t2);
2068 return EXIT_NORETURN;
2069 }
2070
2071 static ExitStatus op_lpswe(DisasContext *s, DisasOps *o)
2072 {
2073 TCGv_i64 t1, t2;
2074
2075 check_privileged(s);
2076
2077 t1 = tcg_temp_new_i64();
2078 t2 = tcg_temp_new_i64();
2079 tcg_gen_qemu_ld64(t1, o->in2, get_mem_index(s));
2080 tcg_gen_addi_i64(o->in2, o->in2, 8);
2081 tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s));
2082 gen_helper_load_psw(cpu_env, t1, t2);
2083 tcg_temp_free_i64(t1);
2084 tcg_temp_free_i64(t2);
2085 return EXIT_NORETURN;
2086 }
2087 #endif
2088
2089 static ExitStatus op_lam(DisasContext *s, DisasOps *o)
2090 {
2091 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2092 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2093 potential_page_fault(s);
2094 gen_helper_lam(cpu_env, r1, o->in2, r3);
2095 tcg_temp_free_i32(r1);
2096 tcg_temp_free_i32(r3);
2097 return NO_EXIT;
2098 }
2099
2100 static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
2101 {
2102 int r1 = get_field(s->fields, r1);
2103 int r3 = get_field(s->fields, r3);
2104 TCGv_i64 t = tcg_temp_new_i64();
2105 TCGv_i64 t4 = tcg_const_i64(4);
2106
2107 while (1) {
2108 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2109 store_reg32_i64(r1, t);
2110 if (r1 == r3) {
2111 break;
2112 }
2113 tcg_gen_add_i64(o->in2, o->in2, t4);
2114 r1 = (r1 + 1) & 15;
2115 }
2116
2117 tcg_temp_free_i64(t);
2118 tcg_temp_free_i64(t4);
2119 return NO_EXIT;
2120 }
2121
2122 static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
2123 {
2124 int r1 = get_field(s->fields, r1);
2125 int r3 = get_field(s->fields, r3);
2126 TCGv_i64 t = tcg_temp_new_i64();
2127 TCGv_i64 t4 = tcg_const_i64(4);
2128
2129 while (1) {
2130 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2131 store_reg32h_i64(r1, t);
2132 if (r1 == r3) {
2133 break;
2134 }
2135 tcg_gen_add_i64(o->in2, o->in2, t4);
2136 r1 = (r1 + 1) & 15;
2137 }
2138
2139 tcg_temp_free_i64(t);
2140 tcg_temp_free_i64(t4);
2141 return NO_EXIT;
2142 }
2143
2144 static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
2145 {
2146 int r1 = get_field(s->fields, r1);
2147 int r3 = get_field(s->fields, r3);
2148 TCGv_i64 t8 = tcg_const_i64(8);
2149
2150 while (1) {
2151 tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
2152 if (r1 == r3) {
2153 break;
2154 }
2155 tcg_gen_add_i64(o->in2, o->in2, t8);
2156 r1 = (r1 + 1) & 15;
2157 }
2158
2159 tcg_temp_free_i64(t8);
2160 return NO_EXIT;
2161 }
2162
2163 static ExitStatus op_mov2(DisasContext *s, DisasOps *o)
2164 {
2165 o->out = o->in2;
2166 o->g_out = o->g_in2;
2167 TCGV_UNUSED_I64(o->in2);
2168 o->g_in2 = false;
2169 return NO_EXIT;
2170 }
2171
2172 static ExitStatus op_movx(DisasContext *s, DisasOps *o)
2173 {
2174 o->out = o->in1;
2175 o->out2 = o->in2;
2176 o->g_out = o->g_in1;
2177 o->g_out2 = o->g_in2;
2178 TCGV_UNUSED_I64(o->in1);
2179 TCGV_UNUSED_I64(o->in2);
2180 o->g_in1 = o->g_in2 = false;
2181 return NO_EXIT;
2182 }
2183
2184 static ExitStatus op_mvc(DisasContext *s, DisasOps *o)
2185 {
2186 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2187 potential_page_fault(s);
2188 gen_helper_mvc(cpu_env, l, o->addr1, o->in2);
2189 tcg_temp_free_i32(l);
2190 return NO_EXIT;
2191 }
2192
2193 static ExitStatus op_mvcl(DisasContext *s, DisasOps *o)
2194 {
2195 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2196 TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
2197 potential_page_fault(s);
2198 gen_helper_mvcl(cc_op, cpu_env, r1, r2);
2199 tcg_temp_free_i32(r1);
2200 tcg_temp_free_i32(r2);
2201 set_cc_static(s);
2202 return NO_EXIT;
2203 }
2204
2205 static ExitStatus op_mvcle(DisasContext *s, DisasOps *o)
2206 {
2207 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2208 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2209 potential_page_fault(s);
2210 gen_helper_mvcle(cc_op, cpu_env, r1, o->in2, r3);
2211 tcg_temp_free_i32(r1);
2212 tcg_temp_free_i32(r3);
2213 set_cc_static(s);
2214 return NO_EXIT;
2215 }
2216
2217 #ifndef CONFIG_USER_ONLY
2218 static ExitStatus op_mvcp(DisasContext *s, DisasOps *o)
2219 {
2220 int r1 = get_field(s->fields, l1);
2221 check_privileged(s);
2222 potential_page_fault(s);
2223 gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2224 set_cc_static(s);
2225 return NO_EXIT;
2226 }
2227
2228 static ExitStatus op_mvcs(DisasContext *s, DisasOps *o)
2229 {
2230 int r1 = get_field(s->fields, l1);
2231 check_privileged(s);
2232 potential_page_fault(s);
2233 gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2234 set_cc_static(s);
2235 return NO_EXIT;
2236 }
2237 #endif
2238
2239 static ExitStatus op_mvpg(DisasContext *s, DisasOps *o)
2240 {
2241 potential_page_fault(s);
2242 gen_helper_mvpg(cpu_env, regs[0], o->in1, o->in2);
2243 set_cc_static(s);
2244 return NO_EXIT;
2245 }
2246
2247 static ExitStatus op_mvst(DisasContext *s, DisasOps *o)
2248 {
2249 potential_page_fault(s);
2250 gen_helper_mvst(o->in1, cpu_env, regs[0], o->in1, o->in2);
2251 set_cc_static(s);
2252 return_low128(o->in2);
2253 return NO_EXIT;
2254 }
2255
2256 static ExitStatus op_mul(DisasContext *s, DisasOps *o)
2257 {
2258 tcg_gen_mul_i64(o->out, o->in1, o->in2);
2259 return NO_EXIT;
2260 }
2261
2262 static ExitStatus op_mul128(DisasContext *s, DisasOps *o)
2263 {
2264 gen_helper_mul128(o->out, cpu_env, o->in1, o->in2);
2265 return_low128(o->out2);
2266 return NO_EXIT;
2267 }
2268
2269 static ExitStatus op_meeb(DisasContext *s, DisasOps *o)
2270 {
2271 gen_helper_meeb(o->out, cpu_env, o->in1, o->in2);
2272 return NO_EXIT;
2273 }
2274
2275 static ExitStatus op_mdeb(DisasContext *s, DisasOps *o)
2276 {
2277 gen_helper_mdeb(o->out, cpu_env, o->in1, o->in2);
2278 return NO_EXIT;
2279 }
2280
2281 static ExitStatus op_mdb(DisasContext *s, DisasOps *o)
2282 {
2283 gen_helper_mdb(o->out, cpu_env, o->in1, o->in2);
2284 return NO_EXIT;
2285 }
2286
2287 static ExitStatus op_mxb(DisasContext *s, DisasOps *o)
2288 {
2289 gen_helper_mxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2290 return_low128(o->out2);
2291 return NO_EXIT;
2292 }
2293
2294 static ExitStatus op_mxdb(DisasContext *s, DisasOps *o)
2295 {
2296 gen_helper_mxdb(o->out, cpu_env, o->out, o->out2, o->in2);
2297 return_low128(o->out2);
2298 return NO_EXIT;
2299 }
2300
2301 static ExitStatus op_maeb(DisasContext *s, DisasOps *o)
2302 {
2303 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2304 gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3);
2305 tcg_temp_free_i64(r3);
2306 return NO_EXIT;
2307 }
2308
2309 static ExitStatus op_madb(DisasContext *s, DisasOps *o)
2310 {
2311 int r3 = get_field(s->fields, r3);
2312 gen_helper_madb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2313 return NO_EXIT;
2314 }
2315
2316 static ExitStatus op_mseb(DisasContext *s, DisasOps *o)
2317 {
2318 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2319 gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3);
2320 tcg_temp_free_i64(r3);
2321 return NO_EXIT;
2322 }
2323
2324 static ExitStatus op_msdb(DisasContext *s, DisasOps *o)
2325 {
2326 int r3 = get_field(s->fields, r3);
2327 gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2328 return NO_EXIT;
2329 }
2330
2331 static ExitStatus op_nabs(DisasContext *s, DisasOps *o)
2332 {
2333 gen_helper_nabs_i64(o->out, o->in2);
2334 return NO_EXIT;
2335 }
2336
2337 static ExitStatus op_nabsf32(DisasContext *s, DisasOps *o)
2338 {
2339 tcg_gen_ori_i64(o->out, o->in2, 0x80000000ull);
2340 return NO_EXIT;
2341 }
2342
2343 static ExitStatus op_nabsf64(DisasContext *s, DisasOps *o)
2344 {
2345 tcg_gen_ori_i64(o->out, o->in2, 0x8000000000000000ull);
2346 return NO_EXIT;
2347 }
2348
2349 static ExitStatus op_nabsf128(DisasContext *s, DisasOps *o)
2350 {
2351 tcg_gen_ori_i64(o->out, o->in1, 0x8000000000000000ull);
2352 tcg_gen_mov_i64(o->out2, o->in2);
2353 return NO_EXIT;
2354 }
2355
2356 static ExitStatus op_nc(DisasContext *s, DisasOps *o)
2357 {
2358 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2359 potential_page_fault(s);
2360 gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2);
2361 tcg_temp_free_i32(l);
2362 set_cc_static(s);
2363 return NO_EXIT;
2364 }
2365
2366 static ExitStatus op_neg(DisasContext *s, DisasOps *o)
2367 {
2368 tcg_gen_neg_i64(o->out, o->in2);
2369 return NO_EXIT;
2370 }
2371
2372 static ExitStatus op_negf32(DisasContext *s, DisasOps *o)
2373 {
2374 tcg_gen_xori_i64(o->out, o->in2, 0x80000000ull);
2375 return NO_EXIT;
2376 }
2377
2378 static ExitStatus op_negf64(DisasContext *s, DisasOps *o)
2379 {
2380 tcg_gen_xori_i64(o->out, o->in2, 0x8000000000000000ull);
2381 return NO_EXIT;
2382 }
2383
2384 static ExitStatus op_negf128(DisasContext *s, DisasOps *o)
2385 {
2386 tcg_gen_xori_i64(o->out, o->in1, 0x8000000000000000ull);
2387 tcg_gen_mov_i64(o->out2, o->in2);
2388 return NO_EXIT;
2389 }
2390
2391 static ExitStatus op_oc(DisasContext *s, DisasOps *o)
2392 {
2393 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2394 potential_page_fault(s);
2395 gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2);
2396 tcg_temp_free_i32(l);
2397 set_cc_static(s);
2398 return NO_EXIT;
2399 }
2400
2401 static ExitStatus op_or(DisasContext *s, DisasOps *o)
2402 {
2403 tcg_gen_or_i64(o->out, o->in1, o->in2);
2404 return NO_EXIT;
2405 }
2406
2407 static ExitStatus op_ori(DisasContext *s, DisasOps *o)
2408 {
2409 int shift = s->insn->data & 0xff;
2410 int size = s->insn->data >> 8;
2411 uint64_t mask = ((1ull << size) - 1) << shift;
2412
2413 assert(!o->g_in2);
2414 tcg_gen_shli_i64(o->in2, o->in2, shift);
2415 tcg_gen_or_i64(o->out, o->in1, o->in2);
2416
2417 /* Produce the CC from only the bits manipulated. */
2418 tcg_gen_andi_i64(cc_dst, o->out, mask);
2419 set_cc_nz_u64(s, cc_dst);
2420 return NO_EXIT;
2421 }
2422
2423 #ifndef CONFIG_USER_ONLY
2424 static ExitStatus op_ptlb(DisasContext *s, DisasOps *o)
2425 {
2426 check_privileged(s);
2427 gen_helper_ptlb(cpu_env);
2428 return NO_EXIT;
2429 }
2430 #endif
2431
2432 static ExitStatus op_risbg(DisasContext *s, DisasOps *o)
2433 {
2434 int i3 = get_field(s->fields, i3);
2435 int i4 = get_field(s->fields, i4);
2436 int i5 = get_field(s->fields, i5);
2437 int do_zero = i4 & 0x80;
2438 uint64_t mask, imask, pmask;
2439 int pos, len, rot;
2440
2441 /* Adjust the arguments for the specific insn. */
2442 switch (s->fields->op2) {
2443 case 0x55: /* risbg */
2444 i3 &= 63;
2445 i4 &= 63;
2446 pmask = ~0;
2447 break;
2448 case 0x5d: /* risbhg */
2449 i3 &= 31;
2450 i4 &= 31;
2451 pmask = 0xffffffff00000000ull;
2452 break;
2453 case 0x51: /* risblg */
2454 i3 &= 31;
2455 i4 &= 31;
2456 pmask = 0x00000000ffffffffull;
2457 break;
2458 default:
2459 abort();
2460 }
2461
2462 /* MASK is the set of bits to be inserted from R2.
2463 Take care for I3/I4 wraparound. */
2464 mask = pmask >> i3;
2465 if (i3 <= i4) {
2466 mask ^= pmask >> i4 >> 1;
2467 } else {
2468 mask |= ~(pmask >> i4 >> 1);
2469 }
2470 mask &= pmask;
2471
2472 /* IMASK is the set of bits to be kept from R1. In the case of the high/low
2473 insns, we need to keep the other half of the register. */
2474 imask = ~mask | ~pmask;
2475 if (do_zero) {
2476 if (s->fields->op2 == 0x55) {
2477 imask = 0;
2478 } else {
2479 imask = ~pmask;
2480 }
2481 }
2482
2483 /* In some cases we can implement this with deposit, which can be more
2484 efficient on some hosts. */
2485 if (~mask == imask && i3 <= i4) {
2486 if (s->fields->op2 == 0x5d) {
2487 i3 += 32, i4 += 32;
2488 }
2489 /* Note that we rotate the bits to be inserted to the lsb, not to
2490 the position as described in the PoO. */
2491 len = i4 - i3 + 1;
2492 pos = 63 - i4;
2493 rot = (i5 - pos) & 63;
2494 } else {
2495 pos = len = -1;
2496 rot = i5 & 63;
2497 }
2498
2499 /* Rotate the input as necessary. */
2500 tcg_gen_rotli_i64(o->in2, o->in2, rot);
2501
2502 /* Insert the selected bits into the output. */
2503 if (pos >= 0) {
2504 tcg_gen_deposit_i64(o->out, o->out, o->in2, pos, len);
2505 } else if (imask == 0) {
2506 tcg_gen_andi_i64(o->out, o->in2, mask);
2507 } else {
2508 tcg_gen_andi_i64(o->in2, o->in2, mask);
2509 tcg_gen_andi_i64(o->out, o->out, imask);
2510 tcg_gen_or_i64(o->out, o->out, o->in2);
2511 }
2512 return NO_EXIT;
2513 }
2514
2515 static ExitStatus op_rosbg(DisasContext *s, DisasOps *o)
2516 {
2517 int i3 = get_field(s->fields, i3);
2518 int i4 = get_field(s->fields, i4);
2519 int i5 = get_field(s->fields, i5);
2520 uint64_t mask;
2521
2522 /* If this is a test-only form, arrange to discard the result. */
2523 if (i3 & 0x80) {
2524 o->out = tcg_temp_new_i64();
2525 o->g_out = false;
2526 }
2527
2528 i3 &= 63;
2529 i4 &= 63;
2530 i5 &= 63;
2531
2532 /* MASK is the set of bits to be operated on from R2.
2533 Take care for I3/I4 wraparound. */
2534 mask = ~0ull >> i3;
2535 if (i3 <= i4) {
2536 mask ^= ~0ull >> i4 >> 1;
2537 } else {
2538 mask |= ~(~0ull >> i4 >> 1);
2539 }
2540
2541 /* Rotate the input as necessary. */
2542 tcg_gen_rotli_i64(o->in2, o->in2, i5);
2543
2544 /* Operate. */
2545 switch (s->fields->op2) {
2546 case 0x55: /* AND */
2547 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
2548 tcg_gen_and_i64(o->out, o->out, o->in2);
2549 break;
2550 case 0x56: /* OR */
2551 tcg_gen_andi_i64(o->in2, o->in2, mask);
2552 tcg_gen_or_i64(o->out, o->out, o->in2);
2553 break;
2554 case 0x57: /* XOR */
2555 tcg_gen_andi_i64(o->in2, o->in2, mask);
2556 tcg_gen_xor_i64(o->out, o->out, o->in2);
2557 break;
2558 default:
2559 abort();
2560 }
2561
2562 /* Set the CC. */
2563 tcg_gen_andi_i64(cc_dst, o->out, mask);
2564 set_cc_nz_u64(s, cc_dst);
2565 return NO_EXIT;
2566 }
2567
2568 static ExitStatus op_rev16(DisasContext *s, DisasOps *o)
2569 {
2570 tcg_gen_bswap16_i64(o->out, o->in2);
2571 return NO_EXIT;
2572 }
2573
2574 static ExitStatus op_rev32(DisasContext *s, DisasOps *o)
2575 {
2576 tcg_gen_bswap32_i64(o->out, o->in2);
2577 return NO_EXIT;
2578 }
2579
2580 static ExitStatus op_rev64(DisasContext *s, DisasOps *o)
2581 {
2582 tcg_gen_bswap64_i64(o->out, o->in2);
2583 return NO_EXIT;
2584 }
2585
2586 static ExitStatus op_rll32(DisasContext *s, DisasOps *o)
2587 {
2588 TCGv_i32 t1 = tcg_temp_new_i32();
2589 TCGv_i32 t2 = tcg_temp_new_i32();
2590 TCGv_i32 to = tcg_temp_new_i32();
2591 tcg_gen_trunc_i64_i32(t1, o->in1);
2592 tcg_gen_trunc_i64_i32(t2, o->in2);
2593 tcg_gen_rotl_i32(to, t1, t2);
2594 tcg_gen_extu_i32_i64(o->out, to);
2595 tcg_temp_free_i32(t1);
2596 tcg_temp_free_i32(t2);
2597 tcg_temp_free_i32(to);
2598 return NO_EXIT;
2599 }
2600
2601 static ExitStatus op_rll64(DisasContext *s, DisasOps *o)
2602 {
2603 tcg_gen_rotl_i64(o->out, o->in1, o->in2);
2604 return NO_EXIT;
2605 }
2606
2607 #ifndef CONFIG_USER_ONLY
2608 static ExitStatus op_rrbe(DisasContext *s, DisasOps *o)
2609 {
2610 check_privileged(s);
2611 gen_helper_rrbe(cc_op, cpu_env, o->in2);
2612 set_cc_static(s);
2613 return NO_EXIT;
2614 }
2615
2616 static ExitStatus op_sacf(DisasContext *s, DisasOps *o)
2617 {
2618 check_privileged(s);
2619 gen_helper_sacf(cpu_env, o->in2);
2620 /* Addressing mode has changed, so end the block. */
2621 return EXIT_PC_STALE;
2622 }
2623 #endif
2624
2625 static ExitStatus op_sar(DisasContext *s, DisasOps *o)
2626 {
2627 int r1 = get_field(s->fields, r1);
2628 tcg_gen_st32_i64(o->in2, cpu_env, offsetof(CPUS390XState, aregs[r1]));
2629 return NO_EXIT;
2630 }
2631
2632 static ExitStatus op_seb(DisasContext *s, DisasOps *o)
2633 {
2634 gen_helper_seb(o->out, cpu_env, o->in1, o->in2);
2635 return NO_EXIT;
2636 }
2637
2638 static ExitStatus op_sdb(DisasContext *s, DisasOps *o)
2639 {
2640 gen_helper_sdb(o->out, cpu_env, o->in1, o->in2);
2641 return NO_EXIT;
2642 }
2643
2644 static ExitStatus op_sxb(DisasContext *s, DisasOps *o)
2645 {
2646 gen_helper_sxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2647 return_low128(o->out2);
2648 return NO_EXIT;
2649 }
2650
2651 static ExitStatus op_sqeb(DisasContext *s, DisasOps *o)
2652 {
2653 gen_helper_sqeb(o->out, cpu_env, o->in2);
2654 return NO_EXIT;
2655 }
2656
2657 static ExitStatus op_sqdb(DisasContext *s, DisasOps *o)
2658 {
2659 gen_helper_sqdb(o->out, cpu_env, o->in2);
2660 return NO_EXIT;
2661 }
2662
2663 static ExitStatus op_sqxb(DisasContext *s, DisasOps *o)
2664 {
2665 gen_helper_sqxb(o->out, cpu_env, o->in1, o->in2);
2666 return_low128(o->out2);
2667 return NO_EXIT;
2668 }
2669
2670 #ifndef CONFIG_USER_ONLY
2671 static ExitStatus op_servc(DisasContext *s, DisasOps *o)
2672 {
2673 check_privileged(s);
2674 potential_page_fault(s);
2675 gen_helper_servc(cc_op, cpu_env, o->in2, o->in1);
2676 set_cc_static(s);
2677 return NO_EXIT;
2678 }
2679
2680 static ExitStatus op_sigp(DisasContext *s, DisasOps *o)
2681 {
2682 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2683 check_privileged(s);
2684 potential_page_fault(s);
2685 gen_helper_sigp(cc_op, cpu_env, o->in2, r1, o->in1);
2686 tcg_temp_free_i32(r1);
2687 return NO_EXIT;
2688 }
2689 #endif
2690
2691 static ExitStatus op_sla(DisasContext *s, DisasOps *o)
2692 {
2693 uint64_t sign = 1ull << s->insn->data;
2694 enum cc_op cco = s->insn->data == 31 ? CC_OP_SLA_32 : CC_OP_SLA_64;
2695 gen_op_update2_cc_i64(s, cco, o->in1, o->in2);
2696 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2697 /* The arithmetic left shift is curious in that it does not affect
2698 the sign bit. Copy that over from the source unchanged. */
2699 tcg_gen_andi_i64(o->out, o->out, ~sign);
2700 tcg_gen_andi_i64(o->in1, o->in1, sign);
2701 tcg_gen_or_i64(o->out, o->out, o->in1);
2702 return NO_EXIT;
2703 }
2704
2705 static ExitStatus op_sll(DisasContext *s, DisasOps *o)
2706 {
2707 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2708 return NO_EXIT;
2709 }
2710
2711 static ExitStatus op_sra(DisasContext *s, DisasOps *o)
2712 {
2713 tcg_gen_sar_i64(o->out, o->in1, o->in2);
2714 return NO_EXIT;
2715 }
2716
2717 static ExitStatus op_srl(DisasContext *s, DisasOps *o)
2718 {
2719 tcg_gen_shr_i64(o->out, o->in1, o->in2);
2720 return NO_EXIT;
2721 }
2722
2723 static ExitStatus op_sfpc(DisasContext *s, DisasOps *o)
2724 {
2725 gen_helper_sfpc(cpu_env, o->in2);
2726 return NO_EXIT;
2727 }
2728
2729 #ifndef CONFIG_USER_ONLY
2730 static ExitStatus op_spka(DisasContext *s, DisasOps *o)
2731 {
2732 check_privileged(s);
2733 tcg_gen_shri_i64(o->in2, o->in2, 4);
2734 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY - 4, 4);
2735 return NO_EXIT;
2736 }
2737
2738 static ExitStatus op_sske(DisasContext *s, DisasOps *o)
2739 {
2740 check_privileged(s);
2741 gen_helper_sske(cpu_env, o->in1, o->in2);
2742 return NO_EXIT;
2743 }
2744
2745 static ExitStatus op_ssm(DisasContext *s, DisasOps *o)
2746 {
2747 check_privileged(s);
2748 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8);
2749 return NO_EXIT;
2750 }
2751
2752 static ExitStatus op_stap(DisasContext *s, DisasOps *o)
2753 {
2754 check_privileged(s);
2755 /* ??? Surely cpu address != cpu number. In any case the previous
2756 version of this stored more than the required half-word, so it
2757 is unlikely this has ever been tested. */
2758 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num));
2759 return NO_EXIT;
2760 }
2761
2762 static ExitStatus op_stck(DisasContext *s, DisasOps *o)
2763 {
2764 gen_helper_stck(o->out, cpu_env);
2765 /* ??? We don't implement clock states. */
2766 gen_op_movi_cc(s, 0);
2767 return NO_EXIT;
2768 }
2769
2770 static ExitStatus op_stcke(DisasContext *s, DisasOps *o)
2771 {
2772 TCGv_i64 c1 = tcg_temp_new_i64();
2773 TCGv_i64 c2 = tcg_temp_new_i64();
2774 gen_helper_stck(c1, cpu_env);
2775 /* Shift the 64-bit value into its place as a zero-extended
2776 104-bit value. Note that "bit positions 64-103 are always
2777 non-zero so that they compare differently to STCK"; we set
2778 the least significant bit to 1. */
2779 tcg_gen_shli_i64(c2, c1, 56);
2780 tcg_gen_shri_i64(c1, c1, 8);
2781 tcg_gen_ori_i64(c2, c2, 0x10000);
2782 tcg_gen_qemu_st64(c1, o->in2, get_mem_index(s));
2783 tcg_gen_addi_i64(o->in2, o->in2, 8);
2784 tcg_gen_qemu_st64(c2, o->in2, get_mem_index(s));
2785 tcg_temp_free_i64(c1);
2786 tcg_temp_free_i64(c2);
2787 /* ??? We don't implement clock states. */
2788 gen_op_movi_cc(s, 0);
2789 return NO_EXIT;
2790 }
2791
2792 static ExitStatus op_sckc(DisasContext *s, DisasOps *o)
2793 {
2794 check_privileged(s);
2795 gen_helper_sckc(cpu_env, o->in2);
2796 return NO_EXIT;
2797 }
2798
2799 static ExitStatus op_stckc(DisasContext *s, DisasOps *o)
2800 {
2801 check_privileged(s);
2802 gen_helper_stckc(o->out, cpu_env);
2803 return NO_EXIT;
2804 }
2805
2806 static ExitStatus op_stctg(DisasContext *s, DisasOps *o)
2807 {
2808 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2809 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2810 check_privileged(s);
2811 potential_page_fault(s);
2812 gen_helper_stctg(cpu_env, r1, o->in2, r3);
2813 tcg_temp_free_i32(r1);
2814 tcg_temp_free_i32(r3);
2815 return NO_EXIT;
2816 }
2817
2818 static ExitStatus op_stctl(DisasContext *s, DisasOps *o)
2819 {
2820 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2821 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2822 check_privileged(s);
2823 potential_page_fault(s);
2824 gen_helper_stctl(cpu_env, r1, o->in2, r3);
2825 tcg_temp_free_i32(r1);
2826 tcg_temp_free_i32(r3);
2827 return NO_EXIT;
2828 }
2829
2830 static ExitStatus op_stidp(DisasContext *s, DisasOps *o)
2831 {
2832 check_privileged(s);
2833 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num));
2834 return NO_EXIT;
2835 }
2836
2837 static ExitStatus op_spt(DisasContext *s, DisasOps *o)
2838 {
2839 check_privileged(s);
2840 gen_helper_spt(cpu_env, o->in2);
2841 return NO_EXIT;
2842 }
2843
2844 static ExitStatus op_stfl(DisasContext *s, DisasOps *o)
2845 {
2846 TCGv_i64 f, a;
2847 /* We really ought to have more complete indication of facilities
2848 that we implement. Address this when STFLE is implemented. */
2849 check_privileged(s);
2850 f = tcg_const_i64(0xc0000000);
2851 a = tcg_const_i64(200);
2852 tcg_gen_qemu_st32(f, a, get_mem_index(s));
2853 tcg_temp_free_i64(f);
2854 tcg_temp_free_i64(a);
2855 return NO_EXIT;
2856 }
2857
2858 static ExitStatus op_stpt(DisasContext *s, DisasOps *o)
2859 {
2860 check_privileged(s);
2861 gen_helper_stpt(o->out, cpu_env);
2862 return NO_EXIT;
2863 }
2864
2865 static ExitStatus op_stsi(DisasContext *s, DisasOps *o)
2866 {
2867 check_privileged(s);
2868 potential_page_fault(s);
2869 gen_helper_stsi(cc_op, cpu_env, o->in2, regs[0], regs[1]);
2870 set_cc_static(s);
2871 return NO_EXIT;
2872 }
2873
2874 static ExitStatus op_spx(DisasContext *s, DisasOps *o)
2875 {
2876 check_privileged(s);
2877 gen_helper_spx(cpu_env, o->in2);
2878 return NO_EXIT;
2879 }
2880
2881 static ExitStatus op_subchannel(DisasContext *s, DisasOps *o)
2882 {
2883 check_privileged(s);
2884 /* Not operational. */
2885 gen_op_movi_cc(s, 3);
2886 return NO_EXIT;
2887 }
2888
2889 static ExitStatus op_stpx(DisasContext *s, DisasOps *o)
2890 {
2891 check_privileged(s);
2892 tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, psa));
2893 tcg_gen_andi_i64(o->out, o->out, 0x7fffe000);
2894 return NO_EXIT;
2895 }
2896
2897 static ExitStatus op_stnosm(DisasContext *s, DisasOps *o)
2898 {
2899 uint64_t i2 = get_field(s->fields, i2);
2900 TCGv_i64 t;
2901
2902 check_privileged(s);
2903
2904 /* It is important to do what the instruction name says: STORE THEN.
2905 If we let the output hook perform the store then if we fault and
2906 restart, we'll have the wrong SYSTEM MASK in place. */
2907 t = tcg_temp_new_i64();
2908 tcg_gen_shri_i64(t, psw_mask, 56);
2909 tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
2910 tcg_temp_free_i64(t);
2911
2912 if (s->fields->op == 0xac) {
2913 tcg_gen_andi_i64(psw_mask, psw_mask,
2914 (i2 << 56) | 0x00ffffffffffffffull);
2915 } else {
2916 tcg_gen_ori_i64(psw_mask, psw_mask, i2 << 56);
2917 }
2918 return NO_EXIT;
2919 }
2920
2921 static ExitStatus op_stura(DisasContext *s, DisasOps *o)
2922 {
2923 check_privileged(s);
2924 potential_page_fault(s);
2925 gen_helper_stura(cpu_env, o->in2, o->in1);
2926 return NO_EXIT;
2927 }
2928 #endif
2929
2930 static ExitStatus op_st8(DisasContext *s, DisasOps *o)
2931 {
2932 tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
2933 return NO_EXIT;
2934 }
2935
2936 static ExitStatus op_st16(DisasContext *s, DisasOps *o)
2937 {
2938 tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
2939 return NO_EXIT;
2940 }
2941
2942 static ExitStatus op_st32(DisasContext *s, DisasOps *o)
2943 {
2944 tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s));
2945 return NO_EXIT;
2946 }
2947
2948 static ExitStatus op_st64(DisasContext *s, DisasOps *o)
2949 {
2950 tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
2951 return NO_EXIT;
2952 }
2953
2954 static ExitStatus op_stam(DisasContext *s, DisasOps *o)
2955 {
2956 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2957 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2958 potential_page_fault(s);
2959 gen_helper_stam(cpu_env, r1, o->in2, r3);
2960 tcg_temp_free_i32(r1);
2961 tcg_temp_free_i32(r3);
2962 return NO_EXIT;
2963 }
2964
2965 static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
2966 {
2967 int m3 = get_field(s->fields, m3);
2968 int pos, base = s->insn->data;
2969 TCGv_i64 tmp = tcg_temp_new_i64();
2970
2971 pos = base + ctz32(m3) * 8;
2972 switch (m3) {
2973 case 0xf:
2974 /* Effectively a 32-bit store. */
2975 tcg_gen_shri_i64(tmp, o->in1, pos);
2976 tcg_gen_qemu_st32(tmp, o->in2, get_mem_index(s));
2977 break;
2978
2979 case 0xc:
2980 case 0x6:
2981 case 0x3:
2982 /* Effectively a 16-bit store. */
2983 tcg_gen_shri_i64(tmp, o->in1, pos);
2984 tcg_gen_qemu_st16(tmp, o->in2, get_mem_index(s));
2985 break;
2986
2987 case 0x8:
2988 case 0x4:
2989 case 0x2:
2990 case 0x1:
2991 /* Effectively an 8-bit store. */
2992 tcg_gen_shri_i64(tmp, o->in1, pos);
2993 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
2994 break;
2995
2996 default:
2997 /* This is going to be a sequence of shifts and stores. */
2998 pos = base + 32 - 8;
2999 while (m3) {
3000 if (m3 & 0x8) {
3001 tcg_gen_shri_i64(tmp, o->in1, pos);
3002 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3003 tcg_gen_addi_i64(o->in2, o->in2, 1);
3004 }
3005 m3 = (m3 << 1) & 0xf;
3006 pos -= 8;
3007 }
3008 break;
3009 }
3010 tcg_temp_free_i64(tmp);
3011 return NO_EXIT;
3012 }
3013
3014 static ExitStatus op_stm(DisasContext *s, DisasOps *o)
3015 {
3016 int r1 = get_field(s->fields, r1);
3017 int r3 = get_field(s->fields, r3);
3018 int size = s->insn->data;
3019 TCGv_i64 tsize = tcg_const_i64(size);
3020
3021 while (1) {
3022 if (size == 8) {
3023 tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
3024 } else {
3025 tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s));
3026 }
3027 if (r1 == r3) {
3028 break;
3029 }
3030 tcg_gen_add_i64(o->in2, o->in2, tsize);
3031 r1 = (r1 + 1) & 15;
3032 }
3033
3034 tcg_temp_free_i64(tsize);
3035 return NO_EXIT;
3036 }
3037
3038 static ExitStatus op_stmh(DisasContext *s, DisasOps *o)
3039 {
3040 int r1 = get_field(s->fields, r1);
3041 int r3 = get_field(s->fields, r3);
3042 TCGv_i64 t = tcg_temp_new_i64();
3043 TCGv_i64 t4 = tcg_const_i64(4);
3044 TCGv_i64 t32 = tcg_const_i64(32);
3045
3046 while (1) {
3047 tcg_gen_shl_i64(t, regs[r1], t32);
3048 tcg_gen_qemu_st32(t, o->in2, get_mem_index(s));
3049 if (r1 == r3) {
3050 break;
3051 }
3052 tcg_gen_add_i64(o->in2, o->in2, t4);
3053 r1 = (r1 + 1) & 15;
3054 }
3055
3056 tcg_temp_free_i64(t);
3057 tcg_temp_free_i64(t4);
3058 tcg_temp_free_i64(t32);
3059 return NO_EXIT;
3060 }
3061
3062 static ExitStatus op_srst(DisasContext *s, DisasOps *o)
3063 {
3064 potential_page_fault(s);
3065 gen_helper_srst(o->in1, cpu_env, regs[0], o->in1, o->in2);
3066 set_cc_static(s);
3067 return_low128(o->in2);
3068 return NO_EXIT;
3069 }
3070
3071 static ExitStatus op_sub(DisasContext *s, DisasOps *o)
3072 {
3073 tcg_gen_sub_i64(o->out, o->in1, o->in2);
3074 return NO_EXIT;
3075 }
3076
3077 static ExitStatus op_subb(DisasContext *s, DisasOps *o)
3078 {
3079 TCGv_i64 cc;
3080
3081 assert(!o->g_in2);
3082 tcg_gen_not_i64(o->in2, o->in2);
3083 tcg_gen_add_i64(o->out, o->in1, o->in2);
3084
3085 /* XXX possible optimization point */
3086 gen_op_calc_cc(s);
3087 cc = tcg_temp_new_i64();
3088 tcg_gen_extu_i32_i64(cc, cc_op);
3089 tcg_gen_shri_i64(cc, cc, 1);
3090 tcg_gen_add_i64(o->out, o->out, cc);
3091 tcg_temp_free_i64(cc);
3092 return NO_EXIT;
3093 }
3094
3095 static ExitStatus op_svc(DisasContext *s, DisasOps *o)
3096 {
3097 TCGv_i32 t;
3098
3099 update_psw_addr(s);
3100 update_cc_op(s);
3101
3102 t = tcg_const_i32(get_field(s->fields, i1) & 0xff);
3103 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code));
3104 tcg_temp_free_i32(t);
3105
3106 t = tcg_const_i32(s->next_pc - s->pc);
3107 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen));
3108 tcg_temp_free_i32(t);
3109
3110 gen_exception(EXCP_SVC);
3111 return EXIT_NORETURN;
3112 }
3113
3114 static ExitStatus op_tceb(DisasContext *s, DisasOps *o)
3115 {
3116 gen_helper_tceb(cc_op, o->in1, o->in2);
3117 set_cc_static(s);
3118 return NO_EXIT;
3119 }
3120
3121 static ExitStatus op_tcdb(DisasContext *s, DisasOps *o)
3122 {
3123 gen_helper_tcdb(cc_op, o->in1, o->in2);
3124 set_cc_static(s);
3125 return NO_EXIT;
3126 }
3127
3128 static ExitStatus op_tcxb(DisasContext *s, DisasOps *o)
3129 {
3130 gen_helper_tcxb(cc_op, o->out, o->out2, o->in2);
3131 set_cc_static(s);
3132 return NO_EXIT;
3133 }
3134
3135 #ifndef CONFIG_USER_ONLY
3136 static ExitStatus op_tprot(DisasContext *s, DisasOps *o)
3137 {
3138 potential_page_fault(s);
3139 gen_helper_tprot(cc_op, o->addr1, o->in2);
3140 set_cc_static(s);
3141 return NO_EXIT;
3142 }
3143 #endif
3144
3145 static ExitStatus op_tr(DisasContext *s, DisasOps *o)
3146 {
3147 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3148 potential_page_fault(s);
3149 gen_helper_tr(cpu_env, l, o->addr1, o->in2);
3150 tcg_temp_free_i32(l);
3151 set_cc_static(s);
3152 return NO_EXIT;
3153 }
3154
3155 static ExitStatus op_unpk(DisasContext *s, DisasOps *o)
3156 {
3157 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3158 potential_page_fault(s);
3159 gen_helper_unpk(cpu_env, l, o->addr1, o->in2);
3160 tcg_temp_free_i32(l);
3161 return NO_EXIT;
3162 }
3163
3164 static ExitStatus op_xc(DisasContext *s, DisasOps *o)
3165 {
3166 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3167 potential_page_fault(s);
3168 gen_helper_xc(cc_op, cpu_env, l, o->addr1, o->in2);
3169 tcg_temp_free_i32(l);
3170 set_cc_static(s);
3171 return NO_EXIT;
3172 }
3173
3174 static ExitStatus op_xor(DisasContext *s, DisasOps *o)
3175 {
3176 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3177 return NO_EXIT;
3178 }
3179
3180 static ExitStatus op_xori(DisasContext *s, DisasOps *o)
3181 {
3182 int shift = s->insn->data & 0xff;
3183 int size = s->insn->data >> 8;
3184 uint64_t mask = ((1ull << size) - 1) << shift;
3185
3186 assert(!o->g_in2);
3187 tcg_gen_shli_i64(o->in2, o->in2, shift);
3188 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3189
3190 /* Produce the CC from only the bits manipulated. */
3191 tcg_gen_andi_i64(cc_dst, o->out, mask);
3192 set_cc_nz_u64(s, cc_dst);
3193 return NO_EXIT;
3194 }
3195
3196 static ExitStatus op_zero(DisasContext *s, DisasOps *o)
3197 {
3198 o->out = tcg_const_i64(0);
3199 return NO_EXIT;
3200 }
3201
3202 static ExitStatus op_zero2(DisasContext *s, DisasOps *o)
3203 {
3204 o->out = tcg_const_i64(0);
3205 o->out2 = o->out;
3206 o->g_out2 = true;
3207 return NO_EXIT;
3208 }
3209
3210 /* ====================================================================== */
3211 /* The "Cc OUTput" generators. Given the generated output (and in some cases
3212 the original inputs), update the various cc data structures in order to
3213 be able to compute the new condition code. */
3214
3215 static void cout_abs32(DisasContext *s, DisasOps *o)
3216 {
3217 gen_op_update1_cc_i64(s, CC_OP_ABS_32, o->out);
3218 }
3219
3220 static void cout_abs64(DisasContext *s, DisasOps *o)
3221 {
3222 gen_op_update1_cc_i64(s, CC_OP_ABS_64, o->out);
3223 }
3224
3225 static void cout_adds32(DisasContext *s, DisasOps *o)
3226 {
3227 gen_op_update3_cc_i64(s, CC_OP_ADD_32, o->in1, o->in2, o->out);
3228 }
3229
3230 static void cout_adds64(DisasContext *s, DisasOps *o)
3231 {
3232 gen_op_update3_cc_i64(s, CC_OP_ADD_64, o->in1, o->in2, o->out);
3233 }
3234
3235 static void cout_addu32(DisasContext *s, DisasOps *o)
3236 {
3237 gen_op_update3_cc_i64(s, CC_OP_ADDU_32, o->in1, o->in2, o->out);
3238 }
3239
3240 static void cout_addu64(DisasContext *s, DisasOps *o)
3241 {
3242 gen_op_update3_cc_i64(s, CC_OP_ADDU_64, o->in1, o->in2, o->out);
3243 }
3244
3245 static void cout_addc32(DisasContext *s, DisasOps *o)
3246 {
3247 gen_op_update3_cc_i64(s, CC_OP_ADDC_32, o->in1, o->in2, o->out);
3248 }
3249
3250 static void cout_addc64(DisasContext *s, DisasOps *o)
3251 {
3252 gen_op_update3_cc_i64(s, CC_OP_ADDC_64, o->in1, o->in2, o->out);
3253 }
3254
3255 static void cout_cmps32(DisasContext *s, DisasOps *o)
3256 {
3257 gen_op_update2_cc_i64(s, CC_OP_LTGT_32, o->in1, o->in2);
3258 }
3259
3260 static void cout_cmps64(DisasContext *s, DisasOps *o)
3261 {
3262 gen_op_update2_cc_i64(s, CC_OP_LTGT_64, o->in1, o->in2);
3263 }
3264
3265 static void cout_cmpu32(DisasContext *s, DisasOps *o)
3266 {
3267 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_32, o->in1, o->in2);
3268 }
3269
3270 static void cout_cmpu64(DisasContext *s, DisasOps *o)
3271 {
3272 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, o->in1, o->in2);
3273 }
3274
3275 static void cout_f32(DisasContext *s, DisasOps *o)
3276 {
3277 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, o->out);
3278 }
3279
3280 static void cout_f64(DisasContext *s, DisasOps *o)
3281 {
3282 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, o->out);
3283 }
3284
3285 static void cout_f128(DisasContext *s, DisasOps *o)
3286 {
3287 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, o->out, o->out2);
3288 }
3289
3290 static void cout_nabs32(DisasContext *s, DisasOps *o)
3291 {
3292 gen_op_update1_cc_i64(s, CC_OP_NABS_32, o->out);
3293 }
3294
3295 static void cout_nabs64(DisasContext *s, DisasOps *o)
3296 {
3297 gen_op_update1_cc_i64(s, CC_OP_NABS_64, o->out);
3298 }
3299
3300 static void cout_neg32(DisasContext *s, DisasOps *o)
3301 {
3302 gen_op_update1_cc_i64(s, CC_OP_COMP_32, o->out);
3303 }
3304
3305 static void cout_neg64(DisasContext *s, DisasOps *o)
3306 {
3307 gen_op_update1_cc_i64(s, CC_OP_COMP_64, o->out);
3308 }
3309
3310 static void cout_nz32(DisasContext *s, DisasOps *o)
3311 {
3312 tcg_gen_ext32u_i64(cc_dst, o->out);
3313 gen_op_update1_cc_i64(s, CC_OP_NZ, cc_dst);
3314 }
3315
3316 static void cout_nz64(DisasContext *s, DisasOps *o)
3317 {
3318 gen_op_update1_cc_i64(s, CC_OP_NZ, o->out);
3319 }
3320
3321 static void cout_s32(DisasContext *s, DisasOps *o)
3322 {
3323 gen_op_update1_cc_i64(s, CC_OP_LTGT0_32, o->out);
3324 }
3325
3326 static void cout_s64(DisasContext *s, DisasOps *o)
3327 {
3328 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, o->out);
3329 }
3330
3331 static void cout_subs32(DisasContext *s, DisasOps *o)
3332 {
3333 gen_op_update3_cc_i64(s, CC_OP_SUB_32, o->in1, o->in2, o->out);
3334 }
3335
3336 static void cout_subs64(DisasContext *s, DisasOps *o)
3337 {
3338 gen_op_update3_cc_i64(s, CC_OP_SUB_64, o->in1, o->in2, o->out);
3339 }
3340
3341 static void cout_subu32(DisasContext *s, DisasOps *o)
3342 {
3343 gen_op_update3_cc_i64(s, CC_OP_SUBU_32, o->in1, o->in2, o->out);
3344 }
3345
3346 static void cout_subu64(DisasContext *s, DisasOps *o)
3347 {
3348 gen_op_update3_cc_i64(s, CC_OP_SUBU_64, o->in1, o->in2, o->out);
3349 }
3350
3351 static void cout_subb32(DisasContext *s, DisasOps *o)
3352 {
3353 gen_op_update3_cc_i64(s, CC_OP_SUBB_32, o->in1, o->in2, o->out);
3354 }
3355
3356 static void cout_subb64(DisasContext *s, DisasOps *o)
3357 {
3358 gen_op_update3_cc_i64(s, CC_OP_SUBB_64, o->in1, o->in2, o->out);
3359 }
3360
3361 static void cout_tm32(DisasContext *s, DisasOps *o)
3362 {
3363 gen_op_update2_cc_i64(s, CC_OP_TM_32, o->in1, o->in2);
3364 }
3365
3366 static void cout_tm64(DisasContext *s, DisasOps *o)
3367 {
3368 gen_op_update2_cc_i64(s, CC_OP_TM_64, o->in1, o->in2);
3369 }
3370
3371 /* ====================================================================== */
3372 /* The "PREPeration" generators. These initialize the DisasOps.OUT fields
3373 with the TCG register to which we will write. Used in combination with
3374 the "wout" generators, in some cases we need a new temporary, and in
3375 some cases we can write to a TCG global. */
3376
3377 static void prep_new(DisasContext *s, DisasFields *f, DisasOps *o)
3378 {
3379 o->out = tcg_temp_new_i64();
3380 }
3381
3382 static void prep_new_P(DisasContext *s, DisasFields *f, DisasOps *o)
3383 {
3384 o->out = tcg_temp_new_i64();
3385 o->out2 = tcg_temp_new_i64();
3386 }
3387
3388 static void prep_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3389 {
3390 o->out = regs[get_field(f, r1)];
3391 o->g_out = true;
3392 }
3393
3394 static void prep_r1_P(DisasContext *s, DisasFields *f, DisasOps *o)
3395 {
3396 /* ??? Specification exception: r1 must be even. */
3397 int r1 = get_field(f, r1);
3398 o->out = regs[r1];
3399 o->out2 = regs[(r1 + 1) & 15];
3400 o->g_out = o->g_out2 = true;
3401 }
3402
3403 static void prep_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3404 {
3405 o->out = fregs[get_field(f, r1)];
3406 o->g_out = true;
3407 }
3408
3409 static void prep_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3410 {
3411 /* ??? Specification exception: r1 must be < 14. */
3412 int r1 = get_field(f, r1);
3413 o->out = fregs[r1];
3414 o->out2 = fregs[(r1 + 2) & 15];
3415 o->g_out = o->g_out2 = true;
3416 }
3417
3418 /* ====================================================================== */
3419 /* The "Write OUTput" generators. These generally perform some non-trivial
3420 copy of data to TCG globals, or to main memory. The trivial cases are
3421 generally handled by having a "prep" generator install the TCG global
3422 as the destination of the operation. */
3423
3424 static void wout_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3425 {
3426 store_reg(get_field(f, r1), o->out);
3427 }
3428
3429 static void wout_r1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3430 {
3431 int r1 = get_field(f, r1);
3432 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8);
3433 }
3434
3435 static void wout_r1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3436 {
3437 int r1 = get_field(f, r1);
3438 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 16);
3439 }
3440
3441 static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3442 {
3443 store_reg32_i64(get_field(f, r1), o->out);
3444 }
3445
3446 static void wout_r1_P32(DisasContext *s, DisasFields *f, DisasOps *o)
3447 {
3448 /* ??? Specification exception: r1 must be even. */
3449 int r1 = get_field(f, r1);
3450 store_reg32_i64(r1, o->out);
3451 store_reg32_i64((r1 + 1) & 15, o->out2);
3452 }
3453
3454 static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3455 {
3456 /* ??? Specification exception: r1 must be even. */
3457 int r1 = get_field(f, r1);
3458 store_reg32_i64((r1 + 1) & 15, o->out);
3459 tcg_gen_shri_i64(o->out, o->out, 32);
3460 store_reg32_i64(r1, o->out);
3461 }
3462
3463 static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3464 {
3465 store_freg32_i64(get_field(f, r1), o->out);
3466 }
3467
3468 static void wout_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3469 {
3470 store_freg(get_field(f, r1), o->out);
3471 }
3472
3473 static void wout_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3474 {
3475 /* ??? Specification exception: r1 must be < 14. */
3476 int f1 = get_field(s->fields, r1);
3477 store_freg(f1, o->out);
3478 store_freg((f1 + 2) & 15, o->out2);
3479 }
3480
3481 static void wout_cond_r1r2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3482 {
3483 if (get_field(f, r1) != get_field(f, r2)) {
3484 store_reg32_i64(get_field(f, r1), o->out);
3485 }
3486 }
3487
3488 static void wout_cond_e1e2(DisasContext *s, DisasFields *f, DisasOps *o)
3489 {
3490 if (get_field(f, r1) != get_field(f, r2)) {
3491 store_freg32_i64(get_field(f, r1), o->out);
3492 }
3493 }
3494
3495 static void wout_m1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3496 {
3497 tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s));
3498 }
3499
3500 static void wout_m1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3501 {
3502 tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s));
3503 }
3504
3505 static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3506 {
3507 tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
3508 }
3509
3510 static void wout_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3511 {
3512 tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
3513 }
3514
3515 static void wout_m2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3516 {
3517 tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s));
3518 }
3519
3520 /* ====================================================================== */
3521 /* The "INput 1" generators. These load the first operand to an insn. */
3522
3523 static void in1_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3524 {
3525 o->in1 = load_reg(get_field(f, r1));
3526 }
3527
3528 static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3529 {
3530 o->in1 = regs[get_field(f, r1)];
3531 o->g_in1 = true;
3532 }
3533
3534 static void in1_r1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3535 {
3536 o->in1 = tcg_temp_new_i64();
3537 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r1)]);
3538 }
3539
3540 static void in1_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3541 {
3542 o->in1 = tcg_temp_new_i64();
3543 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r1)]);
3544 }
3545
3546 static void in1_r1_sr32(DisasContext *s, DisasFields *f, DisasOps *o)
3547 {
3548 o->in1 = tcg_temp_new_i64();
3549 tcg_gen_shri_i64(o->in1, regs[get_field(f, r1)], 32);
3550 }
3551
3552 static void in1_r1p1(DisasContext *s, DisasFields *f, DisasOps *o)
3553 {
3554 /* ??? Specification exception: r1 must be even. */
3555 int r1 = get_field(f, r1);
3556 o->in1 = load_reg((r1 + 1) & 15);
3557 }
3558
3559 static void in1_r1p1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3560 {
3561 /* ??? Specification exception: r1 must be even. */
3562 int r1 = get_field(f, r1);
3563 o->in1 = tcg_temp_new_i64();
3564 tcg_gen_ext32s_i64(o->in1, regs[(r1 + 1) & 15]);
3565 }
3566
3567 static void in1_r1p1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3568 {
3569 /* ??? Specification exception: r1 must be even. */
3570 int r1 = get_field(f, r1);
3571 o->in1 = tcg_temp_new_i64();
3572 tcg_gen_ext32u_i64(o->in1, regs[(r1 + 1) & 15]);
3573 }
3574
3575 static void in1_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3576 {
3577 /* ??? Specification exception: r1 must be even. */
3578 int r1 = get_field(f, r1);
3579 o->in1 = tcg_temp_new_i64();
3580 tcg_gen_concat32_i64(o->in1, regs[r1 + 1], regs[r1]);
3581 }
3582
3583 static void in1_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3584 {
3585 o->in1 = load_reg(get_field(f, r2));
3586 }
3587
3588 static void in1_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3589 {
3590 o->in1 = load_reg(get_field(f, r3));
3591 }
3592
3593 static void in1_r3_o(DisasContext *s, DisasFields *f, DisasOps *o)
3594 {
3595 o->in1 = regs[get_field(f, r3)];
3596 o->g_in1 = true;
3597 }
3598
3599 static void in1_r3_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3600 {
3601 o->in1 = tcg_temp_new_i64();
3602 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r3)]);
3603 }
3604
3605 static void in1_r3_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3606 {
3607 o->in1 = tcg_temp_new_i64();
3608 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r3)]);
3609 }
3610
3611 static void in1_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3612 {
3613 o->in1 = load_freg32_i64(get_field(f, r1));
3614 }
3615
3616 static void in1_f1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3617 {
3618 o->in1 = fregs[get_field(f, r1)];
3619 o->g_in1 = true;
3620 }
3621
3622 static void in1_x1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3623 {
3624 /* ??? Specification exception: r1 must be < 14. */
3625 int r1 = get_field(f, r1);
3626 o->out = fregs[r1];
3627 o->out2 = fregs[(r1 + 2) & 15];
3628 o->g_out = o->g_out2 = true;
3629 }
3630
3631 static void in1_la1(DisasContext *s, DisasFields *f, DisasOps *o)
3632 {
3633 o->addr1 = get_address(s, 0, get_field(f, b1), get_field(f, d1));
3634 }
3635
3636 static void in1_la2(DisasContext *s, DisasFields *f, DisasOps *o)
3637 {
3638 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3639 o->addr1 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3640 }
3641
3642 static void in1_m1_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3643 {
3644 in1_la1(s, f, o);
3645 o->in1 = tcg_temp_new_i64();
3646 tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s));
3647 }
3648
3649 static void in1_m1_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3650 {
3651 in1_la1(s, f, o);
3652 o->in1 = tcg_temp_new_i64();
3653 tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s));
3654 }
3655
3656 static void in1_m1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3657 {
3658 in1_la1(s, f, o);
3659 o->in1 = tcg_temp_new_i64();
3660 tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s));
3661 }
3662
3663 static void in1_m1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3664 {
3665 in1_la1(s, f, o);
3666 o->in1 = tcg_temp_new_i64();
3667 tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s));
3668 }
3669
3670 static void in1_m1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3671 {
3672 in1_la1(s, f, o);
3673 o->in1 = tcg_temp_new_i64();
3674 tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s));
3675 }
3676
3677 static void in1_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3678 {
3679 in1_la1(s, f, o);
3680 o->in1 = tcg_temp_new_i64();
3681 tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s));
3682 }
3683
3684 /* ====================================================================== */
3685 /* The "INput 2" generators. These load the second operand to an insn. */
3686
3687 static void in2_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3688 {
3689 o->in2 = regs[get_field(f, r1)];
3690 o->g_in2 = true;
3691 }
3692
3693 static void in2_r1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3694 {
3695 o->in2 = tcg_temp_new_i64();
3696 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r1)]);
3697 }
3698
3699 static void in2_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3700 {
3701 o->in2 = tcg_temp_new_i64();
3702 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r1)]);
3703 }
3704
3705 static void in2_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3706 {
3707 o->in2 = load_reg(get_field(f, r2));
3708 }
3709
3710 static void in2_r2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3711 {
3712 o->in2 = regs[get_field(f, r2)];
3713 o->g_in2 = true;
3714 }
3715
3716 static void in2_r2_nz(DisasContext *s, DisasFields *f, DisasOps *o)
3717 {
3718 int r2 = get_field(f, r2);
3719 if (r2 != 0) {
3720 o->in2 = load_reg(r2);
3721 }
3722 }
3723
3724 static void in2_r2_8s(DisasContext *s, DisasFields *f, DisasOps *o)
3725 {
3726 o->in2 = tcg_temp_new_i64();
3727 tcg_gen_ext8s_i64(o->in2, regs[get_field(f, r2)]);
3728 }
3729
3730 static void in2_r2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3731 {
3732 o->in2 = tcg_temp_new_i64();
3733 tcg_gen_ext8u_i64(o->in2, regs[get_field(f, r2)]);
3734 }
3735
3736 static void in2_r2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3737 {
3738 o->in2 = tcg_temp_new_i64();
3739 tcg_gen_ext16s_i64(o->in2, regs[get_field(f, r2)]);
3740 }
3741
3742 static void in2_r2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3743 {
3744 o->in2 = tcg_temp_new_i64();
3745 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r2)]);
3746 }
3747
3748 static void in2_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3749 {
3750 o->in2 = load_reg(get_field(f, r3));
3751 }
3752
3753 static void in2_r2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3754 {
3755 o->in2 = tcg_temp_new_i64();
3756 tcg_gen_ext32s_i64(o->in2, regs[get_field(f, r2)]);
3757 }
3758
3759 static void in2_r2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3760 {
3761 o->in2 = tcg_temp_new_i64();
3762 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r2)]);
3763 }
3764
3765 static void in2_e2(DisasContext *s, DisasFields *f, DisasOps *o)
3766 {
3767 o->in2 = load_freg32_i64(get_field(f, r2));
3768 }
3769
3770 static void in2_f2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3771 {
3772 o->in2 = fregs[get_field(f, r2)];
3773 o->g_in2 = true;
3774 }
3775
3776 static void in2_x2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3777 {
3778 /* ??? Specification exception: r1 must be < 14. */
3779 int r2 = get_field(f, r2);
3780 o->in1 = fregs[r2];
3781 o->in2 = fregs[(r2 + 2) & 15];
3782 o->g_in1 = o->g_in2 = true;
3783 }
3784
3785 static void in2_ra2(DisasContext *s, DisasFields *f, DisasOps *o)
3786 {
3787 o->in2 = get_address(s, 0, get_field(f, r2), 0);
3788 }
3789
3790 static void in2_a2(DisasContext *s, DisasFields *f, DisasOps *o)
3791 {
3792 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3793 o->in2 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3794 }
3795
3796 static void in2_ri2(DisasContext *s, DisasFields *f, DisasOps *o)
3797 {
3798 o->in2 = tcg_const_i64(s->pc + (int64_t)get_field(f, i2) * 2);
3799 }
3800
3801 static void in2_sh32(DisasContext *s, DisasFields *f, DisasOps *o)
3802 {
3803 help_l2_shift(s, f, o, 31);
3804 }
3805
3806 static void in2_sh64(DisasContext *s, DisasFields *f, DisasOps *o)
3807 {
3808 help_l2_shift(s, f, o, 63);
3809 }
3810
3811 static void in2_m2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3812 {
3813 in2_a2(s, f, o);
3814 tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s));
3815 }
3816
3817 static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3818 {
3819 in2_a2(s, f, o);
3820 tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
3821 }
3822
3823 static void in2_m2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3824 {
3825 in2_a2(s, f, o);
3826 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3827 }
3828
3829 static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3830 {
3831 in2_a2(s, f, o);
3832 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3833 }
3834
3835 static void in2_m2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3836 {
3837 in2_a2(s, f, o);
3838 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3839 }
3840
3841 static void in2_m2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3842 {
3843 in2_a2(s, f, o);
3844 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3845 }
3846
3847 static void in2_mri2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3848 {
3849 in2_ri2(s, f, o);
3850 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3851 }
3852
3853 static void in2_mri2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3854 {
3855 in2_ri2(s, f, o);
3856 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3857 }
3858
3859 static void in2_mri2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3860 {
3861 in2_ri2(s, f, o);
3862 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3863 }
3864
3865 static void in2_mri2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3866 {
3867 in2_ri2(s, f, o);
3868 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3869 }
3870
3871 static void in2_i2(DisasContext *s, DisasFields *f, DisasOps *o)
3872 {
3873 o->in2 = tcg_const_i64(get_field(f, i2));
3874 }
3875
3876 static void in2_i2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3877 {
3878 o->in2 = tcg_const_i64((uint8_t)get_field(f, i2));
3879 }
3880
3881 static void in2_i2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3882 {
3883 o->in2 = tcg_const_i64((uint16_t)get_field(f, i2));
3884 }
3885
3886 static void in2_i2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3887 {
3888 o->in2 = tcg_const_i64((uint32_t)get_field(f, i2));
3889 }
3890
3891 static void in2_i2_16u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
3892 {
3893 uint64_t i2 = (uint16_t)get_field(f, i2);
3894 o->in2 = tcg_const_i64(i2 << s->insn->data);
3895 }
3896
3897 static void in2_i2_32u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
3898 {
3899 uint64_t i2 = (uint32_t)get_field(f, i2);
3900 o->in2 = tcg_const_i64(i2 << s->insn->data);
3901 }
3902
3903 /* ====================================================================== */
3904
3905 /* Find opc within the table of insns. This is formulated as a switch
3906 statement so that (1) we get compile-time notice of cut-paste errors
3907 for duplicated opcodes, and (2) the compiler generates the binary
3908 search tree, rather than us having to post-process the table. */
3909
3910 #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
3911 D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0)
3912
3913 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) insn_ ## NM,
3914
3915 enum DisasInsnEnum {
3916 #include "insn-data.def"
3917 };
3918
3919 #undef D
3920 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) { \
3921 .opc = OPC, \
3922 .fmt = FMT_##FT, \
3923 .fac = FAC_##FC, \
3924 .name = #NM, \
3925 .help_in1 = in1_##I1, \
3926 .help_in2 = in2_##I2, \
3927 .help_prep = prep_##P, \
3928 .help_wout = wout_##W, \
3929 .help_cout = cout_##CC, \
3930 .help_op = op_##OP, \
3931 .data = D \
3932 },
3933
3934 /* Allow 0 to be used for NULL in the table below. */
3935 #define in1_0 NULL
3936 #define in2_0 NULL
3937 #define prep_0 NULL
3938 #define wout_0 NULL
3939 #define cout_0 NULL
3940 #define op_0 NULL
3941
3942 static const DisasInsn insn_info[] = {
3943 #include "insn-data.def"
3944 };
3945
3946 #undef D
3947 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
3948 case OPC: return &insn_info[insn_ ## NM];
3949
3950 static const DisasInsn *lookup_opc(uint16_t opc)
3951 {
3952 switch (opc) {
3953 #include "insn-data.def"
3954 default:
3955 return NULL;
3956 }
3957 }
3958
3959 #undef D
3960 #undef C
3961
3962 /* Extract a field from the insn. The INSN should be left-aligned in
3963 the uint64_t so that we can more easily utilize the big-bit-endian
3964 definitions we extract from the Principals of Operation. */
3965
3966 static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn)
3967 {
3968 uint32_t r, m;
3969
3970 if (f->size == 0) {
3971 return;
3972 }
3973
3974 /* Zero extract the field from the insn. */
3975 r = (insn << f->beg) >> (64 - f->size);
3976
3977 /* Sign-extend, or un-swap the field as necessary. */
3978 switch (f->type) {
3979 case 0: /* unsigned */
3980 break;
3981 case 1: /* signed */
3982 assert(f->size <= 32);
3983 m = 1u << (f->size - 1);
3984 r = (r ^ m) - m;
3985 break;
3986 case 2: /* dl+dh split, signed 20 bit. */
3987 r = ((int8_t)r << 12) | (r >> 8);
3988 break;
3989 default:
3990 abort();
3991 }
3992
3993 /* Validate that the "compressed" encoding we selected above is valid.
3994 I.e. we havn't make two different original fields overlap. */
3995 assert(((o->presentC >> f->indexC) & 1) == 0);
3996 o->presentC |= 1 << f->indexC;
3997 o->presentO |= 1 << f->indexO;
3998
3999 o->c[f->indexC] = r;
4000 }
4001
4002 /* Lookup the insn at the current PC, extracting the operands into O and
4003 returning the info struct for the insn. Returns NULL for invalid insn. */
4004
4005 static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
4006 DisasFields *f)
4007 {
4008 uint64_t insn, pc = s->pc;
4009 int op, op2, ilen;
4010 const DisasInsn *info;
4011
4012 insn = ld_code2(env, pc);
4013 op = (insn >> 8) & 0xff;
4014 ilen = get_ilen(op);
4015 s->next_pc = s->pc + ilen;
4016
4017 switch (ilen) {
4018 case 2:
4019 insn = insn << 48;
4020 break;
4021 case 4:
4022 insn = ld_code4(env, pc) << 32;
4023 break;
4024 case 6:
4025 insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
4026 break;
4027 default:
4028 abort();
4029 }
4030
4031 /* We can't actually determine the insn format until we've looked up
4032 the full insn opcode. Which we can't do without locating the
4033 secondary opcode. Assume by default that OP2 is at bit 40; for
4034 those smaller insns that don't actually have a secondary opcode
4035 this will correctly result in OP2 = 0. */
4036 switch (op) {
4037 case 0x01: /* E */
4038 case 0x80: /* S */
4039 case 0x82: /* S */
4040 case 0x93: /* S */
4041 case 0xb2: /* S, RRF, RRE */
4042 case 0xb3: /* RRE, RRD, RRF */
4043 case 0xb9: /* RRE, RRF */
4044 case 0xe5: /* SSE, SIL */
4045 op2 = (insn << 8) >> 56;
4046 break;
4047 case 0xa5: /* RI */
4048 case 0xa7: /* RI */
4049 case 0xc0: /* RIL */
4050 case 0xc2: /* RIL */
4051 case 0xc4: /* RIL */
4052 case 0xc6: /* RIL */
4053 case 0xc8: /* SSF */
4054 case 0xcc: /* RIL */
4055 op2 = (insn << 12) >> 60;
4056 break;
4057 case 0xd0 ... 0xdf: /* SS */
4058 case 0xe1: /* SS */
4059 case 0xe2: /* SS */
4060 case 0xe8: /* SS */
4061 case 0xe9: /* SS */
4062 case 0xea: /* SS */
4063 case 0xee ... 0xf3: /* SS */
4064 case 0xf8 ... 0xfd: /* SS */
4065 op2 = 0;
4066 break;
4067 default:
4068 op2 = (insn << 40) >> 56;
4069 break;
4070 }
4071
4072 memset(f, 0, sizeof(*f));
4073 f->op = op;
4074 f->op2 = op2;
4075
4076 /* Lookup the instruction. */
4077 info = lookup_opc(op << 8 | op2);
4078
4079 /* If we found it, extract the operands. */
4080 if (info != NULL) {
4081 DisasFormat fmt = info->fmt;
4082 int i;
4083
4084 for (i = 0; i < NUM_C_FIELD; ++i) {
4085 extract_field(f, &format_info[fmt].op[i], insn);
4086 }
4087 }
4088 return info;
4089 }
4090
4091 static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
4092 {
4093 const DisasInsn *insn;
4094 ExitStatus ret = NO_EXIT;
4095 DisasFields f;
4096 DisasOps o;
4097
4098 /* Search for the insn in the table. */
4099 insn = extract_insn(env, s, &f);
4100
4101 /* Not found means unimplemented/illegal opcode. */
4102 if (insn == NULL) {
4103 qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%02x%02x\n",
4104 f.op, f.op2);
4105 gen_illegal_opcode(s);
4106 return EXIT_NORETURN;
4107 }
4108
4109 /* Set up the strutures we use to communicate with the helpers. */
4110 s->insn = insn;
4111 s->fields = &f;
4112 o.g_out = o.g_out2 = o.g_in1 = o.g_in2 = false;
4113 TCGV_UNUSED_I64(o.out);
4114 TCGV_UNUSED_I64(o.out2);
4115 TCGV_UNUSED_I64(o.in1);
4116 TCGV_UNUSED_I64(o.in2);
4117 TCGV_UNUSED_I64(o.addr1);
4118
4119 /* Implement the instruction. */
4120 if (insn->help_in1) {
4121 insn->help_in1(s, &f, &o);
4122 }
4123 if (insn->help_in2) {
4124 insn->help_in2(s, &f, &o);
4125 }
4126 if (insn->help_prep) {
4127 insn->help_prep(s, &f, &o);
4128 }
4129 if (insn->help_op) {
4130 ret = insn->help_op(s, &o);
4131 }
4132 if (insn->help_wout) {
4133 insn->help_wout(s, &f, &o);
4134 }
4135 if (insn->help_cout) {
4136 insn->help_cout(s, &o);
4137 }
4138
4139 /* Free any temporaries created by the helpers. */
4140 if (!TCGV_IS_UNUSED_I64(o.out) && !o.g_out) {
4141 tcg_temp_free_i64(o.out);
4142 }
4143 if (!TCGV_IS_UNUSED_I64(o.out2) && !o.g_out2) {
4144 tcg_temp_free_i64(o.out2);
4145 }
4146 if (!TCGV_IS_UNUSED_I64(o.in1) && !o.g_in1) {
4147 tcg_temp_free_i64(o.in1);
4148 }
4149 if (!TCGV_IS_UNUSED_I64(o.in2) && !o.g_in2) {
4150 tcg_temp_free_i64(o.in2);
4151 }
4152 if (!TCGV_IS_UNUSED_I64(o.addr1)) {
4153 tcg_temp_free_i64(o.addr1);
4154 }
4155
4156 /* Advance to the next instruction. */
4157 s->pc = s->next_pc;
4158 return ret;
4159 }
4160
4161 static inline void gen_intermediate_code_internal(CPUS390XState *env,
4162 TranslationBlock *tb,
4163 int search_pc)
4164 {
4165 DisasContext dc;
4166 target_ulong pc_start;
4167 uint64_t next_page_start;
4168 uint16_t *gen_opc_end;
4169 int j, lj = -1;
4170 int num_insns, max_insns;
4171 CPUBreakpoint *bp;
4172 ExitStatus status;
4173 bool do_debug;
4174
4175 pc_start = tb->pc;
4176
4177 /* 31-bit mode */
4178 if (!(tb->flags & FLAG_MASK_64)) {
4179 pc_start &= 0x7fffffff;
4180 }
4181
4182 dc.tb = tb;
4183 dc.pc = pc_start;
4184 dc.cc_op = CC_OP_DYNAMIC;
4185 do_debug = dc.singlestep_enabled = env->singlestep_enabled;
4186
4187 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
4188
4189 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4190
4191 num_insns = 0;
4192 max_insns = tb->cflags & CF_COUNT_MASK;
4193 if (max_insns == 0) {
4194 max_insns = CF_COUNT_MASK;
4195 }
4196
4197 gen_icount_start();
4198
4199 do {
4200 if (search_pc) {
4201 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4202 if (lj < j) {
4203 lj++;
4204 while (lj < j) {
4205 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4206 }
4207 }
4208 tcg_ctx.gen_opc_pc[lj] = dc.pc;
4209 gen_opc_cc_op[lj] = dc.cc_op;
4210 tcg_ctx.gen_opc_instr_start[lj] = 1;
4211 tcg_ctx.gen_opc_icount[lj] = num_insns;
4212 }
4213 if (++num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
4214 gen_io_start();
4215 }
4216
4217 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4218 tcg_gen_debug_insn_start(dc.pc);
4219 }
4220
4221 status = NO_EXIT;
4222 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
4223 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
4224 if (bp->pc == dc.pc) {
4225 status = EXIT_PC_STALE;
4226 do_debug = true;
4227 break;
4228 }
4229 }
4230 }
4231 if (status == NO_EXIT) {
4232 status = translate_one(env, &dc);
4233 }
4234
4235 /* If we reach a page boundary, are single stepping,
4236 or exhaust instruction count, stop generation. */
4237 if (status == NO_EXIT
4238 && (dc.pc >= next_page_start
4239 || tcg_ctx.gen_opc_ptr >= gen_opc_end
4240 || num_insns >= max_insns
4241 || singlestep
4242 || env->singlestep_enabled)) {
4243 status = EXIT_PC_STALE;
4244 }
4245 } while (status == NO_EXIT);
4246
4247 if (tb->cflags & CF_LAST_IO) {
4248 gen_io_end();
4249 }
4250
4251 switch (status) {
4252 case EXIT_GOTO_TB:
4253 case EXIT_NORETURN:
4254 break;
4255 case EXIT_PC_STALE:
4256 update_psw_addr(&dc);
4257 /* FALLTHRU */
4258 case EXIT_PC_UPDATED:
4259 /* Next TB starts off with CC_OP_DYNAMIC, so make sure the
4260 cc op type is in env */
4261 update_cc_op(&dc);
4262 /* Exit the TB, either by raising a debug exception or by return. */
4263 if (do_debug) {
4264 gen_exception(EXCP_DEBUG);
4265 } else {
4266 tcg_gen_exit_tb(0);
4267 }
4268 break;
4269 default:
4270 abort();
4271 }
4272
4273 gen_icount_end(tb, num_insns);
4274 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
4275 if (search_pc) {
4276 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4277 lj++;
4278 while (lj <= j) {
4279 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4280 }
4281 } else {
4282 tb->size = dc.pc - pc_start;
4283 tb->icount = num_insns;
4284 }
4285
4286 #if defined(S390X_DEBUG_DISAS)
4287 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
4288 qemu_log("IN: %s\n", lookup_symbol(pc_start));
4289 log_target_disas(env, pc_start, dc.pc - pc_start, 1);
4290 qemu_log("\n");
4291 }
4292 #endif
4293 }
4294
4295 void gen_intermediate_code (CPUS390XState *env, struct TranslationBlock *tb)
4296 {
4297 gen_intermediate_code_internal(env, tb, 0);
4298 }
4299
4300 void gen_intermediate_code_pc (CPUS390XState *env, struct TranslationBlock *tb)
4301 {
4302 gen_intermediate_code_internal(env, tb, 1);
4303 }
4304
4305 void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos)
4306 {
4307 int cc_op;
4308 env->psw.addr = tcg_ctx.gen_opc_pc[pc_pos];
4309 cc_op = gen_opc_cc_op[pc_pos];
4310 if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {
4311 env->cc_op = cc_op;
4312 }
4313 }
Qemu copy for testing