4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
26 /* #define DEBUG_ILLEGAL_INSTRUCTIONS */
27 /* #define DEBUG_INLINE_BRANCHES */
28 #define S390X_DEBUG_DISAS
29 /* #define S390X_DEBUG_DISAS_VERBOSE */
31 #ifdef S390X_DEBUG_DISAS_VERBOSE
32 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
34 # define LOG_DISAS(...) do { } while (0)
43 /* global register indexes */
44 static TCGv_ptr cpu_env
;
46 #include "gen-icount.h"
51 typedef struct DisasContext DisasContext
;
56 struct TranslationBlock
*tb
;
61 static void gen_op_calc_cc(DisasContext
*s
);
63 #ifdef DEBUG_INLINE_BRANCHES
64 static uint64_t inline_branch_hit
[CC_OP_MAX
];
65 static uint64_t inline_branch_miss
[CC_OP_MAX
];
68 static inline void debug_insn(uint64_t insn
)
70 LOG_DISAS("insn: 0x%" PRIx64
"\n", insn
);
73 static inline uint64_t pc_to_link_info(DisasContext
*s
, uint64_t pc
)
75 if (!(s
->tb
->flags
& FLAG_MASK_64
)) {
76 if (s
->tb
->flags
& FLAG_MASK_32
) {
77 return pc
| 0x80000000;
83 void cpu_dump_state(CPUState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
88 for (i
= 0; i
< 16; i
++) {
89 cpu_fprintf(f
, "R%02d=%016" PRIx64
, i
, env
->regs
[i
]);
97 for (i
= 0; i
< 16; i
++) {
98 cpu_fprintf(f
, "F%02d=%016" PRIx64
, i
, *(uint64_t *)&env
->fregs
[i
]);
100 cpu_fprintf(f
, "\n");
106 cpu_fprintf(f
, "\n");
108 #ifndef CONFIG_USER_ONLY
109 for (i
= 0; i
< 16; i
++) {
110 cpu_fprintf(f
, "C%02d=%016" PRIx64
, i
, env
->cregs
[i
]);
112 cpu_fprintf(f
, "\n");
119 cpu_fprintf(f
, "\n");
121 if (env
->cc_op
> 3) {
122 cpu_fprintf(f
, "PSW=mask %016" PRIx64
" addr %016" PRIx64
" cc %15s\n",
123 env
->psw
.mask
, env
->psw
.addr
, cc_name(env
->cc_op
));
125 cpu_fprintf(f
, "PSW=mask %016" PRIx64
" addr %016" PRIx64
" cc %02x\n",
126 env
->psw
.mask
, env
->psw
.addr
, env
->cc_op
);
129 #ifdef DEBUG_INLINE_BRANCHES
130 for (i
= 0; i
< CC_OP_MAX
; i
++) {
131 cpu_fprintf(f
, " %15s = %10ld\t%10ld\n", cc_name(i
),
132 inline_branch_miss
[i
], inline_branch_hit
[i
]);
137 static TCGv_i64 psw_addr
;
138 static TCGv_i64 psw_mask
;
140 static TCGv_i32 cc_op
;
141 static TCGv_i64 cc_src
;
142 static TCGv_i64 cc_dst
;
143 static TCGv_i64 cc_vr
;
145 static char cpu_reg_names
[10*3 + 6*4];
146 static TCGv_i64 regs
[16];
148 static uint8_t gen_opc_cc_op
[OPC_BUF_SIZE
];
150 void s390x_translate_init(void)
153 size_t cpu_reg_names_size
= sizeof(cpu_reg_names
);
156 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
157 psw_addr
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUState
, psw
.addr
),
159 psw_mask
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUState
, psw
.mask
),
162 cc_op
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUState
, cc_op
),
164 cc_src
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUState
, cc_src
),
166 cc_dst
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUState
, cc_dst
),
168 cc_vr
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUState
, cc_vr
),
172 for (i
= 0; i
< 16; i
++) {
173 snprintf(p
, cpu_reg_names_size
, "r%d", i
);
174 regs
[i
] = tcg_global_mem_new(TCG_AREG0
,
175 offsetof(CPUState
, regs
[i
]), p
);
176 p
+= (i
< 10) ? 3 : 4;
177 cpu_reg_names_size
-= (i
< 10) ? 3 : 4;
181 static inline TCGv_i64
load_reg(int reg
)
183 TCGv_i64 r
= tcg_temp_new_i64();
184 tcg_gen_mov_i64(r
, regs
[reg
]);
188 static inline TCGv_i64
load_freg(int reg
)
190 TCGv_i64 r
= tcg_temp_new_i64();
191 tcg_gen_ld_i64(r
, cpu_env
, offsetof(CPUState
, fregs
[reg
].d
));
195 static inline TCGv_i32
load_freg32(int reg
)
197 TCGv_i32 r
= tcg_temp_new_i32();
198 tcg_gen_ld_i32(r
, cpu_env
, offsetof(CPUState
, fregs
[reg
].l
.upper
));
202 static inline TCGv_i32
load_reg32(int reg
)
204 TCGv_i32 r
= tcg_temp_new_i32();
205 tcg_gen_trunc_i64_i32(r
, regs
[reg
]);
209 static inline TCGv_i64
load_reg32_i64(int reg
)
211 TCGv_i64 r
= tcg_temp_new_i64();
212 tcg_gen_ext32s_i64(r
, regs
[reg
]);
216 static inline void store_reg(int reg
, TCGv_i64 v
)
218 tcg_gen_mov_i64(regs
[reg
], v
);
221 static inline void store_freg(int reg
, TCGv_i64 v
)
223 tcg_gen_st_i64(v
, cpu_env
, offsetof(CPUState
, fregs
[reg
].d
));
226 static inline void store_reg32(int reg
, TCGv_i32 v
)
228 #if HOST_LONG_BITS == 32
229 tcg_gen_mov_i32(TCGV_LOW(regs
[reg
]), v
);
231 TCGv_i64 tmp
= tcg_temp_new_i64();
232 tcg_gen_extu_i32_i64(tmp
, v
);
233 /* 32 bit register writes keep the upper half */
234 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
], tmp
, 0, 32);
235 tcg_temp_free_i64(tmp
);
239 static inline void store_reg32_i64(int reg
, TCGv_i64 v
)
241 /* 32 bit register writes keep the upper half */
242 #if HOST_LONG_BITS == 32
243 tcg_gen_mov_i32(TCGV_LOW(regs
[reg
]), TCGV_LOW(v
));
245 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
], v
, 0, 32);
249 static inline void store_reg16(int reg
, TCGv_i32 v
)
251 TCGv_i64 tmp
= tcg_temp_new_i64();
252 tcg_gen_extu_i32_i64(tmp
, v
);
253 /* 16 bit register writes keep the upper bytes */
254 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
], tmp
, 0, 16);
255 tcg_temp_free_i64(tmp
);
258 static inline void store_reg8(int reg
, TCGv_i64 v
)
260 /* 8 bit register writes keep the upper bytes */
261 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
], v
, 0, 8);
264 static inline void store_freg32(int reg
, TCGv_i32 v
)
266 tcg_gen_st_i32(v
, cpu_env
, offsetof(CPUState
, fregs
[reg
].l
.upper
));
269 static inline void update_psw_addr(DisasContext
*s
)
272 tcg_gen_movi_i64(psw_addr
, s
->pc
);
275 static inline void potential_page_fault(DisasContext
*s
)
277 #ifndef CONFIG_USER_ONLY
283 static inline uint64_t ld_code2(uint64_t pc
)
285 return (uint64_t)lduw_code(pc
);
288 static inline uint64_t ld_code4(uint64_t pc
)
290 return (uint64_t)ldl_code(pc
);
293 static inline uint64_t ld_code6(uint64_t pc
)
296 opc
= (uint64_t)lduw_code(pc
) << 32;
297 opc
|= (uint64_t)(uint32_t)ldl_code(pc
+2);
301 static inline int get_mem_index(DisasContext
*s
)
303 switch (s
->tb
->flags
& FLAG_MASK_ASC
) {
304 case PSW_ASC_PRIMARY
>> 32:
306 case PSW_ASC_SECONDARY
>> 32:
308 case PSW_ASC_HOME
>> 32:
316 static inline void gen_debug(DisasContext
*s
)
318 TCGv_i32 tmp
= tcg_const_i32(EXCP_DEBUG
);
321 gen_helper_exception(tmp
);
322 tcg_temp_free_i32(tmp
);
323 s
->is_jmp
= DISAS_EXCP
;
326 #ifdef CONFIG_USER_ONLY
328 static void gen_illegal_opcode(DisasContext
*s
, int ilc
)
330 TCGv_i32 tmp
= tcg_const_i32(EXCP_SPEC
);
333 gen_helper_exception(tmp
);
334 tcg_temp_free_i32(tmp
);
335 s
->is_jmp
= DISAS_EXCP
;
338 #else /* CONFIG_USER_ONLY */
340 static void debug_print_inst(DisasContext
*s
, int ilc
)
342 #ifdef DEBUG_ILLEGAL_INSTRUCTIONS
347 inst
= ld_code2(s
->pc
);
350 inst
= ld_code4(s
->pc
);
353 inst
= ld_code6(s
->pc
);
357 fprintf(stderr
, "Illegal instruction [%d at %016" PRIx64
"]: 0x%016"
358 PRIx64
"\n", ilc
, s
->pc
, inst
);
362 static void gen_program_exception(DisasContext
*s
, int ilc
, int code
)
366 debug_print_inst(s
, ilc
);
368 /* remember what pgm exeption this was */
369 tmp
= tcg_const_i32(code
);
370 tcg_gen_st_i32(tmp
, cpu_env
, offsetof(CPUState
, int_pgm_code
));
371 tcg_temp_free_i32(tmp
);
373 tmp
= tcg_const_i32(ilc
);
374 tcg_gen_st_i32(tmp
, cpu_env
, offsetof(CPUState
, int_pgm_ilc
));
375 tcg_temp_free_i32(tmp
);
377 /* advance past instruction */
384 /* trigger exception */
385 tmp
= tcg_const_i32(EXCP_PGM
);
386 gen_helper_exception(tmp
);
387 tcg_temp_free_i32(tmp
);
390 s
->is_jmp
= DISAS_EXCP
;
394 static void gen_illegal_opcode(DisasContext
*s
, int ilc
)
396 gen_program_exception(s
, ilc
, PGM_SPECIFICATION
);
399 static void gen_privileged_exception(DisasContext
*s
, int ilc
)
401 gen_program_exception(s
, ilc
, PGM_PRIVILEGED
);
404 static void check_privileged(DisasContext
*s
, int ilc
)
406 if (s
->tb
->flags
& (PSW_MASK_PSTATE
>> 32)) {
407 gen_privileged_exception(s
, ilc
);
411 #endif /* CONFIG_USER_ONLY */
413 static TCGv_i64
get_address(DisasContext
*s
, int x2
, int b2
, int d2
)
417 /* 31-bitify the immediate part; register contents are dealt with below */
418 if (!(s
->tb
->flags
& FLAG_MASK_64
)) {
424 tmp
= tcg_const_i64(d2
);
425 tcg_gen_add_i64(tmp
, tmp
, regs
[x2
]);
430 tcg_gen_add_i64(tmp
, tmp
, regs
[b2
]);
434 tmp
= tcg_const_i64(d2
);
435 tcg_gen_add_i64(tmp
, tmp
, regs
[b2
]);
440 tmp
= tcg_const_i64(d2
);
443 /* 31-bit mode mask if there are values loaded from registers */
444 if (!(s
->tb
->flags
& FLAG_MASK_64
) && (x2
|| b2
)) {
445 tcg_gen_andi_i64(tmp
, tmp
, 0x7fffffffUL
);
451 static void gen_op_movi_cc(DisasContext
*s
, uint32_t val
)
453 s
->cc_op
= CC_OP_CONST0
+ val
;
456 static void gen_op_update1_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 dst
)
458 tcg_gen_discard_i64(cc_src
);
459 tcg_gen_mov_i64(cc_dst
, dst
);
460 tcg_gen_discard_i64(cc_vr
);
464 static void gen_op_update1_cc_i32(DisasContext
*s
, enum cc_op op
, TCGv_i32 dst
)
466 tcg_gen_discard_i64(cc_src
);
467 tcg_gen_extu_i32_i64(cc_dst
, dst
);
468 tcg_gen_discard_i64(cc_vr
);
472 static void gen_op_update2_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 src
,
475 tcg_gen_mov_i64(cc_src
, src
);
476 tcg_gen_mov_i64(cc_dst
, dst
);
477 tcg_gen_discard_i64(cc_vr
);
481 static void gen_op_update2_cc_i32(DisasContext
*s
, enum cc_op op
, TCGv_i32 src
,
484 tcg_gen_extu_i32_i64(cc_src
, src
);
485 tcg_gen_extu_i32_i64(cc_dst
, dst
);
486 tcg_gen_discard_i64(cc_vr
);
490 static void gen_op_update3_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 src
,
491 TCGv_i64 dst
, TCGv_i64 vr
)
493 tcg_gen_mov_i64(cc_src
, src
);
494 tcg_gen_mov_i64(cc_dst
, dst
);
495 tcg_gen_mov_i64(cc_vr
, vr
);
499 static void gen_op_update3_cc_i32(DisasContext
*s
, enum cc_op op
, TCGv_i32 src
,
500 TCGv_i32 dst
, TCGv_i32 vr
)
502 tcg_gen_extu_i32_i64(cc_src
, src
);
503 tcg_gen_extu_i32_i64(cc_dst
, dst
);
504 tcg_gen_extu_i32_i64(cc_vr
, vr
);
508 static inline void set_cc_nz_u32(DisasContext
*s
, TCGv_i32 val
)
510 gen_op_update1_cc_i32(s
, CC_OP_NZ
, val
);
513 static inline void set_cc_nz_u64(DisasContext
*s
, TCGv_i64 val
)
515 gen_op_update1_cc_i64(s
, CC_OP_NZ
, val
);
518 static inline void cmp_32(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
,
521 gen_op_update2_cc_i32(s
, cond
, v1
, v2
);
524 static inline void cmp_64(DisasContext
*s
, TCGv_i64 v1
, TCGv_i64 v2
,
527 gen_op_update2_cc_i64(s
, cond
, v1
, v2
);
530 static inline void cmp_s32(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
)
532 cmp_32(s
, v1
, v2
, CC_OP_LTGT_32
);
535 static inline void cmp_u32(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
)
537 cmp_32(s
, v1
, v2
, CC_OP_LTUGTU_32
);
540 static inline void cmp_s32c(DisasContext
*s
, TCGv_i32 v1
, int32_t v2
)
542 /* XXX optimize for the constant? put it in s? */
543 TCGv_i32 tmp
= tcg_const_i32(v2
);
544 cmp_32(s
, v1
, tmp
, CC_OP_LTGT_32
);
545 tcg_temp_free_i32(tmp
);
548 static inline void cmp_u32c(DisasContext
*s
, TCGv_i32 v1
, uint32_t v2
)
550 TCGv_i32 tmp
= tcg_const_i32(v2
);
551 cmp_32(s
, v1
, tmp
, CC_OP_LTUGTU_32
);
552 tcg_temp_free_i32(tmp
);
555 static inline void cmp_s64(DisasContext
*s
, TCGv_i64 v1
, TCGv_i64 v2
)
557 cmp_64(s
, v1
, v2
, CC_OP_LTGT_64
);
560 static inline void cmp_u64(DisasContext
*s
, TCGv_i64 v1
, TCGv_i64 v2
)
562 cmp_64(s
, v1
, v2
, CC_OP_LTUGTU_64
);
565 static inline void cmp_s64c(DisasContext
*s
, TCGv_i64 v1
, int64_t v2
)
567 TCGv_i64 tmp
= tcg_const_i64(v2
);
569 tcg_temp_free_i64(tmp
);
572 static inline void cmp_u64c(DisasContext
*s
, TCGv_i64 v1
, uint64_t v2
)
574 TCGv_i64 tmp
= tcg_const_i64(v2
);
576 tcg_temp_free_i64(tmp
);
579 static inline void set_cc_s32(DisasContext
*s
, TCGv_i32 val
)
581 gen_op_update1_cc_i32(s
, CC_OP_LTGT0_32
, val
);
584 static inline void set_cc_s64(DisasContext
*s
, TCGv_i64 val
)
586 gen_op_update1_cc_i64(s
, CC_OP_LTGT0_64
, val
);
589 static void set_cc_add64(DisasContext
*s
, TCGv_i64 v1
, TCGv_i64 v2
, TCGv_i64 vr
)
591 gen_op_update3_cc_i64(s
, CC_OP_ADD_64
, v1
, v2
, vr
);
594 static void set_cc_addu64(DisasContext
*s
, TCGv_i64 v1
, TCGv_i64 v2
,
597 gen_op_update3_cc_i64(s
, CC_OP_ADDU_64
, v1
, v2
, vr
);
600 static void set_cc_sub64(DisasContext
*s
, TCGv_i64 v1
, TCGv_i64 v2
, TCGv_i64 vr
)
602 gen_op_update3_cc_i64(s
, CC_OP_SUB_64
, v1
, v2
, vr
);
605 static void set_cc_subu64(DisasContext
*s
, TCGv_i64 v1
, TCGv_i64 v2
,
608 gen_op_update3_cc_i64(s
, CC_OP_SUBU_64
, v1
, v2
, vr
);
611 static void set_cc_abs64(DisasContext
*s
, TCGv_i64 v1
)
613 gen_op_update1_cc_i64(s
, CC_OP_ABS_64
, v1
);
616 static void set_cc_nabs64(DisasContext
*s
, TCGv_i64 v1
)
618 gen_op_update1_cc_i64(s
, CC_OP_NABS_64
, v1
);
621 static void set_cc_add32(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
, TCGv_i32 vr
)
623 gen_op_update3_cc_i32(s
, CC_OP_ADD_32
, v1
, v2
, vr
);
626 static void set_cc_addu32(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
,
629 gen_op_update3_cc_i32(s
, CC_OP_ADDU_32
, v1
, v2
, vr
);
632 static void set_cc_sub32(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
, TCGv_i32 vr
)
634 gen_op_update3_cc_i32(s
, CC_OP_SUB_32
, v1
, v2
, vr
);
637 static void set_cc_subu32(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
,
640 gen_op_update3_cc_i32(s
, CC_OP_SUBU_32
, v1
, v2
, vr
);
643 static void set_cc_abs32(DisasContext
*s
, TCGv_i32 v1
)
645 gen_op_update1_cc_i32(s
, CC_OP_ABS_32
, v1
);
648 static void set_cc_nabs32(DisasContext
*s
, TCGv_i32 v1
)
650 gen_op_update1_cc_i32(s
, CC_OP_NABS_32
, v1
);
653 static void set_cc_comp32(DisasContext
*s
, TCGv_i32 v1
)
655 gen_op_update1_cc_i32(s
, CC_OP_COMP_32
, v1
);
658 static void set_cc_comp64(DisasContext
*s
, TCGv_i64 v1
)
660 gen_op_update1_cc_i64(s
, CC_OP_COMP_64
, v1
);
663 static void set_cc_icm(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
)
665 gen_op_update2_cc_i32(s
, CC_OP_ICM
, v1
, v2
);
668 static void set_cc_cmp_f32_i64(DisasContext
*s
, TCGv_i32 v1
, TCGv_i64 v2
)
670 tcg_gen_extu_i32_i64(cc_src
, v1
);
671 tcg_gen_mov_i64(cc_dst
, v2
);
672 tcg_gen_discard_i64(cc_vr
);
673 s
->cc_op
= CC_OP_LTGT_F32
;
676 static void set_cc_nz_f32(DisasContext
*s
, TCGv_i32 v1
)
678 gen_op_update1_cc_i32(s
, CC_OP_NZ_F32
, v1
);
681 static inline void set_cc_nz_f64(DisasContext
*s
, TCGv_i64 v1
)
683 gen_op_update1_cc_i64(s
, CC_OP_NZ_F64
, v1
);
686 /* CC value is in env->cc_op */
687 static inline void set_cc_static(DisasContext
*s
)
689 tcg_gen_discard_i64(cc_src
);
690 tcg_gen_discard_i64(cc_dst
);
691 tcg_gen_discard_i64(cc_vr
);
692 s
->cc_op
= CC_OP_STATIC
;
695 static inline void gen_op_set_cc_op(DisasContext
*s
)
697 if (s
->cc_op
!= CC_OP_DYNAMIC
&& s
->cc_op
!= CC_OP_STATIC
) {
698 tcg_gen_movi_i32(cc_op
, s
->cc_op
);
702 static inline void gen_update_cc_op(DisasContext
*s
)
707 /* calculates cc into cc_op */
708 static void gen_op_calc_cc(DisasContext
*s
)
710 TCGv_i32 local_cc_op
= tcg_const_i32(s
->cc_op
);
711 TCGv_i64 dummy
= tcg_const_i64(0);
718 /* s->cc_op is the cc value */
719 tcg_gen_movi_i32(cc_op
, s
->cc_op
- CC_OP_CONST0
);
722 /* env->cc_op already is the cc value */
736 gen_helper_calc_cc(cc_op
, local_cc_op
, dummy
, cc_dst
, dummy
);
741 case CC_OP_LTUGTU_32
:
742 case CC_OP_LTUGTU_64
:
749 gen_helper_calc_cc(cc_op
, local_cc_op
, cc_src
, cc_dst
, dummy
);
760 gen_helper_calc_cc(cc_op
, local_cc_op
, cc_src
, cc_dst
, cc_vr
);
763 /* unknown operation - assume 3 arguments and cc_op in env */
764 gen_helper_calc_cc(cc_op
, cc_op
, cc_src
, cc_dst
, cc_vr
);
770 tcg_temp_free_i32(local_cc_op
);
772 /* We now have cc in cc_op as constant */
776 static inline void decode_rr(DisasContext
*s
, uint64_t insn
, int *r1
, int *r2
)
780 *r1
= (insn
>> 4) & 0xf;
784 static inline TCGv_i64
decode_rx(DisasContext
*s
, uint64_t insn
, int *r1
,
785 int *x2
, int *b2
, int *d2
)
789 *r1
= (insn
>> 20) & 0xf;
790 *x2
= (insn
>> 16) & 0xf;
791 *b2
= (insn
>> 12) & 0xf;
794 return get_address(s
, *x2
, *b2
, *d2
);
797 static inline void decode_rs(DisasContext
*s
, uint64_t insn
, int *r1
, int *r3
,
802 *r1
= (insn
>> 20) & 0xf;
804 *r3
= (insn
>> 16) & 0xf;
805 *b2
= (insn
>> 12) & 0xf;
809 static inline TCGv_i64
decode_si(DisasContext
*s
, uint64_t insn
, int *i2
,
814 *i2
= (insn
>> 16) & 0xff;
815 *b1
= (insn
>> 12) & 0xf;
818 return get_address(s
, 0, *b1
, *d1
);
821 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
, target_ulong pc
)
823 TranslationBlock
*tb
;
828 /* NOTE: we handle the case where the TB spans two pages here */
829 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) ||
830 (pc
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
)) {
831 /* jump to same page: we can use a direct jump */
832 tcg_gen_goto_tb(tb_num
);
833 tcg_gen_movi_i64(psw_addr
, pc
);
834 tcg_gen_exit_tb((long)tb
+ tb_num
);
836 /* jump to another page: currently not optimized */
837 tcg_gen_movi_i64(psw_addr
, pc
);
842 static inline void account_noninline_branch(DisasContext
*s
, int cc_op
)
844 #ifdef DEBUG_INLINE_BRANCHES
845 inline_branch_miss
[cc_op
]++;
849 static inline void account_inline_branch(DisasContext
*s
)
851 #ifdef DEBUG_INLINE_BRANCHES
852 inline_branch_hit
[s
->cc_op
]++;
856 static void gen_jcc(DisasContext
*s
, uint32_t mask
, int skip
)
858 TCGv_i32 tmp
, tmp2
, r
;
864 tmp
= tcg_temp_new_i32();
865 tcg_gen_trunc_i64_i32(tmp
, cc_dst
);
867 case 0x8 | 0x4: /* dst <= 0 */
868 tcg_gen_brcondi_i32(TCG_COND_GT
, tmp
, 0, skip
);
870 case 0x8 | 0x2: /* dst >= 0 */
871 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, skip
);
873 case 0x8: /* dst == 0 */
874 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, skip
);
876 case 0x7: /* dst != 0 */
877 case 0x6: /* dst != 0 */
878 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, skip
);
880 case 0x4: /* dst < 0 */
881 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, skip
);
883 case 0x2: /* dst > 0 */
884 tcg_gen_brcondi_i32(TCG_COND_LE
, tmp
, 0, skip
);
887 tcg_temp_free_i32(tmp
);
890 account_inline_branch(s
);
891 tcg_temp_free_i32(tmp
);
895 case 0x8 | 0x4: /* dst <= 0 */
896 tcg_gen_brcondi_i64(TCG_COND_GT
, cc_dst
, 0, skip
);
898 case 0x8 | 0x2: /* dst >= 0 */
899 tcg_gen_brcondi_i64(TCG_COND_LT
, cc_dst
, 0, skip
);
901 case 0x8: /* dst == 0 */
902 tcg_gen_brcondi_i64(TCG_COND_NE
, cc_dst
, 0, skip
);
904 case 0x7: /* dst != 0 */
905 case 0x6: /* dst != 0 */
906 tcg_gen_brcondi_i64(TCG_COND_EQ
, cc_dst
, 0, skip
);
908 case 0x4: /* dst < 0 */
909 tcg_gen_brcondi_i64(TCG_COND_GE
, cc_dst
, 0, skip
);
911 case 0x2: /* dst > 0 */
912 tcg_gen_brcondi_i64(TCG_COND_LE
, cc_dst
, 0, skip
);
917 account_inline_branch(s
);
920 tmp
= tcg_temp_new_i32();
921 tmp2
= tcg_temp_new_i32();
922 tcg_gen_trunc_i64_i32(tmp
, cc_src
);
923 tcg_gen_trunc_i64_i32(tmp2
, cc_dst
);
925 case 0x8 | 0x4: /* src <= dst */
926 tcg_gen_brcond_i32(TCG_COND_GT
, tmp
, tmp2
, skip
);
928 case 0x8 | 0x2: /* src >= dst */
929 tcg_gen_brcond_i32(TCG_COND_LT
, tmp
, tmp2
, skip
);
931 case 0x8: /* src == dst */
932 tcg_gen_brcond_i32(TCG_COND_NE
, tmp
, tmp2
, skip
);
934 case 0x7: /* src != dst */
935 case 0x6: /* src != dst */
936 tcg_gen_brcond_i32(TCG_COND_EQ
, tmp
, tmp2
, skip
);
938 case 0x4: /* src < dst */
939 tcg_gen_brcond_i32(TCG_COND_GE
, tmp
, tmp2
, skip
);
941 case 0x2: /* src > dst */
942 tcg_gen_brcond_i32(TCG_COND_LE
, tmp
, tmp2
, skip
);
945 tcg_temp_free_i32(tmp
);
946 tcg_temp_free_i32(tmp2
);
949 account_inline_branch(s
);
950 tcg_temp_free_i32(tmp
);
951 tcg_temp_free_i32(tmp2
);
955 case 0x8 | 0x4: /* src <= dst */
956 tcg_gen_brcond_i64(TCG_COND_GT
, cc_src
, cc_dst
, skip
);
958 case 0x8 | 0x2: /* src >= dst */
959 tcg_gen_brcond_i64(TCG_COND_LT
, cc_src
, cc_dst
, skip
);
961 case 0x8: /* src == dst */
962 tcg_gen_brcond_i64(TCG_COND_NE
, cc_src
, cc_dst
, skip
);
964 case 0x7: /* src != dst */
965 case 0x6: /* src != dst */
966 tcg_gen_brcond_i64(TCG_COND_EQ
, cc_src
, cc_dst
, skip
);
968 case 0x4: /* src < dst */
969 tcg_gen_brcond_i64(TCG_COND_GE
, cc_src
, cc_dst
, skip
);
971 case 0x2: /* src > dst */
972 tcg_gen_brcond_i64(TCG_COND_LE
, cc_src
, cc_dst
, skip
);
977 account_inline_branch(s
);
979 case CC_OP_LTUGTU_32
:
980 tmp
= tcg_temp_new_i32();
981 tmp2
= tcg_temp_new_i32();
982 tcg_gen_trunc_i64_i32(tmp
, cc_src
);
983 tcg_gen_trunc_i64_i32(tmp2
, cc_dst
);
985 case 0x8 | 0x4: /* src <= dst */
986 tcg_gen_brcond_i32(TCG_COND_GTU
, tmp
, tmp2
, skip
);
988 case 0x8 | 0x2: /* src >= dst */
989 tcg_gen_brcond_i32(TCG_COND_LTU
, tmp
, tmp2
, skip
);
991 case 0x8: /* src == dst */
992 tcg_gen_brcond_i32(TCG_COND_NE
, tmp
, tmp2
, skip
);
994 case 0x7: /* src != dst */
995 case 0x6: /* src != dst */
996 tcg_gen_brcond_i32(TCG_COND_EQ
, tmp
, tmp2
, skip
);
998 case 0x4: /* src < dst */
999 tcg_gen_brcond_i32(TCG_COND_GEU
, tmp
, tmp2
, skip
);
1001 case 0x2: /* src > dst */
1002 tcg_gen_brcond_i32(TCG_COND_LEU
, tmp
, tmp2
, skip
);
1005 tcg_temp_free_i32(tmp
);
1006 tcg_temp_free_i32(tmp2
);
1009 account_inline_branch(s
);
1010 tcg_temp_free_i32(tmp
);
1011 tcg_temp_free_i32(tmp2
);
1013 case CC_OP_LTUGTU_64
:
1015 case 0x8 | 0x4: /* src <= dst */
1016 tcg_gen_brcond_i64(TCG_COND_GTU
, cc_src
, cc_dst
, skip
);
1018 case 0x8 | 0x2: /* src >= dst */
1019 tcg_gen_brcond_i64(TCG_COND_LTU
, cc_src
, cc_dst
, skip
);
1021 case 0x8: /* src == dst */
1022 tcg_gen_brcond_i64(TCG_COND_NE
, cc_src
, cc_dst
, skip
);
1024 case 0x7: /* src != dst */
1025 case 0x6: /* src != dst */
1026 tcg_gen_brcond_i64(TCG_COND_EQ
, cc_src
, cc_dst
, skip
);
1028 case 0x4: /* src < dst */
1029 tcg_gen_brcond_i64(TCG_COND_GEU
, cc_src
, cc_dst
, skip
);
1031 case 0x2: /* src > dst */
1032 tcg_gen_brcond_i64(TCG_COND_LEU
, cc_src
, cc_dst
, skip
);
1037 account_inline_branch(s
);
1041 /* dst == 0 || dst != 0 */
1043 case 0x8 | 0x4 | 0x2:
1044 case 0x8 | 0x4 | 0x2 | 0x1:
1045 case 0x8 | 0x4 | 0x1:
1050 case 0x8 | 0x2 | 0x1:
1052 tcg_gen_brcondi_i64(TCG_COND_NE
, cc_dst
, 0, skip
);
1057 case 0x4 | 0x2 | 0x1:
1059 tcg_gen_brcondi_i64(TCG_COND_EQ
, cc_dst
, 0, skip
);
1064 account_inline_branch(s
);
1067 tmp
= tcg_temp_new_i32();
1068 tmp2
= tcg_temp_new_i32();
1070 tcg_gen_trunc_i64_i32(tmp
, cc_src
);
1071 tcg_gen_trunc_i64_i32(tmp2
, cc_dst
);
1072 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1074 case 0x8: /* val & mask == 0 */
1075 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, skip
);
1077 case 0x4 | 0x2 | 0x1: /* val & mask != 0 */
1078 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, skip
);
1083 tcg_temp_free_i32(tmp
);
1084 account_inline_branch(s
);
1087 tmp64
= tcg_temp_new_i64();
1089 tcg_gen_and_i64(tmp64
, cc_src
, cc_dst
);
1091 case 0x8: /* val & mask == 0 */
1092 tcg_gen_brcondi_i64(TCG_COND_NE
, tmp64
, 0, skip
);
1094 case 0x4 | 0x2 | 0x1: /* val & mask != 0 */
1095 tcg_gen_brcondi_i64(TCG_COND_EQ
, tmp64
, 0, skip
);
1098 tcg_temp_free_i64(tmp64
);
1101 tcg_temp_free_i64(tmp64
);
1102 account_inline_branch(s
);
1106 case 0x8: /* val == 0 */
1107 tcg_gen_brcondi_i64(TCG_COND_NE
, cc_dst
, 0, skip
);
1109 case 0x4 | 0x2 | 0x1: /* val != 0 */
1110 case 0x4 | 0x2: /* val != 0 */
1111 tcg_gen_brcondi_i64(TCG_COND_EQ
, cc_dst
, 0, skip
);
1116 account_inline_branch(s
);
1119 old_cc_op
= s
->cc_op
;
1120 goto do_dynamic_nocccalc
;
1124 old_cc_op
= s
->cc_op
;
1125 /* calculate cc value */
1128 do_dynamic_nocccalc
:
1129 /* jump based on cc */
1130 account_noninline_branch(s
, old_cc_op
);
1133 case 0x8 | 0x4 | 0x2 | 0x1:
1136 case 0x8 | 0x4 | 0x2: /* cc != 3 */
1137 tcg_gen_brcondi_i32(TCG_COND_EQ
, cc_op
, 3, skip
);
1139 case 0x8 | 0x4 | 0x1: /* cc != 2 */
1140 tcg_gen_brcondi_i32(TCG_COND_EQ
, cc_op
, 2, skip
);
1142 case 0x8 | 0x2 | 0x1: /* cc != 1 */
1143 tcg_gen_brcondi_i32(TCG_COND_EQ
, cc_op
, 1, skip
);
1145 case 0x8 | 0x2: /* cc == 0 ||Â cc == 2 */
1146 tmp
= tcg_temp_new_i32();
1147 tcg_gen_andi_i32(tmp
, cc_op
, 1);
1148 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, skip
);
1149 tcg_temp_free_i32(tmp
);
1151 case 0x8 | 0x4: /* cc < 2 */
1152 tcg_gen_brcondi_i32(TCG_COND_GEU
, cc_op
, 2, skip
);
1154 case 0x8: /* cc == 0 */
1155 tcg_gen_brcondi_i32(TCG_COND_NE
, cc_op
, 0, skip
);
1157 case 0x4 | 0x2 | 0x1: /* cc != 0 */
1158 tcg_gen_brcondi_i32(TCG_COND_EQ
, cc_op
, 0, skip
);
1160 case 0x4 | 0x1: /* cc == 1 ||Â cc == 3 */
1161 tmp
= tcg_temp_new_i32();
1162 tcg_gen_andi_i32(tmp
, cc_op
, 1);
1163 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, skip
);
1164 tcg_temp_free_i32(tmp
);
1166 case 0x4: /* cc == 1 */
1167 tcg_gen_brcondi_i32(TCG_COND_NE
, cc_op
, 1, skip
);
1169 case 0x2 | 0x1: /* cc > 1 */
1170 tcg_gen_brcondi_i32(TCG_COND_LEU
, cc_op
, 1, skip
);
1172 case 0x2: /* cc == 2 */
1173 tcg_gen_brcondi_i32(TCG_COND_NE
, cc_op
, 2, skip
);
1175 case 0x1: /* cc == 3 */
1176 tcg_gen_brcondi_i32(TCG_COND_NE
, cc_op
, 3, skip
);
1178 default: /* cc is masked by something else */
1179 tmp
= tcg_const_i32(3);
1181 tcg_gen_sub_i32(tmp
, tmp
, cc_op
);
1182 tmp2
= tcg_const_i32(1);
1184 tcg_gen_shl_i32(tmp2
, tmp2
, tmp
);
1185 r
= tcg_const_i32(mask
);
1186 /* mask & (1 << (3 - cc)) */
1187 tcg_gen_and_i32(r
, r
, tmp2
);
1188 tcg_temp_free_i32(tmp
);
1189 tcg_temp_free_i32(tmp2
);
1191 tcg_gen_brcondi_i32(TCG_COND_EQ
, r
, 0, skip
);
1192 tcg_temp_free_i32(r
);
1199 static void gen_bcr(DisasContext
*s
, uint32_t mask
, TCGv_i64 target
,
1206 tcg_gen_mov_i64(psw_addr
, target
);
1208 } else if (mask
== 0) {
1209 /* ignore cc and never match */
1210 gen_goto_tb(s
, 0, offset
+ 2);
1212 TCGv_i64 new_addr
= tcg_temp_local_new_i64();
1214 tcg_gen_mov_i64(new_addr
, target
);
1215 skip
= gen_new_label();
1216 gen_jcc(s
, mask
, skip
);
1217 tcg_gen_mov_i64(psw_addr
, new_addr
);
1218 tcg_temp_free_i64(new_addr
);
1220 gen_set_label(skip
);
1221 tcg_temp_free_i64(new_addr
);
1222 gen_goto_tb(s
, 1, offset
+ 2);
1226 static void gen_brc(uint32_t mask
, DisasContext
*s
, int32_t offset
)
1232 gen_goto_tb(s
, 0, s
->pc
+ offset
);
1233 } else if (mask
== 0) {
1234 /* ignore cc and never match */
1235 gen_goto_tb(s
, 0, s
->pc
+ 4);
1237 skip
= gen_new_label();
1238 gen_jcc(s
, mask
, skip
);
1239 gen_goto_tb(s
, 0, s
->pc
+ offset
);
1240 gen_set_label(skip
);
1241 gen_goto_tb(s
, 1, s
->pc
+ 4);
1243 s
->is_jmp
= DISAS_TB_JUMP
;
1246 static void gen_op_mvc(DisasContext
*s
, int l
, TCGv_i64 s1
, TCGv_i64 s2
)
1250 int l_memset
= gen_new_label();
1251 int l_out
= gen_new_label();
1252 TCGv_i64 dest
= tcg_temp_local_new_i64();
1253 TCGv_i64 src
= tcg_temp_local_new_i64();
1256 /* Find out if we should use the inline version of mvc */
1271 /* Fall back to helper */
1272 vl
= tcg_const_i32(l
);
1273 potential_page_fault(s
);
1274 gen_helper_mvc(vl
, s1
, s2
);
1275 tcg_temp_free_i32(vl
);
1279 tcg_gen_mov_i64(dest
, s1
);
1280 tcg_gen_mov_i64(src
, s2
);
1282 if (!(s
->tb
->flags
& FLAG_MASK_64
)) {
1283 /* XXX what if we overflow while moving? */
1284 tcg_gen_andi_i64(dest
, dest
, 0x7fffffffUL
);
1285 tcg_gen_andi_i64(src
, src
, 0x7fffffffUL
);
1288 tmp
= tcg_temp_new_i64();
1289 tcg_gen_addi_i64(tmp
, src
, 1);
1290 tcg_gen_brcond_i64(TCG_COND_EQ
, dest
, tmp
, l_memset
);
1291 tcg_temp_free_i64(tmp
);
1295 tmp
= tcg_temp_new_i64();
1297 tcg_gen_qemu_ld8u(tmp
, src
, get_mem_index(s
));
1298 tcg_gen_qemu_st8(tmp
, dest
, get_mem_index(s
));
1300 tcg_temp_free_i64(tmp
);
1303 tmp
= tcg_temp_new_i64();
1305 tcg_gen_qemu_ld16u(tmp
, src
, get_mem_index(s
));
1306 tcg_gen_qemu_st16(tmp
, dest
, get_mem_index(s
));
1308 tcg_temp_free_i64(tmp
);
1311 tmp
= tcg_temp_new_i64();
1313 tcg_gen_qemu_ld32u(tmp
, src
, get_mem_index(s
));
1314 tcg_gen_qemu_st32(tmp
, dest
, get_mem_index(s
));
1316 tcg_temp_free_i64(tmp
);
1319 tmp
= tcg_temp_new_i64();
1320 tmp2
= tcg_temp_new_i64();
1322 tcg_gen_qemu_ld32u(tmp
, src
, get_mem_index(s
));
1323 tcg_gen_addi_i64(src
, src
, 4);
1324 tcg_gen_qemu_ld8u(tmp2
, src
, get_mem_index(s
));
1325 tcg_gen_qemu_st32(tmp
, dest
, get_mem_index(s
));
1326 tcg_gen_addi_i64(dest
, dest
, 4);
1327 tcg_gen_qemu_st8(tmp2
, dest
, get_mem_index(s
));
1329 tcg_temp_free_i64(tmp
);
1330 tcg_temp_free_i64(tmp2
);
1333 tmp
= tcg_temp_new_i64();
1335 tcg_gen_qemu_ld64(tmp
, src
, get_mem_index(s
));
1336 tcg_gen_qemu_st64(tmp
, dest
, get_mem_index(s
));
1338 tcg_temp_free_i64(tmp
);
1341 /* The inline version can become too big for too uneven numbers, only
1342 use it on known good lengths */
1343 tmp
= tcg_temp_new_i64();
1344 tmp2
= tcg_const_i64(8);
1345 for (i
= 0; (i
+ 7) <= l
; i
+= 8) {
1346 tcg_gen_qemu_ld64(tmp
, src
, get_mem_index(s
));
1347 tcg_gen_qemu_st64(tmp
, dest
, get_mem_index(s
));
1349 tcg_gen_add_i64(src
, src
, tmp2
);
1350 tcg_gen_add_i64(dest
, dest
, tmp2
);
1353 tcg_temp_free_i64(tmp2
);
1354 tmp2
= tcg_const_i64(1);
1356 for (; i
<= l
; i
++) {
1357 tcg_gen_qemu_ld8u(tmp
, src
, get_mem_index(s
));
1358 tcg_gen_qemu_st8(tmp
, dest
, get_mem_index(s
));
1360 tcg_gen_add_i64(src
, src
, tmp2
);
1361 tcg_gen_add_i64(dest
, dest
, tmp2
);
1364 tcg_temp_free_i64(tmp2
);
1365 tcg_temp_free_i64(tmp
);
1371 gen_set_label(l_memset
);
1372 /* memset case (dest == (src + 1)) */
1374 tmp
= tcg_temp_new_i64();
1375 tmp2
= tcg_temp_new_i64();
1376 /* fill tmp with the byte */
1377 tcg_gen_qemu_ld8u(tmp
, src
, get_mem_index(s
));
1378 tcg_gen_shli_i64(tmp2
, tmp
, 8);
1379 tcg_gen_or_i64(tmp
, tmp
, tmp2
);
1380 tcg_gen_shli_i64(tmp2
, tmp
, 16);
1381 tcg_gen_or_i64(tmp
, tmp
, tmp2
);
1382 tcg_gen_shli_i64(tmp2
, tmp
, 32);
1383 tcg_gen_or_i64(tmp
, tmp
, tmp2
);
1384 tcg_temp_free_i64(tmp2
);
1386 tmp2
= tcg_const_i64(8);
1388 for (i
= 0; (i
+ 7) <= l
; i
+= 8) {
1389 tcg_gen_qemu_st64(tmp
, dest
, get_mem_index(s
));
1390 tcg_gen_addi_i64(dest
, dest
, 8);
1393 tcg_temp_free_i64(tmp2
);
1394 tmp2
= tcg_const_i64(1);
1396 for (; i
<= l
; i
++) {
1397 tcg_gen_qemu_st8(tmp
, dest
, get_mem_index(s
));
1398 tcg_gen_addi_i64(dest
, dest
, 1);
1401 tcg_temp_free_i64(tmp2
);
1402 tcg_temp_free_i64(tmp
);
1404 gen_set_label(l_out
);
1406 tcg_temp_free(dest
);
1410 static void gen_op_clc(DisasContext
*s
, int l
, TCGv_i64 s1
, TCGv_i64 s2
)
1416 /* check for simple 32bit or 64bit match */
1419 tmp
= tcg_temp_new_i64();
1420 tmp2
= tcg_temp_new_i64();
1422 tcg_gen_qemu_ld8u(tmp
, s1
, get_mem_index(s
));
1423 tcg_gen_qemu_ld8u(tmp2
, s2
, get_mem_index(s
));
1424 cmp_u64(s
, tmp
, tmp2
);
1426 tcg_temp_free_i64(tmp
);
1427 tcg_temp_free_i64(tmp2
);
1430 tmp
= tcg_temp_new_i64();
1431 tmp2
= tcg_temp_new_i64();
1433 tcg_gen_qemu_ld16u(tmp
, s1
, get_mem_index(s
));
1434 tcg_gen_qemu_ld16u(tmp2
, s2
, get_mem_index(s
));
1435 cmp_u64(s
, tmp
, tmp2
);
1437 tcg_temp_free_i64(tmp
);
1438 tcg_temp_free_i64(tmp2
);
1441 tmp
= tcg_temp_new_i64();
1442 tmp2
= tcg_temp_new_i64();
1444 tcg_gen_qemu_ld32u(tmp
, s1
, get_mem_index(s
));
1445 tcg_gen_qemu_ld32u(tmp2
, s2
, get_mem_index(s
));
1446 cmp_u64(s
, tmp
, tmp2
);
1448 tcg_temp_free_i64(tmp
);
1449 tcg_temp_free_i64(tmp2
);
1452 tmp
= tcg_temp_new_i64();
1453 tmp2
= tcg_temp_new_i64();
1455 tcg_gen_qemu_ld64(tmp
, s1
, get_mem_index(s
));
1456 tcg_gen_qemu_ld64(tmp2
, s2
, get_mem_index(s
));
1457 cmp_u64(s
, tmp
, tmp2
);
1459 tcg_temp_free_i64(tmp
);
1460 tcg_temp_free_i64(tmp2
);
1464 potential_page_fault(s
);
1465 vl
= tcg_const_i32(l
);
1466 gen_helper_clc(cc_op
, vl
, s1
, s2
);
1467 tcg_temp_free_i32(vl
);
1471 static void disas_e3(DisasContext
* s
, int op
, int r1
, int x2
, int b2
, int d2
)
1473 TCGv_i64 addr
, tmp
, tmp2
, tmp3
, tmp4
;
1474 TCGv_i32 tmp32_1
, tmp32_2
, tmp32_3
;
1476 LOG_DISAS("disas_e3: op 0x%x r1 %d x2 %d b2 %d d2 %d\n",
1477 op
, r1
, x2
, b2
, d2
);
1478 addr
= get_address(s
, x2
, b2
, d2
);
1480 case 0x2: /* LTG R1,D2(X2,B2) [RXY] */
1481 case 0x4: /* lg r1,d2(x2,b2) */
1482 tcg_gen_qemu_ld64(regs
[r1
], addr
, get_mem_index(s
));
1484 set_cc_s64(s
, regs
[r1
]);
1487 case 0x12: /* LT R1,D2(X2,B2) [RXY] */
1488 tmp2
= tcg_temp_new_i64();
1489 tmp32_1
= tcg_temp_new_i32();
1490 tcg_gen_qemu_ld32s(tmp2
, addr
, get_mem_index(s
));
1491 tcg_gen_trunc_i64_i32(tmp32_1
, tmp2
);
1492 store_reg32(r1
, tmp32_1
);
1493 set_cc_s32(s
, tmp32_1
);
1494 tcg_temp_free_i64(tmp2
);
1495 tcg_temp_free_i32(tmp32_1
);
1497 case 0xc: /* MSG R1,D2(X2,B2) [RXY] */
1498 case 0x1c: /* MSGF R1,D2(X2,B2) [RXY] */
1499 tmp2
= tcg_temp_new_i64();
1501 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1503 tcg_gen_qemu_ld32s(tmp2
, addr
, get_mem_index(s
));
1505 tcg_gen_mul_i64(regs
[r1
], regs
[r1
], tmp2
);
1506 tcg_temp_free_i64(tmp2
);
1508 case 0xd: /* DSG R1,D2(X2,B2) [RXY] */
1509 case 0x1d: /* DSGF R1,D2(X2,B2) [RXY] */
1510 tmp2
= tcg_temp_new_i64();
1512 tcg_gen_qemu_ld32s(tmp2
, addr
, get_mem_index(s
));
1514 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1516 tmp4
= load_reg(r1
+ 1);
1517 tmp3
= tcg_temp_new_i64();
1518 tcg_gen_div_i64(tmp3
, tmp4
, tmp2
);
1519 store_reg(r1
+ 1, tmp3
);
1520 tcg_gen_rem_i64(tmp3
, tmp4
, tmp2
);
1521 store_reg(r1
, tmp3
);
1522 tcg_temp_free_i64(tmp2
);
1523 tcg_temp_free_i64(tmp3
);
1524 tcg_temp_free_i64(tmp4
);
1526 case 0x8: /* AG R1,D2(X2,B2) [RXY] */
1527 case 0xa: /* ALG R1,D2(X2,B2) [RXY] */
1528 case 0x18: /* AGF R1,D2(X2,B2) [RXY] */
1529 case 0x1a: /* ALGF R1,D2(X2,B2) [RXY] */
1531 tmp2
= tcg_temp_new_i64();
1532 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1533 } else if (op
== 0x18) {
1534 tmp2
= tcg_temp_new_i64();
1535 tcg_gen_qemu_ld32s(tmp2
, addr
, get_mem_index(s
));
1537 tmp2
= tcg_temp_new_i64();
1538 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1540 tmp4
= load_reg(r1
);
1541 tmp3
= tcg_temp_new_i64();
1542 tcg_gen_add_i64(tmp3
, tmp4
, tmp2
);
1543 store_reg(r1
, tmp3
);
1547 set_cc_add64(s
, tmp4
, tmp2
, tmp3
);
1551 set_cc_addu64(s
, tmp4
, tmp2
, tmp3
);
1556 tcg_temp_free_i64(tmp2
);
1557 tcg_temp_free_i64(tmp3
);
1558 tcg_temp_free_i64(tmp4
);
1560 case 0x9: /* SG R1,D2(X2,B2) [RXY] */
1561 case 0xb: /* SLG R1,D2(X2,B2) [RXY] */
1562 case 0x19: /* SGF R1,D2(X2,B2) [RXY] */
1563 case 0x1b: /* SLGF R1,D2(X2,B2) [RXY] */
1564 tmp2
= tcg_temp_new_i64();
1566 tcg_gen_qemu_ld32s(tmp2
, addr
, get_mem_index(s
));
1567 } else if (op
== 0x1b) {
1568 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1570 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1572 tmp4
= load_reg(r1
);
1573 tmp3
= tcg_temp_new_i64();
1574 tcg_gen_sub_i64(tmp3
, tmp4
, tmp2
);
1575 store_reg(r1
, tmp3
);
1579 set_cc_sub64(s
, tmp4
, tmp2
, tmp3
);
1583 set_cc_subu64(s
, tmp4
, tmp2
, tmp3
);
1588 tcg_temp_free_i64(tmp2
);
1589 tcg_temp_free_i64(tmp3
);
1590 tcg_temp_free_i64(tmp4
);
1592 case 0xf: /* LRVG R1,D2(X2,B2) [RXE] */
1593 tmp2
= tcg_temp_new_i64();
1594 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1595 tcg_gen_bswap64_i64(tmp2
, tmp2
);
1596 store_reg(r1
, tmp2
);
1597 tcg_temp_free_i64(tmp2
);
1599 case 0x14: /* LGF R1,D2(X2,B2) [RXY] */
1600 case 0x16: /* LLGF R1,D2(X2,B2) [RXY] */
1601 tmp2
= tcg_temp_new_i64();
1602 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1604 tcg_gen_ext32s_i64(tmp2
, tmp2
);
1606 store_reg(r1
, tmp2
);
1607 tcg_temp_free_i64(tmp2
);
1609 case 0x15: /* LGH R1,D2(X2,B2) [RXY] */
1610 tmp2
= tcg_temp_new_i64();
1611 tcg_gen_qemu_ld16s(tmp2
, addr
, get_mem_index(s
));
1612 store_reg(r1
, tmp2
);
1613 tcg_temp_free_i64(tmp2
);
1615 case 0x17: /* LLGT R1,D2(X2,B2) [RXY] */
1616 tmp2
= tcg_temp_new_i64();
1617 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1618 tcg_gen_andi_i64(tmp2
, tmp2
, 0x7fffffffULL
);
1619 store_reg(r1
, tmp2
);
1620 tcg_temp_free_i64(tmp2
);
1622 case 0x1e: /* LRV R1,D2(X2,B2) [RXY] */
1623 tmp2
= tcg_temp_new_i64();
1624 tmp32_1
= tcg_temp_new_i32();
1625 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1626 tcg_gen_trunc_i64_i32(tmp32_1
, tmp2
);
1627 tcg_temp_free_i64(tmp2
);
1628 tcg_gen_bswap32_i32(tmp32_1
, tmp32_1
);
1629 store_reg32(r1
, tmp32_1
);
1630 tcg_temp_free_i32(tmp32_1
);
1632 case 0x1f: /* LRVH R1,D2(X2,B2) [RXY] */
1633 tmp2
= tcg_temp_new_i64();
1634 tmp32_1
= tcg_temp_new_i32();
1635 tcg_gen_qemu_ld16u(tmp2
, addr
, get_mem_index(s
));
1636 tcg_gen_trunc_i64_i32(tmp32_1
, tmp2
);
1637 tcg_temp_free_i64(tmp2
);
1638 tcg_gen_bswap16_i32(tmp32_1
, tmp32_1
);
1639 store_reg16(r1
, tmp32_1
);
1640 tcg_temp_free_i32(tmp32_1
);
1642 case 0x20: /* CG R1,D2(X2,B2) [RXY] */
1643 case 0x21: /* CLG R1,D2(X2,B2) */
1644 case 0x30: /* CGF R1,D2(X2,B2) [RXY] */
1645 case 0x31: /* CLGF R1,D2(X2,B2) [RXY] */
1646 tmp2
= tcg_temp_new_i64();
1650 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1653 tcg_gen_qemu_ld32s(tmp2
, addr
, get_mem_index(s
));
1656 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1664 cmp_s64(s
, regs
[r1
], tmp2
);
1668 cmp_u64(s
, regs
[r1
], tmp2
);
1673 tcg_temp_free_i64(tmp2
);
1675 case 0x24: /* stg r1, d2(x2,b2) */
1676 tcg_gen_qemu_st64(regs
[r1
], addr
, get_mem_index(s
));
1678 case 0x3e: /* STRV R1,D2(X2,B2) [RXY] */
1679 tmp32_1
= load_reg32(r1
);
1680 tmp2
= tcg_temp_new_i64();
1681 tcg_gen_bswap32_i32(tmp32_1
, tmp32_1
);
1682 tcg_gen_extu_i32_i64(tmp2
, tmp32_1
);
1683 tcg_temp_free_i32(tmp32_1
);
1684 tcg_gen_qemu_st32(tmp2
, addr
, get_mem_index(s
));
1685 tcg_temp_free_i64(tmp2
);
1687 case 0x50: /* STY R1,D2(X2,B2) [RXY] */
1688 tmp32_1
= load_reg32(r1
);
1689 tmp2
= tcg_temp_new_i64();
1690 tcg_gen_extu_i32_i64(tmp2
, tmp32_1
);
1691 tcg_temp_free_i32(tmp32_1
);
1692 tcg_gen_qemu_st32(tmp2
, addr
, get_mem_index(s
));
1693 tcg_temp_free_i64(tmp2
);
1695 case 0x57: /* XY R1,D2(X2,B2) [RXY] */
1696 tmp32_1
= load_reg32(r1
);
1697 tmp32_2
= tcg_temp_new_i32();
1698 tmp2
= tcg_temp_new_i64();
1699 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1700 tcg_gen_trunc_i64_i32(tmp32_2
, tmp2
);
1701 tcg_temp_free_i64(tmp2
);
1702 tcg_gen_xor_i32(tmp32_2
, tmp32_1
, tmp32_2
);
1703 store_reg32(r1
, tmp32_2
);
1704 set_cc_nz_u32(s
, tmp32_2
);
1705 tcg_temp_free_i32(tmp32_1
);
1706 tcg_temp_free_i32(tmp32_2
);
1708 case 0x58: /* LY R1,D2(X2,B2) [RXY] */
1709 tmp3
= tcg_temp_new_i64();
1710 tcg_gen_qemu_ld32u(tmp3
, addr
, get_mem_index(s
));
1711 store_reg32_i64(r1
, tmp3
);
1712 tcg_temp_free_i64(tmp3
);
1714 case 0x5a: /* AY R1,D2(X2,B2) [RXY] */
1715 case 0x5b: /* SY R1,D2(X2,B2) [RXY] */
1716 tmp32_1
= load_reg32(r1
);
1717 tmp32_2
= tcg_temp_new_i32();
1718 tmp32_3
= tcg_temp_new_i32();
1719 tmp2
= tcg_temp_new_i64();
1720 tcg_gen_qemu_ld32s(tmp2
, addr
, get_mem_index(s
));
1721 tcg_gen_trunc_i64_i32(tmp32_2
, tmp2
);
1722 tcg_temp_free_i64(tmp2
);
1725 tcg_gen_add_i32(tmp32_3
, tmp32_1
, tmp32_2
);
1728 tcg_gen_sub_i32(tmp32_3
, tmp32_1
, tmp32_2
);
1733 store_reg32(r1
, tmp32_3
);
1736 set_cc_add32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
1739 set_cc_sub32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
1744 tcg_temp_free_i32(tmp32_1
);
1745 tcg_temp_free_i32(tmp32_2
);
1746 tcg_temp_free_i32(tmp32_3
);
1748 case 0x71: /* LAY R1,D2(X2,B2) [RXY] */
1749 store_reg(r1
, addr
);
1751 case 0x72: /* STCY R1,D2(X2,B2) [RXY] */
1752 tmp32_1
= load_reg32(r1
);
1753 tmp2
= tcg_temp_new_i64();
1754 tcg_gen_ext_i32_i64(tmp2
, tmp32_1
);
1755 tcg_gen_qemu_st8(tmp2
, addr
, get_mem_index(s
));
1756 tcg_temp_free_i32(tmp32_1
);
1757 tcg_temp_free_i64(tmp2
);
1759 case 0x73: /* ICY R1,D2(X2,B2) [RXY] */
1760 tmp3
= tcg_temp_new_i64();
1761 tcg_gen_qemu_ld8u(tmp3
, addr
, get_mem_index(s
));
1762 store_reg8(r1
, tmp3
);
1763 tcg_temp_free_i64(tmp3
);
1765 case 0x76: /* LB R1,D2(X2,B2) [RXY] */
1766 case 0x77: /* LGB R1,D2(X2,B2) [RXY] */
1767 tmp2
= tcg_temp_new_i64();
1768 tcg_gen_qemu_ld8s(tmp2
, addr
, get_mem_index(s
));
1771 tcg_gen_ext8s_i64(tmp2
, tmp2
);
1772 store_reg32_i64(r1
, tmp2
);
1775 tcg_gen_ext8s_i64(tmp2
, tmp2
);
1776 store_reg(r1
, tmp2
);
1781 tcg_temp_free_i64(tmp2
);
1783 case 0x78: /* LHY R1,D2(X2,B2) [RXY] */
1784 tmp2
= tcg_temp_new_i64();
1785 tcg_gen_qemu_ld16s(tmp2
, addr
, get_mem_index(s
));
1786 store_reg32_i64(r1
, tmp2
);
1787 tcg_temp_free_i64(tmp2
);
1789 case 0x80: /* NG R1,D2(X2,B2) [RXY] */
1790 case 0x81: /* OG R1,D2(X2,B2) [RXY] */
1791 case 0x82: /* XG R1,D2(X2,B2) [RXY] */
1792 tmp3
= tcg_temp_new_i64();
1793 tcg_gen_qemu_ld64(tmp3
, addr
, get_mem_index(s
));
1796 tcg_gen_and_i64(regs
[r1
], regs
[r1
], tmp3
);
1799 tcg_gen_or_i64(regs
[r1
], regs
[r1
], tmp3
);
1802 tcg_gen_xor_i64(regs
[r1
], regs
[r1
], tmp3
);
1807 set_cc_nz_u64(s
, regs
[r1
]);
1808 tcg_temp_free_i64(tmp3
);
1810 case 0x86: /* MLG R1,D2(X2,B2) [RXY] */
1811 tmp2
= tcg_temp_new_i64();
1812 tmp32_1
= tcg_const_i32(r1
);
1813 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1814 gen_helper_mlg(tmp32_1
, tmp2
);
1815 tcg_temp_free_i64(tmp2
);
1816 tcg_temp_free_i32(tmp32_1
);
1818 case 0x87: /* DLG R1,D2(X2,B2) [RXY] */
1819 tmp2
= tcg_temp_new_i64();
1820 tmp32_1
= tcg_const_i32(r1
);
1821 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1822 gen_helper_dlg(tmp32_1
, tmp2
);
1823 tcg_temp_free_i64(tmp2
);
1824 tcg_temp_free_i32(tmp32_1
);
1826 case 0x88: /* ALCG R1,D2(X2,B2) [RXY] */
1827 tmp2
= tcg_temp_new_i64();
1828 tmp3
= tcg_temp_new_i64();
1829 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1830 /* XXX possible optimization point */
1832 tcg_gen_extu_i32_i64(tmp3
, cc_op
);
1833 tcg_gen_shri_i64(tmp3
, tmp3
, 1);
1834 tcg_gen_andi_i64(tmp3
, tmp3
, 1);
1835 tcg_gen_add_i64(tmp3
, tmp2
, tmp3
);
1836 tcg_gen_add_i64(tmp3
, regs
[r1
], tmp3
);
1837 store_reg(r1
, tmp3
);
1838 set_cc_addu64(s
, regs
[r1
], tmp2
, tmp3
);
1839 tcg_temp_free_i64(tmp2
);
1840 tcg_temp_free_i64(tmp3
);
1842 case 0x89: /* SLBG R1,D2(X2,B2) [RXY] */
1843 tmp2
= tcg_temp_new_i64();
1844 tmp32_1
= tcg_const_i32(r1
);
1845 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1846 /* XXX possible optimization point */
1848 gen_helper_slbg(cc_op
, cc_op
, tmp32_1
, regs
[r1
], tmp2
);
1850 tcg_temp_free_i64(tmp2
);
1851 tcg_temp_free_i32(tmp32_1
);
1853 case 0x90: /* LLGC R1,D2(X2,B2) [RXY] */
1854 tcg_gen_qemu_ld8u(regs
[r1
], addr
, get_mem_index(s
));
1856 case 0x91: /* LLGH R1,D2(X2,B2) [RXY] */
1857 tcg_gen_qemu_ld16u(regs
[r1
], addr
, get_mem_index(s
));
1859 case 0x94: /* LLC R1,D2(X2,B2) [RXY] */
1860 tmp2
= tcg_temp_new_i64();
1861 tcg_gen_qemu_ld8u(tmp2
, addr
, get_mem_index(s
));
1862 store_reg32_i64(r1
, tmp2
);
1863 tcg_temp_free_i64(tmp2
);
1865 case 0x95: /* LLH R1,D2(X2,B2) [RXY] */
1866 tmp2
= tcg_temp_new_i64();
1867 tcg_gen_qemu_ld16u(tmp2
, addr
, get_mem_index(s
));
1868 store_reg32_i64(r1
, tmp2
);
1869 tcg_temp_free_i64(tmp2
);
1871 case 0x96: /* ML R1,D2(X2,B2) [RXY] */
1872 tmp2
= tcg_temp_new_i64();
1873 tmp3
= load_reg((r1
+ 1) & 15);
1874 tcg_gen_ext32u_i64(tmp3
, tmp3
);
1875 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1876 tcg_gen_mul_i64(tmp2
, tmp2
, tmp3
);
1877 store_reg32_i64((r1
+ 1) & 15, tmp2
);
1878 tcg_gen_shri_i64(tmp2
, tmp2
, 32);
1879 store_reg32_i64(r1
, tmp2
);
1880 tcg_temp_free_i64(tmp2
);
1881 tcg_temp_free_i64(tmp3
);
1883 case 0x97: /* DL R1,D2(X2,B2) [RXY] */
1884 /* reg(r1) = reg(r1, r1+1) % ld32(addr) */
1885 /* reg(r1+1) = reg(r1, r1+1) / ld32(addr) */
1887 tmp2
= tcg_temp_new_i64();
1888 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1889 tmp3
= load_reg((r1
+ 1) & 15);
1890 tcg_gen_ext32u_i64(tmp2
, tmp2
);
1891 tcg_gen_ext32u_i64(tmp3
, tmp3
);
1892 tcg_gen_shli_i64(tmp
, tmp
, 32);
1893 tcg_gen_or_i64(tmp
, tmp
, tmp3
);
1895 tcg_gen_rem_i64(tmp3
, tmp
, tmp2
);
1896 tcg_gen_div_i64(tmp
, tmp
, tmp2
);
1897 store_reg32_i64((r1
+ 1) & 15, tmp
);
1898 store_reg32_i64(r1
, tmp3
);
1899 tcg_temp_free_i64(tmp
);
1900 tcg_temp_free_i64(tmp2
);
1901 tcg_temp_free_i64(tmp3
);
1903 case 0x98: /* ALC R1,D2(X2,B2) [RXY] */
1904 tmp2
= tcg_temp_new_i64();
1905 tmp32_1
= load_reg32(r1
);
1906 tmp32_2
= tcg_temp_new_i32();
1907 tmp32_3
= tcg_temp_new_i32();
1908 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1909 tcg_gen_trunc_i64_i32(tmp32_2
, tmp2
);
1910 /* XXX possible optimization point */
1912 gen_helper_addc_u32(tmp32_3
, cc_op
, tmp32_1
, tmp32_2
);
1913 set_cc_addu32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
1914 store_reg32(r1
, tmp32_3
);
1915 tcg_temp_free_i64(tmp2
);
1916 tcg_temp_free_i32(tmp32_1
);
1917 tcg_temp_free_i32(tmp32_2
);
1918 tcg_temp_free_i32(tmp32_3
);
1920 case 0x99: /* SLB R1,D2(X2,B2) [RXY] */
1921 tmp2
= tcg_temp_new_i64();
1922 tmp32_1
= tcg_const_i32(r1
);
1923 tmp32_2
= tcg_temp_new_i32();
1924 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1925 tcg_gen_trunc_i64_i32(tmp32_2
, tmp2
);
1926 /* XXX possible optimization point */
1928 gen_helper_slb(cc_op
, cc_op
, tmp32_1
, tmp32_2
);
1930 tcg_temp_free_i64(tmp2
);
1931 tcg_temp_free_i32(tmp32_1
);
1932 tcg_temp_free_i32(tmp32_2
);
1935 LOG_DISAS("illegal e3 operation 0x%x\n", op
);
1936 gen_illegal_opcode(s
, 3);
1939 tcg_temp_free_i64(addr
);
1942 #ifndef CONFIG_USER_ONLY
1943 static void disas_e5(DisasContext
* s
, uint64_t insn
)
1946 int op
= (insn
>> 32) & 0xff;
1948 tmp
= get_address(s
, 0, (insn
>> 28) & 0xf, (insn
>> 16) & 0xfff);
1949 tmp2
= get_address(s
, 0, (insn
>> 12) & 0xf, insn
& 0xfff);
1951 LOG_DISAS("disas_e5: insn %" PRIx64
"\n", insn
);
1953 case 0x01: /* TPROT D1(B1),D2(B2) [SSE] */
1954 /* Test Protection */
1955 potential_page_fault(s
);
1956 gen_helper_tprot(cc_op
, tmp
, tmp2
);
1960 LOG_DISAS("illegal e5 operation 0x%x\n", op
);
1961 gen_illegal_opcode(s
, 3);
1965 tcg_temp_free_i64(tmp
);
1966 tcg_temp_free_i64(tmp2
);
1970 static void disas_eb(DisasContext
*s
, int op
, int r1
, int r3
, int b2
, int d2
)
1972 TCGv_i64 tmp
, tmp2
, tmp3
, tmp4
;
1973 TCGv_i32 tmp32_1
, tmp32_2
;
1977 LOG_DISAS("disas_eb: op 0x%x r1 %d r3 %d b2 %d d2 0x%x\n",
1978 op
, r1
, r3
, b2
, d2
);
1980 case 0xc: /* SRLG R1,R3,D2(B2) [RSY] */
1981 case 0xd: /* SLLG R1,R3,D2(B2) [RSY] */
1982 case 0xa: /* SRAG R1,R3,D2(B2) [RSY] */
1983 case 0xb: /* SLAG R1,R3,D2(B2) [RSY] */
1984 case 0x1c: /* RLLG R1,R3,D2(B2) [RSY] */
1986 tmp
= get_address(s
, 0, b2
, d2
);
1987 tcg_gen_andi_i64(tmp
, tmp
, 0x3f);
1989 tmp
= tcg_const_i64(d2
& 0x3f);
1993 tcg_gen_shr_i64(regs
[r1
], regs
[r3
], tmp
);
1996 tcg_gen_shl_i64(regs
[r1
], regs
[r3
], tmp
);
1999 tcg_gen_sar_i64(regs
[r1
], regs
[r3
], tmp
);
2002 tmp2
= tcg_temp_new_i64();
2003 tmp3
= tcg_temp_new_i64();
2004 gen_op_update2_cc_i64(s
, CC_OP_SLAG
, regs
[r3
], tmp
);
2005 tcg_gen_shl_i64(tmp2
, regs
[r3
], tmp
);
2006 /* override sign bit with source sign */
2007 tcg_gen_andi_i64(tmp2
, tmp2
, ~0x8000000000000000ULL
);
2008 tcg_gen_andi_i64(tmp3
, regs
[r3
], 0x8000000000000000ULL
);
2009 tcg_gen_or_i64(regs
[r1
], tmp2
, tmp3
);
2010 tcg_temp_free_i64(tmp2
);
2011 tcg_temp_free_i64(tmp3
);
2014 tcg_gen_rotl_i64(regs
[r1
], regs
[r3
], tmp
);
2021 set_cc_s64(s
, regs
[r1
]);
2023 tcg_temp_free_i64(tmp
);
2025 case 0x1d: /* RLL R1,R3,D2(B2) [RSY] */
2027 tmp
= get_address(s
, 0, b2
, d2
);
2028 tcg_gen_andi_i64(tmp
, tmp
, 0x3f);
2030 tmp
= tcg_const_i64(d2
& 0x3f);
2032 tmp32_1
= tcg_temp_new_i32();
2033 tmp32_2
= load_reg32(r3
);
2034 tcg_gen_trunc_i64_i32(tmp32_1
, tmp
);
2037 tcg_gen_rotl_i32(tmp32_1
, tmp32_2
, tmp32_1
);
2043 store_reg32(r1
, tmp32_1
);
2044 tcg_temp_free_i64(tmp
);
2045 tcg_temp_free_i32(tmp32_1
);
2046 tcg_temp_free_i32(tmp32_2
);
2048 case 0x4: /* LMG R1,R3,D2(B2) [RSE] */
2049 case 0x24: /* STMG R1,R3,D2(B2) [RSE] */
2052 case 0x26: /* STMH R1,R3,D2(B2) [RSE] */
2053 case 0x96: /* LMH R1,R3,D2(B2) [RSE] */
2056 /* Apparently, unrolling lmg/stmg of any size gains performance -
2057 even for very long ones... */
2058 tmp
= get_address(s
, 0, b2
, d2
);
2059 tmp3
= tcg_const_i64(stm_len
);
2060 tmp4
= tcg_const_i64(op
== 0x26 ? 32 : 4);
2061 for (i
= r1
;; i
= (i
+ 1) % 16) {
2064 tcg_gen_qemu_ld64(regs
[i
], tmp
, get_mem_index(s
));
2067 tmp2
= tcg_temp_new_i64();
2068 #if HOST_LONG_BITS == 32
2069 tcg_gen_qemu_ld32u(tmp2
, tmp
, get_mem_index(s
));
2070 tcg_gen_trunc_i64_i32(TCGV_HIGH(regs
[i
]), tmp2
);
2072 tcg_gen_qemu_ld32u(tmp2
, tmp
, get_mem_index(s
));
2073 tcg_gen_shl_i64(tmp2
, tmp2
, tmp4
);
2074 tcg_gen_ext32u_i64(regs
[i
], regs
[i
]);
2075 tcg_gen_or_i64(regs
[i
], regs
[i
], tmp2
);
2077 tcg_temp_free_i64(tmp2
);
2080 tcg_gen_qemu_st64(regs
[i
], tmp
, get_mem_index(s
));
2083 tmp2
= tcg_temp_new_i64();
2084 tcg_gen_shr_i64(tmp2
, regs
[i
], tmp4
);
2085 tcg_gen_qemu_st32(tmp2
, tmp
, get_mem_index(s
));
2086 tcg_temp_free_i64(tmp2
);
2094 tcg_gen_add_i64(tmp
, tmp
, tmp3
);
2096 tcg_temp_free_i64(tmp
);
2097 tcg_temp_free_i64(tmp3
);
2098 tcg_temp_free_i64(tmp4
);
2100 case 0x2c: /* STCMH R1,M3,D2(B2) [RSY] */
2101 tmp
= get_address(s
, 0, b2
, d2
);
2102 tmp32_1
= tcg_const_i32(r1
);
2103 tmp32_2
= tcg_const_i32(r3
);
2104 potential_page_fault(s
);
2105 gen_helper_stcmh(tmp32_1
, tmp
, tmp32_2
);
2106 tcg_temp_free_i64(tmp
);
2107 tcg_temp_free_i32(tmp32_1
);
2108 tcg_temp_free_i32(tmp32_2
);
2110 #ifndef CONFIG_USER_ONLY
2111 case 0x2f: /* LCTLG R1,R3,D2(B2) [RSE] */
2113 check_privileged(s
, ilc
);
2114 tmp
= get_address(s
, 0, b2
, d2
);
2115 tmp32_1
= tcg_const_i32(r1
);
2116 tmp32_2
= tcg_const_i32(r3
);
2117 potential_page_fault(s
);
2118 gen_helper_lctlg(tmp32_1
, tmp
, tmp32_2
);
2119 tcg_temp_free_i64(tmp
);
2120 tcg_temp_free_i32(tmp32_1
);
2121 tcg_temp_free_i32(tmp32_2
);
2123 case 0x25: /* STCTG R1,R3,D2(B2) [RSE] */
2125 check_privileged(s
, ilc
);
2126 tmp
= get_address(s
, 0, b2
, d2
);
2127 tmp32_1
= tcg_const_i32(r1
);
2128 tmp32_2
= tcg_const_i32(r3
);
2129 potential_page_fault(s
);
2130 gen_helper_stctg(tmp32_1
, tmp
, tmp32_2
);
2131 tcg_temp_free_i64(tmp
);
2132 tcg_temp_free_i32(tmp32_1
);
2133 tcg_temp_free_i32(tmp32_2
);
2136 case 0x30: /* CSG R1,R3,D2(B2) [RSY] */
2137 tmp
= get_address(s
, 0, b2
, d2
);
2138 tmp32_1
= tcg_const_i32(r1
);
2139 tmp32_2
= tcg_const_i32(r3
);
2140 potential_page_fault(s
);
2141 /* XXX rewrite in tcg */
2142 gen_helper_csg(cc_op
, tmp32_1
, tmp
, tmp32_2
);
2144 tcg_temp_free_i64(tmp
);
2145 tcg_temp_free_i32(tmp32_1
);
2146 tcg_temp_free_i32(tmp32_2
);
2148 case 0x3e: /* CDSG R1,R3,D2(B2) [RSY] */
2149 tmp
= get_address(s
, 0, b2
, d2
);
2150 tmp32_1
= tcg_const_i32(r1
);
2151 tmp32_2
= tcg_const_i32(r3
);
2152 potential_page_fault(s
);
2153 /* XXX rewrite in tcg */
2154 gen_helper_cdsg(cc_op
, tmp32_1
, tmp
, tmp32_2
);
2156 tcg_temp_free_i64(tmp
);
2157 tcg_temp_free_i32(tmp32_1
);
2158 tcg_temp_free_i32(tmp32_2
);
2160 case 0x51: /* TMY D1(B1),I2 [SIY] */
2161 tmp
= get_address(s
, 0, b2
, d2
); /* SIY -> this is the destination */
2162 tmp2
= tcg_const_i64((r1
<< 4) | r3
);
2163 tcg_gen_qemu_ld8u(tmp
, tmp
, get_mem_index(s
));
2164 /* yes, this is a 32 bit operation with 64 bit tcg registers, because
2165 that incurs less conversions */
2166 cmp_64(s
, tmp
, tmp2
, CC_OP_TM_32
);
2167 tcg_temp_free_i64(tmp
);
2168 tcg_temp_free_i64(tmp2
);
2170 case 0x52: /* MVIY D1(B1),I2 [SIY] */
2171 tmp
= get_address(s
, 0, b2
, d2
); /* SIY -> this is the destination */
2172 tmp2
= tcg_const_i64((r1
<< 4) | r3
);
2173 tcg_gen_qemu_st8(tmp2
, tmp
, get_mem_index(s
));
2174 tcg_temp_free_i64(tmp
);
2175 tcg_temp_free_i64(tmp2
);
2177 case 0x55: /* CLIY D1(B1),I2 [SIY] */
2178 tmp3
= get_address(s
, 0, b2
, d2
); /* SIY -> this is the 1st operand */
2179 tmp
= tcg_temp_new_i64();
2180 tmp32_1
= tcg_temp_new_i32();
2181 tcg_gen_qemu_ld8u(tmp
, tmp3
, get_mem_index(s
));
2182 tcg_gen_trunc_i64_i32(tmp32_1
, tmp
);
2183 cmp_u32c(s
, tmp32_1
, (r1
<< 4) | r3
);
2184 tcg_temp_free_i64(tmp
);
2185 tcg_temp_free_i64(tmp3
);
2186 tcg_temp_free_i32(tmp32_1
);
2188 case 0x80: /* ICMH R1,M3,D2(B2) [RSY] */
2189 tmp
= get_address(s
, 0, b2
, d2
);
2190 tmp32_1
= tcg_const_i32(r1
);
2191 tmp32_2
= tcg_const_i32(r3
);
2192 potential_page_fault(s
);
2193 /* XXX split CC calculation out */
2194 gen_helper_icmh(cc_op
, tmp32_1
, tmp
, tmp32_2
);
2196 tcg_temp_free_i64(tmp
);
2197 tcg_temp_free_i32(tmp32_1
);
2198 tcg_temp_free_i32(tmp32_2
);
2201 LOG_DISAS("illegal eb operation 0x%x\n", op
);
2202 gen_illegal_opcode(s
, ilc
);
2207 static void disas_ed(DisasContext
*s
, int op
, int r1
, int x2
, int b2
, int d2
,
2210 TCGv_i32 tmp_r1
, tmp32
;
2212 addr
= get_address(s
, x2
, b2
, d2
);
2213 tmp_r1
= tcg_const_i32(r1
);
2215 case 0x5: /* LXDB R1,D2(X2,B2) [RXE] */
2216 potential_page_fault(s
);
2217 gen_helper_lxdb(tmp_r1
, addr
);
2219 case 0x9: /* CEB R1,D2(X2,B2) [RXE] */
2220 tmp
= tcg_temp_new_i64();
2221 tmp32
= load_freg32(r1
);
2222 tcg_gen_qemu_ld32u(tmp
, addr
, get_mem_index(s
));
2223 set_cc_cmp_f32_i64(s
, tmp32
, tmp
);
2224 tcg_temp_free_i64(tmp
);
2225 tcg_temp_free_i32(tmp32
);
2227 case 0xa: /* AEB R1,D2(X2,B2) [RXE] */
2228 tmp
= tcg_temp_new_i64();
2229 tmp32
= tcg_temp_new_i32();
2230 tcg_gen_qemu_ld32u(tmp
, addr
, get_mem_index(s
));
2231 tcg_gen_trunc_i64_i32(tmp32
, tmp
);
2232 gen_helper_aeb(tmp_r1
, tmp32
);
2233 tcg_temp_free_i64(tmp
);
2234 tcg_temp_free_i32(tmp32
);
2236 tmp32
= load_freg32(r1
);
2237 set_cc_nz_f32(s
, tmp32
);
2238 tcg_temp_free_i32(tmp32
);
2240 case 0xb: /* SEB R1,D2(X2,B2) [RXE] */
2241 tmp
= tcg_temp_new_i64();
2242 tmp32
= tcg_temp_new_i32();
2243 tcg_gen_qemu_ld32u(tmp
, addr
, get_mem_index(s
));
2244 tcg_gen_trunc_i64_i32(tmp32
, tmp
);
2245 gen_helper_seb(tmp_r1
, tmp32
);
2246 tcg_temp_free_i64(tmp
);
2247 tcg_temp_free_i32(tmp32
);
2249 tmp32
= load_freg32(r1
);
2250 set_cc_nz_f32(s
, tmp32
);
2251 tcg_temp_free_i32(tmp32
);
2253 case 0xd: /* DEB R1,D2(X2,B2) [RXE] */
2254 tmp
= tcg_temp_new_i64();
2255 tmp32
= tcg_temp_new_i32();
2256 tcg_gen_qemu_ld32u(tmp
, addr
, get_mem_index(s
));
2257 tcg_gen_trunc_i64_i32(tmp32
, tmp
);
2258 gen_helper_deb(tmp_r1
, tmp32
);
2259 tcg_temp_free_i64(tmp
);
2260 tcg_temp_free_i32(tmp32
);
2262 case 0x10: /* TCEB R1,D2(X2,B2) [RXE] */
2263 potential_page_fault(s
);
2264 gen_helper_tceb(cc_op
, tmp_r1
, addr
);
2267 case 0x11: /* TCDB R1,D2(X2,B2) [RXE] */
2268 potential_page_fault(s
);
2269 gen_helper_tcdb(cc_op
, tmp_r1
, addr
);
2272 case 0x12: /* TCXB R1,D2(X2,B2) [RXE] */
2273 potential_page_fault(s
);
2274 gen_helper_tcxb(cc_op
, tmp_r1
, addr
);
2277 case 0x17: /* MEEB R1,D2(X2,B2) [RXE] */
2278 tmp
= tcg_temp_new_i64();
2279 tmp32
= tcg_temp_new_i32();
2280 tcg_gen_qemu_ld32u(tmp
, addr
, get_mem_index(s
));
2281 tcg_gen_trunc_i64_i32(tmp32
, tmp
);
2282 gen_helper_meeb(tmp_r1
, tmp32
);
2283 tcg_temp_free_i64(tmp
);
2284 tcg_temp_free_i32(tmp32
);
2286 case 0x19: /* CDB R1,D2(X2,B2) [RXE] */
2287 potential_page_fault(s
);
2288 gen_helper_cdb(cc_op
, tmp_r1
, addr
);
2291 case 0x1a: /* ADB R1,D2(X2,B2) [RXE] */
2292 potential_page_fault(s
);
2293 gen_helper_adb(cc_op
, tmp_r1
, addr
);
2296 case 0x1b: /* SDB R1,D2(X2,B2) [RXE] */
2297 potential_page_fault(s
);
2298 gen_helper_sdb(cc_op
, tmp_r1
, addr
);
2301 case 0x1c: /* MDB R1,D2(X2,B2) [RXE] */
2302 potential_page_fault(s
);
2303 gen_helper_mdb(tmp_r1
, addr
);
2305 case 0x1d: /* DDB R1,D2(X2,B2) [RXE] */
2306 potential_page_fault(s
);
2307 gen_helper_ddb(tmp_r1
, addr
);
2309 case 0x1e: /* MADB R1,R3,D2(X2,B2) [RXF] */
2310 /* for RXF insns, r1 is R3 and r1b is R1 */
2311 tmp32
= tcg_const_i32(r1b
);
2312 potential_page_fault(s
);
2313 gen_helper_madb(tmp32
, addr
, tmp_r1
);
2314 tcg_temp_free_i32(tmp32
);
2317 LOG_DISAS("illegal ed operation 0x%x\n", op
);
2318 gen_illegal_opcode(s
, 3);
2321 tcg_temp_free_i32(tmp_r1
);
2322 tcg_temp_free_i64(addr
);
2325 static void disas_a5(DisasContext
*s
, int op
, int r1
, int i2
)
2329 LOG_DISAS("disas_a5: op 0x%x r1 %d i2 0x%x\n", op
, r1
, i2
);
2331 case 0x0: /* IIHH R1,I2 [RI] */
2332 tmp
= tcg_const_i64(i2
);
2333 tcg_gen_deposit_i64(regs
[r1
], regs
[r1
], tmp
, 48, 16);
2335 case 0x1: /* IIHL R1,I2 [RI] */
2336 tmp
= tcg_const_i64(i2
);
2337 tcg_gen_deposit_i64(regs
[r1
], regs
[r1
], tmp
, 32, 16);
2339 case 0x2: /* IILH R1,I2 [RI] */
2340 tmp
= tcg_const_i64(i2
);
2341 tcg_gen_deposit_i64(regs
[r1
], regs
[r1
], tmp
, 16, 16);
2343 case 0x3: /* IILL R1,I2 [RI] */
2344 tmp
= tcg_const_i64(i2
);
2345 tcg_gen_deposit_i64(regs
[r1
], regs
[r1
], tmp
, 0, 16);
2347 case 0x4: /* NIHH R1,I2 [RI] */
2348 case 0x8: /* OIHH R1,I2 [RI] */
2350 tmp32
= tcg_temp_new_i32();
2353 tmp2
= tcg_const_i64((((uint64_t)i2
) << 48)
2354 | 0x0000ffffffffffffULL
);
2355 tcg_gen_and_i64(tmp
, tmp
, tmp2
);
2358 tmp2
= tcg_const_i64(((uint64_t)i2
) << 48);
2359 tcg_gen_or_i64(tmp
, tmp
, tmp2
);
2365 tcg_gen_shri_i64(tmp2
, tmp
, 48);
2366 tcg_gen_trunc_i64_i32(tmp32
, tmp2
);
2367 set_cc_nz_u32(s
, tmp32
);
2368 tcg_temp_free_i64(tmp2
);
2369 tcg_temp_free_i32(tmp32
);
2371 case 0x5: /* NIHL R1,I2 [RI] */
2372 case 0x9: /* OIHL R1,I2 [RI] */
2374 tmp32
= tcg_temp_new_i32();
2377 tmp2
= tcg_const_i64((((uint64_t)i2
) << 32)
2378 | 0xffff0000ffffffffULL
);
2379 tcg_gen_and_i64(tmp
, tmp
, tmp2
);
2382 tmp2
= tcg_const_i64(((uint64_t)i2
) << 32);
2383 tcg_gen_or_i64(tmp
, tmp
, tmp2
);
2389 tcg_gen_shri_i64(tmp2
, tmp
, 32);
2390 tcg_gen_trunc_i64_i32(tmp32
, tmp2
);
2391 tcg_gen_andi_i32(tmp32
, tmp32
, 0xffff);
2392 set_cc_nz_u32(s
, tmp32
);
2393 tcg_temp_free_i64(tmp2
);
2394 tcg_temp_free_i32(tmp32
);
2396 case 0x6: /* NILH R1,I2 [RI] */
2397 case 0xa: /* OILH R1,I2 [RI] */
2399 tmp32
= tcg_temp_new_i32();
2402 tmp2
= tcg_const_i64((((uint64_t)i2
) << 16)
2403 | 0xffffffff0000ffffULL
);
2404 tcg_gen_and_i64(tmp
, tmp
, tmp2
);
2407 tmp2
= tcg_const_i64(((uint64_t)i2
) << 16);
2408 tcg_gen_or_i64(tmp
, tmp
, tmp2
);
2414 tcg_gen_shri_i64(tmp
, tmp
, 16);
2415 tcg_gen_trunc_i64_i32(tmp32
, tmp
);
2416 tcg_gen_andi_i32(tmp32
, tmp32
, 0xffff);
2417 set_cc_nz_u32(s
, tmp32
);
2418 tcg_temp_free_i64(tmp2
);
2419 tcg_temp_free_i32(tmp32
);
2421 case 0x7: /* NILL R1,I2 [RI] */
2422 case 0xb: /* OILL R1,I2 [RI] */
2424 tmp32
= tcg_temp_new_i32();
2427 tmp2
= tcg_const_i64(i2
| 0xffffffffffff0000ULL
);
2428 tcg_gen_and_i64(tmp
, tmp
, tmp2
);
2431 tmp2
= tcg_const_i64(i2
);
2432 tcg_gen_or_i64(tmp
, tmp
, tmp2
);
2438 tcg_gen_trunc_i64_i32(tmp32
, tmp
);
2439 tcg_gen_andi_i32(tmp32
, tmp32
, 0xffff);
2440 set_cc_nz_u32(s
, tmp32
); /* signedness should not matter here */
2441 tcg_temp_free_i64(tmp2
);
2442 tcg_temp_free_i32(tmp32
);
2444 case 0xc: /* LLIHH R1,I2 [RI] */
2445 tmp
= tcg_const_i64( ((uint64_t)i2
) << 48 );
2448 case 0xd: /* LLIHL R1,I2 [RI] */
2449 tmp
= tcg_const_i64( ((uint64_t)i2
) << 32 );
2452 case 0xe: /* LLILH R1,I2 [RI] */
2453 tmp
= tcg_const_i64( ((uint64_t)i2
) << 16 );
2456 case 0xf: /* LLILL R1,I2 [RI] */
2457 tmp
= tcg_const_i64(i2
);
2461 LOG_DISAS("illegal a5 operation 0x%x\n", op
);
2462 gen_illegal_opcode(s
, 2);
2465 tcg_temp_free_i64(tmp
);
2468 static void disas_a7(DisasContext
*s
, int op
, int r1
, int i2
)
2471 TCGv_i32 tmp32_1
, tmp32_2
, tmp32_3
;
2474 LOG_DISAS("disas_a7: op 0x%x r1 %d i2 0x%x\n", op
, r1
, i2
);
2476 case 0x0: /* TMLH or TMH R1,I2 [RI] */
2477 case 0x1: /* TMLL or TML R1,I2 [RI] */
2478 case 0x2: /* TMHH R1,I2 [RI] */
2479 case 0x3: /* TMHL R1,I2 [RI] */
2481 tmp2
= tcg_const_i64((uint16_t)i2
);
2484 tcg_gen_shri_i64(tmp
, tmp
, 16);
2489 tcg_gen_shri_i64(tmp
, tmp
, 48);
2492 tcg_gen_shri_i64(tmp
, tmp
, 32);
2495 tcg_gen_andi_i64(tmp
, tmp
, 0xffff);
2496 cmp_64(s
, tmp
, tmp2
, CC_OP_TM_64
);
2497 tcg_temp_free_i64(tmp
);
2498 tcg_temp_free_i64(tmp2
);
2500 case 0x4: /* brc m1, i2 */
2501 gen_brc(r1
, s
, i2
* 2LL);
2503 case 0x5: /* BRAS R1,I2 [RI] */
2504 tmp
= tcg_const_i64(pc_to_link_info(s
, s
->pc
+ 4));
2506 tcg_temp_free_i64(tmp
);
2507 gen_goto_tb(s
, 0, s
->pc
+ i2
* 2LL);
2508 s
->is_jmp
= DISAS_TB_JUMP
;
2510 case 0x6: /* BRCT R1,I2 [RI] */
2511 tmp32_1
= load_reg32(r1
);
2512 tcg_gen_subi_i32(tmp32_1
, tmp32_1
, 1);
2513 store_reg32(r1
, tmp32_1
);
2514 gen_update_cc_op(s
);
2515 l1
= gen_new_label();
2516 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp32_1
, 0, l1
);
2517 gen_goto_tb(s
, 0, s
->pc
+ (i2
* 2LL));
2519 gen_goto_tb(s
, 1, s
->pc
+ 4);
2520 s
->is_jmp
= DISAS_TB_JUMP
;
2521 tcg_temp_free_i32(tmp32_1
);
2523 case 0x7: /* BRCTG R1,I2 [RI] */
2525 tcg_gen_subi_i64(tmp
, tmp
, 1);
2527 gen_update_cc_op(s
);
2528 l1
= gen_new_label();
2529 tcg_gen_brcondi_i64(TCG_COND_EQ
, tmp
, 0, l1
);
2530 gen_goto_tb(s
, 0, s
->pc
+ (i2
* 2LL));
2532 gen_goto_tb(s
, 1, s
->pc
+ 4);
2533 s
->is_jmp
= DISAS_TB_JUMP
;
2534 tcg_temp_free_i64(tmp
);
2536 case 0x8: /* lhi r1, i2 */
2537 tmp32_1
= tcg_const_i32(i2
);
2538 store_reg32(r1
, tmp32_1
);
2539 tcg_temp_free_i32(tmp32_1
);
2541 case 0x9: /* lghi r1, i2 */
2542 tmp
= tcg_const_i64(i2
);
2544 tcg_temp_free_i64(tmp
);
2546 case 0xa: /* AHI R1,I2 [RI] */
2547 tmp32_1
= load_reg32(r1
);
2548 tmp32_2
= tcg_temp_new_i32();
2549 tmp32_3
= tcg_const_i32(i2
);
2552 tcg_gen_subi_i32(tmp32_2
, tmp32_1
, -i2
);
2554 tcg_gen_add_i32(tmp32_2
, tmp32_1
, tmp32_3
);
2557 store_reg32(r1
, tmp32_2
);
2558 set_cc_add32(s
, tmp32_1
, tmp32_3
, tmp32_2
);
2559 tcg_temp_free_i32(tmp32_1
);
2560 tcg_temp_free_i32(tmp32_2
);
2561 tcg_temp_free_i32(tmp32_3
);
2563 case 0xb: /* aghi r1, i2 */
2565 tmp2
= tcg_const_i64(i2
);
2568 tcg_gen_subi_i64(regs
[r1
], tmp
, -i2
);
2570 tcg_gen_add_i64(regs
[r1
], tmp
, tmp2
);
2572 set_cc_add64(s
, tmp
, tmp2
, regs
[r1
]);
2573 tcg_temp_free_i64(tmp
);
2574 tcg_temp_free_i64(tmp2
);
2576 case 0xc: /* MHI R1,I2 [RI] */
2577 tmp32_1
= load_reg32(r1
);
2578 tcg_gen_muli_i32(tmp32_1
, tmp32_1
, i2
);
2579 store_reg32(r1
, tmp32_1
);
2580 tcg_temp_free_i32(tmp32_1
);
2582 case 0xd: /* MGHI R1,I2 [RI] */
2584 tcg_gen_muli_i64(tmp
, tmp
, i2
);
2586 tcg_temp_free_i64(tmp
);
2588 case 0xe: /* CHI R1,I2 [RI] */
2589 tmp32_1
= load_reg32(r1
);
2590 cmp_s32c(s
, tmp32_1
, i2
);
2591 tcg_temp_free_i32(tmp32_1
);
2593 case 0xf: /* CGHI R1,I2 [RI] */
2595 cmp_s64c(s
, tmp
, i2
);
2596 tcg_temp_free_i64(tmp
);
2599 LOG_DISAS("illegal a7 operation 0x%x\n", op
);
2600 gen_illegal_opcode(s
, 2);
2605 static void disas_b2(DisasContext
*s
, int op
, uint32_t insn
)
2607 TCGv_i64 tmp
, tmp2
, tmp3
;
2608 TCGv_i32 tmp32_1
, tmp32_2
, tmp32_3
;
2611 #ifndef CONFIG_USER_ONLY
2615 r1
= (insn
>> 4) & 0xf;
2618 LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op
, r1
, r2
);
2621 case 0x22: /* IPM R1 [RRE] */
2622 tmp32_1
= tcg_const_i32(r1
);
2624 gen_helper_ipm(cc_op
, tmp32_1
);
2625 tcg_temp_free_i32(tmp32_1
);
2627 case 0x41: /* CKSM R1,R2 [RRE] */
2628 tmp32_1
= tcg_const_i32(r1
);
2629 tmp32_2
= tcg_const_i32(r2
);
2630 potential_page_fault(s
);
2631 gen_helper_cksm(tmp32_1
, tmp32_2
);
2632 tcg_temp_free_i32(tmp32_1
);
2633 tcg_temp_free_i32(tmp32_2
);
2634 gen_op_movi_cc(s
, 0);
2636 case 0x4e: /* SAR R1,R2 [RRE] */
2637 tmp32_1
= load_reg32(r2
);
2638 tcg_gen_st_i32(tmp32_1
, cpu_env
, offsetof(CPUState
, aregs
[r1
]));
2639 tcg_temp_free_i32(tmp32_1
);
2641 case 0x4f: /* EAR R1,R2 [RRE] */
2642 tmp32_1
= tcg_temp_new_i32();
2643 tcg_gen_ld_i32(tmp32_1
, cpu_env
, offsetof(CPUState
, aregs
[r2
]));
2644 store_reg32(r1
, tmp32_1
);
2645 tcg_temp_free_i32(tmp32_1
);
2647 case 0x52: /* MSR R1,R2 [RRE] */
2648 tmp32_1
= load_reg32(r1
);
2649 tmp32_2
= load_reg32(r2
);
2650 tcg_gen_mul_i32(tmp32_1
, tmp32_1
, tmp32_2
);
2651 store_reg32(r1
, tmp32_1
);
2652 tcg_temp_free_i32(tmp32_1
);
2653 tcg_temp_free_i32(tmp32_2
);
2655 case 0x54: /* MVPG R1,R2 [RRE] */
2657 tmp2
= load_reg(r1
);
2658 tmp3
= load_reg(r2
);
2659 potential_page_fault(s
);
2660 gen_helper_mvpg(tmp
, tmp2
, tmp3
);
2661 tcg_temp_free_i64(tmp
);
2662 tcg_temp_free_i64(tmp2
);
2663 tcg_temp_free_i64(tmp3
);
2664 /* XXX check CCO bit and set CC accordingly */
2665 gen_op_movi_cc(s
, 0);
2667 case 0x55: /* MVST R1,R2 [RRE] */
2668 tmp32_1
= load_reg32(0);
2669 tmp32_2
= tcg_const_i32(r1
);
2670 tmp32_3
= tcg_const_i32(r2
);
2671 potential_page_fault(s
);
2672 gen_helper_mvst(tmp32_1
, tmp32_2
, tmp32_3
);
2673 tcg_temp_free_i32(tmp32_1
);
2674 tcg_temp_free_i32(tmp32_2
);
2675 tcg_temp_free_i32(tmp32_3
);
2676 gen_op_movi_cc(s
, 1);
2678 case 0x5d: /* CLST R1,R2 [RRE] */
2679 tmp32_1
= load_reg32(0);
2680 tmp32_2
= tcg_const_i32(r1
);
2681 tmp32_3
= tcg_const_i32(r2
);
2682 potential_page_fault(s
);
2683 gen_helper_clst(cc_op
, tmp32_1
, tmp32_2
, tmp32_3
);
2685 tcg_temp_free_i32(tmp32_1
);
2686 tcg_temp_free_i32(tmp32_2
);
2687 tcg_temp_free_i32(tmp32_3
);
2689 case 0x5e: /* SRST R1,R2 [RRE] */
2690 tmp32_1
= load_reg32(0);
2691 tmp32_2
= tcg_const_i32(r1
);
2692 tmp32_3
= tcg_const_i32(r2
);
2693 potential_page_fault(s
);
2694 gen_helper_srst(cc_op
, tmp32_1
, tmp32_2
, tmp32_3
);
2696 tcg_temp_free_i32(tmp32_1
);
2697 tcg_temp_free_i32(tmp32_2
);
2698 tcg_temp_free_i32(tmp32_3
);
2701 #ifndef CONFIG_USER_ONLY
2702 case 0x02: /* STIDP D2(B2) [S] */
2704 check_privileged(s
, ilc
);
2705 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2706 tmp
= get_address(s
, 0, b2
, d2
);
2707 potential_page_fault(s
);
2708 gen_helper_stidp(tmp
);
2709 tcg_temp_free_i64(tmp
);
2711 case 0x04: /* SCK D2(B2) [S] */
2713 check_privileged(s
, ilc
);
2714 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2715 tmp
= get_address(s
, 0, b2
, d2
);
2716 potential_page_fault(s
);
2717 gen_helper_sck(cc_op
, tmp
);
2719 tcg_temp_free_i64(tmp
);
2721 case 0x05: /* STCK D2(B2) [S] */
2723 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2724 tmp
= get_address(s
, 0, b2
, d2
);
2725 potential_page_fault(s
);
2726 gen_helper_stck(cc_op
, tmp
);
2728 tcg_temp_free_i64(tmp
);
2730 case 0x06: /* SCKC D2(B2) [S] */
2731 /* Set Clock Comparator */
2732 check_privileged(s
, ilc
);
2733 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2734 tmp
= get_address(s
, 0, b2
, d2
);
2735 potential_page_fault(s
);
2736 gen_helper_sckc(tmp
);
2737 tcg_temp_free_i64(tmp
);
2739 case 0x07: /* STCKC D2(B2) [S] */
2740 /* Store Clock Comparator */
2741 check_privileged(s
, ilc
);
2742 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2743 tmp
= get_address(s
, 0, b2
, d2
);
2744 potential_page_fault(s
);
2745 gen_helper_stckc(tmp
);
2746 tcg_temp_free_i64(tmp
);
2748 case 0x08: /* SPT D2(B2) [S] */
2750 check_privileged(s
, ilc
);
2751 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2752 tmp
= get_address(s
, 0, b2
, d2
);
2753 potential_page_fault(s
);
2754 gen_helper_spt(tmp
);
2755 tcg_temp_free_i64(tmp
);
2757 case 0x09: /* STPT D2(B2) [S] */
2758 /* Store CPU Timer */
2759 check_privileged(s
, ilc
);
2760 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2761 tmp
= get_address(s
, 0, b2
, d2
);
2762 potential_page_fault(s
);
2763 gen_helper_stpt(tmp
);
2764 tcg_temp_free_i64(tmp
);
2766 case 0x0a: /* SPKA D2(B2) [S] */
2767 /* Set PSW Key from Address */
2768 check_privileged(s
, ilc
);
2769 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2770 tmp
= get_address(s
, 0, b2
, d2
);
2771 tmp2
= tcg_temp_new_i64();
2772 tcg_gen_andi_i64(tmp2
, psw_mask
, ~PSW_MASK_KEY
);
2773 tcg_gen_shli_i64(tmp
, tmp
, PSW_SHIFT_KEY
- 4);
2774 tcg_gen_or_i64(psw_mask
, tmp2
, tmp
);
2775 tcg_temp_free_i64(tmp2
);
2776 tcg_temp_free_i64(tmp
);
2778 case 0x0d: /* PTLB [S] */
2780 check_privileged(s
, ilc
);
2783 case 0x10: /* SPX D2(B2) [S] */
2784 /* Set Prefix Register */
2785 check_privileged(s
, ilc
);
2786 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2787 tmp
= get_address(s
, 0, b2
, d2
);
2788 potential_page_fault(s
);
2789 gen_helper_spx(tmp
);
2790 tcg_temp_free_i64(tmp
);
2792 case 0x11: /* STPX D2(B2) [S] */
2794 check_privileged(s
, ilc
);
2795 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2796 tmp
= get_address(s
, 0, b2
, d2
);
2797 tmp2
= tcg_temp_new_i64();
2798 tcg_gen_ld_i64(tmp2
, cpu_env
, offsetof(CPUState
, psa
));
2799 tcg_gen_qemu_st32(tmp2
, tmp
, get_mem_index(s
));
2800 tcg_temp_free_i64(tmp
);
2801 tcg_temp_free_i64(tmp2
);
2803 case 0x12: /* STAP D2(B2) [S] */
2804 /* Store CPU Address */
2805 check_privileged(s
, ilc
);
2806 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2807 tmp
= get_address(s
, 0, b2
, d2
);
2808 tmp2
= tcg_temp_new_i64();
2809 tmp32_1
= tcg_temp_new_i32();
2810 tcg_gen_ld_i32(tmp32_1
, cpu_env
, offsetof(CPUState
, cpu_num
));
2811 tcg_gen_extu_i32_i64(tmp2
, tmp32_1
);
2812 tcg_gen_qemu_st32(tmp2
, tmp
, get_mem_index(s
));
2813 tcg_temp_free_i64(tmp
);
2814 tcg_temp_free_i64(tmp2
);
2815 tcg_temp_free_i32(tmp32_1
);
2817 case 0x21: /* IPTE R1,R2 [RRE] */
2818 /* Invalidate PTE */
2819 check_privileged(s
, ilc
);
2820 r1
= (insn
>> 4) & 0xf;
2823 tmp2
= load_reg(r2
);
2824 gen_helper_ipte(tmp
, tmp2
);
2825 tcg_temp_free_i64(tmp
);
2826 tcg_temp_free_i64(tmp2
);
2828 case 0x29: /* ISKE R1,R2 [RRE] */
2829 /* Insert Storage Key Extended */
2830 check_privileged(s
, ilc
);
2831 r1
= (insn
>> 4) & 0xf;
2834 tmp2
= tcg_temp_new_i64();
2835 gen_helper_iske(tmp2
, tmp
);
2836 store_reg(r1
, tmp2
);
2837 tcg_temp_free_i64(tmp
);
2838 tcg_temp_free_i64(tmp2
);
2840 case 0x2a: /* RRBE R1,R2 [RRE] */
2841 /* Set Storage Key Extended */
2842 check_privileged(s
, ilc
);
2843 r1
= (insn
>> 4) & 0xf;
2845 tmp32_1
= load_reg32(r1
);
2847 gen_helper_rrbe(cc_op
, tmp32_1
, tmp
);
2849 tcg_temp_free_i32(tmp32_1
);
2850 tcg_temp_free_i64(tmp
);
2852 case 0x2b: /* SSKE R1,R2 [RRE] */
2853 /* Set Storage Key Extended */
2854 check_privileged(s
, ilc
);
2855 r1
= (insn
>> 4) & 0xf;
2857 tmp32_1
= load_reg32(r1
);
2859 gen_helper_sske(tmp32_1
, tmp
);
2860 tcg_temp_free_i32(tmp32_1
);
2861 tcg_temp_free_i64(tmp
);
2863 case 0x34: /* STCH ? */
2864 /* Store Subchannel */
2865 check_privileged(s
, ilc
);
2866 gen_op_movi_cc(s
, 3);
2868 case 0x46: /* STURA R1,R2 [RRE] */
2869 /* Store Using Real Address */
2870 check_privileged(s
, ilc
);
2871 r1
= (insn
>> 4) & 0xf;
2873 tmp32_1
= load_reg32(r1
);
2875 potential_page_fault(s
);
2876 gen_helper_stura(tmp
, tmp32_1
);
2877 tcg_temp_free_i32(tmp32_1
);
2878 tcg_temp_free_i64(tmp
);
2880 case 0x50: /* CSP R1,R2 [RRE] */
2881 /* Compare And Swap And Purge */
2882 check_privileged(s
, ilc
);
2883 r1
= (insn
>> 4) & 0xf;
2885 tmp32_1
= tcg_const_i32(r1
);
2886 tmp32_2
= tcg_const_i32(r2
);
2887 gen_helper_csp(cc_op
, tmp32_1
, tmp32_2
);
2889 tcg_temp_free_i32(tmp32_1
);
2890 tcg_temp_free_i32(tmp32_2
);
2892 case 0x5f: /* CHSC ? */
2893 /* Channel Subsystem Call */
2894 check_privileged(s
, ilc
);
2895 gen_op_movi_cc(s
, 3);
2897 case 0x78: /* STCKE D2(B2) [S] */
2898 /* Store Clock Extended */
2899 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2900 tmp
= get_address(s
, 0, b2
, d2
);
2901 potential_page_fault(s
);
2902 gen_helper_stcke(cc_op
, tmp
);
2904 tcg_temp_free_i64(tmp
);
2906 case 0x79: /* SACF D2(B2) [S] */
2907 /* Store Clock Extended */
2908 check_privileged(s
, ilc
);
2909 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2910 tmp
= get_address(s
, 0, b2
, d2
);
2911 potential_page_fault(s
);
2912 gen_helper_sacf(tmp
);
2913 tcg_temp_free_i64(tmp
);
2914 /* addressing mode has changed, so end the block */
2917 s
->is_jmp
= DISAS_EXCP
;
2919 case 0x7d: /* STSI D2,(B2) [S] */
2920 check_privileged(s
, ilc
);
2921 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2922 tmp
= get_address(s
, 0, b2
, d2
);
2923 tmp32_1
= load_reg32(0);
2924 tmp32_2
= load_reg32(1);
2925 potential_page_fault(s
);
2926 gen_helper_stsi(cc_op
, tmp
, tmp32_1
, tmp32_2
);
2928 tcg_temp_free_i64(tmp
);
2929 tcg_temp_free_i32(tmp32_1
);
2930 tcg_temp_free_i32(tmp32_2
);
2932 case 0x9d: /* LFPC D2(B2) [S] */
2933 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2934 tmp
= get_address(s
, 0, b2
, d2
);
2935 tmp2
= tcg_temp_new_i64();
2936 tmp32_1
= tcg_temp_new_i32();
2937 tcg_gen_qemu_ld32u(tmp2
, tmp
, get_mem_index(s
));
2938 tcg_gen_trunc_i64_i32(tmp32_1
, tmp2
);
2939 tcg_gen_st_i32(tmp32_1
, cpu_env
, offsetof(CPUState
, fpc
));
2940 tcg_temp_free_i64(tmp
);
2941 tcg_temp_free_i64(tmp2
);
2942 tcg_temp_free_i32(tmp32_1
);
2944 case 0xb1: /* STFL D2(B2) [S] */
2945 /* Store Facility List (CPU features) at 200 */
2946 check_privileged(s
, ilc
);
2947 tmp2
= tcg_const_i64(0xc0000000);
2948 tmp
= tcg_const_i64(200);
2949 tcg_gen_qemu_st32(tmp2
, tmp
, get_mem_index(s
));
2950 tcg_temp_free_i64(tmp2
);
2951 tcg_temp_free_i64(tmp
);
2953 case 0xb2: /* LPSWE D2(B2) [S] */
2954 /* Load PSW Extended */
2955 check_privileged(s
, ilc
);
2956 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2957 tmp
= get_address(s
, 0, b2
, d2
);
2958 tmp2
= tcg_temp_new_i64();
2959 tmp3
= tcg_temp_new_i64();
2960 tcg_gen_qemu_ld64(tmp2
, tmp
, get_mem_index(s
));
2961 tcg_gen_addi_i64(tmp
, tmp
, 8);
2962 tcg_gen_qemu_ld64(tmp3
, tmp
, get_mem_index(s
));
2963 gen_helper_load_psw(tmp2
, tmp3
);
2964 /* we need to keep cc_op intact */
2965 s
->is_jmp
= DISAS_JUMP
;
2966 tcg_temp_free_i64(tmp
);
2967 tcg_temp_free_i64(tmp2
);
2968 tcg_temp_free_i64(tmp3
);
2970 case 0x20: /* SERVC R1,R2 [RRE] */
2971 /* SCLP Service call (PV hypercall) */
2972 check_privileged(s
, ilc
);
2973 potential_page_fault(s
);
2974 tmp32_1
= load_reg32(r2
);
2976 gen_helper_servc(cc_op
, tmp32_1
, tmp
);
2978 tcg_temp_free_i32(tmp32_1
);
2979 tcg_temp_free_i64(tmp
);
2983 LOG_DISAS("illegal b2 operation 0x%x\n", op
);
2984 gen_illegal_opcode(s
, ilc
);
2989 static void disas_b3(DisasContext
*s
, int op
, int m3
, int r1
, int r2
)
2992 TCGv_i32 tmp32_1
, tmp32_2
, tmp32_3
;
2993 LOG_DISAS("disas_b3: op 0x%x m3 0x%x r1 %d r2 %d\n", op
, m3
, r1
, r2
);
2994 #define FP_HELPER(i) \
2995 tmp32_1 = tcg_const_i32(r1); \
2996 tmp32_2 = tcg_const_i32(r2); \
2997 gen_helper_ ## i (tmp32_1, tmp32_2); \
2998 tcg_temp_free_i32(tmp32_1); \
2999 tcg_temp_free_i32(tmp32_2);
3001 #define FP_HELPER_CC(i) \
3002 tmp32_1 = tcg_const_i32(r1); \
3003 tmp32_2 = tcg_const_i32(r2); \
3004 gen_helper_ ## i (cc_op, tmp32_1, tmp32_2); \
3006 tcg_temp_free_i32(tmp32_1); \
3007 tcg_temp_free_i32(tmp32_2);
3010 case 0x0: /* LPEBR R1,R2 [RRE] */
3011 FP_HELPER_CC(lpebr
);
3013 case 0x2: /* LTEBR R1,R2 [RRE] */
3014 FP_HELPER_CC(ltebr
);
3016 case 0x3: /* LCEBR R1,R2 [RRE] */
3017 FP_HELPER_CC(lcebr
);
3019 case 0x4: /* LDEBR R1,R2 [RRE] */
3022 case 0x5: /* LXDBR R1,R2 [RRE] */
3025 case 0x9: /* CEBR R1,R2 [RRE] */
3028 case 0xa: /* AEBR R1,R2 [RRE] */
3031 case 0xb: /* SEBR R1,R2 [RRE] */
3034 case 0xd: /* DEBR R1,R2 [RRE] */
3037 case 0x10: /* LPDBR R1,R2 [RRE] */
3038 FP_HELPER_CC(lpdbr
);
3040 case 0x12: /* LTDBR R1,R2 [RRE] */
3041 FP_HELPER_CC(ltdbr
);
3043 case 0x13: /* LCDBR R1,R2 [RRE] */
3044 FP_HELPER_CC(lcdbr
);
3046 case 0x15: /* SQBDR R1,R2 [RRE] */
3049 case 0x17: /* MEEBR R1,R2 [RRE] */
3052 case 0x19: /* CDBR R1,R2 [RRE] */
3055 case 0x1a: /* ADBR R1,R2 [RRE] */
3058 case 0x1b: /* SDBR R1,R2 [RRE] */
3061 case 0x1c: /* MDBR R1,R2 [RRE] */
3064 case 0x1d: /* DDBR R1,R2 [RRE] */
3067 case 0xe: /* MAEBR R1,R3,R2 [RRF] */
3068 case 0x1e: /* MADBR R1,R3,R2 [RRF] */
3069 case 0x1f: /* MSDBR R1,R3,R2 [RRF] */
3070 /* for RRF insns, m3 is R1, r1 is R3, and r2 is R2 */
3071 tmp32_1
= tcg_const_i32(m3
);
3072 tmp32_2
= tcg_const_i32(r2
);
3073 tmp32_3
= tcg_const_i32(r1
);
3076 gen_helper_maebr(tmp32_1
, tmp32_3
, tmp32_2
);
3079 gen_helper_madbr(tmp32_1
, tmp32_3
, tmp32_2
);
3082 gen_helper_msdbr(tmp32_1
, tmp32_3
, tmp32_2
);
3087 tcg_temp_free_i32(tmp32_1
);
3088 tcg_temp_free_i32(tmp32_2
);
3089 tcg_temp_free_i32(tmp32_3
);
3091 case 0x40: /* LPXBR R1,R2 [RRE] */
3092 FP_HELPER_CC(lpxbr
);
3094 case 0x42: /* LTXBR R1,R2 [RRE] */
3095 FP_HELPER_CC(ltxbr
);
3097 case 0x43: /* LCXBR R1,R2 [RRE] */
3098 FP_HELPER_CC(lcxbr
);
3100 case 0x44: /* LEDBR R1,R2 [RRE] */
3103 case 0x45: /* LDXBR R1,R2 [RRE] */
3106 case 0x46: /* LEXBR R1,R2 [RRE] */
3109 case 0x49: /* CXBR R1,R2 [RRE] */
3112 case 0x4a: /* AXBR R1,R2 [RRE] */
3115 case 0x4b: /* SXBR R1,R2 [RRE] */
3118 case 0x4c: /* MXBR R1,R2 [RRE] */
3121 case 0x4d: /* DXBR R1,R2 [RRE] */
3124 case 0x65: /* LXR R1,R2 [RRE] */
3125 tmp
= load_freg(r2
);
3126 store_freg(r1
, tmp
);
3127 tcg_temp_free_i64(tmp
);
3128 tmp
= load_freg(r2
+ 2);
3129 store_freg(r1
+ 2, tmp
);
3130 tcg_temp_free_i64(tmp
);
3132 case 0x74: /* LZER R1 [RRE] */
3133 tmp32_1
= tcg_const_i32(r1
);
3134 gen_helper_lzer(tmp32_1
);
3135 tcg_temp_free_i32(tmp32_1
);
3137 case 0x75: /* LZDR R1 [RRE] */
3138 tmp32_1
= tcg_const_i32(r1
);
3139 gen_helper_lzdr(tmp32_1
);
3140 tcg_temp_free_i32(tmp32_1
);
3142 case 0x76: /* LZXR R1 [RRE] */
3143 tmp32_1
= tcg_const_i32(r1
);
3144 gen_helper_lzxr(tmp32_1
);
3145 tcg_temp_free_i32(tmp32_1
);
3147 case 0x84: /* SFPC R1 [RRE] */
3148 tmp32_1
= load_reg32(r1
);
3149 tcg_gen_st_i32(tmp32_1
, cpu_env
, offsetof(CPUState
, fpc
));
3150 tcg_temp_free_i32(tmp32_1
);
3152 case 0x8c: /* EFPC R1 [RRE] */
3153 tmp32_1
= tcg_temp_new_i32();
3154 tcg_gen_ld_i32(tmp32_1
, cpu_env
, offsetof(CPUState
, fpc
));
3155 store_reg32(r1
, tmp32_1
);
3156 tcg_temp_free_i32(tmp32_1
);
3158 case 0x94: /* CEFBR R1,R2 [RRE] */
3159 case 0x95: /* CDFBR R1,R2 [RRE] */
3160 case 0x96: /* CXFBR R1,R2 [RRE] */
3161 tmp32_1
= tcg_const_i32(r1
);
3162 tmp32_2
= load_reg32(r2
);
3165 gen_helper_cefbr(tmp32_1
, tmp32_2
);
3168 gen_helper_cdfbr(tmp32_1
, tmp32_2
);
3171 gen_helper_cxfbr(tmp32_1
, tmp32_2
);
3176 tcg_temp_free_i32(tmp32_1
);
3177 tcg_temp_free_i32(tmp32_2
);
3179 case 0x98: /* CFEBR R1,R2 [RRE] */
3180 case 0x99: /* CFDBR R1,R2 [RRE] */
3181 case 0x9a: /* CFXBR R1,R2 [RRE] */
3182 tmp32_1
= tcg_const_i32(r1
);
3183 tmp32_2
= tcg_const_i32(r2
);
3184 tmp32_3
= tcg_const_i32(m3
);
3187 gen_helper_cfebr(cc_op
, tmp32_1
, tmp32_2
, tmp32_3
);
3190 gen_helper_cfdbr(cc_op
, tmp32_1
, tmp32_2
, tmp32_3
);
3193 gen_helper_cfxbr(cc_op
, tmp32_1
, tmp32_2
, tmp32_3
);
3199 tcg_temp_free_i32(tmp32_1
);
3200 tcg_temp_free_i32(tmp32_2
);
3201 tcg_temp_free_i32(tmp32_3
);
3203 case 0xa4: /* CEGBR R1,R2 [RRE] */
3204 case 0xa5: /* CDGBR R1,R2 [RRE] */
3205 tmp32_1
= tcg_const_i32(r1
);
3209 gen_helper_cegbr(tmp32_1
, tmp
);
3212 gen_helper_cdgbr(tmp32_1
, tmp
);
3217 tcg_temp_free_i32(tmp32_1
);
3218 tcg_temp_free_i64(tmp
);
3220 case 0xa6: /* CXGBR R1,R2 [RRE] */
3221 tmp32_1
= tcg_const_i32(r1
);
3223 gen_helper_cxgbr(tmp32_1
, tmp
);
3224 tcg_temp_free_i32(tmp32_1
);
3225 tcg_temp_free_i64(tmp
);
3227 case 0xa8: /* CGEBR R1,R2 [RRE] */
3228 tmp32_1
= tcg_const_i32(r1
);
3229 tmp32_2
= tcg_const_i32(r2
);
3230 tmp32_3
= tcg_const_i32(m3
);
3231 gen_helper_cgebr(cc_op
, tmp32_1
, tmp32_2
, tmp32_3
);
3233 tcg_temp_free_i32(tmp32_1
);
3234 tcg_temp_free_i32(tmp32_2
);
3235 tcg_temp_free_i32(tmp32_3
);
3237 case 0xa9: /* CGDBR R1,R2 [RRE] */
3238 tmp32_1
= tcg_const_i32(r1
);
3239 tmp32_2
= tcg_const_i32(r2
);
3240 tmp32_3
= tcg_const_i32(m3
);
3241 gen_helper_cgdbr(cc_op
, tmp32_1
, tmp32_2
, tmp32_3
);
3243 tcg_temp_free_i32(tmp32_1
);
3244 tcg_temp_free_i32(tmp32_2
);
3245 tcg_temp_free_i32(tmp32_3
);
3247 case 0xaa: /* CGXBR R1,R2 [RRE] */
3248 tmp32_1
= tcg_const_i32(r1
);
3249 tmp32_2
= tcg_const_i32(r2
);
3250 tmp32_3
= tcg_const_i32(m3
);
3251 gen_helper_cgxbr(cc_op
, tmp32_1
, tmp32_2
, tmp32_3
);
3253 tcg_temp_free_i32(tmp32_1
);
3254 tcg_temp_free_i32(tmp32_2
);
3255 tcg_temp_free_i32(tmp32_3
);
3258 LOG_DISAS("illegal b3 operation 0x%x\n", op
);
3259 gen_illegal_opcode(s
, 2);
3267 static void disas_b9(DisasContext
*s
, int op
, int r1
, int r2
)
3269 TCGv_i64 tmp
, tmp2
, tmp3
;
3270 TCGv_i32 tmp32_1
, tmp32_2
, tmp32_3
;
3272 LOG_DISAS("disas_b9: op 0x%x r1 %d r2 %d\n", op
, r1
, r2
);
3274 case 0x0: /* LPGR R1,R2 [RRE] */
3275 case 0x1: /* LNGR R1,R2 [RRE] */
3276 case 0x2: /* LTGR R1,R2 [RRE] */
3277 case 0x3: /* LCGR R1,R2 [RRE] */
3278 case 0x10: /* LPGFR R1,R2 [RRE] */
3279 case 0x11: /* LNFGR R1,R2 [RRE] */
3280 case 0x12: /* LTGFR R1,R2 [RRE] */
3281 case 0x13: /* LCGFR R1,R2 [RRE] */
3283 tmp
= load_reg32_i64(r2
);
3288 case 0x0: /* LP?GR */
3289 set_cc_abs64(s
, tmp
);
3290 gen_helper_abs_i64(tmp
, tmp
);
3293 case 0x1: /* LN?GR */
3294 set_cc_nabs64(s
, tmp
);
3295 gen_helper_nabs_i64(tmp
, tmp
);
3298 case 0x2: /* LT?GR */
3304 case 0x3: /* LC?GR */
3305 tcg_gen_neg_i64(regs
[r1
], tmp
);
3306 set_cc_comp64(s
, regs
[r1
]);
3309 tcg_temp_free_i64(tmp
);
3311 case 0x4: /* LGR R1,R2 [RRE] */
3312 store_reg(r1
, regs
[r2
]);
3314 case 0x6: /* LGBR R1,R2 [RRE] */
3315 tmp2
= load_reg(r2
);
3316 tcg_gen_ext8s_i64(tmp2
, tmp2
);
3317 store_reg(r1
, tmp2
);
3318 tcg_temp_free_i64(tmp2
);
3320 case 0x8: /* AGR R1,R2 [RRE] */
3321 case 0xa: /* ALGR R1,R2 [RRE] */
3323 tmp2
= load_reg(r2
);
3324 tmp3
= tcg_temp_new_i64();
3325 tcg_gen_add_i64(tmp3
, tmp
, tmp2
);
3326 store_reg(r1
, tmp3
);
3329 set_cc_add64(s
, tmp
, tmp2
, tmp3
);
3332 set_cc_addu64(s
, tmp
, tmp2
, tmp3
);
3337 tcg_temp_free_i64(tmp
);
3338 tcg_temp_free_i64(tmp2
);
3339 tcg_temp_free_i64(tmp3
);
3341 case 0x9: /* SGR R1,R2 [RRE] */
3342 case 0xb: /* SLGR R1,R2 [RRE] */
3343 case 0x1b: /* SLGFR R1,R2 [RRE] */
3344 case 0x19: /* SGFR R1,R2 [RRE] */
3348 tmp32_1
= load_reg32(r2
);
3349 tmp2
= tcg_temp_new_i64();
3350 tcg_gen_extu_i32_i64(tmp2
, tmp32_1
);
3351 tcg_temp_free_i32(tmp32_1
);
3354 tmp32_1
= load_reg32(r2
);
3355 tmp2
= tcg_temp_new_i64();
3356 tcg_gen_ext_i32_i64(tmp2
, tmp32_1
);
3357 tcg_temp_free_i32(tmp32_1
);
3360 tmp2
= load_reg(r2
);
3363 tmp3
= tcg_temp_new_i64();
3364 tcg_gen_sub_i64(tmp3
, tmp
, tmp2
);
3365 store_reg(r1
, tmp3
);
3369 set_cc_sub64(s
, tmp
, tmp2
, tmp3
);
3373 set_cc_subu64(s
, tmp
, tmp2
, tmp3
);
3378 tcg_temp_free_i64(tmp
);
3379 tcg_temp_free_i64(tmp2
);
3380 tcg_temp_free_i64(tmp3
);
3382 case 0xc: /* MSGR R1,R2 [RRE] */
3383 case 0x1c: /* MSGFR R1,R2 [RRE] */
3385 tmp2
= load_reg(r2
);
3387 tcg_gen_ext32s_i64(tmp2
, tmp2
);
3389 tcg_gen_mul_i64(tmp
, tmp
, tmp2
);
3391 tcg_temp_free_i64(tmp
);
3392 tcg_temp_free_i64(tmp2
);
3394 case 0xd: /* DSGR R1,R2 [RRE] */
3395 case 0x1d: /* DSGFR R1,R2 [RRE] */
3396 tmp
= load_reg(r1
+ 1);
3398 tmp2
= load_reg(r2
);
3400 tmp32_1
= load_reg32(r2
);
3401 tmp2
= tcg_temp_new_i64();
3402 tcg_gen_ext_i32_i64(tmp2
, tmp32_1
);
3403 tcg_temp_free_i32(tmp32_1
);
3405 tmp3
= tcg_temp_new_i64();
3406 tcg_gen_div_i64(tmp3
, tmp
, tmp2
);
3407 store_reg(r1
+ 1, tmp3
);
3408 tcg_gen_rem_i64(tmp3
, tmp
, tmp2
);
3409 store_reg(r1
, tmp3
);
3410 tcg_temp_free_i64(tmp
);
3411 tcg_temp_free_i64(tmp2
);
3412 tcg_temp_free_i64(tmp3
);
3414 case 0x14: /* LGFR R1,R2 [RRE] */
3415 tmp32_1
= load_reg32(r2
);
3416 tmp
= tcg_temp_new_i64();
3417 tcg_gen_ext_i32_i64(tmp
, tmp32_1
);
3419 tcg_temp_free_i32(tmp32_1
);
3420 tcg_temp_free_i64(tmp
);
3422 case 0x16: /* LLGFR R1,R2 [RRE] */
3423 tmp32_1
= load_reg32(r2
);
3424 tmp
= tcg_temp_new_i64();
3425 tcg_gen_extu_i32_i64(tmp
, tmp32_1
);
3427 tcg_temp_free_i32(tmp32_1
);
3428 tcg_temp_free_i64(tmp
);
3430 case 0x17: /* LLGTR R1,R2 [RRE] */
3431 tmp32_1
= load_reg32(r2
);
3432 tmp
= tcg_temp_new_i64();
3433 tcg_gen_andi_i32(tmp32_1
, tmp32_1
, 0x7fffffffUL
);
3434 tcg_gen_extu_i32_i64(tmp
, tmp32_1
);
3436 tcg_temp_free_i32(tmp32_1
);
3437 tcg_temp_free_i64(tmp
);
3439 case 0x18: /* AGFR R1,R2 [RRE] */
3440 case 0x1a: /* ALGFR R1,R2 [RRE] */
3441 tmp32_1
= load_reg32(r2
);
3442 tmp2
= tcg_temp_new_i64();
3444 tcg_gen_ext_i32_i64(tmp2
, tmp32_1
);
3446 tcg_gen_extu_i32_i64(tmp2
, tmp32_1
);
3448 tcg_temp_free_i32(tmp32_1
);
3450 tmp3
= tcg_temp_new_i64();
3451 tcg_gen_add_i64(tmp3
, tmp
, tmp2
);
3452 store_reg(r1
, tmp3
);
3454 set_cc_add64(s
, tmp
, tmp2
, tmp3
);
3456 set_cc_addu64(s
, tmp
, tmp2
, tmp3
);
3458 tcg_temp_free_i64(tmp
);
3459 tcg_temp_free_i64(tmp2
);
3460 tcg_temp_free_i64(tmp3
);
3462 case 0x1f: /* LRVR R1,R2 [RRE] */
3463 tmp32_1
= load_reg32(r2
);
3464 tcg_gen_bswap32_i32(tmp32_1
, tmp32_1
);
3465 store_reg32(r1
, tmp32_1
);
3466 tcg_temp_free_i32(tmp32_1
);
3468 case 0x20: /* CGR R1,R2 [RRE] */
3469 case 0x30: /* CGFR R1,R2 [RRE] */
3470 tmp2
= load_reg(r2
);
3472 tcg_gen_ext32s_i64(tmp2
, tmp2
);
3475 cmp_s64(s
, tmp
, tmp2
);
3476 tcg_temp_free_i64(tmp
);
3477 tcg_temp_free_i64(tmp2
);
3479 case 0x21: /* CLGR R1,R2 [RRE] */
3480 case 0x31: /* CLGFR R1,R2 [RRE] */
3481 tmp2
= load_reg(r2
);
3483 tcg_gen_ext32u_i64(tmp2
, tmp2
);
3486 cmp_u64(s
, tmp
, tmp2
);
3487 tcg_temp_free_i64(tmp
);
3488 tcg_temp_free_i64(tmp2
);
3490 case 0x26: /* LBR R1,R2 [RRE] */
3491 tmp32_1
= load_reg32(r2
);
3492 tcg_gen_ext8s_i32(tmp32_1
, tmp32_1
);
3493 store_reg32(r1
, tmp32_1
);
3494 tcg_temp_free_i32(tmp32_1
);
3496 case 0x27: /* LHR R1,R2 [RRE] */
3497 tmp32_1
= load_reg32(r2
);
3498 tcg_gen_ext16s_i32(tmp32_1
, tmp32_1
);
3499 store_reg32(r1
, tmp32_1
);
3500 tcg_temp_free_i32(tmp32_1
);
3502 case 0x80: /* NGR R1,R2 [RRE] */
3503 case 0x81: /* OGR R1,R2 [RRE] */
3504 case 0x82: /* XGR R1,R2 [RRE] */
3506 tmp2
= load_reg(r2
);
3509 tcg_gen_and_i64(tmp
, tmp
, tmp2
);
3512 tcg_gen_or_i64(tmp
, tmp
, tmp2
);
3515 tcg_gen_xor_i64(tmp
, tmp
, tmp2
);
3521 set_cc_nz_u64(s
, tmp
);
3522 tcg_temp_free_i64(tmp
);
3523 tcg_temp_free_i64(tmp2
);
3525 case 0x83: /* FLOGR R1,R2 [RRE] */
3527 tmp32_1
= tcg_const_i32(r1
);
3528 gen_helper_flogr(cc_op
, tmp32_1
, tmp
);
3530 tcg_temp_free_i64(tmp
);
3531 tcg_temp_free_i32(tmp32_1
);
3533 case 0x84: /* LLGCR R1,R2 [RRE] */
3535 tcg_gen_andi_i64(tmp
, tmp
, 0xff);
3537 tcg_temp_free_i64(tmp
);
3539 case 0x85: /* LLGHR R1,R2 [RRE] */
3541 tcg_gen_andi_i64(tmp
, tmp
, 0xffff);
3543 tcg_temp_free_i64(tmp
);
3545 case 0x87: /* DLGR R1,R2 [RRE] */
3546 tmp32_1
= tcg_const_i32(r1
);
3548 gen_helper_dlg(tmp32_1
, tmp
);
3549 tcg_temp_free_i64(tmp
);
3550 tcg_temp_free_i32(tmp32_1
);
3552 case 0x88: /* ALCGR R1,R2 [RRE] */
3554 tmp2
= load_reg(r2
);
3555 tmp3
= tcg_temp_new_i64();
3557 tcg_gen_extu_i32_i64(tmp3
, cc_op
);
3558 tcg_gen_shri_i64(tmp3
, tmp3
, 1);
3559 tcg_gen_andi_i64(tmp3
, tmp3
, 1);
3560 tcg_gen_add_i64(tmp3
, tmp2
, tmp3
);
3561 tcg_gen_add_i64(tmp3
, tmp
, tmp3
);
3562 store_reg(r1
, tmp3
);
3563 set_cc_addu64(s
, tmp
, tmp2
, tmp3
);
3564 tcg_temp_free_i64(tmp
);
3565 tcg_temp_free_i64(tmp2
);
3566 tcg_temp_free_i64(tmp3
);
3568 case 0x89: /* SLBGR R1,R2 [RRE] */
3570 tmp2
= load_reg(r2
);
3571 tmp32_1
= tcg_const_i32(r1
);
3573 gen_helper_slbg(cc_op
, cc_op
, tmp32_1
, tmp
, tmp2
);
3575 tcg_temp_free_i64(tmp
);
3576 tcg_temp_free_i64(tmp2
);
3577 tcg_temp_free_i32(tmp32_1
);
3579 case 0x94: /* LLCR R1,R2 [RRE] */
3580 tmp32_1
= load_reg32(r2
);
3581 tcg_gen_andi_i32(tmp32_1
, tmp32_1
, 0xff);
3582 store_reg32(r1
, tmp32_1
);
3583 tcg_temp_free_i32(tmp32_1
);
3585 case 0x95: /* LLHR R1,R2 [RRE] */
3586 tmp32_1
= load_reg32(r2
);
3587 tcg_gen_andi_i32(tmp32_1
, tmp32_1
, 0xffff);
3588 store_reg32(r1
, tmp32_1
);
3589 tcg_temp_free_i32(tmp32_1
);
3591 case 0x96: /* MLR R1,R2 [RRE] */
3592 /* reg(r1, r1+1) = reg(r1+1) * reg(r2) */
3593 tmp2
= load_reg(r2
);
3594 tmp3
= load_reg((r1
+ 1) & 15);
3595 tcg_gen_ext32u_i64(tmp2
, tmp2
);
3596 tcg_gen_ext32u_i64(tmp3
, tmp3
);
3597 tcg_gen_mul_i64(tmp2
, tmp2
, tmp3
);
3598 store_reg32_i64((r1
+ 1) & 15, tmp2
);
3599 tcg_gen_shri_i64(tmp2
, tmp2
, 32);
3600 store_reg32_i64(r1
, tmp2
);
3601 tcg_temp_free_i64(tmp2
);
3602 tcg_temp_free_i64(tmp3
);
3604 case 0x97: /* DLR R1,R2 [RRE] */
3605 /* reg(r1) = reg(r1, r1+1) % reg(r2) */
3606 /* reg(r1+1) = reg(r1, r1+1) / reg(r2) */
3608 tmp2
= load_reg(r2
);
3609 tmp3
= load_reg((r1
+ 1) & 15);
3610 tcg_gen_ext32u_i64(tmp2
, tmp2
);
3611 tcg_gen_ext32u_i64(tmp3
, tmp3
);
3612 tcg_gen_shli_i64(tmp
, tmp
, 32);
3613 tcg_gen_or_i64(tmp
, tmp
, tmp3
);
3615 tcg_gen_rem_i64(tmp3
, tmp
, tmp2
);
3616 tcg_gen_div_i64(tmp
, tmp
, tmp2
);
3617 store_reg32_i64((r1
+ 1) & 15, tmp
);
3618 store_reg32_i64(r1
, tmp3
);
3619 tcg_temp_free_i64(tmp
);
3620 tcg_temp_free_i64(tmp2
);
3621 tcg_temp_free_i64(tmp3
);
3623 case 0x98: /* ALCR R1,R2 [RRE] */
3624 tmp32_1
= load_reg32(r1
);
3625 tmp32_2
= load_reg32(r2
);
3626 tmp32_3
= tcg_temp_new_i32();
3627 /* XXX possible optimization point */
3629 gen_helper_addc_u32(tmp32_3
, cc_op
, tmp32_1
, tmp32_2
);
3630 set_cc_addu32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
3631 store_reg32(r1
, tmp32_3
);
3632 tcg_temp_free_i32(tmp32_1
);
3633 tcg_temp_free_i32(tmp32_2
);
3634 tcg_temp_free_i32(tmp32_3
);
3636 case 0x99: /* SLBR R1,R2 [RRE] */
3637 tmp32_1
= load_reg32(r2
);
3638 tmp32_2
= tcg_const_i32(r1
);
3640 gen_helper_slb(cc_op
, cc_op
, tmp32_2
, tmp32_1
);
3642 tcg_temp_free_i32(tmp32_1
);
3643 tcg_temp_free_i32(tmp32_2
);
3646 LOG_DISAS("illegal b9 operation 0x%x\n", op
);
3647 gen_illegal_opcode(s
, 2);
3652 static void disas_c0(DisasContext
*s
, int op
, int r1
, int i2
)
3655 TCGv_i32 tmp32_1
, tmp32_2
;
3656 uint64_t target
= s
->pc
+ i2
* 2LL;
3659 LOG_DISAS("disas_c0: op 0x%x r1 %d i2 %d\n", op
, r1
, i2
);
3662 case 0: /* larl r1, i2 */
3663 tmp
= tcg_const_i64(target
);
3665 tcg_temp_free_i64(tmp
);
3667 case 0x1: /* LGFI R1,I2 [RIL] */
3668 tmp
= tcg_const_i64((int64_t)i2
);
3670 tcg_temp_free_i64(tmp
);
3672 case 0x4: /* BRCL M1,I2 [RIL] */
3673 /* m1 & (1 << (3 - cc)) */
3674 tmp32_1
= tcg_const_i32(3);
3675 tmp32_2
= tcg_const_i32(1);
3677 tcg_gen_sub_i32(tmp32_1
, tmp32_1
, cc_op
);
3678 tcg_gen_shl_i32(tmp32_2
, tmp32_2
, tmp32_1
);
3679 tcg_temp_free_i32(tmp32_1
);
3680 tmp32_1
= tcg_const_i32(r1
); /* m1 == r1 */
3681 tcg_gen_and_i32(tmp32_1
, tmp32_1
, tmp32_2
);
3682 l1
= gen_new_label();
3683 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp32_1
, 0, l1
);
3684 gen_goto_tb(s
, 0, target
);
3686 gen_goto_tb(s
, 1, s
->pc
+ 6);
3687 s
->is_jmp
= DISAS_TB_JUMP
;
3688 tcg_temp_free_i32(tmp32_1
);
3689 tcg_temp_free_i32(tmp32_2
);
3691 case 0x5: /* brasl r1, i2 */
3692 tmp
= tcg_const_i64(pc_to_link_info(s
, s
->pc
+ 6));
3694 tcg_temp_free_i64(tmp
);
3695 gen_goto_tb(s
, 0, target
);
3696 s
->is_jmp
= DISAS_TB_JUMP
;
3698 case 0x7: /* XILF R1,I2 [RIL] */
3699 case 0xb: /* NILF R1,I2 [RIL] */
3700 case 0xd: /* OILF R1,I2 [RIL] */
3701 tmp32_1
= load_reg32(r1
);
3704 tcg_gen_xori_i32(tmp32_1
, tmp32_1
, (uint32_t)i2
);
3707 tcg_gen_andi_i32(tmp32_1
, tmp32_1
, (uint32_t)i2
);
3710 tcg_gen_ori_i32(tmp32_1
, tmp32_1
, (uint32_t)i2
);
3715 store_reg32(r1
, tmp32_1
);
3716 set_cc_nz_u32(s
, tmp32_1
);
3717 tcg_temp_free_i32(tmp32_1
);
3719 case 0x9: /* IILF R1,I2 [RIL] */
3720 tmp32_1
= tcg_const_i32((uint32_t)i2
);
3721 store_reg32(r1
, tmp32_1
);
3722 tcg_temp_free_i32(tmp32_1
);
3724 case 0xa: /* NIHF R1,I2 [RIL] */
3726 tmp32_1
= tcg_temp_new_i32();
3727 tcg_gen_andi_i64(tmp
, tmp
, (((uint64_t)((uint32_t)i2
)) << 32)
3730 tcg_gen_shri_i64(tmp
, tmp
, 32);
3731 tcg_gen_trunc_i64_i32(tmp32_1
, tmp
);
3732 set_cc_nz_u32(s
, tmp32_1
);
3733 tcg_temp_free_i64(tmp
);
3734 tcg_temp_free_i32(tmp32_1
);
3736 case 0xe: /* LLIHF R1,I2 [RIL] */
3737 tmp
= tcg_const_i64(((uint64_t)(uint32_t)i2
) << 32);
3739 tcg_temp_free_i64(tmp
);
3741 case 0xf: /* LLILF R1,I2 [RIL] */
3742 tmp
= tcg_const_i64((uint32_t)i2
);
3744 tcg_temp_free_i64(tmp
);
3747 LOG_DISAS("illegal c0 operation 0x%x\n", op
);
3748 gen_illegal_opcode(s
, 3);
3753 static void disas_c2(DisasContext
*s
, int op
, int r1
, int i2
)
3755 TCGv_i64 tmp
, tmp2
, tmp3
;
3756 TCGv_i32 tmp32_1
, tmp32_2
, tmp32_3
;
3759 case 0x4: /* SLGFI R1,I2 [RIL] */
3760 case 0xa: /* ALGFI R1,I2 [RIL] */
3762 tmp2
= tcg_const_i64((uint64_t)(uint32_t)i2
);
3763 tmp3
= tcg_temp_new_i64();
3766 tcg_gen_sub_i64(tmp3
, tmp
, tmp2
);
3767 set_cc_subu64(s
, tmp
, tmp2
, tmp3
);
3770 tcg_gen_add_i64(tmp3
, tmp
, tmp2
);
3771 set_cc_addu64(s
, tmp
, tmp2
, tmp3
);
3776 store_reg(r1
, tmp3
);
3777 tcg_temp_free_i64(tmp
);
3778 tcg_temp_free_i64(tmp2
);
3779 tcg_temp_free_i64(tmp3
);
3781 case 0x5: /* SLFI R1,I2 [RIL] */
3782 case 0xb: /* ALFI R1,I2 [RIL] */
3783 tmp32_1
= load_reg32(r1
);
3784 tmp32_2
= tcg_const_i32(i2
);
3785 tmp32_3
= tcg_temp_new_i32();
3788 tcg_gen_sub_i32(tmp32_3
, tmp32_1
, tmp32_2
);
3789 set_cc_subu32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
3792 tcg_gen_add_i32(tmp32_3
, tmp32_1
, tmp32_2
);
3793 set_cc_addu32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
3798 store_reg32(r1
, tmp32_3
);
3799 tcg_temp_free_i32(tmp32_1
);
3800 tcg_temp_free_i32(tmp32_2
);
3801 tcg_temp_free_i32(tmp32_3
);
3803 case 0xc: /* CGFI R1,I2 [RIL] */
3805 cmp_s64c(s
, tmp
, (int64_t)i2
);
3806 tcg_temp_free_i64(tmp
);
3808 case 0xe: /* CLGFI R1,I2 [RIL] */
3810 cmp_u64c(s
, tmp
, (uint64_t)(uint32_t)i2
);
3811 tcg_temp_free_i64(tmp
);
3813 case 0xd: /* CFI R1,I2 [RIL] */
3814 tmp32_1
= load_reg32(r1
);
3815 cmp_s32c(s
, tmp32_1
, i2
);
3816 tcg_temp_free_i32(tmp32_1
);
3818 case 0xf: /* CLFI R1,I2 [RIL] */
3819 tmp32_1
= load_reg32(r1
);
3820 cmp_u32c(s
, tmp32_1
, i2
);
3821 tcg_temp_free_i32(tmp32_1
);
3824 LOG_DISAS("illegal c2 operation 0x%x\n", op
);
3825 gen_illegal_opcode(s
, 3);
3830 static void gen_and_or_xor_i32(int opc
, TCGv_i32 tmp
, TCGv_i32 tmp2
)
3832 switch (opc
& 0xf) {
3834 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
3837 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
3840 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
3847 static void disas_s390_insn(DisasContext
*s
)
3849 TCGv_i64 tmp
, tmp2
, tmp3
, tmp4
;
3850 TCGv_i32 tmp32_1
, tmp32_2
, tmp32_3
, tmp32_4
;
3853 int op
, r1
, r2
, r3
, d1
, d2
, x2
, b1
, b2
, i
, i2
, r1b
;
3858 opc
= ldub_code(s
->pc
);
3859 LOG_DISAS("opc 0x%x\n", opc
);
3864 #ifndef CONFIG_USER_ONLY
3865 case 0x01: /* SAM */
3866 insn
= ld_code2(s
->pc
);
3867 /* set addressing mode, but we only do 64bit anyways */
3870 case 0x6: /* BCTR R1,R2 [RR] */
3871 insn
= ld_code2(s
->pc
);
3872 decode_rr(s
, insn
, &r1
, &r2
);
3873 tmp32_1
= load_reg32(r1
);
3874 tcg_gen_subi_i32(tmp32_1
, tmp32_1
, 1);
3875 store_reg32(r1
, tmp32_1
);
3878 gen_update_cc_op(s
);
3879 l1
= gen_new_label();
3880 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp32_1
, 0, l1
);
3882 /* not taking the branch, jump to after the instruction */
3883 gen_goto_tb(s
, 0, s
->pc
+ 2);
3886 /* take the branch, move R2 into psw.addr */
3887 tmp32_1
= load_reg32(r2
);
3888 tmp
= tcg_temp_new_i64();
3889 tcg_gen_extu_i32_i64(tmp
, tmp32_1
);
3890 tcg_gen_mov_i64(psw_addr
, tmp
);
3891 s
->is_jmp
= DISAS_JUMP
;
3892 tcg_temp_free_i32(tmp32_1
);
3893 tcg_temp_free_i64(tmp
);
3896 case 0x7: /* BCR M1,R2 [RR] */
3897 insn
= ld_code2(s
->pc
);
3898 decode_rr(s
, insn
, &r1
, &r2
);
3901 gen_bcr(s
, r1
, tmp
, s
->pc
);
3902 tcg_temp_free_i64(tmp
);
3903 s
->is_jmp
= DISAS_TB_JUMP
;
3905 /* XXX: "serialization and checkpoint-synchronization function"? */
3908 case 0xa: /* SVC I [RR] */
3909 insn
= ld_code2(s
->pc
);
3914 tmp32_1
= tcg_const_i32(i
);
3915 tmp32_2
= tcg_const_i32(ilc
* 2);
3916 tmp32_3
= tcg_const_i32(EXCP_SVC
);
3917 tcg_gen_st_i32(tmp32_1
, cpu_env
, offsetof(CPUState
, int_svc_code
));
3918 tcg_gen_st_i32(tmp32_2
, cpu_env
, offsetof(CPUState
, int_svc_ilc
));
3919 gen_helper_exception(tmp32_3
);
3920 s
->is_jmp
= DISAS_EXCP
;
3921 tcg_temp_free_i32(tmp32_1
);
3922 tcg_temp_free_i32(tmp32_2
);
3923 tcg_temp_free_i32(tmp32_3
);
3925 case 0xd: /* BASR R1,R2 [RR] */
3926 insn
= ld_code2(s
->pc
);
3927 decode_rr(s
, insn
, &r1
, &r2
);
3928 tmp
= tcg_const_i64(pc_to_link_info(s
, s
->pc
+ 2));
3931 tmp2
= load_reg(r2
);
3932 tcg_gen_mov_i64(psw_addr
, tmp2
);
3933 tcg_temp_free_i64(tmp2
);
3934 s
->is_jmp
= DISAS_JUMP
;
3936 tcg_temp_free_i64(tmp
);
3938 case 0xe: /* MVCL R1,R2 [RR] */
3939 insn
= ld_code2(s
->pc
);
3940 decode_rr(s
, insn
, &r1
, &r2
);
3941 tmp32_1
= tcg_const_i32(r1
);
3942 tmp32_2
= tcg_const_i32(r2
);
3943 potential_page_fault(s
);
3944 gen_helper_mvcl(cc_op
, tmp32_1
, tmp32_2
);
3946 tcg_temp_free_i32(tmp32_1
);
3947 tcg_temp_free_i32(tmp32_2
);
3949 case 0x10: /* LPR R1,R2 [RR] */
3950 insn
= ld_code2(s
->pc
);
3951 decode_rr(s
, insn
, &r1
, &r2
);
3952 tmp32_1
= load_reg32(r2
);
3953 set_cc_abs32(s
, tmp32_1
);
3954 gen_helper_abs_i32(tmp32_1
, tmp32_1
);
3955 store_reg32(r1
, tmp32_1
);
3956 tcg_temp_free_i32(tmp32_1
);
3958 case 0x11: /* LNR R1,R2 [RR] */
3959 insn
= ld_code2(s
->pc
);
3960 decode_rr(s
, insn
, &r1
, &r2
);
3961 tmp32_1
= load_reg32(r2
);
3962 set_cc_nabs32(s
, tmp32_1
);
3963 gen_helper_nabs_i32(tmp32_1
, tmp32_1
);
3964 store_reg32(r1
, tmp32_1
);
3965 tcg_temp_free_i32(tmp32_1
);
3967 case 0x12: /* LTR R1,R2 [RR] */
3968 insn
= ld_code2(s
->pc
);
3969 decode_rr(s
, insn
, &r1
, &r2
);
3970 tmp32_1
= load_reg32(r2
);
3972 store_reg32(r1
, tmp32_1
);
3974 set_cc_s32(s
, tmp32_1
);
3975 tcg_temp_free_i32(tmp32_1
);
3977 case 0x13: /* LCR R1,R2 [RR] */
3978 insn
= ld_code2(s
->pc
);
3979 decode_rr(s
, insn
, &r1
, &r2
);
3980 tmp32_1
= load_reg32(r2
);
3981 tcg_gen_neg_i32(tmp32_1
, tmp32_1
);
3982 store_reg32(r1
, tmp32_1
);
3983 set_cc_comp32(s
, tmp32_1
);
3984 tcg_temp_free_i32(tmp32_1
);
3986 case 0x14: /* NR R1,R2 [RR] */
3987 case 0x16: /* OR R1,R2 [RR] */
3988 case 0x17: /* XR R1,R2 [RR] */
3989 insn
= ld_code2(s
->pc
);
3990 decode_rr(s
, insn
, &r1
, &r2
);
3991 tmp32_2
= load_reg32(r2
);
3992 tmp32_1
= load_reg32(r1
);
3993 gen_and_or_xor_i32(opc
, tmp32_1
, tmp32_2
);
3994 store_reg32(r1
, tmp32_1
);
3995 set_cc_nz_u32(s
, tmp32_1
);
3996 tcg_temp_free_i32(tmp32_1
);
3997 tcg_temp_free_i32(tmp32_2
);
3999 case 0x18: /* LR R1,R2 [RR] */
4000 insn
= ld_code2(s
->pc
);
4001 decode_rr(s
, insn
, &r1
, &r2
);
4002 tmp32_1
= load_reg32(r2
);
4003 store_reg32(r1
, tmp32_1
);
4004 tcg_temp_free_i32(tmp32_1
);
4006 case 0x15: /* CLR R1,R2 [RR] */
4007 case 0x19: /* CR R1,R2 [RR] */
4008 insn
= ld_code2(s
->pc
);
4009 decode_rr(s
, insn
, &r1
, &r2
);
4010 tmp32_1
= load_reg32(r1
);
4011 tmp32_2
= load_reg32(r2
);
4013 cmp_u32(s
, tmp32_1
, tmp32_2
);
4015 cmp_s32(s
, tmp32_1
, tmp32_2
);
4017 tcg_temp_free_i32(tmp32_1
);
4018 tcg_temp_free_i32(tmp32_2
);
4020 case 0x1a: /* AR R1,R2 [RR] */
4021 case 0x1e: /* ALR R1,R2 [RR] */
4022 insn
= ld_code2(s
->pc
);
4023 decode_rr(s
, insn
, &r1
, &r2
);
4024 tmp32_1
= load_reg32(r1
);
4025 tmp32_2
= load_reg32(r2
);
4026 tmp32_3
= tcg_temp_new_i32();
4027 tcg_gen_add_i32(tmp32_3
, tmp32_1
, tmp32_2
);
4028 store_reg32(r1
, tmp32_3
);
4030 set_cc_add32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
4032 set_cc_addu32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
4034 tcg_temp_free_i32(tmp32_1
);
4035 tcg_temp_free_i32(tmp32_2
);
4036 tcg_temp_free_i32(tmp32_3
);
4038 case 0x1b: /* SR R1,R2 [RR] */
4039 case 0x1f: /* SLR R1,R2 [RR] */
4040 insn
= ld_code2(s
->pc
);
4041 decode_rr(s
, insn
, &r1
, &r2
);
4042 tmp32_1
= load_reg32(r1
);
4043 tmp32_2
= load_reg32(r2
);
4044 tmp32_3
= tcg_temp_new_i32();
4045 tcg_gen_sub_i32(tmp32_3
, tmp32_1
, tmp32_2
);
4046 store_reg32(r1
, tmp32_3
);
4048 set_cc_sub32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
4050 set_cc_subu32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
4052 tcg_temp_free_i32(tmp32_1
);
4053 tcg_temp_free_i32(tmp32_2
);
4054 tcg_temp_free_i32(tmp32_3
);
4056 case 0x1c: /* MR R1,R2 [RR] */
4057 /* reg(r1, r1+1) = reg(r1+1) * reg(r2) */
4058 insn
= ld_code2(s
->pc
);
4059 decode_rr(s
, insn
, &r1
, &r2
);
4060 tmp2
= load_reg(r2
);
4061 tmp3
= load_reg((r1
+ 1) & 15);
4062 tcg_gen_ext32s_i64(tmp2
, tmp2
);
4063 tcg_gen_ext32s_i64(tmp3
, tmp3
);
4064 tcg_gen_mul_i64(tmp2
, tmp2
, tmp3
);
4065 store_reg32_i64((r1
+ 1) & 15, tmp2
);
4066 tcg_gen_shri_i64(tmp2
, tmp2
, 32);
4067 store_reg32_i64(r1
, tmp2
);
4068 tcg_temp_free_i64(tmp2
);
4069 tcg_temp_free_i64(tmp3
);
4071 case 0x1d: /* DR R1,R2 [RR] */
4072 insn
= ld_code2(s
->pc
);
4073 decode_rr(s
, insn
, &r1
, &r2
);
4074 tmp32_1
= load_reg32(r1
);
4075 tmp32_2
= load_reg32(r1
+ 1);
4076 tmp32_3
= load_reg32(r2
);
4078 tmp
= tcg_temp_new_i64(); /* dividend */
4079 tmp2
= tcg_temp_new_i64(); /* divisor */
4080 tmp3
= tcg_temp_new_i64();
4082 /* dividend is r(r1 << 32) | r(r1 + 1) */
4083 tcg_gen_extu_i32_i64(tmp
, tmp32_1
);
4084 tcg_gen_extu_i32_i64(tmp2
, tmp32_2
);
4085 tcg_gen_shli_i64(tmp
, tmp
, 32);
4086 tcg_gen_or_i64(tmp
, tmp
, tmp2
);
4088 /* divisor is r(r2) */
4089 tcg_gen_ext_i32_i64(tmp2
, tmp32_3
);
4091 tcg_gen_div_i64(tmp3
, tmp
, tmp2
);
4092 tcg_gen_rem_i64(tmp
, tmp
, tmp2
);
4094 tcg_gen_trunc_i64_i32(tmp32_1
, tmp
);
4095 tcg_gen_trunc_i64_i32(tmp32_2
, tmp3
);
4097 store_reg32(r1
, tmp32_1
); /* remainder */
4098 store_reg32(r1
+ 1, tmp32_2
); /* quotient */
4099 tcg_temp_free_i32(tmp32_1
);
4100 tcg_temp_free_i32(tmp32_2
);
4101 tcg_temp_free_i32(tmp32_3
);
4102 tcg_temp_free_i64(tmp
);
4103 tcg_temp_free_i64(tmp2
);
4104 tcg_temp_free_i64(tmp3
);
4106 case 0x28: /* LDR R1,R2 [RR] */
4107 insn
= ld_code2(s
->pc
);
4108 decode_rr(s
, insn
, &r1
, &r2
);
4109 tmp
= load_freg(r2
);
4110 store_freg(r1
, tmp
);
4111 tcg_temp_free_i64(tmp
);
4113 case 0x38: /* LER R1,R2 [RR] */
4114 insn
= ld_code2(s
->pc
);
4115 decode_rr(s
, insn
, &r1
, &r2
);
4116 tmp32_1
= load_freg32(r2
);
4117 store_freg32(r1
, tmp32_1
);
4118 tcg_temp_free_i32(tmp32_1
);
4120 case 0x40: /* STH R1,D2(X2,B2) [RX] */
4121 insn
= ld_code4(s
->pc
);
4122 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4123 tmp2
= load_reg(r1
);
4124 tcg_gen_qemu_st16(tmp2
, tmp
, get_mem_index(s
));
4125 tcg_temp_free_i64(tmp
);
4126 tcg_temp_free_i64(tmp2
);
4129 insn
= ld_code4(s
->pc
);
4130 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4131 store_reg(r1
, tmp
); /* FIXME: 31/24-bit addressing */
4132 tcg_temp_free_i64(tmp
);
4134 case 0x42: /* STC R1,D2(X2,B2) [RX] */
4135 insn
= ld_code4(s
->pc
);
4136 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4137 tmp2
= load_reg(r1
);
4138 tcg_gen_qemu_st8(tmp2
, tmp
, get_mem_index(s
));
4139 tcg_temp_free_i64(tmp
);
4140 tcg_temp_free_i64(tmp2
);
4142 case 0x43: /* IC R1,D2(X2,B2) [RX] */
4143 insn
= ld_code4(s
->pc
);
4144 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4145 tmp2
= tcg_temp_new_i64();
4146 tcg_gen_qemu_ld8u(tmp2
, tmp
, get_mem_index(s
));
4147 store_reg8(r1
, tmp2
);
4148 tcg_temp_free_i64(tmp
);
4149 tcg_temp_free_i64(tmp2
);
4151 case 0x44: /* EX R1,D2(X2,B2) [RX] */
4152 insn
= ld_code4(s
->pc
);
4153 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4154 tmp2
= load_reg(r1
);
4155 tmp3
= tcg_const_i64(s
->pc
+ 4);
4158 gen_helper_ex(cc_op
, cc_op
, tmp2
, tmp
, tmp3
);
4160 tcg_temp_free_i64(tmp
);
4161 tcg_temp_free_i64(tmp2
);
4162 tcg_temp_free_i64(tmp3
);
4164 case 0x46: /* BCT R1,D2(X2,B2) [RX] */
4165 insn
= ld_code4(s
->pc
);
4166 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4167 tcg_temp_free_i64(tmp
);
4169 tmp32_1
= load_reg32(r1
);
4170 tcg_gen_subi_i32(tmp32_1
, tmp32_1
, 1);
4171 store_reg32(r1
, tmp32_1
);
4173 gen_update_cc_op(s
);
4174 l1
= gen_new_label();
4175 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp32_1
, 0, l1
);
4177 /* not taking the branch, jump to after the instruction */
4178 gen_goto_tb(s
, 0, s
->pc
+ 4);
4181 /* take the branch, move R2 into psw.addr */
4182 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4183 tcg_gen_mov_i64(psw_addr
, tmp
);
4184 s
->is_jmp
= DISAS_JUMP
;
4185 tcg_temp_free_i32(tmp32_1
);
4186 tcg_temp_free_i64(tmp
);
4188 case 0x47: /* BC M1,D2(X2,B2) [RX] */
4189 insn
= ld_code4(s
->pc
);
4190 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4191 gen_bcr(s
, r1
, tmp
, s
->pc
+ 4);
4192 tcg_temp_free_i64(tmp
);
4193 s
->is_jmp
= DISAS_TB_JUMP
;
4195 case 0x48: /* LH R1,D2(X2,B2) [RX] */
4196 insn
= ld_code4(s
->pc
);
4197 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4198 tmp2
= tcg_temp_new_i64();
4199 tcg_gen_qemu_ld16s(tmp2
, tmp
, get_mem_index(s
));
4200 store_reg32_i64(r1
, tmp2
);
4201 tcg_temp_free_i64(tmp
);
4202 tcg_temp_free_i64(tmp2
);
4204 case 0x49: /* CH R1,D2(X2,B2) [RX] */
4205 insn
= ld_code4(s
->pc
);
4206 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4207 tmp32_1
= load_reg32(r1
);
4208 tmp32_2
= tcg_temp_new_i32();
4209 tmp2
= tcg_temp_new_i64();
4210 tcg_gen_qemu_ld16s(tmp2
, tmp
, get_mem_index(s
));
4211 tcg_gen_trunc_i64_i32(tmp32_2
, tmp2
);
4212 cmp_s32(s
, tmp32_1
, tmp32_2
);
4213 tcg_temp_free_i32(tmp32_1
);
4214 tcg_temp_free_i32(tmp32_2
);
4215 tcg_temp_free_i64(tmp
);
4216 tcg_temp_free_i64(tmp2
);
4218 case 0x4a: /* AH R1,D2(X2,B2) [RX] */
4219 case 0x4b: /* SH R1,D2(X2,B2) [RX] */
4220 case 0x4c: /* MH R1,D2(X2,B2) [RX] */
4221 insn
= ld_code4(s
->pc
);
4222 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4223 tmp2
= tcg_temp_new_i64();
4224 tmp32_1
= load_reg32(r1
);
4225 tmp32_2
= tcg_temp_new_i32();
4226 tmp32_3
= tcg_temp_new_i32();
4228 tcg_gen_qemu_ld16s(tmp2
, tmp
, get_mem_index(s
));
4229 tcg_gen_trunc_i64_i32(tmp32_2
, tmp2
);
4232 tcg_gen_add_i32(tmp32_3
, tmp32_1
, tmp32_2
);
4233 set_cc_add32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
4236 tcg_gen_sub_i32(tmp32_3
, tmp32_1
, tmp32_2
);
4237 set_cc_sub32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
4240 tcg_gen_mul_i32(tmp32_3
, tmp32_1
, tmp32_2
);
4245 store_reg32(r1
, tmp32_3
);
4247 tcg_temp_free_i32(tmp32_1
);
4248 tcg_temp_free_i32(tmp32_2
);
4249 tcg_temp_free_i32(tmp32_3
);
4250 tcg_temp_free_i64(tmp
);
4251 tcg_temp_free_i64(tmp2
);
4253 case 0x4d: /* BAS R1,D2(X2,B2) [RX] */
4254 insn
= ld_code4(s
->pc
);
4255 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4256 tmp2
= tcg_const_i64(pc_to_link_info(s
, s
->pc
+ 4));
4257 store_reg(r1
, tmp2
);
4258 tcg_gen_mov_i64(psw_addr
, tmp
);
4259 tcg_temp_free_i64(tmp
);
4260 tcg_temp_free_i64(tmp2
);
4261 s
->is_jmp
= DISAS_JUMP
;
4263 case 0x4e: /* CVD R1,D2(X2,B2) [RX] */
4264 insn
= ld_code4(s
->pc
);
4265 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4266 tmp2
= tcg_temp_new_i64();
4267 tmp32_1
= tcg_temp_new_i32();
4268 tcg_gen_trunc_i64_i32(tmp32_1
, regs
[r1
]);
4269 gen_helper_cvd(tmp2
, tmp32_1
);
4270 tcg_gen_qemu_st64(tmp2
, tmp
, get_mem_index(s
));
4271 tcg_temp_free_i64(tmp
);
4272 tcg_temp_free_i64(tmp2
);
4273 tcg_temp_free_i32(tmp32_1
);
4275 case 0x50: /* st r1, d2(x2, b2) */
4276 insn
= ld_code4(s
->pc
);
4277 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4278 tmp2
= load_reg(r1
);
4279 tcg_gen_qemu_st32(tmp2
, tmp
, get_mem_index(s
));
4280 tcg_temp_free_i64(tmp
);
4281 tcg_temp_free_i64(tmp2
);
4283 case 0x55: /* CL R1,D2(X2,B2) [RX] */
4284 insn
= ld_code4(s
->pc
);
4285 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4286 tmp2
= tcg_temp_new_i64();
4287 tmp32_1
= tcg_temp_new_i32();
4288 tmp32_2
= load_reg32(r1
);
4289 tcg_gen_qemu_ld32u(tmp2
, tmp
, get_mem_index(s
));
4290 tcg_gen_trunc_i64_i32(tmp32_1
, tmp2
);
4291 cmp_u32(s
, tmp32_2
, tmp32_1
);
4292 tcg_temp_free_i64(tmp
);
4293 tcg_temp_free_i64(tmp2
);
4294 tcg_temp_free_i32(tmp32_1
);
4295 tcg_temp_free_i32(tmp32_2
);
4297 case 0x54: /* N R1,D2(X2,B2) [RX] */
4298 case 0x56: /* O R1,D2(X2,B2) [RX] */
4299 case 0x57: /* X R1,D2(X2,B2) [RX] */
4300 insn
= ld_code4(s
->pc
);
4301 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4302 tmp2
= tcg_temp_new_i64();
4303 tmp32_1
= load_reg32(r1
);
4304 tmp32_2
= tcg_temp_new_i32();
4305 tcg_gen_qemu_ld32u(tmp2
, tmp
, get_mem_index(s
));
4306 tcg_gen_trunc_i64_i32(tmp32_2
, tmp2
);
4307 gen_and_or_xor_i32(opc
, tmp32_1
, tmp32_2
);
4308 store_reg32(r1
, tmp32_1
);
4309 set_cc_nz_u32(s
, tmp32_1
);
4310 tcg_temp_free_i64(tmp
);
4311 tcg_temp_free_i64(tmp2
);
4312 tcg_temp_free_i32(tmp32_1
);
4313 tcg_temp_free_i32(tmp32_2
);
4315 case 0x58: /* l r1, d2(x2, b2) */
4316 insn
= ld_code4(s
->pc
);
4317 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4318 tmp2
= tcg_temp_new_i64();
4319 tmp32_1
= tcg_temp_new_i32();
4320 tcg_gen_qemu_ld32u(tmp2
, tmp
, get_mem_index(s
));
4321 tcg_gen_trunc_i64_i32(tmp32_1
, tmp2
);
4322 store_reg32(r1
, tmp32_1
);
4323 tcg_temp_free_i64(tmp
);
4324 tcg_temp_free_i64(tmp2
);
4325 tcg_temp_free_i32(tmp32_1
);
4327 case 0x59: /* C R1,D2(X2,B2) [RX] */
4328 insn
= ld_code4(s
->pc
);
4329 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4330 tmp2
= tcg_temp_new_i64();
4331 tmp32_1
= tcg_temp_new_i32();
4332 tmp32_2
= load_reg32(r1
);
4333 tcg_gen_qemu_ld32s(tmp2
, tmp
, get_mem_index(s
));
4334 tcg_gen_trunc_i64_i32(tmp32_1
, tmp2
);
4335 cmp_s32(s
, tmp32_2
, tmp32_1
);
4336 tcg_temp_free_i64(tmp
);
4337 tcg_temp_free_i64(tmp2
);
4338 tcg_temp_free_i32(tmp32_1
);
4339 tcg_temp_free_i32(tmp32_2
);
4341 case 0x5a: /* A R1,D2(X2,B2) [RX] */
4342 case 0x5b: /* S R1,D2(X2,B2) [RX] */
4343 case 0x5e: /* AL R1,D2(X2,B2) [RX] */
4344 case 0x5f: /* SL R1,D2(X2,B2) [RX] */
4345 insn
= ld_code4(s
->pc
);
4346 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4347 tmp32_1
= load_reg32(r1
);
4348 tmp32_2
= tcg_temp_new_i32();
4349 tmp32_3
= tcg_temp_new_i32();
4350 tcg_gen_qemu_ld32s(tmp
, tmp
, get_mem_index(s
));
4351 tcg_gen_trunc_i64_i32(tmp32_2
, tmp
);
4355 tcg_gen_add_i32(tmp32_3
, tmp32_1
, tmp32_2
);
4359 tcg_gen_sub_i32(tmp32_3
, tmp32_1
, tmp32_2
);
4364 store_reg32(r1
, tmp32_3
);
4367 set_cc_add32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
4370 set_cc_addu32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
4373 set_cc_sub32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
4376 set_cc_subu32(s
, tmp32_1
, tmp32_2
, tmp32_3
);
4381 tcg_temp_free_i64(tmp
);
4382 tcg_temp_free_i32(tmp32_1
);
4383 tcg_temp_free_i32(tmp32_2
);
4384 tcg_temp_free_i32(tmp32_3
);
4386 case 0x5c: /* M R1,D2(X2,B2) [RX] */
4387 /* reg(r1, r1+1) = reg(r1+1) * *(s32*)addr */
4388 insn
= ld_code4(s
->pc
);
4389 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4390 tmp2
= tcg_temp_new_i64();
4391 tcg_gen_qemu_ld32s(tmp2
, tmp
, get_mem_index(s
));
4392 tmp3
= load_reg((r1
+ 1) & 15);
4393 tcg_gen_ext32s_i64(tmp2
, tmp2
);
4394 tcg_gen_ext32s_i64(tmp3
, tmp3
);
4395 tcg_gen_mul_i64(tmp2
, tmp2
, tmp3
);
4396 store_reg32_i64((r1
+ 1) & 15, tmp2
);
4397 tcg_gen_shri_i64(tmp2
, tmp2
, 32);
4398 store_reg32_i64(r1
, tmp2
);
4399 tcg_temp_free_i64(tmp
);
4400 tcg_temp_free_i64(tmp2
);
4401 tcg_temp_free_i64(tmp3
);
4403 case 0x5d: /* D R1,D2(X2,B2) [RX] */
4404 insn
= ld_code4(s
->pc
);
4405 tmp3
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4406 tmp32_1
= load_reg32(r1
);
4407 tmp32_2
= load_reg32(r1
+ 1);
4409 tmp
= tcg_temp_new_i64();
4410 tmp2
= tcg_temp_new_i64();
4412 /* dividend is r(r1 << 32) | r(r1 + 1) */
4413 tcg_gen_extu_i32_i64(tmp
, tmp32_1
);
4414 tcg_gen_extu_i32_i64(tmp2
, tmp32_2
);
4415 tcg_gen_shli_i64(tmp
, tmp
, 32);
4416 tcg_gen_or_i64(tmp
, tmp
, tmp2
);
4418 /* divisor is in memory */
4419 tcg_gen_qemu_ld32s(tmp2
, tmp3
, get_mem_index(s
));
4421 /* XXX divisor == 0 -> FixP divide exception */
4423 tcg_gen_div_i64(tmp3
, tmp
, tmp2
);
4424 tcg_gen_rem_i64(tmp
, tmp
, tmp2
);
4426 tcg_gen_trunc_i64_i32(tmp32_1
, tmp
);
4427 tcg_gen_trunc_i64_i32(tmp32_2
, tmp3
);
4429 store_reg32(r1
, tmp32_1
); /* remainder */
4430 store_reg32(r1
+ 1, tmp32_2
); /* quotient */
4431 tcg_temp_free_i32(tmp32_1
);
4432 tcg_temp_free_i32(tmp32_2
);
4433 tcg_temp_free_i64(tmp
);
4434 tcg_temp_free_i64(tmp2
);
4435 tcg_temp_free_i64(tmp3
);
4437 case 0x60: /* STD R1,D2(X2,B2) [RX] */
4438 insn
= ld_code4(s
->pc
);
4439 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4440 tmp2
= load_freg(r1
);
4441 tcg_gen_qemu_st64(tmp2
, tmp
, get_mem_index(s
));
4442 tcg_temp_free_i64(tmp
);
4443 tcg_temp_free_i64(tmp2
);
4445 case 0x68: /* LD R1,D2(X2,B2) [RX] */
4446 insn
= ld_code4(s
->pc
);
4447 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4448 tmp2
= tcg_temp_new_i64();
4449 tcg_gen_qemu_ld64(tmp2
, tmp
, get_mem_index(s
));
4450 store_freg(r1
, tmp2
);
4451 tcg_temp_free_i64(tmp
);
4452 tcg_temp_free_i64(tmp2
);
4454 case 0x70: /* STE R1,D2(X2,B2) [RX] */
4455 insn
= ld_code4(s
->pc
);
4456 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4457 tmp2
= tcg_temp_new_i64();
4458 tmp32_1
= load_freg32(r1
);
4459 tcg_gen_extu_i32_i64(tmp2
, tmp32_1
);
4460 tcg_gen_qemu_st32(tmp2
, tmp
, get_mem_index(s
));
4461 tcg_temp_free_i64(tmp
);
4462 tcg_temp_free_i64(tmp2
);
4463 tcg_temp_free_i32(tmp32_1
);
4465 case 0x71: /* MS R1,D2(X2,B2) [RX] */
4466 insn
= ld_code4(s
->pc
);
4467 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4468 tmp2
= tcg_temp_new_i64();
4469 tmp32_1
= load_reg32(r1
);
4470 tmp32_2
= tcg_temp_new_i32();
4471 tcg_gen_qemu_ld32s(tmp2
, tmp
, get_mem_index(s
));
4472 tcg_gen_trunc_i64_i32(tmp32_2
, tmp2
);
4473 tcg_gen_mul_i32(tmp32_1
, tmp32_1
, tmp32_2
);
4474 store_reg32(r1
, tmp32_1
);
4475 tcg_temp_free_i64(tmp
);
4476 tcg_temp_free_i64(tmp2
);
4477 tcg_temp_free_i32(tmp32_1
);
4478 tcg_temp_free_i32(tmp32_2
);
4480 case 0x78: /* LE R1,D2(X2,B2) [RX] */
4481 insn
= ld_code4(s
->pc
);
4482 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4483 tmp2
= tcg_temp_new_i64();
4484 tmp32_1
= tcg_temp_new_i32();
4485 tcg_gen_qemu_ld32u(tmp2
, tmp
, get_mem_index(s
));
4486 tcg_gen_trunc_i64_i32(tmp32_1
, tmp2
);
4487 store_freg32(r1
, tmp32_1
);
4488 tcg_temp_free_i64(tmp
);
4489 tcg_temp_free_i64(tmp2
);
4490 tcg_temp_free_i32(tmp32_1
);
4492 #ifndef CONFIG_USER_ONLY
4493 case 0x80: /* SSM D2(B2) [S] */
4494 /* Set System Mask */
4495 check_privileged(s
, ilc
);
4496 insn
= ld_code4(s
->pc
);
4497 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4498 tmp
= get_address(s
, 0, b2
, d2
);
4499 tmp2
= tcg_temp_new_i64();
4500 tmp3
= tcg_temp_new_i64();
4501 tcg_gen_andi_i64(tmp3
, psw_mask
, ~0xff00000000000000ULL
);
4502 tcg_gen_qemu_ld8u(tmp2
, tmp
, get_mem_index(s
));
4503 tcg_gen_shli_i64(tmp2
, tmp2
, 56);
4504 tcg_gen_or_i64(psw_mask
, tmp3
, tmp2
);
4505 tcg_temp_free_i64(tmp
);
4506 tcg_temp_free_i64(tmp2
);
4507 tcg_temp_free_i64(tmp3
);
4509 case 0x82: /* LPSW D2(B2) [S] */
4511 check_privileged(s
, ilc
);
4512 insn
= ld_code4(s
->pc
);
4513 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4514 tmp
= get_address(s
, 0, b2
, d2
);
4515 tmp2
= tcg_temp_new_i64();
4516 tmp3
= tcg_temp_new_i64();
4517 tcg_gen_qemu_ld32u(tmp2
, tmp
, get_mem_index(s
));
4518 tcg_gen_addi_i64(tmp
, tmp
, 4);
4519 tcg_gen_qemu_ld32u(tmp3
, tmp
, get_mem_index(s
));
4520 gen_helper_load_psw(tmp2
, tmp3
);
4521 tcg_temp_free_i64(tmp
);
4522 tcg_temp_free_i64(tmp2
);
4523 tcg_temp_free_i64(tmp3
);
4524 /* we need to keep cc_op intact */
4525 s
->is_jmp
= DISAS_JUMP
;
4527 case 0x83: /* DIAG R1,R3,D2 [RS] */
4528 /* Diagnose call (KVM hypercall) */
4529 check_privileged(s
, ilc
);
4530 potential_page_fault(s
);
4531 insn
= ld_code4(s
->pc
);
4532 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4533 tmp32_1
= tcg_const_i32(insn
& 0xfff);
4536 gen_helper_diag(tmp2
, tmp32_1
, tmp2
, tmp3
);
4538 tcg_temp_free_i32(tmp32_1
);
4539 tcg_temp_free_i64(tmp2
);
4540 tcg_temp_free_i64(tmp3
);
4543 case 0x88: /* SRL R1,D2(B2) [RS] */
4544 case 0x89: /* SLL R1,D2(B2) [RS] */
4545 case 0x8a: /* SRA R1,D2(B2) [RS] */
4546 insn
= ld_code4(s
->pc
);
4547 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4548 tmp
= get_address(s
, 0, b2
, d2
);
4549 tmp32_1
= load_reg32(r1
);
4550 tmp32_2
= tcg_temp_new_i32();
4551 tcg_gen_trunc_i64_i32(tmp32_2
, tmp
);
4552 tcg_gen_andi_i32(tmp32_2
, tmp32_2
, 0x3f);
4555 tcg_gen_shr_i32(tmp32_1
, tmp32_1
, tmp32_2
);
4558 tcg_gen_shl_i32(tmp32_1
, tmp32_1
, tmp32_2
);
4561 tcg_gen_sar_i32(tmp32_1
, tmp32_1
, tmp32_2
);
4562 set_cc_s32(s
, tmp32_1
);
4567 store_reg32(r1
, tmp32_1
);
4568 tcg_temp_free_i64(tmp
);
4569 tcg_temp_free_i32(tmp32_1
);
4570 tcg_temp_free_i32(tmp32_2
);
4572 case 0x8c: /* SRDL R1,D2(B2) [RS] */
4573 case 0x8d: /* SLDL R1,D2(B2) [RS] */
4574 case 0x8e: /* SRDA R1,D2(B2) [RS] */
4575 insn
= ld_code4(s
->pc
);
4576 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4577 tmp
= get_address(s
, 0, b2
, d2
); /* shift */
4578 tmp2
= tcg_temp_new_i64();
4579 tmp32_1
= load_reg32(r1
);
4580 tmp32_2
= load_reg32(r1
+ 1);
4581 tcg_gen_concat_i32_i64(tmp2
, tmp32_2
, tmp32_1
); /* operand */
4584 tcg_gen_shr_i64(tmp2
, tmp2
, tmp
);
4587 tcg_gen_shl_i64(tmp2
, tmp2
, tmp
);
4590 tcg_gen_sar_i64(tmp2
, tmp2
, tmp
);
4591 set_cc_s64(s
, tmp2
);
4594 tcg_gen_shri_i64(tmp
, tmp2
, 32);
4595 tcg_gen_trunc_i64_i32(tmp32_1
, tmp
);
4596 store_reg32(r1
, tmp32_1
);
4597 tcg_gen_trunc_i64_i32(tmp32_2
, tmp2
);
4598 store_reg32(r1
+ 1, tmp32_2
);
4600 case 0x98: /* LM R1,R3,D2(B2) [RS] */
4601 case 0x90: /* STM R1,R3,D2(B2) [RS] */
4602 insn
= ld_code4(s
->pc
);
4603 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4605 tmp
= get_address(s
, 0, b2
, d2
);
4606 tmp2
= tcg_temp_new_i64();
4607 tmp3
= tcg_const_i64(4);
4608 tmp4
= tcg_const_i64(0xffffffff00000000ULL
);
4609 for (i
= r1
;; i
= (i
+ 1) % 16) {
4611 tcg_gen_qemu_ld32u(tmp2
, tmp
, get_mem_index(s
));
4612 tcg_gen_and_i64(regs
[i
], regs
[i
], tmp4
);
4613 tcg_gen_or_i64(regs
[i
], regs
[i
], tmp2
);
4615 tcg_gen_qemu_st32(regs
[i
], tmp
, get_mem_index(s
));
4620 tcg_gen_add_i64(tmp
, tmp
, tmp3
);
4622 tcg_temp_free_i64(tmp2
);
4623 tcg_temp_free_i64(tmp3
);
4624 tcg_temp_free_i64(tmp4
);
4626 case 0x91: /* TM D1(B1),I2 [SI] */
4627 insn
= ld_code4(s
->pc
);
4628 tmp
= decode_si(s
, insn
, &i2
, &b1
, &d1
);
4629 tmp2
= tcg_const_i64(i2
);
4630 tcg_gen_qemu_ld8u(tmp
, tmp
, get_mem_index(s
));
4631 cmp_64(s
, tmp
, tmp2
, CC_OP_TM_32
);
4632 tcg_temp_free_i64(tmp
);
4633 tcg_temp_free_i64(tmp2
);
4635 case 0x92: /* MVI D1(B1),I2 [SI] */
4636 insn
= ld_code4(s
->pc
);
4637 tmp
= decode_si(s
, insn
, &i2
, &b1
, &d1
);
4638 tmp2
= tcg_const_i64(i2
);
4639 tcg_gen_qemu_st8(tmp2
, tmp
, get_mem_index(s
));
4640 tcg_temp_free_i64(tmp
);
4641 tcg_temp_free_i64(tmp2
);
4643 case 0x94: /* NI D1(B1),I2 [SI] */
4644 case 0x96: /* OI D1(B1),I2 [SI] */
4645 case 0x97: /* XI D1(B1),I2 [SI] */
4646 insn
= ld_code4(s
->pc
);
4647 tmp
= decode_si(s
, insn
, &i2
, &b1
, &d1
);
4648 tmp2
= tcg_temp_new_i64();
4649 tcg_gen_qemu_ld8u(tmp2
, tmp
, get_mem_index(s
));
4652 tcg_gen_andi_i64(tmp2
, tmp2
, i2
);
4655 tcg_gen_ori_i64(tmp2
, tmp2
, i2
);
4658 tcg_gen_xori_i64(tmp2
, tmp2
, i2
);
4663 tcg_gen_qemu_st8(tmp2
, tmp
, get_mem_index(s
));
4664 set_cc_nz_u64(s
, tmp2
);
4665 tcg_temp_free_i64(tmp
);
4666 tcg_temp_free_i64(tmp2
);
4668 case 0x95: /* CLI D1(B1),I2 [SI] */
4669 insn
= ld_code4(s
->pc
);
4670 tmp
= decode_si(s
, insn
, &i2
, &b1
, &d1
);
4671 tmp2
= tcg_temp_new_i64();
4672 tcg_gen_qemu_ld8u(tmp2
, tmp
, get_mem_index(s
));
4673 cmp_u64c(s
, tmp2
, i2
);
4674 tcg_temp_free_i64(tmp
);
4675 tcg_temp_free_i64(tmp2
);
4677 case 0x9a: /* LAM R1,R3,D2(B2) [RS] */
4678 insn
= ld_code4(s
->pc
);
4679 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4680 tmp
= get_address(s
, 0, b2
, d2
);
4681 tmp32_1
= tcg_const_i32(r1
);
4682 tmp32_2
= tcg_const_i32(r3
);
4683 potential_page_fault(s
);
4684 gen_helper_lam(tmp32_1
, tmp
, tmp32_2
);
4685 tcg_temp_free_i64(tmp
);
4686 tcg_temp_free_i32(tmp32_1
);
4687 tcg_temp_free_i32(tmp32_2
);
4689 case 0x9b: /* STAM R1,R3,D2(B2) [RS] */
4690 insn
= ld_code4(s
->pc
);
4691 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4692 tmp
= get_address(s
, 0, b2
, d2
);
4693 tmp32_1
= tcg_const_i32(r1
);
4694 tmp32_2
= tcg_const_i32(r3
);
4695 potential_page_fault(s
);
4696 gen_helper_stam(tmp32_1
, tmp
, tmp32_2
);
4697 tcg_temp_free_i64(tmp
);
4698 tcg_temp_free_i32(tmp32_1
);
4699 tcg_temp_free_i32(tmp32_2
);
4702 insn
= ld_code4(s
->pc
);
4703 r1
= (insn
>> 20) & 0xf;
4704 op
= (insn
>> 16) & 0xf;
4706 disas_a5(s
, op
, r1
, i2
);
4709 insn
= ld_code4(s
->pc
);
4710 r1
= (insn
>> 20) & 0xf;
4711 op
= (insn
>> 16) & 0xf;
4713 disas_a7(s
, op
, r1
, i2
);
4715 case 0xa8: /* MVCLE R1,R3,D2(B2) [RS] */
4716 insn
= ld_code4(s
->pc
);
4717 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4718 tmp
= get_address(s
, 0, b2
, d2
);
4719 tmp32_1
= tcg_const_i32(r1
);
4720 tmp32_2
= tcg_const_i32(r3
);
4721 potential_page_fault(s
);
4722 gen_helper_mvcle(cc_op
, tmp32_1
, tmp
, tmp32_2
);
4724 tcg_temp_free_i64(tmp
);
4725 tcg_temp_free_i32(tmp32_1
);
4726 tcg_temp_free_i32(tmp32_2
);
4728 case 0xa9: /* CLCLE R1,R3,D2(B2) [RS] */
4729 insn
= ld_code4(s
->pc
);
4730 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4731 tmp
= get_address(s
, 0, b2
, d2
);
4732 tmp32_1
= tcg_const_i32(r1
);
4733 tmp32_2
= tcg_const_i32(r3
);
4734 potential_page_fault(s
);
4735 gen_helper_clcle(cc_op
, tmp32_1
, tmp
, tmp32_2
);
4737 tcg_temp_free_i64(tmp
);
4738 tcg_temp_free_i32(tmp32_1
);
4739 tcg_temp_free_i32(tmp32_2
);
4741 #ifndef CONFIG_USER_ONLY
4742 case 0xac: /* STNSM D1(B1),I2 [SI] */
4743 case 0xad: /* STOSM D1(B1),I2 [SI] */
4744 check_privileged(s
, ilc
);
4745 insn
= ld_code4(s
->pc
);
4746 tmp
= decode_si(s
, insn
, &i2
, &b1
, &d1
);
4747 tmp2
= tcg_temp_new_i64();
4748 tcg_gen_shri_i64(tmp2
, psw_mask
, 56);
4749 tcg_gen_qemu_st8(tmp2
, tmp
, get_mem_index(s
));
4751 tcg_gen_andi_i64(psw_mask
, psw_mask
,
4752 ((uint64_t)i2
<< 56) | 0x00ffffffffffffffULL
);
4754 tcg_gen_ori_i64(psw_mask
, psw_mask
, (uint64_t)i2
<< 56);
4756 tcg_temp_free_i64(tmp
);
4757 tcg_temp_free_i64(tmp2
);
4759 case 0xae: /* SIGP R1,R3,D2(B2) [RS] */
4760 check_privileged(s
, ilc
);
4761 insn
= ld_code4(s
->pc
);
4762 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4763 tmp
= get_address(s
, 0, b2
, d2
);
4764 tmp2
= load_reg(r3
);
4765 tmp32_1
= tcg_const_i32(r1
);
4766 potential_page_fault(s
);
4767 gen_helper_sigp(cc_op
, tmp
, tmp32_1
, tmp2
);
4769 tcg_temp_free_i64(tmp
);
4770 tcg_temp_free_i64(tmp2
);
4771 tcg_temp_free_i32(tmp32_1
);
4773 case 0xb1: /* LRA R1,D2(X2, B2) [RX] */
4774 check_privileged(s
, ilc
);
4775 insn
= ld_code4(s
->pc
);
4776 tmp
= decode_rx(s
, insn
, &r1
, &x2
, &b2
, &d2
);
4777 tmp32_1
= tcg_const_i32(r1
);
4778 potential_page_fault(s
);
4779 gen_helper_lra(cc_op
, tmp
, tmp32_1
);
4781 tcg_temp_free_i64(tmp
);
4782 tcg_temp_free_i32(tmp32_1
);
4786 insn
= ld_code4(s
->pc
);
4787 op
= (insn
>> 16) & 0xff;
4789 case 0x9c: /* STFPC D2(B2) [S] */
4791 b2
= (insn
>> 12) & 0xf;
4792 tmp32_1
= tcg_temp_new_i32();
4793 tmp
= tcg_temp_new_i64();
4794 tmp2
= get_address(s
, 0, b2
, d2
);
4795 tcg_gen_ld_i32(tmp32_1
, cpu_env
, offsetof(CPUState
, fpc
));
4796 tcg_gen_extu_i32_i64(tmp
, tmp32_1
);
4797 tcg_gen_qemu_st32(tmp
, tmp2
, get_mem_index(s
));
4798 tcg_temp_free_i32(tmp32_1
);
4799 tcg_temp_free_i64(tmp
);
4800 tcg_temp_free_i64(tmp2
);
4803 disas_b2(s
, op
, insn
);
4808 insn
= ld_code4(s
->pc
);
4809 op
= (insn
>> 16) & 0xff;
4810 r3
= (insn
>> 12) & 0xf; /* aka m3 */
4811 r1
= (insn
>> 4) & 0xf;
4813 disas_b3(s
, op
, r3
, r1
, r2
);
4815 #ifndef CONFIG_USER_ONLY
4816 case 0xb6: /* STCTL R1,R3,D2(B2) [RS] */
4818 check_privileged(s
, ilc
);
4819 insn
= ld_code4(s
->pc
);
4820 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4821 tmp
= get_address(s
, 0, b2
, d2
);
4822 tmp32_1
= tcg_const_i32(r1
);
4823 tmp32_2
= tcg_const_i32(r3
);
4824 potential_page_fault(s
);
4825 gen_helper_stctl(tmp32_1
, tmp
, tmp32_2
);
4826 tcg_temp_free_i64(tmp
);
4827 tcg_temp_free_i32(tmp32_1
);
4828 tcg_temp_free_i32(tmp32_2
);
4830 case 0xb7: /* LCTL R1,R3,D2(B2) [RS] */
4832 check_privileged(s
, ilc
);
4833 insn
= ld_code4(s
->pc
);
4834 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4835 tmp
= get_address(s
, 0, b2
, d2
);
4836 tmp32_1
= tcg_const_i32(r1
);
4837 tmp32_2
= tcg_const_i32(r3
);
4838 potential_page_fault(s
);
4839 gen_helper_lctl(tmp32_1
, tmp
, tmp32_2
);
4840 tcg_temp_free_i64(tmp
);
4841 tcg_temp_free_i32(tmp32_1
);
4842 tcg_temp_free_i32(tmp32_2
);
4846 insn
= ld_code4(s
->pc
);
4847 r1
= (insn
>> 4) & 0xf;
4849 op
= (insn
>> 16) & 0xff;
4850 disas_b9(s
, op
, r1
, r2
);
4852 case 0xba: /* CS R1,R3,D2(B2) [RS] */
4853 insn
= ld_code4(s
->pc
);
4854 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4855 tmp
= get_address(s
, 0, b2
, d2
);
4856 tmp32_1
= tcg_const_i32(r1
);
4857 tmp32_2
= tcg_const_i32(r3
);
4858 potential_page_fault(s
);
4859 gen_helper_cs(cc_op
, tmp32_1
, tmp
, tmp32_2
);
4861 tcg_temp_free_i64(tmp
);
4862 tcg_temp_free_i32(tmp32_1
);
4863 tcg_temp_free_i32(tmp32_2
);
4865 case 0xbd: /* CLM R1,M3,D2(B2) [RS] */
4866 insn
= ld_code4(s
->pc
);
4867 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4868 tmp
= get_address(s
, 0, b2
, d2
);
4869 tmp32_1
= load_reg32(r1
);
4870 tmp32_2
= tcg_const_i32(r3
);
4871 potential_page_fault(s
);
4872 gen_helper_clm(cc_op
, tmp32_1
, tmp32_2
, tmp
);
4874 tcg_temp_free_i64(tmp
);
4875 tcg_temp_free_i32(tmp32_1
);
4876 tcg_temp_free_i32(tmp32_2
);
4878 case 0xbe: /* STCM R1,M3,D2(B2) [RS] */
4879 insn
= ld_code4(s
->pc
);
4880 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4881 tmp
= get_address(s
, 0, b2
, d2
);
4882 tmp32_1
= load_reg32(r1
);
4883 tmp32_2
= tcg_const_i32(r3
);
4884 potential_page_fault(s
);
4885 gen_helper_stcm(tmp32_1
, tmp32_2
, tmp
);
4886 tcg_temp_free_i64(tmp
);
4887 tcg_temp_free_i32(tmp32_1
);
4888 tcg_temp_free_i32(tmp32_2
);
4890 case 0xbf: /* ICM R1,M3,D2(B2) [RS] */
4891 insn
= ld_code4(s
->pc
);
4892 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
4894 /* effectively a 32-bit load */
4895 tmp
= get_address(s
, 0, b2
, d2
);
4896 tmp32_1
= tcg_temp_new_i32();
4897 tmp32_2
= tcg_const_i32(r3
);
4898 tcg_gen_qemu_ld32u(tmp
, tmp
, get_mem_index(s
));
4899 store_reg32_i64(r1
, tmp
);
4900 tcg_gen_trunc_i64_i32(tmp32_1
, tmp
);
4901 set_cc_icm(s
, tmp32_2
, tmp32_1
);
4902 tcg_temp_free_i64(tmp
);
4903 tcg_temp_free_i32(tmp32_1
);
4904 tcg_temp_free_i32(tmp32_2
);
4906 uint32_t mask
= 0x00ffffffUL
;
4907 uint32_t shift
= 24;
4909 tmp
= get_address(s
, 0, b2
, d2
);
4910 tmp2
= tcg_temp_new_i64();
4911 tmp32_1
= load_reg32(r1
);
4912 tmp32_2
= tcg_temp_new_i32();
4913 tmp32_3
= tcg_const_i32(r3
);
4914 tmp32_4
= tcg_const_i32(0);
4917 tcg_gen_qemu_ld8u(tmp2
, tmp
, get_mem_index(s
));
4918 tcg_gen_trunc_i64_i32(tmp32_2
, tmp2
);
4920 tcg_gen_shli_i32(tmp32_2
, tmp32_2
, shift
);
4922 tcg_gen_andi_i32(tmp32_1
, tmp32_1
, mask
);
4923 tcg_gen_or_i32(tmp32_1
, tmp32_1
, tmp32_2
);
4924 tcg_gen_or_i32(tmp32_4
, tmp32_4
, tmp32_2
);
4925 tcg_gen_addi_i64(tmp
, tmp
, 1);
4927 m3
= (m3
<< 1) & 0xf;
4928 mask
= (mask
>> 8) | 0xff000000UL
;
4931 store_reg32(r1
, tmp32_1
);
4932 set_cc_icm(s
, tmp32_3
, tmp32_4
);
4933 tcg_temp_free_i64(tmp
);
4934 tcg_temp_free_i64(tmp2
);
4935 tcg_temp_free_i32(tmp32_1
);
4936 tcg_temp_free_i32(tmp32_2
);
4937 tcg_temp_free_i32(tmp32_3
);
4938 tcg_temp_free_i32(tmp32_4
);
4940 /* i.e. env->cc = 0 */
4941 gen_op_movi_cc(s
, 0);
4946 insn
= ld_code6(s
->pc
);
4947 r1
= (insn
>> 36) & 0xf;
4948 op
= (insn
>> 32) & 0xf;
4952 disas_c0(s
, op
, r1
, i2
);
4955 disas_c2(s
, op
, r1
, i2
);
4961 case 0xd2: /* MVC D1(L,B1),D2(B2) [SS] */
4962 case 0xd4: /* NC D1(L,B1),D2(B2) [SS] */
4963 case 0xd5: /* CLC D1(L,B1),D2(B2) [SS] */
4964 case 0xd6: /* OC D1(L,B1),D2(B2) [SS] */
4965 case 0xd7: /* XC D1(L,B1),D2(B2) [SS] */
4966 case 0xdc: /* TR D1(L,B1),D2(B2) [SS] */
4967 case 0xf3: /* UNPK D1(L1,B1),D2(L2,B2) [SS] */
4968 insn
= ld_code6(s
->pc
);
4969 vl
= tcg_const_i32((insn
>> 32) & 0xff);
4970 b1
= (insn
>> 28) & 0xf;
4971 b2
= (insn
>> 12) & 0xf;
4972 d1
= (insn
>> 16) & 0xfff;
4974 tmp
= get_address(s
, 0, b1
, d1
);
4975 tmp2
= get_address(s
, 0, b2
, d2
);
4978 gen_op_mvc(s
, (insn
>> 32) & 0xff, tmp
, tmp2
);
4981 potential_page_fault(s
);
4982 gen_helper_nc(cc_op
, vl
, tmp
, tmp2
);
4986 gen_op_clc(s
, (insn
>> 32) & 0xff, tmp
, tmp2
);
4989 potential_page_fault(s
);
4990 gen_helper_oc(cc_op
, vl
, tmp
, tmp2
);
4994 potential_page_fault(s
);
4995 gen_helper_xc(cc_op
, vl
, tmp
, tmp2
);
4999 potential_page_fault(s
);
5000 gen_helper_tr(vl
, tmp
, tmp2
);
5004 potential_page_fault(s
);
5005 gen_helper_unpk(vl
, tmp
, tmp2
);
5010 tcg_temp_free_i64(tmp
);
5011 tcg_temp_free_i64(tmp2
);
5013 #ifndef CONFIG_USER_ONLY
5014 case 0xda: /* MVCP D1(R1,B1),D2(B2),R3 [SS] */
5015 case 0xdb: /* MVCS D1(R1,B1),D2(B2),R3 [SS] */
5016 check_privileged(s
, ilc
);
5017 potential_page_fault(s
);
5018 insn
= ld_code6(s
->pc
);
5019 r1
= (insn
>> 36) & 0xf;
5020 r3
= (insn
>> 32) & 0xf;
5021 b1
= (insn
>> 28) & 0xf;
5022 d1
= (insn
>> 16) & 0xfff;
5023 b2
= (insn
>> 12) & 0xf;
5027 tmp2
= get_address(s
, 0, b1
, d1
);
5028 tmp3
= get_address(s
, 0, b2
, d2
);
5030 gen_helper_mvcp(cc_op
, tmp
, tmp2
, tmp3
);
5032 gen_helper_mvcs(cc_op
, tmp
, tmp2
, tmp3
);
5035 tcg_temp_free_i64(tmp
);
5036 tcg_temp_free_i64(tmp2
);
5037 tcg_temp_free_i64(tmp3
);
5041 insn
= ld_code6(s
->pc
);
5044 r1
= (insn
>> 36) & 0xf;
5045 x2
= (insn
>> 32) & 0xf;
5046 b2
= (insn
>> 28) & 0xf;
5047 d2
= ((int)((((insn
>> 16) & 0xfff)
5048 | ((insn
<< 4) & 0xff000)) << 12)) >> 12;
5049 disas_e3(s
, op
, r1
, x2
, b2
, d2
);
5051 #ifndef CONFIG_USER_ONLY
5053 /* Test Protection */
5054 check_privileged(s
, ilc
);
5055 insn
= ld_code6(s
->pc
);
5061 insn
= ld_code6(s
->pc
);
5064 r1
= (insn
>> 36) & 0xf;
5065 r3
= (insn
>> 32) & 0xf;
5066 b2
= (insn
>> 28) & 0xf;
5067 d2
= ((int)((((insn
>> 16) & 0xfff)
5068 | ((insn
<< 4) & 0xff000)) << 12)) >> 12;
5069 disas_eb(s
, op
, r1
, r3
, b2
, d2
);
5072 insn
= ld_code6(s
->pc
);
5075 r1
= (insn
>> 36) & 0xf;
5076 x2
= (insn
>> 32) & 0xf;
5077 b2
= (insn
>> 28) & 0xf;
5078 d2
= (short)((insn
>> 16) & 0xfff);
5079 r1b
= (insn
>> 12) & 0xf;
5080 disas_ed(s
, op
, r1
, x2
, b2
, d2
, r1b
);
5083 LOG_DISAS("unimplemented opcode 0x%x\n", opc
);
5084 gen_illegal_opcode(s
, ilc
);
5088 /* Instruction length is encoded in the opcode */
5092 static inline void gen_intermediate_code_internal(CPUState
*env
,
5093 TranslationBlock
*tb
,
5097 target_ulong pc_start
;
5098 uint64_t next_page_start
;
5099 uint16_t *gen_opc_end
;
5101 int num_insns
, max_insns
;
5107 if (!(tb
->flags
& FLAG_MASK_64
)) {
5108 pc_start
&= 0x7fffffff;
5112 dc
.is_jmp
= DISAS_NEXT
;
5114 dc
.cc_op
= CC_OP_DYNAMIC
;
5116 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
5118 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
5121 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
5122 if (max_insns
== 0) {
5123 max_insns
= CF_COUNT_MASK
;
5129 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
5130 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
5131 if (bp
->pc
== dc
.pc
) {
5138 j
= gen_opc_ptr
- gen_opc_buf
;
5142 gen_opc_instr_start
[lj
++] = 0;
5145 gen_opc_pc
[lj
] = dc
.pc
;
5146 gen_opc_cc_op
[lj
] = dc
.cc_op
;
5147 gen_opc_instr_start
[lj
] = 1;
5148 gen_opc_icount
[lj
] = num_insns
;
5150 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
5153 #if defined(S390X_DEBUG_DISAS_VERBOSE)
5154 LOG_DISAS("pc " TARGET_FMT_lx
"\n",
5157 disas_s390_insn(&dc
);
5160 if (env
->singlestep_enabled
) {
5163 } while (!dc
.is_jmp
&& gen_opc_ptr
< gen_opc_end
&& dc
.pc
< next_page_start
5164 && num_insns
< max_insns
&& !env
->singlestep_enabled
5168 update_psw_addr(&dc
);
5171 if (singlestep
&& dc
.cc_op
!= CC_OP_DYNAMIC
) {
5172 gen_op_calc_cc(&dc
);
5174 /* next TB starts off with CC_OP_DYNAMIC, so make sure the cc op type
5176 gen_op_set_cc_op(&dc
);
5179 if (tb
->cflags
& CF_LAST_IO
) {
5182 /* Generate the return instruction */
5183 if (dc
.is_jmp
!= DISAS_TB_JUMP
) {
5186 gen_icount_end(tb
, num_insns
);
5187 *gen_opc_ptr
= INDEX_op_end
;
5189 j
= gen_opc_ptr
- gen_opc_buf
;
5192 gen_opc_instr_start
[lj
++] = 0;
5195 tb
->size
= dc
.pc
- pc_start
;
5196 tb
->icount
= num_insns
;
5198 #if defined(S390X_DEBUG_DISAS)
5199 log_cpu_state_mask(CPU_LOG_TB_CPU
, env
, 0);
5200 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
5201 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
5202 log_target_disas(pc_start
, dc
.pc
- pc_start
, 1);
5208 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
5210 gen_intermediate_code_internal(env
, tb
, 0);
5213 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
5215 gen_intermediate_code_internal(env
, tb
, 1);
5218 void restore_state_to_opc(CPUState
*env
, TranslationBlock
*tb
, int pc_pos
)
5221 env
->psw
.addr
= gen_opc_pc
[pc_pos
];
5222 cc_op
= gen_opc_cc_op
[pc_pos
];
5223 if ((cc_op
!= CC_OP_DYNAMIC
) && (cc_op
!= CC_OP_STATIC
)) {