4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 /* #define DEBUG_INLINE_BRANCHES */
22 #define S390X_DEBUG_DISAS
23 /* #define S390X_DEBUG_DISAS_VERBOSE */
25 #ifdef S390X_DEBUG_DISAS_VERBOSE
26 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
28 # define LOG_DISAS(...) do { } while (0)
32 #include "disas/disas.h"
35 #include "qemu/host-utils.h"
37 /* global register indexes */
38 static TCGv_ptr cpu_env
;
40 #include "exec/gen-icount.h"
46 /* Information that (most) every instruction needs to manipulate. */
47 typedef struct DisasContext DisasContext
;
48 typedef struct DisasInsn DisasInsn
;
49 typedef struct DisasFields DisasFields
;
52 struct TranslationBlock
*tb
;
53 const DisasInsn
*insn
;
57 bool singlestep_enabled
;
61 /* Information carried about a condition to be evaluated. */
68 struct { TCGv_i64 a
, b
; } s64
;
69 struct { TCGv_i32 a
, b
; } s32
;
75 static void gen_op_calc_cc(DisasContext
*s
);
77 #ifdef DEBUG_INLINE_BRANCHES
78 static uint64_t inline_branch_hit
[CC_OP_MAX
];
79 static uint64_t inline_branch_miss
[CC_OP_MAX
];
82 static inline void debug_insn(uint64_t insn
)
84 LOG_DISAS("insn: 0x%" PRIx64
"\n", insn
);
87 static inline uint64_t pc_to_link_info(DisasContext
*s
, uint64_t pc
)
89 if (!(s
->tb
->flags
& FLAG_MASK_64
)) {
90 if (s
->tb
->flags
& FLAG_MASK_32
) {
91 return pc
| 0x80000000;
97 void cpu_dump_state(CPUS390XState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
102 if (env
->cc_op
> 3) {
103 cpu_fprintf(f
, "PSW=mask %016" PRIx64
" addr %016" PRIx64
" cc %15s\n",
104 env
->psw
.mask
, env
->psw
.addr
, cc_name(env
->cc_op
));
106 cpu_fprintf(f
, "PSW=mask %016" PRIx64
" addr %016" PRIx64
" cc %02x\n",
107 env
->psw
.mask
, env
->psw
.addr
, env
->cc_op
);
110 for (i
= 0; i
< 16; i
++) {
111 cpu_fprintf(f
, "R%02d=%016" PRIx64
, i
, env
->regs
[i
]);
113 cpu_fprintf(f
, "\n");
119 for (i
= 0; i
< 16; i
++) {
120 cpu_fprintf(f
, "F%02d=%016" PRIx64
, i
, env
->fregs
[i
].ll
);
122 cpu_fprintf(f
, "\n");
128 #ifndef CONFIG_USER_ONLY
129 for (i
= 0; i
< 16; i
++) {
130 cpu_fprintf(f
, "C%02d=%016" PRIx64
, i
, env
->cregs
[i
]);
132 cpu_fprintf(f
, "\n");
139 #ifdef DEBUG_INLINE_BRANCHES
140 for (i
= 0; i
< CC_OP_MAX
; i
++) {
141 cpu_fprintf(f
, " %15s = %10ld\t%10ld\n", cc_name(i
),
142 inline_branch_miss
[i
], inline_branch_hit
[i
]);
146 cpu_fprintf(f
, "\n");
149 static TCGv_i64 psw_addr
;
150 static TCGv_i64 psw_mask
;
152 static TCGv_i32 cc_op
;
153 static TCGv_i64 cc_src
;
154 static TCGv_i64 cc_dst
;
155 static TCGv_i64 cc_vr
;
157 static char cpu_reg_names
[32][4];
158 static TCGv_i64 regs
[16];
159 static TCGv_i64 fregs
[16];
161 static uint8_t gen_opc_cc_op
[OPC_BUF_SIZE
];
163 void s390x_translate_init(void)
167 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
168 psw_addr
= tcg_global_mem_new_i64(TCG_AREG0
,
169 offsetof(CPUS390XState
, psw
.addr
),
171 psw_mask
= tcg_global_mem_new_i64(TCG_AREG0
,
172 offsetof(CPUS390XState
, psw
.mask
),
175 cc_op
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUS390XState
, cc_op
),
177 cc_src
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUS390XState
, cc_src
),
179 cc_dst
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUS390XState
, cc_dst
),
181 cc_vr
= tcg_global_mem_new_i64(TCG_AREG0
, offsetof(CPUS390XState
, cc_vr
),
184 for (i
= 0; i
< 16; i
++) {
185 snprintf(cpu_reg_names
[i
], sizeof(cpu_reg_names
[0]), "r%d", i
);
186 regs
[i
] = tcg_global_mem_new(TCG_AREG0
,
187 offsetof(CPUS390XState
, regs
[i
]),
191 for (i
= 0; i
< 16; i
++) {
192 snprintf(cpu_reg_names
[i
+ 16], sizeof(cpu_reg_names
[0]), "f%d", i
);
193 fregs
[i
] = tcg_global_mem_new(TCG_AREG0
,
194 offsetof(CPUS390XState
, fregs
[i
].d
),
195 cpu_reg_names
[i
+ 16]);
198 /* register helpers */
203 static inline TCGv_i64
load_reg(int reg
)
205 TCGv_i64 r
= tcg_temp_new_i64();
206 tcg_gen_mov_i64(r
, regs
[reg
]);
210 static inline TCGv_i64
load_freg(int reg
)
212 TCGv_i64 r
= tcg_temp_new_i64();
213 tcg_gen_mov_i64(r
, fregs
[reg
]);
217 static inline TCGv_i32
load_freg32(int reg
)
219 TCGv_i32 r
= tcg_temp_new_i32();
220 #if HOST_LONG_BITS == 32
221 tcg_gen_mov_i32(r
, TCGV_HIGH(fregs
[reg
]));
223 tcg_gen_shri_i64(MAKE_TCGV_I64(GET_TCGV_I32(r
)), fregs
[reg
], 32);
228 static inline TCGv_i64
load_freg32_i64(int reg
)
230 TCGv_i64 r
= tcg_temp_new_i64();
231 tcg_gen_shri_i64(r
, fregs
[reg
], 32);
235 static inline TCGv_i32
load_reg32(int reg
)
237 TCGv_i32 r
= tcg_temp_new_i32();
238 tcg_gen_trunc_i64_i32(r
, regs
[reg
]);
242 static inline TCGv_i64
load_reg32_i64(int reg
)
244 TCGv_i64 r
= tcg_temp_new_i64();
245 tcg_gen_ext32s_i64(r
, regs
[reg
]);
249 static inline void store_reg(int reg
, TCGv_i64 v
)
251 tcg_gen_mov_i64(regs
[reg
], v
);
254 static inline void store_freg(int reg
, TCGv_i64 v
)
256 tcg_gen_mov_i64(fregs
[reg
], v
);
259 static inline void store_reg32(int reg
, TCGv_i32 v
)
261 /* 32 bit register writes keep the upper half */
262 #if HOST_LONG_BITS == 32
263 tcg_gen_mov_i32(TCGV_LOW(regs
[reg
]), v
);
265 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
],
266 MAKE_TCGV_I64(GET_TCGV_I32(v
)), 0, 32);
270 static inline void store_reg32_i64(int reg
, TCGv_i64 v
)
272 /* 32 bit register writes keep the upper half */
273 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
], v
, 0, 32);
276 static inline void store_reg32h_i64(int reg
, TCGv_i64 v
)
278 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
], v
, 32, 32);
281 static inline void store_reg16(int reg
, TCGv_i32 v
)
283 /* 16 bit register writes keep the upper bytes */
284 #if HOST_LONG_BITS == 32
285 tcg_gen_deposit_i32(TCGV_LOW(regs
[reg
]), TCGV_LOW(regs
[reg
]), v
, 0, 16);
287 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
],
288 MAKE_TCGV_I64(GET_TCGV_I32(v
)), 0, 16);
292 static inline void store_freg32(int reg
, TCGv_i32 v
)
294 /* 32 bit register writes keep the lower half */
295 #if HOST_LONG_BITS == 32
296 tcg_gen_mov_i32(TCGV_HIGH(fregs
[reg
]), v
);
298 tcg_gen_deposit_i64(fregs
[reg
], fregs
[reg
],
299 MAKE_TCGV_I64(GET_TCGV_I32(v
)), 32, 32);
303 static inline void store_freg32_i64(int reg
, TCGv_i64 v
)
305 tcg_gen_deposit_i64(fregs
[reg
], fregs
[reg
], v
, 32, 32);
308 static inline void return_low128(TCGv_i64 dest
)
310 tcg_gen_ld_i64(dest
, cpu_env
, offsetof(CPUS390XState
, retxl
));
313 static inline void update_psw_addr(DisasContext
*s
)
316 tcg_gen_movi_i64(psw_addr
, s
->pc
);
319 static inline void potential_page_fault(DisasContext
*s
)
321 #ifndef CONFIG_USER_ONLY
327 static inline uint64_t ld_code2(CPUS390XState
*env
, uint64_t pc
)
329 return (uint64_t)cpu_lduw_code(env
, pc
);
332 static inline uint64_t ld_code4(CPUS390XState
*env
, uint64_t pc
)
334 return (uint64_t)(uint32_t)cpu_ldl_code(env
, pc
);
337 static inline uint64_t ld_code6(CPUS390XState
*env
, uint64_t pc
)
339 return (ld_code2(env
, pc
) << 32) | ld_code4(env
, pc
+ 2);
342 static inline int get_mem_index(DisasContext
*s
)
344 switch (s
->tb
->flags
& FLAG_MASK_ASC
) {
345 case PSW_ASC_PRIMARY
>> 32:
347 case PSW_ASC_SECONDARY
>> 32:
349 case PSW_ASC_HOME
>> 32:
357 static void gen_exception(int excp
)
359 TCGv_i32 tmp
= tcg_const_i32(excp
);
360 gen_helper_exception(cpu_env
, tmp
);
361 tcg_temp_free_i32(tmp
);
364 static void gen_program_exception(DisasContext
*s
, int code
)
368 /* Remember what pgm exeption this was. */
369 tmp
= tcg_const_i32(code
);
370 tcg_gen_st_i32(tmp
, cpu_env
, offsetof(CPUS390XState
, int_pgm_code
));
371 tcg_temp_free_i32(tmp
);
373 tmp
= tcg_const_i32(s
->next_pc
- s
->pc
);
374 tcg_gen_st_i32(tmp
, cpu_env
, offsetof(CPUS390XState
, int_pgm_ilen
));
375 tcg_temp_free_i32(tmp
);
377 /* Advance past instruction. */
384 /* Trigger exception. */
385 gen_exception(EXCP_PGM
);
388 s
->is_jmp
= DISAS_EXCP
;
391 static inline void gen_illegal_opcode(DisasContext
*s
)
393 gen_program_exception(s
, PGM_SPECIFICATION
);
396 static inline void check_privileged(DisasContext
*s
)
398 if (s
->tb
->flags
& (PSW_MASK_PSTATE
>> 32)) {
399 gen_program_exception(s
, PGM_PRIVILEGED
);
403 static TCGv_i64
get_address(DisasContext
*s
, int x2
, int b2
, int d2
)
407 /* 31-bitify the immediate part; register contents are dealt with below */
408 if (!(s
->tb
->flags
& FLAG_MASK_64
)) {
414 tmp
= tcg_const_i64(d2
);
415 tcg_gen_add_i64(tmp
, tmp
, regs
[x2
]);
420 tcg_gen_add_i64(tmp
, tmp
, regs
[b2
]);
424 tmp
= tcg_const_i64(d2
);
425 tcg_gen_add_i64(tmp
, tmp
, regs
[b2
]);
430 tmp
= tcg_const_i64(d2
);
433 /* 31-bit mode mask if there are values loaded from registers */
434 if (!(s
->tb
->flags
& FLAG_MASK_64
) && (x2
|| b2
)) {
435 tcg_gen_andi_i64(tmp
, tmp
, 0x7fffffffUL
);
441 static void gen_op_movi_cc(DisasContext
*s
, uint32_t val
)
443 s
->cc_op
= CC_OP_CONST0
+ val
;
446 static void gen_op_update1_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 dst
)
448 tcg_gen_discard_i64(cc_src
);
449 tcg_gen_mov_i64(cc_dst
, dst
);
450 tcg_gen_discard_i64(cc_vr
);
454 static void gen_op_update1_cc_i32(DisasContext
*s
, enum cc_op op
, TCGv_i32 dst
)
456 tcg_gen_discard_i64(cc_src
);
457 tcg_gen_extu_i32_i64(cc_dst
, dst
);
458 tcg_gen_discard_i64(cc_vr
);
462 static void gen_op_update2_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 src
,
465 tcg_gen_mov_i64(cc_src
, src
);
466 tcg_gen_mov_i64(cc_dst
, dst
);
467 tcg_gen_discard_i64(cc_vr
);
471 static void gen_op_update2_cc_i32(DisasContext
*s
, enum cc_op op
, TCGv_i32 src
,
474 tcg_gen_extu_i32_i64(cc_src
, src
);
475 tcg_gen_extu_i32_i64(cc_dst
, dst
);
476 tcg_gen_discard_i64(cc_vr
);
480 static void gen_op_update3_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 src
,
481 TCGv_i64 dst
, TCGv_i64 vr
)
483 tcg_gen_mov_i64(cc_src
, src
);
484 tcg_gen_mov_i64(cc_dst
, dst
);
485 tcg_gen_mov_i64(cc_vr
, vr
);
489 static inline void set_cc_nz_u32(DisasContext
*s
, TCGv_i32 val
)
491 gen_op_update1_cc_i32(s
, CC_OP_NZ
, val
);
494 static inline void set_cc_nz_u64(DisasContext
*s
, TCGv_i64 val
)
496 gen_op_update1_cc_i64(s
, CC_OP_NZ
, val
);
499 static inline void cmp_32(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
,
502 gen_op_update2_cc_i32(s
, cond
, v1
, v2
);
505 static inline void cmp_64(DisasContext
*s
, TCGv_i64 v1
, TCGv_i64 v2
,
508 gen_op_update2_cc_i64(s
, cond
, v1
, v2
);
511 static inline void cmp_s32(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
)
513 cmp_32(s
, v1
, v2
, CC_OP_LTGT_32
);
516 static inline void cmp_u32(DisasContext
*s
, TCGv_i32 v1
, TCGv_i32 v2
)
518 cmp_32(s
, v1
, v2
, CC_OP_LTUGTU_32
);
521 static inline void cmp_s32c(DisasContext
*s
, TCGv_i32 v1
, int32_t v2
)
523 /* XXX optimize for the constant? put it in s? */
524 TCGv_i32 tmp
= tcg_const_i32(v2
);
525 cmp_32(s
, v1
, tmp
, CC_OP_LTGT_32
);
526 tcg_temp_free_i32(tmp
);
529 static inline void cmp_u32c(DisasContext
*s
, TCGv_i32 v1
, uint32_t v2
)
531 TCGv_i32 tmp
= tcg_const_i32(v2
);
532 cmp_32(s
, v1
, tmp
, CC_OP_LTUGTU_32
);
533 tcg_temp_free_i32(tmp
);
536 static inline void cmp_s64(DisasContext
*s
, TCGv_i64 v1
, TCGv_i64 v2
)
538 cmp_64(s
, v1
, v2
, CC_OP_LTGT_64
);
541 static inline void cmp_u64(DisasContext
*s
, TCGv_i64 v1
, TCGv_i64 v2
)
543 cmp_64(s
, v1
, v2
, CC_OP_LTUGTU_64
);
546 static inline void cmp_s64c(DisasContext
*s
, TCGv_i64 v1
, int64_t v2
)
548 TCGv_i64 tmp
= tcg_const_i64(v2
);
550 tcg_temp_free_i64(tmp
);
553 static inline void cmp_u64c(DisasContext
*s
, TCGv_i64 v1
, uint64_t v2
)
555 TCGv_i64 tmp
= tcg_const_i64(v2
);
557 tcg_temp_free_i64(tmp
);
560 static inline void set_cc_s32(DisasContext
*s
, TCGv_i32 val
)
562 gen_op_update1_cc_i32(s
, CC_OP_LTGT0_32
, val
);
565 static inline void set_cc_s64(DisasContext
*s
, TCGv_i64 val
)
567 gen_op_update1_cc_i64(s
, CC_OP_LTGT0_64
, val
);
570 static void set_cc_cmp_f32_i64(DisasContext
*s
, TCGv_i32 v1
, TCGv_i64 v2
)
572 tcg_gen_extu_i32_i64(cc_src
, v1
);
573 tcg_gen_mov_i64(cc_dst
, v2
);
574 tcg_gen_discard_i64(cc_vr
);
575 s
->cc_op
= CC_OP_LTGT_F32
;
578 static void gen_set_cc_nz_f32(DisasContext
*s
, TCGv_i32 v1
)
580 gen_op_update1_cc_i32(s
, CC_OP_NZ_F32
, v1
);
583 /* CC value is in env->cc_op */
584 static inline void set_cc_static(DisasContext
*s
)
586 tcg_gen_discard_i64(cc_src
);
587 tcg_gen_discard_i64(cc_dst
);
588 tcg_gen_discard_i64(cc_vr
);
589 s
->cc_op
= CC_OP_STATIC
;
592 static inline void gen_op_set_cc_op(DisasContext
*s
)
594 if (s
->cc_op
!= CC_OP_DYNAMIC
&& s
->cc_op
!= CC_OP_STATIC
) {
595 tcg_gen_movi_i32(cc_op
, s
->cc_op
);
599 static inline void gen_update_cc_op(DisasContext
*s
)
604 /* calculates cc into cc_op */
605 static void gen_op_calc_cc(DisasContext
*s
)
607 TCGv_i32 local_cc_op
= tcg_const_i32(s
->cc_op
);
608 TCGv_i64 dummy
= tcg_const_i64(0);
615 /* s->cc_op is the cc value */
616 tcg_gen_movi_i32(cc_op
, s
->cc_op
- CC_OP_CONST0
);
619 /* env->cc_op already is the cc value */
633 gen_helper_calc_cc(cc_op
, cpu_env
, local_cc_op
, dummy
, cc_dst
, dummy
);
638 case CC_OP_LTUGTU_32
:
639 case CC_OP_LTUGTU_64
:
647 gen_helper_calc_cc(cc_op
, cpu_env
, local_cc_op
, cc_src
, cc_dst
, dummy
);
662 gen_helper_calc_cc(cc_op
, cpu_env
, local_cc_op
, cc_src
, cc_dst
, cc_vr
);
665 /* unknown operation - assume 3 arguments and cc_op in env */
666 gen_helper_calc_cc(cc_op
, cpu_env
, cc_op
, cc_src
, cc_dst
, cc_vr
);
672 tcg_temp_free_i32(local_cc_op
);
673 tcg_temp_free_i64(dummy
);
675 /* We now have cc in cc_op as constant */
679 static inline void decode_rr(DisasContext
*s
, uint64_t insn
, int *r1
, int *r2
)
683 *r1
= (insn
>> 4) & 0xf;
687 static inline TCGv_i64
decode_rx(DisasContext
*s
, uint64_t insn
, int *r1
,
688 int *x2
, int *b2
, int *d2
)
692 *r1
= (insn
>> 20) & 0xf;
693 *x2
= (insn
>> 16) & 0xf;
694 *b2
= (insn
>> 12) & 0xf;
697 return get_address(s
, *x2
, *b2
, *d2
);
700 static inline void decode_rs(DisasContext
*s
, uint64_t insn
, int *r1
, int *r3
,
705 *r1
= (insn
>> 20) & 0xf;
707 *r3
= (insn
>> 16) & 0xf;
708 *b2
= (insn
>> 12) & 0xf;
712 static inline TCGv_i64
decode_si(DisasContext
*s
, uint64_t insn
, int *i2
,
717 *i2
= (insn
>> 16) & 0xff;
718 *b1
= (insn
>> 12) & 0xf;
721 return get_address(s
, 0, *b1
, *d1
);
724 static int use_goto_tb(DisasContext
*s
, uint64_t dest
)
726 /* NOTE: we handle the case where the TB spans two pages here */
727 return (((dest
& TARGET_PAGE_MASK
) == (s
->tb
->pc
& TARGET_PAGE_MASK
)
728 || (dest
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
))
729 && !s
->singlestep_enabled
730 && !(s
->tb
->cflags
& CF_LAST_IO
));
733 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
, target_ulong pc
)
737 if (use_goto_tb(s
, pc
)) {
738 tcg_gen_goto_tb(tb_num
);
739 tcg_gen_movi_i64(psw_addr
, pc
);
740 tcg_gen_exit_tb((tcg_target_long
)s
->tb
+ tb_num
);
742 /* jump to another page: currently not optimized */
743 tcg_gen_movi_i64(psw_addr
, pc
);
748 static inline void account_noninline_branch(DisasContext
*s
, int cc_op
)
750 #ifdef DEBUG_INLINE_BRANCHES
751 inline_branch_miss
[cc_op
]++;
755 static inline void account_inline_branch(DisasContext
*s
, int cc_op
)
757 #ifdef DEBUG_INLINE_BRANCHES
758 inline_branch_hit
[cc_op
]++;
762 /* Table of mask values to comparison codes, given a comparison as input.
763 For a true comparison CC=3 will never be set, but we treat this
764 conservatively for possible use when CC=3 indicates overflow. */
765 static const TCGCond ltgt_cond
[16] = {
766 TCG_COND_NEVER
, TCG_COND_NEVER
, /* | | | x */
767 TCG_COND_GT
, TCG_COND_NEVER
, /* | | GT | x */
768 TCG_COND_LT
, TCG_COND_NEVER
, /* | LT | | x */
769 TCG_COND_NE
, TCG_COND_NEVER
, /* | LT | GT | x */
770 TCG_COND_EQ
, TCG_COND_NEVER
, /* EQ | | | x */
771 TCG_COND_GE
, TCG_COND_NEVER
, /* EQ | | GT | x */
772 TCG_COND_LE
, TCG_COND_NEVER
, /* EQ | LT | | x */
773 TCG_COND_ALWAYS
, TCG_COND_ALWAYS
, /* EQ | LT | GT | x */
776 /* Table of mask values to comparison codes, given a logic op as input.
777 For such, only CC=0 and CC=1 should be possible. */
778 static const TCGCond nz_cond
[16] = {
780 TCG_COND_NEVER
, TCG_COND_NEVER
, TCG_COND_NEVER
, TCG_COND_NEVER
,
782 TCG_COND_NE
, TCG_COND_NE
, TCG_COND_NE
, TCG_COND_NE
,
784 TCG_COND_EQ
, TCG_COND_EQ
, TCG_COND_EQ
, TCG_COND_EQ
,
785 /* EQ | NE | x | x */
786 TCG_COND_ALWAYS
, TCG_COND_ALWAYS
, TCG_COND_ALWAYS
, TCG_COND_ALWAYS
,
789 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
790 details required to generate a TCG comparison. */
791 static void disas_jcc(DisasContext
*s
, DisasCompare
*c
, uint32_t mask
)
794 enum cc_op old_cc_op
= s
->cc_op
;
796 if (mask
== 15 || mask
== 0) {
797 c
->cond
= (mask
? TCG_COND_ALWAYS
: TCG_COND_NEVER
);
800 c
->g1
= c
->g2
= true;
805 /* Find the TCG condition for the mask + cc op. */
811 cond
= ltgt_cond
[mask
];
812 if (cond
== TCG_COND_NEVER
) {
815 account_inline_branch(s
, old_cc_op
);
818 case CC_OP_LTUGTU_32
:
819 case CC_OP_LTUGTU_64
:
820 cond
= tcg_unsigned_cond(ltgt_cond
[mask
]);
821 if (cond
== TCG_COND_NEVER
) {
824 account_inline_branch(s
, old_cc_op
);
828 cond
= nz_cond
[mask
];
829 if (cond
== TCG_COND_NEVER
) {
832 account_inline_branch(s
, old_cc_op
);
847 account_inline_branch(s
, old_cc_op
);
862 account_inline_branch(s
, old_cc_op
);
867 /* Calculate cc value. */
872 /* Jump based on CC. We'll load up the real cond below;
873 the assignment here merely avoids a compiler warning. */
874 account_noninline_branch(s
, old_cc_op
);
875 old_cc_op
= CC_OP_STATIC
;
876 cond
= TCG_COND_NEVER
;
880 /* Load up the arguments of the comparison. */
882 c
->g1
= c
->g2
= false;
886 c
->u
.s32
.a
= tcg_temp_new_i32();
887 tcg_gen_trunc_i64_i32(c
->u
.s32
.a
, cc_dst
);
888 c
->u
.s32
.b
= tcg_const_i32(0);
891 case CC_OP_LTUGTU_32
:
893 c
->u
.s32
.a
= tcg_temp_new_i32();
894 tcg_gen_trunc_i64_i32(c
->u
.s32
.a
, cc_src
);
895 c
->u
.s32
.b
= tcg_temp_new_i32();
896 tcg_gen_trunc_i64_i32(c
->u
.s32
.b
, cc_dst
);
902 c
->u
.s64
.b
= tcg_const_i64(0);
906 case CC_OP_LTUGTU_64
:
909 c
->g1
= c
->g2
= true;
915 c
->u
.s64
.a
= tcg_temp_new_i64();
916 c
->u
.s64
.b
= tcg_const_i64(0);
917 tcg_gen_and_i64(c
->u
.s64
.a
, cc_src
, cc_dst
);
925 case 0x8 | 0x4 | 0x2: /* cc != 3 */
927 c
->u
.s32
.b
= tcg_const_i32(3);
929 case 0x8 | 0x4 | 0x1: /* cc != 2 */
931 c
->u
.s32
.b
= tcg_const_i32(2);
933 case 0x8 | 0x2 | 0x1: /* cc != 1 */
935 c
->u
.s32
.b
= tcg_const_i32(1);
937 case 0x8 | 0x2: /* cc == 0 ||Â cc == 2 => (cc & 1) == 0 */
940 c
->u
.s32
.a
= tcg_temp_new_i32();
941 c
->u
.s32
.b
= tcg_const_i32(0);
942 tcg_gen_andi_i32(c
->u
.s32
.a
, cc_op
, 1);
944 case 0x8 | 0x4: /* cc < 2 */
946 c
->u
.s32
.b
= tcg_const_i32(2);
948 case 0x8: /* cc == 0 */
950 c
->u
.s32
.b
= tcg_const_i32(0);
952 case 0x4 | 0x2 | 0x1: /* cc != 0 */
954 c
->u
.s32
.b
= tcg_const_i32(0);
956 case 0x4 | 0x1: /* cc == 1 ||Â cc == 3 => (cc & 1) != 0 */
959 c
->u
.s32
.a
= tcg_temp_new_i32();
960 c
->u
.s32
.b
= tcg_const_i32(0);
961 tcg_gen_andi_i32(c
->u
.s32
.a
, cc_op
, 1);
963 case 0x4: /* cc == 1 */
965 c
->u
.s32
.b
= tcg_const_i32(1);
967 case 0x2 | 0x1: /* cc > 1 */
969 c
->u
.s32
.b
= tcg_const_i32(1);
971 case 0x2: /* cc == 2 */
973 c
->u
.s32
.b
= tcg_const_i32(2);
975 case 0x1: /* cc == 3 */
977 c
->u
.s32
.b
= tcg_const_i32(3);
980 /* CC is masked by something else: (8 >> cc) & mask. */
983 c
->u
.s32
.a
= tcg_const_i32(8);
984 c
->u
.s32
.b
= tcg_const_i32(0);
985 tcg_gen_shr_i32(c
->u
.s32
.a
, c
->u
.s32
.a
, cc_op
);
986 tcg_gen_andi_i32(c
->u
.s32
.a
, c
->u
.s32
.a
, mask
);
997 static void free_compare(DisasCompare
*c
)
1001 tcg_temp_free_i64(c
->u
.s64
.a
);
1003 tcg_temp_free_i32(c
->u
.s32
.a
);
1008 tcg_temp_free_i64(c
->u
.s64
.b
);
1010 tcg_temp_free_i32(c
->u
.s32
.b
);
1015 static void disas_e3(CPUS390XState
*env
, DisasContext
* s
, int op
, int r1
,
1016 int x2
, int b2
, int d2
)
1018 TCGv_i64 addr
, tmp2
;
1021 LOG_DISAS("disas_e3: op 0x%x r1 %d x2 %d b2 %d d2 %d\n",
1022 op
, r1
, x2
, b2
, d2
);
1023 addr
= get_address(s
, x2
, b2
, d2
);
1025 case 0xf: /* LRVG R1,D2(X2,B2) [RXE] */
1026 tmp2
= tcg_temp_new_i64();
1027 tcg_gen_qemu_ld64(tmp2
, addr
, get_mem_index(s
));
1028 tcg_gen_bswap64_i64(tmp2
, tmp2
);
1029 store_reg(r1
, tmp2
);
1030 tcg_temp_free_i64(tmp2
);
1032 case 0x17: /* LLGT R1,D2(X2,B2) [RXY] */
1033 tmp2
= tcg_temp_new_i64();
1034 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1035 tcg_gen_andi_i64(tmp2
, tmp2
, 0x7fffffffULL
);
1036 store_reg(r1
, tmp2
);
1037 tcg_temp_free_i64(tmp2
);
1039 case 0x1e: /* LRV R1,D2(X2,B2) [RXY] */
1040 tmp2
= tcg_temp_new_i64();
1041 tmp32_1
= tcg_temp_new_i32();
1042 tcg_gen_qemu_ld32u(tmp2
, addr
, get_mem_index(s
));
1043 tcg_gen_trunc_i64_i32(tmp32_1
, tmp2
);
1044 tcg_temp_free_i64(tmp2
);
1045 tcg_gen_bswap32_i32(tmp32_1
, tmp32_1
);
1046 store_reg32(r1
, tmp32_1
);
1047 tcg_temp_free_i32(tmp32_1
);
1049 case 0x1f: /* LRVH R1,D2(X2,B2) [RXY] */
1050 tmp2
= tcg_temp_new_i64();
1051 tmp32_1
= tcg_temp_new_i32();
1052 tcg_gen_qemu_ld16u(tmp2
, addr
, get_mem_index(s
));
1053 tcg_gen_trunc_i64_i32(tmp32_1
, tmp2
);
1054 tcg_temp_free_i64(tmp2
);
1055 tcg_gen_bswap16_i32(tmp32_1
, tmp32_1
);
1056 store_reg16(r1
, tmp32_1
);
1057 tcg_temp_free_i32(tmp32_1
);
1059 case 0x3e: /* STRV R1,D2(X2,B2) [RXY] */
1060 tmp32_1
= load_reg32(r1
);
1061 tmp2
= tcg_temp_new_i64();
1062 tcg_gen_bswap32_i32(tmp32_1
, tmp32_1
);
1063 tcg_gen_extu_i32_i64(tmp2
, tmp32_1
);
1064 tcg_temp_free_i32(tmp32_1
);
1065 tcg_gen_qemu_st32(tmp2
, addr
, get_mem_index(s
));
1066 tcg_temp_free_i64(tmp2
);
1069 LOG_DISAS("illegal e3 operation 0x%x\n", op
);
1070 gen_illegal_opcode(s
);
1073 tcg_temp_free_i64(addr
);
1076 #ifndef CONFIG_USER_ONLY
1077 static void disas_e5(CPUS390XState
*env
, DisasContext
* s
, uint64_t insn
)
1080 int op
= (insn
>> 32) & 0xff;
1082 tmp
= get_address(s
, 0, (insn
>> 28) & 0xf, (insn
>> 16) & 0xfff);
1083 tmp2
= get_address(s
, 0, (insn
>> 12) & 0xf, insn
& 0xfff);
1085 LOG_DISAS("disas_e5: insn %" PRIx64
"\n", insn
);
1087 case 0x01: /* TPROT D1(B1),D2(B2) [SSE] */
1088 /* Test Protection */
1089 potential_page_fault(s
);
1090 gen_helper_tprot(cc_op
, tmp
, tmp2
);
1094 LOG_DISAS("illegal e5 operation 0x%x\n", op
);
1095 gen_illegal_opcode(s
);
1099 tcg_temp_free_i64(tmp
);
1100 tcg_temp_free_i64(tmp2
);
1104 static void disas_eb(CPUS390XState
*env
, DisasContext
*s
, int op
, int r1
,
1105 int r3
, int b2
, int d2
)
1108 TCGv_i32 tmp32_1
, tmp32_2
;
1110 LOG_DISAS("disas_eb: op 0x%x r1 %d r3 %d b2 %d d2 0x%x\n",
1111 op
, r1
, r3
, b2
, d2
);
1113 case 0x2c: /* STCMH R1,M3,D2(B2) [RSY] */
1114 tmp
= get_address(s
, 0, b2
, d2
);
1115 tmp32_1
= tcg_const_i32(r1
);
1116 tmp32_2
= tcg_const_i32(r3
);
1117 potential_page_fault(s
);
1118 gen_helper_stcmh(cpu_env
, tmp32_1
, tmp
, tmp32_2
);
1119 tcg_temp_free_i64(tmp
);
1120 tcg_temp_free_i32(tmp32_1
);
1121 tcg_temp_free_i32(tmp32_2
);
1123 #ifndef CONFIG_USER_ONLY
1124 case 0x2f: /* LCTLG R1,R3,D2(B2) [RSE] */
1126 check_privileged(s
);
1127 tmp
= get_address(s
, 0, b2
, d2
);
1128 tmp32_1
= tcg_const_i32(r1
);
1129 tmp32_2
= tcg_const_i32(r3
);
1130 potential_page_fault(s
);
1131 gen_helper_lctlg(cpu_env
, tmp32_1
, tmp
, tmp32_2
);
1132 tcg_temp_free_i64(tmp
);
1133 tcg_temp_free_i32(tmp32_1
);
1134 tcg_temp_free_i32(tmp32_2
);
1136 case 0x25: /* STCTG R1,R3,D2(B2) [RSE] */
1138 check_privileged(s
);
1139 tmp
= get_address(s
, 0, b2
, d2
);
1140 tmp32_1
= tcg_const_i32(r1
);
1141 tmp32_2
= tcg_const_i32(r3
);
1142 potential_page_fault(s
);
1143 gen_helper_stctg(cpu_env
, tmp32_1
, tmp
, tmp32_2
);
1144 tcg_temp_free_i64(tmp
);
1145 tcg_temp_free_i32(tmp32_1
);
1146 tcg_temp_free_i32(tmp32_2
);
1149 case 0x30: /* CSG R1,R3,D2(B2) [RSY] */
1150 tmp
= get_address(s
, 0, b2
, d2
);
1151 tmp32_1
= tcg_const_i32(r1
);
1152 tmp32_2
= tcg_const_i32(r3
);
1153 potential_page_fault(s
);
1154 /* XXX rewrite in tcg */
1155 gen_helper_csg(cc_op
, cpu_env
, tmp32_1
, tmp
, tmp32_2
);
1157 tcg_temp_free_i64(tmp
);
1158 tcg_temp_free_i32(tmp32_1
);
1159 tcg_temp_free_i32(tmp32_2
);
1161 case 0x3e: /* CDSG R1,R3,D2(B2) [RSY] */
1162 tmp
= get_address(s
, 0, b2
, d2
);
1163 tmp32_1
= tcg_const_i32(r1
);
1164 tmp32_2
= tcg_const_i32(r3
);
1165 potential_page_fault(s
);
1166 /* XXX rewrite in tcg */
1167 gen_helper_cdsg(cc_op
, cpu_env
, tmp32_1
, tmp
, tmp32_2
);
1169 tcg_temp_free_i64(tmp
);
1170 tcg_temp_free_i32(tmp32_1
);
1171 tcg_temp_free_i32(tmp32_2
);
1174 LOG_DISAS("illegal eb operation 0x%x\n", op
);
1175 gen_illegal_opcode(s
);
1180 static void disas_ed(CPUS390XState
*env
, DisasContext
*s
, int op
, int r1
,
1181 int x2
, int b2
, int d2
, int r1b
)
1183 TCGv_i32 tmp_r1
, tmp32
;
1185 addr
= get_address(s
, x2
, b2
, d2
);
1186 tmp_r1
= tcg_const_i32(r1
);
1188 case 0x4: /* LDEB R1,D2(X2,B2) [RXE] */
1189 potential_page_fault(s
);
1190 gen_helper_ldeb(cpu_env
, tmp_r1
, addr
);
1192 case 0x5: /* LXDB R1,D2(X2,B2) [RXE] */
1193 potential_page_fault(s
);
1194 gen_helper_lxdb(cpu_env
, tmp_r1
, addr
);
1196 case 0x9: /* CEB R1,D2(X2,B2) [RXE] */
1197 tmp
= tcg_temp_new_i64();
1198 tmp32
= load_freg32(r1
);
1199 tcg_gen_qemu_ld32u(tmp
, addr
, get_mem_index(s
));
1200 set_cc_cmp_f32_i64(s
, tmp32
, tmp
);
1201 tcg_temp_free_i64(tmp
);
1202 tcg_temp_free_i32(tmp32
);
1204 case 0xa: /* AEB R1,D2(X2,B2) [RXE] */
1205 tmp
= tcg_temp_new_i64();
1206 tmp32
= tcg_temp_new_i32();
1207 tcg_gen_qemu_ld32u(tmp
, addr
, get_mem_index(s
));
1208 tcg_gen_trunc_i64_i32(tmp32
, tmp
);
1209 gen_helper_aeb(cpu_env
, tmp_r1
, tmp32
);
1210 tcg_temp_free_i64(tmp
);
1211 tcg_temp_free_i32(tmp32
);
1213 tmp32
= load_freg32(r1
);
1214 gen_set_cc_nz_f32(s
, tmp32
);
1215 tcg_temp_free_i32(tmp32
);
1217 case 0xb: /* SEB R1,D2(X2,B2) [RXE] */
1218 tmp
= tcg_temp_new_i64();
1219 tmp32
= tcg_temp_new_i32();
1220 tcg_gen_qemu_ld32u(tmp
, addr
, get_mem_index(s
));
1221 tcg_gen_trunc_i64_i32(tmp32
, tmp
);
1222 gen_helper_seb(cpu_env
, tmp_r1
, tmp32
);
1223 tcg_temp_free_i64(tmp
);
1224 tcg_temp_free_i32(tmp32
);
1226 tmp32
= load_freg32(r1
);
1227 gen_set_cc_nz_f32(s
, tmp32
);
1228 tcg_temp_free_i32(tmp32
);
1230 case 0xd: /* DEB R1,D2(X2,B2) [RXE] */
1231 tmp
= tcg_temp_new_i64();
1232 tmp32
= tcg_temp_new_i32();
1233 tcg_gen_qemu_ld32u(tmp
, addr
, get_mem_index(s
));
1234 tcg_gen_trunc_i64_i32(tmp32
, tmp
);
1235 gen_helper_deb(cpu_env
, tmp_r1
, tmp32
);
1236 tcg_temp_free_i64(tmp
);
1237 tcg_temp_free_i32(tmp32
);
1239 case 0x10: /* TCEB R1,D2(X2,B2) [RXE] */
1240 potential_page_fault(s
);
1241 gen_helper_tceb(cc_op
, cpu_env
, tmp_r1
, addr
);
1244 case 0x11: /* TCDB R1,D2(X2,B2) [RXE] */
1245 potential_page_fault(s
);
1246 gen_helper_tcdb(cc_op
, cpu_env
, tmp_r1
, addr
);
1249 case 0x12: /* TCXB R1,D2(X2,B2) [RXE] */
1250 potential_page_fault(s
);
1251 gen_helper_tcxb(cc_op
, cpu_env
, tmp_r1
, addr
);
1254 case 0x17: /* MEEB R1,D2(X2,B2) [RXE] */
1255 tmp
= tcg_temp_new_i64();
1256 tmp32
= tcg_temp_new_i32();
1257 tcg_gen_qemu_ld32u(tmp
, addr
, get_mem_index(s
));
1258 tcg_gen_trunc_i64_i32(tmp32
, tmp
);
1259 gen_helper_meeb(cpu_env
, tmp_r1
, tmp32
);
1260 tcg_temp_free_i64(tmp
);
1261 tcg_temp_free_i32(tmp32
);
1263 case 0x19: /* CDB R1,D2(X2,B2) [RXE] */
1264 potential_page_fault(s
);
1265 gen_helper_cdb(cc_op
, cpu_env
, tmp_r1
, addr
);
1268 case 0x1a: /* ADB R1,D2(X2,B2) [RXE] */
1269 potential_page_fault(s
);
1270 gen_helper_adb(cc_op
, cpu_env
, tmp_r1
, addr
);
1273 case 0x1b: /* SDB R1,D2(X2,B2) [RXE] */
1274 potential_page_fault(s
);
1275 gen_helper_sdb(cc_op
, cpu_env
, tmp_r1
, addr
);
1278 case 0x1c: /* MDB R1,D2(X2,B2) [RXE] */
1279 potential_page_fault(s
);
1280 gen_helper_mdb(cpu_env
, tmp_r1
, addr
);
1282 case 0x1d: /* DDB R1,D2(X2,B2) [RXE] */
1283 potential_page_fault(s
);
1284 gen_helper_ddb(cpu_env
, tmp_r1
, addr
);
1286 case 0x1e: /* MADB R1,R3,D2(X2,B2) [RXF] */
1287 /* for RXF insns, r1 is R3 and r1b is R1 */
1288 tmp32
= tcg_const_i32(r1b
);
1289 potential_page_fault(s
);
1290 gen_helper_madb(cpu_env
, tmp32
, addr
, tmp_r1
);
1291 tcg_temp_free_i32(tmp32
);
1294 LOG_DISAS("illegal ed operation 0x%x\n", op
);
1295 gen_illegal_opcode(s
);
1298 tcg_temp_free_i32(tmp_r1
);
1299 tcg_temp_free_i64(addr
);
1302 static void disas_b2(CPUS390XState
*env
, DisasContext
*s
, int op
,
1305 TCGv_i64 tmp
, tmp2
, tmp3
;
1306 TCGv_i32 tmp32_1
, tmp32_2
, tmp32_3
;
1308 #ifndef CONFIG_USER_ONLY
1312 r1
= (insn
>> 4) & 0xf;
1315 LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op
, r1
, r2
);
1318 case 0x22: /* IPM R1 [RRE] */
1319 tmp32_1
= tcg_const_i32(r1
);
1321 gen_helper_ipm(cpu_env
, cc_op
, tmp32_1
);
1322 tcg_temp_free_i32(tmp32_1
);
1324 case 0x41: /* CKSM R1,R2 [RRE] */
1325 tmp32_1
= tcg_const_i32(r1
);
1326 tmp32_2
= tcg_const_i32(r2
);
1327 potential_page_fault(s
);
1328 gen_helper_cksm(cpu_env
, tmp32_1
, tmp32_2
);
1329 tcg_temp_free_i32(tmp32_1
);
1330 tcg_temp_free_i32(tmp32_2
);
1331 gen_op_movi_cc(s
, 0);
1333 case 0x4e: /* SAR R1,R2 [RRE] */
1334 tmp32_1
= load_reg32(r2
);
1335 tcg_gen_st_i32(tmp32_1
, cpu_env
, offsetof(CPUS390XState
, aregs
[r1
]));
1336 tcg_temp_free_i32(tmp32_1
);
1338 case 0x4f: /* EAR R1,R2 [RRE] */
1339 tmp32_1
= tcg_temp_new_i32();
1340 tcg_gen_ld_i32(tmp32_1
, cpu_env
, offsetof(CPUS390XState
, aregs
[r2
]));
1341 store_reg32(r1
, tmp32_1
);
1342 tcg_temp_free_i32(tmp32_1
);
1344 case 0x54: /* MVPG R1,R2 [RRE] */
1346 tmp2
= load_reg(r1
);
1347 tmp3
= load_reg(r2
);
1348 potential_page_fault(s
);
1349 gen_helper_mvpg(cpu_env
, tmp
, tmp2
, tmp3
);
1350 tcg_temp_free_i64(tmp
);
1351 tcg_temp_free_i64(tmp2
);
1352 tcg_temp_free_i64(tmp3
);
1353 /* XXX check CCO bit and set CC accordingly */
1354 gen_op_movi_cc(s
, 0);
1356 case 0x55: /* MVST R1,R2 [RRE] */
1357 tmp32_1
= load_reg32(0);
1358 tmp32_2
= tcg_const_i32(r1
);
1359 tmp32_3
= tcg_const_i32(r2
);
1360 potential_page_fault(s
);
1361 gen_helper_mvst(cpu_env
, tmp32_1
, tmp32_2
, tmp32_3
);
1362 tcg_temp_free_i32(tmp32_1
);
1363 tcg_temp_free_i32(tmp32_2
);
1364 tcg_temp_free_i32(tmp32_3
);
1365 gen_op_movi_cc(s
, 1);
1367 case 0x5d: /* CLST R1,R2 [RRE] */
1368 tmp32_1
= load_reg32(0);
1369 tmp32_2
= tcg_const_i32(r1
);
1370 tmp32_3
= tcg_const_i32(r2
);
1371 potential_page_fault(s
);
1372 gen_helper_clst(cc_op
, cpu_env
, tmp32_1
, tmp32_2
, tmp32_3
);
1374 tcg_temp_free_i32(tmp32_1
);
1375 tcg_temp_free_i32(tmp32_2
);
1376 tcg_temp_free_i32(tmp32_3
);
1378 case 0x5e: /* SRST R1,R2 [RRE] */
1379 tmp32_1
= load_reg32(0);
1380 tmp32_2
= tcg_const_i32(r1
);
1381 tmp32_3
= tcg_const_i32(r2
);
1382 potential_page_fault(s
);
1383 gen_helper_srst(cc_op
, cpu_env
, tmp32_1
, tmp32_2
, tmp32_3
);
1385 tcg_temp_free_i32(tmp32_1
);
1386 tcg_temp_free_i32(tmp32_2
);
1387 tcg_temp_free_i32(tmp32_3
);
1390 #ifndef CONFIG_USER_ONLY
1391 case 0x02: /* STIDP D2(B2) [S] */
1393 check_privileged(s
);
1394 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1395 tmp
= get_address(s
, 0, b2
, d2
);
1396 potential_page_fault(s
);
1397 gen_helper_stidp(cpu_env
, tmp
);
1398 tcg_temp_free_i64(tmp
);
1400 case 0x04: /* SCK D2(B2) [S] */
1402 check_privileged(s
);
1403 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1404 tmp
= get_address(s
, 0, b2
, d2
);
1405 potential_page_fault(s
);
1406 gen_helper_sck(cc_op
, tmp
);
1408 tcg_temp_free_i64(tmp
);
1410 case 0x05: /* STCK D2(B2) [S] */
1412 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1413 tmp
= get_address(s
, 0, b2
, d2
);
1414 potential_page_fault(s
);
1415 gen_helper_stck(cc_op
, cpu_env
, tmp
);
1417 tcg_temp_free_i64(tmp
);
1419 case 0x06: /* SCKC D2(B2) [S] */
1420 /* Set Clock Comparator */
1421 check_privileged(s
);
1422 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1423 tmp
= get_address(s
, 0, b2
, d2
);
1424 potential_page_fault(s
);
1425 gen_helper_sckc(cpu_env
, tmp
);
1426 tcg_temp_free_i64(tmp
);
1428 case 0x07: /* STCKC D2(B2) [S] */
1429 /* Store Clock Comparator */
1430 check_privileged(s
);
1431 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1432 tmp
= get_address(s
, 0, b2
, d2
);
1433 potential_page_fault(s
);
1434 gen_helper_stckc(cpu_env
, tmp
);
1435 tcg_temp_free_i64(tmp
);
1437 case 0x08: /* SPT D2(B2) [S] */
1439 check_privileged(s
);
1440 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1441 tmp
= get_address(s
, 0, b2
, d2
);
1442 potential_page_fault(s
);
1443 gen_helper_spt(cpu_env
, tmp
);
1444 tcg_temp_free_i64(tmp
);
1446 case 0x09: /* STPT D2(B2) [S] */
1447 /* Store CPU Timer */
1448 check_privileged(s
);
1449 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1450 tmp
= get_address(s
, 0, b2
, d2
);
1451 potential_page_fault(s
);
1452 gen_helper_stpt(cpu_env
, tmp
);
1453 tcg_temp_free_i64(tmp
);
1455 case 0x0a: /* SPKA D2(B2) [S] */
1456 /* Set PSW Key from Address */
1457 check_privileged(s
);
1458 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1459 tmp
= get_address(s
, 0, b2
, d2
);
1460 tmp2
= tcg_temp_new_i64();
1461 tcg_gen_andi_i64(tmp2
, psw_mask
, ~PSW_MASK_KEY
);
1462 tcg_gen_shli_i64(tmp
, tmp
, PSW_SHIFT_KEY
- 4);
1463 tcg_gen_or_i64(psw_mask
, tmp2
, tmp
);
1464 tcg_temp_free_i64(tmp2
);
1465 tcg_temp_free_i64(tmp
);
1467 case 0x0d: /* PTLB [S] */
1469 check_privileged(s
);
1470 gen_helper_ptlb(cpu_env
);
1472 case 0x10: /* SPX D2(B2) [S] */
1473 /* Set Prefix Register */
1474 check_privileged(s
);
1475 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1476 tmp
= get_address(s
, 0, b2
, d2
);
1477 potential_page_fault(s
);
1478 gen_helper_spx(cpu_env
, tmp
);
1479 tcg_temp_free_i64(tmp
);
1481 case 0x11: /* STPX D2(B2) [S] */
1483 check_privileged(s
);
1484 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1485 tmp
= get_address(s
, 0, b2
, d2
);
1486 tmp2
= tcg_temp_new_i64();
1487 tcg_gen_ld_i64(tmp2
, cpu_env
, offsetof(CPUS390XState
, psa
));
1488 tcg_gen_qemu_st32(tmp2
, tmp
, get_mem_index(s
));
1489 tcg_temp_free_i64(tmp
);
1490 tcg_temp_free_i64(tmp2
);
1492 case 0x12: /* STAP D2(B2) [S] */
1493 /* Store CPU Address */
1494 check_privileged(s
);
1495 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1496 tmp
= get_address(s
, 0, b2
, d2
);
1497 tmp2
= tcg_temp_new_i64();
1498 tmp32_1
= tcg_temp_new_i32();
1499 tcg_gen_ld_i32(tmp32_1
, cpu_env
, offsetof(CPUS390XState
, cpu_num
));
1500 tcg_gen_extu_i32_i64(tmp2
, tmp32_1
);
1501 tcg_gen_qemu_st32(tmp2
, tmp
, get_mem_index(s
));
1502 tcg_temp_free_i64(tmp
);
1503 tcg_temp_free_i64(tmp2
);
1504 tcg_temp_free_i32(tmp32_1
);
1506 case 0x21: /* IPTE R1,R2 [RRE] */
1507 /* Invalidate PTE */
1508 check_privileged(s
);
1509 r1
= (insn
>> 4) & 0xf;
1512 tmp2
= load_reg(r2
);
1513 gen_helper_ipte(cpu_env
, tmp
, tmp2
);
1514 tcg_temp_free_i64(tmp
);
1515 tcg_temp_free_i64(tmp2
);
1517 case 0x29: /* ISKE R1,R2 [RRE] */
1518 /* Insert Storage Key Extended */
1519 check_privileged(s
);
1520 r1
= (insn
>> 4) & 0xf;
1523 tmp2
= tcg_temp_new_i64();
1524 gen_helper_iske(tmp2
, cpu_env
, tmp
);
1525 store_reg(r1
, tmp2
);
1526 tcg_temp_free_i64(tmp
);
1527 tcg_temp_free_i64(tmp2
);
1529 case 0x2a: /* RRBE R1,R2 [RRE] */
1530 /* Set Storage Key Extended */
1531 check_privileged(s
);
1532 r1
= (insn
>> 4) & 0xf;
1534 tmp32_1
= load_reg32(r1
);
1536 gen_helper_rrbe(cc_op
, cpu_env
, tmp32_1
, tmp
);
1538 tcg_temp_free_i32(tmp32_1
);
1539 tcg_temp_free_i64(tmp
);
1541 case 0x2b: /* SSKE R1,R2 [RRE] */
1542 /* Set Storage Key Extended */
1543 check_privileged(s
);
1544 r1
= (insn
>> 4) & 0xf;
1546 tmp32_1
= load_reg32(r1
);
1548 gen_helper_sske(cpu_env
, tmp32_1
, tmp
);
1549 tcg_temp_free_i32(tmp32_1
);
1550 tcg_temp_free_i64(tmp
);
1552 case 0x34: /* STCH ? */
1553 /* Store Subchannel */
1554 check_privileged(s
);
1555 gen_op_movi_cc(s
, 3);
1557 case 0x46: /* STURA R1,R2 [RRE] */
1558 /* Store Using Real Address */
1559 check_privileged(s
);
1560 r1
= (insn
>> 4) & 0xf;
1562 tmp32_1
= load_reg32(r1
);
1564 potential_page_fault(s
);
1565 gen_helper_stura(cpu_env
, tmp
, tmp32_1
);
1566 tcg_temp_free_i32(tmp32_1
);
1567 tcg_temp_free_i64(tmp
);
1569 case 0x50: /* CSP R1,R2 [RRE] */
1570 /* Compare And Swap And Purge */
1571 check_privileged(s
);
1572 r1
= (insn
>> 4) & 0xf;
1574 tmp32_1
= tcg_const_i32(r1
);
1575 tmp32_2
= tcg_const_i32(r2
);
1576 gen_helper_csp(cc_op
, cpu_env
, tmp32_1
, tmp32_2
);
1578 tcg_temp_free_i32(tmp32_1
);
1579 tcg_temp_free_i32(tmp32_2
);
1581 case 0x5f: /* CHSC ? */
1582 /* Channel Subsystem Call */
1583 check_privileged(s
);
1584 gen_op_movi_cc(s
, 3);
1586 case 0x78: /* STCKE D2(B2) [S] */
1587 /* Store Clock Extended */
1588 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1589 tmp
= get_address(s
, 0, b2
, d2
);
1590 potential_page_fault(s
);
1591 gen_helper_stcke(cc_op
, cpu_env
, tmp
);
1593 tcg_temp_free_i64(tmp
);
1595 case 0x79: /* SACF D2(B2) [S] */
1596 /* Set Address Space Control Fast */
1597 check_privileged(s
);
1598 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1599 tmp
= get_address(s
, 0, b2
, d2
);
1600 potential_page_fault(s
);
1601 gen_helper_sacf(cpu_env
, tmp
);
1602 tcg_temp_free_i64(tmp
);
1603 /* addressing mode has changed, so end the block */
1606 s
->is_jmp
= DISAS_JUMP
;
1608 case 0x7d: /* STSI D2,(B2) [S] */
1609 check_privileged(s
);
1610 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1611 tmp
= get_address(s
, 0, b2
, d2
);
1612 tmp32_1
= load_reg32(0);
1613 tmp32_2
= load_reg32(1);
1614 potential_page_fault(s
);
1615 gen_helper_stsi(cc_op
, cpu_env
, tmp
, tmp32_1
, tmp32_2
);
1617 tcg_temp_free_i64(tmp
);
1618 tcg_temp_free_i32(tmp32_1
);
1619 tcg_temp_free_i32(tmp32_2
);
1621 case 0x9d: /* LFPC D2(B2) [S] */
1622 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1623 tmp
= get_address(s
, 0, b2
, d2
);
1624 tmp2
= tcg_temp_new_i64();
1625 tmp32_1
= tcg_temp_new_i32();
1626 tcg_gen_qemu_ld32u(tmp2
, tmp
, get_mem_index(s
));
1627 tcg_gen_trunc_i64_i32(tmp32_1
, tmp2
);
1628 tcg_gen_st_i32(tmp32_1
, cpu_env
, offsetof(CPUS390XState
, fpc
));
1629 tcg_temp_free_i64(tmp
);
1630 tcg_temp_free_i64(tmp2
);
1631 tcg_temp_free_i32(tmp32_1
);
1633 case 0xb1: /* STFL D2(B2) [S] */
1634 /* Store Facility List (CPU features) at 200 */
1635 check_privileged(s
);
1636 tmp2
= tcg_const_i64(0xc0000000);
1637 tmp
= tcg_const_i64(200);
1638 tcg_gen_qemu_st32(tmp2
, tmp
, get_mem_index(s
));
1639 tcg_temp_free_i64(tmp2
);
1640 tcg_temp_free_i64(tmp
);
1642 case 0xb2: /* LPSWE D2(B2) [S] */
1643 /* Load PSW Extended */
1644 check_privileged(s
);
1645 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
1646 tmp
= get_address(s
, 0, b2
, d2
);
1647 tmp2
= tcg_temp_new_i64();
1648 tmp3
= tcg_temp_new_i64();
1649 tcg_gen_qemu_ld64(tmp2
, tmp
, get_mem_index(s
));
1650 tcg_gen_addi_i64(tmp
, tmp
, 8);
1651 tcg_gen_qemu_ld64(tmp3
, tmp
, get_mem_index(s
));
1652 gen_helper_load_psw(cpu_env
, tmp2
, tmp3
);
1653 /* we need to keep cc_op intact */
1654 s
->is_jmp
= DISAS_JUMP
;
1655 tcg_temp_free_i64(tmp
);
1656 tcg_temp_free_i64(tmp2
);
1657 tcg_temp_free_i64(tmp3
);
1659 case 0x20: /* SERVC R1,R2 [RRE] */
1660 /* SCLP Service call (PV hypercall) */
1661 check_privileged(s
);
1662 potential_page_fault(s
);
1663 tmp32_1
= load_reg32(r2
);
1665 gen_helper_servc(cc_op
, cpu_env
, tmp32_1
, tmp
);
1667 tcg_temp_free_i32(tmp32_1
);
1668 tcg_temp_free_i64(tmp
);
1672 LOG_DISAS("illegal b2 operation 0x%x\n", op
);
1673 gen_illegal_opcode(s
);
1678 static void disas_b3(CPUS390XState
*env
, DisasContext
*s
, int op
, int m3
,
1682 TCGv_i32 tmp32_1
, tmp32_2
, tmp32_3
;
1683 LOG_DISAS("disas_b3: op 0x%x m3 0x%x r1 %d r2 %d\n", op
, m3
, r1
, r2
);
1684 #define FP_HELPER(i) \
1685 tmp32_1 = tcg_const_i32(r1); \
1686 tmp32_2 = tcg_const_i32(r2); \
1687 gen_helper_ ## i(cpu_env, tmp32_1, tmp32_2); \
1688 tcg_temp_free_i32(tmp32_1); \
1689 tcg_temp_free_i32(tmp32_2);
1691 #define FP_HELPER_CC(i) \
1692 tmp32_1 = tcg_const_i32(r1); \
1693 tmp32_2 = tcg_const_i32(r2); \
1694 gen_helper_ ## i(cc_op, cpu_env, tmp32_1, tmp32_2); \
1696 tcg_temp_free_i32(tmp32_1); \
1697 tcg_temp_free_i32(tmp32_2);
1700 case 0x0: /* LPEBR R1,R2 [RRE] */
1701 FP_HELPER_CC(lpebr
);
1703 case 0x2: /* LTEBR R1,R2 [RRE] */
1704 FP_HELPER_CC(ltebr
);
1706 case 0x3: /* LCEBR R1,R2 [RRE] */
1707 FP_HELPER_CC(lcebr
);
1709 case 0x4: /* LDEBR R1,R2 [RRE] */
1712 case 0x5: /* LXDBR R1,R2 [RRE] */
1715 case 0x9: /* CEBR R1,R2 [RRE] */
1718 case 0xa: /* AEBR R1,R2 [RRE] */
1721 case 0xb: /* SEBR R1,R2 [RRE] */
1724 case 0xd: /* DEBR R1,R2 [RRE] */
1727 case 0x10: /* LPDBR R1,R2 [RRE] */
1728 FP_HELPER_CC(lpdbr
);
1730 case 0x12: /* LTDBR R1,R2 [RRE] */
1731 FP_HELPER_CC(ltdbr
);
1733 case 0x13: /* LCDBR R1,R2 [RRE] */
1734 FP_HELPER_CC(lcdbr
);
1736 case 0x15: /* SQBDR R1,R2 [RRE] */
1739 case 0x17: /* MEEBR R1,R2 [RRE] */
1742 case 0x19: /* CDBR R1,R2 [RRE] */
1745 case 0x1a: /* ADBR R1,R2 [RRE] */
1748 case 0x1b: /* SDBR R1,R2 [RRE] */
1751 case 0x1c: /* MDBR R1,R2 [RRE] */
1754 case 0x1d: /* DDBR R1,R2 [RRE] */
1757 case 0xe: /* MAEBR R1,R3,R2 [RRF] */
1758 case 0x1e: /* MADBR R1,R3,R2 [RRF] */
1759 case 0x1f: /* MSDBR R1,R3,R2 [RRF] */
1760 /* for RRF insns, m3 is R1, r1 is R3, and r2 is R2 */
1761 tmp32_1
= tcg_const_i32(m3
);
1762 tmp32_2
= tcg_const_i32(r2
);
1763 tmp32_3
= tcg_const_i32(r1
);
1766 gen_helper_maebr(cpu_env
, tmp32_1
, tmp32_3
, tmp32_2
);
1769 gen_helper_madbr(cpu_env
, tmp32_1
, tmp32_3
, tmp32_2
);
1772 gen_helper_msdbr(cpu_env
, tmp32_1
, tmp32_3
, tmp32_2
);
1777 tcg_temp_free_i32(tmp32_1
);
1778 tcg_temp_free_i32(tmp32_2
);
1779 tcg_temp_free_i32(tmp32_3
);
1781 case 0x40: /* LPXBR R1,R2 [RRE] */
1782 FP_HELPER_CC(lpxbr
);
1784 case 0x42: /* LTXBR R1,R2 [RRE] */
1785 FP_HELPER_CC(ltxbr
);
1787 case 0x43: /* LCXBR R1,R2 [RRE] */
1788 FP_HELPER_CC(lcxbr
);
1790 case 0x44: /* LEDBR R1,R2 [RRE] */
1793 case 0x45: /* LDXBR R1,R2 [RRE] */
1796 case 0x46: /* LEXBR R1,R2 [RRE] */
1799 case 0x49: /* CXBR R1,R2 [RRE] */
1802 case 0x4a: /* AXBR R1,R2 [RRE] */
1805 case 0x4b: /* SXBR R1,R2 [RRE] */
1808 case 0x4c: /* MXBR R1,R2 [RRE] */
1811 case 0x4d: /* DXBR R1,R2 [RRE] */
1814 case 0x65: /* LXR R1,R2 [RRE] */
1815 tmp
= load_freg(r2
);
1816 store_freg(r1
, tmp
);
1817 tcg_temp_free_i64(tmp
);
1818 tmp
= load_freg(r2
+ 2);
1819 store_freg(r1
+ 2, tmp
);
1820 tcg_temp_free_i64(tmp
);
1822 case 0x74: /* LZER R1 [RRE] */
1823 tmp32_1
= tcg_const_i32(r1
);
1824 gen_helper_lzer(cpu_env
, tmp32_1
);
1825 tcg_temp_free_i32(tmp32_1
);
1827 case 0x75: /* LZDR R1 [RRE] */
1828 tmp32_1
= tcg_const_i32(r1
);
1829 gen_helper_lzdr(cpu_env
, tmp32_1
);
1830 tcg_temp_free_i32(tmp32_1
);
1832 case 0x76: /* LZXR R1 [RRE] */
1833 tmp32_1
= tcg_const_i32(r1
);
1834 gen_helper_lzxr(cpu_env
, tmp32_1
);
1835 tcg_temp_free_i32(tmp32_1
);
1837 case 0x84: /* SFPC R1 [RRE] */
1838 tmp32_1
= load_reg32(r1
);
1839 tcg_gen_st_i32(tmp32_1
, cpu_env
, offsetof(CPUS390XState
, fpc
));
1840 tcg_temp_free_i32(tmp32_1
);
1842 case 0x94: /* CEFBR R1,R2 [RRE] */
1843 case 0x95: /* CDFBR R1,R2 [RRE] */
1844 case 0x96: /* CXFBR R1,R2 [RRE] */
1845 tmp32_1
= tcg_const_i32(r1
);
1846 tmp32_2
= load_reg32(r2
);
1849 gen_helper_cefbr(cpu_env
, tmp32_1
, tmp32_2
);
1852 gen_helper_cdfbr(cpu_env
, tmp32_1
, tmp32_2
);
1855 gen_helper_cxfbr(cpu_env
, tmp32_1
, tmp32_2
);
1860 tcg_temp_free_i32(tmp32_1
);
1861 tcg_temp_free_i32(tmp32_2
);
1863 case 0x98: /* CFEBR R1,R2 [RRE] */
1864 case 0x99: /* CFDBR R1,R2 [RRE] */
1865 case 0x9a: /* CFXBR R1,R2 [RRE] */
1866 tmp32_1
= tcg_const_i32(r1
);
1867 tmp32_2
= tcg_const_i32(r2
);
1868 tmp32_3
= tcg_const_i32(m3
);
1871 gen_helper_cfebr(cc_op
, cpu_env
, tmp32_1
, tmp32_2
, tmp32_3
);
1874 gen_helper_cfdbr(cc_op
, cpu_env
, tmp32_1
, tmp32_2
, tmp32_3
);
1877 gen_helper_cfxbr(cc_op
, cpu_env
, tmp32_1
, tmp32_2
, tmp32_3
);
1883 tcg_temp_free_i32(tmp32_1
);
1884 tcg_temp_free_i32(tmp32_2
);
1885 tcg_temp_free_i32(tmp32_3
);
1887 case 0xa4: /* CEGBR R1,R2 [RRE] */
1888 case 0xa5: /* CDGBR R1,R2 [RRE] */
1889 tmp32_1
= tcg_const_i32(r1
);
1893 gen_helper_cegbr(cpu_env
, tmp32_1
, tmp
);
1896 gen_helper_cdgbr(cpu_env
, tmp32_1
, tmp
);
1901 tcg_temp_free_i32(tmp32_1
);
1902 tcg_temp_free_i64(tmp
);
1904 case 0xa6: /* CXGBR R1,R2 [RRE] */
1905 tmp32_1
= tcg_const_i32(r1
);
1907 gen_helper_cxgbr(cpu_env
, tmp32_1
, tmp
);
1908 tcg_temp_free_i32(tmp32_1
);
1909 tcg_temp_free_i64(tmp
);
1911 case 0xa8: /* CGEBR R1,R2 [RRE] */
1912 tmp32_1
= tcg_const_i32(r1
);
1913 tmp32_2
= tcg_const_i32(r2
);
1914 tmp32_3
= tcg_const_i32(m3
);
1915 gen_helper_cgebr(cc_op
, cpu_env
, tmp32_1
, tmp32_2
, tmp32_3
);
1917 tcg_temp_free_i32(tmp32_1
);
1918 tcg_temp_free_i32(tmp32_2
);
1919 tcg_temp_free_i32(tmp32_3
);
1921 case 0xa9: /* CGDBR R1,R2 [RRE] */
1922 tmp32_1
= tcg_const_i32(r1
);
1923 tmp32_2
= tcg_const_i32(r2
);
1924 tmp32_3
= tcg_const_i32(m3
);
1925 gen_helper_cgdbr(cc_op
, cpu_env
, tmp32_1
, tmp32_2
, tmp32_3
);
1927 tcg_temp_free_i32(tmp32_1
);
1928 tcg_temp_free_i32(tmp32_2
);
1929 tcg_temp_free_i32(tmp32_3
);
1931 case 0xaa: /* CGXBR R1,R2 [RRE] */
1932 tmp32_1
= tcg_const_i32(r1
);
1933 tmp32_2
= tcg_const_i32(r2
);
1934 tmp32_3
= tcg_const_i32(m3
);
1935 gen_helper_cgxbr(cc_op
, cpu_env
, tmp32_1
, tmp32_2
, tmp32_3
);
1937 tcg_temp_free_i32(tmp32_1
);
1938 tcg_temp_free_i32(tmp32_2
);
1939 tcg_temp_free_i32(tmp32_3
);
1942 LOG_DISAS("illegal b3 operation 0x%x\n", op
);
1943 gen_illegal_opcode(s
);
1951 static void disas_b9(CPUS390XState
*env
, DisasContext
*s
, int op
, int r1
,
1957 LOG_DISAS("disas_b9: op 0x%x r1 %d r2 %d\n", op
, r1
, r2
);
1959 case 0x17: /* LLGTR R1,R2 [RRE] */
1960 tmp32_1
= load_reg32(r2
);
1961 tmp
= tcg_temp_new_i64();
1962 tcg_gen_andi_i32(tmp32_1
, tmp32_1
, 0x7fffffffUL
);
1963 tcg_gen_extu_i32_i64(tmp
, tmp32_1
);
1965 tcg_temp_free_i32(tmp32_1
);
1966 tcg_temp_free_i64(tmp
);
1968 case 0x0f: /* LRVGR R1,R2 [RRE] */
1969 tcg_gen_bswap64_i64(regs
[r1
], regs
[r2
]);
1971 case 0x1f: /* LRVR R1,R2 [RRE] */
1972 tmp32_1
= load_reg32(r2
);
1973 tcg_gen_bswap32_i32(tmp32_1
, tmp32_1
);
1974 store_reg32(r1
, tmp32_1
);
1975 tcg_temp_free_i32(tmp32_1
);
1977 case 0x83: /* FLOGR R1,R2 [RRE] */
1979 tmp32_1
= tcg_const_i32(r1
);
1980 gen_helper_flogr(cc_op
, cpu_env
, tmp32_1
, tmp
);
1982 tcg_temp_free_i64(tmp
);
1983 tcg_temp_free_i32(tmp32_1
);
1986 LOG_DISAS("illegal b9 operation 0x%x\n", op
);
1987 gen_illegal_opcode(s
);
1992 static void disas_s390_insn(CPUS390XState
*env
, DisasContext
*s
)
1995 TCGv_i32 tmp32_1
, tmp32_2
;
1998 int op
, r1
, r2
, r3
, d2
, x2
, b2
, r1b
;
2000 opc
= cpu_ldub_code(env
, s
->pc
);
2001 LOG_DISAS("opc 0x%x\n", opc
);
2005 insn
= ld_code4(env
, s
->pc
);
2006 op
= (insn
>> 16) & 0xff;
2007 disas_b2(env
, s
, op
, insn
);
2010 insn
= ld_code4(env
, s
->pc
);
2011 op
= (insn
>> 16) & 0xff;
2012 r3
= (insn
>> 12) & 0xf; /* aka m3 */
2013 r1
= (insn
>> 4) & 0xf;
2015 disas_b3(env
, s
, op
, r3
, r1
, r2
);
2017 #ifndef CONFIG_USER_ONLY
2018 case 0xb6: /* STCTL R1,R3,D2(B2) [RS] */
2020 check_privileged(s
);
2021 insn
= ld_code4(env
, s
->pc
);
2022 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2023 tmp
= get_address(s
, 0, b2
, d2
);
2024 tmp32_1
= tcg_const_i32(r1
);
2025 tmp32_2
= tcg_const_i32(r3
);
2026 potential_page_fault(s
);
2027 gen_helper_stctl(cpu_env
, tmp32_1
, tmp
, tmp32_2
);
2028 tcg_temp_free_i64(tmp
);
2029 tcg_temp_free_i32(tmp32_1
);
2030 tcg_temp_free_i32(tmp32_2
);
2032 case 0xb7: /* LCTL R1,R3,D2(B2) [RS] */
2034 check_privileged(s
);
2035 insn
= ld_code4(env
, s
->pc
);
2036 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2037 tmp
= get_address(s
, 0, b2
, d2
);
2038 tmp32_1
= tcg_const_i32(r1
);
2039 tmp32_2
= tcg_const_i32(r3
);
2040 potential_page_fault(s
);
2041 gen_helper_lctl(cpu_env
, tmp32_1
, tmp
, tmp32_2
);
2042 tcg_temp_free_i64(tmp
);
2043 tcg_temp_free_i32(tmp32_1
);
2044 tcg_temp_free_i32(tmp32_2
);
2048 insn
= ld_code4(env
, s
->pc
);
2049 r1
= (insn
>> 4) & 0xf;
2051 op
= (insn
>> 16) & 0xff;
2052 disas_b9(env
, s
, op
, r1
, r2
);
2054 case 0xba: /* CS R1,R3,D2(B2) [RS] */
2055 insn
= ld_code4(env
, s
->pc
);
2056 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2057 tmp
= get_address(s
, 0, b2
, d2
);
2058 tmp32_1
= tcg_const_i32(r1
);
2059 tmp32_2
= tcg_const_i32(r3
);
2060 potential_page_fault(s
);
2061 gen_helper_cs(cc_op
, cpu_env
, tmp32_1
, tmp
, tmp32_2
);
2063 tcg_temp_free_i64(tmp
);
2064 tcg_temp_free_i32(tmp32_1
);
2065 tcg_temp_free_i32(tmp32_2
);
2067 case 0xbd: /* CLM R1,M3,D2(B2) [RS] */
2068 insn
= ld_code4(env
, s
->pc
);
2069 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2070 tmp
= get_address(s
, 0, b2
, d2
);
2071 tmp32_1
= load_reg32(r1
);
2072 tmp32_2
= tcg_const_i32(r3
);
2073 potential_page_fault(s
);
2074 gen_helper_clm(cc_op
, cpu_env
, tmp32_1
, tmp32_2
, tmp
);
2076 tcg_temp_free_i64(tmp
);
2077 tcg_temp_free_i32(tmp32_1
);
2078 tcg_temp_free_i32(tmp32_2
);
2080 case 0xbe: /* STCM R1,M3,D2(B2) [RS] */
2081 insn
= ld_code4(env
, s
->pc
);
2082 decode_rs(s
, insn
, &r1
, &r3
, &b2
, &d2
);
2083 tmp
= get_address(s
, 0, b2
, d2
);
2084 tmp32_1
= load_reg32(r1
);
2085 tmp32_2
= tcg_const_i32(r3
);
2086 potential_page_fault(s
);
2087 gen_helper_stcm(cpu_env
, tmp32_1
, tmp32_2
, tmp
);
2088 tcg_temp_free_i64(tmp
);
2089 tcg_temp_free_i32(tmp32_1
);
2090 tcg_temp_free_i32(tmp32_2
);
2093 insn
= ld_code6(env
, s
->pc
);
2096 r1
= (insn
>> 36) & 0xf;
2097 x2
= (insn
>> 32) & 0xf;
2098 b2
= (insn
>> 28) & 0xf;
2099 d2
= ((int)((((insn
>> 16) & 0xfff)
2100 | ((insn
<< 4) & 0xff000)) << 12)) >> 12;
2101 disas_e3(env
, s
, op
, r1
, x2
, b2
, d2
);
2103 #ifndef CONFIG_USER_ONLY
2105 /* Test Protection */
2106 check_privileged(s
);
2107 insn
= ld_code6(env
, s
->pc
);
2109 disas_e5(env
, s
, insn
);
2113 insn
= ld_code6(env
, s
->pc
);
2116 r1
= (insn
>> 36) & 0xf;
2117 r3
= (insn
>> 32) & 0xf;
2118 b2
= (insn
>> 28) & 0xf;
2119 d2
= ((int)((((insn
>> 16) & 0xfff)
2120 | ((insn
<< 4) & 0xff000)) << 12)) >> 12;
2121 disas_eb(env
, s
, op
, r1
, r3
, b2
, d2
);
2124 insn
= ld_code6(env
, s
->pc
);
2127 r1
= (insn
>> 36) & 0xf;
2128 x2
= (insn
>> 32) & 0xf;
2129 b2
= (insn
>> 28) & 0xf;
2130 d2
= (short)((insn
>> 16) & 0xfff);
2131 r1b
= (insn
>> 12) & 0xf;
2132 disas_ed(env
, s
, op
, r1
, x2
, b2
, d2
, r1b
);
2135 qemu_log_mask(LOG_UNIMP
, "unimplemented opcode 0x%x\n", opc
);
2136 gen_illegal_opcode(s
);
2141 /* ====================================================================== */
2142 /* Define the insn format enumeration. */
2143 #define F0(N) FMT_##N,
2144 #define F1(N, X1) F0(N)
2145 #define F2(N, X1, X2) F0(N)
2146 #define F3(N, X1, X2, X3) F0(N)
2147 #define F4(N, X1, X2, X3, X4) F0(N)
2148 #define F5(N, X1, X2, X3, X4, X5) F0(N)
2151 #include "insn-format.def"
2161 /* Define a structure to hold the decoded fields. We'll store each inside
2162 an array indexed by an enum. In order to conserve memory, we'll arrange
2163 for fields that do not exist at the same time to overlap, thus the "C"
2164 for compact. For checking purposes there is an "O" for original index
2165 as well that will be applied to availability bitmaps. */
2167 enum DisasFieldIndexO
{
2190 enum DisasFieldIndexC
{
2221 struct DisasFields
{
2224 unsigned presentC
:16;
2225 unsigned int presentO
;
2229 /* This is the way fields are to be accessed out of DisasFields. */
2230 #define have_field(S, F) have_field1((S), FLD_O_##F)
2231 #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
2233 static bool have_field1(const DisasFields
*f
, enum DisasFieldIndexO c
)
2235 return (f
->presentO
>> c
) & 1;
2238 static int get_field1(const DisasFields
*f
, enum DisasFieldIndexO o
,
2239 enum DisasFieldIndexC c
)
2241 assert(have_field1(f
, o
));
2245 /* Describe the layout of each field in each format. */
2246 typedef struct DisasField
{
2248 unsigned int size
:8;
2249 unsigned int type
:2;
2250 unsigned int indexC
:6;
2251 enum DisasFieldIndexO indexO
:8;
2254 typedef struct DisasFormatInfo
{
2255 DisasField op
[NUM_C_FIELD
];
2258 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
2259 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
2260 #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
2261 { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
2262 #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
2263 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
2264 { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
2265 #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
2266 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
2267 #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
2268 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
2269 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
2270 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
2271 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
2273 #define F0(N) { { } },
2274 #define F1(N, X1) { { X1 } },
2275 #define F2(N, X1, X2) { { X1, X2 } },
2276 #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
2277 #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
2278 #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
2280 static const DisasFormatInfo format_info
[] = {
2281 #include "insn-format.def"
2299 /* Generally, we'll extract operands into this structures, operate upon
2300 them, and store them back. See the "in1", "in2", "prep", "wout" sets
2301 of routines below for more details. */
2303 bool g_out
, g_out2
, g_in1
, g_in2
;
2304 TCGv_i64 out
, out2
, in1
, in2
;
2308 /* Return values from translate_one, indicating the state of the TB. */
2310 /* Continue the TB. */
2312 /* We have emitted one or more goto_tb. No fixup required. */
2314 /* We are not using a goto_tb (for whatever reason), but have updated
2315 the PC (for whatever reason), so there's no need to do it again on
2318 /* We are exiting the TB, but have neither emitted a goto_tb, nor
2319 updated the PC for the next instruction to be executed. */
2321 /* We are ending the TB with a noreturn function call, e.g. longjmp.
2322 No following code will be executed. */
2326 typedef enum DisasFacility
{
2327 FAC_Z
, /* zarch (default) */
2328 FAC_CASS
, /* compare and swap and store */
2329 FAC_CASS2
, /* compare and swap and store 2*/
2330 FAC_DFP
, /* decimal floating point */
2331 FAC_DFPR
, /* decimal floating point rounding */
2332 FAC_DO
, /* distinct operands */
2333 FAC_EE
, /* execute extensions */
2334 FAC_EI
, /* extended immediate */
2335 FAC_FPE
, /* floating point extension */
2336 FAC_FPSSH
, /* floating point support sign handling */
2337 FAC_FPRGR
, /* FPR-GR transfer */
2338 FAC_GIE
, /* general instructions extension */
2339 FAC_HFP_MA
, /* HFP multiply-and-add/subtract */
2340 FAC_HW
, /* high-word */
2341 FAC_IEEEE_SIM
, /* IEEE exception sumilation */
2342 FAC_LOC
, /* load/store on condition */
2343 FAC_LD
, /* long displacement */
2344 FAC_PC
, /* population count */
2345 FAC_SCF
, /* store clock fast */
2346 FAC_SFLE
, /* store facility list extended */
2352 DisasFacility fac
:6;
2356 void (*help_in1
)(DisasContext
*, DisasFields
*, DisasOps
*);
2357 void (*help_in2
)(DisasContext
*, DisasFields
*, DisasOps
*);
2358 void (*help_prep
)(DisasContext
*, DisasFields
*, DisasOps
*);
2359 void (*help_wout
)(DisasContext
*, DisasFields
*, DisasOps
*);
2360 void (*help_cout
)(DisasContext
*, DisasOps
*);
2361 ExitStatus (*help_op
)(DisasContext
*, DisasOps
*);
2366 /* ====================================================================== */
2367 /* Miscelaneous helpers, used by several operations. */
2369 static void help_l2_shift(DisasContext
*s
, DisasFields
*f
,
2370 DisasOps
*o
, int mask
)
2372 int b2
= get_field(f
, b2
);
2373 int d2
= get_field(f
, d2
);
2376 o
->in2
= tcg_const_i64(d2
& mask
);
2378 o
->in2
= get_address(s
, 0, b2
, d2
);
2379 tcg_gen_andi_i64(o
->in2
, o
->in2
, mask
);
2383 static ExitStatus
help_goto_direct(DisasContext
*s
, uint64_t dest
)
2385 if (dest
== s
->next_pc
) {
2388 if (use_goto_tb(s
, dest
)) {
2389 gen_update_cc_op(s
);
2391 tcg_gen_movi_i64(psw_addr
, dest
);
2392 tcg_gen_exit_tb((tcg_target_long
)s
->tb
);
2393 return EXIT_GOTO_TB
;
2395 tcg_gen_movi_i64(psw_addr
, dest
);
2396 return EXIT_PC_UPDATED
;
2400 static ExitStatus
help_branch(DisasContext
*s
, DisasCompare
*c
,
2401 bool is_imm
, int imm
, TCGv_i64 cdest
)
2404 uint64_t dest
= s
->pc
+ 2 * imm
;
2407 /* Take care of the special cases first. */
2408 if (c
->cond
== TCG_COND_NEVER
) {
2413 if (dest
== s
->next_pc
) {
2414 /* Branch to next. */
2418 if (c
->cond
== TCG_COND_ALWAYS
) {
2419 ret
= help_goto_direct(s
, dest
);
2423 if (TCGV_IS_UNUSED_I64(cdest
)) {
2424 /* E.g. bcr %r0 -> no branch. */
2428 if (c
->cond
== TCG_COND_ALWAYS
) {
2429 tcg_gen_mov_i64(psw_addr
, cdest
);
2430 ret
= EXIT_PC_UPDATED
;
2435 if (use_goto_tb(s
, s
->next_pc
)) {
2436 if (is_imm
&& use_goto_tb(s
, dest
)) {
2437 /* Both exits can use goto_tb. */
2438 gen_update_cc_op(s
);
2440 lab
= gen_new_label();
2442 tcg_gen_brcond_i64(c
->cond
, c
->u
.s64
.a
, c
->u
.s64
.b
, lab
);
2444 tcg_gen_brcond_i32(c
->cond
, c
->u
.s32
.a
, c
->u
.s32
.b
, lab
);
2447 /* Branch not taken. */
2449 tcg_gen_movi_i64(psw_addr
, s
->next_pc
);
2450 tcg_gen_exit_tb((tcg_target_long
)s
->tb
+ 0);
2455 tcg_gen_movi_i64(psw_addr
, dest
);
2456 tcg_gen_exit_tb((tcg_target_long
)s
->tb
+ 1);
2460 /* Fallthru can use goto_tb, but taken branch cannot. */
2461 /* Store taken branch destination before the brcond. This
2462 avoids having to allocate a new local temp to hold it.
2463 We'll overwrite this in the not taken case anyway. */
2465 tcg_gen_mov_i64(psw_addr
, cdest
);
2468 lab
= gen_new_label();
2470 tcg_gen_brcond_i64(c
->cond
, c
->u
.s64
.a
, c
->u
.s64
.b
, lab
);
2472 tcg_gen_brcond_i32(c
->cond
, c
->u
.s32
.a
, c
->u
.s32
.b
, lab
);
2475 /* Branch not taken. */
2476 gen_update_cc_op(s
);
2478 tcg_gen_movi_i64(psw_addr
, s
->next_pc
);
2479 tcg_gen_exit_tb((tcg_target_long
)s
->tb
+ 0);
2483 tcg_gen_movi_i64(psw_addr
, dest
);
2485 ret
= EXIT_PC_UPDATED
;
2488 /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
2489 Most commonly we're single-stepping or some other condition that
2490 disables all use of goto_tb. Just update the PC and exit. */
2492 TCGv_i64 next
= tcg_const_i64(s
->next_pc
);
2494 cdest
= tcg_const_i64(dest
);
2498 tcg_gen_movcond_i64(c
->cond
, psw_addr
, c
->u
.s64
.a
, c
->u
.s64
.b
,
2501 TCGv_i32 t0
= tcg_temp_new_i32();
2502 TCGv_i64 t1
= tcg_temp_new_i64();
2503 TCGv_i64 z
= tcg_const_i64(0);
2504 tcg_gen_setcond_i32(c
->cond
, t0
, c
->u
.s32
.a
, c
->u
.s32
.b
);
2505 tcg_gen_extu_i32_i64(t1
, t0
);
2506 tcg_temp_free_i32(t0
);
2507 tcg_gen_movcond_i64(TCG_COND_NE
, psw_addr
, t1
, z
, cdest
, next
);
2508 tcg_temp_free_i64(t1
);
2509 tcg_temp_free_i64(z
);
2513 tcg_temp_free_i64(cdest
);
2515 tcg_temp_free_i64(next
);
2517 ret
= EXIT_PC_UPDATED
;
2525 /* ====================================================================== */
2526 /* The operations. These perform the bulk of the work for any insn,
2527 usually after the operands have been loaded and output initialized. */
2529 static ExitStatus
op_abs(DisasContext
*s
, DisasOps
*o
)
2531 gen_helper_abs_i64(o
->out
, o
->in2
);
2535 static ExitStatus
op_add(DisasContext
*s
, DisasOps
*o
)
2537 tcg_gen_add_i64(o
->out
, o
->in1
, o
->in2
);
2541 static ExitStatus
op_addc(DisasContext
*s
, DisasOps
*o
)
2545 tcg_gen_add_i64(o
->out
, o
->in1
, o
->in2
);
2547 /* XXX possible optimization point */
2549 cc
= tcg_temp_new_i64();
2550 tcg_gen_extu_i32_i64(cc
, cc_op
);
2551 tcg_gen_shri_i64(cc
, cc
, 1);
2553 tcg_gen_add_i64(o
->out
, o
->out
, cc
);
2554 tcg_temp_free_i64(cc
);
2558 static ExitStatus
op_and(DisasContext
*s
, DisasOps
*o
)
2560 tcg_gen_and_i64(o
->out
, o
->in1
, o
->in2
);
2564 static ExitStatus
op_andi(DisasContext
*s
, DisasOps
*o
)
2566 int shift
= s
->insn
->data
& 0xff;
2567 int size
= s
->insn
->data
>> 8;
2568 uint64_t mask
= ((1ull << size
) - 1) << shift
;
2571 tcg_gen_shli_i64(o
->in2
, o
->in2
, shift
);
2572 tcg_gen_ori_i64(o
->in2
, o
->in2
, ~mask
);
2573 tcg_gen_and_i64(o
->out
, o
->in1
, o
->in2
);
2575 /* Produce the CC from only the bits manipulated. */
2576 tcg_gen_andi_i64(cc_dst
, o
->out
, mask
);
2577 set_cc_nz_u64(s
, cc_dst
);
2581 static ExitStatus
op_bas(DisasContext
*s
, DisasOps
*o
)
2583 tcg_gen_movi_i64(o
->out
, pc_to_link_info(s
, s
->next_pc
));
2584 if (!TCGV_IS_UNUSED_I64(o
->in2
)) {
2585 tcg_gen_mov_i64(psw_addr
, o
->in2
);
2586 return EXIT_PC_UPDATED
;
2592 static ExitStatus
op_basi(DisasContext
*s
, DisasOps
*o
)
2594 tcg_gen_movi_i64(o
->out
, pc_to_link_info(s
, s
->next_pc
));
2595 return help_goto_direct(s
, s
->pc
+ 2 * get_field(s
->fields
, i2
));
2598 static ExitStatus
op_bc(DisasContext
*s
, DisasOps
*o
)
2600 int m1
= get_field(s
->fields
, m1
);
2601 bool is_imm
= have_field(s
->fields
, i2
);
2602 int imm
= is_imm
? get_field(s
->fields
, i2
) : 0;
2605 disas_jcc(s
, &c
, m1
);
2606 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
2609 static ExitStatus
op_bct32(DisasContext
*s
, DisasOps
*o
)
2611 int r1
= get_field(s
->fields
, r1
);
2612 bool is_imm
= have_field(s
->fields
, i2
);
2613 int imm
= is_imm
? get_field(s
->fields
, i2
) : 0;
2617 c
.cond
= TCG_COND_NE
;
2622 t
= tcg_temp_new_i64();
2623 tcg_gen_subi_i64(t
, regs
[r1
], 1);
2624 store_reg32_i64(r1
, t
);
2625 c
.u
.s32
.a
= tcg_temp_new_i32();
2626 c
.u
.s32
.b
= tcg_const_i32(0);
2627 tcg_gen_trunc_i64_i32(c
.u
.s32
.a
, t
);
2628 tcg_temp_free_i64(t
);
2630 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
2633 static ExitStatus
op_bct64(DisasContext
*s
, DisasOps
*o
)
2635 int r1
= get_field(s
->fields
, r1
);
2636 bool is_imm
= have_field(s
->fields
, i2
);
2637 int imm
= is_imm
? get_field(s
->fields
, i2
) : 0;
2640 c
.cond
= TCG_COND_NE
;
2645 tcg_gen_subi_i64(regs
[r1
], regs
[r1
], 1);
2646 c
.u
.s64
.a
= regs
[r1
];
2647 c
.u
.s64
.b
= tcg_const_i64(0);
2649 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
2652 static ExitStatus
op_clc(DisasContext
*s
, DisasOps
*o
)
2654 int l
= get_field(s
->fields
, l1
);
2659 tcg_gen_qemu_ld8u(cc_src
, o
->addr1
, get_mem_index(s
));
2660 tcg_gen_qemu_ld8u(cc_dst
, o
->in2
, get_mem_index(s
));
2663 tcg_gen_qemu_ld16u(cc_src
, o
->addr1
, get_mem_index(s
));
2664 tcg_gen_qemu_ld16u(cc_dst
, o
->in2
, get_mem_index(s
));
2667 tcg_gen_qemu_ld32u(cc_src
, o
->addr1
, get_mem_index(s
));
2668 tcg_gen_qemu_ld32u(cc_dst
, o
->in2
, get_mem_index(s
));
2671 tcg_gen_qemu_ld64(cc_src
, o
->addr1
, get_mem_index(s
));
2672 tcg_gen_qemu_ld64(cc_dst
, o
->in2
, get_mem_index(s
));
2675 potential_page_fault(s
);
2676 vl
= tcg_const_i32(l
);
2677 gen_helper_clc(cc_op
, cpu_env
, vl
, o
->addr1
, o
->in2
);
2678 tcg_temp_free_i32(vl
);
2682 gen_op_update2_cc_i64(s
, CC_OP_LTUGTU_64
, cc_src
, cc_dst
);
2686 static ExitStatus
op_clcle(DisasContext
*s
, DisasOps
*o
)
2688 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2689 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
2690 potential_page_fault(s
);
2691 gen_helper_clcle(cc_op
, cpu_env
, r1
, o
->in2
, r3
);
2692 tcg_temp_free_i32(r1
);
2693 tcg_temp_free_i32(r3
);
2698 static ExitStatus
op_cvd(DisasContext
*s
, DisasOps
*o
)
2700 TCGv_i64 t1
= tcg_temp_new_i64();
2701 TCGv_i32 t2
= tcg_temp_new_i32();
2702 tcg_gen_trunc_i64_i32(t2
, o
->in1
);
2703 gen_helper_cvd(t1
, t2
);
2704 tcg_temp_free_i32(t2
);
2705 tcg_gen_qemu_st64(t1
, o
->in2
, get_mem_index(s
));
2706 tcg_temp_free_i64(t1
);
2710 #ifndef CONFIG_USER_ONLY
2711 static ExitStatus
op_diag(DisasContext
*s
, DisasOps
*o
)
2715 check_privileged(s
);
2716 potential_page_fault(s
);
2718 /* We pretend the format is RX_a so that D2 is the field we want. */
2719 tmp
= tcg_const_i32(get_field(s
->fields
, d2
) & 0xfff);
2720 gen_helper_diag(regs
[2], cpu_env
, tmp
, regs
[2], regs
[1]);
2721 tcg_temp_free_i32(tmp
);
2726 static ExitStatus
op_divs32(DisasContext
*s
, DisasOps
*o
)
2728 gen_helper_divs32(o
->out2
, cpu_env
, o
->in1
, o
->in2
);
2729 return_low128(o
->out
);
2733 static ExitStatus
op_divu32(DisasContext
*s
, DisasOps
*o
)
2735 gen_helper_divu32(o
->out2
, cpu_env
, o
->in1
, o
->in2
);
2736 return_low128(o
->out
);
2740 static ExitStatus
op_divs64(DisasContext
*s
, DisasOps
*o
)
2742 gen_helper_divs64(o
->out2
, cpu_env
, o
->in1
, o
->in2
);
2743 return_low128(o
->out
);
2747 static ExitStatus
op_divu64(DisasContext
*s
, DisasOps
*o
)
2749 gen_helper_divu64(o
->out2
, cpu_env
, o
->out
, o
->out2
, o
->in2
);
2750 return_low128(o
->out
);
2754 static ExitStatus
op_efpc(DisasContext
*s
, DisasOps
*o
)
2756 tcg_gen_ld32u_i64(o
->out
, cpu_env
, offsetof(CPUS390XState
, fpc
));
2760 static ExitStatus
op_ex(DisasContext
*s
, DisasOps
*o
)
2762 /* ??? Perhaps a better way to implement EXECUTE is to set a bit in
2763 tb->flags, (ab)use the tb->cs_base field as the address of
2764 the template in memory, and grab 8 bits of tb->flags/cflags for
2765 the contents of the register. We would then recognize all this
2766 in gen_intermediate_code_internal, generating code for exactly
2767 one instruction. This new TB then gets executed normally.
2769 On the other hand, this seems to be mostly used for modifying
2770 MVC inside of memcpy, which needs a helper call anyway. So
2771 perhaps this doesn't bear thinking about any further. */
2778 tmp
= tcg_const_i64(s
->next_pc
);
2779 gen_helper_ex(cc_op
, cpu_env
, cc_op
, o
->in1
, o
->in2
, tmp
);
2780 tcg_temp_free_i64(tmp
);
2786 static ExitStatus
op_icm(DisasContext
*s
, DisasOps
*o
)
2788 int m3
= get_field(s
->fields
, m3
);
2789 int pos
, len
, base
= s
->insn
->data
;
2790 TCGv_i64 tmp
= tcg_temp_new_i64();
2795 /* Effectively a 32-bit load. */
2796 tcg_gen_qemu_ld32u(tmp
, o
->in2
, get_mem_index(s
));
2803 /* Effectively a 16-bit load. */
2804 tcg_gen_qemu_ld16u(tmp
, o
->in2
, get_mem_index(s
));
2812 /* Effectively an 8-bit load. */
2813 tcg_gen_qemu_ld8u(tmp
, o
->in2
, get_mem_index(s
));
2818 pos
= base
+ ctz32(m3
) * 8;
2819 tcg_gen_deposit_i64(o
->out
, o
->out
, tmp
, pos
, len
);
2820 ccm
= ((1ull << len
) - 1) << pos
;
2824 /* This is going to be a sequence of loads and inserts. */
2825 pos
= base
+ 32 - 8;
2829 tcg_gen_qemu_ld8u(tmp
, o
->in2
, get_mem_index(s
));
2830 tcg_gen_addi_i64(o
->in2
, o
->in2
, 1);
2831 tcg_gen_deposit_i64(o
->out
, o
->out
, tmp
, pos
, 8);
2834 m3
= (m3
<< 1) & 0xf;
2840 tcg_gen_movi_i64(tmp
, ccm
);
2841 gen_op_update2_cc_i64(s
, CC_OP_ICM
, tmp
, o
->out
);
2842 tcg_temp_free_i64(tmp
);
2846 static ExitStatus
op_insi(DisasContext
*s
, DisasOps
*o
)
2848 int shift
= s
->insn
->data
& 0xff;
2849 int size
= s
->insn
->data
>> 8;
2850 tcg_gen_deposit_i64(o
->out
, o
->in1
, o
->in2
, shift
, size
);
2854 static ExitStatus
op_ld8s(DisasContext
*s
, DisasOps
*o
)
2856 tcg_gen_qemu_ld8s(o
->out
, o
->in2
, get_mem_index(s
));
2860 static ExitStatus
op_ld8u(DisasContext
*s
, DisasOps
*o
)
2862 tcg_gen_qemu_ld8u(o
->out
, o
->in2
, get_mem_index(s
));
2866 static ExitStatus
op_ld16s(DisasContext
*s
, DisasOps
*o
)
2868 tcg_gen_qemu_ld16s(o
->out
, o
->in2
, get_mem_index(s
));
2872 static ExitStatus
op_ld16u(DisasContext
*s
, DisasOps
*o
)
2874 tcg_gen_qemu_ld16u(o
->out
, o
->in2
, get_mem_index(s
));
2878 static ExitStatus
op_ld32s(DisasContext
*s
, DisasOps
*o
)
2880 tcg_gen_qemu_ld32s(o
->out
, o
->in2
, get_mem_index(s
));
2884 static ExitStatus
op_ld32u(DisasContext
*s
, DisasOps
*o
)
2886 tcg_gen_qemu_ld32u(o
->out
, o
->in2
, get_mem_index(s
));
2890 static ExitStatus
op_ld64(DisasContext
*s
, DisasOps
*o
)
2892 tcg_gen_qemu_ld64(o
->out
, o
->in2
, get_mem_index(s
));
2896 #ifndef CONFIG_USER_ONLY
2897 static ExitStatus
op_lra(DisasContext
*s
, DisasOps
*o
)
2899 check_privileged(s
);
2900 potential_page_fault(s
);
2901 gen_helper_lra(o
->out
, cpu_env
, o
->in2
);
2906 static ExitStatus
op_lpsw(DisasContext
*s
, DisasOps
*o
)
2910 check_privileged(s
);
2912 t1
= tcg_temp_new_i64();
2913 t2
= tcg_temp_new_i64();
2914 tcg_gen_qemu_ld32u(t1
, o
->in2
, get_mem_index(s
));
2915 tcg_gen_addi_i64(o
->in2
, o
->in2
, 4);
2916 tcg_gen_qemu_ld32u(t2
, o
->in2
, get_mem_index(s
));
2917 /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
2918 tcg_gen_shli_i64(t1
, t1
, 32);
2919 gen_helper_load_psw(cpu_env
, t1
, t2
);
2920 tcg_temp_free_i64(t1
);
2921 tcg_temp_free_i64(t2
);
2922 return EXIT_NORETURN
;
2926 static ExitStatus
op_lam(DisasContext
*s
, DisasOps
*o
)
2928 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
2929 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
2930 potential_page_fault(s
);
2931 gen_helper_lam(cpu_env
, r1
, o
->in2
, r3
);
2932 tcg_temp_free_i32(r1
);
2933 tcg_temp_free_i32(r3
);
2937 static ExitStatus
op_lm32(DisasContext
*s
, DisasOps
*o
)
2939 int r1
= get_field(s
->fields
, r1
);
2940 int r3
= get_field(s
->fields
, r3
);
2941 TCGv_i64 t
= tcg_temp_new_i64();
2942 TCGv_i64 t4
= tcg_const_i64(4);
2945 tcg_gen_qemu_ld32u(t
, o
->in2
, get_mem_index(s
));
2946 store_reg32_i64(r1
, t
);
2950 tcg_gen_add_i64(o
->in2
, o
->in2
, t4
);
2954 tcg_temp_free_i64(t
);
2955 tcg_temp_free_i64(t4
);
2959 static ExitStatus
op_lmh(DisasContext
*s
, DisasOps
*o
)
2961 int r1
= get_field(s
->fields
, r1
);
2962 int r3
= get_field(s
->fields
, r3
);
2963 TCGv_i64 t
= tcg_temp_new_i64();
2964 TCGv_i64 t4
= tcg_const_i64(4);
2967 tcg_gen_qemu_ld32u(t
, o
->in2
, get_mem_index(s
));
2968 store_reg32h_i64(r1
, t
);
2972 tcg_gen_add_i64(o
->in2
, o
->in2
, t4
);
2976 tcg_temp_free_i64(t
);
2977 tcg_temp_free_i64(t4
);
2981 static ExitStatus
op_lm64(DisasContext
*s
, DisasOps
*o
)
2983 int r1
= get_field(s
->fields
, r1
);
2984 int r3
= get_field(s
->fields
, r3
);
2985 TCGv_i64 t8
= tcg_const_i64(8);
2988 tcg_gen_qemu_ld64(regs
[r1
], o
->in2
, get_mem_index(s
));
2992 tcg_gen_add_i64(o
->in2
, o
->in2
, t8
);
2996 tcg_temp_free_i64(t8
);
3000 static ExitStatus
op_mov2(DisasContext
*s
, DisasOps
*o
)
3003 o
->g_out
= o
->g_in2
;
3004 TCGV_UNUSED_I64(o
->in2
);
3009 static ExitStatus
op_movx(DisasContext
*s
, DisasOps
*o
)
3013 o
->g_out
= o
->g_in1
;
3014 o
->g_out2
= o
->g_in2
;
3015 TCGV_UNUSED_I64(o
->in1
);
3016 TCGV_UNUSED_I64(o
->in2
);
3017 o
->g_in1
= o
->g_in2
= false;
3021 static ExitStatus
op_mvc(DisasContext
*s
, DisasOps
*o
)
3023 TCGv_i32 l
= tcg_const_i32(get_field(s
->fields
, l1
));
3024 potential_page_fault(s
);
3025 gen_helper_mvc(cpu_env
, l
, o
->addr1
, o
->in2
);
3026 tcg_temp_free_i32(l
);
3030 static ExitStatus
op_mvcl(DisasContext
*s
, DisasOps
*o
)
3032 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
3033 TCGv_i32 r2
= tcg_const_i32(get_field(s
->fields
, r2
));
3034 potential_page_fault(s
);
3035 gen_helper_mvcl(cc_op
, cpu_env
, r1
, r2
);
3036 tcg_temp_free_i32(r1
);
3037 tcg_temp_free_i32(r2
);
3042 static ExitStatus
op_mvcle(DisasContext
*s
, DisasOps
*o
)
3044 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
3045 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
3046 potential_page_fault(s
);
3047 gen_helper_mvcle(cc_op
, cpu_env
, r1
, o
->in2
, r3
);
3048 tcg_temp_free_i32(r1
);
3049 tcg_temp_free_i32(r3
);
3054 #ifndef CONFIG_USER_ONLY
3055 static ExitStatus
op_mvcp(DisasContext
*s
, DisasOps
*o
)
3057 int r1
= get_field(s
->fields
, l1
);
3058 check_privileged(s
);
3059 potential_page_fault(s
);
3060 gen_helper_mvcp(cc_op
, cpu_env
, regs
[r1
], o
->addr1
, o
->in2
);
3065 static ExitStatus
op_mvcs(DisasContext
*s
, DisasOps
*o
)
3067 int r1
= get_field(s
->fields
, l1
);
3068 check_privileged(s
);
3069 potential_page_fault(s
);
3070 gen_helper_mvcs(cc_op
, cpu_env
, regs
[r1
], o
->addr1
, o
->in2
);
3076 static ExitStatus
op_mul(DisasContext
*s
, DisasOps
*o
)
3078 tcg_gen_mul_i64(o
->out
, o
->in1
, o
->in2
);
3082 static ExitStatus
op_mul128(DisasContext
*s
, DisasOps
*o
)
3084 gen_helper_mul128(o
->out
, cpu_env
, o
->in1
, o
->in2
);
3085 return_low128(o
->out2
);
3089 static ExitStatus
op_nabs(DisasContext
*s
, DisasOps
*o
)
3091 gen_helper_nabs_i64(o
->out
, o
->in2
);
3095 static ExitStatus
op_nc(DisasContext
*s
, DisasOps
*o
)
3097 TCGv_i32 l
= tcg_const_i32(get_field(s
->fields
, l1
));
3098 potential_page_fault(s
);
3099 gen_helper_nc(cc_op
, cpu_env
, l
, o
->addr1
, o
->in2
);
3100 tcg_temp_free_i32(l
);
3105 static ExitStatus
op_neg(DisasContext
*s
, DisasOps
*o
)
3107 tcg_gen_neg_i64(o
->out
, o
->in2
);
3111 static ExitStatus
op_oc(DisasContext
*s
, DisasOps
*o
)
3113 TCGv_i32 l
= tcg_const_i32(get_field(s
->fields
, l1
));
3114 potential_page_fault(s
);
3115 gen_helper_oc(cc_op
, cpu_env
, l
, o
->addr1
, o
->in2
);
3116 tcg_temp_free_i32(l
);
3121 static ExitStatus
op_or(DisasContext
*s
, DisasOps
*o
)
3123 tcg_gen_or_i64(o
->out
, o
->in1
, o
->in2
);
3127 static ExitStatus
op_ori(DisasContext
*s
, DisasOps
*o
)
3129 int shift
= s
->insn
->data
& 0xff;
3130 int size
= s
->insn
->data
>> 8;
3131 uint64_t mask
= ((1ull << size
) - 1) << shift
;
3134 tcg_gen_shli_i64(o
->in2
, o
->in2
, shift
);
3135 tcg_gen_or_i64(o
->out
, o
->in1
, o
->in2
);
3137 /* Produce the CC from only the bits manipulated. */
3138 tcg_gen_andi_i64(cc_dst
, o
->out
, mask
);
3139 set_cc_nz_u64(s
, cc_dst
);
3143 static ExitStatus
op_rll32(DisasContext
*s
, DisasOps
*o
)
3145 TCGv_i32 t1
= tcg_temp_new_i32();
3146 TCGv_i32 t2
= tcg_temp_new_i32();
3147 TCGv_i32 to
= tcg_temp_new_i32();
3148 tcg_gen_trunc_i64_i32(t1
, o
->in1
);
3149 tcg_gen_trunc_i64_i32(t2
, o
->in2
);
3150 tcg_gen_rotl_i32(to
, t1
, t2
);
3151 tcg_gen_extu_i32_i64(o
->out
, to
);
3152 tcg_temp_free_i32(t1
);
3153 tcg_temp_free_i32(t2
);
3154 tcg_temp_free_i32(to
);
3158 static ExitStatus
op_rll64(DisasContext
*s
, DisasOps
*o
)
3160 tcg_gen_rotl_i64(o
->out
, o
->in1
, o
->in2
);
3164 #ifndef CONFIG_USER_ONLY
3165 static ExitStatus
op_sigp(DisasContext
*s
, DisasOps
*o
)
3167 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
3168 check_privileged(s
);
3169 potential_page_fault(s
);
3170 gen_helper_sigp(cc_op
, cpu_env
, o
->in2
, r1
, o
->in1
);
3171 tcg_temp_free_i32(r1
);
3176 static ExitStatus
op_sla(DisasContext
*s
, DisasOps
*o
)
3178 uint64_t sign
= 1ull << s
->insn
->data
;
3179 enum cc_op cco
= s
->insn
->data
== 31 ? CC_OP_SLA_32
: CC_OP_SLA_64
;
3180 gen_op_update2_cc_i64(s
, cco
, o
->in1
, o
->in2
);
3181 tcg_gen_shl_i64(o
->out
, o
->in1
, o
->in2
);
3182 /* The arithmetic left shift is curious in that it does not affect
3183 the sign bit. Copy that over from the source unchanged. */
3184 tcg_gen_andi_i64(o
->out
, o
->out
, ~sign
);
3185 tcg_gen_andi_i64(o
->in1
, o
->in1
, sign
);
3186 tcg_gen_or_i64(o
->out
, o
->out
, o
->in1
);
3190 static ExitStatus
op_sll(DisasContext
*s
, DisasOps
*o
)
3192 tcg_gen_shl_i64(o
->out
, o
->in1
, o
->in2
);
3196 static ExitStatus
op_sra(DisasContext
*s
, DisasOps
*o
)
3198 tcg_gen_sar_i64(o
->out
, o
->in1
, o
->in2
);
3202 static ExitStatus
op_srl(DisasContext
*s
, DisasOps
*o
)
3204 tcg_gen_shr_i64(o
->out
, o
->in1
, o
->in2
);
3208 #ifndef CONFIG_USER_ONLY
3209 static ExitStatus
op_ssm(DisasContext
*s
, DisasOps
*o
)
3211 check_privileged(s
);
3212 tcg_gen_deposit_i64(psw_mask
, psw_mask
, o
->in2
, 56, 8);
3216 static ExitStatus
op_stnosm(DisasContext
*s
, DisasOps
*o
)
3218 uint64_t i2
= get_field(s
->fields
, i2
);
3221 check_privileged(s
);
3223 /* It is important to do what the instruction name says: STORE THEN.
3224 If we let the output hook perform the store then if we fault and
3225 restart, we'll have the wrong SYSTEM MASK in place. */
3226 t
= tcg_temp_new_i64();
3227 tcg_gen_shri_i64(t
, psw_mask
, 56);
3228 tcg_gen_qemu_st8(t
, o
->addr1
, get_mem_index(s
));
3229 tcg_temp_free_i64(t
);
3231 if (s
->fields
->op
== 0xac) {
3232 tcg_gen_andi_i64(psw_mask
, psw_mask
,
3233 (i2
<< 56) | 0x00ffffffffffffffull
);
3235 tcg_gen_ori_i64(psw_mask
, psw_mask
, i2
<< 56);
3241 static ExitStatus
op_st8(DisasContext
*s
, DisasOps
*o
)
3243 tcg_gen_qemu_st8(o
->in1
, o
->in2
, get_mem_index(s
));
3247 static ExitStatus
op_st16(DisasContext
*s
, DisasOps
*o
)
3249 tcg_gen_qemu_st16(o
->in1
, o
->in2
, get_mem_index(s
));
3253 static ExitStatus
op_st32(DisasContext
*s
, DisasOps
*o
)
3255 tcg_gen_qemu_st32(o
->in1
, o
->in2
, get_mem_index(s
));
3259 static ExitStatus
op_st64(DisasContext
*s
, DisasOps
*o
)
3261 tcg_gen_qemu_st64(o
->in1
, o
->in2
, get_mem_index(s
));
3265 static ExitStatus
op_stam(DisasContext
*s
, DisasOps
*o
)
3267 TCGv_i32 r1
= tcg_const_i32(get_field(s
->fields
, r1
));
3268 TCGv_i32 r3
= tcg_const_i32(get_field(s
->fields
, r3
));
3269 potential_page_fault(s
);
3270 gen_helper_stam(cpu_env
, r1
, o
->in2
, r3
);
3271 tcg_temp_free_i32(r1
);
3272 tcg_temp_free_i32(r3
);
3276 static ExitStatus
op_stm(DisasContext
*s
, DisasOps
*o
)
3278 int r1
= get_field(s
->fields
, r1
);
3279 int r3
= get_field(s
->fields
, r3
);
3280 int size
= s
->insn
->data
;
3281 TCGv_i64 tsize
= tcg_const_i64(size
);
3285 tcg_gen_qemu_st64(regs
[r1
], o
->in2
, get_mem_index(s
));
3287 tcg_gen_qemu_st32(regs
[r1
], o
->in2
, get_mem_index(s
));
3292 tcg_gen_add_i64(o
->in2
, o
->in2
, tsize
);
3296 tcg_temp_free_i64(tsize
);
3300 static ExitStatus
op_stmh(DisasContext
*s
, DisasOps
*o
)
3302 int r1
= get_field(s
->fields
, r1
);
3303 int r3
= get_field(s
->fields
, r3
);
3304 TCGv_i64 t
= tcg_temp_new_i64();
3305 TCGv_i64 t4
= tcg_const_i64(4);
3306 TCGv_i64 t32
= tcg_const_i64(32);
3309 tcg_gen_shl_i64(t
, regs
[r1
], t32
);
3310 tcg_gen_qemu_st32(t
, o
->in2
, get_mem_index(s
));
3314 tcg_gen_add_i64(o
->in2
, o
->in2
, t4
);
3318 tcg_temp_free_i64(t
);
3319 tcg_temp_free_i64(t4
);
3320 tcg_temp_free_i64(t32
);
3324 static ExitStatus
op_sub(DisasContext
*s
, DisasOps
*o
)
3326 tcg_gen_sub_i64(o
->out
, o
->in1
, o
->in2
);
3330 static ExitStatus
op_subb(DisasContext
*s
, DisasOps
*o
)
3335 tcg_gen_not_i64(o
->in2
, o
->in2
);
3336 tcg_gen_add_i64(o
->out
, o
->in1
, o
->in2
);
3338 /* XXX possible optimization point */
3340 cc
= tcg_temp_new_i64();
3341 tcg_gen_extu_i32_i64(cc
, cc_op
);
3342 tcg_gen_shri_i64(cc
, cc
, 1);
3343 tcg_gen_add_i64(o
->out
, o
->out
, cc
);
3344 tcg_temp_free_i64(cc
);
3348 static ExitStatus
op_svc(DisasContext
*s
, DisasOps
*o
)
3355 t
= tcg_const_i32(get_field(s
->fields
, i1
) & 0xff);
3356 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUS390XState
, int_svc_code
));
3357 tcg_temp_free_i32(t
);
3359 t
= tcg_const_i32(s
->next_pc
- s
->pc
);
3360 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUS390XState
, int_svc_ilen
));
3361 tcg_temp_free_i32(t
);
3363 gen_exception(EXCP_SVC
);
3364 return EXIT_NORETURN
;
3367 static ExitStatus
op_tr(DisasContext
*s
, DisasOps
*o
)
3369 TCGv_i32 l
= tcg_const_i32(get_field(s
->fields
, l1
));
3370 potential_page_fault(s
);
3371 gen_helper_tr(cpu_env
, l
, o
->addr1
, o
->in2
);
3372 tcg_temp_free_i32(l
);
3377 static ExitStatus
op_unpk(DisasContext
*s
, DisasOps
*o
)
3379 TCGv_i32 l
= tcg_const_i32(get_field(s
->fields
, l1
));
3380 potential_page_fault(s
);
3381 gen_helper_unpk(cpu_env
, l
, o
->addr1
, o
->in2
);
3382 tcg_temp_free_i32(l
);
3386 static ExitStatus
op_xc(DisasContext
*s
, DisasOps
*o
)
3388 TCGv_i32 l
= tcg_const_i32(get_field(s
->fields
, l1
));
3389 potential_page_fault(s
);
3390 gen_helper_xc(cc_op
, cpu_env
, l
, o
->addr1
, o
->in2
);
3391 tcg_temp_free_i32(l
);
3396 static ExitStatus
op_xor(DisasContext
*s
, DisasOps
*o
)
3398 tcg_gen_xor_i64(o
->out
, o
->in1
, o
->in2
);
3402 static ExitStatus
op_xori(DisasContext
*s
, DisasOps
*o
)
3404 int shift
= s
->insn
->data
& 0xff;
3405 int size
= s
->insn
->data
>> 8;
3406 uint64_t mask
= ((1ull << size
) - 1) << shift
;
3409 tcg_gen_shli_i64(o
->in2
, o
->in2
, shift
);
3410 tcg_gen_xor_i64(o
->out
, o
->in1
, o
->in2
);
3412 /* Produce the CC from only the bits manipulated. */
3413 tcg_gen_andi_i64(cc_dst
, o
->out
, mask
);
3414 set_cc_nz_u64(s
, cc_dst
);
3418 /* ====================================================================== */
3419 /* The "Cc OUTput" generators. Given the generated output (and in some cases
3420 the original inputs), update the various cc data structures in order to
3421 be able to compute the new condition code. */
3423 static void cout_abs32(DisasContext
*s
, DisasOps
*o
)
3425 gen_op_update1_cc_i64(s
, CC_OP_ABS_32
, o
->out
);
3428 static void cout_abs64(DisasContext
*s
, DisasOps
*o
)
3430 gen_op_update1_cc_i64(s
, CC_OP_ABS_64
, o
->out
);
3433 static void cout_adds32(DisasContext
*s
, DisasOps
*o
)
3435 gen_op_update3_cc_i64(s
, CC_OP_ADD_32
, o
->in1
, o
->in2
, o
->out
);
3438 static void cout_adds64(DisasContext
*s
, DisasOps
*o
)
3440 gen_op_update3_cc_i64(s
, CC_OP_ADD_64
, o
->in1
, o
->in2
, o
->out
);
3443 static void cout_addu32(DisasContext
*s
, DisasOps
*o
)
3445 gen_op_update3_cc_i64(s
, CC_OP_ADDU_32
, o
->in1
, o
->in2
, o
->out
);
3448 static void cout_addu64(DisasContext
*s
, DisasOps
*o
)
3450 gen_op_update3_cc_i64(s
, CC_OP_ADDU_64
, o
->in1
, o
->in2
, o
->out
);
3453 static void cout_addc32(DisasContext
*s
, DisasOps
*o
)
3455 gen_op_update3_cc_i64(s
, CC_OP_ADDC_32
, o
->in1
, o
->in2
, o
->out
);
3458 static void cout_addc64(DisasContext
*s
, DisasOps
*o
)
3460 gen_op_update3_cc_i64(s
, CC_OP_ADDC_64
, o
->in1
, o
->in2
, o
->out
);
3463 static void cout_cmps32(DisasContext
*s
, DisasOps
*o
)
3465 gen_op_update2_cc_i64(s
, CC_OP_LTGT_32
, o
->in1
, o
->in2
);
3468 static void cout_cmps64(DisasContext
*s
, DisasOps
*o
)
3470 gen_op_update2_cc_i64(s
, CC_OP_LTGT_64
, o
->in1
, o
->in2
);
3473 static void cout_cmpu32(DisasContext
*s
, DisasOps
*o
)
3475 gen_op_update2_cc_i64(s
, CC_OP_LTUGTU_32
, o
->in1
, o
->in2
);
3478 static void cout_cmpu64(DisasContext
*s
, DisasOps
*o
)
3480 gen_op_update2_cc_i64(s
, CC_OP_LTUGTU_64
, o
->in1
, o
->in2
);
3483 static void cout_nabs32(DisasContext
*s
, DisasOps
*o
)
3485 gen_op_update1_cc_i64(s
, CC_OP_NABS_32
, o
->out
);
3488 static void cout_nabs64(DisasContext
*s
, DisasOps
*o
)
3490 gen_op_update1_cc_i64(s
, CC_OP_NABS_64
, o
->out
);
3493 static void cout_neg32(DisasContext
*s
, DisasOps
*o
)
3495 gen_op_update1_cc_i64(s
, CC_OP_COMP_32
, o
->out
);
3498 static void cout_neg64(DisasContext
*s
, DisasOps
*o
)
3500 gen_op_update1_cc_i64(s
, CC_OP_COMP_64
, o
->out
);
3503 static void cout_nz32(DisasContext
*s
, DisasOps
*o
)
3505 tcg_gen_ext32u_i64(cc_dst
, o
->out
);
3506 gen_op_update1_cc_i64(s
, CC_OP_NZ
, cc_dst
);
3509 static void cout_nz64(DisasContext
*s
, DisasOps
*o
)
3511 gen_op_update1_cc_i64(s
, CC_OP_NZ
, o
->out
);
3514 static void cout_s32(DisasContext
*s
, DisasOps
*o
)
3516 gen_op_update1_cc_i64(s
, CC_OP_LTGT0_32
, o
->out
);
3519 static void cout_s64(DisasContext
*s
, DisasOps
*o
)
3521 gen_op_update1_cc_i64(s
, CC_OP_LTGT0_64
, o
->out
);
3524 static void cout_subs32(DisasContext
*s
, DisasOps
*o
)
3526 gen_op_update3_cc_i64(s
, CC_OP_SUB_32
, o
->in1
, o
->in2
, o
->out
);
3529 static void cout_subs64(DisasContext
*s
, DisasOps
*o
)
3531 gen_op_update3_cc_i64(s
, CC_OP_SUB_64
, o
->in1
, o
->in2
, o
->out
);
3534 static void cout_subu32(DisasContext
*s
, DisasOps
*o
)
3536 gen_op_update3_cc_i64(s
, CC_OP_SUBU_32
, o
->in1
, o
->in2
, o
->out
);
3539 static void cout_subu64(DisasContext
*s
, DisasOps
*o
)
3541 gen_op_update3_cc_i64(s
, CC_OP_SUBU_64
, o
->in1
, o
->in2
, o
->out
);
3544 static void cout_subb32(DisasContext
*s
, DisasOps
*o
)
3546 gen_op_update3_cc_i64(s
, CC_OP_SUBB_32
, o
->in1
, o
->in2
, o
->out
);
3549 static void cout_subb64(DisasContext
*s
, DisasOps
*o
)
3551 gen_op_update3_cc_i64(s
, CC_OP_SUBB_64
, o
->in1
, o
->in2
, o
->out
);
3554 static void cout_tm32(DisasContext
*s
, DisasOps
*o
)
3556 gen_op_update2_cc_i64(s
, CC_OP_TM_32
, o
->in1
, o
->in2
);
3559 static void cout_tm64(DisasContext
*s
, DisasOps
*o
)
3561 gen_op_update2_cc_i64(s
, CC_OP_TM_64
, o
->in1
, o
->in2
);
3564 /* ====================================================================== */
3565 /* The "PREPeration" generators. These initialize the DisasOps.OUT fields
3566 with the TCG register to which we will write. Used in combination with
3567 the "wout" generators, in some cases we need a new temporary, and in
3568 some cases we can write to a TCG global. */
3570 static void prep_new(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3572 o
->out
= tcg_temp_new_i64();
3575 static void prep_new_P(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3577 o
->out
= tcg_temp_new_i64();
3578 o
->out2
= tcg_temp_new_i64();
3581 static void prep_r1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3583 o
->out
= regs
[get_field(f
, r1
)];
3587 static void prep_r1_P(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3589 /* ??? Specification exception: r1 must be even. */
3590 int r1
= get_field(f
, r1
);
3592 o
->out2
= regs
[(r1
+ 1) & 15];
3593 o
->g_out
= o
->g_out2
= true;
3596 /* ====================================================================== */
3597 /* The "Write OUTput" generators. These generally perform some non-trivial
3598 copy of data to TCG globals, or to main memory. The trivial cases are
3599 generally handled by having a "prep" generator install the TCG global
3600 as the destination of the operation. */
3602 static void wout_r1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3604 store_reg(get_field(f
, r1
), o
->out
);
3607 static void wout_r1_8(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3609 int r1
= get_field(f
, r1
);
3610 tcg_gen_deposit_i64(regs
[r1
], regs
[r1
], o
->out
, 0, 8);
3613 static void wout_r1_32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3615 store_reg32_i64(get_field(f
, r1
), o
->out
);
3618 static void wout_r1_P32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3620 /* ??? Specification exception: r1 must be even. */
3621 int r1
= get_field(f
, r1
);
3622 store_reg32_i64(r1
, o
->out
);
3623 store_reg32_i64((r1
+ 1) & 15, o
->out2
);
3626 static void wout_r1_D32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3628 /* ??? Specification exception: r1 must be even. */
3629 int r1
= get_field(f
, r1
);
3630 store_reg32_i64((r1
+ 1) & 15, o
->out
);
3631 tcg_gen_shri_i64(o
->out
, o
->out
, 32);
3632 store_reg32_i64(r1
, o
->out
);
3635 static void wout_e1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3637 store_freg32_i64(get_field(f
, r1
), o
->out
);
3640 static void wout_f1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3642 store_freg(get_field(f
, r1
), o
->out
);
3645 static void wout_x1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3647 int f1
= get_field(s
->fields
, r1
);
3648 store_freg(f1
, o
->out
);
3649 store_freg((f1
+ 2) & 15, o
->out2
);
3652 static void wout_cond_r1r2_32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3654 if (get_field(f
, r1
) != get_field(f
, r2
)) {
3655 store_reg32_i64(get_field(f
, r1
), o
->out
);
3659 static void wout_cond_e1e2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3661 if (get_field(f
, r1
) != get_field(f
, r2
)) {
3662 store_freg32_i64(get_field(f
, r1
), o
->out
);
3666 static void wout_m1_8(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3668 tcg_gen_qemu_st8(o
->out
, o
->addr1
, get_mem_index(s
));
3671 static void wout_m1_16(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3673 tcg_gen_qemu_st16(o
->out
, o
->addr1
, get_mem_index(s
));
3676 static void wout_m1_32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3678 tcg_gen_qemu_st32(o
->out
, o
->addr1
, get_mem_index(s
));
3681 static void wout_m1_64(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3683 tcg_gen_qemu_st64(o
->out
, o
->addr1
, get_mem_index(s
));
3686 static void wout_m2_32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3688 tcg_gen_qemu_st32(o
->out
, o
->in2
, get_mem_index(s
));
3691 /* ====================================================================== */
3692 /* The "INput 1" generators. These load the first operand to an insn. */
3694 static void in1_r1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3696 o
->in1
= load_reg(get_field(f
, r1
));
3699 static void in1_r1_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3701 o
->in1
= regs
[get_field(f
, r1
)];
3705 static void in1_r1_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3707 o
->in1
= tcg_temp_new_i64();
3708 tcg_gen_ext32s_i64(o
->in1
, regs
[get_field(f
, r1
)]);
3711 static void in1_r1_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3713 o
->in1
= tcg_temp_new_i64();
3714 tcg_gen_ext32u_i64(o
->in1
, regs
[get_field(f
, r1
)]);
3717 static void in1_r1p1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3719 /* ??? Specification exception: r1 must be even. */
3720 int r1
= get_field(f
, r1
);
3721 o
->in1
= load_reg((r1
+ 1) & 15);
3724 static void in1_r1p1_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3726 /* ??? Specification exception: r1 must be even. */
3727 int r1
= get_field(f
, r1
);
3728 o
->in1
= tcg_temp_new_i64();
3729 tcg_gen_ext32s_i64(o
->in1
, regs
[(r1
+ 1) & 15]);
3732 static void in1_r1p1_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3734 /* ??? Specification exception: r1 must be even. */
3735 int r1
= get_field(f
, r1
);
3736 o
->in1
= tcg_temp_new_i64();
3737 tcg_gen_ext32u_i64(o
->in1
, regs
[(r1
+ 1) & 15]);
3740 static void in1_r1_D32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3742 /* ??? Specification exception: r1 must be even. */
3743 int r1
= get_field(f
, r1
);
3744 o
->in1
= tcg_temp_new_i64();
3745 tcg_gen_concat32_i64(o
->in1
, regs
[r1
+ 1], regs
[r1
]);
3748 static void in1_r2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3750 o
->in1
= load_reg(get_field(f
, r2
));
3753 static void in1_r3(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3755 o
->in1
= load_reg(get_field(f
, r3
));
3758 static void in1_r3_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3760 o
->in1
= regs
[get_field(f
, r3
)];
3764 static void in1_r3_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3766 o
->in1
= tcg_temp_new_i64();
3767 tcg_gen_ext32s_i64(o
->in1
, regs
[get_field(f
, r3
)]);
3770 static void in1_r3_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3772 o
->in1
= tcg_temp_new_i64();
3773 tcg_gen_ext32u_i64(o
->in1
, regs
[get_field(f
, r3
)]);
3776 static void in1_e1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3778 o
->in1
= load_freg32_i64(get_field(f
, r1
));
3781 static void in1_f1_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3783 o
->in1
= fregs
[get_field(f
, r1
)];
3787 static void in1_la1(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3789 o
->addr1
= get_address(s
, 0, get_field(f
, b1
), get_field(f
, d1
));
3792 static void in1_m1_8u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3795 o
->in1
= tcg_temp_new_i64();
3796 tcg_gen_qemu_ld8u(o
->in1
, o
->addr1
, get_mem_index(s
));
3799 static void in1_m1_16s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3802 o
->in1
= tcg_temp_new_i64();
3803 tcg_gen_qemu_ld16s(o
->in1
, o
->addr1
, get_mem_index(s
));
3806 static void in1_m1_16u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3809 o
->in1
= tcg_temp_new_i64();
3810 tcg_gen_qemu_ld16u(o
->in1
, o
->addr1
, get_mem_index(s
));
3813 static void in1_m1_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3816 o
->in1
= tcg_temp_new_i64();
3817 tcg_gen_qemu_ld32s(o
->in1
, o
->addr1
, get_mem_index(s
));
3820 static void in1_m1_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3823 o
->in1
= tcg_temp_new_i64();
3824 tcg_gen_qemu_ld32u(o
->in1
, o
->addr1
, get_mem_index(s
));
3827 static void in1_m1_64(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3830 o
->in1
= tcg_temp_new_i64();
3831 tcg_gen_qemu_ld64(o
->in1
, o
->addr1
, get_mem_index(s
));
3834 /* ====================================================================== */
3835 /* The "INput 2" generators. These load the second operand to an insn. */
3837 static void in2_r2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3839 o
->in2
= load_reg(get_field(f
, r2
));
3842 static void in2_r2_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3844 o
->in2
= regs
[get_field(f
, r2
)];
3848 static void in2_r2_nz(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3850 int r2
= get_field(f
, r2
);
3852 o
->in2
= load_reg(r2
);
3856 static void in2_r2_8s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3858 o
->in2
= tcg_temp_new_i64();
3859 tcg_gen_ext8s_i64(o
->in2
, regs
[get_field(f
, r2
)]);
3862 static void in2_r2_8u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3864 o
->in2
= tcg_temp_new_i64();
3865 tcg_gen_ext8u_i64(o
->in2
, regs
[get_field(f
, r2
)]);
3868 static void in2_r2_16s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3870 o
->in2
= tcg_temp_new_i64();
3871 tcg_gen_ext16s_i64(o
->in2
, regs
[get_field(f
, r2
)]);
3874 static void in2_r2_16u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3876 o
->in2
= tcg_temp_new_i64();
3877 tcg_gen_ext16u_i64(o
->in2
, regs
[get_field(f
, r2
)]);
3880 static void in2_r3(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3882 o
->in2
= load_reg(get_field(f
, r3
));
3885 static void in2_r2_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3887 o
->in2
= tcg_temp_new_i64();
3888 tcg_gen_ext32s_i64(o
->in2
, regs
[get_field(f
, r2
)]);
3891 static void in2_r2_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3893 o
->in2
= tcg_temp_new_i64();
3894 tcg_gen_ext32u_i64(o
->in2
, regs
[get_field(f
, r2
)]);
3897 static void in2_e2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3899 o
->in2
= load_freg32_i64(get_field(f
, r2
));
3902 static void in2_f2_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3904 o
->in2
= fregs
[get_field(f
, r2
)];
3908 static void in2_x2_o(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3910 int f2
= get_field(f
, r2
);
3912 o
->in2
= fregs
[(f2
+ 2) & 15];
3913 o
->g_in1
= o
->g_in2
= true;
3916 static void in2_a2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3918 int x2
= have_field(f
, x2
) ? get_field(f
, x2
) : 0;
3919 o
->in2
= get_address(s
, x2
, get_field(f
, b2
), get_field(f
, d2
));
3922 static void in2_ri2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3924 o
->in2
= tcg_const_i64(s
->pc
+ (int64_t)get_field(f
, i2
) * 2);
3927 static void in2_sh32(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3929 help_l2_shift(s
, f
, o
, 31);
3932 static void in2_sh64(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3934 help_l2_shift(s
, f
, o
, 63);
3937 static void in2_m2_8u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3940 tcg_gen_qemu_ld8u(o
->in2
, o
->in2
, get_mem_index(s
));
3943 static void in2_m2_16s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3946 tcg_gen_qemu_ld16s(o
->in2
, o
->in2
, get_mem_index(s
));
3949 static void in2_m2_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3952 tcg_gen_qemu_ld32s(o
->in2
, o
->in2
, get_mem_index(s
));
3955 static void in2_m2_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3958 tcg_gen_qemu_ld32u(o
->in2
, o
->in2
, get_mem_index(s
));
3961 static void in2_m2_64(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3964 tcg_gen_qemu_ld64(o
->in2
, o
->in2
, get_mem_index(s
));
3967 static void in2_mri2_16u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3970 tcg_gen_qemu_ld16u(o
->in2
, o
->in2
, get_mem_index(s
));
3973 static void in2_mri2_32s(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3976 tcg_gen_qemu_ld32s(o
->in2
, o
->in2
, get_mem_index(s
));
3979 static void in2_mri2_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3982 tcg_gen_qemu_ld32u(o
->in2
, o
->in2
, get_mem_index(s
));
3985 static void in2_mri2_64(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3988 tcg_gen_qemu_ld64(o
->in2
, o
->in2
, get_mem_index(s
));
3991 static void in2_i2(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3993 o
->in2
= tcg_const_i64(get_field(f
, i2
));
3996 static void in2_i2_8u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
3998 o
->in2
= tcg_const_i64((uint8_t)get_field(f
, i2
));
4001 static void in2_i2_16u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
4003 o
->in2
= tcg_const_i64((uint16_t)get_field(f
, i2
));
4006 static void in2_i2_32u(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
4008 o
->in2
= tcg_const_i64((uint32_t)get_field(f
, i2
));
4011 static void in2_i2_16u_shl(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
4013 uint64_t i2
= (uint16_t)get_field(f
, i2
);
4014 o
->in2
= tcg_const_i64(i2
<< s
->insn
->data
);
4017 static void in2_i2_32u_shl(DisasContext
*s
, DisasFields
*f
, DisasOps
*o
)
4019 uint64_t i2
= (uint32_t)get_field(f
, i2
);
4020 o
->in2
= tcg_const_i64(i2
<< s
->insn
->data
);
4023 /* ====================================================================== */
4025 /* Find opc within the table of insns. This is formulated as a switch
4026 statement so that (1) we get compile-time notice of cut-paste errors
4027 for duplicated opcodes, and (2) the compiler generates the binary
4028 search tree, rather than us having to post-process the table. */
4030 #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
4031 D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0)
4033 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) insn_ ## NM,
4035 enum DisasInsnEnum
{
4036 #include "insn-data.def"
4040 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) { \
4045 .help_in1 = in1_##I1, \
4046 .help_in2 = in2_##I2, \
4047 .help_prep = prep_##P, \
4048 .help_wout = wout_##W, \
4049 .help_cout = cout_##CC, \
4050 .help_op = op_##OP, \
4054 /* Allow 0 to be used for NULL in the table below. */
4062 static const DisasInsn insn_info
[] = {
4063 #include "insn-data.def"
4067 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
4068 case OPC: return &insn_info[insn_ ## NM];
4070 static const DisasInsn
*lookup_opc(uint16_t opc
)
4073 #include "insn-data.def"
4082 /* Extract a field from the insn. The INSN should be left-aligned in
4083 the uint64_t so that we can more easily utilize the big-bit-endian
4084 definitions we extract from the Principals of Operation. */
4086 static void extract_field(DisasFields
*o
, const DisasField
*f
, uint64_t insn
)
4094 /* Zero extract the field from the insn. */
4095 r
= (insn
<< f
->beg
) >> (64 - f
->size
);
4097 /* Sign-extend, or un-swap the field as necessary. */
4099 case 0: /* unsigned */
4101 case 1: /* signed */
4102 assert(f
->size
<= 32);
4103 m
= 1u << (f
->size
- 1);
4106 case 2: /* dl+dh split, signed 20 bit. */
4107 r
= ((int8_t)r
<< 12) | (r
>> 8);
4113 /* Validate that the "compressed" encoding we selected above is valid.
4114 I.e. we havn't make two different original fields overlap. */
4115 assert(((o
->presentC
>> f
->indexC
) & 1) == 0);
4116 o
->presentC
|= 1 << f
->indexC
;
4117 o
->presentO
|= 1 << f
->indexO
;
4119 o
->c
[f
->indexC
] = r
;
4122 /* Lookup the insn at the current PC, extracting the operands into O and
4123 returning the info struct for the insn. Returns NULL for invalid insn. */
4125 static const DisasInsn
*extract_insn(CPUS390XState
*env
, DisasContext
*s
,
4128 uint64_t insn
, pc
= s
->pc
;
4130 const DisasInsn
*info
;
4132 insn
= ld_code2(env
, pc
);
4133 op
= (insn
>> 8) & 0xff;
4134 ilen
= get_ilen(op
);
4135 s
->next_pc
= s
->pc
+ ilen
;
4142 insn
= ld_code4(env
, pc
) << 32;
4145 insn
= (insn
<< 48) | (ld_code4(env
, pc
+ 2) << 16);
4151 /* We can't actually determine the insn format until we've looked up
4152 the full insn opcode. Which we can't do without locating the
4153 secondary opcode. Assume by default that OP2 is at bit 40; for
4154 those smaller insns that don't actually have a secondary opcode
4155 this will correctly result in OP2 = 0. */
4161 case 0xb2: /* S, RRF, RRE */
4162 case 0xb3: /* RRE, RRD, RRF */
4163 case 0xb9: /* RRE, RRF */
4164 case 0xe5: /* SSE, SIL */
4165 op2
= (insn
<< 8) >> 56;
4169 case 0xc0: /* RIL */
4170 case 0xc2: /* RIL */
4171 case 0xc4: /* RIL */
4172 case 0xc6: /* RIL */
4173 case 0xc8: /* SSF */
4174 case 0xcc: /* RIL */
4175 op2
= (insn
<< 12) >> 60;
4177 case 0xd0 ... 0xdf: /* SS */
4183 case 0xee ... 0xf3: /* SS */
4184 case 0xf8 ... 0xfd: /* SS */
4188 op2
= (insn
<< 40) >> 56;
4192 memset(f
, 0, sizeof(*f
));
4196 /* Lookup the instruction. */
4197 info
= lookup_opc(op
<< 8 | op2
);
4199 /* If we found it, extract the operands. */
4201 DisasFormat fmt
= info
->fmt
;
4204 for (i
= 0; i
< NUM_C_FIELD
; ++i
) {
4205 extract_field(f
, &format_info
[fmt
].op
[i
], insn
);
4211 static ExitStatus
translate_one(CPUS390XState
*env
, DisasContext
*s
)
4213 const DisasInsn
*insn
;
4214 ExitStatus ret
= NO_EXIT
;
4218 insn
= extract_insn(env
, s
, &f
);
4220 /* If not found, try the old interpreter. This includes ILLOPC. */
4222 disas_s390_insn(env
, s
);
4223 switch (s
->is_jmp
) {
4231 ret
= EXIT_PC_UPDATED
;
4234 ret
= EXIT_NORETURN
;
4244 /* Set up the strutures we use to communicate with the helpers. */
4247 o
.g_out
= o
.g_out2
= o
.g_in1
= o
.g_in2
= false;
4248 TCGV_UNUSED_I64(o
.out
);
4249 TCGV_UNUSED_I64(o
.out2
);
4250 TCGV_UNUSED_I64(o
.in1
);
4251 TCGV_UNUSED_I64(o
.in2
);
4252 TCGV_UNUSED_I64(o
.addr1
);
4254 /* Implement the instruction. */
4255 if (insn
->help_in1
) {
4256 insn
->help_in1(s
, &f
, &o
);
4258 if (insn
->help_in2
) {
4259 insn
->help_in2(s
, &f
, &o
);
4261 if (insn
->help_prep
) {
4262 insn
->help_prep(s
, &f
, &o
);
4264 if (insn
->help_op
) {
4265 ret
= insn
->help_op(s
, &o
);
4267 if (insn
->help_wout
) {
4268 insn
->help_wout(s
, &f
, &o
);
4270 if (insn
->help_cout
) {
4271 insn
->help_cout(s
, &o
);
4274 /* Free any temporaries created by the helpers. */
4275 if (!TCGV_IS_UNUSED_I64(o
.out
) && !o
.g_out
) {
4276 tcg_temp_free_i64(o
.out
);
4278 if (!TCGV_IS_UNUSED_I64(o
.out2
) && !o
.g_out2
) {
4279 tcg_temp_free_i64(o
.out2
);
4281 if (!TCGV_IS_UNUSED_I64(o
.in1
) && !o
.g_in1
) {
4282 tcg_temp_free_i64(o
.in1
);
4284 if (!TCGV_IS_UNUSED_I64(o
.in2
) && !o
.g_in2
) {
4285 tcg_temp_free_i64(o
.in2
);
4287 if (!TCGV_IS_UNUSED_I64(o
.addr1
)) {
4288 tcg_temp_free_i64(o
.addr1
);
4291 /* Advance to the next instruction. */
4296 static inline void gen_intermediate_code_internal(CPUS390XState
*env
,
4297 TranslationBlock
*tb
,
4301 target_ulong pc_start
;
4302 uint64_t next_page_start
;
4303 uint16_t *gen_opc_end
;
4305 int num_insns
, max_insns
;
4313 if (!(tb
->flags
& FLAG_MASK_64
)) {
4314 pc_start
&= 0x7fffffff;
4319 dc
.cc_op
= CC_OP_DYNAMIC
;
4320 do_debug
= dc
.singlestep_enabled
= env
->singlestep_enabled
;
4321 dc
.is_jmp
= DISAS_NEXT
;
4323 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
4325 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
4328 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
4329 if (max_insns
== 0) {
4330 max_insns
= CF_COUNT_MASK
;
4337 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
4341 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
4344 tcg_ctx
.gen_opc_pc
[lj
] = dc
.pc
;
4345 gen_opc_cc_op
[lj
] = dc
.cc_op
;
4346 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
4347 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
4349 if (++num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
4353 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
4354 tcg_gen_debug_insn_start(dc
.pc
);
4358 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
4359 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
4360 if (bp
->pc
== dc
.pc
) {
4361 status
= EXIT_PC_STALE
;
4367 if (status
== NO_EXIT
) {
4368 status
= translate_one(env
, &dc
);
4371 /* If we reach a page boundary, are single stepping,
4372 or exhaust instruction count, stop generation. */
4373 if (status
== NO_EXIT
4374 && (dc
.pc
>= next_page_start
4375 || tcg_ctx
.gen_opc_ptr
>= gen_opc_end
4376 || num_insns
>= max_insns
4378 || env
->singlestep_enabled
)) {
4379 status
= EXIT_PC_STALE
;
4381 } while (status
== NO_EXIT
);
4383 if (tb
->cflags
& CF_LAST_IO
) {
4392 update_psw_addr(&dc
);
4394 case EXIT_PC_UPDATED
:
4395 if (singlestep
&& dc
.cc_op
!= CC_OP_DYNAMIC
) {
4396 gen_op_calc_cc(&dc
);
4398 /* Next TB starts off with CC_OP_DYNAMIC,
4399 so make sure the cc op type is in env */
4400 gen_op_set_cc_op(&dc
);
4403 gen_exception(EXCP_DEBUG
);
4405 /* Generate the return instruction */
4413 gen_icount_end(tb
, num_insns
);
4414 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
4416 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
4419 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
4422 tb
->size
= dc
.pc
- pc_start
;
4423 tb
->icount
= num_insns
;
4426 #if defined(S390X_DEBUG_DISAS)
4427 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
4428 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
4429 log_target_disas(env
, pc_start
, dc
.pc
- pc_start
, 1);
4435 void gen_intermediate_code (CPUS390XState
*env
, struct TranslationBlock
*tb
)
4437 gen_intermediate_code_internal(env
, tb
, 0);
4440 void gen_intermediate_code_pc (CPUS390XState
*env
, struct TranslationBlock
*tb
)
4442 gen_intermediate_code_internal(env
, tb
, 1);
4445 void restore_state_to_opc(CPUS390XState
*env
, TranslationBlock
*tb
, int pc_pos
)
4448 env
->psw
.addr
= tcg_ctx
.gen_opc_pc
[pc_pos
];
4449 cc_op
= gen_opc_cc_op
[pc_pos
];
4450 if ((cc_op
!= CC_OP_DYNAMIC
) && (cc_op
!= CC_OP_STATIC
)) {