target-sh4/helper.c

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdarg.h>
  20 #include <stdlib.h>
  21 #include <stdio.h>
  22 #include <string.h>
  23 #include <inttypes.h>
  24 #include <signal.h>
  25
  26 #include "cpu.h"
  27
  28 #if !defined(CONFIG_USER_ONLY)
  29 #include "hw/sh_intc.h"
  30 #endif
  31
  32 #if defined(CONFIG_USER_ONLY)
  33
  34 void do_interrupt (CPUSH4State *env)
  35 {
  36   env->exception_index = -1;
  37 }
  38
  39 int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
  40                              int mmu_idx)
  41 {
  42     env->tea = address;
  43     env->exception_index = -1;
  44     switch (rw) {
  45     case 0:
  46         env->exception_index = 0x0a0;
  47         break;
  48     case 1:
  49         env->exception_index = 0x0c0;
  50         break;
  51     case 2:
  52         env->exception_index = 0x0a0;
  53         break;
  54     }
  55     return 1;
  56 }
  57
  58 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
  59 {
  60     /* For user mode, only U0 area is cachable. */
  61     return !(addr & 0x80000000);
  62 }
  63
  64 #else /* !CONFIG_USER_ONLY */
  65
  66 #define MMU_OK                   0
  67 #define MMU_ITLB_MISS            (-1)
  68 #define MMU_ITLB_MULTIPLE        (-2)
  69 #define MMU_ITLB_VIOLATION       (-3)
  70 #define MMU_DTLB_MISS_READ       (-4)
  71 #define MMU_DTLB_MISS_WRITE      (-5)
  72 #define MMU_DTLB_INITIAL_WRITE   (-6)
  73 #define MMU_DTLB_VIOLATION_READ  (-7)
  74 #define MMU_DTLB_VIOLATION_WRITE (-8)
  75 #define MMU_DTLB_MULTIPLE        (-9)
  76 #define MMU_DTLB_MISS            (-10)
  77 #define MMU_IADDR_ERROR          (-11)
  78 #define MMU_DADDR_ERROR_READ     (-12)
  79 #define MMU_DADDR_ERROR_WRITE    (-13)
  80
  81 void do_interrupt(CPUSH4State *env)
  82 {
  83     CPUState *cs = CPU(sh_env_get_cpu(env));
  84     int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD;
  85     int do_exp, irq_vector = env->exception_index;
  86
  87     /* prioritize exceptions over interrupts */
  88
  89     do_exp = env->exception_index != -1;
  90     do_irq = do_irq && (env->exception_index == -1);
  91
  92     if (env->sr & SR_BL) {
  93         if (do_exp && env->exception_index != 0x1e0) {
  94             env->exception_index = 0x000; /* masked exception -> reset */
  95         }
  96         if (do_irq && !env->in_sleep) {
  97             return; /* masked */
  98         }
  99     }
 100     env->in_sleep = 0;
 101
 102     if (do_irq) {
 103         irq_vector = sh_intc_get_pending_vector(env->intc_handle,
 104                                                 (env->sr >> 4) & 0xf);
 105         if (irq_vector == -1) {
 106             return; /* masked */
 107         }
 108     }
 109
 110     if (qemu_loglevel_mask(CPU_LOG_INT)) {
 111         const char *expname;
 112         switch (env->exception_index) {
 113         case 0x0e0:
 114             expname = "addr_error";
 115             break;
 116         case 0x040:
 117             expname = "tlb_miss";
 118             break;
 119         case 0x0a0:
 120             expname = "tlb_violation";
 121             break;
 122         case 0x180:
 123             expname = "illegal_instruction";
 124             break;
 125         case 0x1a0:
 126             expname = "slot_illegal_instruction";
 127             break;
 128         case 0x800:
 129             expname = "fpu_disable";
 130             break;
 131         case 0x820:
 132             expname = "slot_fpu";
 133             break;
 134         case 0x100:
 135             expname = "data_write";
 136             break;
 137         case 0x060:
 138             expname = "dtlb_miss_write";
 139             break;
 140         case 0x0c0:
 141             expname = "dtlb_violation_write";
 142             break;
 143         case 0x120:
 144             expname = "fpu_exception";
 145             break;
 146         case 0x080:
 147             expname = "initial_page_write";
 148             break;
 149         case 0x160:
 150             expname = "trapa";
 151             break;
 152         default:
 153             expname = do_irq ? "interrupt" : "???";
 154             break;
 155         }
 156         qemu_log("exception 0x%03x [%s] raised\n",
 157                   irq_vector, expname);
 158         log_cpu_state(env, 0);
 159     }
 160
 161     env->ssr = env->sr;
 162     env->spc = env->pc;
 163     env->sgr = env->gregs[15];
 164     env->sr |= SR_BL | SR_MD | SR_RB;
 165
 166     if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
 167         /* Branch instruction should be executed again before delay slot. */
 168         env->spc -= 2;
 169         /* Clear flags for exception/interrupt routine. */
 170         env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);
 171     }
 172     if (env->flags & DELAY_SLOT_CLEARME)
 173         env->flags = 0;
 174
 175     if (do_exp) {
 176         env->expevt = env->exception_index;
 177         switch (env->exception_index) {
 178         case 0x000:
 179         case 0x020:
 180         case 0x140:
 181             env->sr &= ~SR_FD;
 182             env->sr |= 0xf << 4; /* IMASK */
 183             env->pc = 0xa0000000;
 184             break;
 185         case 0x040:
 186         case 0x060:
 187             env->pc = env->vbr + 0x400;
 188             break;
 189         case 0x160:
 190             env->spc += 2; /* special case for TRAPA */
 191             /* fall through */
 192         default:
 193             env->pc = env->vbr + 0x100;
 194             break;
 195         }
 196         return;
 197     }
 198
 199     if (do_irq) {
 200         env->intevt = irq_vector;
 201         env->pc = env->vbr + 0x600;
 202         return;
 203     }
 204 }
 205
 206 static void update_itlb_use(CPUSH4State * env, int itlbnb)
 207 {
 208     uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
 209
 210     switch (itlbnb) {
 211     case 0:
 212         and_mask = 0x1f;
 213         break;
 214     case 1:
 215         and_mask = 0xe7;
 216         or_mask = 0x80;
 217         break;
 218     case 2:
 219         and_mask = 0xfb;
 220         or_mask = 0x50;
 221         break;
 222     case 3:
 223         or_mask = 0x2c;
 224         break;
 225     }
 226
 227     env->mmucr &= (and_mask << 24) | 0x00ffffff;
 228     env->mmucr |= (or_mask << 24);
 229 }
 230
 231 static int itlb_replacement(CPUSH4State * env)
 232 {
 233     if ((env->mmucr & 0xe0000000) == 0xe0000000)
 234         return 0;
 235     if ((env->mmucr & 0x98000000) == 0x18000000)
 236         return 1;
 237     if ((env->mmucr & 0x54000000) == 0x04000000)
 238         return 2;
 239     if ((env->mmucr & 0x2c000000) == 0x00000000)
 240         return 3;
 241     cpu_abort(env, "Unhandled itlb_replacement");
 242 }
 243
 244 /* Find the corresponding entry in the right TLB
 245    Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
 246 */
 247 static int find_tlb_entry(CPUSH4State * env, target_ulong address,
 248                           tlb_t * entries, uint8_t nbtlb, int use_asid)
 249 {
 250     int match = MMU_DTLB_MISS;
 251     uint32_t start, end;
 252     uint8_t asid;
 253     int i;
 254
 255     asid = env->pteh & 0xff;
 256
 257     for (i = 0; i < nbtlb; i++) {
 258         if (!entries[i].v)
 259             continue;           /* Invalid entry */
 260         if (!entries[i].sh && use_asid && entries[i].asid != asid)
 261             continue;           /* Bad ASID */
 262         start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
 263         end = start + entries[i].size - 1;
 264         if (address >= start && address <= end) {       /* Match */
 265             if (match != MMU_DTLB_MISS)
 266                 return MMU_DTLB_MULTIPLE;       /* Multiple match */
 267             match = i;
 268         }
 269     }
 270     return match;
 271 }
 272
 273 static void increment_urc(CPUSH4State * env)
 274 {
 275     uint8_t urb, urc;
 276
 277     /* Increment URC */
 278     urb = ((env->mmucr) >> 18) & 0x3f;
 279     urc = ((env->mmucr) >> 10) & 0x3f;
 280     urc++;
 281     if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
 282         urc = 0;
 283     env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
 284 }
 285
 286 /* Copy and utlb entry into itlb
 287    Return entry
 288 */
 289 static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
 290 {
 291     int itlb;
 292
 293     tlb_t * ientry;
 294     itlb = itlb_replacement(env);
 295     ientry = &env->itlb[itlb];
 296     if (ientry->v) {
 297         tlb_flush_page(env, ientry->vpn << 10);
 298     }
 299     *ientry = env->utlb[utlb];
 300     update_itlb_use(env, itlb);
 301     return itlb;
 302 }
 303
 304 /* Find itlb entry
 305    Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
 306 */
 307 static int find_itlb_entry(CPUSH4State * env, target_ulong address,
 308                            int use_asid)
 309 {
 310     int e;
 311
 312     e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
 313     if (e == MMU_DTLB_MULTIPLE) {
 314         e = MMU_ITLB_MULTIPLE;
 315     } else if (e == MMU_DTLB_MISS) {
 316         e = MMU_ITLB_MISS;
 317     } else if (e >= 0) {
 318         update_itlb_use(env, e);
 319     }
 320     return e;
 321 }
 322
 323 /* Find utlb entry
 324    Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
 325 static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
 326 {
 327     /* per utlb access */
 328     increment_urc(env);
 329
 330     /* Return entry */
 331     return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
 332 }
 333
 334 /* Match address against MMU
 335    Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
 336    MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
 337    MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
 338    MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
 339    MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
 340 */
 341 static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
 342                            int *prot, target_ulong address,
 343                            int rw, int access_type)
 344 {
 345     int use_asid, n;
 346     tlb_t *matching = NULL;
 347
 348     use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
 349
 350     if (rw == 2) {
 351         n = find_itlb_entry(env, address, use_asid);
 352         if (n >= 0) {
 353             matching = &env->itlb[n];
 354             if (!(env->sr & SR_MD) && !(matching->pr & 2))
 355                 n = MMU_ITLB_VIOLATION;
 356             else
 357                 *prot = PAGE_EXEC;
 358         } else {
 359             n = find_utlb_entry(env, address, use_asid);
 360             if (n >= 0) {
 361                 n = copy_utlb_entry_itlb(env, n);
 362                 matching = &env->itlb[n];
 363                 if (!(env->sr & SR_MD) && !(matching->pr & 2)) {
 364                       n = MMU_ITLB_VIOLATION;
 365                 } else {
 366                     *prot = PAGE_READ | PAGE_EXEC;
 367                     if ((matching->pr & 1) && matching->d) {
 368                         *prot |= PAGE_WRITE;
 369                     }
 370                 }
 371             } else if (n == MMU_DTLB_MULTIPLE) {
 372                 n = MMU_ITLB_MULTIPLE;
 373             } else if (n == MMU_DTLB_MISS) {
 374                 n = MMU_ITLB_MISS;
 375             }
 376         }
 377     } else {
 378         n = find_utlb_entry(env, address, use_asid);
 379         if (n >= 0) {
 380             matching = &env->utlb[n];
 381             if (!(env->sr & SR_MD) && !(matching->pr & 2)) {
 382                 n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
 383                     MMU_DTLB_VIOLATION_READ;
 384             } else if ((rw == 1) && !(matching->pr & 1)) {
 385                 n = MMU_DTLB_VIOLATION_WRITE;
 386             } else if ((rw == 1) && !matching->d) {
 387                 n = MMU_DTLB_INITIAL_WRITE;
 388             } else {
 389                 *prot = PAGE_READ;
 390                 if ((matching->pr & 1) && matching->d) {
 391                     *prot |= PAGE_WRITE;
 392                 }
 393             }
 394         } else if (n == MMU_DTLB_MISS) {
 395             n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
 396                 MMU_DTLB_MISS_READ;
 397         }
 398     }
 399     if (n >= 0) {
 400         n = MMU_OK;
 401         *physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
 402             (address & (matching->size - 1));
 403     }
 404     return n;
 405 }
 406
 407 static int get_physical_address(CPUSH4State * env, target_ulong * physical,
 408                                 int *prot, target_ulong address,
 409                                 int rw, int access_type)
 410 {
 411     /* P1, P2 and P4 areas do not use translation */
 412     if ((address >= 0x80000000 && address < 0xc0000000) ||
 413         address >= 0xe0000000) {
 414         if (!(env->sr & SR_MD)
 415             && (address < 0xe0000000 || address >= 0xe4000000)) {
 416             /* Unauthorized access in user mode (only store queues are available) */
 417             fprintf(stderr, "Unauthorized access\n");
 418             if (rw == 0)
 419                 return MMU_DADDR_ERROR_READ;
 420             else if (rw == 1)
 421                 return MMU_DADDR_ERROR_WRITE;
 422             else
 423                 return MMU_IADDR_ERROR;
 424         }
 425         if (address >= 0x80000000 && address < 0xc0000000) {
 426             /* Mask upper 3 bits for P1 and P2 areas */
 427             *physical = address & 0x1fffffff;
 428         } else {
 429             *physical = address;
 430         }
 431         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 432         return MMU_OK;
 433     }
 434
 435     /* If MMU is disabled, return the corresponding physical page */
 436     if (!(env->mmucr & MMUCR_AT)) {
 437         *physical = address & 0x1FFFFFFF;
 438         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 439         return MMU_OK;
 440     }
 441
 442     /* We need to resort to the MMU */
 443     return get_mmu_address(env, physical, prot, address, rw, access_type);
 444 }
 445
 446 int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
 447                              int mmu_idx)
 448 {
 449     target_ulong physical;
 450     int prot, ret, access_type;
 451
 452     access_type = ACCESS_INT;
 453     ret =
 454         get_physical_address(env, &physical, &prot, address, rw,
 455                              access_type);
 456
 457     if (ret != MMU_OK) {
 458         env->tea = address;
 459         if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) {
 460             env->pteh = (env->pteh & PTEH_ASID_MASK) |
 461                     (address & PTEH_VPN_MASK);
 462         }
 463         switch (ret) {
 464         case MMU_ITLB_MISS:
 465         case MMU_DTLB_MISS_READ:
 466             env->exception_index = 0x040;
 467             break;
 468         case MMU_DTLB_MULTIPLE:
 469         case MMU_ITLB_MULTIPLE:
 470             env->exception_index = 0x140;
 471             break;
 472         case MMU_ITLB_VIOLATION:
 473             env->exception_index = 0x0a0;
 474             break;
 475         case MMU_DTLB_MISS_WRITE:
 476             env->exception_index = 0x060;
 477             break;
 478         case MMU_DTLB_INITIAL_WRITE:
 479             env->exception_index = 0x080;
 480             break;
 481         case MMU_DTLB_VIOLATION_READ:
 482             env->exception_index = 0x0a0;
 483             break;
 484         case MMU_DTLB_VIOLATION_WRITE:
 485             env->exception_index = 0x0c0;
 486             break;
 487         case MMU_IADDR_ERROR:
 488         case MMU_DADDR_ERROR_READ:
 489             env->exception_index = 0x0e0;
 490             break;
 491         case MMU_DADDR_ERROR_WRITE:
 492             env->exception_index = 0x100;
 493             break;
 494         default:
 495             cpu_abort(env, "Unhandled MMU fault");
 496         }
 497         return 1;
 498     }
 499
 500     address &= TARGET_PAGE_MASK;
 501     physical &= TARGET_PAGE_MASK;
 502
 503     tlb_set_page(env, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
 504     return 0;
 505 }
 506
 507 hwaddr cpu_get_phys_page_debug(CPUSH4State * env, target_ulong addr)
 508 {
 509     target_ulong physical;
 510     int prot;
 511
 512     get_physical_address(env, &physical, &prot, addr, 0, 0);
 513     return physical;
 514 }
 515
 516 void cpu_load_tlb(CPUSH4State * env)
 517 {
 518     int n = cpu_mmucr_urc(env->mmucr);
 519     tlb_t * entry = &env->utlb[n];
 520
 521     if (entry->v) {
 522         /* Overwriting valid entry in utlb. */
 523         target_ulong address = entry->vpn << 10;
 524         tlb_flush_page(env, address);
 525     }
 526
 527     /* Take values into cpu status from registers. */
 528     entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
 529     entry->vpn  = cpu_pteh_vpn(env->pteh);
 530     entry->v    = (uint8_t)cpu_ptel_v(env->ptel);
 531     entry->ppn  = cpu_ptel_ppn(env->ptel);
 532     entry->sz   = (uint8_t)cpu_ptel_sz(env->ptel);
 533     switch (entry->sz) {
 534     case 0: /* 00 */
 535         entry->size = 1024; /* 1K */
 536         break;
 537     case 1: /* 01 */
 538         entry->size = 1024 * 4; /* 4K */
 539         break;
 540     case 2: /* 10 */
 541         entry->size = 1024 * 64; /* 64K */
 542         break;
 543     case 3: /* 11 */
 544         entry->size = 1024 * 1024; /* 1M */
 545         break;
 546     default:
 547         cpu_abort(env, "Unhandled load_tlb");
 548         break;
 549     }
 550     entry->sh   = (uint8_t)cpu_ptel_sh(env->ptel);
 551     entry->c    = (uint8_t)cpu_ptel_c(env->ptel);
 552     entry->pr   = (uint8_t)cpu_ptel_pr(env->ptel);
 553     entry->d    = (uint8_t)cpu_ptel_d(env->ptel);
 554     entry->wt   = (uint8_t)cpu_ptel_wt(env->ptel);
 555     entry->sa   = (uint8_t)cpu_ptea_sa(env->ptea);
 556     entry->tc   = (uint8_t)cpu_ptea_tc(env->ptea);
 557 }
 558
 559  void cpu_sh4_invalidate_tlb(CPUSH4State *s)
 560 {
 561     int i;
 562
 563     /* UTLB */
 564     for (i = 0; i < UTLB_SIZE; i++) {
 565         tlb_t * entry = &s->utlb[i];
 566         entry->v = 0;
 567     }
 568     /* ITLB */
 569     for (i = 0; i < ITLB_SIZE; i++) {
 570         tlb_t * entry = &s->itlb[i];
 571         entry->v = 0;
 572     }
 573
 574     tlb_flush(s, 1);
 575 }
 576
 577 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
 578                                        hwaddr addr)
 579 {
 580     int index = (addr & 0x00000300) >> 8;
 581     tlb_t * entry = &s->itlb[index];
 582
 583     return (entry->vpn  << 10) |
 584            (entry->v    <<  8) |
 585            (entry->asid);
 586 }
 587
 588 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
 589                                     uint32_t mem_value)
 590 {
 591     uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
 592     uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
 593     uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
 594
 595     int index = (addr & 0x00000300) >> 8;
 596     tlb_t * entry = &s->itlb[index];
 597     if (entry->v) {
 598         /* Overwriting valid entry in itlb. */
 599         target_ulong address = entry->vpn << 10;
 600         tlb_flush_page(s, address);
 601     }
 602     entry->asid = asid;
 603     entry->vpn = vpn;
 604     entry->v = v;
 605 }
 606
 607 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
 608                                        hwaddr addr)
 609 {
 610     int array = (addr & 0x00800000) >> 23;
 611     int index = (addr & 0x00000300) >> 8;
 612     tlb_t * entry = &s->itlb[index];
 613
 614     if (array == 0) {
 615         /* ITLB Data Array 1 */
 616         return (entry->ppn << 10) |
 617                (entry->v   <<  8) |
 618                (entry->pr  <<  5) |
 619                ((entry->sz & 1) <<  6) |
 620                ((entry->sz & 2) <<  4) |
 621                (entry->c   <<  3) |
 622                (entry->sh  <<  1);
 623     } else {
 624         /* ITLB Data Array 2 */
 625         return (entry->tc << 1) |
 626                (entry->sa);
 627     }
 628 }
 629
 630 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
 631                                     uint32_t mem_value)
 632 {
 633     int array = (addr & 0x00800000) >> 23;
 634     int index = (addr & 0x00000300) >> 8;
 635     tlb_t * entry = &s->itlb[index];
 636
 637     if (array == 0) {
 638         /* ITLB Data Array 1 */
 639         if (entry->v) {
 640             /* Overwriting valid entry in utlb. */
 641             target_ulong address = entry->vpn << 10;
 642             tlb_flush_page(s, address);
 643         }
 644         entry->ppn = (mem_value & 0x1ffffc00) >> 10;
 645         entry->v   = (mem_value & 0x00000100) >> 8;
 646         entry->sz  = (mem_value & 0x00000080) >> 6 |
 647                      (mem_value & 0x00000010) >> 4;
 648         entry->pr  = (mem_value & 0x00000040) >> 5;
 649         entry->c   = (mem_value & 0x00000008) >> 3;
 650         entry->sh  = (mem_value & 0x00000002) >> 1;
 651     } else {
 652         /* ITLB Data Array 2 */
 653         entry->tc  = (mem_value & 0x00000008) >> 3;
 654         entry->sa  = (mem_value & 0x00000007);
 655     }
 656 }
 657
 658 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
 659                                        hwaddr addr)
 660 {
 661     int index = (addr & 0x00003f00) >> 8;
 662     tlb_t * entry = &s->utlb[index];
 663
 664     increment_urc(s); /* per utlb access */
 665
 666     return (entry->vpn  << 10) |
 667            (entry->v    <<  8) |
 668            (entry->asid);
 669 }
 670
 671 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
 672                                     uint32_t mem_value)
 673 {
 674     int associate = addr & 0x0000080;
 675     uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
 676     uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
 677     uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
 678     uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
 679     int use_asid = (s->mmucr & MMUCR_SV) == 0 || (s->sr & SR_MD) == 0;
 680
 681     if (associate) {
 682         int i;
 683         tlb_t * utlb_match_entry = NULL;
 684         int needs_tlb_flush = 0;
 685
 686         /* search UTLB */
 687         for (i = 0; i < UTLB_SIZE; i++) {
 688             tlb_t * entry = &s->utlb[i];
 689             if (!entry->v)
 690                 continue;
 691
 692             if (entry->vpn == vpn
 693                 && (!use_asid || entry->asid == asid || entry->sh)) {
 694                 if (utlb_match_entry) {
 695                     /* Multiple TLB Exception */
 696                     s->exception_index = 0x140;
 697                     s->tea = addr;
 698                     break;
 699                 }
 700                 if (entry->v && !v)
 701                     needs_tlb_flush = 1;
 702                 entry->v = v;
 703                 entry->d = d;
 704                 utlb_match_entry = entry;
 705             }
 706             increment_urc(s); /* per utlb access */
 707         }
 708
 709         /* search ITLB */
 710         for (i = 0; i < ITLB_SIZE; i++) {
 711             tlb_t * entry = &s->itlb[i];
 712             if (entry->vpn == vpn
 713                 && (!use_asid || entry->asid == asid || entry->sh)) {
 714                 if (entry->v && !v)
 715                     needs_tlb_flush = 1;
 716                 if (utlb_match_entry)
 717                     *entry = *utlb_match_entry;
 718                 else
 719                     entry->v = v;
 720                 break;
 721             }
 722         }
 723
 724         if (needs_tlb_flush)
 725             tlb_flush_page(s, vpn << 10);
 726
 727     } else {
 728         int index = (addr & 0x00003f00) >> 8;
 729         tlb_t * entry = &s->utlb[index];
 730         if (entry->v) {
 731             /* Overwriting valid entry in utlb. */
 732             target_ulong address = entry->vpn << 10;
 733             tlb_flush_page(s, address);
 734         }
 735         entry->asid = asid;
 736         entry->vpn = vpn;
 737         entry->d = d;
 738         entry->v = v;
 739         increment_urc(s);
 740     }
 741 }
 742
 743 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
 744                                        hwaddr addr)
 745 {
 746     int array = (addr & 0x00800000) >> 23;
 747     int index = (addr & 0x00003f00) >> 8;
 748     tlb_t * entry = &s->utlb[index];
 749
 750     increment_urc(s); /* per utlb access */
 751
 752     if (array == 0) {
 753         /* ITLB Data Array 1 */
 754         return (entry->ppn << 10) |
 755                (entry->v   <<  8) |
 756                (entry->pr  <<  5) |
 757                ((entry->sz & 1) <<  6) |
 758                ((entry->sz & 2) <<  4) |
 759                (entry->c   <<  3) |
 760                (entry->d   <<  2) |
 761                (entry->sh  <<  1) |
 762                (entry->wt);
 763     } else {
 764         /* ITLB Data Array 2 */
 765         return (entry->tc << 1) |
 766                (entry->sa);
 767     }
 768 }
 769
 770 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
 771                                     uint32_t mem_value)
 772 {
 773     int array = (addr & 0x00800000) >> 23;
 774     int index = (addr & 0x00003f00) >> 8;
 775     tlb_t * entry = &s->utlb[index];
 776
 777     increment_urc(s); /* per utlb access */
 778
 779     if (array == 0) {
 780         /* UTLB Data Array 1 */
 781         if (entry->v) {
 782             /* Overwriting valid entry in utlb. */
 783             target_ulong address = entry->vpn << 10;
 784             tlb_flush_page(s, address);
 785         }
 786         entry->ppn = (mem_value & 0x1ffffc00) >> 10;
 787         entry->v   = (mem_value & 0x00000100) >> 8;
 788         entry->sz  = (mem_value & 0x00000080) >> 6 |
 789                      (mem_value & 0x00000010) >> 4;
 790         entry->pr  = (mem_value & 0x00000060) >> 5;
 791         entry->c   = (mem_value & 0x00000008) >> 3;
 792         entry->d   = (mem_value & 0x00000004) >> 2;
 793         entry->sh  = (mem_value & 0x00000002) >> 1;
 794         entry->wt  = (mem_value & 0x00000001);
 795     } else {
 796         /* UTLB Data Array 2 */
 797         entry->tc = (mem_value & 0x00000008) >> 3;
 798         entry->sa = (mem_value & 0x00000007);
 799     }
 800 }
 801
 802 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
 803 {
 804     int n;
 805     int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
 806
 807     /* check area */
 808     if (env->sr & SR_MD) {
 809         /* For previledged mode, P2 and P4 area is not cachable. */
 810         if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
 811             return 0;
 812     } else {
 813         /* For user mode, only U0 area is cachable. */
 814         if (0x80000000 <= addr)
 815             return 0;
 816     }
 817
 818     /*
 819      * TODO : Evaluate CCR and check if the cache is on or off.
 820      *        Now CCR is not in CPUSH4State, but in SH7750State.
 821      *        When you move the ccr into CPUSH4State, the code will be
 822      *        as follows.
 823      */
 824 #if 0
 825     /* check if operand cache is enabled or not. */
 826     if (!(env->ccr & 1))
 827         return 0;
 828 #endif
 829
 830     /* if MMU is off, no check for TLB. */
 831     if (env->mmucr & MMUCR_AT)
 832         return 1;
 833
 834     /* check TLB */
 835     n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
 836     if (n >= 0)
 837         return env->itlb[n].c;
 838
 839     n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
 840     if (n >= 0)
 841         return env->utlb[n].c;
 842
 843     return 0;
 844 }
 845
 846 #endif