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git.proxmox.com Git - qemu.git/blob - target-sh4/helper.c
4 * Copyright (c) 2005 Samuel Tardieu
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
28 #include "hw/sh_intc.h"
30 #if defined(CONFIG_USER_ONLY)
32 void do_interrupt (CPUState
*env
)
34 env
->exception_index
= -1;
37 int cpu_sh4_handle_mmu_fault(CPUState
* env
, target_ulong address
, int rw
,
38 int mmu_idx
, int is_softmmu
)
41 env
->exception_index
= 0;
44 env
->exception_index
= 0x0a0;
47 env
->exception_index
= 0x0c0;
50 env
->exception_index
= 0x0a0;
56 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
* env
, target_ulong addr
)
61 int cpu_sh4_is_cached(CPUSH4State
* env
, target_ulong addr
)
63 /* For user mode, only U0 area is cachable. */
64 return !(addr
& 0x80000000);
67 #else /* !CONFIG_USER_ONLY */
70 #define MMU_ITLB_MISS (-1)
71 #define MMU_ITLB_MULTIPLE (-2)
72 #define MMU_ITLB_VIOLATION (-3)
73 #define MMU_DTLB_MISS_READ (-4)
74 #define MMU_DTLB_MISS_WRITE (-5)
75 #define MMU_DTLB_INITIAL_WRITE (-6)
76 #define MMU_DTLB_VIOLATION_READ (-7)
77 #define MMU_DTLB_VIOLATION_WRITE (-8)
78 #define MMU_DTLB_MULTIPLE (-9)
79 #define MMU_DTLB_MISS (-10)
80 #define MMU_IADDR_ERROR (-11)
81 #define MMU_DADDR_ERROR_READ (-12)
82 #define MMU_DADDR_ERROR_WRITE (-13)
84 void do_interrupt(CPUState
* env
)
86 int do_irq
= env
->interrupt_request
& CPU_INTERRUPT_HARD
;
87 int do_exp
, irq_vector
= env
->exception_index
;
89 /* prioritize exceptions over interrupts */
91 do_exp
= env
->exception_index
!= -1;
92 do_irq
= do_irq
&& (env
->exception_index
== -1);
94 if (env
->sr
& SR_BL
) {
95 if (do_exp
&& env
->exception_index
!= 0x1e0) {
96 env
->exception_index
= 0x000; /* masked exception -> reset */
98 if (do_irq
&& !env
->intr_at_halt
) {
101 env
->intr_at_halt
= 0;
105 irq_vector
= sh_intc_get_pending_vector(env
->intc_handle
,
106 (env
->sr
>> 4) & 0xf);
107 if (irq_vector
== -1) {
112 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
114 switch (env
->exception_index
) {
116 expname
= "addr_error";
119 expname
= "tlb_miss";
122 expname
= "tlb_violation";
125 expname
= "illegal_instruction";
128 expname
= "slot_illegal_instruction";
131 expname
= "fpu_disable";
134 expname
= "slot_fpu";
137 expname
= "data_write";
140 expname
= "dtlb_miss_write";
143 expname
= "dtlb_violation_write";
146 expname
= "fpu_exception";
149 expname
= "initial_page_write";
155 expname
= do_irq
? "interrupt" : "???";
158 qemu_log("exception 0x%03x [%s] raised\n",
159 irq_vector
, expname
);
160 log_cpu_state(env
, 0);
165 env
->sgr
= env
->gregs
[15];
166 env
->sr
|= SR_BL
| SR_MD
| SR_RB
;
168 if (env
->flags
& (DELAY_SLOT
| DELAY_SLOT_CONDITIONAL
)) {
169 /* Branch instruction should be executed again before delay slot. */
171 /* Clear flags for exception/interrupt routine. */
172 env
->flags
&= ~(DELAY_SLOT
| DELAY_SLOT_CONDITIONAL
| DELAY_SLOT_TRUE
);
174 if (env
->flags
& DELAY_SLOT_CLEARME
)
178 env
->expevt
= env
->exception_index
;
179 switch (env
->exception_index
) {
184 env
->sr
|= 0xf << 4; /* IMASK */
185 env
->pc
= 0xa0000000;
189 env
->pc
= env
->vbr
+ 0x400;
192 env
->spc
+= 2; /* special case for TRAPA */
195 env
->pc
= env
->vbr
+ 0x100;
202 env
->intevt
= irq_vector
;
203 env
->pc
= env
->vbr
+ 0x600;
208 static void update_itlb_use(CPUState
* env
, int itlbnb
)
210 uint8_t or_mask
= 0, and_mask
= (uint8_t) - 1;
229 env
->mmucr
&= (and_mask
<< 24) | 0x00ffffff;
230 env
->mmucr
|= (or_mask
<< 24);
233 static int itlb_replacement(CPUState
* env
)
235 if ((env
->mmucr
& 0xe0000000) == 0xe0000000)
237 if ((env
->mmucr
& 0x98000000) == 0x18000000)
239 if ((env
->mmucr
& 0x54000000) == 0x04000000)
241 if ((env
->mmucr
& 0x2c000000) == 0x00000000)
246 /* Find the corresponding entry in the right TLB
247 Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
249 static int find_tlb_entry(CPUState
* env
, target_ulong address
,
250 tlb_t
* entries
, uint8_t nbtlb
, int use_asid
)
252 int match
= MMU_DTLB_MISS
;
257 asid
= env
->pteh
& 0xff;
259 for (i
= 0; i
< nbtlb
; i
++) {
261 continue; /* Invalid entry */
262 if (!entries
[i
].sh
&& use_asid
&& entries
[i
].asid
!= asid
)
263 continue; /* Bad ASID */
264 start
= (entries
[i
].vpn
<< 10) & ~(entries
[i
].size
- 1);
265 end
= start
+ entries
[i
].size
- 1;
266 if (address
>= start
&& address
<= end
) { /* Match */
267 if (match
!= MMU_DTLB_MISS
)
268 return MMU_DTLB_MULTIPLE
; /* Multiple match */
275 static int same_tlb_entry_exists(const tlb_t
* haystack
, uint8_t nbtlb
,
276 const tlb_t
* needle
)
279 for (i
= 0; i
< nbtlb
; i
++)
280 if (!memcmp(&haystack
[i
], needle
, sizeof(tlb_t
)))
285 static void increment_urc(CPUState
* env
)
290 urb
= ((env
->mmucr
) >> 18) & 0x3f;
291 urc
= ((env
->mmucr
) >> 10) & 0x3f;
293 if ((urb
> 0 && urc
> urb
) || urc
> (UTLB_SIZE
- 1))
295 env
->mmucr
= (env
->mmucr
& 0xffff03ff) | (urc
<< 10);
298 /* Find itlb entry - update itlb from utlb if necessary and asked for
299 Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
300 Update the itlb from utlb if update is not 0
302 static int find_itlb_entry(CPUState
* env
, target_ulong address
,
303 int use_asid
, int update
)
307 e
= find_tlb_entry(env
, address
, env
->itlb
, ITLB_SIZE
, use_asid
);
308 if (e
== MMU_DTLB_MULTIPLE
)
309 e
= MMU_ITLB_MULTIPLE
;
310 else if (e
== MMU_DTLB_MISS
&& update
) {
311 e
= find_tlb_entry(env
, address
, env
->utlb
, UTLB_SIZE
, use_asid
);
314 n
= itlb_replacement(env
);
315 ientry
= &env
->itlb
[n
];
317 if (!same_tlb_entry_exists(env
->utlb
, UTLB_SIZE
, ientry
))
318 tlb_flush_page(env
, ientry
->vpn
<< 10);
320 *ientry
= env
->utlb
[e
];
322 } else if (e
== MMU_DTLB_MISS
)
324 } else if (e
== MMU_DTLB_MISS
)
327 update_itlb_use(env
, e
);
332 Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
333 static int find_utlb_entry(CPUState
* env
, target_ulong address
, int use_asid
)
335 /* per utlb access */
339 return find_tlb_entry(env
, address
, env
->utlb
, UTLB_SIZE
, use_asid
);
342 /* Match address against MMU
343 Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
344 MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
345 MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
346 MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
347 MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
349 static int get_mmu_address(CPUState
* env
, target_ulong
* physical
,
350 int *prot
, target_ulong address
,
351 int rw
, int access_type
)
354 tlb_t
*matching
= NULL
;
356 use_asid
= (env
->mmucr
& MMUCR_SV
) == 0 || (env
->sr
& SR_MD
) == 0;
359 n
= find_itlb_entry(env
, address
, use_asid
, 1);
361 matching
= &env
->itlb
[n
];
362 if (!(env
->sr
& SR_MD
) && !(matching
->pr
& 2))
363 n
= MMU_ITLB_VIOLATION
;
368 n
= find_utlb_entry(env
, address
, use_asid
);
370 matching
= &env
->utlb
[n
];
371 if (!(env
->sr
& SR_MD
) && !(matching
->pr
& 2)) {
372 n
= (rw
== 1) ? MMU_DTLB_VIOLATION_WRITE
:
373 MMU_DTLB_VIOLATION_READ
;
374 } else if ((rw
== 1) && !(matching
->pr
& 1)) {
375 n
= MMU_DTLB_VIOLATION_WRITE
;
376 } else if ((rw
== 1) & !matching
->d
) {
377 n
= MMU_DTLB_INITIAL_WRITE
;
380 if ((matching
->pr
& 1) && matching
->d
) {
384 } else if (n
== MMU_DTLB_MISS
) {
385 n
= (rw
== 1) ? MMU_DTLB_MISS_WRITE
:
391 *physical
= ((matching
->ppn
<< 10) & ~(matching
->size
- 1)) |
392 (address
& (matching
->size
- 1));
397 static int get_physical_address(CPUState
* env
, target_ulong
* physical
,
398 int *prot
, target_ulong address
,
399 int rw
, int access_type
)
401 /* P1, P2 and P4 areas do not use translation */
402 if ((address
>= 0x80000000 && address
< 0xc0000000) ||
403 address
>= 0xe0000000) {
404 if (!(env
->sr
& SR_MD
)
405 && (address
< 0xe0000000 || address
> 0xe4000000)) {
406 /* Unauthorized access in user mode (only store queues are available) */
407 fprintf(stderr
, "Unauthorized access\n");
409 return MMU_DADDR_ERROR_READ
;
411 return MMU_DADDR_ERROR_WRITE
;
413 return MMU_IADDR_ERROR
;
415 if (address
>= 0x80000000 && address
< 0xc0000000) {
416 /* Mask upper 3 bits for P1 and P2 areas */
417 *physical
= address
& 0x1fffffff;
421 *prot
= PAGE_READ
| PAGE_WRITE
;
425 /* If MMU is disabled, return the corresponding physical page */
426 if (!env
->mmucr
& MMUCR_AT
) {
427 *physical
= address
& 0x1FFFFFFF;
428 *prot
= PAGE_READ
| PAGE_WRITE
;
432 /* We need to resort to the MMU */
433 return get_mmu_address(env
, physical
, prot
, address
, rw
, access_type
);
436 int cpu_sh4_handle_mmu_fault(CPUState
* env
, target_ulong address
, int rw
,
437 int mmu_idx
, int is_softmmu
)
439 target_ulong physical
;
440 int prot
, ret
, access_type
;
442 access_type
= ACCESS_INT
;
444 get_physical_address(env
, &physical
, &prot
, address
, rw
,
451 case MMU_DTLB_MISS_READ
:
452 env
->exception_index
= 0x040;
454 case MMU_DTLB_MULTIPLE
:
455 case MMU_ITLB_MULTIPLE
:
456 env
->exception_index
= 0x140;
458 case MMU_ITLB_VIOLATION
:
459 env
->exception_index
= 0x0a0;
461 case MMU_DTLB_MISS_WRITE
:
462 env
->exception_index
= 0x060;
464 case MMU_DTLB_INITIAL_WRITE
:
465 env
->exception_index
= 0x080;
467 case MMU_DTLB_VIOLATION_READ
:
468 env
->exception_index
= 0x0a0;
470 case MMU_DTLB_VIOLATION_WRITE
:
471 env
->exception_index
= 0x0c0;
473 case MMU_IADDR_ERROR
:
474 case MMU_DADDR_ERROR_READ
:
475 env
->exception_index
= 0x0c0;
477 case MMU_DADDR_ERROR_WRITE
:
478 env
->exception_index
= 0x100;
486 address
&= TARGET_PAGE_MASK
;
487 physical
&= TARGET_PAGE_MASK
;
489 return tlb_set_page(env
, address
, physical
, prot
, mmu_idx
, is_softmmu
);
492 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
* env
, target_ulong addr
)
494 target_ulong physical
;
497 get_physical_address(env
, &physical
, &prot
, addr
, 0, 0);
501 void cpu_load_tlb(CPUSH4State
* env
)
503 int n
= cpu_mmucr_urc(env
->mmucr
);
504 tlb_t
* entry
= &env
->utlb
[n
];
507 /* Overwriting valid entry in utlb. */
508 target_ulong address
= entry
->vpn
<< 10;
509 if (!same_tlb_entry_exists(env
->itlb
, ITLB_SIZE
, entry
)) {
510 tlb_flush_page(env
, address
);
514 /* Take values into cpu status from registers. */
515 entry
->asid
= (uint8_t)cpu_pteh_asid(env
->pteh
);
516 entry
->vpn
= cpu_pteh_vpn(env
->pteh
);
517 entry
->v
= (uint8_t)cpu_ptel_v(env
->ptel
);
518 entry
->ppn
= cpu_ptel_ppn(env
->ptel
);
519 entry
->sz
= (uint8_t)cpu_ptel_sz(env
->ptel
);
522 entry
->size
= 1024; /* 1K */
525 entry
->size
= 1024 * 4; /* 4K */
528 entry
->size
= 1024 * 64; /* 64K */
531 entry
->size
= 1024 * 1024; /* 1M */
537 entry
->sh
= (uint8_t)cpu_ptel_sh(env
->ptel
);
538 entry
->c
= (uint8_t)cpu_ptel_c(env
->ptel
);
539 entry
->pr
= (uint8_t)cpu_ptel_pr(env
->ptel
);
540 entry
->d
= (uint8_t)cpu_ptel_d(env
->ptel
);
541 entry
->wt
= (uint8_t)cpu_ptel_wt(env
->ptel
);
542 entry
->sa
= (uint8_t)cpu_ptea_sa(env
->ptea
);
543 entry
->tc
= (uint8_t)cpu_ptea_tc(env
->ptea
);
546 void cpu_sh4_invalidate_tlb(CPUSH4State
*s
)
551 for (i
= 0; i
< UTLB_SIZE
; i
++) {
552 tlb_t
* entry
= &s
->utlb
[i
];
556 for (i
= 0; i
< UTLB_SIZE
; i
++) {
557 tlb_t
* entry
= &s
->utlb
[i
];
564 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State
*s
, target_phys_addr_t addr
,
567 int associate
= addr
& 0x0000080;
568 uint32_t vpn
= (mem_value
& 0xfffffc00) >> 10;
569 uint8_t d
= (uint8_t)((mem_value
& 0x00000200) >> 9);
570 uint8_t v
= (uint8_t)((mem_value
& 0x00000100) >> 8);
571 uint8_t asid
= (uint8_t)(mem_value
& 0x000000ff);
572 int use_asid
= (s
->mmucr
& MMUCR_SV
) == 0 || (s
->sr
& SR_MD
) == 0;
576 tlb_t
* utlb_match_entry
= NULL
;
577 int needs_tlb_flush
= 0;
580 for (i
= 0; i
< UTLB_SIZE
; i
++) {
581 tlb_t
* entry
= &s
->utlb
[i
];
585 if (entry
->vpn
== vpn
586 && (!use_asid
|| entry
->asid
== asid
|| entry
->sh
)) {
587 if (utlb_match_entry
) {
588 /* Multiple TLB Exception */
589 s
->exception_index
= 0x140;
597 utlb_match_entry
= entry
;
599 increment_urc(s
); /* per utlb access */
603 for (i
= 0; i
< ITLB_SIZE
; i
++) {
604 tlb_t
* entry
= &s
->itlb
[i
];
605 if (entry
->vpn
== vpn
606 && (!use_asid
|| entry
->asid
== asid
|| entry
->sh
)) {
609 if (utlb_match_entry
)
610 *entry
= *utlb_match_entry
;
618 tlb_flush_page(s
, vpn
<< 10);
621 int index
= (addr
& 0x00003f00) >> 8;
622 tlb_t
* entry
= &s
->utlb
[index
];
624 /* Overwriting valid entry in utlb. */
625 target_ulong address
= entry
->vpn
<< 10;
626 if (!same_tlb_entry_exists(s
->itlb
, ITLB_SIZE
, entry
)) {
627 tlb_flush_page(s
, address
);
638 int cpu_sh4_is_cached(CPUSH4State
* env
, target_ulong addr
)
641 int use_asid
= (env
->mmucr
& MMUCR_SV
) == 0 || (env
->sr
& SR_MD
) == 0;
644 if (env
->sr
& SR_MD
) {
645 /* For previledged mode, P2 and P4 area is not cachable. */
646 if ((0xA0000000 <= addr
&& addr
< 0xC0000000) || 0xE0000000 <= addr
)
649 /* For user mode, only U0 area is cachable. */
650 if (0x80000000 <= addr
)
655 * TODO : Evaluate CCR and check if the cache is on or off.
656 * Now CCR is not in CPUSH4State, but in SH7750State.
657 * When you move the ccr inot CPUSH4State, the code will be
661 /* check if operand cache is enabled or not. */
666 /* if MMU is off, no check for TLB. */
667 if (env
->mmucr
& MMUCR_AT
)
671 n
= find_tlb_entry(env
, addr
, env
->itlb
, ITLB_SIZE
, use_asid
);
673 return env
->itlb
[n
].c
;
675 n
= find_tlb_entry(env
, addr
, env
->utlb
, UTLB_SIZE
, use_asid
);
677 return env
->utlb
[n
].c
;