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git.proxmox.com Git - qemu.git/blob - target-sh4/helper.c
4 * Copyright (c) 2005 Samuel Tardieu
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 #include "hw/sh_intc.h"
32 #if defined(CONFIG_USER_ONLY)
34 void do_interrupt (CPUState
*env
)
36 env
->exception_index
= -1;
39 int cpu_sh4_handle_mmu_fault(CPUState
* env
, target_ulong address
, int rw
,
40 int mmu_idx
, int is_softmmu
)
43 env
->exception_index
= 0;
47 env
->exception_index
= 0x0a0;
51 env
->exception_index
= 0x0c0;
57 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
* env
, target_ulong addr
)
62 #else /* !CONFIG_USER_ONLY */
65 #define MMU_ITLB_MISS (-1)
66 #define MMU_ITLB_MULTIPLE (-2)
67 #define MMU_ITLB_VIOLATION (-3)
68 #define MMU_DTLB_MISS_READ (-4)
69 #define MMU_DTLB_MISS_WRITE (-5)
70 #define MMU_DTLB_INITIAL_WRITE (-6)
71 #define MMU_DTLB_VIOLATION_READ (-7)
72 #define MMU_DTLB_VIOLATION_WRITE (-8)
73 #define MMU_DTLB_MULTIPLE (-9)
74 #define MMU_DTLB_MISS (-10)
76 void do_interrupt(CPUState
* env
)
78 int do_irq
= env
->interrupt_request
& CPU_INTERRUPT_HARD
;
79 int do_exp
, irq_vector
= env
->exception_index
;
81 /* prioritize exceptions over interrupts */
83 do_exp
= env
->exception_index
!= -1;
84 do_irq
= do_irq
&& (env
->exception_index
== -1);
86 if (env
->sr
& SR_BL
) {
87 if (do_exp
&& env
->exception_index
!= 0x1e0) {
88 env
->exception_index
= 0x000; /* masked exception -> reset */
96 irq_vector
= sh_intc_get_pending_vector(env
->intc_handle
,
97 (env
->sr
>> 4) & 0xf);
98 if (irq_vector
== -1) {
103 if (loglevel
& CPU_LOG_INT
) {
105 switch (env
->exception_index
) {
107 expname
= "addr_error";
110 expname
= "tlb_miss";
113 expname
= "tlb_violation";
116 expname
= "illegal_instruction";
119 expname
= "slot_illegal_instruction";
122 expname
= "fpu_disable";
125 expname
= "slot_fpu";
128 expname
= "data_write";
131 expname
= "dtlb_miss_write";
134 expname
= "dtlb_violation_write";
137 expname
= "fpu_exception";
140 expname
= "initial_page_write";
146 expname
= do_irq
? "interrupt" : "???";
149 fprintf(logfile
, "exception 0x%03x [%s] raised\n",
150 irq_vector
, expname
);
151 cpu_dump_state(env
, logfile
, fprintf
, 0);
156 env
->sgr
= env
->gregs
[15];
157 env
->sr
|= SR_BL
| SR_MD
| SR_RB
;
160 env
->expevt
= env
->exception_index
;
161 switch (env
->exception_index
) {
166 env
->sr
|= 0xf << 4; /* IMASK */
167 env
->pc
= 0xa0000000;
171 env
->pc
= env
->vbr
+ 0x400;
174 env
->spc
+= 2; /* special case for TRAPA */
177 env
->pc
= env
->vbr
+ 0x100;
184 env
->intevt
= irq_vector
;
185 env
->pc
= env
->vbr
+ 0x600;
190 static void update_itlb_use(CPUState
* env
, int itlbnb
)
192 uint8_t or_mask
= 0, and_mask
= (uint8_t) - 1;
211 env
->mmucr
&= (and_mask
<< 24) | 0x00ffffff;
212 env
->mmucr
|= (or_mask
<< 24);
215 static int itlb_replacement(CPUState
* env
)
217 if ((env
->mmucr
& 0xe0000000) == 0xe0000000)
219 if ((env
->mmucr
& 0x98000000) == 0x18000000)
221 if ((env
->mmucr
& 0x54000000) == 0x04000000)
223 if ((env
->mmucr
& 0x2c000000) == 0x00000000)
228 /* Find the corresponding entry in the right TLB
229 Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
231 static int find_tlb_entry(CPUState
* env
, target_ulong address
,
232 tlb_t
* entries
, uint8_t nbtlb
, int use_asid
)
234 int match
= MMU_DTLB_MISS
;
239 asid
= env
->pteh
& 0xff;
241 for (i
= 0; i
< nbtlb
; i
++) {
243 continue; /* Invalid entry */
244 if (use_asid
&& entries
[i
].asid
!= asid
&& !entries
[i
].sh
)
245 continue; /* Bad ASID */
247 switch (entries
[i
].sz
) {
249 size
= 1024; /* 1kB */
252 size
= 4 * 1024; /* 4kB */
255 size
= 64 * 1024; /* 64kB */
258 size
= 1024 * 1024; /* 1MB */
264 start
= (entries
[i
].vpn
<< 10) & ~(entries
[i
].size
- 1);
265 end
= start
+ entries
[i
].size
- 1;
266 if (address
>= start
&& address
<= end
) { /* Match */
267 if (match
!= MMU_DTLB_MISS
)
268 return MMU_DTLB_MULTIPLE
; /* Multiple match */
275 /* Find itlb entry - update itlb from utlb if necessary and asked for
276 Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
277 Update the itlb from utlb if update is not 0
279 int find_itlb_entry(CPUState
* env
, target_ulong address
,
280 int use_asid
, int update
)
284 e
= find_tlb_entry(env
, address
, env
->itlb
, ITLB_SIZE
, use_asid
);
285 if (e
== MMU_DTLB_MULTIPLE
)
286 e
= MMU_ITLB_MULTIPLE
;
287 else if (e
== MMU_DTLB_MISS
&& update
) {
288 e
= find_tlb_entry(env
, address
, env
->utlb
, UTLB_SIZE
, use_asid
);
290 n
= itlb_replacement(env
);
291 env
->itlb
[n
] = env
->utlb
[e
];
293 } else if (e
== MMU_DTLB_MISS
)
295 } else if (e
== MMU_DTLB_MISS
)
298 update_itlb_use(env
, e
);
303 Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
304 int find_utlb_entry(CPUState
* env
, target_ulong address
, int use_asid
)
309 urb
= ((env
->mmucr
) >> 18) & 0x3f;
310 urc
= ((env
->mmucr
) >> 10) & 0x3f;
312 if (urc
== urb
|| urc
== UTLB_SIZE
- 1)
314 env
->mmucr
= (env
->mmucr
& 0xffff03ff) | (urc
<< 10);
317 return find_tlb_entry(env
, address
, env
->utlb
, UTLB_SIZE
, use_asid
);
320 /* Match address against MMU
321 Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
322 MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
323 MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
324 MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION
326 static int get_mmu_address(CPUState
* env
, target_ulong
* physical
,
327 int *prot
, target_ulong address
,
328 int rw
, int access_type
)
330 int use_asid
, is_code
, n
;
331 tlb_t
*matching
= NULL
;
333 use_asid
= (env
->mmucr
& MMUCR_SV
) == 0 && (env
->sr
& SR_MD
) == 0;
334 is_code
= env
->pc
== address
; /* Hack */
336 /* Use a hack to find if this is an instruction or data access */
337 if (env
->pc
== address
&& !(rw
& PAGE_WRITE
)) {
338 n
= find_itlb_entry(env
, address
, use_asid
, 1);
340 matching
= &env
->itlb
[n
];
341 if ((env
->sr
& SR_MD
) & !(matching
->pr
& 2))
342 n
= MMU_ITLB_VIOLATION
;
347 n
= find_utlb_entry(env
, address
, use_asid
);
349 matching
= &env
->utlb
[n
];
350 switch ((matching
->pr
<< 1) | ((env
->sr
& SR_MD
) ? 1 : 0)) {
353 n
= (rw
& PAGE_WRITE
) ? MMU_DTLB_VIOLATION_WRITE
:
354 MMU_DTLB_VIOLATION_READ
;
360 n
= MMU_DTLB_VIOLATION_WRITE
;
367 *prot
= rw
& (PAGE_READ
| PAGE_WRITE
);
370 } else if (n
== MMU_DTLB_MISS
) {
371 n
= (rw
& PAGE_WRITE
) ? MMU_DTLB_MISS_WRITE
:
376 *physical
= ((matching
->ppn
<< 10) & ~(matching
->size
- 1)) |
377 (address
& (matching
->size
- 1));
378 if ((rw
& PAGE_WRITE
) & !matching
->d
)
379 n
= MMU_DTLB_INITIAL_WRITE
;
386 int get_physical_address(CPUState
* env
, target_ulong
* physical
,
387 int *prot
, target_ulong address
,
388 int rw
, int access_type
)
390 /* P1, P2 and P4 areas do not use translation */
391 if ((address
>= 0x80000000 && address
< 0xc0000000) ||
392 address
>= 0xe0000000) {
393 if (!(env
->sr
& SR_MD
)
394 && (address
< 0xe0000000 || address
> 0xe4000000)) {
395 /* Unauthorized access in user mode (only store queues are available) */
396 fprintf(stderr
, "Unauthorized access\n");
397 return (rw
& PAGE_WRITE
) ? MMU_DTLB_MISS_WRITE
:
400 /* Mask upper 3 bits */
401 *physical
= address
& 0x1FFFFFFF;
402 *prot
= PAGE_READ
| PAGE_WRITE
;
406 /* If MMU is disabled, return the corresponding physical page */
407 if (!env
->mmucr
& MMUCR_AT
) {
408 *physical
= address
& 0x1FFFFFFF;
409 *prot
= PAGE_READ
| PAGE_WRITE
;
413 /* We need to resort to the MMU */
414 return get_mmu_address(env
, physical
, prot
, address
, rw
, access_type
);
417 int cpu_sh4_handle_mmu_fault(CPUState
* env
, target_ulong address
, int rw
,
418 int mmu_idx
, int is_softmmu
)
420 target_ulong physical
, page_offset
, page_size
;
421 int prot
, ret
, access_type
;
430 case 2: /* READ_ACCESS_TYPE == 2 defined in softmmu_template.h */
440 fprintf(stderr
, "%s pc %08x ad %08x rw %d mmu_idx %d smmu %d\n",
441 __func__
, env
->pc
, address
, rw
, mmu_idx
, is_softmmu
);
444 access_type
= ACCESS_INT
;
446 get_physical_address(env
, &physical
, &prot
, address
, rw
,
453 case MMU_DTLB_MISS_READ
:
454 env
->exception_index
= 0x040;
456 case MMU_DTLB_MULTIPLE
:
457 case MMU_ITLB_MULTIPLE
:
458 env
->exception_index
= 0x140;
460 case MMU_ITLB_VIOLATION
:
461 env
->exception_index
= 0x0a0;
463 case MMU_DTLB_MISS_WRITE
:
464 env
->exception_index
= 0x060;
466 case MMU_DTLB_INITIAL_WRITE
:
467 env
->exception_index
= 0x080;
469 case MMU_DTLB_VIOLATION_READ
:
470 env
->exception_index
= 0x0a0;
472 case MMU_DTLB_VIOLATION_WRITE
:
473 env
->exception_index
= 0x0c0;
481 page_size
= TARGET_PAGE_SIZE
;
483 (address
- (address
& TARGET_PAGE_MASK
)) & ~(page_size
- 1);
484 address
= (address
& TARGET_PAGE_MASK
) + page_offset
;
485 physical
= (physical
& TARGET_PAGE_MASK
) + page_offset
;
487 return tlb_set_page(env
, address
, physical
, prot
, mmu_idx
, is_softmmu
);
490 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
* env
, target_ulong addr
)
492 target_ulong physical
;
495 get_physical_address(env
, &physical
, &prot
, addr
, PAGE_READ
, 0);
499 void cpu_load_tlb(CPUState
* env
)
501 int n
= cpu_mmucr_urc(env
->mmucr
);
502 tlb_t
* entry
= &env
->utlb
[n
];
504 /* Take values into cpu status from registers. */
505 entry
->asid
= (uint8_t)cpu_pteh_asid(env
->pteh
);
506 entry
->vpn
= cpu_pteh_vpn(env
->pteh
);
507 entry
->v
= (uint8_t)cpu_ptel_v(env
->ptel
);
508 entry
->ppn
= cpu_ptel_ppn(env
->ptel
);
509 entry
->sz
= (uint8_t)cpu_ptel_sz(env
->ptel
);
512 entry
->size
= 1024; /* 1K */
515 entry
->size
= 1024 * 4; /* 4K */
518 entry
->size
= 1024 * 64; /* 64K */
521 entry
->size
= 1024 * 1024; /* 1M */
527 entry
->sh
= (uint8_t)cpu_ptel_sh(env
->ptel
);
528 entry
->c
= (uint8_t)cpu_ptel_c(env
->ptel
);
529 entry
->pr
= (uint8_t)cpu_ptel_pr(env
->ptel
);
530 entry
->d
= (uint8_t)cpu_ptel_d(env
->ptel
);
531 entry
->wt
= (uint8_t)cpu_ptel_wt(env
->ptel
);
532 entry
->sa
= (uint8_t)cpu_ptea_sa(env
->ptea
);
533 entry
->tc
= (uint8_t)cpu_ptea_tc(env
->ptea
);