target-sh4/op_helper.c

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <assert.h>
  20 #include <stdlib.h>
  21 #include "cpu.h"
  22 #include "helper.h"
  23
  24 static void cpu_restore_state_from_retaddr(CPUSH4State *env, uintptr_t retaddr)
  25 {
  26     TranslationBlock *tb;
  27
  28     if (retaddr) {
  29         tb = tb_find_pc(retaddr);
  30         if (tb) {
  31             /* the PC is inside the translated code. It means that we have
  32                a virtual CPU fault */
  33             cpu_restore_state(tb, env, retaddr);
  34         }
  35     }
  36 }
  37
  38 #ifndef CONFIG_USER_ONLY
  39 #include "softmmu_exec.h"
  40
  41 #define MMUSUFFIX _mmu
  42
  43 #define SHIFT 0
  44 #include "softmmu_template.h"
  45
  46 #define SHIFT 1
  47 #include "softmmu_template.h"
  48
  49 #define SHIFT 2
  50 #include "softmmu_template.h"
  51
  52 #define SHIFT 3
  53 #include "softmmu_template.h"
  54
  55 void tlb_fill(CPUSH4State *env, target_ulong addr, int is_write, int mmu_idx,
  56               uintptr_t retaddr)
  57 {
  58     int ret;
  59
  60     ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx);
  61     if (ret) {
  62         /* now we have a real cpu fault */
  63         cpu_restore_state_from_retaddr(env, retaddr);
  64         cpu_loop_exit(env);
  65     }
  66 }
  67
  68 #endif
  69
  70 void helper_ldtlb(CPUSH4State *env)
  71 {
  72 #ifdef CONFIG_USER_ONLY
  73     /* XXXXX */
  74     cpu_abort(env, "Unhandled ldtlb");
  75 #else
  76     cpu_load_tlb(env);
  77 #endif
  78 }
  79
  80 static inline void raise_exception(CPUSH4State *env, int index,
  81                                    uintptr_t retaddr)
  82 {
  83     env->exception_index = index;
  84     cpu_restore_state_from_retaddr(env, retaddr);
  85     cpu_loop_exit(env);
  86 }
  87
  88 void helper_raise_illegal_instruction(CPUSH4State *env)
  89 {
  90     raise_exception(env, 0x180, GETPC());
  91 }
  92
  93 void helper_raise_slot_illegal_instruction(CPUSH4State *env)
  94 {
  95     raise_exception(env, 0x1a0, GETPC());
  96 }
  97
  98 void helper_raise_fpu_disable(CPUSH4State *env)
  99 {
 100     raise_exception(env, 0x800, GETPC());
 101 }
 102
 103 void helper_raise_slot_fpu_disable(CPUSH4State *env)
 104 {
 105     raise_exception(env, 0x820, GETPC());
 106 }
 107
 108 void helper_debug(CPUSH4State *env)
 109 {
 110     env->exception_index = EXCP_DEBUG;
 111     cpu_loop_exit(env);
 112 }
 113
 114 void helper_sleep(CPUSH4State *env, uint32_t next_pc)
 115 {
 116     env->halted = 1;
 117     env->in_sleep = 1;
 118     env->exception_index = EXCP_HLT;
 119     env->pc = next_pc;
 120     cpu_loop_exit(env);
 121 }
 122
 123 void helper_trapa(CPUSH4State *env, uint32_t tra)
 124 {
 125     env->tra = tra << 2;
 126     raise_exception(env, 0x160, GETPC());
 127 }
 128
 129 void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
 130 {
 131     if (cpu_sh4_is_cached (env, address))
 132     {
 133         memory_content *r = malloc (sizeof(memory_content));
 134         r->address = address;
 135         r->value = value;
 136         r->next = NULL;
 137
 138         *(env->movcal_backup_tail) = r;
 139         env->movcal_backup_tail = &(r->next);
 140     }
 141 }
 142
 143 void helper_discard_movcal_backup(CPUSH4State *env)
 144 {
 145     memory_content *current = env->movcal_backup;
 146
 147     while(current)
 148     {
 149         memory_content *next = current->next;
 150         free (current);
 151         env->movcal_backup = current = next;
 152         if (current == NULL)
 153             env->movcal_backup_tail = &(env->movcal_backup);
 154     }
 155 }
 156
 157 void helper_ocbi(CPUSH4State *env, uint32_t address)
 158 {
 159     memory_content **current = &(env->movcal_backup);
 160     while (*current)
 161     {
 162         uint32_t a = (*current)->address;
 163         if ((a & ~0x1F) == (address & ~0x1F))
 164         {
 165             memory_content *next = (*current)->next;
 166             cpu_stl_data(env, a, (*current)->value);
 167
 168             if (next == NULL)
 169             {
 170                 env->movcal_backup_tail = current;
 171             }
 172
 173             free (*current);
 174             *current = next;
 175             break;
 176         }
 177     }
 178 }
 179
 180 uint32_t helper_addv(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 181 {
 182     uint32_t dest, src, ans;
 183
 184     if ((int32_t) arg1 >= 0)
 185         dest = 0;
 186     else
 187         dest = 1;
 188     if ((int32_t) arg0 >= 0)
 189         src = 0;
 190     else
 191         src = 1;
 192     src += dest;
 193     arg1 += arg0;
 194     if ((int32_t) arg1 >= 0)
 195         ans = 0;
 196     else
 197         ans = 1;
 198     ans += dest;
 199     if (src == 0 || src == 2) {
 200         if (ans == 1)
 201             env->sr |= SR_T;
 202         else
 203             env->sr &= ~SR_T;
 204     } else
 205         env->sr &= ~SR_T;
 206     return arg1;
 207 }
 208
 209 #define T (env->sr & SR_T)
 210 #define Q (env->sr & SR_Q ? 1 : 0)
 211 #define M (env->sr & SR_M ? 1 : 0)
 212 #define SETT env->sr |= SR_T
 213 #define CLRT env->sr &= ~SR_T
 214 #define SETQ env->sr |= SR_Q
 215 #define CLRQ env->sr &= ~SR_Q
 216 #define SETM env->sr |= SR_M
 217 #define CLRM env->sr &= ~SR_M
 218
 219 uint32_t helper_div1(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 220 {
 221     uint32_t tmp0, tmp2;
 222     uint8_t old_q, tmp1 = 0xff;
 223
 224     //printf("div1 arg0=0x%08x arg1=0x%08x M=%d Q=%d T=%d\n", arg0, arg1, M, Q, T);
 225     old_q = Q;
 226     if ((0x80000000 & arg1) != 0)
 227         SETQ;
 228     else
 229         CLRQ;
 230     tmp2 = arg0;
 231     arg1 <<= 1;
 232     arg1 |= T;
 233     switch (old_q) {
 234     case 0:
 235         switch (M) {
 236         case 0:
 237             tmp0 = arg1;
 238             arg1 -= tmp2;
 239             tmp1 = arg1 > tmp0;
 240             switch (Q) {
 241             case 0:
 242                 if (tmp1)
 243                     SETQ;
 244                 else
 245                     CLRQ;
 246                 break;
 247             case 1:
 248                 if (tmp1 == 0)
 249                     SETQ;
 250                 else
 251                     CLRQ;
 252                 break;
 253             }
 254             break;
 255         case 1:
 256             tmp0 = arg1;
 257             arg1 += tmp2;
 258             tmp1 = arg1 < tmp0;
 259             switch (Q) {
 260             case 0:
 261                 if (tmp1 == 0)
 262                     SETQ;
 263                 else
 264                     CLRQ;
 265                 break;
 266             case 1:
 267                 if (tmp1)
 268                     SETQ;
 269                 else
 270                     CLRQ;
 271                 break;
 272             }
 273             break;
 274         }
 275         break;
 276     case 1:
 277         switch (M) {
 278         case 0:
 279             tmp0 = arg1;
 280             arg1 += tmp2;
 281             tmp1 = arg1 < tmp0;
 282             switch (Q) {
 283             case 0:
 284                 if (tmp1)
 285                     SETQ;
 286                 else
 287                     CLRQ;
 288                 break;
 289             case 1:
 290                 if (tmp1 == 0)
 291                     SETQ;
 292                 else
 293                     CLRQ;
 294                 break;
 295             }
 296             break;
 297         case 1:
 298             tmp0 = arg1;
 299             arg1 -= tmp2;
 300             tmp1 = arg1 > tmp0;
 301             switch (Q) {
 302             case 0:
 303                 if (tmp1 == 0)
 304                     SETQ;
 305                 else
 306                     CLRQ;
 307                 break;
 308             case 1:
 309                 if (tmp1)
 310                     SETQ;
 311                 else
 312                     CLRQ;
 313                 break;
 314             }
 315             break;
 316         }
 317         break;
 318     }
 319     if (Q == M)
 320         SETT;
 321     else
 322         CLRT;
 323     //printf("Output: arg1=0x%08x M=%d Q=%d T=%d\n", arg1, M, Q, T);
 324     return arg1;
 325 }
 326
 327 void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 328 {
 329     int64_t res;
 330
 331     res = ((uint64_t) env->mach << 32) | env->macl;
 332     res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
 333     env->mach = (res >> 32) & 0xffffffff;
 334     env->macl = res & 0xffffffff;
 335     if (env->sr & SR_S) {
 336         if (res < 0)
 337             env->mach |= 0xffff0000;
 338         else
 339             env->mach &= 0x00007fff;
 340     }
 341 }
 342
 343 void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 344 {
 345     int64_t res;
 346
 347     res = ((uint64_t) env->mach << 32) | env->macl;
 348     res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
 349     env->mach = (res >> 32) & 0xffffffff;
 350     env->macl = res & 0xffffffff;
 351     if (env->sr & SR_S) {
 352         if (res < -0x80000000) {
 353             env->mach = 1;
 354             env->macl = 0x80000000;
 355         } else if (res > 0x000000007fffffff) {
 356             env->mach = 1;
 357             env->macl = 0x7fffffff;
 358         }
 359     }
 360 }
 361
 362 uint32_t helper_subv(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 363 {
 364     int32_t dest, src, ans;
 365
 366     if ((int32_t) arg1 >= 0)
 367         dest = 0;
 368     else
 369         dest = 1;
 370     if ((int32_t) arg0 >= 0)
 371         src = 0;
 372     else
 373         src = 1;
 374     src += dest;
 375     arg1 -= arg0;
 376     if ((int32_t) arg1 >= 0)
 377         ans = 0;
 378     else
 379         ans = 1;
 380     ans += dest;
 381     if (src == 1) {
 382         if (ans == 1)
 383             env->sr |= SR_T;
 384         else
 385             env->sr &= ~SR_T;
 386     } else
 387         env->sr &= ~SR_T;
 388     return arg1;
 389 }
 390
 391 static inline void set_t(CPUSH4State *env)
 392 {
 393     env->sr |= SR_T;
 394 }
 395
 396 static inline void clr_t(CPUSH4State *env)
 397 {
 398     env->sr &= ~SR_T;
 399 }
 400
 401 void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
 402 {
 403     env->fpscr = val & FPSCR_MASK;
 404     if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
 405         set_float_rounding_mode(float_round_to_zero, &env->fp_status);
 406     } else {
 407         set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 408     }
 409     set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
 410 }
 411
 412 static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
 413 {
 414     int xcpt, cause, enable;
 415
 416     xcpt = get_float_exception_flags(&env->fp_status);
 417
 418     /* Clear the flag entries */
 419     env->fpscr &= ~FPSCR_FLAG_MASK;
 420
 421     if (unlikely(xcpt)) {
 422         if (xcpt & float_flag_invalid) {
 423             env->fpscr |= FPSCR_FLAG_V;
 424         }
 425         if (xcpt & float_flag_divbyzero) {
 426             env->fpscr |= FPSCR_FLAG_Z;
 427         }
 428         if (xcpt & float_flag_overflow) {
 429             env->fpscr |= FPSCR_FLAG_O;
 430         }
 431         if (xcpt & float_flag_underflow) {
 432             env->fpscr |= FPSCR_FLAG_U;
 433         }
 434         if (xcpt & float_flag_inexact) {
 435             env->fpscr |= FPSCR_FLAG_I;
 436         }
 437
 438         /* Accumulate in cause entries */
 439         env->fpscr |= (env->fpscr & FPSCR_FLAG_MASK)
 440                       << (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);
 441
 442         /* Generate an exception if enabled */
 443         cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
 444         enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
 445         if (cause & enable) {
 446             cpu_restore_state_from_retaddr(env, retaddr);
 447             env->exception_index = 0x120;
 448             cpu_loop_exit(env);
 449         }
 450     }
 451 }
 452
 453 float32 helper_fabs_FT(float32 t0)
 454 {
 455     return float32_abs(t0);
 456 }
 457
 458 float64 helper_fabs_DT(float64 t0)
 459 {
 460     return float64_abs(t0);
 461 }
 462
 463 float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
 464 {
 465     set_float_exception_flags(0, &env->fp_status);
 466     t0 = float32_add(t0, t1, &env->fp_status);
 467     update_fpscr(env, GETPC());
 468     return t0;
 469 }
 470
 471 float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
 472 {
 473     set_float_exception_flags(0, &env->fp_status);
 474     t0 = float64_add(t0, t1, &env->fp_status);
 475     update_fpscr(env, GETPC());
 476     return t0;
 477 }
 478
 479 void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
 480 {
 481     int relation;
 482
 483     set_float_exception_flags(0, &env->fp_status);
 484     relation = float32_compare(t0, t1, &env->fp_status);
 485     if (unlikely(relation == float_relation_unordered)) {
 486         update_fpscr(env, GETPC());
 487     } else if (relation == float_relation_equal) {
 488         set_t(env);
 489     } else {
 490         clr_t(env);
 491     }
 492 }
 493
 494 void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
 495 {
 496     int relation;
 497
 498     set_float_exception_flags(0, &env->fp_status);
 499     relation = float64_compare(t0, t1, &env->fp_status);
 500     if (unlikely(relation == float_relation_unordered)) {
 501         update_fpscr(env, GETPC());
 502     } else if (relation == float_relation_equal) {
 503         set_t(env);
 504     } else {
 505         clr_t(env);
 506     }
 507 }
 508
 509 void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
 510 {
 511     int relation;
 512
 513     set_float_exception_flags(0, &env->fp_status);
 514     relation = float32_compare(t0, t1, &env->fp_status);
 515     if (unlikely(relation == float_relation_unordered)) {
 516         update_fpscr(env, GETPC());
 517     } else if (relation == float_relation_greater) {
 518         set_t(env);
 519     } else {
 520         clr_t(env);
 521     }
 522 }
 523
 524 void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
 525 {
 526     int relation;
 527
 528     set_float_exception_flags(0, &env->fp_status);
 529     relation = float64_compare(t0, t1, &env->fp_status);
 530     if (unlikely(relation == float_relation_unordered)) {
 531         update_fpscr(env, GETPC());
 532     } else if (relation == float_relation_greater) {
 533         set_t(env);
 534     } else {
 535         clr_t(env);
 536     }
 537 }
 538
 539 float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
 540 {
 541     float64 ret;
 542     set_float_exception_flags(0, &env->fp_status);
 543     ret = float32_to_float64(t0, &env->fp_status);
 544     update_fpscr(env, GETPC());
 545     return ret;
 546 }
 547
 548 float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
 549 {
 550     float32 ret;
 551     set_float_exception_flags(0, &env->fp_status);
 552     ret = float64_to_float32(t0, &env->fp_status);
 553     update_fpscr(env, GETPC());
 554     return ret;
 555 }
 556
 557 float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1)
 558 {
 559     set_float_exception_flags(0, &env->fp_status);
 560     t0 = float32_div(t0, t1, &env->fp_status);
 561     update_fpscr(env, GETPC());
 562     return t0;
 563 }
 564
 565 float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1)
 566 {
 567     set_float_exception_flags(0, &env->fp_status);
 568     t0 = float64_div(t0, t1, &env->fp_status);
 569     update_fpscr(env, GETPC());
 570     return t0;
 571 }
 572
 573 float32 helper_float_FT(CPUSH4State *env, uint32_t t0)
 574 {
 575     float32 ret;
 576     set_float_exception_flags(0, &env->fp_status);
 577     ret = int32_to_float32(t0, &env->fp_status);
 578     update_fpscr(env, GETPC());
 579     return ret;
 580 }
 581
 582 float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
 583 {
 584     float64 ret;
 585     set_float_exception_flags(0, &env->fp_status);
 586     ret = int32_to_float64(t0, &env->fp_status);
 587     update_fpscr(env, GETPC());
 588     return ret;
 589 }
 590
 591 float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
 592 {
 593     set_float_exception_flags(0, &env->fp_status);
 594     t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status);
 595     update_fpscr(env, GETPC());
 596     return t0;
 597 }
 598
 599 float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
 600 {
 601     set_float_exception_flags(0, &env->fp_status);
 602     t0 = float32_mul(t0, t1, &env->fp_status);
 603     update_fpscr(env, GETPC());
 604     return t0;
 605 }
 606
 607 float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
 608 {
 609     set_float_exception_flags(0, &env->fp_status);
 610     t0 = float64_mul(t0, t1, &env->fp_status);
 611     update_fpscr(env, GETPC());
 612     return t0;
 613 }
 614
 615 float32 helper_fneg_T(float32 t0)
 616 {
 617     return float32_chs(t0);
 618 }
 619
 620 float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
 621 {
 622     set_float_exception_flags(0, &env->fp_status);
 623     t0 = float32_sqrt(t0, &env->fp_status);
 624     update_fpscr(env, GETPC());
 625     return t0;
 626 }
 627
 628 float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0)
 629 {
 630     set_float_exception_flags(0, &env->fp_status);
 631     t0 = float64_sqrt(t0, &env->fp_status);
 632     update_fpscr(env, GETPC());
 633     return t0;
 634 }
 635
 636 float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1)
 637 {
 638     set_float_exception_flags(0, &env->fp_status);
 639     t0 = float32_sub(t0, t1, &env->fp_status);
 640     update_fpscr(env, GETPC());
 641     return t0;
 642 }
 643
 644 float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
 645 {
 646     set_float_exception_flags(0, &env->fp_status);
 647     t0 = float64_sub(t0, t1, &env->fp_status);
 648     update_fpscr(env, GETPC());
 649     return t0;
 650 }
 651
 652 uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0)
 653 {
 654     uint32_t ret;
 655     set_float_exception_flags(0, &env->fp_status);
 656     ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
 657     update_fpscr(env, GETPC());
 658     return ret;
 659 }
 660
 661 uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
 662 {
 663     uint32_t ret;
 664     set_float_exception_flags(0, &env->fp_status);
 665     ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
 666     update_fpscr(env, GETPC());
 667     return ret;
 668 }
 669
 670 void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
 671 {
 672     int bank, i;
 673     float32 r, p;
 674
 675     bank = (env->sr & FPSCR_FR) ? 16 : 0;
 676     r = float32_zero;
 677     set_float_exception_flags(0, &env->fp_status);
 678
 679     for (i = 0 ; i < 4 ; i++) {
 680         p = float32_mul(env->fregs[bank + m + i],
 681                         env->fregs[bank + n + i],
 682                         &env->fp_status);
 683         r = float32_add(r, p, &env->fp_status);
 684     }
 685     update_fpscr(env, GETPC());
 686
 687     env->fregs[bank + n + 3] = r;
 688 }
 689
 690 void helper_ftrv(CPUSH4State *env, uint32_t n)
 691 {
 692     int bank_matrix, bank_vector;
 693     int i, j;
 694     float32 r[4];
 695     float32 p;
 696
 697     bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
 698     bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
 699     set_float_exception_flags(0, &env->fp_status);
 700     for (i = 0 ; i < 4 ; i++) {
 701         r[i] = float32_zero;
 702         for (j = 0 ; j < 4 ; j++) {
 703             p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
 704                             env->fregs[bank_vector + j],
 705                             &env->fp_status);
 706             r[i] = float32_add(r[i], p, &env->fp_status);
 707         }
 708     }
 709     update_fpscr(env, GETPC());
 710
 711     for (i = 0 ; i < 4 ; i++) {
 712         env->fregs[bank_vector + i] = r[i];
 713     }
 714 }