target-sh4/op_helper.c

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <assert.h>
  20 #include <stdlib.h>
  21 #include "cpu.h"
  22 #include "helper.h"
  23
  24 static void cpu_restore_state_from_retaddr(CPUSH4State *env, uintptr_t retaddr)
  25 {
  26     TranslationBlock *tb;
  27
  28     if (retaddr) {
  29         tb = tb_find_pc(retaddr);
  30         if (tb) {
  31             /* the PC is inside the translated code. It means that we have
  32                a virtual CPU fault */
  33             cpu_restore_state(tb, env, retaddr);
  34         }
  35     }
  36 }
  37
  38 #ifndef CONFIG_USER_ONLY
  39 #include "softmmu_exec.h"
  40
  41 #define MMUSUFFIX _mmu
  42
  43 #define SHIFT 0
  44 #include "softmmu_template.h"
  45
  46 #define SHIFT 1
  47 #include "softmmu_template.h"
  48
  49 #define SHIFT 2
  50 #include "softmmu_template.h"
  51
  52 #define SHIFT 3
  53 #include "softmmu_template.h"
  54
  55 void tlb_fill(CPUSH4State *env, target_ulong addr, int is_write, int mmu_idx,
  56               uintptr_t retaddr)
  57 {
  58     int ret;
  59
  60     ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx);
  61     if (ret) {
  62         /* now we have a real cpu fault */
  63         cpu_restore_state_from_retaddr(env, retaddr);
  64         cpu_loop_exit(env);
  65     }
  66 }
  67
  68 #endif
  69
  70 void helper_ldtlb(CPUSH4State *env)
  71 {
  72 #ifdef CONFIG_USER_ONLY
  73     /* XXXXX */
  74     cpu_abort(env, "Unhandled ldtlb");
  75 #else
  76     cpu_load_tlb(env);
  77 #endif
  78 }
  79
  80 static inline void raise_exception(CPUSH4State *env, int index,
  81                                    uintptr_t retaddr)
  82 {
  83     env->exception_index = index;
  84     cpu_restore_state_from_retaddr(env, retaddr);
  85     cpu_loop_exit(env);
  86 }
  87
  88 void helper_raise_illegal_instruction(CPUSH4State *env)
  89 {
  90     raise_exception(env, 0x180, GETPC());
  91 }
  92
  93 void helper_raise_slot_illegal_instruction(CPUSH4State *env)
  94 {
  95     raise_exception(env, 0x1a0, GETPC());
  96 }
  97
  98 void helper_raise_fpu_disable(CPUSH4State *env)
  99 {
 100     raise_exception(env, 0x800, GETPC());
 101 }
 102
 103 void helper_raise_slot_fpu_disable(CPUSH4State *env)
 104 {
 105     raise_exception(env, 0x820, GETPC());
 106 }
 107
 108 void helper_debug(CPUSH4State *env)
 109 {
 110     env->exception_index = EXCP_DEBUG;
 111     cpu_loop_exit(env);
 112 }
 113
 114 void helper_sleep(CPUSH4State *env, uint32_t next_pc)
 115 {
 116     env->halted = 1;
 117     env->in_sleep = 1;
 118     env->exception_index = EXCP_HLT;
 119     env->pc = next_pc;
 120     cpu_loop_exit(env);
 121 }
 122
 123 void helper_trapa(CPUSH4State *env, uint32_t tra)
 124 {
 125     env->tra = tra << 2;
 126     raise_exception(env, 0x160, GETPC());
 127 }
 128
 129 void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
 130 {
 131     if (cpu_sh4_is_cached (env, address))
 132     {
 133         memory_content *r = malloc (sizeof(memory_content));
 134         r->address = address;
 135         r->value = value;
 136         r->next = NULL;
 137
 138         *(env->movcal_backup_tail) = r;
 139         env->movcal_backup_tail = &(r->next);
 140     }
 141 }
 142
 143 void helper_discard_movcal_backup(CPUSH4State *env)
 144 {
 145     memory_content *current = env->movcal_backup;
 146
 147     while(current)
 148     {
 149         memory_content *next = current->next;
 150         free (current);
 151         env->movcal_backup = current = next;
 152         if (current == NULL)
 153             env->movcal_backup_tail = &(env->movcal_backup);
 154     }
 155 }
 156
 157 void helper_ocbi(CPUSH4State *env, uint32_t address)
 158 {
 159     memory_content **current = &(env->movcal_backup);
 160     while (*current)
 161     {
 162         uint32_t a = (*current)->address;
 163         if ((a & ~0x1F) == (address & ~0x1F))
 164         {
 165             memory_content *next = (*current)->next;
 166             cpu_stl_data(env, a, (*current)->value);
 167
 168             if (next == NULL)
 169             {
 170                 env->movcal_backup_tail = current;
 171             }
 172
 173             free (*current);
 174             *current = next;
 175             break;
 176         }
 177     }
 178 }
 179
 180 uint32_t helper_addc(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 181 {
 182     uint32_t tmp0, tmp1;
 183
 184     tmp1 = arg0 + arg1;
 185     tmp0 = arg1;
 186     arg1 = tmp1 + (env->sr & 1);
 187     if (tmp0 > tmp1)
 188         env->sr |= SR_T;
 189     else
 190         env->sr &= ~SR_T;
 191     if (tmp1 > arg1)
 192         env->sr |= SR_T;
 193     return arg1;
 194 }
 195
 196 uint32_t helper_addv(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 197 {
 198     uint32_t dest, src, ans;
 199
 200     if ((int32_t) arg1 >= 0)
 201         dest = 0;
 202     else
 203         dest = 1;
 204     if ((int32_t) arg0 >= 0)
 205         src = 0;
 206     else
 207         src = 1;
 208     src += dest;
 209     arg1 += arg0;
 210     if ((int32_t) arg1 >= 0)
 211         ans = 0;
 212     else
 213         ans = 1;
 214     ans += dest;
 215     if (src == 0 || src == 2) {
 216         if (ans == 1)
 217             env->sr |= SR_T;
 218         else
 219             env->sr &= ~SR_T;
 220     } else
 221         env->sr &= ~SR_T;
 222     return arg1;
 223 }
 224
 225 #define T (env->sr & SR_T)
 226 #define Q (env->sr & SR_Q ? 1 : 0)
 227 #define M (env->sr & SR_M ? 1 : 0)
 228 #define SETT env->sr |= SR_T
 229 #define CLRT env->sr &= ~SR_T
 230 #define SETQ env->sr |= SR_Q
 231 #define CLRQ env->sr &= ~SR_Q
 232 #define SETM env->sr |= SR_M
 233 #define CLRM env->sr &= ~SR_M
 234
 235 uint32_t helper_div1(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 236 {
 237     uint32_t tmp0, tmp2;
 238     uint8_t old_q, tmp1 = 0xff;
 239
 240     //printf("div1 arg0=0x%08x arg1=0x%08x M=%d Q=%d T=%d\n", arg0, arg1, M, Q, T);
 241     old_q = Q;
 242     if ((0x80000000 & arg1) != 0)
 243         SETQ;
 244     else
 245         CLRQ;
 246     tmp2 = arg0;
 247     arg1 <<= 1;
 248     arg1 |= T;
 249     switch (old_q) {
 250     case 0:
 251         switch (M) {
 252         case 0:
 253             tmp0 = arg1;
 254             arg1 -= tmp2;
 255             tmp1 = arg1 > tmp0;
 256             switch (Q) {
 257             case 0:
 258                 if (tmp1)
 259                     SETQ;
 260                 else
 261                     CLRQ;
 262                 break;
 263             case 1:
 264                 if (tmp1 == 0)
 265                     SETQ;
 266                 else
 267                     CLRQ;
 268                 break;
 269             }
 270             break;
 271         case 1:
 272             tmp0 = arg1;
 273             arg1 += tmp2;
 274             tmp1 = arg1 < tmp0;
 275             switch (Q) {
 276             case 0:
 277                 if (tmp1 == 0)
 278                     SETQ;
 279                 else
 280                     CLRQ;
 281                 break;
 282             case 1:
 283                 if (tmp1)
 284                     SETQ;
 285                 else
 286                     CLRQ;
 287                 break;
 288             }
 289             break;
 290         }
 291         break;
 292     case 1:
 293         switch (M) {
 294         case 0:
 295             tmp0 = arg1;
 296             arg1 += tmp2;
 297             tmp1 = arg1 < tmp0;
 298             switch (Q) {
 299             case 0:
 300                 if (tmp1)
 301                     SETQ;
 302                 else
 303                     CLRQ;
 304                 break;
 305             case 1:
 306                 if (tmp1 == 0)
 307                     SETQ;
 308                 else
 309                     CLRQ;
 310                 break;
 311             }
 312             break;
 313         case 1:
 314             tmp0 = arg1;
 315             arg1 -= tmp2;
 316             tmp1 = arg1 > tmp0;
 317             switch (Q) {
 318             case 0:
 319                 if (tmp1 == 0)
 320                     SETQ;
 321                 else
 322                     CLRQ;
 323                 break;
 324             case 1:
 325                 if (tmp1)
 326                     SETQ;
 327                 else
 328                     CLRQ;
 329                 break;
 330             }
 331             break;
 332         }
 333         break;
 334     }
 335     if (Q == M)
 336         SETT;
 337     else
 338         CLRT;
 339     //printf("Output: arg1=0x%08x M=%d Q=%d T=%d\n", arg1, M, Q, T);
 340     return arg1;
 341 }
 342
 343 void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 344 {
 345     int64_t res;
 346
 347     res = ((uint64_t) env->mach << 32) | env->macl;
 348     res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
 349     env->mach = (res >> 32) & 0xffffffff;
 350     env->macl = res & 0xffffffff;
 351     if (env->sr & SR_S) {
 352         if (res < 0)
 353             env->mach |= 0xffff0000;
 354         else
 355             env->mach &= 0x00007fff;
 356     }
 357 }
 358
 359 void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 360 {
 361     int64_t res;
 362
 363     res = ((uint64_t) env->mach << 32) | env->macl;
 364     res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
 365     env->mach = (res >> 32) & 0xffffffff;
 366     env->macl = res & 0xffffffff;
 367     if (env->sr & SR_S) {
 368         if (res < -0x80000000) {
 369             env->mach = 1;
 370             env->macl = 0x80000000;
 371         } else if (res > 0x000000007fffffff) {
 372             env->mach = 1;
 373             env->macl = 0x7fffffff;
 374         }
 375     }
 376 }
 377
 378 uint32_t helper_subc(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 379 {
 380     uint32_t tmp0, tmp1;
 381
 382     tmp1 = arg1 - arg0;
 383     tmp0 = arg1;
 384     arg1 = tmp1 - (env->sr & SR_T);
 385     if (tmp0 < tmp1)
 386         env->sr |= SR_T;
 387     else
 388         env->sr &= ~SR_T;
 389     if (tmp1 < arg1)
 390         env->sr |= SR_T;
 391     return arg1;
 392 }
 393
 394 uint32_t helper_subv(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 395 {
 396     int32_t dest, src, ans;
 397
 398     if ((int32_t) arg1 >= 0)
 399         dest = 0;
 400     else
 401         dest = 1;
 402     if ((int32_t) arg0 >= 0)
 403         src = 0;
 404     else
 405         src = 1;
 406     src += dest;
 407     arg1 -= arg0;
 408     if ((int32_t) arg1 >= 0)
 409         ans = 0;
 410     else
 411         ans = 1;
 412     ans += dest;
 413     if (src == 1) {
 414         if (ans == 1)
 415             env->sr |= SR_T;
 416         else
 417             env->sr &= ~SR_T;
 418     } else
 419         env->sr &= ~SR_T;
 420     return arg1;
 421 }
 422
 423 static inline void set_t(CPUSH4State *env)
 424 {
 425     env->sr |= SR_T;
 426 }
 427
 428 static inline void clr_t(CPUSH4State *env)
 429 {
 430     env->sr &= ~SR_T;
 431 }
 432
 433 void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
 434 {
 435     env->fpscr = val & FPSCR_MASK;
 436     if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
 437         set_float_rounding_mode(float_round_to_zero, &env->fp_status);
 438     } else {
 439         set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 440     }
 441     set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
 442 }
 443
 444 static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
 445 {
 446     int xcpt, cause, enable;
 447
 448     xcpt = get_float_exception_flags(&env->fp_status);
 449
 450     /* Clear the flag entries */
 451     env->fpscr &= ~FPSCR_FLAG_MASK;
 452
 453     if (unlikely(xcpt)) {
 454         if (xcpt & float_flag_invalid) {
 455             env->fpscr |= FPSCR_FLAG_V;
 456         }
 457         if (xcpt & float_flag_divbyzero) {
 458             env->fpscr |= FPSCR_FLAG_Z;
 459         }
 460         if (xcpt & float_flag_overflow) {
 461             env->fpscr |= FPSCR_FLAG_O;
 462         }
 463         if (xcpt & float_flag_underflow) {
 464             env->fpscr |= FPSCR_FLAG_U;
 465         }
 466         if (xcpt & float_flag_inexact) {
 467             env->fpscr |= FPSCR_FLAG_I;
 468         }
 469
 470         /* Accumulate in cause entries */
 471         env->fpscr |= (env->fpscr & FPSCR_FLAG_MASK)
 472                       << (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);
 473
 474         /* Generate an exception if enabled */
 475         cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
 476         enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
 477         if (cause & enable) {
 478             cpu_restore_state_from_retaddr(env, retaddr);
 479             env->exception_index = 0x120;
 480             cpu_loop_exit(env);
 481         }
 482     }
 483 }
 484
 485 float32 helper_fabs_FT(float32 t0)
 486 {
 487     return float32_abs(t0);
 488 }
 489
 490 float64 helper_fabs_DT(float64 t0)
 491 {
 492     return float64_abs(t0);
 493 }
 494
 495 float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
 496 {
 497     set_float_exception_flags(0, &env->fp_status);
 498     t0 = float32_add(t0, t1, &env->fp_status);
 499     update_fpscr(env, GETPC());
 500     return t0;
 501 }
 502
 503 float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
 504 {
 505     set_float_exception_flags(0, &env->fp_status);
 506     t0 = float64_add(t0, t1, &env->fp_status);
 507     update_fpscr(env, GETPC());
 508     return t0;
 509 }
 510
 511 void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
 512 {
 513     int relation;
 514
 515     set_float_exception_flags(0, &env->fp_status);
 516     relation = float32_compare(t0, t1, &env->fp_status);
 517     if (unlikely(relation == float_relation_unordered)) {
 518         update_fpscr(env, GETPC());
 519     } else if (relation == float_relation_equal) {
 520         set_t(env);
 521     } else {
 522         clr_t(env);
 523     }
 524 }
 525
 526 void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
 527 {
 528     int relation;
 529
 530     set_float_exception_flags(0, &env->fp_status);
 531     relation = float64_compare(t0, t1, &env->fp_status);
 532     if (unlikely(relation == float_relation_unordered)) {
 533         update_fpscr(env, GETPC());
 534     } else if (relation == float_relation_equal) {
 535         set_t(env);
 536     } else {
 537         clr_t(env);
 538     }
 539 }
 540
 541 void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
 542 {
 543     int relation;
 544
 545     set_float_exception_flags(0, &env->fp_status);
 546     relation = float32_compare(t0, t1, &env->fp_status);
 547     if (unlikely(relation == float_relation_unordered)) {
 548         update_fpscr(env, GETPC());
 549     } else if (relation == float_relation_greater) {
 550         set_t(env);
 551     } else {
 552         clr_t(env);
 553     }
 554 }
 555
 556 void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
 557 {
 558     int relation;
 559
 560     set_float_exception_flags(0, &env->fp_status);
 561     relation = float64_compare(t0, t1, &env->fp_status);
 562     if (unlikely(relation == float_relation_unordered)) {
 563         update_fpscr(env, GETPC());
 564     } else if (relation == float_relation_greater) {
 565         set_t(env);
 566     } else {
 567         clr_t(env);
 568     }
 569 }
 570
 571 float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
 572 {
 573     float64 ret;
 574     set_float_exception_flags(0, &env->fp_status);
 575     ret = float32_to_float64(t0, &env->fp_status);
 576     update_fpscr(env, GETPC());
 577     return ret;
 578 }
 579
 580 float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
 581 {
 582     float32 ret;
 583     set_float_exception_flags(0, &env->fp_status);
 584     ret = float64_to_float32(t0, &env->fp_status);
 585     update_fpscr(env, GETPC());
 586     return ret;
 587 }
 588
 589 float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1)
 590 {
 591     set_float_exception_flags(0, &env->fp_status);
 592     t0 = float32_div(t0, t1, &env->fp_status);
 593     update_fpscr(env, GETPC());
 594     return t0;
 595 }
 596
 597 float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1)
 598 {
 599     set_float_exception_flags(0, &env->fp_status);
 600     t0 = float64_div(t0, t1, &env->fp_status);
 601     update_fpscr(env, GETPC());
 602     return t0;
 603 }
 604
 605 float32 helper_float_FT(CPUSH4State *env, uint32_t t0)
 606 {
 607     float32 ret;
 608     set_float_exception_flags(0, &env->fp_status);
 609     ret = int32_to_float32(t0, &env->fp_status);
 610     update_fpscr(env, GETPC());
 611     return ret;
 612 }
 613
 614 float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
 615 {
 616     float64 ret;
 617     set_float_exception_flags(0, &env->fp_status);
 618     ret = int32_to_float64(t0, &env->fp_status);
 619     update_fpscr(env, GETPC());
 620     return ret;
 621 }
 622
 623 float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
 624 {
 625     set_float_exception_flags(0, &env->fp_status);
 626     t0 = float32_mul(t0, t1, &env->fp_status);
 627     t0 = float32_add(t0, t2, &env->fp_status);
 628     update_fpscr(env, GETPC());
 629     return t0;
 630 }
 631
 632 float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
 633 {
 634     set_float_exception_flags(0, &env->fp_status);
 635     t0 = float32_mul(t0, t1, &env->fp_status);
 636     update_fpscr(env, GETPC());
 637     return t0;
 638 }
 639
 640 float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
 641 {
 642     set_float_exception_flags(0, &env->fp_status);
 643     t0 = float64_mul(t0, t1, &env->fp_status);
 644     update_fpscr(env, GETPC());
 645     return t0;
 646 }
 647
 648 float32 helper_fneg_T(float32 t0)
 649 {
 650     return float32_chs(t0);
 651 }
 652
 653 float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
 654 {
 655     set_float_exception_flags(0, &env->fp_status);
 656     t0 = float32_sqrt(t0, &env->fp_status);
 657     update_fpscr(env, GETPC());
 658     return t0;
 659 }
 660
 661 float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0)
 662 {
 663     set_float_exception_flags(0, &env->fp_status);
 664     t0 = float64_sqrt(t0, &env->fp_status);
 665     update_fpscr(env, GETPC());
 666     return t0;
 667 }
 668
 669 float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1)
 670 {
 671     set_float_exception_flags(0, &env->fp_status);
 672     t0 = float32_sub(t0, t1, &env->fp_status);
 673     update_fpscr(env, GETPC());
 674     return t0;
 675 }
 676
 677 float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
 678 {
 679     set_float_exception_flags(0, &env->fp_status);
 680     t0 = float64_sub(t0, t1, &env->fp_status);
 681     update_fpscr(env, GETPC());
 682     return t0;
 683 }
 684
 685 uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0)
 686 {
 687     uint32_t ret;
 688     set_float_exception_flags(0, &env->fp_status);
 689     ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
 690     update_fpscr(env, GETPC());
 691     return ret;
 692 }
 693
 694 uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
 695 {
 696     uint32_t ret;
 697     set_float_exception_flags(0, &env->fp_status);
 698     ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
 699     update_fpscr(env, GETPC());
 700     return ret;
 701 }
 702
 703 void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
 704 {
 705     int bank, i;
 706     float32 r, p;
 707
 708     bank = (env->sr & FPSCR_FR) ? 16 : 0;
 709     r = float32_zero;
 710     set_float_exception_flags(0, &env->fp_status);
 711
 712     for (i = 0 ; i < 4 ; i++) {
 713         p = float32_mul(env->fregs[bank + m + i],
 714                         env->fregs[bank + n + i],
 715                         &env->fp_status);
 716         r = float32_add(r, p, &env->fp_status);
 717     }
 718     update_fpscr(env, GETPC());
 719
 720     env->fregs[bank + n + 3] = r;
 721 }
 722
 723 void helper_ftrv(CPUSH4State *env, uint32_t n)
 724 {
 725     int bank_matrix, bank_vector;
 726     int i, j;
 727     float32 r[4];
 728     float32 p;
 729
 730     bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
 731     bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
 732     set_float_exception_flags(0, &env->fp_status);
 733     for (i = 0 ; i < 4 ; i++) {
 734         r[i] = float32_zero;
 735         for (j = 0 ; j < 4 ; j++) {
 736             p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
 737                             env->fregs[bank_vector + j],
 738                             &env->fp_status);
 739             r[i] = float32_add(r[i], p, &env->fp_status);
 740         }
 741     }
 742     update_fpscr(env, GETPC());
 743
 744     for (i = 0 ; i < 4 ; i++) {
 745         env->fregs[bank_vector + i] = r[i];
 746     }
 747 }