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6 #if !defined(TARGET_SPARC64)
7 #define TARGET_LONG_BITS 32
8 #define TARGET_FPREGS 32
9 #define TARGET_PAGE_BITS 12 /* 4k */
11 #define TARGET_LONG_BITS 64
12 #define TARGET_FPREGS 64
13 #define TARGET_PAGE_BITS 12 /* XXX */
18 #include "softfloat.h"
20 #define TARGET_HAS_ICE 1
22 #if !defined(TARGET_SPARC64)
23 #define ELF_MACHINE EM_SPARC
25 #define ELF_MACHINE EM_SPARCV9
28 /*#define EXCP_INTERRUPT 0x100*/
30 /* trap definitions */
31 #ifndef TARGET_SPARC64
32 #define TT_TFAULT 0x01
33 #define TT_ILL_INSN 0x02
34 #define TT_PRIV_INSN 0x03
35 #define TT_NFPU_INSN 0x04
36 #define TT_WIN_OVF 0x05
37 #define TT_WIN_UNF 0x06
38 #define TT_UNALIGNED 0x07
39 #define TT_FP_EXCP 0x08
40 #define TT_DFAULT 0x09
42 #define TT_EXTINT 0x10
43 #define TT_DATA_ACCESS 0x29
44 #define TT_DIV_ZERO 0x2a
45 #define TT_NCP_INSN 0x24
48 #define TT_TFAULT 0x08
50 #define TT_ILL_INSN 0x10
51 #define TT_PRIV_INSN 0x11
52 #define TT_NFPU_INSN 0x20
53 #define TT_FP_EXCP 0x21
55 #define TT_CLRWIN 0x24
56 #define TT_DIV_ZERO 0x28
57 #define TT_DFAULT 0x30
59 #define TT_DATA_ACCESS 0x32
61 #define TT_UNALIGNED 0x34
62 #define TT_PRIV_ACT 0x37
63 #define TT_EXTINT 0x40
66 #define TT_WOTHER 0x10
70 #define PSR_NEG (1<<23)
71 #define PSR_ZERO (1<<22)
72 #define PSR_OVF (1<<21)
73 #define PSR_CARRY (1<<20)
74 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
75 #define PSR_EF (1<<12)
82 /* Trap base register */
83 #define TBR_BASE_MASK 0xfffff000
85 #if defined(TARGET_SPARC64)
91 #define PS_PRIV (1<<2)
95 #define FPRS_FEF (1<<2)
99 #define FSR_RD1 (1<<31)
100 #define FSR_RD0 (1<<30)
101 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
102 #define FSR_RD_NEAREST 0
103 #define FSR_RD_ZERO FSR_RD0
104 #define FSR_RD_POS FSR_RD1
105 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
107 #define FSR_NVM (1<<27)
108 #define FSR_OFM (1<<26)
109 #define FSR_UFM (1<<25)
110 #define FSR_DZM (1<<24)
111 #define FSR_NXM (1<<23)
112 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
114 #define FSR_NVA (1<<9)
115 #define FSR_OFA (1<<8)
116 #define FSR_UFA (1<<7)
117 #define FSR_DZA (1<<6)
118 #define FSR_NXA (1<<5)
119 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
121 #define FSR_NVC (1<<4)
122 #define FSR_OFC (1<<3)
123 #define FSR_UFC (1<<2)
124 #define FSR_DZC (1<<1)
125 #define FSR_NXC (1<<0)
126 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
128 #define FSR_FTT2 (1<<16)
129 #define FSR_FTT1 (1<<15)
130 #define FSR_FTT0 (1<<14)
131 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
132 #define FSR_FTT_IEEE_EXCP (1 << 14)
133 #define FSR_FTT_UNIMPFPOP (3 << 14)
134 #define FSR_FTT_SEQ_ERROR (4 << 14)
135 #define FSR_FTT_INVAL_FPR (6 << 14)
137 #define FSR_FCC1 (1<<11)
138 #define FSR_FCC0 (1<<10)
142 #define MMU_NF (1<<1)
144 #define PTE_ENTRYTYPE_MASK 3
145 #define PTE_ACCESS_MASK 0x1c
146 #define PTE_ACCESS_SHIFT 2
147 #define PTE_PPN_SHIFT 7
148 #define PTE_ADDR_MASK 0xffffff00
150 #define PG_ACCESSED_BIT 5
151 #define PG_MODIFIED_BIT 6
152 #define PG_CACHE_BIT 7
154 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
155 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
156 #define PG_CACHE_MASK (1 << PG_CACHE_BIT)
158 /* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
161 typedef struct sparc_def_t sparc_def_t
;
163 typedef struct CPUSPARCState
{
164 target_ulong gregs
[8]; /* general registers */
165 target_ulong
*regwptr
; /* pointer to current register window */
166 float32 fpr
[TARGET_FPREGS
]; /* floating point registers */
167 target_ulong pc
; /* program counter */
168 target_ulong npc
; /* next program counter */
169 target_ulong y
; /* multiply/divide register */
170 uint32_t psr
; /* processor state register */
171 target_ulong fsr
; /* FPU state register */
172 uint32_t cwp
; /* index of current register window (extracted
174 uint32_t wim
; /* window invalid mask */
175 target_ulong tbr
; /* trap base register */
176 int psrs
; /* supervisor mode (extracted from PSR) */
177 int psrps
; /* previous supervisor mode */
178 int psret
; /* enable traps */
179 uint32_t psrpil
; /* interrupt level */
180 int psref
; /* enable fpu */
181 target_ulong version
;
186 int interrupt_request
;
188 /* NOTE: we allow 8 more registers to handle wrapping */
189 target_ulong regbase
[NWINDOWS
* 16 + 8];
194 #if defined(TARGET_SPARC64)
198 uint64_t immuregs
[16];
199 uint64_t dmmuregs
[16];
200 uint64_t itlb_tag
[64];
201 uint64_t itlb_tte
[64];
202 uint64_t dtlb_tag
[64];
203 uint64_t dtlb_tte
[64];
205 uint32_t mmuregs
[16];
207 /* temporary float registers */
210 float_status fp_status
;
211 #if defined(TARGET_SPARC64)
215 uint64_t tnpc
[MAXTL
];
216 uint64_t tstate
[MAXTL
];
218 uint32_t xcc
; /* Extended integer condition codes */
222 uint32_t cansave
, canrestore
, otherwin
, wstate
, cleanwin
;
223 uint64_t agregs
[8]; /* alternate general registers */
224 uint64_t bgregs
[8]; /* backup for normal global registers */
225 uint64_t igregs
[8]; /* interrupt general registers */
226 uint64_t mgregs
[8]; /* mmu general registers */
228 uint64_t tick_cmpr
, stick_cmpr
;
231 uint32_t gl
; // UA2005
232 /* UA 2005 hyperprivileged registers */
233 uint64_t hpstate
, htstate
[MAXTL
], hintp
, htba
, hver
, hstick_cmpr
, ssr
;
234 void *hstick
; // UA 2005
236 #if !defined(TARGET_SPARC64) && !defined(reg_T2)
240 #if defined(TARGET_SPARC64)
241 #define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
242 #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
243 env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \
245 #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
246 #define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
247 env->fsr = _tmp & 0x3fcfc1c3ffULL; \
250 #define GET_FSR32(env) (env->fsr)
251 #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
252 env->fsr = (_tmp & 0xcfc1dfff) | (env->fsr & 0x000e0000); \
256 CPUSPARCState
*cpu_sparc_init(void);
257 int cpu_sparc_exec(CPUSPARCState
*s
);
258 int cpu_sparc_close(CPUSPARCState
*s
);
259 int sparc_find_by_name (const unsigned char *name
, const sparc_def_t
**def
);
260 void sparc_cpu_list (FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
,
262 int cpu_sparc_register (CPUSPARCState
*env
, const sparc_def_t
*def
);
264 #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \
265 (env->psref? PSR_EF : 0) | \
266 (env->psrpil << 8) | \
267 (env->psrs? PSR_S : 0) | \
268 (env->psrps? PSR_PS : 0) | \
269 (env->psret? PSR_ET : 0) | env->cwp)
271 #ifndef NO_CPU_IO_DEFS
272 void cpu_set_cwp(CPUSPARCState
*env1
, int new_cwp
);
275 #define PUT_PSR(env, val) do { int _tmp = val; \
276 env->psr = _tmp & PSR_ICC; \
277 env->psref = (_tmp & PSR_EF)? 1 : 0; \
278 env->psrpil = (_tmp & PSR_PIL) >> 8; \
279 env->psrs = (_tmp & PSR_S)? 1 : 0; \
280 env->psrps = (_tmp & PSR_PS)? 1 : 0; \
281 env->psret = (_tmp & PSR_ET)? 1 : 0; \
282 cpu_set_cwp(env, _tmp & PSR_CWP); \
285 #ifdef TARGET_SPARC64
286 #define GET_CCR(env) ((env->xcc << 4) | (env->psr & PSR_ICC))
287 #define PUT_CCR(env, val) do { int _tmp = val; \
288 env->xcc = _tmp >> 4; \
289 env->psr = (_tmp & 0xf) << 20; \
293 int cpu_sparc_signal_handler(int host_signum
, void *pinfo
, void *puc
);
294 void raise_exception(int tt
);
295 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
297 void do_tick_set_count(void *opaque
, uint64_t count
);
298 uint64_t do_tick_get_count(void *opaque
);
299 void do_tick_set_limit(void *opaque
, uint64_t limit
);