target-sparc/cpu.h

   1 #ifndef CPU_SPARC_H
   2 #define CPU_SPARC_H
   3
   4 #define TARGET_LONG_BITS 32
   5
   6 #include "cpu-defs.h"
   7
   8 /*#define EXCP_INTERRUPT 0x100*/
   9
  10 /* trap definitions */
  11 #define TT_ILL_INSN 0x02
  12 #define TT_PRIV_INSN 0x03
  13 #define TT_WIN_OVF  0x05
  14 #define TT_WIN_UNF  0x06
  15 #define TT_FP_EXCP  0x08
  16 #define TT_DIV_ZERO 0x2a
  17 #define TT_TRAP     0x80
  18
  19 #define PSR_NEG   (1<<23)
  20 #define PSR_ZERO  (1<<22)
  21 #define PSR_OVF   (1<<21)
  22 #define PSR_CARRY (1<<20)
  23 #define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
  24 #define PSR_S     (1<<7)
  25 #define PSR_PS    (1<<6)
  26 #define PSR_ET    (1<<5)
  27 #define PSR_CWP   0x1f
  28 /* Fake impl 0, version 4 */
  29 #define GET_PSR(env) ((0<<28) | (4<<24) | env->psr | (env->psrs? PSR_S : 0) | (env->psrs? PSR_PS : 0) |(env->psret? PSR_ET : 0) | env->cwp)
  30
  31 /* Trap base register */
  32 #define TBR_BASE_MASK 0xfffff000
  33
  34 /* Fcc */
  35 #define FSR_RD1        (1<<31)
  36 #define FSR_RD0        (1<<30)
  37 #define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
  38 #define FSR_RD_NEAREST 0
  39 #define FSR_RD_ZERO    FSR_RD0
  40 #define FSR_RD_POS     FSR_RD1
  41 #define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)
  42
  43 #define FSR_NVM   (1<<27)
  44 #define FSR_OFM   (1<<26)
  45 #define FSR_UFM   (1<<25)
  46 #define FSR_DZM   (1<<24)
  47 #define FSR_NXM   (1<<23)
  48 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
  49
  50 #define FSR_NVA   (1<<9)
  51 #define FSR_OFA   (1<<8)
  52 #define FSR_UFA   (1<<7)
  53 #define FSR_DZA   (1<<6)
  54 #define FSR_NXA   (1<<5)
  55 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  56
  57 #define FSR_NVC   (1<<4)
  58 #define FSR_OFC   (1<<3)
  59 #define FSR_UFC   (1<<2)
  60 #define FSR_DZC   (1<<1)
  61 #define FSR_NXC   (1<<0)
  62 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
  63
  64 #define FSR_FTT2   (1<<16)
  65 #define FSR_FTT1   (1<<15)
  66 #define FSR_FTT0   (1<<14)
  67 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
  68
  69 #define FSR_FCC1  (1<<11)
  70 #define FSR_FCC0  (1<<10)
  71
  72 /* MMU */
  73 #define MMU_E     (1<<0)
  74 #define MMU_NF    (1<<1)
  75
  76 #define PTE_ENTRYTYPE_MASK 3
  77 #define PTE_ACCESS_MASK    0x1c
  78 #define PTE_ACCESS_SHIFT   2
  79 #define PTE_ADDR_MASK      0xffffff00
  80
  81 #define PG_ACCESSED_BIT 5
  82 #define PG_MODIFIED_BIT 6
  83 #define PG_CACHE_BIT    7
  84
  85 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
  86 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
  87 #define PG_CACHE_MASK    (1 << PG_CACHE_BIT)
  88
  89 #define ACCESS_DATA     0
  90 #define ACCESS_CODE     1
  91 #define ACCESS_MMU      2
  92
  93 #define NWINDOWS  32
  94
  95 typedef struct CPUSPARCState {
  96     uint32_t gregs[8]; /* general registers */
  97     uint32_t *regwptr; /* pointer to current register window */
  98     float    fpr[32];  /* floating point registers */
  99     uint32_t pc;       /* program counter */
 100     uint32_t npc;      /* next program counter */
 101     uint32_t y;        /* multiply/divide register */
 102     uint32_t psr;      /* processor state register */
 103     uint32_t fsr;      /* FPU state register */
 104     uint32_t T2;
 105     uint32_t cwp;      /* index of current register window (extracted
 106                           from PSR) */
 107     uint32_t wim;      /* window invalid mask */
 108     uint32_t tbr;      /* trap base register */
 109     int      psrs;     /* supervisor mode (extracted from PSR) */
 110     int      psrps;    /* previous supervisor mode */
 111     int      psret;    /* enable traps */
 112     jmp_buf  jmp_env;
 113     int user_mode_only;
 114     int exception_index;
 115     int interrupt_index;
 116     int interrupt_request;
 117     uint32_t exception_next_pc;
 118     struct TranslationBlock *current_tb;
 119     void *opaque;
 120     /* NOTE: we allow 8 more registers to handle wrapping */
 121     uint32_t regbase[NWINDOWS * 16 + 8];
 122
 123     /* in order to avoid passing too many arguments to the memory
 124        write helpers, we store some rarely used information in the CPU
 125        context) */
 126     unsigned long mem_write_pc; /* host pc at which the memory was
 127                                    written */
 128     unsigned long mem_write_vaddr; /* target virtual addr at which the
 129                                       memory was written */
 130     /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
 131     CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
 132     CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
 133     int error_code;
 134     int access_type;
 135     /* MMU regs */
 136     uint32_t mmuregs[16];
 137     /* temporary float registers */
 138     float ft0, ft1, ft2;
 139     double dt0, dt1, dt2;
 140
 141     /* ice debug support */
 142     uint32_t breakpoints[MAX_BREAKPOINTS];
 143     int nb_breakpoints;
 144     int singlestep_enabled; /* XXX: should use CPU single step mode instead */
 145
 146 } CPUSPARCState;
 147
 148 CPUSPARCState *cpu_sparc_init(void);
 149 int cpu_sparc_exec(CPUSPARCState *s);
 150 int cpu_sparc_close(CPUSPARCState *s);
 151
 152 struct siginfo;
 153 int cpu_sparc_signal_handler(int hostsignum, struct siginfo *info, void *puc);
 154 void cpu_sparc_dump_state(CPUSPARCState *env, FILE *f, int flags);
 155
 156 #define TARGET_PAGE_BITS 12 /* 4k */
 157 #include "cpu-all.h"
 158
 159 #endif