target-sparc/cpu.h

   1 #ifndef CPU_SPARC_H
   2 #define CPU_SPARC_H
   3
   4 #include "config.h"
   5
   6 #if !defined(TARGET_SPARC64)
   7 #define TARGET_LONG_BITS 32
   8 #define TARGET_FPREGS 32
   9 #define TARGET_PAGE_BITS 12 /* 4k */
  10 #else
  11 #define TARGET_LONG_BITS 64
  12 #define TARGET_FPREGS 64
  13 #define TARGET_PAGE_BITS 13 /* 8k */
  14 #endif
  15
  16 #define TARGET_PHYS_ADDR_BITS 64
  17
  18 #include "cpu-defs.h"
  19
  20 #include "softfloat.h"
  21
  22 #define TARGET_HAS_ICE 1
  23
  24 #if !defined(TARGET_SPARC64)
  25 #define ELF_MACHINE     EM_SPARC
  26 #else
  27 #define ELF_MACHINE     EM_SPARCV9
  28 #endif
  29
  30 /*#define EXCP_INTERRUPT 0x100*/
  31
  32 /* trap definitions */
  33 #ifndef TARGET_SPARC64
  34 #define TT_TFAULT   0x01
  35 #define TT_ILL_INSN 0x02
  36 #define TT_PRIV_INSN 0x03
  37 #define TT_NFPU_INSN 0x04
  38 #define TT_WIN_OVF  0x05
  39 #define TT_WIN_UNF  0x06
  40 #define TT_UNALIGNED 0x07
  41 #define TT_FP_EXCP  0x08
  42 #define TT_DFAULT   0x09
  43 #define TT_TOVF     0x0a
  44 #define TT_EXTINT   0x10
  45 #define TT_CODE_ACCESS 0x21
  46 #define TT_DATA_ACCESS 0x29
  47 #define TT_DIV_ZERO 0x2a
  48 #define TT_NCP_INSN 0x24
  49 #define TT_TRAP     0x80
  50 #else
  51 #define TT_TFAULT   0x08
  52 #define TT_TMISS    0x09
  53 #define TT_CODE_ACCESS 0x0a
  54 #define TT_ILL_INSN 0x10
  55 #define TT_PRIV_INSN 0x11
  56 #define TT_NFPU_INSN 0x20
  57 #define TT_FP_EXCP  0x21
  58 #define TT_TOVF     0x23
  59 #define TT_CLRWIN   0x24
  60 #define TT_DIV_ZERO 0x28
  61 #define TT_DFAULT   0x30
  62 #define TT_DMISS    0x31
  63 #define TT_DATA_ACCESS 0x32
  64 #define TT_DPROT    0x33
  65 #define TT_UNALIGNED 0x34
  66 #define TT_PRIV_ACT 0x37
  67 #define TT_EXTINT   0x40
  68 #define TT_SPILL    0x80
  69 #define TT_FILL     0xc0
  70 #define TT_WOTHER   0x10
  71 #define TT_TRAP     0x100
  72 #endif
  73
  74 #define PSR_NEG   (1<<23)
  75 #define PSR_ZERO  (1<<22)
  76 #define PSR_OVF   (1<<21)
  77 #define PSR_CARRY (1<<20)
  78 #define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
  79 #define PSR_EF    (1<<12)
  80 #define PSR_PIL   0xf00
  81 #define PSR_S     (1<<7)
  82 #define PSR_PS    (1<<6)
  83 #define PSR_ET    (1<<5)
  84 #define PSR_CWP   0x1f
  85
  86 /* Trap base register */
  87 #define TBR_BASE_MASK 0xfffff000
  88
  89 #if defined(TARGET_SPARC64)
  90 #define PS_IG    (1<<11)
  91 #define PS_MG    (1<<10)
  92 #define PS_RMO   (1<<7)
  93 #define PS_RED   (1<<5)
  94 #define PS_PEF   (1<<4)
  95 #define PS_AM    (1<<3)
  96 #define PS_PRIV  (1<<2)
  97 #define PS_IE    (1<<1)
  98 #define PS_AG    (1<<0)
  99
 100 #define FPRS_FEF (1<<2)
 101 #endif
 102
 103 /* Fcc */
 104 #define FSR_RD1        (1<<31)
 105 #define FSR_RD0        (1<<30)
 106 #define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
 107 #define FSR_RD_NEAREST 0
 108 #define FSR_RD_ZERO    FSR_RD0
 109 #define FSR_RD_POS     FSR_RD1
 110 #define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)
 111
 112 #define FSR_NVM   (1<<27)
 113 #define FSR_OFM   (1<<26)
 114 #define FSR_UFM   (1<<25)
 115 #define FSR_DZM   (1<<24)
 116 #define FSR_NXM   (1<<23)
 117 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
 118
 119 #define FSR_NVA   (1<<9)
 120 #define FSR_OFA   (1<<8)
 121 #define FSR_UFA   (1<<7)
 122 #define FSR_DZA   (1<<6)
 123 #define FSR_NXA   (1<<5)
 124 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
 125
 126 #define FSR_NVC   (1<<4)
 127 #define FSR_OFC   (1<<3)
 128 #define FSR_UFC   (1<<2)
 129 #define FSR_DZC   (1<<1)
 130 #define FSR_NXC   (1<<0)
 131 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
 132
 133 #define FSR_FTT2   (1<<16)
 134 #define FSR_FTT1   (1<<15)
 135 #define FSR_FTT0   (1<<14)
 136 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
 137 #define FSR_FTT_IEEE_EXCP (1 << 14)
 138 #define FSR_FTT_UNIMPFPOP (3 << 14)
 139 #define FSR_FTT_SEQ_ERROR (4 << 14)
 140 #define FSR_FTT_INVAL_FPR (6 << 14)
 141
 142 #define FSR_FCC1  (1<<11)
 143 #define FSR_FCC0  (1<<10)
 144
 145 /* MMU */
 146 #define MMU_E     (1<<0)
 147 #define MMU_NF    (1<<1)
 148
 149 #define PTE_ENTRYTYPE_MASK 3
 150 #define PTE_ACCESS_MASK    0x1c
 151 #define PTE_ACCESS_SHIFT   2
 152 #define PTE_PPN_SHIFT      7
 153 #define PTE_ADDR_MASK      0xffffff00
 154
 155 #define PG_ACCESSED_BIT 5
 156 #define PG_MODIFIED_BIT 6
 157 #define PG_CACHE_BIT    7
 158
 159 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 160 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
 161 #define PG_CACHE_MASK    (1 << PG_CACHE_BIT)
 162
 163 /* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
 164 #define NWINDOWS  8
 165
 166 typedef struct sparc_def_t sparc_def_t;
 167
 168 typedef struct CPUSPARCState {
 169     target_ulong gregs[8]; /* general registers */
 170     target_ulong *regwptr; /* pointer to current register window */
 171     float32 fpr[TARGET_FPREGS];  /* floating point registers */
 172     target_ulong pc;       /* program counter */
 173     target_ulong npc;      /* next program counter */
 174     target_ulong y;        /* multiply/divide register */
 175     uint32_t psr;      /* processor state register */
 176     target_ulong fsr;      /* FPU state register */
 177     uint32_t cwp;      /* index of current register window (extracted
 178                           from PSR) */
 179     uint32_t wim;      /* window invalid mask */
 180     target_ulong tbr;  /* trap base register */
 181     int      psrs;     /* supervisor mode (extracted from PSR) */
 182     int      psrps;    /* previous supervisor mode */
 183     int      psret;    /* enable traps */
 184     uint32_t psrpil;   /* interrupt blocking level */
 185     uint32_t pil_in;   /* incoming interrupt level bitmap */
 186     int      psref;    /* enable fpu */
 187     target_ulong version;
 188     jmp_buf  jmp_env;
 189     int user_mode_only;
 190     int exception_index;
 191     int interrupt_index;
 192     int interrupt_request;
 193     int halted;
 194     /* NOTE: we allow 8 more registers to handle wrapping */
 195     target_ulong regbase[NWINDOWS * 16 + 8];
 196
 197     CPU_COMMON
 198
 199     /* MMU regs */
 200 #if defined(TARGET_SPARC64)
 201     uint64_t lsu;
 202 #define DMMU_E 0x8
 203 #define IMMU_E 0x4
 204     uint64_t immuregs[16];
 205     uint64_t dmmuregs[16];
 206     uint64_t itlb_tag[64];
 207     uint64_t itlb_tte[64];
 208     uint64_t dtlb_tag[64];
 209     uint64_t dtlb_tte[64];
 210 #else
 211     uint32_t mmuregs[16];
 212 #endif
 213     /* temporary float registers */
 214     float32 ft0, ft1;
 215     float64 dt0, dt1;
 216     float_status fp_status;
 217 #if defined(TARGET_SPARC64)
 218 #define MAXTL 4
 219     uint64_t t0, t1, t2;
 220     uint64_t tpc[MAXTL];
 221     uint64_t tnpc[MAXTL];
 222     uint64_t tstate[MAXTL];
 223     uint32_t tt[MAXTL];
 224     uint32_t xcc;               /* Extended integer condition codes */
 225     uint32_t asi;
 226     uint32_t pstate;
 227     uint32_t tl;
 228     uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
 229     uint64_t agregs[8]; /* alternate general registers */
 230     uint64_t bgregs[8]; /* backup for normal global registers */
 231     uint64_t igregs[8]; /* interrupt general registers */
 232     uint64_t mgregs[8]; /* mmu general registers */
 233     uint64_t fprs;
 234     uint64_t tick_cmpr, stick_cmpr;
 235     void *tick, *stick;
 236     uint64_t gsr;
 237     uint32_t gl; // UA2005
 238     /* UA 2005 hyperprivileged registers */
 239     uint64_t hpstate, htstate[MAXTL], hintp, htba, hver, hstick_cmpr, ssr;
 240     void *hstick; // UA 2005
 241 #endif
 242 #if !defined(TARGET_SPARC64) && !defined(reg_T2)
 243     target_ulong t2;
 244 #endif
 245 } CPUSPARCState;
 246 #if defined(TARGET_SPARC64)
 247 #define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
 248 #define PUT_FSR32(env, val) do { uint32_t _tmp = val;                   \
 249         env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL);  \
 250     } while (0)
 251 #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
 252 #define PUT_FSR64(env, val) do { uint64_t _tmp = val;   \
 253         env->fsr = _tmp & 0x3fcfc1c3ffULL;              \
 254     } while (0)
 255 #else
 256 #define GET_FSR32(env) (env->fsr)
 257 #define PUT_FSR32(env, val) do { uint32_t _tmp = val;                   \
 258         env->fsr = (_tmp & 0xcfc1dfff) | (env->fsr & 0x000e0000);       \
 259     } while (0)
 260 #endif
 261
 262 CPUSPARCState *cpu_sparc_init(void);
 263 int cpu_sparc_exec(CPUSPARCState *s);
 264 int cpu_sparc_close(CPUSPARCState *s);
 265 int sparc_find_by_name (const unsigned char *name, const sparc_def_t **def);
 266 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
 267                                                  ...));
 268 int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def);
 269
 270 #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) |             \
 271                       (env->psref? PSR_EF : 0) |                        \
 272                       (env->psrpil << 8) |                              \
 273                       (env->psrs? PSR_S : 0) |                          \
 274                       (env->psrps? PSR_PS : 0) |                        \
 275                       (env->psret? PSR_ET : 0) | env->cwp)
 276
 277 #ifndef NO_CPU_IO_DEFS
 278 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
 279 #endif
 280
 281 #define PUT_PSR(env, val) do { int _tmp = val;                          \
 282         env->psr = _tmp & PSR_ICC;                                      \
 283         env->psref = (_tmp & PSR_EF)? 1 : 0;                            \
 284         env->psrpil = (_tmp & PSR_PIL) >> 8;                            \
 285         env->psrs = (_tmp & PSR_S)? 1 : 0;                              \
 286         env->psrps = (_tmp & PSR_PS)? 1 : 0;                            \
 287         env->psret = (_tmp & PSR_ET)? 1 : 0;                            \
 288         cpu_set_cwp(env, _tmp & PSR_CWP);                               \
 289     } while (0)
 290
 291 #ifdef TARGET_SPARC64
 292 #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
 293 #define PUT_CCR(env, val) do { int _tmp = val;                          \
 294         env->xcc = (_tmp >> 4) << 20;                                           \
 295         env->psr = (_tmp & 0xf) << 20;                                  \
 296     } while (0)
 297 #define GET_CWP64(env) (NWINDOWS - 1 - (env)->cwp)
 298 #define PUT_CWP64(env, val) \
 299     cpu_set_cwp(env, NWINDOWS - 1 - ((val) & (NWINDOWS - 1)))
 300
 301 #endif
 302
 303 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
 304 void raise_exception(int tt);
 305 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
 306                           int is_asi);
 307 void do_tick_set_count(void *opaque, uint64_t count);
 308 uint64_t do_tick_get_count(void *opaque);
 309 void do_tick_set_limit(void *opaque, uint64_t limit);
 310 void cpu_check_irqs(CPUSPARCState *env);
 311
 312 #define CPUState CPUSPARCState
 313 #define cpu_init cpu_sparc_init
 314 #define cpu_exec cpu_sparc_exec
 315 #define cpu_gen_code cpu_sparc_gen_code
 316 #define cpu_signal_handler cpu_sparc_signal_handler
 317
 318 #include "cpu-all.h"
 319
 320 #endif