target-sparc/helper.c

   1 /*
   2  *  sparc helpers
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20 #include <stdarg.h>
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <string.h>
  24 #include <inttypes.h>
  25 #include <signal.h>
  26 #include <assert.h>
  27
  28 #include "cpu.h"
  29 #include "exec-all.h"
  30 #include "qemu-common.h"
  31
  32 //#define DEBUG_MMU
  33 //#define DEBUG_FEATURES
  34
  35 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
  36
  37 /* Sparc MMU emulation */
  38
  39 /* thread support */
  40
  41 static spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
  42
  43 void cpu_lock(void)
  44 {
  45     spin_lock(&global_cpu_lock);
  46 }
  47
  48 void cpu_unlock(void)
  49 {
  50     spin_unlock(&global_cpu_lock);
  51 }
  52
  53 #if defined(CONFIG_USER_ONLY)
  54
  55 int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw,
  56                                int mmu_idx, int is_softmmu)
  57 {
  58     if (rw & 2)
  59         env1->exception_index = TT_TFAULT;
  60     else
  61         env1->exception_index = TT_DFAULT;
  62     return 1;
  63 }
  64
  65 #else
  66
  67 #ifndef TARGET_SPARC64
  68 /*
  69  * Sparc V8 Reference MMU (SRMMU)
  70  */
  71 static const int access_table[8][8] = {
  72     { 0, 0, 0, 0, 8, 0, 12, 12 },
  73     { 0, 0, 0, 0, 8, 0, 0, 0 },
  74     { 8, 8, 0, 0, 0, 8, 12, 12 },
  75     { 8, 8, 0, 0, 0, 8, 0, 0 },
  76     { 8, 0, 8, 0, 8, 8, 12, 12 },
  77     { 8, 0, 8, 0, 8, 0, 8, 0 },
  78     { 8, 8, 8, 0, 8, 8, 12, 12 },
  79     { 8, 8, 8, 0, 8, 8, 8, 0 }
  80 };
  81
  82 static const int perm_table[2][8] = {
  83     {
  84         PAGE_READ,
  85         PAGE_READ | PAGE_WRITE,
  86         PAGE_READ | PAGE_EXEC,
  87         PAGE_READ | PAGE_WRITE | PAGE_EXEC,
  88         PAGE_EXEC,
  89         PAGE_READ | PAGE_WRITE,
  90         PAGE_READ | PAGE_EXEC,
  91         PAGE_READ | PAGE_WRITE | PAGE_EXEC
  92     },
  93     {
  94         PAGE_READ,
  95         PAGE_READ | PAGE_WRITE,
  96         PAGE_READ | PAGE_EXEC,
  97         PAGE_READ | PAGE_WRITE | PAGE_EXEC,
  98         PAGE_EXEC,
  99         PAGE_READ,
 100         0,
 101         0,
 102     }
 103 };
 104
 105 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
 106                                 int *prot, int *access_index,
 107                                 target_ulong address, int rw, int mmu_idx)
 108 {
 109     int access_perms = 0;
 110     target_phys_addr_t pde_ptr;
 111     uint32_t pde;
 112     target_ulong virt_addr;
 113     int error_code = 0, is_dirty, is_user;
 114     unsigned long page_offset;
 115
 116     is_user = mmu_idx == MMU_USER_IDX;
 117     virt_addr = address & TARGET_PAGE_MASK;
 118
 119     if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
 120         // Boot mode: instruction fetches are taken from PROM
 121         if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) {
 122             *physical = env->prom_addr | (address & 0x7ffffULL);
 123             *prot = PAGE_READ | PAGE_EXEC;
 124             return 0;
 125         }
 126         *physical = address;
 127         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 128         return 0;
 129     }
 130
 131     *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
 132     *physical = 0xffffffffffff0000ULL;
 133
 134     /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
 135     /* Context base + context number */
 136     pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
 137     pde = ldl_phys(pde_ptr);
 138
 139     /* Ctx pde */
 140     switch (pde & PTE_ENTRYTYPE_MASK) {
 141     default:
 142     case 0: /* Invalid */
 143         return 1 << 2;
 144     case 2: /* L0 PTE, maybe should not happen? */
 145     case 3: /* Reserved */
 146         return 4 << 2;
 147     case 1: /* L0 PDE */
 148         pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
 149         pde = ldl_phys(pde_ptr);
 150
 151         switch (pde & PTE_ENTRYTYPE_MASK) {
 152         default:
 153         case 0: /* Invalid */
 154             return (1 << 8) | (1 << 2);
 155         case 3: /* Reserved */
 156             return (1 << 8) | (4 << 2);
 157         case 1: /* L1 PDE */
 158             pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
 159             pde = ldl_phys(pde_ptr);
 160
 161             switch (pde & PTE_ENTRYTYPE_MASK) {
 162             default:
 163             case 0: /* Invalid */
 164                 return (2 << 8) | (1 << 2);
 165             case 3: /* Reserved */
 166                 return (2 << 8) | (4 << 2);
 167             case 1: /* L2 PDE */
 168                 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
 169                 pde = ldl_phys(pde_ptr);
 170
 171                 switch (pde & PTE_ENTRYTYPE_MASK) {
 172                 default:
 173                 case 0: /* Invalid */
 174                     return (3 << 8) | (1 << 2);
 175                 case 1: /* PDE, should not happen */
 176                 case 3: /* Reserved */
 177                     return (3 << 8) | (4 << 2);
 178                 case 2: /* L3 PTE */
 179                     virt_addr = address & TARGET_PAGE_MASK;
 180                     page_offset = (address & TARGET_PAGE_MASK) &
 181                         (TARGET_PAGE_SIZE - 1);
 182                 }
 183                 break;
 184             case 2: /* L2 PTE */
 185                 virt_addr = address & ~0x3ffff;
 186                 page_offset = address & 0x3ffff;
 187             }
 188             break;
 189         case 2: /* L1 PTE */
 190             virt_addr = address & ~0xffffff;
 191             page_offset = address & 0xffffff;
 192         }
 193     }
 194
 195     /* update page modified and dirty bits */
 196     is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
 197     if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
 198         pde |= PG_ACCESSED_MASK;
 199         if (is_dirty)
 200             pde |= PG_MODIFIED_MASK;
 201         stl_phys_notdirty(pde_ptr, pde);
 202     }
 203     /* check access */
 204     access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
 205     error_code = access_table[*access_index][access_perms];
 206     if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
 207         return error_code;
 208
 209     /* the page can be put in the TLB */
 210     *prot = perm_table[is_user][access_perms];
 211     if (!(pde & PG_MODIFIED_MASK)) {
 212         /* only set write access if already dirty... otherwise wait
 213            for dirty access */
 214         *prot &= ~PAGE_WRITE;
 215     }
 216
 217     /* Even if large ptes, we map only one 4KB page in the cache to
 218        avoid filling it too fast */
 219     *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
 220     return error_code;
 221 }
 222
 223 /* Perform address translation */
 224 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
 225                               int mmu_idx, int is_softmmu)
 226 {
 227     target_phys_addr_t paddr;
 228     target_ulong vaddr;
 229     int error_code = 0, prot, ret = 0, access_index;
 230
 231     error_code = get_physical_address(env, &paddr, &prot, &access_index,
 232                                       address, rw, mmu_idx);
 233     if (error_code == 0) {
 234         vaddr = address & TARGET_PAGE_MASK;
 235         paddr &= TARGET_PAGE_MASK;
 236 #ifdef DEBUG_MMU
 237         printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
 238                TARGET_FMT_lx "\n", address, paddr, vaddr);
 239 #endif
 240         ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
 241         return ret;
 242     }
 243
 244     if (env->mmuregs[3]) /* Fault status register */
 245         env->mmuregs[3] = 1; /* overflow (not read before another fault) */
 246     env->mmuregs[3] |= (access_index << 5) | error_code | 2;
 247     env->mmuregs[4] = address; /* Fault address register */
 248
 249     if ((env->mmuregs[0] & MMU_NF) || env->psret == 0)  {
 250         // No fault mode: if a mapping is available, just override
 251         // permissions. If no mapping is available, redirect accesses to
 252         // neverland. Fake/overridden mappings will be flushed when
 253         // switching to normal mode.
 254         vaddr = address & TARGET_PAGE_MASK;
 255         prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 256         ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
 257         return ret;
 258     } else {
 259         if (rw & 2)
 260             env->exception_index = TT_TFAULT;
 261         else
 262             env->exception_index = TT_DFAULT;
 263         return 1;
 264     }
 265 }
 266
 267 target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
 268 {
 269     target_phys_addr_t pde_ptr;
 270     uint32_t pde;
 271
 272     /* Context base + context number */
 273     pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
 274         (env->mmuregs[2] << 2);
 275     pde = ldl_phys(pde_ptr);
 276
 277     switch (pde & PTE_ENTRYTYPE_MASK) {
 278     default:
 279     case 0: /* Invalid */
 280     case 2: /* PTE, maybe should not happen? */
 281     case 3: /* Reserved */
 282         return 0;
 283     case 1: /* L1 PDE */
 284         if (mmulev == 3)
 285             return pde;
 286         pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
 287         pde = ldl_phys(pde_ptr);
 288
 289         switch (pde & PTE_ENTRYTYPE_MASK) {
 290         default:
 291         case 0: /* Invalid */
 292         case 3: /* Reserved */
 293             return 0;
 294         case 2: /* L1 PTE */
 295             return pde;
 296         case 1: /* L2 PDE */
 297             if (mmulev == 2)
 298                 return pde;
 299             pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
 300             pde = ldl_phys(pde_ptr);
 301
 302             switch (pde & PTE_ENTRYTYPE_MASK) {
 303             default:
 304             case 0: /* Invalid */
 305             case 3: /* Reserved */
 306                 return 0;
 307             case 2: /* L2 PTE */
 308                 return pde;
 309             case 1: /* L3 PDE */
 310                 if (mmulev == 1)
 311                     return pde;
 312                 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
 313                 pde = ldl_phys(pde_ptr);
 314
 315                 switch (pde & PTE_ENTRYTYPE_MASK) {
 316                 default:
 317                 case 0: /* Invalid */
 318                 case 1: /* PDE, should not happen */
 319                 case 3: /* Reserved */
 320                     return 0;
 321                 case 2: /* L3 PTE */
 322                     return pde;
 323                 }
 324             }
 325         }
 326     }
 327     return 0;
 328 }
 329
 330 #ifdef DEBUG_MMU
 331 void dump_mmu(CPUState *env)
 332 {
 333     target_ulong va, va1, va2;
 334     unsigned int n, m, o;
 335     target_phys_addr_t pde_ptr, pa;
 336     uint32_t pde;
 337
 338     printf("MMU dump:\n");
 339     pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
 340     pde = ldl_phys(pde_ptr);
 341     printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
 342            (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
 343     for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
 344         pde = mmu_probe(env, va, 2);
 345         if (pde) {
 346             pa = cpu_get_phys_page_debug(env, va);
 347             printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
 348                    " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
 349             for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
 350                 pde = mmu_probe(env, va1, 1);
 351                 if (pde) {
 352                     pa = cpu_get_phys_page_debug(env, va1);
 353                     printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
 354                            " PDE: " TARGET_FMT_lx "\n", va1, pa, pde);
 355                     for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
 356                         pde = mmu_probe(env, va2, 0);
 357                         if (pde) {
 358                             pa = cpu_get_phys_page_debug(env, va2);
 359                             printf("  VA: " TARGET_FMT_lx ", PA: "
 360                                    TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n",
 361                                    va2, pa, pde);
 362                         }
 363                     }
 364                 }
 365             }
 366         }
 367     }
 368     printf("MMU dump ends\n");
 369 }
 370 #endif /* DEBUG_MMU */
 371
 372 #else /* !TARGET_SPARC64 */
 373 /*
 374  * UltraSparc IIi I/DMMUs
 375  */
 376 static int get_physical_address_data(CPUState *env,
 377                                      target_phys_addr_t *physical, int *prot,
 378                                      target_ulong address, int rw, int is_user)
 379 {
 380     target_ulong mask;
 381     unsigned int i;
 382
 383     if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
 384         *physical = address;
 385         *prot = PAGE_READ | PAGE_WRITE;
 386         return 0;
 387     }
 388
 389     for (i = 0; i < 64; i++) {
 390         switch ((env->dtlb_tte[i] >> 61) & 3) {
 391         default:
 392         case 0x0: // 8k
 393             mask = 0xffffffffffffe000ULL;
 394             break;
 395         case 0x1: // 64k
 396             mask = 0xffffffffffff0000ULL;
 397             break;
 398         case 0x2: // 512k
 399             mask = 0xfffffffffff80000ULL;
 400             break;
 401         case 0x3: // 4M
 402             mask = 0xffffffffffc00000ULL;
 403             break;
 404         }
 405         // ctx match, vaddr match, valid?
 406         if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
 407             (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL) &&
 408             (env->dtlb_tte[i] & 0x8000000000000000ULL)) {
 409             // access ok?
 410             if (((env->dtlb_tte[i] & 0x4) && is_user) ||
 411                 (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
 412                 if (env->dmmuregs[3]) /* Fault status register */
 413                     env->dmmuregs[3] = 2; /* overflow (not read before
 414                                              another fault) */
 415                 env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
 416                 env->dmmuregs[4] = address; /* Fault address register */
 417                 env->exception_index = TT_DFAULT;
 418 #ifdef DEBUG_MMU
 419                 printf("DFAULT at 0x%" PRIx64 "\n", address);
 420 #endif
 421                 return 1;
 422             }
 423             *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) +
 424                 (address & ~mask & 0x1fffffff000ULL);
 425             *prot = PAGE_READ;
 426             if (env->dtlb_tte[i] & 0x2)
 427                 *prot |= PAGE_WRITE;
 428             return 0;
 429         }
 430     }
 431 #ifdef DEBUG_MMU
 432     printf("DMISS at 0x%" PRIx64 "\n", address);
 433 #endif
 434     env->dmmuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff);
 435     env->exception_index = TT_DMISS;
 436     return 1;
 437 }
 438
 439 static int get_physical_address_code(CPUState *env,
 440                                      target_phys_addr_t *physical, int *prot,
 441                                      target_ulong address, int is_user)
 442 {
 443     target_ulong mask;
 444     unsigned int i;
 445
 446     if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
 447         *physical = address;
 448         *prot = PAGE_EXEC;
 449         return 0;
 450     }
 451
 452     for (i = 0; i < 64; i++) {
 453         switch ((env->itlb_tte[i] >> 61) & 3) {
 454         default:
 455         case 0x0: // 8k
 456             mask = 0xffffffffffffe000ULL;
 457             break;
 458         case 0x1: // 64k
 459             mask = 0xffffffffffff0000ULL;
 460             break;
 461         case 0x2: // 512k
 462             mask = 0xfffffffffff80000ULL;
 463             break;
 464         case 0x3: // 4M
 465             mask = 0xffffffffffc00000ULL;
 466                 break;
 467         }
 468         // ctx match, vaddr match, valid?
 469         if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
 470             (address & mask) == (env->itlb_tag[i] & ~0x1fffULL) &&
 471             (env->itlb_tte[i] & 0x8000000000000000ULL)) {
 472             // access ok?
 473             if ((env->itlb_tte[i] & 0x4) && is_user) {
 474                 if (env->immuregs[3]) /* Fault status register */
 475                     env->immuregs[3] = 2; /* overflow (not read before
 476                                              another fault) */
 477                 env->immuregs[3] |= (is_user << 3) | 1;
 478                 env->exception_index = TT_TFAULT;
 479 #ifdef DEBUG_MMU
 480                 printf("TFAULT at 0x%" PRIx64 "\n", address);
 481 #endif
 482                 return 1;
 483             }
 484             *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) +
 485                 (address & ~mask & 0x1fffffff000ULL);
 486             *prot = PAGE_EXEC;
 487             return 0;
 488         }
 489     }
 490 #ifdef DEBUG_MMU
 491     printf("TMISS at 0x%" PRIx64 "\n", address);
 492 #endif
 493     env->immuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff);
 494     env->exception_index = TT_TMISS;
 495     return 1;
 496 }
 497
 498 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
 499                                 int *prot, int *access_index,
 500                                 target_ulong address, int rw, int mmu_idx)
 501 {
 502     int is_user = mmu_idx == MMU_USER_IDX;
 503
 504     if (rw == 2)
 505         return get_physical_address_code(env, physical, prot, address,
 506                                          is_user);
 507     else
 508         return get_physical_address_data(env, physical, prot, address, rw,
 509                                          is_user);
 510 }
 511
 512 /* Perform address translation */
 513 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
 514                               int mmu_idx, int is_softmmu)
 515 {
 516     target_ulong virt_addr, vaddr;
 517     target_phys_addr_t paddr;
 518     int error_code = 0, prot, ret = 0, access_index;
 519
 520     error_code = get_physical_address(env, &paddr, &prot, &access_index,
 521                                       address, rw, mmu_idx);
 522     if (error_code == 0) {
 523         virt_addr = address & TARGET_PAGE_MASK;
 524         vaddr = virt_addr + ((address & TARGET_PAGE_MASK) &
 525                              (TARGET_PAGE_SIZE - 1));
 526 #ifdef DEBUG_MMU
 527         printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64
 528                "\n", address, paddr, vaddr);
 529 #endif
 530         ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
 531         return ret;
 532     }
 533     // XXX
 534     return 1;
 535 }
 536
 537 #ifdef DEBUG_MMU
 538 void dump_mmu(CPUState *env)
 539 {
 540     unsigned int i;
 541     const char *mask;
 542
 543     printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n",
 544            env->dmmuregs[1], env->dmmuregs[2]);
 545     if ((env->lsu & DMMU_E) == 0) {
 546         printf("DMMU disabled\n");
 547     } else {
 548         printf("DMMU dump:\n");
 549         for (i = 0; i < 64; i++) {
 550             switch ((env->dtlb_tte[i] >> 61) & 3) {
 551             default:
 552             case 0x0:
 553                 mask = "  8k";
 554                 break;
 555             case 0x1:
 556                 mask = " 64k";
 557                 break;
 558             case 0x2:
 559                 mask = "512k";
 560                 break;
 561             case 0x3:
 562                 mask = "  4M";
 563                 break;
 564             }
 565             if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
 566                 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx
 567                        ", %s, %s, %s, %s, ctx %" PRId64 "\n",
 568                        env->dtlb_tag[i] & ~0x1fffULL,
 569                        env->dtlb_tte[i] & 0x1ffffffe000ULL,
 570                        mask,
 571                        env->dtlb_tte[i] & 0x4? "priv": "user",
 572                        env->dtlb_tte[i] & 0x2? "RW": "RO",
 573                        env->dtlb_tte[i] & 0x40? "locked": "unlocked",
 574                        env->dtlb_tag[i] & 0x1fffULL);
 575             }
 576         }
 577     }
 578     if ((env->lsu & IMMU_E) == 0) {
 579         printf("IMMU disabled\n");
 580     } else {
 581         printf("IMMU dump:\n");
 582         for (i = 0; i < 64; i++) {
 583             switch ((env->itlb_tte[i] >> 61) & 3) {
 584             default:
 585             case 0x0:
 586                 mask = "  8k";
 587                 break;
 588             case 0x1:
 589                 mask = " 64k";
 590                 break;
 591             case 0x2:
 592                 mask = "512k";
 593                 break;
 594             case 0x3:
 595                 mask = "  4M";
 596                 break;
 597             }
 598             if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
 599                 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx
 600                        ", %s, %s, %s, ctx %" PRId64 "\n",
 601                        env->itlb_tag[i] & ~0x1fffULL,
 602                        env->itlb_tte[i] & 0x1ffffffe000ULL,
 603                        mask,
 604                        env->itlb_tte[i] & 0x4? "priv": "user",
 605                        env->itlb_tte[i] & 0x40? "locked": "unlocked",
 606                        env->itlb_tag[i] & 0x1fffULL);
 607             }
 608         }
 609     }
 610 }
 611 #endif /* DEBUG_MMU */
 612
 613 #endif /* TARGET_SPARC64 */
 614 #endif /* !CONFIG_USER_ONLY */
 615
 616
 617 #if defined(CONFIG_USER_ONLY)
 618 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 619 {
 620     return addr;
 621 }
 622
 623 #else
 624 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 625 {
 626     target_phys_addr_t phys_addr;
 627     int prot, access_index;
 628
 629     if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
 630                              MMU_KERNEL_IDX) != 0)
 631         if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
 632                                  0, MMU_KERNEL_IDX) != 0)
 633             return -1;
 634     if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
 635         return -1;
 636     return phys_addr;
 637 }
 638 #endif
 639
 640 void cpu_reset(CPUSPARCState *env)
 641 {
 642     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
 643         qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
 644         log_cpu_state(env, 0);
 645     }
 646
 647     tlb_flush(env, 1);
 648     env->cwp = 0;
 649     env->wim = 1;
 650     env->regwptr = env->regbase + (env->cwp * 16);
 651 #if defined(CONFIG_USER_ONLY)
 652 #ifdef TARGET_SPARC64
 653     env->cleanwin = env->nwindows - 2;
 654     env->cansave = env->nwindows - 2;
 655     env->pstate = PS_RMO | PS_PEF | PS_IE;
 656     env->asi = 0x82; // Primary no-fault
 657 #endif
 658 #else
 659     env->psret = 0;
 660     env->psrs = 1;
 661     env->psrps = 1;
 662 #ifdef TARGET_SPARC64
 663     env->pstate = PS_PRIV;
 664     env->hpstate = HS_PRIV;
 665     env->tsptr = &env->ts[env->tl & MAXTL_MASK];
 666 #else
 667     env->mmuregs[0] &= ~(MMU_E | MMU_NF);
 668     env->mmuregs[0] |= env->def->mmu_bm;
 669 #endif
 670     env->pc = 0;
 671     env->npc = env->pc + 4;
 672 #endif
 673 }
 674
 675 static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
 676 {
 677     sparc_def_t def1, *def = &def1;
 678
 679     if (cpu_sparc_find_by_name(def, cpu_model) < 0)
 680         return -1;
 681
 682     env->def = qemu_mallocz(sizeof(*def));
 683     memcpy(env->def, def, sizeof(*def));
 684 #if defined(CONFIG_USER_ONLY)
 685     if ((env->def->features & CPU_FEATURE_FLOAT))
 686         env->def->features |= CPU_FEATURE_FLOAT128;
 687 #endif
 688     env->cpu_model_str = cpu_model;
 689     env->version = def->iu_version;
 690     env->fsr = def->fpu_version;
 691     env->nwindows = def->nwindows;
 692 #if !defined(TARGET_SPARC64)
 693     env->mmuregs[0] |= def->mmu_version;
 694     cpu_sparc_set_id(env, 0);
 695     env->mxccregs[7] |= def->mxcc_version;
 696 #else
 697     env->mmu_version = def->mmu_version;
 698     env->maxtl = def->maxtl;
 699     env->version |= def->maxtl << 8;
 700     env->version |= def->nwindows - 1;
 701 #endif
 702     return 0;
 703 }
 704
 705 static void cpu_sparc_close(CPUSPARCState *env)
 706 {
 707     free(env->def);
 708     free(env);
 709 }
 710
 711 CPUSPARCState *cpu_sparc_init(const char *cpu_model)
 712 {
 713     CPUSPARCState *env;
 714
 715     env = qemu_mallocz(sizeof(CPUSPARCState));
 716     cpu_exec_init(env);
 717
 718     gen_intermediate_code_init(env);
 719
 720     if (cpu_sparc_register(env, cpu_model) < 0) {
 721         cpu_sparc_close(env);
 722         return NULL;
 723     }
 724     cpu_reset(env);
 725
 726     return env;
 727 }
 728
 729 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
 730 {
 731 #if !defined(TARGET_SPARC64)
 732     env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
 733 #endif
 734 }
 735
 736 static const sparc_def_t sparc_defs[] = {
 737 #ifdef TARGET_SPARC64
 738     {
 739         .name = "Fujitsu Sparc64",
 740         .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
 741         .fpu_version = 0x00000000,
 742         .mmu_version = mmu_us_12,
 743         .nwindows = 4,
 744         .maxtl = 4,
 745         .features = CPU_DEFAULT_FEATURES,
 746     },
 747     {
 748         .name = "Fujitsu Sparc64 III",
 749         .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
 750         .fpu_version = 0x00000000,
 751         .mmu_version = mmu_us_12,
 752         .nwindows = 5,
 753         .maxtl = 4,
 754         .features = CPU_DEFAULT_FEATURES,
 755     },
 756     {
 757         .name = "Fujitsu Sparc64 IV",
 758         .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
 759         .fpu_version = 0x00000000,
 760         .mmu_version = mmu_us_12,
 761         .nwindows = 8,
 762         .maxtl = 5,
 763         .features = CPU_DEFAULT_FEATURES,
 764     },
 765     {
 766         .name = "Fujitsu Sparc64 V",
 767         .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
 768         .fpu_version = 0x00000000,
 769         .mmu_version = mmu_us_12,
 770         .nwindows = 8,
 771         .maxtl = 5,
 772         .features = CPU_DEFAULT_FEATURES,
 773     },
 774     {
 775         .name = "TI UltraSparc I",
 776         .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
 777         .fpu_version = 0x00000000,
 778         .mmu_version = mmu_us_12,
 779         .nwindows = 8,
 780         .maxtl = 5,
 781         .features = CPU_DEFAULT_FEATURES,
 782     },
 783     {
 784         .name = "TI UltraSparc II",
 785         .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
 786         .fpu_version = 0x00000000,
 787         .mmu_version = mmu_us_12,
 788         .nwindows = 8,
 789         .maxtl = 5,
 790         .features = CPU_DEFAULT_FEATURES,
 791     },
 792     {
 793         .name = "TI UltraSparc IIi",
 794         .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
 795         .fpu_version = 0x00000000,
 796         .mmu_version = mmu_us_12,
 797         .nwindows = 8,
 798         .maxtl = 5,
 799         .features = CPU_DEFAULT_FEATURES,
 800     },
 801     {
 802         .name = "TI UltraSparc IIe",
 803         .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
 804         .fpu_version = 0x00000000,
 805         .mmu_version = mmu_us_12,
 806         .nwindows = 8,
 807         .maxtl = 5,
 808         .features = CPU_DEFAULT_FEATURES,
 809     },
 810     {
 811         .name = "Sun UltraSparc III",
 812         .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
 813         .fpu_version = 0x00000000,
 814         .mmu_version = mmu_us_12,
 815         .nwindows = 8,
 816         .maxtl = 5,
 817         .features = CPU_DEFAULT_FEATURES,
 818     },
 819     {
 820         .name = "Sun UltraSparc III Cu",
 821         .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
 822         .fpu_version = 0x00000000,
 823         .mmu_version = mmu_us_3,
 824         .nwindows = 8,
 825         .maxtl = 5,
 826         .features = CPU_DEFAULT_FEATURES,
 827     },
 828     {
 829         .name = "Sun UltraSparc IIIi",
 830         .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
 831         .fpu_version = 0x00000000,
 832         .mmu_version = mmu_us_12,
 833         .nwindows = 8,
 834         .maxtl = 5,
 835         .features = CPU_DEFAULT_FEATURES,
 836     },
 837     {
 838         .name = "Sun UltraSparc IV",
 839         .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
 840         .fpu_version = 0x00000000,
 841         .mmu_version = mmu_us_4,
 842         .nwindows = 8,
 843         .maxtl = 5,
 844         .features = CPU_DEFAULT_FEATURES,
 845     },
 846     {
 847         .name = "Sun UltraSparc IV+",
 848         .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
 849         .fpu_version = 0x00000000,
 850         .mmu_version = mmu_us_12,
 851         .nwindows = 8,
 852         .maxtl = 5,
 853         .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
 854     },
 855     {
 856         .name = "Sun UltraSparc IIIi+",
 857         .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
 858         .fpu_version = 0x00000000,
 859         .mmu_version = mmu_us_3,
 860         .nwindows = 8,
 861         .maxtl = 5,
 862         .features = CPU_DEFAULT_FEATURES,
 863     },
 864     {
 865         .name = "Sun UltraSparc T1",
 866         // defined in sparc_ifu_fdp.v and ctu.h
 867         .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
 868         .fpu_version = 0x00000000,
 869         .mmu_version = mmu_sun4v,
 870         .nwindows = 8,
 871         .maxtl = 6,
 872         .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
 873         | CPU_FEATURE_GL,
 874     },
 875     {
 876         .name = "Sun UltraSparc T2",
 877         // defined in tlu_asi_ctl.v and n2_revid_cust.v
 878         .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
 879         .fpu_version = 0x00000000,
 880         .mmu_version = mmu_sun4v,
 881         .nwindows = 8,
 882         .maxtl = 6,
 883         .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
 884         | CPU_FEATURE_GL,
 885     },
 886     {
 887         .name = "NEC UltraSparc I",
 888         .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
 889         .fpu_version = 0x00000000,
 890         .mmu_version = mmu_us_12,
 891         .nwindows = 8,
 892         .maxtl = 5,
 893         .features = CPU_DEFAULT_FEATURES,
 894     },
 895 #else
 896     {
 897         .name = "Fujitsu MB86900",
 898         .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
 899         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
 900         .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
 901         .mmu_bm = 0x00004000,
 902         .mmu_ctpr_mask = 0x007ffff0,
 903         .mmu_cxr_mask = 0x0000003f,
 904         .mmu_sfsr_mask = 0xffffffff,
 905         .mmu_trcr_mask = 0xffffffff,
 906         .nwindows = 7,
 907         .features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD,
 908     },
 909     {
 910         .name = "Fujitsu MB86904",
 911         .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
 912         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
 913         .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
 914         .mmu_bm = 0x00004000,
 915         .mmu_ctpr_mask = 0x00ffffc0,
 916         .mmu_cxr_mask = 0x000000ff,
 917         .mmu_sfsr_mask = 0x00016fff,
 918         .mmu_trcr_mask = 0x00ffffff,
 919         .nwindows = 8,
 920         .features = CPU_DEFAULT_FEATURES,
 921     },
 922     {
 923         .name = "Fujitsu MB86907",
 924         .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
 925         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
 926         .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
 927         .mmu_bm = 0x00004000,
 928         .mmu_ctpr_mask = 0xffffffc0,
 929         .mmu_cxr_mask = 0x000000ff,
 930         .mmu_sfsr_mask = 0x00016fff,
 931         .mmu_trcr_mask = 0xffffffff,
 932         .nwindows = 8,
 933         .features = CPU_DEFAULT_FEATURES,
 934     },
 935     {
 936         .name = "LSI L64811",
 937         .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
 938         .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
 939         .mmu_version = 0x10 << 24,
 940         .mmu_bm = 0x00004000,
 941         .mmu_ctpr_mask = 0x007ffff0,
 942         .mmu_cxr_mask = 0x0000003f,
 943         .mmu_sfsr_mask = 0xffffffff,
 944         .mmu_trcr_mask = 0xffffffff,
 945         .nwindows = 8,
 946         .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
 947         CPU_FEATURE_FSMULD,
 948     },
 949     {
 950         .name = "Cypress CY7C601",
 951         .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
 952         .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
 953         .mmu_version = 0x10 << 24,
 954         .mmu_bm = 0x00004000,
 955         .mmu_ctpr_mask = 0x007ffff0,
 956         .mmu_cxr_mask = 0x0000003f,
 957         .mmu_sfsr_mask = 0xffffffff,
 958         .mmu_trcr_mask = 0xffffffff,
 959         .nwindows = 8,
 960         .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
 961         CPU_FEATURE_FSMULD,
 962     },
 963     {
 964         .name = "Cypress CY7C611",
 965         .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
 966         .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
 967         .mmu_version = 0x10 << 24,
 968         .mmu_bm = 0x00004000,
 969         .mmu_ctpr_mask = 0x007ffff0,
 970         .mmu_cxr_mask = 0x0000003f,
 971         .mmu_sfsr_mask = 0xffffffff,
 972         .mmu_trcr_mask = 0xffffffff,
 973         .nwindows = 8,
 974         .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
 975         CPU_FEATURE_FSMULD,
 976     },
 977     {
 978         .name = "TI MicroSparc I",
 979         .iu_version = 0x41000000,
 980         .fpu_version = 4 << 17,
 981         .mmu_version = 0x41000000,
 982         .mmu_bm = 0x00004000,
 983         .mmu_ctpr_mask = 0x007ffff0,
 984         .mmu_cxr_mask = 0x0000003f,
 985         .mmu_sfsr_mask = 0x00016fff,
 986         .mmu_trcr_mask = 0x0000003f,
 987         .nwindows = 7,
 988         .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
 989         CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
 990         CPU_FEATURE_FMUL,
 991     },
 992     {
 993         .name = "TI MicroSparc II",
 994         .iu_version = 0x42000000,
 995         .fpu_version = 4 << 17,
 996         .mmu_version = 0x02000000,
 997         .mmu_bm = 0x00004000,
 998         .mmu_ctpr_mask = 0x00ffffc0,
 999         .mmu_cxr_mask = 0x000000ff,
1000         .mmu_sfsr_mask = 0x00016fff,
1001         .mmu_trcr_mask = 0x00ffffff,
1002         .nwindows = 8,
1003         .features = CPU_DEFAULT_FEATURES,
1004     },
1005     {
1006         .name = "TI MicroSparc IIep",
1007         .iu_version = 0x42000000,
1008         .fpu_version = 4 << 17,
1009         .mmu_version = 0x04000000,
1010         .mmu_bm = 0x00004000,
1011         .mmu_ctpr_mask = 0x00ffffc0,
1012         .mmu_cxr_mask = 0x000000ff,
1013         .mmu_sfsr_mask = 0x00016bff,
1014         .mmu_trcr_mask = 0x00ffffff,
1015         .nwindows = 8,
1016         .features = CPU_DEFAULT_FEATURES,
1017     },
1018     {
1019         .name = "TI SuperSparc 40", // STP1020NPGA
1020         .iu_version = 0x41000000, // SuperSPARC 2.x
1021         .fpu_version = 0 << 17,
1022         .mmu_version = 0x00000800, // SuperSPARC 2.x, no MXCC
1023         .mmu_bm = 0x00002000,
1024         .mmu_ctpr_mask = 0xffffffc0,
1025         .mmu_cxr_mask = 0x0000ffff,
1026         .mmu_sfsr_mask = 0xffffffff,
1027         .mmu_trcr_mask = 0xffffffff,
1028         .nwindows = 8,
1029         .features = CPU_DEFAULT_FEATURES,
1030     },
1031     {
1032         .name = "TI SuperSparc 50", // STP1020PGA
1033         .iu_version = 0x40000000, // SuperSPARC 3.x
1034         .fpu_version = 0 << 17,
1035         .mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC
1036         .mmu_bm = 0x00002000,
1037         .mmu_ctpr_mask = 0xffffffc0,
1038         .mmu_cxr_mask = 0x0000ffff,
1039         .mmu_sfsr_mask = 0xffffffff,
1040         .mmu_trcr_mask = 0xffffffff,
1041         .nwindows = 8,
1042         .features = CPU_DEFAULT_FEATURES,
1043     },
1044     {
1045         .name = "TI SuperSparc 51",
1046         .iu_version = 0x40000000, // SuperSPARC 3.x
1047         .fpu_version = 0 << 17,
1048         .mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC
1049         .mmu_bm = 0x00002000,
1050         .mmu_ctpr_mask = 0xffffffc0,
1051         .mmu_cxr_mask = 0x0000ffff,
1052         .mmu_sfsr_mask = 0xffffffff,
1053         .mmu_trcr_mask = 0xffffffff,
1054         .mxcc_version = 0x00000104,
1055         .nwindows = 8,
1056         .features = CPU_DEFAULT_FEATURES,
1057     },
1058     {
1059         .name = "TI SuperSparc 60", // STP1020APGA
1060         .iu_version = 0x40000000, // SuperSPARC 3.x
1061         .fpu_version = 0 << 17,
1062         .mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC
1063         .mmu_bm = 0x00002000,
1064         .mmu_ctpr_mask = 0xffffffc0,
1065         .mmu_cxr_mask = 0x0000ffff,
1066         .mmu_sfsr_mask = 0xffffffff,
1067         .mmu_trcr_mask = 0xffffffff,
1068         .nwindows = 8,
1069         .features = CPU_DEFAULT_FEATURES,
1070     },
1071     {
1072         .name = "TI SuperSparc 61",
1073         .iu_version = 0x44000000, // SuperSPARC 3.x
1074         .fpu_version = 0 << 17,
1075         .mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC
1076         .mmu_bm = 0x00002000,
1077         .mmu_ctpr_mask = 0xffffffc0,
1078         .mmu_cxr_mask = 0x0000ffff,
1079         .mmu_sfsr_mask = 0xffffffff,
1080         .mmu_trcr_mask = 0xffffffff,
1081         .mxcc_version = 0x00000104,
1082         .nwindows = 8,
1083         .features = CPU_DEFAULT_FEATURES,
1084     },
1085     {
1086         .name = "TI SuperSparc II",
1087         .iu_version = 0x40000000, // SuperSPARC II 1.x
1088         .fpu_version = 0 << 17,
1089         .mmu_version = 0x08000000, // SuperSPARC II 1.x, MXCC
1090         .mmu_bm = 0x00002000,
1091         .mmu_ctpr_mask = 0xffffffc0,
1092         .mmu_cxr_mask = 0x0000ffff,
1093         .mmu_sfsr_mask = 0xffffffff,
1094         .mmu_trcr_mask = 0xffffffff,
1095         .mxcc_version = 0x00000104,
1096         .nwindows = 8,
1097         .features = CPU_DEFAULT_FEATURES,
1098     },
1099     {
1100         .name = "Ross RT625",
1101         .iu_version = 0x1e000000,
1102         .fpu_version = 1 << 17,
1103         .mmu_version = 0x1e000000,
1104         .mmu_bm = 0x00004000,
1105         .mmu_ctpr_mask = 0x007ffff0,
1106         .mmu_cxr_mask = 0x0000003f,
1107         .mmu_sfsr_mask = 0xffffffff,
1108         .mmu_trcr_mask = 0xffffffff,
1109         .nwindows = 8,
1110         .features = CPU_DEFAULT_FEATURES,
1111     },
1112     {
1113         .name = "Ross RT620",
1114         .iu_version = 0x1f000000,
1115         .fpu_version = 1 << 17,
1116         .mmu_version = 0x1f000000,
1117         .mmu_bm = 0x00004000,
1118         .mmu_ctpr_mask = 0x007ffff0,
1119         .mmu_cxr_mask = 0x0000003f,
1120         .mmu_sfsr_mask = 0xffffffff,
1121         .mmu_trcr_mask = 0xffffffff,
1122         .nwindows = 8,
1123         .features = CPU_DEFAULT_FEATURES,
1124     },
1125     {
1126         .name = "BIT B5010",
1127         .iu_version = 0x20000000,
1128         .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
1129         .mmu_version = 0x20000000,
1130         .mmu_bm = 0x00004000,
1131         .mmu_ctpr_mask = 0x007ffff0,
1132         .mmu_cxr_mask = 0x0000003f,
1133         .mmu_sfsr_mask = 0xffffffff,
1134         .mmu_trcr_mask = 0xffffffff,
1135         .nwindows = 8,
1136         .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1137         CPU_FEATURE_FSMULD,
1138     },
1139     {
1140         .name = "Matsushita MN10501",
1141         .iu_version = 0x50000000,
1142         .fpu_version = 0 << 17,
1143         .mmu_version = 0x50000000,
1144         .mmu_bm = 0x00004000,
1145         .mmu_ctpr_mask = 0x007ffff0,
1146         .mmu_cxr_mask = 0x0000003f,
1147         .mmu_sfsr_mask = 0xffffffff,
1148         .mmu_trcr_mask = 0xffffffff,
1149         .nwindows = 8,
1150         .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT |
1151         CPU_FEATURE_FSMULD,
1152     },
1153     {
1154         .name = "Weitek W8601",
1155         .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
1156         .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
1157         .mmu_version = 0x10 << 24,
1158         .mmu_bm = 0x00004000,
1159         .mmu_ctpr_mask = 0x007ffff0,
1160         .mmu_cxr_mask = 0x0000003f,
1161         .mmu_sfsr_mask = 0xffffffff,
1162         .mmu_trcr_mask = 0xffffffff,
1163         .nwindows = 8,
1164         .features = CPU_DEFAULT_FEATURES,
1165     },
1166     {
1167         .name = "LEON2",
1168         .iu_version = 0xf2000000,
1169         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1170         .mmu_version = 0xf2000000,
1171         .mmu_bm = 0x00004000,
1172         .mmu_ctpr_mask = 0x007ffff0,
1173         .mmu_cxr_mask = 0x0000003f,
1174         .mmu_sfsr_mask = 0xffffffff,
1175         .mmu_trcr_mask = 0xffffffff,
1176         .nwindows = 8,
1177         .features = CPU_DEFAULT_FEATURES,
1178     },
1179     {
1180         .name = "LEON3",
1181         .iu_version = 0xf3000000,
1182         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1183         .mmu_version = 0xf3000000,
1184         .mmu_bm = 0x00004000,
1185         .mmu_ctpr_mask = 0x007ffff0,
1186         .mmu_cxr_mask = 0x0000003f,
1187         .mmu_sfsr_mask = 0xffffffff,
1188         .mmu_trcr_mask = 0xffffffff,
1189         .nwindows = 8,
1190         .features = CPU_DEFAULT_FEATURES,
1191     },
1192 #endif
1193 };
1194
1195 static const char * const feature_name[] = {
1196     "float",
1197     "float128",
1198     "swap",
1199     "mul",
1200     "div",
1201     "flush",
1202     "fsqrt",
1203     "fmul",
1204     "vis1",
1205     "vis2",
1206     "fsmuld",
1207     "hypv",
1208     "cmt",
1209     "gl",
1210 };
1211
1212 static void print_features(FILE *f,
1213                            int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1214                            uint32_t features, const char *prefix)
1215 {
1216     unsigned int i;
1217
1218     for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1219         if (feature_name[i] && (features & (1 << i))) {
1220             if (prefix)
1221                 (*cpu_fprintf)(f, "%s", prefix);
1222             (*cpu_fprintf)(f, "%s ", feature_name[i]);
1223         }
1224 }
1225
1226 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
1227 {
1228     unsigned int i;
1229
1230     for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1231         if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
1232             *features |= 1 << i;
1233             return;
1234         }
1235     fprintf(stderr, "CPU feature %s not found\n", flagname);
1236 }
1237
1238 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model)
1239 {
1240     unsigned int i;
1241     const sparc_def_t *def = NULL;
1242     char *s = strdup(cpu_model);
1243     char *featurestr, *name = strtok(s, ",");
1244     uint32_t plus_features = 0;
1245     uint32_t minus_features = 0;
1246     long long iu_version;
1247     uint32_t fpu_version, mmu_version, nwindows;
1248
1249     for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
1250         if (strcasecmp(name, sparc_defs[i].name) == 0) {
1251             def = &sparc_defs[i];
1252         }
1253     }
1254     if (!def)
1255         goto error;
1256     memcpy(cpu_def, def, sizeof(*def));
1257
1258     featurestr = strtok(NULL, ",");
1259     while (featurestr) {
1260         char *val;
1261
1262         if (featurestr[0] == '+') {
1263             add_flagname_to_bitmaps(featurestr + 1, &plus_features);
1264         } else if (featurestr[0] == '-') {
1265             add_flagname_to_bitmaps(featurestr + 1, &minus_features);
1266         } else if ((val = strchr(featurestr, '='))) {
1267             *val = 0; val++;
1268             if (!strcmp(featurestr, "iu_version")) {
1269                 char *err;
1270
1271                 iu_version = strtoll(val, &err, 0);
1272                 if (!*val || *err) {
1273                     fprintf(stderr, "bad numerical value %s\n", val);
1274                     goto error;
1275                 }
1276                 cpu_def->iu_version = iu_version;
1277 #ifdef DEBUG_FEATURES
1278                 fprintf(stderr, "iu_version %llx\n", iu_version);
1279 #endif
1280             } else if (!strcmp(featurestr, "fpu_version")) {
1281                 char *err;
1282
1283                 fpu_version = strtol(val, &err, 0);
1284                 if (!*val || *err) {
1285                     fprintf(stderr, "bad numerical value %s\n", val);
1286                     goto error;
1287                 }
1288                 cpu_def->fpu_version = fpu_version;
1289 #ifdef DEBUG_FEATURES
1290                 fprintf(stderr, "fpu_version %llx\n", fpu_version);
1291 #endif
1292             } else if (!strcmp(featurestr, "mmu_version")) {
1293                 char *err;
1294
1295                 mmu_version = strtol(val, &err, 0);
1296                 if (!*val || *err) {
1297                     fprintf(stderr, "bad numerical value %s\n", val);
1298                     goto error;
1299                 }
1300                 cpu_def->mmu_version = mmu_version;
1301 #ifdef DEBUG_FEATURES
1302                 fprintf(stderr, "mmu_version %llx\n", mmu_version);
1303 #endif
1304             } else if (!strcmp(featurestr, "nwindows")) {
1305                 char *err;
1306
1307                 nwindows = strtol(val, &err, 0);
1308                 if (!*val || *err || nwindows > MAX_NWINDOWS ||
1309                     nwindows < MIN_NWINDOWS) {
1310                     fprintf(stderr, "bad numerical value %s\n", val);
1311                     goto error;
1312                 }
1313                 cpu_def->nwindows = nwindows;
1314 #ifdef DEBUG_FEATURES
1315                 fprintf(stderr, "nwindows %d\n", nwindows);
1316 #endif
1317             } else {
1318                 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1319                 goto error;
1320             }
1321         } else {
1322             fprintf(stderr, "feature string `%s' not in format "
1323                     "(+feature|-feature|feature=xyz)\n", featurestr);
1324             goto error;
1325         }
1326         featurestr = strtok(NULL, ",");
1327     }
1328     cpu_def->features |= plus_features;
1329     cpu_def->features &= ~minus_features;
1330 #ifdef DEBUG_FEATURES
1331     print_features(stderr, fprintf, cpu_def->features, NULL);
1332 #endif
1333     free(s);
1334     return 0;
1335
1336  error:
1337     free(s);
1338     return -1;
1339 }
1340
1341 void sparc_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
1342 {
1343     unsigned int i;
1344
1345     for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
1346         (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x NWINS %d ",
1347                        sparc_defs[i].name,
1348                        sparc_defs[i].iu_version,
1349                        sparc_defs[i].fpu_version,
1350                        sparc_defs[i].mmu_version,
1351                        sparc_defs[i].nwindows);
1352         print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES &
1353                        ~sparc_defs[i].features, "-");
1354         print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES &
1355                        sparc_defs[i].features, "+");
1356         (*cpu_fprintf)(f, "\n");
1357     }
1358     (*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
1359     print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
1360     (*cpu_fprintf)(f, "\n");
1361     (*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
1362     print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
1363     (*cpu_fprintf)(f, "\n");
1364     (*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
1365                    "fpu_version mmu_version nwindows\n");
1366 }
1367
1368 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
1369
1370 void cpu_dump_state(CPUState *env, FILE *f,
1371                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1372                     int flags)
1373 {
1374     int i, x;
1375
1376     cpu_fprintf(f, "pc: " TARGET_FMT_lx "  npc: " TARGET_FMT_lx "\n", env->pc,
1377                 env->npc);
1378     cpu_fprintf(f, "General Registers:\n");
1379     for (i = 0; i < 4; i++)
1380         cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1381     cpu_fprintf(f, "\n");
1382     for (; i < 8; i++)
1383         cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1384     cpu_fprintf(f, "\nCurrent Register Window:\n");
1385     for (x = 0; x < 3; x++) {
1386         for (i = 0; i < 4; i++)
1387             cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1388                     (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
1389                     env->regwptr[i + x * 8]);
1390         cpu_fprintf(f, "\n");
1391         for (; i < 8; i++)
1392             cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1393                     (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
1394                     env->regwptr[i + x * 8]);
1395         cpu_fprintf(f, "\n");
1396     }
1397     cpu_fprintf(f, "\nFloating Point Registers:\n");
1398     for (i = 0; i < 32; i++) {
1399         if ((i & 3) == 0)
1400             cpu_fprintf(f, "%%f%02d:", i);
1401         cpu_fprintf(f, " %016f", *(float *)&env->fpr[i]);
1402         if ((i & 3) == 3)
1403             cpu_fprintf(f, "\n");
1404     }
1405 #ifdef TARGET_SPARC64
1406     cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
1407                 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
1408     cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d "
1409                 "cleanwin %d cwp %d\n",
1410                 env->cansave, env->canrestore, env->otherwin, env->wstate,
1411                 env->cleanwin, env->nwindows - 1 - env->cwp);
1412 #else
1413     cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n",
1414                 GET_PSR(env), GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
1415                 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
1416                 env->psrs?'S':'-', env->psrps?'P':'-',
1417                 env->psret?'E':'-', env->wim);
1418 #endif
1419     cpu_fprintf(f, "fsr: 0x%08x\n", env->fsr);
1420 }