4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 /* Sparc MMU emulation */
25 int cpu_sparc_handle_mmu_fault (CPUState
*env
, uint32_t address
, int rw
,
26 int is_user
, int is_softmmu
);
30 spinlock_t global_cpu_lock
= SPIN_LOCK_UNLOCKED
;
34 spin_lock(&global_cpu_lock
);
39 spin_unlock(&global_cpu_lock
);
42 #if !defined(CONFIG_USER_ONLY)
44 #define MMUSUFFIX _mmu
45 #define GETPC() (__builtin_return_address(0))
48 #include "softmmu_template.h"
51 #include "softmmu_template.h"
54 #include "softmmu_template.h"
57 #include "softmmu_template.h"
60 /* try to fill the TLB and return an exception if error. If retaddr is
61 NULL, it means that the function was called in C code (i.e. not
62 from generated code or from helper.c) */
63 /* XXX: fix it to restore all registers */
64 void tlb_fill(unsigned long addr
, int is_write
, int is_user
, void *retaddr
)
71 /* XXX: hack to restore env in all cases, even if not called from
76 ret
= cpu_sparc_handle_mmu_fault(env
, addr
, is_write
, is_user
, 1);
79 /* now we have a real cpu fault */
80 pc
= (unsigned long)retaddr
;
83 /* the PC is inside the translated code. It means that we have
84 a virtual CPU fault */
85 cpu_restore_state(tb
, env
, pc
, NULL
);
88 raise_exception_err(ret
, env
->error_code
);
94 static const int access_table
[8][8] = {
95 { 0, 0, 0, 0, 2, 0, 3, 3 },
96 { 0, 0, 0, 0, 2, 0, 0, 0 },
97 { 2, 2, 0, 0, 0, 2, 3, 3 },
98 { 2, 2, 0, 0, 0, 2, 0, 0 },
99 { 2, 0, 2, 0, 2, 2, 3, 3 },
100 { 2, 0, 2, 0, 2, 0, 2, 0 },
101 { 2, 2, 2, 0, 2, 2, 3, 3 },
102 { 2, 2, 2, 0, 2, 2, 2, 0 }
106 static const int rw_table
[2][8] = {
107 { 0, 1, 0, 1, 0, 1, 0, 1 },
108 { 0, 1, 0, 1, 0, 0, 0, 0 }
112 /* Perform address translation */
113 int cpu_sparc_handle_mmu_fault (CPUState
*env
, uint32_t address
, int rw
,
114 int is_user
, int is_softmmu
)
117 int access_perms
= 0, access_index
= 0;
119 uint32_t pde
, virt_addr
;
120 int error_code
= 0, is_dirty
, prot
, ret
= 0;
121 unsigned long paddr
, vaddr
, page_offset
;
123 if (env
->user_mode_only
) {
124 /* user mode only emulation */
129 virt_addr
= address
& TARGET_PAGE_MASK
;
130 if ((env
->mmuregs
[0] & MMU_E
) == 0) { /* MMU disabled */
132 page_offset
= address
& (TARGET_PAGE_SIZE
- 1);
133 prot
= PAGE_READ
| PAGE_WRITE
;
137 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
138 /* Context base + context number */
139 pde_ptr
= phys_ram_base
+ (env
->mmuregs
[1] << 4) + (env
->mmuregs
[2] << 4);
140 pde
= ldl_raw(pde_ptr
);
143 switch (pde
& PTE_ENTRYTYPE_MASK
) {
144 case 0: /* Invalid */
147 case 2: /* PTE, maybe should not happen? */
148 case 3: /* Reserved */
152 pde_ptr
= phys_ram_base
+ ((address
>> 22) & ~3) + ((pde
& ~3) << 4);
153 pde
= ldl_raw(pde_ptr
);
155 switch (pde
& PTE_ENTRYTYPE_MASK
) {
156 case 0: /* Invalid */
159 case 3: /* Reserved */
163 pde_ptr
= phys_ram_base
+ ((address
& 0xfc0000) >> 16) + ((pde
& ~3) << 4);
164 pde
= ldl_raw(pde_ptr
);
166 switch (pde
& PTE_ENTRYTYPE_MASK
) {
167 case 0: /* Invalid */
170 case 3: /* Reserved */
174 pde_ptr
= phys_ram_base
+ ((address
& 0x3f000) >> 10) + ((pde
& ~3) << 4);
175 pde
= ldl_raw(pde_ptr
);
177 switch (pde
& PTE_ENTRYTYPE_MASK
) {
178 case 0: /* Invalid */
181 case 1: /* PDE, should not happen */
182 case 3: /* Reserved */
186 virt_addr
= address
& TARGET_PAGE_MASK
;
187 page_offset
= (address
& TARGET_PAGE_MASK
) & (TARGET_PAGE_SIZE
- 1);
191 virt_addr
= address
& ~0x3ffff;
192 page_offset
= address
& 0x3ffff;
196 virt_addr
= address
& ~0xffffff;
197 page_offset
= address
& 0xffffff;
201 /* update page modified and dirty bits */
202 is_dirty
= (rw
& 1) && !(pde
& PG_MODIFIED_MASK
);
203 if (!(pde
& PG_ACCESSED_MASK
) || is_dirty
) {
204 pde
|= PG_ACCESSED_MASK
;
206 pde
|= PG_MODIFIED_MASK
;
207 stl_raw(pde_ptr
, pde
);
211 access_index
= ((rw
& 1) << 2) | (rw
& 2) | (is_user
? 0 : 1);
212 access_perms
= (pde
& PTE_ACCESS_MASK
) >> PTE_ACCESS_SHIFT
;
213 error_code
= access_table
[access_index
][access_perms
];
217 /* the page can be put in the TLB */
219 if (pde
& PG_MODIFIED_MASK
) {
220 /* only set write access if already dirty... otherwise wait
222 if (rw_table
[is_user
][access_perms
])
226 /* Even if large ptes, we map only one 4KB page in the cache to
227 avoid filling it too fast */
228 virt_addr
= address
& TARGET_PAGE_MASK
;
229 paddr
= ((pde
& PTE_ADDR_MASK
) << 4) + page_offset
;
232 vaddr
= virt_addr
+ ((address
& TARGET_PAGE_MASK
) & (TARGET_PAGE_SIZE
- 1));
234 ret
= tlb_set_page(env
, vaddr
, paddr
, prot
, is_user
, is_softmmu
);
238 if (env
->mmuregs
[3]) /* Fault status register */
239 env
->mmuregs
[3] = 1; /* overflow (not read before another fault) */
240 env
->mmuregs
[3] |= (access_index
<< 5) | (error_code
<< 2) | 2;
241 env
->mmuregs
[4] = address
; /* Fault address register */
243 if (env
->mmuregs
[0] & MMU_NF
|| env
->psret
== 0) // No fault
246 env
->exception_index
= exception
;
247 env
->error_code
= error_code
;
251 void memcpy32(uint32_t *dst
, const uint32_t *src
)
263 void set_cwp(int new_cwp
)
265 /* put the modified wrap registers at their proper location */
266 if (env
->cwp
== (NWINDOWS
- 1))
267 memcpy32(env
->regbase
, env
->regbase
+ NWINDOWS
* 16);
269 /* put the wrap registers at their temporary location */
270 if (new_cwp
== (NWINDOWS
- 1))
271 memcpy32(env
->regbase
+ NWINDOWS
* 16, env
->regbase
);
272 env
->regwptr
= env
->regbase
+ (new_cwp
* 16);
276 * Begin execution of an interruption. is_int is TRUE if coming from
277 * the int instruction. next_eip is the EIP value AFTER the interrupt
278 * instruction. It is only relevant if is_int is TRUE.
280 void do_interrupt(int intno
, int is_int
, int error_code
,
281 unsigned int next_eip
, int is_hw
)
286 if (loglevel
& CPU_LOG_INT
) {
288 fprintf(logfile
, "%6d: v=%02x e=%04x i=%d pc=%08x npc=%08x SP=%08x\n",
289 count
, intno
, error_code
, is_int
,
291 env
->npc
, env
->regwptr
[6]);
293 cpu_sparc_dump_state(env
, logfile
, 0);
297 fprintf(logfile
, " code=");
299 for(i
= 0; i
< 16; i
++) {
300 fprintf(logfile
, " %02x", ldub(ptr
+ i
));
302 fprintf(logfile
, "\n");
309 cwp
= (env
->cwp
- 1) & (NWINDOWS
- 1);
311 env
->regwptr
[9] = env
->pc
;
312 env
->regwptr
[10] = env
->npc
;
313 env
->psrps
= env
->psrs
;
315 env
->tbr
= (env
->tbr
& TBR_BASE_MASK
) | (intno
<< 4);
317 env
->npc
= env
->pc
+ 4;
318 env
->exception_index
= 0;
321 void raise_exception_err(int exception_index
, int error_code
)
323 raise_exception(exception_index
);