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[qemu.git] / target-sparc / helper.c
1 /*
2 * sparc helpers
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <signal.h>
26 #include <assert.h>
27
28 #include "cpu.h"
29 #include "exec-all.h"
30 #include "qemu-common.h"
31
32 //#define DEBUG_MMU
33 //#define DEBUG_FEATURES
34
35 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
36
37 /* Sparc MMU emulation */
38
39 /* thread support */
40
41 static spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
42
43 void cpu_lock(void)
44 {
45 spin_lock(&global_cpu_lock);
46 }
47
48 void cpu_unlock(void)
49 {
50 spin_unlock(&global_cpu_lock);
51 }
52
53 #if defined(CONFIG_USER_ONLY)
54
55 int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw,
56 int mmu_idx, int is_softmmu)
57 {
58 if (rw & 2)
59 env1->exception_index = TT_TFAULT;
60 else
61 env1->exception_index = TT_DFAULT;
62 return 1;
63 }
64
65 #else
66
67 #ifndef TARGET_SPARC64
68 /*
69 * Sparc V8 Reference MMU (SRMMU)
70 */
71 static const int access_table[8][8] = {
72 { 0, 0, 0, 0, 8, 0, 12, 12 },
73 { 0, 0, 0, 0, 8, 0, 0, 0 },
74 { 8, 8, 0, 0, 0, 8, 12, 12 },
75 { 8, 8, 0, 0, 0, 8, 0, 0 },
76 { 8, 0, 8, 0, 8, 8, 12, 12 },
77 { 8, 0, 8, 0, 8, 0, 8, 0 },
78 { 8, 8, 8, 0, 8, 8, 12, 12 },
79 { 8, 8, 8, 0, 8, 8, 8, 0 }
80 };
81
82 static const int perm_table[2][8] = {
83 {
84 PAGE_READ,
85 PAGE_READ | PAGE_WRITE,
86 PAGE_READ | PAGE_EXEC,
87 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
88 PAGE_EXEC,
89 PAGE_READ | PAGE_WRITE,
90 PAGE_READ | PAGE_EXEC,
91 PAGE_READ | PAGE_WRITE | PAGE_EXEC
92 },
93 {
94 PAGE_READ,
95 PAGE_READ | PAGE_WRITE,
96 PAGE_READ | PAGE_EXEC,
97 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
98 PAGE_EXEC,
99 PAGE_READ,
100 0,
101 0,
102 }
103 };
104
105 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
106 int *prot, int *access_index,
107 target_ulong address, int rw, int mmu_idx)
108 {
109 int access_perms = 0;
110 target_phys_addr_t pde_ptr;
111 uint32_t pde;
112 target_ulong virt_addr;
113 int error_code = 0, is_dirty, is_user;
114 unsigned long page_offset;
115
116 is_user = mmu_idx == MMU_USER_IDX;
117 virt_addr = address & TARGET_PAGE_MASK;
118
119 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
120 // Boot mode: instruction fetches are taken from PROM
121 if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) {
122 *physical = env->prom_addr | (address & 0x7ffffULL);
123 *prot = PAGE_READ | PAGE_EXEC;
124 return 0;
125 }
126 *physical = address;
127 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
128 return 0;
129 }
130
131 *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
132 *physical = 0xffffffffffff0000ULL;
133
134 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
135 /* Context base + context number */
136 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
137 pde = ldl_phys(pde_ptr);
138
139 /* Ctx pde */
140 switch (pde & PTE_ENTRYTYPE_MASK) {
141 default:
142 case 0: /* Invalid */
143 return 1 << 2;
144 case 2: /* L0 PTE, maybe should not happen? */
145 case 3: /* Reserved */
146 return 4 << 2;
147 case 1: /* L0 PDE */
148 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
149 pde = ldl_phys(pde_ptr);
150
151 switch (pde & PTE_ENTRYTYPE_MASK) {
152 default:
153 case 0: /* Invalid */
154 return (1 << 8) | (1 << 2);
155 case 3: /* Reserved */
156 return (1 << 8) | (4 << 2);
157 case 1: /* L1 PDE */
158 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
159 pde = ldl_phys(pde_ptr);
160
161 switch (pde & PTE_ENTRYTYPE_MASK) {
162 default:
163 case 0: /* Invalid */
164 return (2 << 8) | (1 << 2);
165 case 3: /* Reserved */
166 return (2 << 8) | (4 << 2);
167 case 1: /* L2 PDE */
168 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
169 pde = ldl_phys(pde_ptr);
170
171 switch (pde & PTE_ENTRYTYPE_MASK) {
172 default:
173 case 0: /* Invalid */
174 return (3 << 8) | (1 << 2);
175 case 1: /* PDE, should not happen */
176 case 3: /* Reserved */
177 return (3 << 8) | (4 << 2);
178 case 2: /* L3 PTE */
179 virt_addr = address & TARGET_PAGE_MASK;
180 page_offset = (address & TARGET_PAGE_MASK) &
181 (TARGET_PAGE_SIZE - 1);
182 }
183 break;
184 case 2: /* L2 PTE */
185 virt_addr = address & ~0x3ffff;
186 page_offset = address & 0x3ffff;
187 }
188 break;
189 case 2: /* L1 PTE */
190 virt_addr = address & ~0xffffff;
191 page_offset = address & 0xffffff;
192 }
193 }
194
195 /* update page modified and dirty bits */
196 is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
197 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
198 pde |= PG_ACCESSED_MASK;
199 if (is_dirty)
200 pde |= PG_MODIFIED_MASK;
201 stl_phys_notdirty(pde_ptr, pde);
202 }
203 /* check access */
204 access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
205 error_code = access_table[*access_index][access_perms];
206 if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
207 return error_code;
208
209 /* the page can be put in the TLB */
210 *prot = perm_table[is_user][access_perms];
211 if (!(pde & PG_MODIFIED_MASK)) {
212 /* only set write access if already dirty... otherwise wait
213 for dirty access */
214 *prot &= ~PAGE_WRITE;
215 }
216
217 /* Even if large ptes, we map only one 4KB page in the cache to
218 avoid filling it too fast */
219 *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
220 return error_code;
221 }
222
223 /* Perform address translation */
224 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
225 int mmu_idx, int is_softmmu)
226 {
227 target_phys_addr_t paddr;
228 target_ulong vaddr;
229 int error_code = 0, prot, ret = 0, access_index;
230
231 error_code = get_physical_address(env, &paddr, &prot, &access_index,
232 address, rw, mmu_idx);
233 if (error_code == 0) {
234 vaddr = address & TARGET_PAGE_MASK;
235 paddr &= TARGET_PAGE_MASK;
236 #ifdef DEBUG_MMU
237 printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
238 TARGET_FMT_lx "\n", address, paddr, vaddr);
239 #endif
240 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
241 return ret;
242 }
243
244 if (env->mmuregs[3]) /* Fault status register */
245 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
246 env->mmuregs[3] |= (access_index << 5) | error_code | 2;
247 env->mmuregs[4] = address; /* Fault address register */
248
249 if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
250 // No fault mode: if a mapping is available, just override
251 // permissions. If no mapping is available, redirect accesses to
252 // neverland. Fake/overridden mappings will be flushed when
253 // switching to normal mode.
254 vaddr = address & TARGET_PAGE_MASK;
255 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
256 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
257 return ret;
258 } else {
259 if (rw & 2)
260 env->exception_index = TT_TFAULT;
261 else
262 env->exception_index = TT_DFAULT;
263 return 1;
264 }
265 }
266
267 target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
268 {
269 target_phys_addr_t pde_ptr;
270 uint32_t pde;
271
272 /* Context base + context number */
273 pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
274 (env->mmuregs[2] << 2);
275 pde = ldl_phys(pde_ptr);
276
277 switch (pde & PTE_ENTRYTYPE_MASK) {
278 default:
279 case 0: /* Invalid */
280 case 2: /* PTE, maybe should not happen? */
281 case 3: /* Reserved */
282 return 0;
283 case 1: /* L1 PDE */
284 if (mmulev == 3)
285 return pde;
286 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
287 pde = ldl_phys(pde_ptr);
288
289 switch (pde & PTE_ENTRYTYPE_MASK) {
290 default:
291 case 0: /* Invalid */
292 case 3: /* Reserved */
293 return 0;
294 case 2: /* L1 PTE */
295 return pde;
296 case 1: /* L2 PDE */
297 if (mmulev == 2)
298 return pde;
299 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
300 pde = ldl_phys(pde_ptr);
301
302 switch (pde & PTE_ENTRYTYPE_MASK) {
303 default:
304 case 0: /* Invalid */
305 case 3: /* Reserved */
306 return 0;
307 case 2: /* L2 PTE */
308 return pde;
309 case 1: /* L3 PDE */
310 if (mmulev == 1)
311 return pde;
312 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
313 pde = ldl_phys(pde_ptr);
314
315 switch (pde & PTE_ENTRYTYPE_MASK) {
316 default:
317 case 0: /* Invalid */
318 case 1: /* PDE, should not happen */
319 case 3: /* Reserved */
320 return 0;
321 case 2: /* L3 PTE */
322 return pde;
323 }
324 }
325 }
326 }
327 return 0;
328 }
329
330 #ifdef DEBUG_MMU
331 void dump_mmu(CPUState *env)
332 {
333 target_ulong va, va1, va2;
334 unsigned int n, m, o;
335 target_phys_addr_t pde_ptr, pa;
336 uint32_t pde;
337
338 printf("MMU dump:\n");
339 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
340 pde = ldl_phys(pde_ptr);
341 printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
342 (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
343 for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
344 pde = mmu_probe(env, va, 2);
345 if (pde) {
346 pa = cpu_get_phys_page_debug(env, va);
347 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
348 " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
349 for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
350 pde = mmu_probe(env, va1, 1);
351 if (pde) {
352 pa = cpu_get_phys_page_debug(env, va1);
353 printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
354 " PDE: " TARGET_FMT_lx "\n", va1, pa, pde);
355 for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
356 pde = mmu_probe(env, va2, 0);
357 if (pde) {
358 pa = cpu_get_phys_page_debug(env, va2);
359 printf(" VA: " TARGET_FMT_lx ", PA: "
360 TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n",
361 va2, pa, pde);
362 }
363 }
364 }
365 }
366 }
367 }
368 printf("MMU dump ends\n");
369 }
370 #endif /* DEBUG_MMU */
371
372 #else /* !TARGET_SPARC64 */
373 /*
374 * UltraSparc IIi I/DMMUs
375 */
376 static int get_physical_address_data(CPUState *env,
377 target_phys_addr_t *physical, int *prot,
378 target_ulong address, int rw, int is_user)
379 {
380 target_ulong mask;
381 unsigned int i;
382
383 if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
384 *physical = address;
385 *prot = PAGE_READ | PAGE_WRITE;
386 return 0;
387 }
388
389 for (i = 0; i < 64; i++) {
390 switch ((env->dtlb_tte[i] >> 61) & 3) {
391 default:
392 case 0x0: // 8k
393 mask = 0xffffffffffffe000ULL;
394 break;
395 case 0x1: // 64k
396 mask = 0xffffffffffff0000ULL;
397 break;
398 case 0x2: // 512k
399 mask = 0xfffffffffff80000ULL;
400 break;
401 case 0x3: // 4M
402 mask = 0xffffffffffc00000ULL;
403 break;
404 }
405 // ctx match, vaddr match, valid?
406 if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
407 (address & mask) == (env->dtlb_tag[i] & mask) &&
408 (env->dtlb_tte[i] & 0x8000000000000000ULL)) {
409 // access ok?
410 if (((env->dtlb_tte[i] & 0x4) && is_user) ||
411 (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
412 if (env->dmmuregs[3]) /* Fault status register */
413 env->dmmuregs[3] = 2; /* overflow (not read before
414 another fault) */
415 env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
416 env->dmmuregs[4] = address; /* Fault address register */
417 env->exception_index = TT_DFAULT;
418 #ifdef DEBUG_MMU
419 printf("DFAULT at 0x%" PRIx64 "\n", address);
420 #endif
421 return 1;
422 }
423 *physical = ((env->dtlb_tte[i] & mask) | (address & ~mask)) &
424 0x1ffffffe000ULL;
425 *prot = PAGE_READ;
426 if (env->dtlb_tte[i] & 0x2)
427 *prot |= PAGE_WRITE;
428 return 0;
429 }
430 }
431 #ifdef DEBUG_MMU
432 printf("DMISS at 0x%" PRIx64 "\n", address);
433 #endif
434 env->dmmuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff);
435 env->exception_index = TT_DMISS;
436 return 1;
437 }
438
439 static int get_physical_address_code(CPUState *env,
440 target_phys_addr_t *physical, int *prot,
441 target_ulong address, int is_user)
442 {
443 target_ulong mask;
444 unsigned int i;
445
446 if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
447 *physical = address;
448 *prot = PAGE_EXEC;
449 return 0;
450 }
451
452 for (i = 0; i < 64; i++) {
453 switch ((env->itlb_tte[i] >> 61) & 3) {
454 default:
455 case 0x0: // 8k
456 mask = 0xffffffffffffe000ULL;
457 break;
458 case 0x1: // 64k
459 mask = 0xffffffffffff0000ULL;
460 break;
461 case 0x2: // 512k
462 mask = 0xfffffffffff80000ULL;
463 break;
464 case 0x3: // 4M
465 mask = 0xffffffffffc00000ULL;
466 break;
467 }
468 // ctx match, vaddr match, valid?
469 if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
470 (address & mask) == (env->itlb_tag[i] & mask) &&
471 (env->itlb_tte[i] & 0x8000000000000000ULL)) {
472 // access ok?
473 if ((env->itlb_tte[i] & 0x4) && is_user) {
474 if (env->immuregs[3]) /* Fault status register */
475 env->immuregs[3] = 2; /* overflow (not read before
476 another fault) */
477 env->immuregs[3] |= (is_user << 3) | 1;
478 env->exception_index = TT_TFAULT;
479 #ifdef DEBUG_MMU
480 printf("TFAULT at 0x%" PRIx64 "\n", address);
481 #endif
482 return 1;
483 }
484 *physical = ((env->itlb_tte[i] & mask) | (address & ~mask)) &
485 0x1ffffffe000ULL;
486 *prot = PAGE_EXEC;
487 return 0;
488 }
489 }
490 #ifdef DEBUG_MMU
491 printf("TMISS at 0x%" PRIx64 "\n", address);
492 #endif
493 /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */
494 env->immuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff);
495 env->exception_index = TT_TMISS;
496 return 1;
497 }
498
499 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
500 int *prot, int *access_index,
501 target_ulong address, int rw, int mmu_idx)
502 {
503 int is_user = mmu_idx == MMU_USER_IDX;
504
505 if (rw == 2)
506 return get_physical_address_code(env, physical, prot, address,
507 is_user);
508 else
509 return get_physical_address_data(env, physical, prot, address, rw,
510 is_user);
511 }
512
513 /* Perform address translation */
514 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
515 int mmu_idx, int is_softmmu)
516 {
517 target_ulong virt_addr, vaddr;
518 target_phys_addr_t paddr;
519 int error_code = 0, prot, ret = 0, access_index;
520
521 error_code = get_physical_address(env, &paddr, &prot, &access_index,
522 address, rw, mmu_idx);
523 if (error_code == 0) {
524 virt_addr = address & TARGET_PAGE_MASK;
525 vaddr = virt_addr + ((address & TARGET_PAGE_MASK) &
526 (TARGET_PAGE_SIZE - 1));
527 #ifdef DEBUG_MMU
528 printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64
529 "\n", address, paddr, vaddr);
530 #endif
531 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
532 return ret;
533 }
534 // XXX
535 return 1;
536 }
537
538 #ifdef DEBUG_MMU
539 void dump_mmu(CPUState *env)
540 {
541 unsigned int i;
542 const char *mask;
543
544 printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n",
545 env->dmmuregs[1], env->dmmuregs[2]);
546 if ((env->lsu & DMMU_E) == 0) {
547 printf("DMMU disabled\n");
548 } else {
549 printf("DMMU dump:\n");
550 for (i = 0; i < 64; i++) {
551 switch ((env->dtlb_tte[i] >> 61) & 3) {
552 default:
553 case 0x0:
554 mask = " 8k";
555 break;
556 case 0x1:
557 mask = " 64k";
558 break;
559 case 0x2:
560 mask = "512k";
561 break;
562 case 0x3:
563 mask = " 4M";
564 break;
565 }
566 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
567 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx
568 ", %s, %s, %s, %s, ctx %" PRId64 "\n",
569 env->dtlb_tag[i] & ~0x1fffULL,
570 env->dtlb_tte[i] & 0x1ffffffe000ULL,
571 mask,
572 env->dtlb_tte[i] & 0x4? "priv": "user",
573 env->dtlb_tte[i] & 0x2? "RW": "RO",
574 env->dtlb_tte[i] & 0x40? "locked": "unlocked",
575 env->dtlb_tag[i] & 0x1fffULL);
576 }
577 }
578 }
579 if ((env->lsu & IMMU_E) == 0) {
580 printf("IMMU disabled\n");
581 } else {
582 printf("IMMU dump:\n");
583 for (i = 0; i < 64; i++) {
584 switch ((env->itlb_tte[i] >> 61) & 3) {
585 default:
586 case 0x0:
587 mask = " 8k";
588 break;
589 case 0x1:
590 mask = " 64k";
591 break;
592 case 0x2:
593 mask = "512k";
594 break;
595 case 0x3:
596 mask = " 4M";
597 break;
598 }
599 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
600 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx
601 ", %s, %s, %s, ctx %" PRId64 "\n",
602 env->itlb_tag[i] & ~0x1fffULL,
603 env->itlb_tte[i] & 0x1ffffffe000ULL,
604 mask,
605 env->itlb_tte[i] & 0x4? "priv": "user",
606 env->itlb_tte[i] & 0x40? "locked": "unlocked",
607 env->itlb_tag[i] & 0x1fffULL);
608 }
609 }
610 }
611 }
612 #endif /* DEBUG_MMU */
613
614 #endif /* TARGET_SPARC64 */
615 #endif /* !CONFIG_USER_ONLY */
616
617
618 #if defined(CONFIG_USER_ONLY)
619 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
620 {
621 return addr;
622 }
623
624 #else
625 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
626 {
627 target_phys_addr_t phys_addr;
628 int prot, access_index;
629
630 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
631 MMU_KERNEL_IDX) != 0)
632 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
633 0, MMU_KERNEL_IDX) != 0)
634 return -1;
635 if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
636 return -1;
637 return phys_addr;
638 }
639 #endif
640
641 void cpu_reset(CPUSPARCState *env)
642 {
643 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
644 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
645 log_cpu_state(env, 0);
646 }
647
648 tlb_flush(env, 1);
649 env->cwp = 0;
650 env->wim = 1;
651 env->regwptr = env->regbase + (env->cwp * 16);
652 #if defined(CONFIG_USER_ONLY)
653 #ifdef TARGET_SPARC64
654 env->cleanwin = env->nwindows - 2;
655 env->cansave = env->nwindows - 2;
656 env->pstate = PS_RMO | PS_PEF | PS_IE;
657 env->asi = 0x82; // Primary no-fault
658 #endif
659 #else
660 env->psret = 0;
661 env->psrs = 1;
662 env->psrps = 1;
663 CC_OP = CC_OP_FLAGS;
664 #ifdef TARGET_SPARC64
665 env->pstate = PS_PRIV;
666 env->hpstate = HS_PRIV;
667 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
668 env->lsu = 0;
669 #else
670 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
671 env->mmuregs[0] |= env->def->mmu_bm;
672 #endif
673 env->pc = 0;
674 env->npc = env->pc + 4;
675 #endif
676 }
677
678 static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
679 {
680 sparc_def_t def1, *def = &def1;
681
682 if (cpu_sparc_find_by_name(def, cpu_model) < 0)
683 return -1;
684
685 env->def = qemu_mallocz(sizeof(*def));
686 memcpy(env->def, def, sizeof(*def));
687 #if defined(CONFIG_USER_ONLY)
688 if ((env->def->features & CPU_FEATURE_FLOAT))
689 env->def->features |= CPU_FEATURE_FLOAT128;
690 #endif
691 env->cpu_model_str = cpu_model;
692 env->version = def->iu_version;
693 env->fsr = def->fpu_version;
694 env->nwindows = def->nwindows;
695 #if !defined(TARGET_SPARC64)
696 env->mmuregs[0] |= def->mmu_version;
697 cpu_sparc_set_id(env, 0);
698 env->mxccregs[7] |= def->mxcc_version;
699 #else
700 env->mmu_version = def->mmu_version;
701 env->maxtl = def->maxtl;
702 env->version |= def->maxtl << 8;
703 env->version |= def->nwindows - 1;
704 #endif
705 return 0;
706 }
707
708 static void cpu_sparc_close(CPUSPARCState *env)
709 {
710 free(env->def);
711 free(env);
712 }
713
714 CPUSPARCState *cpu_sparc_init(const char *cpu_model)
715 {
716 CPUSPARCState *env;
717
718 env = qemu_mallocz(sizeof(CPUSPARCState));
719 cpu_exec_init(env);
720
721 gen_intermediate_code_init(env);
722
723 if (cpu_sparc_register(env, cpu_model) < 0) {
724 cpu_sparc_close(env);
725 return NULL;
726 }
727 cpu_reset(env);
728 qemu_init_vcpu(env);
729
730 return env;
731 }
732
733 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
734 {
735 #if !defined(TARGET_SPARC64)
736 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
737 #endif
738 }
739
740 static const sparc_def_t sparc_defs[] = {
741 #ifdef TARGET_SPARC64
742 {
743 .name = "Fujitsu Sparc64",
744 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
745 .fpu_version = 0x00000000,
746 .mmu_version = mmu_us_12,
747 .nwindows = 4,
748 .maxtl = 4,
749 .features = CPU_DEFAULT_FEATURES,
750 },
751 {
752 .name = "Fujitsu Sparc64 III",
753 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
754 .fpu_version = 0x00000000,
755 .mmu_version = mmu_us_12,
756 .nwindows = 5,
757 .maxtl = 4,
758 .features = CPU_DEFAULT_FEATURES,
759 },
760 {
761 .name = "Fujitsu Sparc64 IV",
762 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
763 .fpu_version = 0x00000000,
764 .mmu_version = mmu_us_12,
765 .nwindows = 8,
766 .maxtl = 5,
767 .features = CPU_DEFAULT_FEATURES,
768 },
769 {
770 .name = "Fujitsu Sparc64 V",
771 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
772 .fpu_version = 0x00000000,
773 .mmu_version = mmu_us_12,
774 .nwindows = 8,
775 .maxtl = 5,
776 .features = CPU_DEFAULT_FEATURES,
777 },
778 {
779 .name = "TI UltraSparc I",
780 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
781 .fpu_version = 0x00000000,
782 .mmu_version = mmu_us_12,
783 .nwindows = 8,
784 .maxtl = 5,
785 .features = CPU_DEFAULT_FEATURES,
786 },
787 {
788 .name = "TI UltraSparc II",
789 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
790 .fpu_version = 0x00000000,
791 .mmu_version = mmu_us_12,
792 .nwindows = 8,
793 .maxtl = 5,
794 .features = CPU_DEFAULT_FEATURES,
795 },
796 {
797 .name = "TI UltraSparc IIi",
798 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
799 .fpu_version = 0x00000000,
800 .mmu_version = mmu_us_12,
801 .nwindows = 8,
802 .maxtl = 5,
803 .features = CPU_DEFAULT_FEATURES,
804 },
805 {
806 .name = "TI UltraSparc IIe",
807 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
808 .fpu_version = 0x00000000,
809 .mmu_version = mmu_us_12,
810 .nwindows = 8,
811 .maxtl = 5,
812 .features = CPU_DEFAULT_FEATURES,
813 },
814 {
815 .name = "Sun UltraSparc III",
816 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
817 .fpu_version = 0x00000000,
818 .mmu_version = mmu_us_12,
819 .nwindows = 8,
820 .maxtl = 5,
821 .features = CPU_DEFAULT_FEATURES,
822 },
823 {
824 .name = "Sun UltraSparc III Cu",
825 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
826 .fpu_version = 0x00000000,
827 .mmu_version = mmu_us_3,
828 .nwindows = 8,
829 .maxtl = 5,
830 .features = CPU_DEFAULT_FEATURES,
831 },
832 {
833 .name = "Sun UltraSparc IIIi",
834 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
835 .fpu_version = 0x00000000,
836 .mmu_version = mmu_us_12,
837 .nwindows = 8,
838 .maxtl = 5,
839 .features = CPU_DEFAULT_FEATURES,
840 },
841 {
842 .name = "Sun UltraSparc IV",
843 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
844 .fpu_version = 0x00000000,
845 .mmu_version = mmu_us_4,
846 .nwindows = 8,
847 .maxtl = 5,
848 .features = CPU_DEFAULT_FEATURES,
849 },
850 {
851 .name = "Sun UltraSparc IV+",
852 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
853 .fpu_version = 0x00000000,
854 .mmu_version = mmu_us_12,
855 .nwindows = 8,
856 .maxtl = 5,
857 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
858 },
859 {
860 .name = "Sun UltraSparc IIIi+",
861 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
862 .fpu_version = 0x00000000,
863 .mmu_version = mmu_us_3,
864 .nwindows = 8,
865 .maxtl = 5,
866 .features = CPU_DEFAULT_FEATURES,
867 },
868 {
869 .name = "Sun UltraSparc T1",
870 // defined in sparc_ifu_fdp.v and ctu.h
871 .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
872 .fpu_version = 0x00000000,
873 .mmu_version = mmu_sun4v,
874 .nwindows = 8,
875 .maxtl = 6,
876 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
877 | CPU_FEATURE_GL,
878 },
879 {
880 .name = "Sun UltraSparc T2",
881 // defined in tlu_asi_ctl.v and n2_revid_cust.v
882 .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
883 .fpu_version = 0x00000000,
884 .mmu_version = mmu_sun4v,
885 .nwindows = 8,
886 .maxtl = 6,
887 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
888 | CPU_FEATURE_GL,
889 },
890 {
891 .name = "NEC UltraSparc I",
892 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
893 .fpu_version = 0x00000000,
894 .mmu_version = mmu_us_12,
895 .nwindows = 8,
896 .maxtl = 5,
897 .features = CPU_DEFAULT_FEATURES,
898 },
899 #else
900 {
901 .name = "Fujitsu MB86900",
902 .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
903 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
904 .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
905 .mmu_bm = 0x00004000,
906 .mmu_ctpr_mask = 0x007ffff0,
907 .mmu_cxr_mask = 0x0000003f,
908 .mmu_sfsr_mask = 0xffffffff,
909 .mmu_trcr_mask = 0xffffffff,
910 .nwindows = 7,
911 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD,
912 },
913 {
914 .name = "Fujitsu MB86904",
915 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
916 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
917 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
918 .mmu_bm = 0x00004000,
919 .mmu_ctpr_mask = 0x00ffffc0,
920 .mmu_cxr_mask = 0x000000ff,
921 .mmu_sfsr_mask = 0x00016fff,
922 .mmu_trcr_mask = 0x00ffffff,
923 .nwindows = 8,
924 .features = CPU_DEFAULT_FEATURES,
925 },
926 {
927 .name = "Fujitsu MB86907",
928 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
929 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
930 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
931 .mmu_bm = 0x00004000,
932 .mmu_ctpr_mask = 0xffffffc0,
933 .mmu_cxr_mask = 0x000000ff,
934 .mmu_sfsr_mask = 0x00016fff,
935 .mmu_trcr_mask = 0xffffffff,
936 .nwindows = 8,
937 .features = CPU_DEFAULT_FEATURES,
938 },
939 {
940 .name = "LSI L64811",
941 .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
942 .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
943 .mmu_version = 0x10 << 24,
944 .mmu_bm = 0x00004000,
945 .mmu_ctpr_mask = 0x007ffff0,
946 .mmu_cxr_mask = 0x0000003f,
947 .mmu_sfsr_mask = 0xffffffff,
948 .mmu_trcr_mask = 0xffffffff,
949 .nwindows = 8,
950 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
951 CPU_FEATURE_FSMULD,
952 },
953 {
954 .name = "Cypress CY7C601",
955 .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
956 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
957 .mmu_version = 0x10 << 24,
958 .mmu_bm = 0x00004000,
959 .mmu_ctpr_mask = 0x007ffff0,
960 .mmu_cxr_mask = 0x0000003f,
961 .mmu_sfsr_mask = 0xffffffff,
962 .mmu_trcr_mask = 0xffffffff,
963 .nwindows = 8,
964 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
965 CPU_FEATURE_FSMULD,
966 },
967 {
968 .name = "Cypress CY7C611",
969 .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
970 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
971 .mmu_version = 0x10 << 24,
972 .mmu_bm = 0x00004000,
973 .mmu_ctpr_mask = 0x007ffff0,
974 .mmu_cxr_mask = 0x0000003f,
975 .mmu_sfsr_mask = 0xffffffff,
976 .mmu_trcr_mask = 0xffffffff,
977 .nwindows = 8,
978 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
979 CPU_FEATURE_FSMULD,
980 },
981 {
982 .name = "TI MicroSparc I",
983 .iu_version = 0x41000000,
984 .fpu_version = 4 << 17,
985 .mmu_version = 0x41000000,
986 .mmu_bm = 0x00004000,
987 .mmu_ctpr_mask = 0x007ffff0,
988 .mmu_cxr_mask = 0x0000003f,
989 .mmu_sfsr_mask = 0x00016fff,
990 .mmu_trcr_mask = 0x0000003f,
991 .nwindows = 7,
992 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
993 CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
994 CPU_FEATURE_FMUL,
995 },
996 {
997 .name = "TI MicroSparc II",
998 .iu_version = 0x42000000,
999 .fpu_version = 4 << 17,
1000 .mmu_version = 0x02000000,
1001 .mmu_bm = 0x00004000,
1002 .mmu_ctpr_mask = 0x00ffffc0,
1003 .mmu_cxr_mask = 0x000000ff,
1004 .mmu_sfsr_mask = 0x00016fff,
1005 .mmu_trcr_mask = 0x00ffffff,
1006 .nwindows = 8,
1007 .features = CPU_DEFAULT_FEATURES,
1008 },
1009 {
1010 .name = "TI MicroSparc IIep",
1011 .iu_version = 0x42000000,
1012 .fpu_version = 4 << 17,
1013 .mmu_version = 0x04000000,
1014 .mmu_bm = 0x00004000,
1015 .mmu_ctpr_mask = 0x00ffffc0,
1016 .mmu_cxr_mask = 0x000000ff,
1017 .mmu_sfsr_mask = 0x00016bff,
1018 .mmu_trcr_mask = 0x00ffffff,
1019 .nwindows = 8,
1020 .features = CPU_DEFAULT_FEATURES,
1021 },
1022 {
1023 .name = "TI SuperSparc 40", // STP1020NPGA
1024 .iu_version = 0x41000000, // SuperSPARC 2.x
1025 .fpu_version = 0 << 17,
1026 .mmu_version = 0x00000800, // SuperSPARC 2.x, no MXCC
1027 .mmu_bm = 0x00002000,
1028 .mmu_ctpr_mask = 0xffffffc0,
1029 .mmu_cxr_mask = 0x0000ffff,
1030 .mmu_sfsr_mask = 0xffffffff,
1031 .mmu_trcr_mask = 0xffffffff,
1032 .nwindows = 8,
1033 .features = CPU_DEFAULT_FEATURES,
1034 },
1035 {
1036 .name = "TI SuperSparc 50", // STP1020PGA
1037 .iu_version = 0x40000000, // SuperSPARC 3.x
1038 .fpu_version = 0 << 17,
1039 .mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC
1040 .mmu_bm = 0x00002000,
1041 .mmu_ctpr_mask = 0xffffffc0,
1042 .mmu_cxr_mask = 0x0000ffff,
1043 .mmu_sfsr_mask = 0xffffffff,
1044 .mmu_trcr_mask = 0xffffffff,
1045 .nwindows = 8,
1046 .features = CPU_DEFAULT_FEATURES,
1047 },
1048 {
1049 .name = "TI SuperSparc 51",
1050 .iu_version = 0x40000000, // SuperSPARC 3.x
1051 .fpu_version = 0 << 17,
1052 .mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC
1053 .mmu_bm = 0x00002000,
1054 .mmu_ctpr_mask = 0xffffffc0,
1055 .mmu_cxr_mask = 0x0000ffff,
1056 .mmu_sfsr_mask = 0xffffffff,
1057 .mmu_trcr_mask = 0xffffffff,
1058 .mxcc_version = 0x00000104,
1059 .nwindows = 8,
1060 .features = CPU_DEFAULT_FEATURES,
1061 },
1062 {
1063 .name = "TI SuperSparc 60", // STP1020APGA
1064 .iu_version = 0x40000000, // SuperSPARC 3.x
1065 .fpu_version = 0 << 17,
1066 .mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC
1067 .mmu_bm = 0x00002000,
1068 .mmu_ctpr_mask = 0xffffffc0,
1069 .mmu_cxr_mask = 0x0000ffff,
1070 .mmu_sfsr_mask = 0xffffffff,
1071 .mmu_trcr_mask = 0xffffffff,
1072 .nwindows = 8,
1073 .features = CPU_DEFAULT_FEATURES,
1074 },
1075 {
1076 .name = "TI SuperSparc 61",
1077 .iu_version = 0x44000000, // SuperSPARC 3.x
1078 .fpu_version = 0 << 17,
1079 .mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC
1080 .mmu_bm = 0x00002000,
1081 .mmu_ctpr_mask = 0xffffffc0,
1082 .mmu_cxr_mask = 0x0000ffff,
1083 .mmu_sfsr_mask = 0xffffffff,
1084 .mmu_trcr_mask = 0xffffffff,
1085 .mxcc_version = 0x00000104,
1086 .nwindows = 8,
1087 .features = CPU_DEFAULT_FEATURES,
1088 },
1089 {
1090 .name = "TI SuperSparc II",
1091 .iu_version = 0x40000000, // SuperSPARC II 1.x
1092 .fpu_version = 0 << 17,
1093 .mmu_version = 0x08000000, // SuperSPARC II 1.x, MXCC
1094 .mmu_bm = 0x00002000,
1095 .mmu_ctpr_mask = 0xffffffc0,
1096 .mmu_cxr_mask = 0x0000ffff,
1097 .mmu_sfsr_mask = 0xffffffff,
1098 .mmu_trcr_mask = 0xffffffff,
1099 .mxcc_version = 0x00000104,
1100 .nwindows = 8,
1101 .features = CPU_DEFAULT_FEATURES,
1102 },
1103 {
1104 .name = "Ross RT625",
1105 .iu_version = 0x1e000000,
1106 .fpu_version = 1 << 17,
1107 .mmu_version = 0x1e000000,
1108 .mmu_bm = 0x00004000,
1109 .mmu_ctpr_mask = 0x007ffff0,
1110 .mmu_cxr_mask = 0x0000003f,
1111 .mmu_sfsr_mask = 0xffffffff,
1112 .mmu_trcr_mask = 0xffffffff,
1113 .nwindows = 8,
1114 .features = CPU_DEFAULT_FEATURES,
1115 },
1116 {
1117 .name = "Ross RT620",
1118 .iu_version = 0x1f000000,
1119 .fpu_version = 1 << 17,
1120 .mmu_version = 0x1f000000,
1121 .mmu_bm = 0x00004000,
1122 .mmu_ctpr_mask = 0x007ffff0,
1123 .mmu_cxr_mask = 0x0000003f,
1124 .mmu_sfsr_mask = 0xffffffff,
1125 .mmu_trcr_mask = 0xffffffff,
1126 .nwindows = 8,
1127 .features = CPU_DEFAULT_FEATURES,
1128 },
1129 {
1130 .name = "BIT B5010",
1131 .iu_version = 0x20000000,
1132 .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
1133 .mmu_version = 0x20000000,
1134 .mmu_bm = 0x00004000,
1135 .mmu_ctpr_mask = 0x007ffff0,
1136 .mmu_cxr_mask = 0x0000003f,
1137 .mmu_sfsr_mask = 0xffffffff,
1138 .mmu_trcr_mask = 0xffffffff,
1139 .nwindows = 8,
1140 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1141 CPU_FEATURE_FSMULD,
1142 },
1143 {
1144 .name = "Matsushita MN10501",
1145 .iu_version = 0x50000000,
1146 .fpu_version = 0 << 17,
1147 .mmu_version = 0x50000000,
1148 .mmu_bm = 0x00004000,
1149 .mmu_ctpr_mask = 0x007ffff0,
1150 .mmu_cxr_mask = 0x0000003f,
1151 .mmu_sfsr_mask = 0xffffffff,
1152 .mmu_trcr_mask = 0xffffffff,
1153 .nwindows = 8,
1154 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT |
1155 CPU_FEATURE_FSMULD,
1156 },
1157 {
1158 .name = "Weitek W8601",
1159 .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
1160 .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
1161 .mmu_version = 0x10 << 24,
1162 .mmu_bm = 0x00004000,
1163 .mmu_ctpr_mask = 0x007ffff0,
1164 .mmu_cxr_mask = 0x0000003f,
1165 .mmu_sfsr_mask = 0xffffffff,
1166 .mmu_trcr_mask = 0xffffffff,
1167 .nwindows = 8,
1168 .features = CPU_DEFAULT_FEATURES,
1169 },
1170 {
1171 .name = "LEON2",
1172 .iu_version = 0xf2000000,
1173 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1174 .mmu_version = 0xf2000000,
1175 .mmu_bm = 0x00004000,
1176 .mmu_ctpr_mask = 0x007ffff0,
1177 .mmu_cxr_mask = 0x0000003f,
1178 .mmu_sfsr_mask = 0xffffffff,
1179 .mmu_trcr_mask = 0xffffffff,
1180 .nwindows = 8,
1181 .features = CPU_DEFAULT_FEATURES,
1182 },
1183 {
1184 .name = "LEON3",
1185 .iu_version = 0xf3000000,
1186 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1187 .mmu_version = 0xf3000000,
1188 .mmu_bm = 0x00004000,
1189 .mmu_ctpr_mask = 0x007ffff0,
1190 .mmu_cxr_mask = 0x0000003f,
1191 .mmu_sfsr_mask = 0xffffffff,
1192 .mmu_trcr_mask = 0xffffffff,
1193 .nwindows = 8,
1194 .features = CPU_DEFAULT_FEATURES,
1195 },
1196 #endif
1197 };
1198
1199 static const char * const feature_name[] = {
1200 "float",
1201 "float128",
1202 "swap",
1203 "mul",
1204 "div",
1205 "flush",
1206 "fsqrt",
1207 "fmul",
1208 "vis1",
1209 "vis2",
1210 "fsmuld",
1211 "hypv",
1212 "cmt",
1213 "gl",
1214 };
1215
1216 static void print_features(FILE *f,
1217 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1218 uint32_t features, const char *prefix)
1219 {
1220 unsigned int i;
1221
1222 for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1223 if (feature_name[i] && (features & (1 << i))) {
1224 if (prefix)
1225 (*cpu_fprintf)(f, "%s", prefix);
1226 (*cpu_fprintf)(f, "%s ", feature_name[i]);
1227 }
1228 }
1229
1230 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
1231 {
1232 unsigned int i;
1233
1234 for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1235 if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
1236 *features |= 1 << i;
1237 return;
1238 }
1239 fprintf(stderr, "CPU feature %s not found\n", flagname);
1240 }
1241
1242 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model)
1243 {
1244 unsigned int i;
1245 const sparc_def_t *def = NULL;
1246 char *s = strdup(cpu_model);
1247 char *featurestr, *name = strtok(s, ",");
1248 uint32_t plus_features = 0;
1249 uint32_t minus_features = 0;
1250 long long iu_version;
1251 uint32_t fpu_version, mmu_version, nwindows;
1252
1253 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
1254 if (strcasecmp(name, sparc_defs[i].name) == 0) {
1255 def = &sparc_defs[i];
1256 }
1257 }
1258 if (!def)
1259 goto error;
1260 memcpy(cpu_def, def, sizeof(*def));
1261
1262 featurestr = strtok(NULL, ",");
1263 while (featurestr) {
1264 char *val;
1265
1266 if (featurestr[0] == '+') {
1267 add_flagname_to_bitmaps(featurestr + 1, &plus_features);
1268 } else if (featurestr[0] == '-') {
1269 add_flagname_to_bitmaps(featurestr + 1, &minus_features);
1270 } else if ((val = strchr(featurestr, '='))) {
1271 *val = 0; val++;
1272 if (!strcmp(featurestr, "iu_version")) {
1273 char *err;
1274
1275 iu_version = strtoll(val, &err, 0);
1276 if (!*val || *err) {
1277 fprintf(stderr, "bad numerical value %s\n", val);
1278 goto error;
1279 }
1280 cpu_def->iu_version = iu_version;
1281 #ifdef DEBUG_FEATURES
1282 fprintf(stderr, "iu_version %llx\n", iu_version);
1283 #endif
1284 } else if (!strcmp(featurestr, "fpu_version")) {
1285 char *err;
1286
1287 fpu_version = strtol(val, &err, 0);
1288 if (!*val || *err) {
1289 fprintf(stderr, "bad numerical value %s\n", val);
1290 goto error;
1291 }
1292 cpu_def->fpu_version = fpu_version;
1293 #ifdef DEBUG_FEATURES
1294 fprintf(stderr, "fpu_version %llx\n", fpu_version);
1295 #endif
1296 } else if (!strcmp(featurestr, "mmu_version")) {
1297 char *err;
1298
1299 mmu_version = strtol(val, &err, 0);
1300 if (!*val || *err) {
1301 fprintf(stderr, "bad numerical value %s\n", val);
1302 goto error;
1303 }
1304 cpu_def->mmu_version = mmu_version;
1305 #ifdef DEBUG_FEATURES
1306 fprintf(stderr, "mmu_version %llx\n", mmu_version);
1307 #endif
1308 } else if (!strcmp(featurestr, "nwindows")) {
1309 char *err;
1310
1311 nwindows = strtol(val, &err, 0);
1312 if (!*val || *err || nwindows > MAX_NWINDOWS ||
1313 nwindows < MIN_NWINDOWS) {
1314 fprintf(stderr, "bad numerical value %s\n", val);
1315 goto error;
1316 }
1317 cpu_def->nwindows = nwindows;
1318 #ifdef DEBUG_FEATURES
1319 fprintf(stderr, "nwindows %d\n", nwindows);
1320 #endif
1321 } else {
1322 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1323 goto error;
1324 }
1325 } else {
1326 fprintf(stderr, "feature string `%s' not in format "
1327 "(+feature|-feature|feature=xyz)\n", featurestr);
1328 goto error;
1329 }
1330 featurestr = strtok(NULL, ",");
1331 }
1332 cpu_def->features |= plus_features;
1333 cpu_def->features &= ~minus_features;
1334 #ifdef DEBUG_FEATURES
1335 print_features(stderr, fprintf, cpu_def->features, NULL);
1336 #endif
1337 free(s);
1338 return 0;
1339
1340 error:
1341 free(s);
1342 return -1;
1343 }
1344
1345 void sparc_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
1346 {
1347 unsigned int i;
1348
1349 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
1350 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x NWINS %d ",
1351 sparc_defs[i].name,
1352 sparc_defs[i].iu_version,
1353 sparc_defs[i].fpu_version,
1354 sparc_defs[i].mmu_version,
1355 sparc_defs[i].nwindows);
1356 print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES &
1357 ~sparc_defs[i].features, "-");
1358 print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES &
1359 sparc_defs[i].features, "+");
1360 (*cpu_fprintf)(f, "\n");
1361 }
1362 (*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
1363 print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
1364 (*cpu_fprintf)(f, "\n");
1365 (*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
1366 print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
1367 (*cpu_fprintf)(f, "\n");
1368 (*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
1369 "fpu_version mmu_version nwindows\n");
1370 }
1371
1372 void cpu_dump_state(CPUState *env, FILE *f,
1373 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1374 int flags)
1375 {
1376 int i, x;
1377
1378 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
1379 env->npc);
1380 cpu_fprintf(f, "General Registers:\n");
1381 for (i = 0; i < 4; i++)
1382 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1383 cpu_fprintf(f, "\n");
1384 for (; i < 8; i++)
1385 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1386 cpu_fprintf(f, "\nCurrent Register Window:\n");
1387 for (x = 0; x < 3; x++) {
1388 for (i = 0; i < 4; i++)
1389 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1390 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
1391 env->regwptr[i + x * 8]);
1392 cpu_fprintf(f, "\n");
1393 for (; i < 8; i++)
1394 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1395 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
1396 env->regwptr[i + x * 8]);
1397 cpu_fprintf(f, "\n");
1398 }
1399 cpu_fprintf(f, "\nFloating Point Registers:\n");
1400 for (i = 0; i < 32; i++) {
1401 if ((i & 3) == 0)
1402 cpu_fprintf(f, "%%f%02d:", i);
1403 cpu_fprintf(f, " %016f", *(float *)&env->fpr[i]);
1404 if ((i & 3) == 3)
1405 cpu_fprintf(f, "\n");
1406 }
1407 #ifdef TARGET_SPARC64
1408 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
1409 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
1410 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d "
1411 "cleanwin %d cwp %d\n",
1412 env->cansave, env->canrestore, env->otherwin, env->wstate,
1413 env->cleanwin, env->nwindows - 1 - env->cwp);
1414 #else
1415
1416 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
1417
1418 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n",
1419 GET_PSR(env), GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
1420 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
1421 env->psrs?'S':'-', env->psrps?'P':'-',
1422 env->psret?'E':'-', env->wim);
1423 #endif
1424 cpu_fprintf(f, "fsr: 0x%08x\n", env->fsr);
1425 }
Qemu copy for testing