target-sparc/helper.c

   1 /*
   2  *  sparc helpers
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <stdarg.h>
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <string.h>
  24 #include <inttypes.h>
  25 #include <signal.h>
  26 #include <assert.h>
  27
  28 #include "cpu.h"
  29 #include "exec-all.h"
  30 #include "qemu-common.h"
  31 #include "helper.h"
  32
  33 //#define DEBUG_MMU
  34 //#define DEBUG_FEATURES
  35
  36 typedef struct sparc_def_t sparc_def_t;
  37
  38 struct sparc_def_t {
  39     const char *name;
  40     target_ulong iu_version;
  41     uint32_t fpu_version;
  42     uint32_t mmu_version;
  43     uint32_t mmu_bm;
  44     uint32_t mmu_ctpr_mask;
  45     uint32_t mmu_cxr_mask;
  46     uint32_t mmu_sfsr_mask;
  47     uint32_t mmu_trcr_mask;
  48     uint32_t features;
  49 };
  50
  51 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
  52
  53 /* Sparc MMU emulation */
  54
  55 /* thread support */
  56
  57 spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
  58
  59 void cpu_lock(void)
  60 {
  61     spin_lock(&global_cpu_lock);
  62 }
  63
  64 void cpu_unlock(void)
  65 {
  66     spin_unlock(&global_cpu_lock);
  67 }
  68
  69 #if defined(CONFIG_USER_ONLY)
  70
  71 int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw,
  72                                int mmu_idx, int is_softmmu)
  73 {
  74     if (rw & 2)
  75         env1->exception_index = TT_TFAULT;
  76     else
  77         env1->exception_index = TT_DFAULT;
  78     return 1;
  79 }
  80
  81 #else
  82
  83 #ifndef TARGET_SPARC64
  84 /*
  85  * Sparc V8 Reference MMU (SRMMU)
  86  */
  87 static const int access_table[8][8] = {
  88     { 0, 0, 0, 0, 2, 0, 3, 3 },
  89     { 0, 0, 0, 0, 2, 0, 0, 0 },
  90     { 2, 2, 0, 0, 0, 2, 3, 3 },
  91     { 2, 2, 0, 0, 0, 2, 0, 0 },
  92     { 2, 0, 2, 0, 2, 2, 3, 3 },
  93     { 2, 0, 2, 0, 2, 0, 2, 0 },
  94     { 2, 2, 2, 0, 2, 2, 3, 3 },
  95     { 2, 2, 2, 0, 2, 2, 2, 0 }
  96 };
  97
  98 static const int perm_table[2][8] = {
  99     {
 100         PAGE_READ,
 101         PAGE_READ | PAGE_WRITE,
 102         PAGE_READ | PAGE_EXEC,
 103         PAGE_READ | PAGE_WRITE | PAGE_EXEC,
 104         PAGE_EXEC,
 105         PAGE_READ | PAGE_WRITE,
 106         PAGE_READ | PAGE_EXEC,
 107         PAGE_READ | PAGE_WRITE | PAGE_EXEC
 108     },
 109     {
 110         PAGE_READ,
 111         PAGE_READ | PAGE_WRITE,
 112         PAGE_READ | PAGE_EXEC,
 113         PAGE_READ | PAGE_WRITE | PAGE_EXEC,
 114         PAGE_EXEC,
 115         PAGE_READ,
 116         0,
 117         0,
 118     }
 119 };
 120
 121 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
 122                                 int *prot, int *access_index,
 123                                 target_ulong address, int rw, int mmu_idx)
 124 {
 125     int access_perms = 0;
 126     target_phys_addr_t pde_ptr;
 127     uint32_t pde;
 128     target_ulong virt_addr;
 129     int error_code = 0, is_dirty, is_user;
 130     unsigned long page_offset;
 131
 132     is_user = mmu_idx == MMU_USER_IDX;
 133     virt_addr = address & TARGET_PAGE_MASK;
 134
 135     if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
 136         // Boot mode: instruction fetches are taken from PROM
 137         if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) {
 138             *physical = env->prom_addr | (address & 0x7ffffULL);
 139             *prot = PAGE_READ | PAGE_EXEC;
 140             return 0;
 141         }
 142         *physical = address;
 143         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 144         return 0;
 145     }
 146
 147     *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
 148     *physical = 0xffffffffffff0000ULL;
 149
 150     /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
 151     /* Context base + context number */
 152     pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
 153     pde = ldl_phys(pde_ptr);
 154
 155     /* Ctx pde */
 156     switch (pde & PTE_ENTRYTYPE_MASK) {
 157     default:
 158     case 0: /* Invalid */
 159         return 1 << 2;
 160     case 2: /* L0 PTE, maybe should not happen? */
 161     case 3: /* Reserved */
 162         return 4 << 2;
 163     case 1: /* L0 PDE */
 164         pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
 165         pde = ldl_phys(pde_ptr);
 166
 167         switch (pde & PTE_ENTRYTYPE_MASK) {
 168         default:
 169         case 0: /* Invalid */
 170             return (1 << 8) | (1 << 2);
 171         case 3: /* Reserved */
 172             return (1 << 8) | (4 << 2);
 173         case 1: /* L1 PDE */
 174             pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
 175             pde = ldl_phys(pde_ptr);
 176
 177             switch (pde & PTE_ENTRYTYPE_MASK) {
 178             default:
 179             case 0: /* Invalid */
 180                 return (2 << 8) | (1 << 2);
 181             case 3: /* Reserved */
 182                 return (2 << 8) | (4 << 2);
 183             case 1: /* L2 PDE */
 184                 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
 185                 pde = ldl_phys(pde_ptr);
 186
 187                 switch (pde & PTE_ENTRYTYPE_MASK) {
 188                 default:
 189                 case 0: /* Invalid */
 190                     return (3 << 8) | (1 << 2);
 191                 case 1: /* PDE, should not happen */
 192                 case 3: /* Reserved */
 193                     return (3 << 8) | (4 << 2);
 194                 case 2: /* L3 PTE */
 195                     virt_addr = address & TARGET_PAGE_MASK;
 196                     page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
 197                 }
 198                 break;
 199             case 2: /* L2 PTE */
 200                 virt_addr = address & ~0x3ffff;
 201                 page_offset = address & 0x3ffff;
 202             }
 203             break;
 204         case 2: /* L1 PTE */
 205             virt_addr = address & ~0xffffff;
 206             page_offset = address & 0xffffff;
 207         }
 208     }
 209
 210     /* update page modified and dirty bits */
 211     is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
 212     if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
 213         pde |= PG_ACCESSED_MASK;
 214         if (is_dirty)
 215             pde |= PG_MODIFIED_MASK;
 216         stl_phys_notdirty(pde_ptr, pde);
 217     }
 218     /* check access */
 219     access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
 220     error_code = access_table[*access_index][access_perms];
 221     if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
 222         return error_code;
 223
 224     /* the page can be put in the TLB */
 225     *prot = perm_table[is_user][access_perms];
 226     if (!(pde & PG_MODIFIED_MASK)) {
 227         /* only set write access if already dirty... otherwise wait
 228            for dirty access */
 229         *prot &= ~PAGE_WRITE;
 230     }
 231
 232     /* Even if large ptes, we map only one 4KB page in the cache to
 233        avoid filling it too fast */
 234     *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
 235     return error_code;
 236 }
 237
 238 /* Perform address translation */
 239 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
 240                               int mmu_idx, int is_softmmu)
 241 {
 242     target_phys_addr_t paddr;
 243     target_ulong vaddr;
 244     int error_code = 0, prot, ret = 0, access_index;
 245
 246     error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx);
 247     if (error_code == 0) {
 248         vaddr = address & TARGET_PAGE_MASK;
 249         paddr &= TARGET_PAGE_MASK;
 250 #ifdef DEBUG_MMU
 251         printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
 252                TARGET_FMT_lx "\n", address, paddr, vaddr);
 253 #endif
 254         ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
 255         return ret;
 256     }
 257
 258     if (env->mmuregs[3]) /* Fault status register */
 259         env->mmuregs[3] = 1; /* overflow (not read before another fault) */
 260     env->mmuregs[3] |= (access_index << 5) | error_code | 2;
 261     env->mmuregs[4] = address; /* Fault address register */
 262
 263     if ((env->mmuregs[0] & MMU_NF) || env->psret == 0)  {
 264         // No fault mode: if a mapping is available, just override
 265         // permissions. If no mapping is available, redirect accesses to
 266         // neverland. Fake/overridden mappings will be flushed when
 267         // switching to normal mode.
 268         vaddr = address & TARGET_PAGE_MASK;
 269         prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 270         ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
 271         return ret;
 272     } else {
 273         if (rw & 2)
 274             env->exception_index = TT_TFAULT;
 275         else
 276             env->exception_index = TT_DFAULT;
 277         return 1;
 278     }
 279 }
 280
 281 target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
 282 {
 283     target_phys_addr_t pde_ptr;
 284     uint32_t pde;
 285
 286     /* Context base + context number */
 287     pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
 288         (env->mmuregs[2] << 2);
 289     pde = ldl_phys(pde_ptr);
 290
 291     switch (pde & PTE_ENTRYTYPE_MASK) {
 292     default:
 293     case 0: /* Invalid */
 294     case 2: /* PTE, maybe should not happen? */
 295     case 3: /* Reserved */
 296         return 0;
 297     case 1: /* L1 PDE */
 298         if (mmulev == 3)
 299             return pde;
 300         pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
 301         pde = ldl_phys(pde_ptr);
 302
 303         switch (pde & PTE_ENTRYTYPE_MASK) {
 304         default:
 305         case 0: /* Invalid */
 306         case 3: /* Reserved */
 307             return 0;
 308         case 2: /* L1 PTE */
 309             return pde;
 310         case 1: /* L2 PDE */
 311             if (mmulev == 2)
 312                 return pde;
 313             pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
 314             pde = ldl_phys(pde_ptr);
 315
 316             switch (pde & PTE_ENTRYTYPE_MASK) {
 317             default:
 318             case 0: /* Invalid */
 319             case 3: /* Reserved */
 320                 return 0;
 321             case 2: /* L2 PTE */
 322                 return pde;
 323             case 1: /* L3 PDE */
 324                 if (mmulev == 1)
 325                     return pde;
 326                 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
 327                 pde = ldl_phys(pde_ptr);
 328
 329                 switch (pde & PTE_ENTRYTYPE_MASK) {
 330                 default:
 331                 case 0: /* Invalid */
 332                 case 1: /* PDE, should not happen */
 333                 case 3: /* Reserved */
 334                     return 0;
 335                 case 2: /* L3 PTE */
 336                     return pde;
 337                 }
 338             }
 339         }
 340     }
 341     return 0;
 342 }
 343
 344 #ifdef DEBUG_MMU
 345 void dump_mmu(CPUState *env)
 346 {
 347     target_ulong va, va1, va2;
 348     unsigned int n, m, o;
 349     target_phys_addr_t pde_ptr, pa;
 350     uint32_t pde;
 351
 352     printf("MMU dump:\n");
 353     pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
 354     pde = ldl_phys(pde_ptr);
 355     printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
 356            (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
 357     for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
 358         pde = mmu_probe(env, va, 2);
 359         if (pde) {
 360             pa = cpu_get_phys_page_debug(env, va);
 361             printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
 362                    " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
 363             for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
 364                 pde = mmu_probe(env, va1, 1);
 365                 if (pde) {
 366                     pa = cpu_get_phys_page_debug(env, va1);
 367                     printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
 368                            " PDE: " TARGET_FMT_lx "\n", va1, pa, pde);
 369                     for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
 370                         pde = mmu_probe(env, va2, 0);
 371                         if (pde) {
 372                             pa = cpu_get_phys_page_debug(env, va2);
 373                             printf("  VA: " TARGET_FMT_lx ", PA: "
 374                                    TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n",
 375                                    va2, pa, pde);
 376                         }
 377                     }
 378                 }
 379             }
 380         }
 381     }
 382     printf("MMU dump ends\n");
 383 }
 384 #endif /* DEBUG_MMU */
 385
 386 #else /* !TARGET_SPARC64 */
 387 /*
 388  * UltraSparc IIi I/DMMUs
 389  */
 390 static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot,
 391                                      target_ulong address, int rw, int is_user)
 392 {
 393     target_ulong mask;
 394     unsigned int i;
 395
 396     if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
 397         *physical = address;
 398         *prot = PAGE_READ | PAGE_WRITE;
 399         return 0;
 400     }
 401
 402     for (i = 0; i < 64; i++) {
 403         switch ((env->dtlb_tte[i] >> 61) & 3) {
 404         default:
 405         case 0x0: // 8k
 406             mask = 0xffffffffffffe000ULL;
 407             break;
 408         case 0x1: // 64k
 409             mask = 0xffffffffffff0000ULL;
 410             break;
 411         case 0x2: // 512k
 412             mask = 0xfffffffffff80000ULL;
 413             break;
 414         case 0x3: // 4M
 415             mask = 0xffffffffffc00000ULL;
 416             break;
 417         }
 418         // ctx match, vaddr match?
 419         if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
 420             (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
 421             // valid, access ok?
 422             if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
 423                 ((env->dtlb_tte[i] & 0x4) && is_user) ||
 424                 (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
 425                 if (env->dmmuregs[3]) /* Fault status register */
 426                     env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
 427                 env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
 428                 env->dmmuregs[4] = address; /* Fault address register */
 429                 env->exception_index = TT_DFAULT;
 430 #ifdef DEBUG_MMU
 431                 printf("DFAULT at 0x%" PRIx64 "\n", address);
 432 #endif
 433                 return 1;
 434             }
 435             *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
 436             *prot = PAGE_READ;
 437             if (env->dtlb_tte[i] & 0x2)
 438                 *prot |= PAGE_WRITE;
 439             return 0;
 440         }
 441     }
 442 #ifdef DEBUG_MMU
 443     printf("DMISS at 0x%" PRIx64 "\n", address);
 444 #endif
 445     env->exception_index = TT_DMISS;
 446     return 1;
 447 }
 448
 449 static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot,
 450                                      target_ulong address, int is_user)
 451 {
 452     target_ulong mask;
 453     unsigned int i;
 454
 455     if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
 456         *physical = address;
 457         *prot = PAGE_EXEC;
 458         return 0;
 459     }
 460
 461     for (i = 0; i < 64; i++) {
 462         switch ((env->itlb_tte[i] >> 61) & 3) {
 463         default:
 464         case 0x0: // 8k
 465             mask = 0xffffffffffffe000ULL;
 466             break;
 467         case 0x1: // 64k
 468             mask = 0xffffffffffff0000ULL;
 469             break;
 470         case 0x2: // 512k
 471             mask = 0xfffffffffff80000ULL;
 472             break;
 473         case 0x3: // 4M
 474             mask = 0xffffffffffc00000ULL;
 475                 break;
 476         }
 477         // ctx match, vaddr match?
 478         if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
 479             (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
 480             // valid, access ok?
 481             if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
 482                 ((env->itlb_tte[i] & 0x4) && is_user)) {
 483                 if (env->immuregs[3]) /* Fault status register */
 484                     env->immuregs[3] = 2; /* overflow (not read before another fault) */
 485                 env->immuregs[3] |= (is_user << 3) | 1;
 486                 env->exception_index = TT_TFAULT;
 487 #ifdef DEBUG_MMU
 488                 printf("TFAULT at 0x%" PRIx64 "\n", address);
 489 #endif
 490                 return 1;
 491             }
 492             *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
 493             *prot = PAGE_EXEC;
 494             return 0;
 495         }
 496     }
 497 #ifdef DEBUG_MMU
 498     printf("TMISS at 0x%" PRIx64 "\n", address);
 499 #endif
 500     env->exception_index = TT_TMISS;
 501     return 1;
 502 }
 503
 504 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
 505                                 int *prot, int *access_index,
 506                                 target_ulong address, int rw, int mmu_idx)
 507 {
 508     int is_user = mmu_idx == MMU_USER_IDX;
 509
 510     if (rw == 2)
 511         return get_physical_address_code(env, physical, prot, address,
 512                                          is_user);
 513     else
 514         return get_physical_address_data(env, physical, prot, address, rw,
 515                                          is_user);
 516 }
 517
 518 /* Perform address translation */
 519 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
 520                               int mmu_idx, int is_softmmu)
 521 {
 522     target_ulong virt_addr, vaddr;
 523     target_phys_addr_t paddr;
 524     int error_code = 0, prot, ret = 0, access_index;
 525
 526     error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx);
 527     if (error_code == 0) {
 528         virt_addr = address & TARGET_PAGE_MASK;
 529         vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
 530 #ifdef DEBUG_MMU
 531         printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
 532 #endif
 533         ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
 534         return ret;
 535     }
 536     // XXX
 537     return 1;
 538 }
 539
 540 #ifdef DEBUG_MMU
 541 void dump_mmu(CPUState *env)
 542 {
 543     unsigned int i;
 544     const char *mask;
 545
 546     printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]);
 547     if ((env->lsu & DMMU_E) == 0) {
 548         printf("DMMU disabled\n");
 549     } else {
 550         printf("DMMU dump:\n");
 551         for (i = 0; i < 64; i++) {
 552             switch ((env->dtlb_tte[i] >> 61) & 3) {
 553             default:
 554             case 0x0:
 555                 mask = "  8k";
 556                 break;
 557             case 0x1:
 558                 mask = " 64k";
 559                 break;
 560             case 0x2:
 561                 mask = "512k";
 562                 break;
 563             case 0x3:
 564                 mask = "  4M";
 565                 break;
 566             }
 567             if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
 568                 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
 569                        env->dtlb_tag[i] & ~0x1fffULL,
 570                        env->dtlb_tte[i] & 0x1ffffffe000ULL,
 571                        mask,
 572                        env->dtlb_tte[i] & 0x4? "priv": "user",
 573                        env->dtlb_tte[i] & 0x2? "RW": "RO",
 574                        env->dtlb_tte[i] & 0x40? "locked": "unlocked",
 575                        env->dtlb_tag[i] & 0x1fffULL);
 576             }
 577         }
 578     }
 579     if ((env->lsu & IMMU_E) == 0) {
 580         printf("IMMU disabled\n");
 581     } else {
 582         printf("IMMU dump:\n");
 583         for (i = 0; i < 64; i++) {
 584             switch ((env->itlb_tte[i] >> 61) & 3) {
 585             default:
 586             case 0x0:
 587                 mask = "  8k";
 588                 break;
 589             case 0x1:
 590                 mask = " 64k";
 591                 break;
 592             case 0x2:
 593                 mask = "512k";
 594                 break;
 595             case 0x3:
 596                 mask = "  4M";
 597                 break;
 598             }
 599             if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
 600                 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
 601                        env->itlb_tag[i] & ~0x1fffULL,
 602                        env->itlb_tte[i] & 0x1ffffffe000ULL,
 603                        mask,
 604                        env->itlb_tte[i] & 0x4? "priv": "user",
 605                        env->itlb_tte[i] & 0x40? "locked": "unlocked",
 606                        env->itlb_tag[i] & 0x1fffULL);
 607             }
 608         }
 609     }
 610 }
 611 #endif /* DEBUG_MMU */
 612
 613 #endif /* TARGET_SPARC64 */
 614 #endif /* !CONFIG_USER_ONLY */
 615
 616
 617 #if defined(CONFIG_USER_ONLY)
 618 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 619 {
 620     return addr;
 621 }
 622
 623 #else
 624 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 625 {
 626     target_phys_addr_t phys_addr;
 627     int prot, access_index;
 628
 629     if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
 630                              MMU_KERNEL_IDX) != 0)
 631         if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
 632                                  0, MMU_KERNEL_IDX) != 0)
 633             return -1;
 634     if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
 635         return -1;
 636     return phys_addr;
 637 }
 638 #endif
 639
 640 void memcpy32(target_ulong *dst, const target_ulong *src)
 641 {
 642     dst[0] = src[0];
 643     dst[1] = src[1];
 644     dst[2] = src[2];
 645     dst[3] = src[3];
 646     dst[4] = src[4];
 647     dst[5] = src[5];
 648     dst[6] = src[6];
 649     dst[7] = src[7];
 650 }
 651
 652 void helper_flush(target_ulong addr)
 653 {
 654     addr &= ~7;
 655     tb_invalidate_page_range(addr, addr + 8);
 656 }
 657
 658 void cpu_reset(CPUSPARCState *env)
 659 {
 660     tlb_flush(env, 1);
 661     env->cwp = 0;
 662     env->wim = 1;
 663     env->regwptr = env->regbase + (env->cwp * 16);
 664 #if defined(CONFIG_USER_ONLY)
 665     env->user_mode_only = 1;
 666 #ifdef TARGET_SPARC64
 667     env->cleanwin = NWINDOWS - 2;
 668     env->cansave = NWINDOWS - 2;
 669     env->pstate = PS_RMO | PS_PEF | PS_IE;
 670     env->asi = 0x82; // Primary no-fault
 671 #endif
 672 #else
 673     env->psret = 0;
 674     env->psrs = 1;
 675     env->psrps = 1;
 676 #ifdef TARGET_SPARC64
 677     env->pstate = PS_PRIV;
 678     env->hpstate = HS_PRIV;
 679     env->pc = 0x1fff0000000ULL;
 680     env->tsptr = &env->ts[env->tl];
 681 #else
 682     env->pc = 0;
 683     env->mmuregs[0] &= ~(MMU_E | MMU_NF);
 684     env->mmuregs[0] |= env->mmu_bm;
 685 #endif
 686     env->npc = env->pc + 4;
 687 #endif
 688 }
 689
 690 static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
 691 {
 692     sparc_def_t def1, *def = &def1;
 693
 694     if (cpu_sparc_find_by_name(def, cpu_model) < 0)
 695         return -1;
 696
 697     env->features = def->features;
 698     env->cpu_model_str = cpu_model;
 699     env->version = def->iu_version;
 700     env->fsr = def->fpu_version;
 701 #if !defined(TARGET_SPARC64)
 702     env->mmu_bm = def->mmu_bm;
 703     env->mmu_ctpr_mask = def->mmu_ctpr_mask;
 704     env->mmu_cxr_mask = def->mmu_cxr_mask;
 705     env->mmu_sfsr_mask = def->mmu_sfsr_mask;
 706     env->mmu_trcr_mask = def->mmu_trcr_mask;
 707     env->mmuregs[0] |= def->mmu_version;
 708     cpu_sparc_set_id(env, 0);
 709 #endif
 710     return 0;
 711 }
 712
 713 static void cpu_sparc_close(CPUSPARCState *env)
 714 {
 715     free(env);
 716 }
 717
 718 CPUSPARCState *cpu_sparc_init(const char *cpu_model)
 719 {
 720     CPUSPARCState *env;
 721
 722     env = qemu_mallocz(sizeof(CPUSPARCState));
 723     if (!env)
 724         return NULL;
 725     cpu_exec_init(env);
 726
 727     gen_intermediate_code_init(env);
 728
 729     if (cpu_sparc_register(env, cpu_model) < 0) {
 730         cpu_sparc_close(env);
 731         return NULL;
 732     }
 733     cpu_reset(env);
 734
 735     return env;
 736 }
 737
 738 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
 739 {
 740 #if !defined(TARGET_SPARC64)
 741     env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
 742 #endif
 743 }
 744
 745 static const sparc_def_t sparc_defs[] = {
 746 #ifdef TARGET_SPARC64
 747     {
 748         .name = "Fujitsu Sparc64",
 749         .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)
 750                        | (MAXTL << 8) | (NWINDOWS - 1)),
 751         .fpu_version = 0x00000000,
 752         .mmu_version = 0,
 753         .features = CPU_DEFAULT_FEATURES,
 754     },
 755     {
 756         .name = "Fujitsu Sparc64 III",
 757         .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)
 758                        | (MAXTL << 8) | (NWINDOWS - 1)),
 759         .fpu_version = 0x00000000,
 760         .mmu_version = 0,
 761         .features = CPU_DEFAULT_FEATURES,
 762     },
 763     {
 764         .name = "Fujitsu Sparc64 IV",
 765         .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)
 766                        | (MAXTL << 8) | (NWINDOWS - 1)),
 767         .fpu_version = 0x00000000,
 768         .mmu_version = 0,
 769         .features = CPU_DEFAULT_FEATURES,
 770     },
 771     {
 772         .name = "Fujitsu Sparc64 V",
 773         .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)
 774                        | (MAXTL << 8) | (NWINDOWS - 1)),
 775         .fpu_version = 0x00000000,
 776         .mmu_version = 0,
 777         .features = CPU_DEFAULT_FEATURES,
 778     },
 779     {
 780         .name = "TI UltraSparc I",
 781         .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
 782                        | (MAXTL << 8) | (NWINDOWS - 1)),
 783         .fpu_version = 0x00000000,
 784         .mmu_version = 0,
 785         .features = CPU_DEFAULT_FEATURES,
 786     },
 787     {
 788         .name = "TI UltraSparc II",
 789         .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)
 790                        | (MAXTL << 8) | (NWINDOWS - 1)),
 791         .fpu_version = 0x00000000,
 792         .mmu_version = 0,
 793         .features = CPU_DEFAULT_FEATURES,
 794     },
 795     {
 796         .name = "TI UltraSparc IIi",
 797         .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)
 798                        | (MAXTL << 8) | (NWINDOWS - 1)),
 799         .fpu_version = 0x00000000,
 800         .mmu_version = 0,
 801         .features = CPU_DEFAULT_FEATURES,
 802     },
 803     {
 804         .name = "TI UltraSparc IIe",
 805         .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)
 806                        | (MAXTL << 8) | (NWINDOWS - 1)),
 807         .fpu_version = 0x00000000,
 808         .mmu_version = 0,
 809         .features = CPU_DEFAULT_FEATURES,
 810     },
 811     {
 812         .name = "Sun UltraSparc III",
 813         .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)
 814                        | (MAXTL << 8) | (NWINDOWS - 1)),
 815         .fpu_version = 0x00000000,
 816         .mmu_version = 0,
 817         .features = CPU_DEFAULT_FEATURES,
 818     },
 819     {
 820         .name = "Sun UltraSparc III Cu",
 821         .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)
 822                        | (MAXTL << 8) | (NWINDOWS - 1)),
 823         .fpu_version = 0x00000000,
 824         .mmu_version = 0,
 825         .features = CPU_DEFAULT_FEATURES,
 826     },
 827     {
 828         .name = "Sun UltraSparc IIIi",
 829         .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)
 830                        | (MAXTL << 8) | (NWINDOWS - 1)),
 831         .fpu_version = 0x00000000,
 832         .mmu_version = 0,
 833         .features = CPU_DEFAULT_FEATURES,
 834     },
 835     {
 836         .name = "Sun UltraSparc IV",
 837         .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)
 838                        | (MAXTL << 8) | (NWINDOWS - 1)),
 839         .fpu_version = 0x00000000,
 840         .mmu_version = 0,
 841         .features = CPU_DEFAULT_FEATURES,
 842     },
 843     {
 844         .name = "Sun UltraSparc IV+",
 845         .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)
 846                        | (MAXTL << 8) | (NWINDOWS - 1)),
 847         .fpu_version = 0x00000000,
 848         .mmu_version = 0,
 849         .features = CPU_DEFAULT_FEATURES,
 850     },
 851     {
 852         .name = "Sun UltraSparc IIIi+",
 853         .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)
 854                        | (MAXTL << 8) | (NWINDOWS - 1)),
 855         .fpu_version = 0x00000000,
 856         .mmu_version = 0,
 857         .features = CPU_DEFAULT_FEATURES,
 858     },
 859     {
 860         .name = "NEC UltraSparc I",
 861         .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
 862                        | (MAXTL << 8) | (NWINDOWS - 1)),
 863         .fpu_version = 0x00000000,
 864         .mmu_version = 0,
 865         .features = CPU_DEFAULT_FEATURES,
 866     },
 867 #else
 868     {
 869         .name = "Fujitsu MB86900",
 870         .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
 871         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
 872         .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
 873         .mmu_bm = 0x00004000,
 874         .mmu_ctpr_mask = 0x007ffff0,
 875         .mmu_cxr_mask = 0x0000003f,
 876         .mmu_sfsr_mask = 0xffffffff,
 877         .mmu_trcr_mask = 0xffffffff,
 878         .features = CPU_FEATURE_FLOAT,
 879     },
 880     {
 881         .name = "Fujitsu MB86904",
 882         .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
 883         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
 884         .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
 885         .mmu_bm = 0x00004000,
 886         .mmu_ctpr_mask = 0x00ffffc0,
 887         .mmu_cxr_mask = 0x000000ff,
 888         .mmu_sfsr_mask = 0x00016fff,
 889         .mmu_trcr_mask = 0x00ffffff,
 890         .features = CPU_DEFAULT_FEATURES,
 891     },
 892     {
 893         .name = "Fujitsu MB86907",
 894         .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
 895         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
 896         .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
 897         .mmu_bm = 0x00004000,
 898         .mmu_ctpr_mask = 0xffffffc0,
 899         .mmu_cxr_mask = 0x000000ff,
 900         .mmu_sfsr_mask = 0x00016fff,
 901         .mmu_trcr_mask = 0xffffffff,
 902         .features = CPU_DEFAULT_FEATURES,
 903     },
 904     {
 905         .name = "LSI L64811",
 906         .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
 907         .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
 908         .mmu_version = 0x10 << 24,
 909         .mmu_bm = 0x00004000,
 910         .mmu_ctpr_mask = 0x007ffff0,
 911         .mmu_cxr_mask = 0x0000003f,
 912         .mmu_sfsr_mask = 0xffffffff,
 913         .mmu_trcr_mask = 0xffffffff,
 914         .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT,
 915     },
 916     {
 917         .name = "Cypress CY7C601",
 918         .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
 919         .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
 920         .mmu_version = 0x10 << 24,
 921         .mmu_bm = 0x00004000,
 922         .mmu_ctpr_mask = 0x007ffff0,
 923         .mmu_cxr_mask = 0x0000003f,
 924         .mmu_sfsr_mask = 0xffffffff,
 925         .mmu_trcr_mask = 0xffffffff,
 926         .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT,
 927     },
 928     {
 929         .name = "Cypress CY7C611",
 930         .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
 931         .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
 932         .mmu_version = 0x10 << 24,
 933         .mmu_bm = 0x00004000,
 934         .mmu_ctpr_mask = 0x007ffff0,
 935         .mmu_cxr_mask = 0x0000003f,
 936         .mmu_sfsr_mask = 0xffffffff,
 937         .mmu_trcr_mask = 0xffffffff,
 938         .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT,
 939     },
 940     {
 941         .name = "TI SuperSparc II",
 942         .iu_version = 0x40000000,
 943         .fpu_version = 0 << 17,
 944         .mmu_version = 0x04000000,
 945         .mmu_bm = 0x00002000,
 946         .mmu_ctpr_mask = 0xffffffc0,
 947         .mmu_cxr_mask = 0x0000ffff,
 948         .mmu_sfsr_mask = 0xffffffff,
 949         .mmu_trcr_mask = 0xffffffff,
 950         .features = CPU_DEFAULT_FEATURES,
 951     },
 952     {
 953         .name = "TI MicroSparc I",
 954         .iu_version = 0x41000000,
 955         .fpu_version = 4 << 17,
 956         .mmu_version = 0x41000000,
 957         .mmu_bm = 0x00004000,
 958         .mmu_ctpr_mask = 0x007ffff0,
 959         .mmu_cxr_mask = 0x0000003f,
 960         .mmu_sfsr_mask = 0x00016fff,
 961         .mmu_trcr_mask = 0x0000003f,
 962         .features = CPU_DEFAULT_FEATURES,
 963     },
 964     {
 965         .name = "TI MicroSparc II",
 966         .iu_version = 0x42000000,
 967         .fpu_version = 4 << 17,
 968         .mmu_version = 0x02000000,
 969         .mmu_bm = 0x00004000,
 970         .mmu_ctpr_mask = 0x00ffffc0,
 971         .mmu_cxr_mask = 0x000000ff,
 972         .mmu_sfsr_mask = 0x00016fff,
 973         .mmu_trcr_mask = 0x00ffffff,
 974         .features = CPU_DEFAULT_FEATURES,
 975     },
 976     {
 977         .name = "TI MicroSparc IIep",
 978         .iu_version = 0x42000000,
 979         .fpu_version = 4 << 17,
 980         .mmu_version = 0x04000000,
 981         .mmu_bm = 0x00004000,
 982         .mmu_ctpr_mask = 0x00ffffc0,
 983         .mmu_cxr_mask = 0x000000ff,
 984         .mmu_sfsr_mask = 0x00016bff,
 985         .mmu_trcr_mask = 0x00ffffff,
 986         .features = CPU_DEFAULT_FEATURES,
 987     },
 988     {
 989         .name = "TI SuperSparc 51",
 990         .iu_version = 0x43000000,
 991         .fpu_version = 0 << 17,
 992         .mmu_version = 0x04000000,
 993         .mmu_bm = 0x00002000,
 994         .mmu_ctpr_mask = 0xffffffc0,
 995         .mmu_cxr_mask = 0x0000ffff,
 996         .mmu_sfsr_mask = 0xffffffff,
 997         .mmu_trcr_mask = 0xffffffff,
 998         .features = CPU_DEFAULT_FEATURES,
 999     },
1000     {
1001         .name = "TI SuperSparc 61",
1002         .iu_version = 0x44000000,
1003         .fpu_version = 0 << 17,
1004         .mmu_version = 0x04000000,
1005         .mmu_bm = 0x00002000,
1006         .mmu_ctpr_mask = 0xffffffc0,
1007         .mmu_cxr_mask = 0x0000ffff,
1008         .mmu_sfsr_mask = 0xffffffff,
1009         .mmu_trcr_mask = 0xffffffff,
1010         .features = CPU_DEFAULT_FEATURES,
1011     },
1012     {
1013         .name = "Ross RT625",
1014         .iu_version = 0x1e000000,
1015         .fpu_version = 1 << 17,
1016         .mmu_version = 0x1e000000,
1017         .mmu_bm = 0x00004000,
1018         .mmu_ctpr_mask = 0x007ffff0,
1019         .mmu_cxr_mask = 0x0000003f,
1020         .mmu_sfsr_mask = 0xffffffff,
1021         .mmu_trcr_mask = 0xffffffff,
1022         .features = CPU_DEFAULT_FEATURES,
1023     },
1024     {
1025         .name = "Ross RT620",
1026         .iu_version = 0x1f000000,
1027         .fpu_version = 1 << 17,
1028         .mmu_version = 0x1f000000,
1029         .mmu_bm = 0x00004000,
1030         .mmu_ctpr_mask = 0x007ffff0,
1031         .mmu_cxr_mask = 0x0000003f,
1032         .mmu_sfsr_mask = 0xffffffff,
1033         .mmu_trcr_mask = 0xffffffff,
1034         .features = CPU_DEFAULT_FEATURES,
1035     },
1036     {
1037         .name = "BIT B5010",
1038         .iu_version = 0x20000000,
1039         .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
1040         .mmu_version = 0x20000000,
1041         .mmu_bm = 0x00004000,
1042         .mmu_ctpr_mask = 0x007ffff0,
1043         .mmu_cxr_mask = 0x0000003f,
1044         .mmu_sfsr_mask = 0xffffffff,
1045         .mmu_trcr_mask = 0xffffffff,
1046         .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT,
1047     },
1048     {
1049         .name = "Matsushita MN10501",
1050         .iu_version = 0x50000000,
1051         .fpu_version = 0 << 17,
1052         .mmu_version = 0x50000000,
1053         .mmu_bm = 0x00004000,
1054         .mmu_ctpr_mask = 0x007ffff0,
1055         .mmu_cxr_mask = 0x0000003f,
1056         .mmu_sfsr_mask = 0xffffffff,
1057         .mmu_trcr_mask = 0xffffffff,
1058         .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT,
1059     },
1060     {
1061         .name = "Weitek W8601",
1062         .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
1063         .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
1064         .mmu_version = 0x10 << 24,
1065         .mmu_bm = 0x00004000,
1066         .mmu_ctpr_mask = 0x007ffff0,
1067         .mmu_cxr_mask = 0x0000003f,
1068         .mmu_sfsr_mask = 0xffffffff,
1069         .mmu_trcr_mask = 0xffffffff,
1070         .features = CPU_DEFAULT_FEATURES,
1071     },
1072     {
1073         .name = "LEON2",
1074         .iu_version = 0xf2000000,
1075         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1076         .mmu_version = 0xf2000000,
1077         .mmu_bm = 0x00004000,
1078         .mmu_ctpr_mask = 0x007ffff0,
1079         .mmu_cxr_mask = 0x0000003f,
1080         .mmu_sfsr_mask = 0xffffffff,
1081         .mmu_trcr_mask = 0xffffffff,
1082         .features = CPU_DEFAULT_FEATURES,
1083     },
1084     {
1085         .name = "LEON3",
1086         .iu_version = 0xf3000000,
1087         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1088         .mmu_version = 0xf3000000,
1089         .mmu_bm = 0x00004000,
1090         .mmu_ctpr_mask = 0x007ffff0,
1091         .mmu_cxr_mask = 0x0000003f,
1092         .mmu_sfsr_mask = 0xffffffff,
1093         .mmu_trcr_mask = 0xffffffff,
1094         .features = CPU_DEFAULT_FEATURES,
1095     },
1096 #endif
1097 };
1098
1099 static const char * const feature_name[] = {
1100     "float",
1101     "float128",
1102     "swap",
1103     "mul",
1104     "div",
1105     "flush",
1106     "fsqrt",
1107     "fmul",
1108     "vis1",
1109     "vis2",
1110 };
1111
1112 static void print_features(FILE *f,
1113                            int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1114                            uint32_t features, const char *prefix)
1115 {
1116     unsigned int i;
1117
1118     for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1119         if (feature_name[i] && (features & (1 << i))) {
1120             if (prefix)
1121                 (*cpu_fprintf)(f, "%s", prefix);
1122             (*cpu_fprintf)(f, "%s ", feature_name[i]);
1123         }
1124 }
1125
1126 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
1127 {
1128     unsigned int i;
1129
1130     for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1131         if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
1132             *features |= 1 << i;
1133             return;
1134         }
1135     fprintf(stderr, "CPU feature %s not found\n", flagname);
1136 }
1137
1138 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model)
1139 {
1140     unsigned int i;
1141     const sparc_def_t *def = NULL;
1142     char *s = strdup(cpu_model);
1143     char *featurestr, *name = strtok(s, ",");
1144     uint32_t plus_features = 0;
1145     uint32_t minus_features = 0;
1146     long long iu_version;
1147     uint32_t fpu_version, mmu_version;
1148
1149     for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
1150         if (strcasecmp(name, sparc_defs[i].name) == 0) {
1151             def = &sparc_defs[i];
1152         }
1153     }
1154     if (!def)
1155         goto error;
1156     memcpy(cpu_def, def, sizeof(*def));
1157
1158     featurestr = strtok(NULL, ",");
1159     while (featurestr) {
1160         char *val;
1161
1162         if (featurestr[0] == '+') {
1163             add_flagname_to_bitmaps(featurestr + 1, &plus_features);
1164         } else if (featurestr[0] == '-') {
1165             add_flagname_to_bitmaps(featurestr + 1, &minus_features);
1166         } else if ((val = strchr(featurestr, '='))) {
1167             *val = 0; val++;
1168             if (!strcmp(featurestr, "iu_version")) {
1169                 char *err;
1170
1171                 iu_version = strtoll(val, &err, 0);
1172                 if (!*val || *err) {
1173                     fprintf(stderr, "bad numerical value %s\n", val);
1174                     goto error;
1175                 }
1176                 cpu_def->iu_version = iu_version;
1177 #ifdef DEBUG_FEATURES
1178                 fprintf(stderr, "iu_version %llx\n", iu_version);
1179 #endif
1180             } else if (!strcmp(featurestr, "fpu_version")) {
1181                 char *err;
1182
1183                 fpu_version = strtol(val, &err, 0);
1184                 if (!*val || *err) {
1185                     fprintf(stderr, "bad numerical value %s\n", val);
1186                     goto error;
1187                 }
1188                 cpu_def->fpu_version = fpu_version;
1189 #ifdef DEBUG_FEATURES
1190                 fprintf(stderr, "fpu_version %llx\n", fpu_version);
1191 #endif
1192             } else if (!strcmp(featurestr, "mmu_version")) {
1193                 char *err;
1194
1195                 mmu_version = strtol(val, &err, 0);
1196                 if (!*val || *err) {
1197                     fprintf(stderr, "bad numerical value %s\n", val);
1198                     goto error;
1199                 }
1200                 cpu_def->mmu_version = mmu_version;
1201 #ifdef DEBUG_FEATURES
1202                 fprintf(stderr, "mmu_version %llx\n", mmu_version);
1203 #endif
1204             } else {
1205                 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1206                 goto error;
1207             }
1208         } else {
1209             fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1210             goto error;
1211         }
1212         featurestr = strtok(NULL, ",");
1213     }
1214     cpu_def->features |= plus_features;
1215     cpu_def->features &= ~minus_features;
1216 #ifdef DEBUG_FEATURES
1217     print_features(stderr, fprintf, cpu_def->features, NULL);
1218 #endif
1219     free(s);
1220     return 0;
1221
1222  error:
1223     free(s);
1224     return -1;
1225 }
1226
1227 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
1228 {
1229     unsigned int i;
1230
1231     for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
1232         (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x ",
1233                        sparc_defs[i].name,
1234                        sparc_defs[i].iu_version,
1235                        sparc_defs[i].fpu_version,
1236                        sparc_defs[i].mmu_version);
1237         print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES & ~sparc_defs[i].features, "-");
1238         print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES & sparc_defs[i].features, "+");
1239         (*cpu_fprintf)(f, "\n");
1240     }
1241     (*cpu_fprintf)(f, "CPU feature flags (+/-): ");
1242     print_features(f, cpu_fprintf, -1, NULL);
1243     (*cpu_fprintf)(f, "\n");
1244     (*cpu_fprintf)(f, "Numerical features (=): iu_version fpu_version mmu_version\n");
1245 }
1246
1247 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
1248
1249 void cpu_dump_state(CPUState *env, FILE *f,
1250                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1251                     int flags)
1252 {
1253     int i, x;
1254
1255     cpu_fprintf(f, "pc: " TARGET_FMT_lx "  npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
1256     cpu_fprintf(f, "General Registers:\n");
1257     for (i = 0; i < 4; i++)
1258         cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1259     cpu_fprintf(f, "\n");
1260     for (; i < 8; i++)
1261         cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1262     cpu_fprintf(f, "\nCurrent Register Window:\n");
1263     for (x = 0; x < 3; x++) {
1264         for (i = 0; i < 4; i++)
1265             cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1266                     (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
1267                     env->regwptr[i + x * 8]);
1268         cpu_fprintf(f, "\n");
1269         for (; i < 8; i++)
1270             cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1271                     (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
1272                     env->regwptr[i + x * 8]);
1273         cpu_fprintf(f, "\n");
1274     }
1275     cpu_fprintf(f, "\nFloating Point Registers:\n");
1276     for (i = 0; i < 32; i++) {
1277         if ((i & 3) == 0)
1278             cpu_fprintf(f, "%%f%02d:", i);
1279         cpu_fprintf(f, " %016lf", env->fpr[i]);
1280         if ((i & 3) == 3)
1281             cpu_fprintf(f, "\n");
1282     }
1283 #ifdef TARGET_SPARC64
1284     cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
1285                 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
1286     cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
1287                 env->cansave, env->canrestore, env->otherwin, env->wstate,
1288                 env->cleanwin, NWINDOWS - 1 - env->cwp);
1289 #else
1290     cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
1291             GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
1292             GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
1293             env->psrs?'S':'-', env->psrps?'P':'-',
1294             env->psret?'E':'-', env->wim);
1295 #endif
1296     cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
1297 }
1298
1299 #ifdef TARGET_SPARC64
1300 #if !defined(CONFIG_USER_ONLY)
1301 #include "qemu-common.h"
1302 #include "hw/irq.h"
1303 #include "qemu-timer.h"
1304 #endif
1305
1306 void helper_tick_set_count(void *opaque, uint64_t count)
1307 {
1308 #if !defined(CONFIG_USER_ONLY)
1309     ptimer_set_count(opaque, -count);
1310 #endif
1311 }
1312
1313 uint64_t helper_tick_get_count(void *opaque)
1314 {
1315 #if !defined(CONFIG_USER_ONLY)
1316     return -ptimer_get_count(opaque);
1317 #else
1318     return 0;
1319 #endif
1320 }
1321
1322 void helper_tick_set_limit(void *opaque, uint64_t limit)
1323 {
1324 #if !defined(CONFIG_USER_ONLY)
1325     ptimer_set_limit(opaque, -limit, 0);
1326 #endif
1327 }
1328 #endif