target-sparc/int32_helper.c

   1 /*
   2  * Sparc32 interrupt helpers
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21
  22 //#define DEBUG_PCALL
  23 //#define DEBUG_CACHE_CONTROL
  24
  25 #ifdef DEBUG_CACHE_CONTROL
  26 #define DPRINTF_CACHE_CONTROL(fmt, ...)                                 \
  27     do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
  28 #else
  29 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
  30 #endif
  31
  32 #ifdef DEBUG_PCALL
  33 static const char * const excp_names[0x80] = {
  34     [TT_TFAULT] = "Instruction Access Fault",
  35     [TT_ILL_INSN] = "Illegal Instruction",
  36     [TT_PRIV_INSN] = "Privileged Instruction",
  37     [TT_NFPU_INSN] = "FPU Disabled",
  38     [TT_WIN_OVF] = "Window Overflow",
  39     [TT_WIN_UNF] = "Window Underflow",
  40     [TT_UNALIGNED] = "Unaligned Memory Access",
  41     [TT_FP_EXCP] = "FPU Exception",
  42     [TT_DFAULT] = "Data Access Fault",
  43     [TT_TOVF] = "Tag Overflow",
  44     [TT_EXTINT | 0x1] = "External Interrupt 1",
  45     [TT_EXTINT | 0x2] = "External Interrupt 2",
  46     [TT_EXTINT | 0x3] = "External Interrupt 3",
  47     [TT_EXTINT | 0x4] = "External Interrupt 4",
  48     [TT_EXTINT | 0x5] = "External Interrupt 5",
  49     [TT_EXTINT | 0x6] = "External Interrupt 6",
  50     [TT_EXTINT | 0x7] = "External Interrupt 7",
  51     [TT_EXTINT | 0x8] = "External Interrupt 8",
  52     [TT_EXTINT | 0x9] = "External Interrupt 9",
  53     [TT_EXTINT | 0xa] = "External Interrupt 10",
  54     [TT_EXTINT | 0xb] = "External Interrupt 11",
  55     [TT_EXTINT | 0xc] = "External Interrupt 12",
  56     [TT_EXTINT | 0xd] = "External Interrupt 13",
  57     [TT_EXTINT | 0xe] = "External Interrupt 14",
  58     [TT_EXTINT | 0xf] = "External Interrupt 15",
  59     [TT_TOVF] = "Tag Overflow",
  60     [TT_CODE_ACCESS] = "Instruction Access Error",
  61     [TT_DATA_ACCESS] = "Data Access Error",
  62     [TT_DIV_ZERO] = "Division By Zero",
  63     [TT_NCP_INSN] = "Coprocessor Disabled",
  64 };
  65 #endif
  66
  67 void do_interrupt(CPUState *env)
  68 {
  69     int cwp, intno = env->exception_index;
  70
  71 #ifdef DEBUG_PCALL
  72     if (qemu_loglevel_mask(CPU_LOG_INT)) {
  73         static int count;
  74         const char *name;
  75
  76         if (intno < 0 || intno >= 0x100) {
  77             name = "Unknown";
  78         } else if (intno >= 0x80) {
  79             name = "Trap Instruction";
  80         } else {
  81             name = excp_names[intno];
  82             if (!name) {
  83                 name = "Unknown";
  84             }
  85         }
  86
  87         qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
  88                 count, name, intno,
  89                 env->pc,
  90                 env->npc, env->regwptr[6]);
  91         log_cpu_state(env, 0);
  92 #if 0
  93         {
  94             int i;
  95             uint8_t *ptr;
  96
  97             qemu_log("       code=");
  98             ptr = (uint8_t *)env->pc;
  99             for (i = 0; i < 16; i++) {
 100                 qemu_log(" %02x", ldub(ptr + i));
 101             }
 102             qemu_log("\n");
 103         }
 104 #endif
 105         count++;
 106     }
 107 #endif
 108 #if !defined(CONFIG_USER_ONLY)
 109     if (env->psret == 0) {
 110         cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
 111                   env->exception_index);
 112         return;
 113     }
 114 #endif
 115     env->psret = 0;
 116     cwp = cpu_cwp_dec(env, env->cwp - 1);
 117     cpu_set_cwp(env, cwp);
 118     env->regwptr[9] = env->pc;
 119     env->regwptr[10] = env->npc;
 120     env->psrps = env->psrs;
 121     env->psrs = 1;
 122     env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
 123     env->pc = env->tbr;
 124     env->npc = env->pc + 4;
 125     env->exception_index = -1;
 126
 127 #if !defined(CONFIG_USER_ONLY)
 128     /* IRQ acknowledgment */
 129     if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) {
 130         env->qemu_irq_ack(env, env->irq_manager, intno);
 131     }
 132 #endif
 133 }
 134
 135 #if !defined(CONFIG_USER_ONLY)
 136 static void leon3_cache_control_int(CPUState *env)
 137 {
 138     uint32_t state = 0;
 139
 140     if (env->cache_control & CACHE_CTRL_IF) {
 141         /* Instruction cache state */
 142         state = env->cache_control & CACHE_STATE_MASK;
 143         if (state == CACHE_ENABLED) {
 144             state = CACHE_FROZEN;
 145             DPRINTF_CACHE_CONTROL("Instruction cache: freeze\n");
 146         }
 147
 148         env->cache_control &= ~CACHE_STATE_MASK;
 149         env->cache_control |= state;
 150     }
 151
 152     if (env->cache_control & CACHE_CTRL_DF) {
 153         /* Data cache state */
 154         state = (env->cache_control >> 2) & CACHE_STATE_MASK;
 155         if (state == CACHE_ENABLED) {
 156             state = CACHE_FROZEN;
 157             DPRINTF_CACHE_CONTROL("Data cache: freeze\n");
 158         }
 159
 160         env->cache_control &= ~(CACHE_STATE_MASK << 2);
 161         env->cache_control |= (state << 2);
 162     }
 163 }
 164
 165 void leon3_irq_manager(CPUState *env, void *irq_manager, int intno)
 166 {
 167     leon3_irq_ack(irq_manager, intno);
 168     leon3_cache_control_int(env);
 169 }
 170 #endif