target-sparc/int64_helper.c

   1 /*
   2  * Sparc64 interrupt helpers
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "helper.h"
  22
  23 //#define DEBUG_PCALL
  24 //#define DEBUG_PSTATE
  25
  26 #ifdef DEBUG_PSTATE
  27 #define DPRINTF_PSTATE(fmt, ...)                                \
  28     do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
  29 #else
  30 #define DPRINTF_PSTATE(fmt, ...) do {} while (0)
  31 #endif
  32
  33 #ifdef DEBUG_PCALL
  34 static const char * const excp_names[0x80] = {
  35     [TT_TFAULT] = "Instruction Access Fault",
  36     [TT_TMISS] = "Instruction Access MMU Miss",
  37     [TT_CODE_ACCESS] = "Instruction Access Error",
  38     [TT_ILL_INSN] = "Illegal Instruction",
  39     [TT_PRIV_INSN] = "Privileged Instruction",
  40     [TT_NFPU_INSN] = "FPU Disabled",
  41     [TT_FP_EXCP] = "FPU Exception",
  42     [TT_TOVF] = "Tag Overflow",
  43     [TT_CLRWIN] = "Clean Windows",
  44     [TT_DIV_ZERO] = "Division By Zero",
  45     [TT_DFAULT] = "Data Access Fault",
  46     [TT_DMISS] = "Data Access MMU Miss",
  47     [TT_DATA_ACCESS] = "Data Access Error",
  48     [TT_DPROT] = "Data Protection Error",
  49     [TT_UNALIGNED] = "Unaligned Memory Access",
  50     [TT_PRIV_ACT] = "Privileged Action",
  51     [TT_EXTINT | 0x1] = "External Interrupt 1",
  52     [TT_EXTINT | 0x2] = "External Interrupt 2",
  53     [TT_EXTINT | 0x3] = "External Interrupt 3",
  54     [TT_EXTINT | 0x4] = "External Interrupt 4",
  55     [TT_EXTINT | 0x5] = "External Interrupt 5",
  56     [TT_EXTINT | 0x6] = "External Interrupt 6",
  57     [TT_EXTINT | 0x7] = "External Interrupt 7",
  58     [TT_EXTINT | 0x8] = "External Interrupt 8",
  59     [TT_EXTINT | 0x9] = "External Interrupt 9",
  60     [TT_EXTINT | 0xa] = "External Interrupt 10",
  61     [TT_EXTINT | 0xb] = "External Interrupt 11",
  62     [TT_EXTINT | 0xc] = "External Interrupt 12",
  63     [TT_EXTINT | 0xd] = "External Interrupt 13",
  64     [TT_EXTINT | 0xe] = "External Interrupt 14",
  65     [TT_EXTINT | 0xf] = "External Interrupt 15",
  66 };
  67 #endif
  68
  69 void do_interrupt(CPUState *env)
  70 {
  71     int intno = env->exception_index;
  72     trap_state *tsptr;
  73
  74 #ifdef DEBUG_PCALL
  75     if (qemu_loglevel_mask(CPU_LOG_INT)) {
  76         static int count;
  77         const char *name;
  78
  79         if (intno < 0 || intno >= 0x180) {
  80             name = "Unknown";
  81         } else if (intno >= 0x100) {
  82             name = "Trap Instruction";
  83         } else if (intno >= 0xc0) {
  84             name = "Window Fill";
  85         } else if (intno >= 0x80) {
  86             name = "Window Spill";
  87         } else {
  88             name = excp_names[intno];
  89             if (!name) {
  90                 name = "Unknown";
  91             }
  92         }
  93
  94         qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
  95                 " SP=%016" PRIx64 "\n",
  96                 count, name, intno,
  97                 env->pc,
  98                 env->npc, env->regwptr[6]);
  99         log_cpu_state(env, 0);
 100 #if 0
 101         {
 102             int i;
 103             uint8_t *ptr;
 104
 105             qemu_log("       code=");
 106             ptr = (uint8_t *)env->pc;
 107             for (i = 0; i < 16; i++) {
 108                 qemu_log(" %02x", ldub(ptr + i));
 109             }
 110             qemu_log("\n");
 111         }
 112 #endif
 113         count++;
 114     }
 115 #endif
 116 #if !defined(CONFIG_USER_ONLY)
 117     if (env->tl >= env->maxtl) {
 118         cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
 119                   " Error state", env->exception_index, env->tl, env->maxtl);
 120         return;
 121     }
 122 #endif
 123     if (env->tl < env->maxtl - 1) {
 124         env->tl++;
 125     } else {
 126         env->pstate |= PS_RED;
 127         if (env->tl < env->maxtl) {
 128             env->tl++;
 129         }
 130     }
 131     tsptr = cpu_tsptr(env);
 132
 133     tsptr->tstate = (cpu_get_ccr(env) << 32) |
 134         ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
 135         cpu_get_cwp64(env);
 136     tsptr->tpc = env->pc;
 137     tsptr->tnpc = env->npc;
 138     tsptr->tt = intno;
 139
 140     switch (intno) {
 141     case TT_IVEC:
 142         cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_IG);
 143         break;
 144     case TT_TFAULT:
 145     case TT_DFAULT:
 146     case TT_TMISS ... TT_TMISS + 3:
 147     case TT_DMISS ... TT_DMISS + 3:
 148     case TT_DPROT ... TT_DPROT + 3:
 149         cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_MG);
 150         break;
 151     default:
 152         cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_AG);
 153         break;
 154     }
 155
 156     if (intno == TT_CLRWIN) {
 157         cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
 158     } else if ((intno & 0x1c0) == TT_SPILL) {
 159         cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
 160     } else if ((intno & 0x1c0) == TT_FILL) {
 161         cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
 162     }
 163     env->tbr &= ~0x7fffULL;
 164     env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
 165     env->pc = env->tbr;
 166     env->npc = env->pc + 4;
 167     env->exception_index = -1;
 168 }
 169
 170 trap_state *cpu_tsptr(CPUState* env)
 171 {
 172     return &env->ts[env->tl & MAXTL_MASK];
 173 }
 174
 175 static void do_modify_softint(CPUState *env, const char *operation,
 176                               uint32_t value)
 177 {
 178     if (env->softint != value) {
 179         env->softint = value;
 180         DPRINTF_PSTATE(": %s new %08x\n", operation, env->softint);
 181 #if !defined(CONFIG_USER_ONLY)
 182         if (cpu_interrupts_enabled(env)) {
 183             cpu_check_irqs(env);
 184         }
 185 #endif
 186     }
 187 }
 188
 189 void helper_set_softint(CPUState *env, uint64_t value)
 190 {
 191     do_modify_softint(env, "helper_set_softint",
 192                       env->softint | (uint32_t)value);
 193 }
 194
 195 void helper_clear_softint(CPUState *env, uint64_t value)
 196 {
 197     do_modify_softint(env, "helper_clear_softint",
 198                       env->softint & (uint32_t)~value);
 199 }
 200
 201 void helper_write_softint(CPUState *env, uint64_t value)
 202 {
 203     do_modify_softint(env, "helper_write_softint", (uint32_t)value);
 204 }