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Merge branch 'target-arm.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
[qemu.git] / target-sparc / ldst_helper.c
1 /*
2 * Helpers for loads and stores
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "dyngen-exec.h"
22 #include "helper.h"
23
24 #if !defined(CONFIG_USER_ONLY)
25 #include "softmmu_exec.h"
26 #endif
27
28 //#define DEBUG_MMU
29 //#define DEBUG_MXCC
30 //#define DEBUG_UNALIGNED
31 //#define DEBUG_UNASSIGNED
32 //#define DEBUG_ASI
33 //#define DEBUG_CACHE_CONTROL
34
35 #ifdef DEBUG_MMU
36 #define DPRINTF_MMU(fmt, ...) \
37 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
38 #else
39 #define DPRINTF_MMU(fmt, ...) do {} while (0)
40 #endif
41
42 #ifdef DEBUG_MXCC
43 #define DPRINTF_MXCC(fmt, ...) \
44 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
45 #else
46 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
47 #endif
48
49 #ifdef DEBUG_ASI
50 #define DPRINTF_ASI(fmt, ...) \
51 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
52 #endif
53
54 #ifdef DEBUG_CACHE_CONTROL
55 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
56 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
57 #else
58 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
59 #endif
60
61 #ifdef TARGET_SPARC64
62 #ifndef TARGET_ABI32
63 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
64 #else
65 #define AM_CHECK(env1) (1)
66 #endif
67 #endif
68
69 #define DT0 (env->dt0)
70 #define DT1 (env->dt1)
71 #define QT0 (env->qt0)
72 #define QT1 (env->qt1)
73
74 #if !defined(CONFIG_USER_ONLY)
75 static void do_unassigned_access(target_phys_addr_t addr, int is_write,
76 int is_exec, int is_asi, int size);
77 #else
78 #ifdef TARGET_SPARC64
79 static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
80 int is_asi, int size);
81 #endif
82 #endif
83
84 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
85 /* Calculates TSB pointer value for fault page size 8k or 64k */
86 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
87 uint64_t tag_access_register,
88 int page_size)
89 {
90 uint64_t tsb_base = tsb_register & ~0x1fffULL;
91 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
92 int tsb_size = tsb_register & 0xf;
93
94 /* discard lower 13 bits which hold tag access context */
95 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
96
97 /* now reorder bits */
98 uint64_t tsb_base_mask = ~0x1fffULL;
99 uint64_t va = tag_access_va;
100
101 /* move va bits to correct position */
102 if (page_size == 8*1024) {
103 va >>= 9;
104 } else if (page_size == 64*1024) {
105 va >>= 12;
106 }
107
108 if (tsb_size) {
109 tsb_base_mask <<= tsb_size;
110 }
111
112 /* calculate tsb_base mask and adjust va if split is in use */
113 if (tsb_split) {
114 if (page_size == 8*1024) {
115 va &= ~(1ULL << (13 + tsb_size));
116 } else if (page_size == 64*1024) {
117 va |= (1ULL << (13 + tsb_size));
118 }
119 tsb_base_mask <<= 1;
120 }
121
122 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
123 }
124
125 /* Calculates tag target register value by reordering bits
126 in tag access register */
127 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
128 {
129 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
130 }
131
132 static void replace_tlb_entry(SparcTLBEntry *tlb,
133 uint64_t tlb_tag, uint64_t tlb_tte,
134 CPUState *env1)
135 {
136 target_ulong mask, size, va, offset;
137
138 /* flush page range if translation is valid */
139 if (TTE_IS_VALID(tlb->tte)) {
140
141 mask = 0xffffffffffffe000ULL;
142 mask <<= 3 * ((tlb->tte >> 61) & 3);
143 size = ~mask + 1;
144
145 va = tlb->tag & mask;
146
147 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
148 tlb_flush_page(env1, va + offset);
149 }
150 }
151
152 tlb->tag = tlb_tag;
153 tlb->tte = tlb_tte;
154 }
155
156 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
157 const char *strmmu, CPUState *env1)
158 {
159 unsigned int i;
160 target_ulong mask;
161 uint64_t context;
162
163 int is_demap_context = (demap_addr >> 6) & 1;
164
165 /* demap context */
166 switch ((demap_addr >> 4) & 3) {
167 case 0: /* primary */
168 context = env1->dmmu.mmu_primary_context;
169 break;
170 case 1: /* secondary */
171 context = env1->dmmu.mmu_secondary_context;
172 break;
173 case 2: /* nucleus */
174 context = 0;
175 break;
176 case 3: /* reserved */
177 default:
178 return;
179 }
180
181 for (i = 0; i < 64; i++) {
182 if (TTE_IS_VALID(tlb[i].tte)) {
183
184 if (is_demap_context) {
185 /* will remove non-global entries matching context value */
186 if (TTE_IS_GLOBAL(tlb[i].tte) ||
187 !tlb_compare_context(&tlb[i], context)) {
188 continue;
189 }
190 } else {
191 /* demap page
192 will remove any entry matching VA */
193 mask = 0xffffffffffffe000ULL;
194 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
195
196 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
197 continue;
198 }
199
200 /* entry should be global or matching context value */
201 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
202 !tlb_compare_context(&tlb[i], context)) {
203 continue;
204 }
205 }
206
207 replace_tlb_entry(&tlb[i], 0, 0, env1);
208 #ifdef DEBUG_MMU
209 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
210 dump_mmu(stdout, fprintf, env1);
211 #endif
212 }
213 }
214 }
215
216 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
217 uint64_t tlb_tag, uint64_t tlb_tte,
218 const char *strmmu, CPUState *env1)
219 {
220 unsigned int i, replace_used;
221
222 /* Try replacing invalid entry */
223 for (i = 0; i < 64; i++) {
224 if (!TTE_IS_VALID(tlb[i].tte)) {
225 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
226 #ifdef DEBUG_MMU
227 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
228 dump_mmu(stdout, fprintf, env1);
229 #endif
230 return;
231 }
232 }
233
234 /* All entries are valid, try replacing unlocked entry */
235
236 for (replace_used = 0; replace_used < 2; ++replace_used) {
237
238 /* Used entries are not replaced on first pass */
239
240 for (i = 0; i < 64; i++) {
241 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
242
243 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
244 #ifdef DEBUG_MMU
245 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
246 strmmu, (replace_used ? "used" : "unused"), i);
247 dump_mmu(stdout, fprintf, env1);
248 #endif
249 return;
250 }
251 }
252
253 /* Now reset used bit and search for unused entries again */
254
255 for (i = 0; i < 64; i++) {
256 TTE_SET_UNUSED(tlb[i].tte);
257 }
258 }
259
260 #ifdef DEBUG_MMU
261 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
262 #endif
263 /* error state? */
264 }
265
266 #endif
267
268 static inline target_ulong address_mask(CPUState *env1, target_ulong addr)
269 {
270 #ifdef TARGET_SPARC64
271 if (AM_CHECK(env1)) {
272 addr &= 0xffffffffULL;
273 }
274 #endif
275 return addr;
276 }
277
278 /* returns true if access using this ASI is to have address translated by MMU
279 otherwise access is to raw physical address */
280 static inline int is_translating_asi(int asi)
281 {
282 #ifdef TARGET_SPARC64
283 /* Ultrasparc IIi translating asi
284 - note this list is defined by cpu implementation
285 */
286 switch (asi) {
287 case 0x04 ... 0x11:
288 case 0x16 ... 0x19:
289 case 0x1E ... 0x1F:
290 case 0x24 ... 0x2C:
291 case 0x70 ... 0x73:
292 case 0x78 ... 0x79:
293 case 0x80 ... 0xFF:
294 return 1;
295
296 default:
297 return 0;
298 }
299 #else
300 /* TODO: check sparc32 bits */
301 return 0;
302 #endif
303 }
304
305 static inline target_ulong asi_address_mask(CPUState *env1,
306 int asi, target_ulong addr)
307 {
308 if (is_translating_asi(asi)) {
309 return address_mask(env, addr);
310 } else {
311 return addr;
312 }
313 }
314
315 void helper_check_align(target_ulong addr, uint32_t align)
316 {
317 if (addr & align) {
318 #ifdef DEBUG_UNALIGNED
319 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
320 "\n", addr, env->pc);
321 #endif
322 helper_raise_exception(env, TT_UNALIGNED);
323 }
324 }
325
326 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
327 defined(DEBUG_MXCC)
328 static void dump_mxcc(CPUState *env)
329 {
330 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
331 "\n",
332 env->mxccdata[0], env->mxccdata[1],
333 env->mxccdata[2], env->mxccdata[3]);
334 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
335 "\n"
336 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
337 "\n",
338 env->mxccregs[0], env->mxccregs[1],
339 env->mxccregs[2], env->mxccregs[3],
340 env->mxccregs[4], env->mxccregs[5],
341 env->mxccregs[6], env->mxccregs[7]);
342 }
343 #endif
344
345 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
346 && defined(DEBUG_ASI)
347 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
348 uint64_t r1)
349 {
350 switch (size) {
351 case 1:
352 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
353 addr, asi, r1 & 0xff);
354 break;
355 case 2:
356 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
357 addr, asi, r1 & 0xffff);
358 break;
359 case 4:
360 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
361 addr, asi, r1 & 0xffffffff);
362 break;
363 case 8:
364 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
365 addr, asi, r1);
366 break;
367 }
368 }
369 #endif
370
371 #ifndef TARGET_SPARC64
372 #ifndef CONFIG_USER_ONLY
373
374
375 /* Leon3 cache control */
376
377 static void leon3_cache_control_st(target_ulong addr, uint64_t val, int size)
378 {
379 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
380 addr, val, size);
381
382 if (size != 4) {
383 DPRINTF_CACHE_CONTROL("32bits only\n");
384 return;
385 }
386
387 switch (addr) {
388 case 0x00: /* Cache control */
389
390 /* These values must always be read as zeros */
391 val &= ~CACHE_CTRL_FD;
392 val &= ~CACHE_CTRL_FI;
393 val &= ~CACHE_CTRL_IB;
394 val &= ~CACHE_CTRL_IP;
395 val &= ~CACHE_CTRL_DP;
396
397 env->cache_control = val;
398 break;
399 case 0x04: /* Instruction cache configuration */
400 case 0x08: /* Data cache configuration */
401 /* Read Only */
402 break;
403 default:
404 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
405 break;
406 };
407 }
408
409 static uint64_t leon3_cache_control_ld(target_ulong addr, int size)
410 {
411 uint64_t ret = 0;
412
413 if (size != 4) {
414 DPRINTF_CACHE_CONTROL("32bits only\n");
415 return 0;
416 }
417
418 switch (addr) {
419 case 0x00: /* Cache control */
420 ret = env->cache_control;
421 break;
422
423 /* Configuration registers are read and only always keep those
424 predefined values */
425
426 case 0x04: /* Instruction cache configuration */
427 ret = 0x10220000;
428 break;
429 case 0x08: /* Data cache configuration */
430 ret = 0x18220000;
431 break;
432 default:
433 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
434 break;
435 };
436 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
437 addr, ret, size);
438 return ret;
439 }
440
441 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
442 {
443 uint64_t ret = 0;
444 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
445 uint32_t last_addr = addr;
446 #endif
447
448 helper_check_align(addr, size - 1);
449 switch (asi) {
450 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
451 switch (addr) {
452 case 0x00: /* Leon3 Cache Control */
453 case 0x08: /* Leon3 Instruction Cache config */
454 case 0x0C: /* Leon3 Date Cache config */
455 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
456 ret = leon3_cache_control_ld(addr, size);
457 }
458 break;
459 case 0x01c00a00: /* MXCC control register */
460 if (size == 8) {
461 ret = env->mxccregs[3];
462 } else {
463 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
464 size);
465 }
466 break;
467 case 0x01c00a04: /* MXCC control register */
468 if (size == 4) {
469 ret = env->mxccregs[3];
470 } else {
471 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
472 size);
473 }
474 break;
475 case 0x01c00c00: /* Module reset register */
476 if (size == 8) {
477 ret = env->mxccregs[5];
478 /* should we do something here? */
479 } else {
480 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
481 size);
482 }
483 break;
484 case 0x01c00f00: /* MBus port address register */
485 if (size == 8) {
486 ret = env->mxccregs[7];
487 } else {
488 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
489 size);
490 }
491 break;
492 default:
493 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
494 size);
495 break;
496 }
497 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
498 "addr = %08x -> ret = %" PRIx64 ","
499 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
500 #ifdef DEBUG_MXCC
501 dump_mxcc(env);
502 #endif
503 break;
504 case 3: /* MMU probe */
505 {
506 int mmulev;
507
508 mmulev = (addr >> 8) & 15;
509 if (mmulev > 4) {
510 ret = 0;
511 } else {
512 ret = mmu_probe(env, addr, mmulev);
513 }
514 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
515 addr, mmulev, ret);
516 }
517 break;
518 case 4: /* read MMU regs */
519 {
520 int reg = (addr >> 8) & 0x1f;
521
522 ret = env->mmuregs[reg];
523 if (reg == 3) { /* Fault status cleared on read */
524 env->mmuregs[3] = 0;
525 } else if (reg == 0x13) { /* Fault status read */
526 ret = env->mmuregs[3];
527 } else if (reg == 0x14) { /* Fault address read */
528 ret = env->mmuregs[4];
529 }
530 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
531 }
532 break;
533 case 5: /* Turbosparc ITLB Diagnostic */
534 case 6: /* Turbosparc DTLB Diagnostic */
535 case 7: /* Turbosparc IOTLB Diagnostic */
536 break;
537 case 9: /* Supervisor code access */
538 switch (size) {
539 case 1:
540 ret = ldub_code(addr);
541 break;
542 case 2:
543 ret = lduw_code(addr);
544 break;
545 default:
546 case 4:
547 ret = ldl_code(addr);
548 break;
549 case 8:
550 ret = ldq_code(addr);
551 break;
552 }
553 break;
554 case 0xa: /* User data access */
555 switch (size) {
556 case 1:
557 ret = ldub_user(addr);
558 break;
559 case 2:
560 ret = lduw_user(addr);
561 break;
562 default:
563 case 4:
564 ret = ldl_user(addr);
565 break;
566 case 8:
567 ret = ldq_user(addr);
568 break;
569 }
570 break;
571 case 0xb: /* Supervisor data access */
572 switch (size) {
573 case 1:
574 ret = ldub_kernel(addr);
575 break;
576 case 2:
577 ret = lduw_kernel(addr);
578 break;
579 default:
580 case 4:
581 ret = ldl_kernel(addr);
582 break;
583 case 8:
584 ret = ldq_kernel(addr);
585 break;
586 }
587 break;
588 case 0xc: /* I-cache tag */
589 case 0xd: /* I-cache data */
590 case 0xe: /* D-cache tag */
591 case 0xf: /* D-cache data */
592 break;
593 case 0x20: /* MMU passthrough */
594 switch (size) {
595 case 1:
596 ret = ldub_phys(addr);
597 break;
598 case 2:
599 ret = lduw_phys(addr);
600 break;
601 default:
602 case 4:
603 ret = ldl_phys(addr);
604 break;
605 case 8:
606 ret = ldq_phys(addr);
607 break;
608 }
609 break;
610 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
611 switch (size) {
612 case 1:
613 ret = ldub_phys((target_phys_addr_t)addr
614 | ((target_phys_addr_t)(asi & 0xf) << 32));
615 break;
616 case 2:
617 ret = lduw_phys((target_phys_addr_t)addr
618 | ((target_phys_addr_t)(asi & 0xf) << 32));
619 break;
620 default:
621 case 4:
622 ret = ldl_phys((target_phys_addr_t)addr
623 | ((target_phys_addr_t)(asi & 0xf) << 32));
624 break;
625 case 8:
626 ret = ldq_phys((target_phys_addr_t)addr
627 | ((target_phys_addr_t)(asi & 0xf) << 32));
628 break;
629 }
630 break;
631 case 0x30: /* Turbosparc secondary cache diagnostic */
632 case 0x31: /* Turbosparc RAM snoop */
633 case 0x32: /* Turbosparc page table descriptor diagnostic */
634 case 0x39: /* data cache diagnostic register */
635 ret = 0;
636 break;
637 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
638 {
639 int reg = (addr >> 8) & 3;
640
641 switch (reg) {
642 case 0: /* Breakpoint Value (Addr) */
643 ret = env->mmubpregs[reg];
644 break;
645 case 1: /* Breakpoint Mask */
646 ret = env->mmubpregs[reg];
647 break;
648 case 2: /* Breakpoint Control */
649 ret = env->mmubpregs[reg];
650 break;
651 case 3: /* Breakpoint Status */
652 ret = env->mmubpregs[reg];
653 env->mmubpregs[reg] = 0ULL;
654 break;
655 }
656 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
657 ret);
658 }
659 break;
660 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
661 ret = env->mmubpctrv;
662 break;
663 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
664 ret = env->mmubpctrc;
665 break;
666 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
667 ret = env->mmubpctrs;
668 break;
669 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
670 ret = env->mmubpaction;
671 break;
672 case 8: /* User code access, XXX */
673 default:
674 do_unassigned_access(addr, 0, 0, asi, size);
675 ret = 0;
676 break;
677 }
678 if (sign) {
679 switch (size) {
680 case 1:
681 ret = (int8_t) ret;
682 break;
683 case 2:
684 ret = (int16_t) ret;
685 break;
686 case 4:
687 ret = (int32_t) ret;
688 break;
689 default:
690 break;
691 }
692 }
693 #ifdef DEBUG_ASI
694 dump_asi("read ", last_addr, asi, size, ret);
695 #endif
696 return ret;
697 }
698
699 void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
700 {
701 helper_check_align(addr, size - 1);
702 switch (asi) {
703 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
704 switch (addr) {
705 case 0x00: /* Leon3 Cache Control */
706 case 0x08: /* Leon3 Instruction Cache config */
707 case 0x0C: /* Leon3 Date Cache config */
708 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
709 leon3_cache_control_st(addr, val, size);
710 }
711 break;
712
713 case 0x01c00000: /* MXCC stream data register 0 */
714 if (size == 8) {
715 env->mxccdata[0] = val;
716 } else {
717 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
718 size);
719 }
720 break;
721 case 0x01c00008: /* MXCC stream data register 1 */
722 if (size == 8) {
723 env->mxccdata[1] = val;
724 } else {
725 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
726 size);
727 }
728 break;
729 case 0x01c00010: /* MXCC stream data register 2 */
730 if (size == 8) {
731 env->mxccdata[2] = val;
732 } else {
733 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
734 size);
735 }
736 break;
737 case 0x01c00018: /* MXCC stream data register 3 */
738 if (size == 8) {
739 env->mxccdata[3] = val;
740 } else {
741 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
742 size);
743 }
744 break;
745 case 0x01c00100: /* MXCC stream source */
746 if (size == 8) {
747 env->mxccregs[0] = val;
748 } else {
749 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
750 size);
751 }
752 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
753 0);
754 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
755 8);
756 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
757 16);
758 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
759 24);
760 break;
761 case 0x01c00200: /* MXCC stream destination */
762 if (size == 8) {
763 env->mxccregs[1] = val;
764 } else {
765 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
766 size);
767 }
768 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
769 env->mxccdata[0]);
770 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
771 env->mxccdata[1]);
772 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
773 env->mxccdata[2]);
774 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
775 env->mxccdata[3]);
776 break;
777 case 0x01c00a00: /* MXCC control register */
778 if (size == 8) {
779 env->mxccregs[3] = val;
780 } else {
781 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
782 size);
783 }
784 break;
785 case 0x01c00a04: /* MXCC control register */
786 if (size == 4) {
787 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
788 | val;
789 } else {
790 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
791 size);
792 }
793 break;
794 case 0x01c00e00: /* MXCC error register */
795 /* writing a 1 bit clears the error */
796 if (size == 8) {
797 env->mxccregs[6] &= ~val;
798 } else {
799 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
800 size);
801 }
802 break;
803 case 0x01c00f00: /* MBus port address register */
804 if (size == 8) {
805 env->mxccregs[7] = val;
806 } else {
807 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
808 size);
809 }
810 break;
811 default:
812 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
813 size);
814 break;
815 }
816 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
817 asi, size, addr, val);
818 #ifdef DEBUG_MXCC
819 dump_mxcc(env);
820 #endif
821 break;
822 case 3: /* MMU flush */
823 {
824 int mmulev;
825
826 mmulev = (addr >> 8) & 15;
827 DPRINTF_MMU("mmu flush level %d\n", mmulev);
828 switch (mmulev) {
829 case 0: /* flush page */
830 tlb_flush_page(env, addr & 0xfffff000);
831 break;
832 case 1: /* flush segment (256k) */
833 case 2: /* flush region (16M) */
834 case 3: /* flush context (4G) */
835 case 4: /* flush entire */
836 tlb_flush(env, 1);
837 break;
838 default:
839 break;
840 }
841 #ifdef DEBUG_MMU
842 dump_mmu(stdout, fprintf, env);
843 #endif
844 }
845 break;
846 case 4: /* write MMU regs */
847 {
848 int reg = (addr >> 8) & 0x1f;
849 uint32_t oldreg;
850
851 oldreg = env->mmuregs[reg];
852 switch (reg) {
853 case 0: /* Control Register */
854 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
855 (val & 0x00ffffff);
856 /* Mappings generated during no-fault mode or MMU
857 disabled mode are invalid in normal mode */
858 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
859 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) {
860 tlb_flush(env, 1);
861 }
862 break;
863 case 1: /* Context Table Pointer Register */
864 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
865 break;
866 case 2: /* Context Register */
867 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
868 if (oldreg != env->mmuregs[reg]) {
869 /* we flush when the MMU context changes because
870 QEMU has no MMU context support */
871 tlb_flush(env, 1);
872 }
873 break;
874 case 3: /* Synchronous Fault Status Register with Clear */
875 case 4: /* Synchronous Fault Address Register */
876 break;
877 case 0x10: /* TLB Replacement Control Register */
878 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
879 break;
880 case 0x13: /* Synchronous Fault Status Register with Read
881 and Clear */
882 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
883 break;
884 case 0x14: /* Synchronous Fault Address Register */
885 env->mmuregs[4] = val;
886 break;
887 default:
888 env->mmuregs[reg] = val;
889 break;
890 }
891 if (oldreg != env->mmuregs[reg]) {
892 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
893 reg, oldreg, env->mmuregs[reg]);
894 }
895 #ifdef DEBUG_MMU
896 dump_mmu(stdout, fprintf, env);
897 #endif
898 }
899 break;
900 case 5: /* Turbosparc ITLB Diagnostic */
901 case 6: /* Turbosparc DTLB Diagnostic */
902 case 7: /* Turbosparc IOTLB Diagnostic */
903 break;
904 case 0xa: /* User data access */
905 switch (size) {
906 case 1:
907 stb_user(addr, val);
908 break;
909 case 2:
910 stw_user(addr, val);
911 break;
912 default:
913 case 4:
914 stl_user(addr, val);
915 break;
916 case 8:
917 stq_user(addr, val);
918 break;
919 }
920 break;
921 case 0xb: /* Supervisor data access */
922 switch (size) {
923 case 1:
924 stb_kernel(addr, val);
925 break;
926 case 2:
927 stw_kernel(addr, val);
928 break;
929 default:
930 case 4:
931 stl_kernel(addr, val);
932 break;
933 case 8:
934 stq_kernel(addr, val);
935 break;
936 }
937 break;
938 case 0xc: /* I-cache tag */
939 case 0xd: /* I-cache data */
940 case 0xe: /* D-cache tag */
941 case 0xf: /* D-cache data */
942 case 0x10: /* I/D-cache flush page */
943 case 0x11: /* I/D-cache flush segment */
944 case 0x12: /* I/D-cache flush region */
945 case 0x13: /* I/D-cache flush context */
946 case 0x14: /* I/D-cache flush user */
947 break;
948 case 0x17: /* Block copy, sta access */
949 {
950 /* val = src
951 addr = dst
952 copy 32 bytes */
953 unsigned int i;
954 uint32_t src = val & ~3, dst = addr & ~3, temp;
955
956 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
957 temp = ldl_kernel(src);
958 stl_kernel(dst, temp);
959 }
960 }
961 break;
962 case 0x1f: /* Block fill, stda access */
963 {
964 /* addr = dst
965 fill 32 bytes with val */
966 unsigned int i;
967 uint32_t dst = addr & 7;
968
969 for (i = 0; i < 32; i += 8, dst += 8) {
970 stq_kernel(dst, val);
971 }
972 }
973 break;
974 case 0x20: /* MMU passthrough */
975 {
976 switch (size) {
977 case 1:
978 stb_phys(addr, val);
979 break;
980 case 2:
981 stw_phys(addr, val);
982 break;
983 case 4:
984 default:
985 stl_phys(addr, val);
986 break;
987 case 8:
988 stq_phys(addr, val);
989 break;
990 }
991 }
992 break;
993 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
994 {
995 switch (size) {
996 case 1:
997 stb_phys((target_phys_addr_t)addr
998 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
999 break;
1000 case 2:
1001 stw_phys((target_phys_addr_t)addr
1002 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1003 break;
1004 case 4:
1005 default:
1006 stl_phys((target_phys_addr_t)addr
1007 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1008 break;
1009 case 8:
1010 stq_phys((target_phys_addr_t)addr
1011 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1012 break;
1013 }
1014 }
1015 break;
1016 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1017 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1018 Turbosparc snoop RAM */
1019 case 0x32: /* store buffer control or Turbosparc page table
1020 descriptor diagnostic */
1021 case 0x36: /* I-cache flash clear */
1022 case 0x37: /* D-cache flash clear */
1023 break;
1024 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1025 {
1026 int reg = (addr >> 8) & 3;
1027
1028 switch (reg) {
1029 case 0: /* Breakpoint Value (Addr) */
1030 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1031 break;
1032 case 1: /* Breakpoint Mask */
1033 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1034 break;
1035 case 2: /* Breakpoint Control */
1036 env->mmubpregs[reg] = (val & 0x7fULL);
1037 break;
1038 case 3: /* Breakpoint Status */
1039 env->mmubpregs[reg] = (val & 0xfULL);
1040 break;
1041 }
1042 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
1043 env->mmuregs[reg]);
1044 }
1045 break;
1046 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1047 env->mmubpctrv = val & 0xffffffff;
1048 break;
1049 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1050 env->mmubpctrc = val & 0x3;
1051 break;
1052 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1053 env->mmubpctrs = val & 0x3;
1054 break;
1055 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1056 env->mmubpaction = val & 0x1fff;
1057 break;
1058 case 8: /* User code access, XXX */
1059 case 9: /* Supervisor code access, XXX */
1060 default:
1061 do_unassigned_access(addr, 1, 0, asi, size);
1062 break;
1063 }
1064 #ifdef DEBUG_ASI
1065 dump_asi("write", addr, asi, size, val);
1066 #endif
1067 }
1068
1069 #endif /* CONFIG_USER_ONLY */
1070 #else /* TARGET_SPARC64 */
1071
1072 #ifdef CONFIG_USER_ONLY
1073 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1074 {
1075 uint64_t ret = 0;
1076 #if defined(DEBUG_ASI)
1077 target_ulong last_addr = addr;
1078 #endif
1079
1080 if (asi < 0x80) {
1081 helper_raise_exception(env, TT_PRIV_ACT);
1082 }
1083
1084 helper_check_align(addr, size - 1);
1085 addr = asi_address_mask(env, asi, addr);
1086
1087 switch (asi) {
1088 case 0x82: /* Primary no-fault */
1089 case 0x8a: /* Primary no-fault LE */
1090 if (page_check_range(addr, size, PAGE_READ) == -1) {
1091 #ifdef DEBUG_ASI
1092 dump_asi("read ", last_addr, asi, size, ret);
1093 #endif
1094 return 0;
1095 }
1096 /* Fall through */
1097 case 0x80: /* Primary */
1098 case 0x88: /* Primary LE */
1099 {
1100 switch (size) {
1101 case 1:
1102 ret = ldub_raw(addr);
1103 break;
1104 case 2:
1105 ret = lduw_raw(addr);
1106 break;
1107 case 4:
1108 ret = ldl_raw(addr);
1109 break;
1110 default:
1111 case 8:
1112 ret = ldq_raw(addr);
1113 break;
1114 }
1115 }
1116 break;
1117 case 0x83: /* Secondary no-fault */
1118 case 0x8b: /* Secondary no-fault LE */
1119 if (page_check_range(addr, size, PAGE_READ) == -1) {
1120 #ifdef DEBUG_ASI
1121 dump_asi("read ", last_addr, asi, size, ret);
1122 #endif
1123 return 0;
1124 }
1125 /* Fall through */
1126 case 0x81: /* Secondary */
1127 case 0x89: /* Secondary LE */
1128 /* XXX */
1129 break;
1130 default:
1131 break;
1132 }
1133
1134 /* Convert from little endian */
1135 switch (asi) {
1136 case 0x88: /* Primary LE */
1137 case 0x89: /* Secondary LE */
1138 case 0x8a: /* Primary no-fault LE */
1139 case 0x8b: /* Secondary no-fault LE */
1140 switch (size) {
1141 case 2:
1142 ret = bswap16(ret);
1143 break;
1144 case 4:
1145 ret = bswap32(ret);
1146 break;
1147 case 8:
1148 ret = bswap64(ret);
1149 break;
1150 default:
1151 break;
1152 }
1153 default:
1154 break;
1155 }
1156
1157 /* Convert to signed number */
1158 if (sign) {
1159 switch (size) {
1160 case 1:
1161 ret = (int8_t) ret;
1162 break;
1163 case 2:
1164 ret = (int16_t) ret;
1165 break;
1166 case 4:
1167 ret = (int32_t) ret;
1168 break;
1169 default:
1170 break;
1171 }
1172 }
1173 #ifdef DEBUG_ASI
1174 dump_asi("read ", last_addr, asi, size, ret);
1175 #endif
1176 return ret;
1177 }
1178
1179 void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
1180 {
1181 #ifdef DEBUG_ASI
1182 dump_asi("write", addr, asi, size, val);
1183 #endif
1184 if (asi < 0x80) {
1185 helper_raise_exception(env, TT_PRIV_ACT);
1186 }
1187
1188 helper_check_align(addr, size - 1);
1189 addr = asi_address_mask(env, asi, addr);
1190
1191 /* Convert to little endian */
1192 switch (asi) {
1193 case 0x88: /* Primary LE */
1194 case 0x89: /* Secondary LE */
1195 switch (size) {
1196 case 2:
1197 val = bswap16(val);
1198 break;
1199 case 4:
1200 val = bswap32(val);
1201 break;
1202 case 8:
1203 val = bswap64(val);
1204 break;
1205 default:
1206 break;
1207 }
1208 default:
1209 break;
1210 }
1211
1212 switch (asi) {
1213 case 0x80: /* Primary */
1214 case 0x88: /* Primary LE */
1215 {
1216 switch (size) {
1217 case 1:
1218 stb_raw(addr, val);
1219 break;
1220 case 2:
1221 stw_raw(addr, val);
1222 break;
1223 case 4:
1224 stl_raw(addr, val);
1225 break;
1226 case 8:
1227 default:
1228 stq_raw(addr, val);
1229 break;
1230 }
1231 }
1232 break;
1233 case 0x81: /* Secondary */
1234 case 0x89: /* Secondary LE */
1235 /* XXX */
1236 return;
1237
1238 case 0x82: /* Primary no-fault, RO */
1239 case 0x83: /* Secondary no-fault, RO */
1240 case 0x8a: /* Primary no-fault LE, RO */
1241 case 0x8b: /* Secondary no-fault LE, RO */
1242 default:
1243 do_unassigned_access(addr, 1, 0, 1, size);
1244 return;
1245 }
1246 }
1247
1248 #else /* CONFIG_USER_ONLY */
1249
1250 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1251 {
1252 uint64_t ret = 0;
1253 #if defined(DEBUG_ASI)
1254 target_ulong last_addr = addr;
1255 #endif
1256
1257 asi &= 0xff;
1258
1259 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1260 || (cpu_has_hypervisor(env)
1261 && asi >= 0x30 && asi < 0x80
1262 && !(env->hpstate & HS_PRIV))) {
1263 helper_raise_exception(env, TT_PRIV_ACT);
1264 }
1265
1266 helper_check_align(addr, size - 1);
1267 addr = asi_address_mask(env, asi, addr);
1268
1269 /* process nonfaulting loads first */
1270 if ((asi & 0xf6) == 0x82) {
1271 int mmu_idx;
1272
1273 /* secondary space access has lowest asi bit equal to 1 */
1274 if (env->pstate & PS_PRIV) {
1275 mmu_idx = (asi & 1) ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX;
1276 } else {
1277 mmu_idx = (asi & 1) ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX;
1278 }
1279
1280 if (cpu_get_phys_page_nofault(env, addr, mmu_idx) == -1ULL) {
1281 #ifdef DEBUG_ASI
1282 dump_asi("read ", last_addr, asi, size, ret);
1283 #endif
1284 /* env->exception_index is set in get_physical_address_data(). */
1285 helper_raise_exception(env, env->exception_index);
1286 }
1287
1288 /* convert nonfaulting load ASIs to normal load ASIs */
1289 asi &= ~0x02;
1290 }
1291
1292 switch (asi) {
1293 case 0x10: /* As if user primary */
1294 case 0x11: /* As if user secondary */
1295 case 0x18: /* As if user primary LE */
1296 case 0x19: /* As if user secondary LE */
1297 case 0x80: /* Primary */
1298 case 0x81: /* Secondary */
1299 case 0x88: /* Primary LE */
1300 case 0x89: /* Secondary LE */
1301 case 0xe2: /* UA2007 Primary block init */
1302 case 0xe3: /* UA2007 Secondary block init */
1303 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1304 if (cpu_hypervisor_mode(env)) {
1305 switch (size) {
1306 case 1:
1307 ret = ldub_hypv(addr);
1308 break;
1309 case 2:
1310 ret = lduw_hypv(addr);
1311 break;
1312 case 4:
1313 ret = ldl_hypv(addr);
1314 break;
1315 default:
1316 case 8:
1317 ret = ldq_hypv(addr);
1318 break;
1319 }
1320 } else {
1321 /* secondary space access has lowest asi bit equal to 1 */
1322 if (asi & 1) {
1323 switch (size) {
1324 case 1:
1325 ret = ldub_kernel_secondary(addr);
1326 break;
1327 case 2:
1328 ret = lduw_kernel_secondary(addr);
1329 break;
1330 case 4:
1331 ret = ldl_kernel_secondary(addr);
1332 break;
1333 default:
1334 case 8:
1335 ret = ldq_kernel_secondary(addr);
1336 break;
1337 }
1338 } else {
1339 switch (size) {
1340 case 1:
1341 ret = ldub_kernel(addr);
1342 break;
1343 case 2:
1344 ret = lduw_kernel(addr);
1345 break;
1346 case 4:
1347 ret = ldl_kernel(addr);
1348 break;
1349 default:
1350 case 8:
1351 ret = ldq_kernel(addr);
1352 break;
1353 }
1354 }
1355 }
1356 } else {
1357 /* secondary space access has lowest asi bit equal to 1 */
1358 if (asi & 1) {
1359 switch (size) {
1360 case 1:
1361 ret = ldub_user_secondary(addr);
1362 break;
1363 case 2:
1364 ret = lduw_user_secondary(addr);
1365 break;
1366 case 4:
1367 ret = ldl_user_secondary(addr);
1368 break;
1369 default:
1370 case 8:
1371 ret = ldq_user_secondary(addr);
1372 break;
1373 }
1374 } else {
1375 switch (size) {
1376 case 1:
1377 ret = ldub_user(addr);
1378 break;
1379 case 2:
1380 ret = lduw_user(addr);
1381 break;
1382 case 4:
1383 ret = ldl_user(addr);
1384 break;
1385 default:
1386 case 8:
1387 ret = ldq_user(addr);
1388 break;
1389 }
1390 }
1391 }
1392 break;
1393 case 0x14: /* Bypass */
1394 case 0x15: /* Bypass, non-cacheable */
1395 case 0x1c: /* Bypass LE */
1396 case 0x1d: /* Bypass, non-cacheable LE */
1397 {
1398 switch (size) {
1399 case 1:
1400 ret = ldub_phys(addr);
1401 break;
1402 case 2:
1403 ret = lduw_phys(addr);
1404 break;
1405 case 4:
1406 ret = ldl_phys(addr);
1407 break;
1408 default:
1409 case 8:
1410 ret = ldq_phys(addr);
1411 break;
1412 }
1413 break;
1414 }
1415 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1416 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1417 Only ldda allowed */
1418 helper_raise_exception(env, TT_ILL_INSN);
1419 return 0;
1420 case 0x04: /* Nucleus */
1421 case 0x0c: /* Nucleus Little Endian (LE) */
1422 {
1423 switch (size) {
1424 case 1:
1425 ret = ldub_nucleus(addr);
1426 break;
1427 case 2:
1428 ret = lduw_nucleus(addr);
1429 break;
1430 case 4:
1431 ret = ldl_nucleus(addr);
1432 break;
1433 default:
1434 case 8:
1435 ret = ldq_nucleus(addr);
1436 break;
1437 }
1438 break;
1439 }
1440 case 0x4a: /* UPA config */
1441 /* XXX */
1442 break;
1443 case 0x45: /* LSU */
1444 ret = env->lsu;
1445 break;
1446 case 0x50: /* I-MMU regs */
1447 {
1448 int reg = (addr >> 3) & 0xf;
1449
1450 if (reg == 0) {
1451 /* I-TSB Tag Target register */
1452 ret = ultrasparc_tag_target(env->immu.tag_access);
1453 } else {
1454 ret = env->immuregs[reg];
1455 }
1456
1457 break;
1458 }
1459 case 0x51: /* I-MMU 8k TSB pointer */
1460 {
1461 /* env->immuregs[5] holds I-MMU TSB register value
1462 env->immuregs[6] holds I-MMU Tag Access register value */
1463 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1464 8*1024);
1465 break;
1466 }
1467 case 0x52: /* I-MMU 64k TSB pointer */
1468 {
1469 /* env->immuregs[5] holds I-MMU TSB register value
1470 env->immuregs[6] holds I-MMU Tag Access register value */
1471 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1472 64*1024);
1473 break;
1474 }
1475 case 0x55: /* I-MMU data access */
1476 {
1477 int reg = (addr >> 3) & 0x3f;
1478
1479 ret = env->itlb[reg].tte;
1480 break;
1481 }
1482 case 0x56: /* I-MMU tag read */
1483 {
1484 int reg = (addr >> 3) & 0x3f;
1485
1486 ret = env->itlb[reg].tag;
1487 break;
1488 }
1489 case 0x58: /* D-MMU regs */
1490 {
1491 int reg = (addr >> 3) & 0xf;
1492
1493 if (reg == 0) {
1494 /* D-TSB Tag Target register */
1495 ret = ultrasparc_tag_target(env->dmmu.tag_access);
1496 } else {
1497 ret = env->dmmuregs[reg];
1498 }
1499 break;
1500 }
1501 case 0x59: /* D-MMU 8k TSB pointer */
1502 {
1503 /* env->dmmuregs[5] holds D-MMU TSB register value
1504 env->dmmuregs[6] holds D-MMU Tag Access register value */
1505 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1506 8*1024);
1507 break;
1508 }
1509 case 0x5a: /* D-MMU 64k TSB pointer */
1510 {
1511 /* env->dmmuregs[5] holds D-MMU TSB register value
1512 env->dmmuregs[6] holds D-MMU Tag Access register value */
1513 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1514 64*1024);
1515 break;
1516 }
1517 case 0x5d: /* D-MMU data access */
1518 {
1519 int reg = (addr >> 3) & 0x3f;
1520
1521 ret = env->dtlb[reg].tte;
1522 break;
1523 }
1524 case 0x5e: /* D-MMU tag read */
1525 {
1526 int reg = (addr >> 3) & 0x3f;
1527
1528 ret = env->dtlb[reg].tag;
1529 break;
1530 }
1531 case 0x46: /* D-cache data */
1532 case 0x47: /* D-cache tag access */
1533 case 0x4b: /* E-cache error enable */
1534 case 0x4c: /* E-cache asynchronous fault status */
1535 case 0x4d: /* E-cache asynchronous fault address */
1536 case 0x4e: /* E-cache tag data */
1537 case 0x66: /* I-cache instruction access */
1538 case 0x67: /* I-cache tag access */
1539 case 0x6e: /* I-cache predecode */
1540 case 0x6f: /* I-cache LRU etc. */
1541 case 0x76: /* E-cache tag */
1542 case 0x7e: /* E-cache tag */
1543 break;
1544 case 0x5b: /* D-MMU data pointer */
1545 case 0x48: /* Interrupt dispatch, RO */
1546 case 0x49: /* Interrupt data receive */
1547 case 0x7f: /* Incoming interrupt vector, RO */
1548 /* XXX */
1549 break;
1550 case 0x54: /* I-MMU data in, WO */
1551 case 0x57: /* I-MMU demap, WO */
1552 case 0x5c: /* D-MMU data in, WO */
1553 case 0x5f: /* D-MMU demap, WO */
1554 case 0x77: /* Interrupt vector, WO */
1555 default:
1556 do_unassigned_access(addr, 0, 0, 1, size);
1557 ret = 0;
1558 break;
1559 }
1560
1561 /* Convert from little endian */
1562 switch (asi) {
1563 case 0x0c: /* Nucleus Little Endian (LE) */
1564 case 0x18: /* As if user primary LE */
1565 case 0x19: /* As if user secondary LE */
1566 case 0x1c: /* Bypass LE */
1567 case 0x1d: /* Bypass, non-cacheable LE */
1568 case 0x88: /* Primary LE */
1569 case 0x89: /* Secondary LE */
1570 switch(size) {
1571 case 2:
1572 ret = bswap16(ret);
1573 break;
1574 case 4:
1575 ret = bswap32(ret);
1576 break;
1577 case 8:
1578 ret = bswap64(ret);
1579 break;
1580 default:
1581 break;
1582 }
1583 default:
1584 break;
1585 }
1586
1587 /* Convert to signed number */
1588 if (sign) {
1589 switch (size) {
1590 case 1:
1591 ret = (int8_t) ret;
1592 break;
1593 case 2:
1594 ret = (int16_t) ret;
1595 break;
1596 case 4:
1597 ret = (int32_t) ret;
1598 break;
1599 default:
1600 break;
1601 }
1602 }
1603 #ifdef DEBUG_ASI
1604 dump_asi("read ", last_addr, asi, size, ret);
1605 #endif
1606 return ret;
1607 }
1608
1609 void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
1610 {
1611 #ifdef DEBUG_ASI
1612 dump_asi("write", addr, asi, size, val);
1613 #endif
1614
1615 asi &= 0xff;
1616
1617 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1618 || (cpu_has_hypervisor(env)
1619 && asi >= 0x30 && asi < 0x80
1620 && !(env->hpstate & HS_PRIV))) {
1621 helper_raise_exception(env, TT_PRIV_ACT);
1622 }
1623
1624 helper_check_align(addr, size - 1);
1625 addr = asi_address_mask(env, asi, addr);
1626
1627 /* Convert to little endian */
1628 switch (asi) {
1629 case 0x0c: /* Nucleus Little Endian (LE) */
1630 case 0x18: /* As if user primary LE */
1631 case 0x19: /* As if user secondary LE */
1632 case 0x1c: /* Bypass LE */
1633 case 0x1d: /* Bypass, non-cacheable LE */
1634 case 0x88: /* Primary LE */
1635 case 0x89: /* Secondary LE */
1636 switch (size) {
1637 case 2:
1638 val = bswap16(val);
1639 break;
1640 case 4:
1641 val = bswap32(val);
1642 break;
1643 case 8:
1644 val = bswap64(val);
1645 break;
1646 default:
1647 break;
1648 }
1649 default:
1650 break;
1651 }
1652
1653 switch (asi) {
1654 case 0x10: /* As if user primary */
1655 case 0x11: /* As if user secondary */
1656 case 0x18: /* As if user primary LE */
1657 case 0x19: /* As if user secondary LE */
1658 case 0x80: /* Primary */
1659 case 0x81: /* Secondary */
1660 case 0x88: /* Primary LE */
1661 case 0x89: /* Secondary LE */
1662 case 0xe2: /* UA2007 Primary block init */
1663 case 0xe3: /* UA2007 Secondary block init */
1664 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1665 if (cpu_hypervisor_mode(env)) {
1666 switch (size) {
1667 case 1:
1668 stb_hypv(addr, val);
1669 break;
1670 case 2:
1671 stw_hypv(addr, val);
1672 break;
1673 case 4:
1674 stl_hypv(addr, val);
1675 break;
1676 case 8:
1677 default:
1678 stq_hypv(addr, val);
1679 break;
1680 }
1681 } else {
1682 /* secondary space access has lowest asi bit equal to 1 */
1683 if (asi & 1) {
1684 switch (size) {
1685 case 1:
1686 stb_kernel_secondary(addr, val);
1687 break;
1688 case 2:
1689 stw_kernel_secondary(addr, val);
1690 break;
1691 case 4:
1692 stl_kernel_secondary(addr, val);
1693 break;
1694 case 8:
1695 default:
1696 stq_kernel_secondary(addr, val);
1697 break;
1698 }
1699 } else {
1700 switch (size) {
1701 case 1:
1702 stb_kernel(addr, val);
1703 break;
1704 case 2:
1705 stw_kernel(addr, val);
1706 break;
1707 case 4:
1708 stl_kernel(addr, val);
1709 break;
1710 case 8:
1711 default:
1712 stq_kernel(addr, val);
1713 break;
1714 }
1715 }
1716 }
1717 } else {
1718 /* secondary space access has lowest asi bit equal to 1 */
1719 if (asi & 1) {
1720 switch (size) {
1721 case 1:
1722 stb_user_secondary(addr, val);
1723 break;
1724 case 2:
1725 stw_user_secondary(addr, val);
1726 break;
1727 case 4:
1728 stl_user_secondary(addr, val);
1729 break;
1730 case 8:
1731 default:
1732 stq_user_secondary(addr, val);
1733 break;
1734 }
1735 } else {
1736 switch (size) {
1737 case 1:
1738 stb_user(addr, val);
1739 break;
1740 case 2:
1741 stw_user(addr, val);
1742 break;
1743 case 4:
1744 stl_user(addr, val);
1745 break;
1746 case 8:
1747 default:
1748 stq_user(addr, val);
1749 break;
1750 }
1751 }
1752 }
1753 break;
1754 case 0x14: /* Bypass */
1755 case 0x15: /* Bypass, non-cacheable */
1756 case 0x1c: /* Bypass LE */
1757 case 0x1d: /* Bypass, non-cacheable LE */
1758 {
1759 switch (size) {
1760 case 1:
1761 stb_phys(addr, val);
1762 break;
1763 case 2:
1764 stw_phys(addr, val);
1765 break;
1766 case 4:
1767 stl_phys(addr, val);
1768 break;
1769 case 8:
1770 default:
1771 stq_phys(addr, val);
1772 break;
1773 }
1774 }
1775 return;
1776 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1777 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1778 Only ldda allowed */
1779 helper_raise_exception(env, TT_ILL_INSN);
1780 return;
1781 case 0x04: /* Nucleus */
1782 case 0x0c: /* Nucleus Little Endian (LE) */
1783 {
1784 switch (size) {
1785 case 1:
1786 stb_nucleus(addr, val);
1787 break;
1788 case 2:
1789 stw_nucleus(addr, val);
1790 break;
1791 case 4:
1792 stl_nucleus(addr, val);
1793 break;
1794 default:
1795 case 8:
1796 stq_nucleus(addr, val);
1797 break;
1798 }
1799 break;
1800 }
1801
1802 case 0x4a: /* UPA config */
1803 /* XXX */
1804 return;
1805 case 0x45: /* LSU */
1806 {
1807 uint64_t oldreg;
1808
1809 oldreg = env->lsu;
1810 env->lsu = val & (DMMU_E | IMMU_E);
1811 /* Mappings generated during D/I MMU disabled mode are
1812 invalid in normal mode */
1813 if (oldreg != env->lsu) {
1814 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
1815 oldreg, env->lsu);
1816 #ifdef DEBUG_MMU
1817 dump_mmu(stdout, fprintf, env1);
1818 #endif
1819 tlb_flush(env, 1);
1820 }
1821 return;
1822 }
1823 case 0x50: /* I-MMU regs */
1824 {
1825 int reg = (addr >> 3) & 0xf;
1826 uint64_t oldreg;
1827
1828 oldreg = env->immuregs[reg];
1829 switch (reg) {
1830 case 0: /* RO */
1831 return;
1832 case 1: /* Not in I-MMU */
1833 case 2:
1834 return;
1835 case 3: /* SFSR */
1836 if ((val & 1) == 0) {
1837 val = 0; /* Clear SFSR */
1838 }
1839 env->immu.sfsr = val;
1840 break;
1841 case 4: /* RO */
1842 return;
1843 case 5: /* TSB access */
1844 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
1845 PRIx64 "\n", env->immu.tsb, val);
1846 env->immu.tsb = val;
1847 break;
1848 case 6: /* Tag access */
1849 env->immu.tag_access = val;
1850 break;
1851 case 7:
1852 case 8:
1853 return;
1854 default:
1855 break;
1856 }
1857
1858 if (oldreg != env->immuregs[reg]) {
1859 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1860 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1861 }
1862 #ifdef DEBUG_MMU
1863 dump_mmu(stdout, fprintf, env);
1864 #endif
1865 return;
1866 }
1867 case 0x54: /* I-MMU data in */
1868 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
1869 return;
1870 case 0x55: /* I-MMU data access */
1871 {
1872 /* TODO: auto demap */
1873
1874 unsigned int i = (addr >> 3) & 0x3f;
1875
1876 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env);
1877
1878 #ifdef DEBUG_MMU
1879 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
1880 dump_mmu(stdout, fprintf, env);
1881 #endif
1882 return;
1883 }
1884 case 0x57: /* I-MMU demap */
1885 demap_tlb(env->itlb, addr, "immu", env);
1886 return;
1887 case 0x58: /* D-MMU regs */
1888 {
1889 int reg = (addr >> 3) & 0xf;
1890 uint64_t oldreg;
1891
1892 oldreg = env->dmmuregs[reg];
1893 switch (reg) {
1894 case 0: /* RO */
1895 case 4:
1896 return;
1897 case 3: /* SFSR */
1898 if ((val & 1) == 0) {
1899 val = 0; /* Clear SFSR, Fault address */
1900 env->dmmu.sfar = 0;
1901 }
1902 env->dmmu.sfsr = val;
1903 break;
1904 case 1: /* Primary context */
1905 env->dmmu.mmu_primary_context = val;
1906 /* can be optimized to only flush MMU_USER_IDX
1907 and MMU_KERNEL_IDX entries */
1908 tlb_flush(env, 1);
1909 break;
1910 case 2: /* Secondary context */
1911 env->dmmu.mmu_secondary_context = val;
1912 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1913 and MMU_KERNEL_SECONDARY_IDX entries */
1914 tlb_flush(env, 1);
1915 break;
1916 case 5: /* TSB access */
1917 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
1918 PRIx64 "\n", env->dmmu.tsb, val);
1919 env->dmmu.tsb = val;
1920 break;
1921 case 6: /* Tag access */
1922 env->dmmu.tag_access = val;
1923 break;
1924 case 7: /* Virtual Watchpoint */
1925 case 8: /* Physical Watchpoint */
1926 default:
1927 env->dmmuregs[reg] = val;
1928 break;
1929 }
1930
1931 if (oldreg != env->dmmuregs[reg]) {
1932 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1933 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1934 }
1935 #ifdef DEBUG_MMU
1936 dump_mmu(stdout, fprintf, env);
1937 #endif
1938 return;
1939 }
1940 case 0x5c: /* D-MMU data in */
1941 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
1942 return;
1943 case 0x5d: /* D-MMU data access */
1944 {
1945 unsigned int i = (addr >> 3) & 0x3f;
1946
1947 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env);
1948
1949 #ifdef DEBUG_MMU
1950 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
1951 dump_mmu(stdout, fprintf, env);
1952 #endif
1953 return;
1954 }
1955 case 0x5f: /* D-MMU demap */
1956 demap_tlb(env->dtlb, addr, "dmmu", env);
1957 return;
1958 case 0x49: /* Interrupt data receive */
1959 /* XXX */
1960 return;
1961 case 0x46: /* D-cache data */
1962 case 0x47: /* D-cache tag access */
1963 case 0x4b: /* E-cache error enable */
1964 case 0x4c: /* E-cache asynchronous fault status */
1965 case 0x4d: /* E-cache asynchronous fault address */
1966 case 0x4e: /* E-cache tag data */
1967 case 0x66: /* I-cache instruction access */
1968 case 0x67: /* I-cache tag access */
1969 case 0x6e: /* I-cache predecode */
1970 case 0x6f: /* I-cache LRU etc. */
1971 case 0x76: /* E-cache tag */
1972 case 0x7e: /* E-cache tag */
1973 return;
1974 case 0x51: /* I-MMU 8k TSB pointer, RO */
1975 case 0x52: /* I-MMU 64k TSB pointer, RO */
1976 case 0x56: /* I-MMU tag read, RO */
1977 case 0x59: /* D-MMU 8k TSB pointer, RO */
1978 case 0x5a: /* D-MMU 64k TSB pointer, RO */
1979 case 0x5b: /* D-MMU data pointer, RO */
1980 case 0x5e: /* D-MMU tag read, RO */
1981 case 0x48: /* Interrupt dispatch, RO */
1982 case 0x7f: /* Incoming interrupt vector, RO */
1983 case 0x82: /* Primary no-fault, RO */
1984 case 0x83: /* Secondary no-fault, RO */
1985 case 0x8a: /* Primary no-fault LE, RO */
1986 case 0x8b: /* Secondary no-fault LE, RO */
1987 default:
1988 do_unassigned_access(addr, 1, 0, 1, size);
1989 return;
1990 }
1991 }
1992 #endif /* CONFIG_USER_ONLY */
1993
1994 void helper_ldda_asi(target_ulong addr, int asi, int rd)
1995 {
1996 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1997 || (cpu_has_hypervisor(env)
1998 && asi >= 0x30 && asi < 0x80
1999 && !(env->hpstate & HS_PRIV))) {
2000 helper_raise_exception(env, TT_PRIV_ACT);
2001 }
2002
2003 addr = asi_address_mask(env, asi, addr);
2004
2005 switch (asi) {
2006 #if !defined(CONFIG_USER_ONLY)
2007 case 0x24: /* Nucleus quad LDD 128 bit atomic */
2008 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE */
2009 helper_check_align(addr, 0xf);
2010 if (rd == 0) {
2011 env->gregs[1] = ldq_nucleus(addr + 8);
2012 if (asi == 0x2c) {
2013 bswap64s(&env->gregs[1]);
2014 }
2015 } else if (rd < 8) {
2016 env->gregs[rd] = ldq_nucleus(addr);
2017 env->gregs[rd + 1] = ldq_nucleus(addr + 8);
2018 if (asi == 0x2c) {
2019 bswap64s(&env->gregs[rd]);
2020 bswap64s(&env->gregs[rd + 1]);
2021 }
2022 } else {
2023 env->regwptr[rd] = ldq_nucleus(addr);
2024 env->regwptr[rd + 1] = ldq_nucleus(addr + 8);
2025 if (asi == 0x2c) {
2026 bswap64s(&env->regwptr[rd]);
2027 bswap64s(&env->regwptr[rd + 1]);
2028 }
2029 }
2030 break;
2031 #endif
2032 default:
2033 helper_check_align(addr, 0x3);
2034 if (rd == 0) {
2035 env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0);
2036 } else if (rd < 8) {
2037 env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0);
2038 env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2039 } else {
2040 env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0);
2041 env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2042 }
2043 break;
2044 }
2045 }
2046
2047 void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
2048 {
2049 unsigned int i;
2050 CPU_DoubleU u;
2051
2052 helper_check_align(addr, 3);
2053 addr = asi_address_mask(env, asi, addr);
2054
2055 switch (asi) {
2056 case 0xf0: /* UA2007/JPS1 Block load primary */
2057 case 0xf1: /* UA2007/JPS1 Block load secondary */
2058 case 0xf8: /* UA2007/JPS1 Block load primary LE */
2059 case 0xf9: /* UA2007/JPS1 Block load secondary LE */
2060 if (rd & 7) {
2061 helper_raise_exception(env, TT_ILL_INSN);
2062 return;
2063 }
2064 helper_check_align(addr, 0x3f);
2065 for (i = 0; i < 16; i++) {
2066 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4,
2067 0);
2068 addr += 4;
2069 }
2070
2071 return;
2072 case 0x16: /* UA2007 Block load primary, user privilege */
2073 case 0x17: /* UA2007 Block load secondary, user privilege */
2074 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2075 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2076 case 0x70: /* JPS1 Block load primary, user privilege */
2077 case 0x71: /* JPS1 Block load secondary, user privilege */
2078 case 0x78: /* JPS1 Block load primary LE, user privilege */
2079 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2080 if (rd & 7) {
2081 helper_raise_exception(env, TT_ILL_INSN);
2082 return;
2083 }
2084 helper_check_align(addr, 0x3f);
2085 for (i = 0; i < 16; i++) {
2086 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x19, 4,
2087 0);
2088 addr += 4;
2089 }
2090
2091 return;
2092 default:
2093 break;
2094 }
2095
2096 switch (size) {
2097 default:
2098 case 4:
2099 *((uint32_t *)&env->fpr[rd]) = helper_ld_asi(addr, asi, size, 0);
2100 break;
2101 case 8:
2102 u.ll = helper_ld_asi(addr, asi, size, 0);
2103 *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
2104 *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
2105 break;
2106 case 16:
2107 u.ll = helper_ld_asi(addr, asi, 8, 0);
2108 *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
2109 *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
2110 u.ll = helper_ld_asi(addr + 8, asi, 8, 0);
2111 *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
2112 *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
2113 break;
2114 }
2115 }
2116
2117 void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
2118 {
2119 unsigned int i;
2120 target_ulong val = 0;
2121 CPU_DoubleU u;
2122
2123 helper_check_align(addr, 3);
2124 addr = asi_address_mask(env, asi, addr);
2125
2126 switch (asi) {
2127 case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */
2128 case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */
2129 case 0xf0: /* UA2007/JPS1 Block store primary */
2130 case 0xf1: /* UA2007/JPS1 Block store secondary */
2131 case 0xf8: /* UA2007/JPS1 Block store primary LE */
2132 case 0xf9: /* UA2007/JPS1 Block store secondary LE */
2133 if (rd & 7) {
2134 helper_raise_exception(env, TT_ILL_INSN);
2135 return;
2136 }
2137 helper_check_align(addr, 0x3f);
2138 for (i = 0; i < 16; i++) {
2139 val = *(uint32_t *)&env->fpr[rd++];
2140 helper_st_asi(addr, val, asi & 0x8f, 4);
2141 addr += 4;
2142 }
2143
2144 return;
2145 case 0x16: /* UA2007 Block load primary, user privilege */
2146 case 0x17: /* UA2007 Block load secondary, user privilege */
2147 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2148 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2149 case 0x70: /* JPS1 Block store primary, user privilege */
2150 case 0x71: /* JPS1 Block store secondary, user privilege */
2151 case 0x78: /* JPS1 Block load primary LE, user privilege */
2152 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2153 if (rd & 7) {
2154 helper_raise_exception(env, TT_ILL_INSN);
2155 return;
2156 }
2157 helper_check_align(addr, 0x3f);
2158 for (i = 0; i < 16; i++) {
2159 val = *(uint32_t *)&env->fpr[rd++];
2160 helper_st_asi(addr, val, asi & 0x19, 4);
2161 addr += 4;
2162 }
2163
2164 return;
2165 default:
2166 break;
2167 }
2168
2169 switch (size) {
2170 default:
2171 case 4:
2172 helper_st_asi(addr, *(uint32_t *)&env->fpr[rd], asi, size);
2173 break;
2174 case 8:
2175 u.l.upper = *(uint32_t *)&env->fpr[rd++];
2176 u.l.lower = *(uint32_t *)&env->fpr[rd++];
2177 helper_st_asi(addr, u.ll, asi, size);
2178 break;
2179 case 16:
2180 u.l.upper = *(uint32_t *)&env->fpr[rd++];
2181 u.l.lower = *(uint32_t *)&env->fpr[rd++];
2182 helper_st_asi(addr, u.ll, asi, 8);
2183 u.l.upper = *(uint32_t *)&env->fpr[rd++];
2184 u.l.lower = *(uint32_t *)&env->fpr[rd++];
2185 helper_st_asi(addr + 8, u.ll, asi, 8);
2186 break;
2187 }
2188 }
2189
2190 target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
2191 target_ulong val2, uint32_t asi)
2192 {
2193 target_ulong ret;
2194
2195 val2 &= 0xffffffffUL;
2196 ret = helper_ld_asi(addr, asi, 4, 0);
2197 ret &= 0xffffffffUL;
2198 if (val2 == ret) {
2199 helper_st_asi(addr, val1 & 0xffffffffUL, asi, 4);
2200 }
2201 return ret;
2202 }
2203
2204 target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
2205 target_ulong val2, uint32_t asi)
2206 {
2207 target_ulong ret;
2208
2209 ret = helper_ld_asi(addr, asi, 8, 0);
2210 if (val2 == ret) {
2211 helper_st_asi(addr, val1, asi, 8);
2212 }
2213 return ret;
2214 }
2215 #endif /* TARGET_SPARC64 */
2216
2217 void helper_stdf(target_ulong addr, int mem_idx)
2218 {
2219 helper_check_align(addr, 7);
2220 #if !defined(CONFIG_USER_ONLY)
2221 switch (mem_idx) {
2222 case MMU_USER_IDX:
2223 stfq_user(addr, DT0);
2224 break;
2225 case MMU_KERNEL_IDX:
2226 stfq_kernel(addr, DT0);
2227 break;
2228 #ifdef TARGET_SPARC64
2229 case MMU_HYPV_IDX:
2230 stfq_hypv(addr, DT0);
2231 break;
2232 #endif
2233 default:
2234 DPRINTF_MMU("helper_stdf: need to check MMU idx %d\n", mem_idx);
2235 break;
2236 }
2237 #else
2238 stfq_raw(address_mask(env, addr), DT0);
2239 #endif
2240 }
2241
2242 void helper_lddf(target_ulong addr, int mem_idx)
2243 {
2244 helper_check_align(addr, 7);
2245 #if !defined(CONFIG_USER_ONLY)
2246 switch (mem_idx) {
2247 case MMU_USER_IDX:
2248 DT0 = ldfq_user(addr);
2249 break;
2250 case MMU_KERNEL_IDX:
2251 DT0 = ldfq_kernel(addr);
2252 break;
2253 #ifdef TARGET_SPARC64
2254 case MMU_HYPV_IDX:
2255 DT0 = ldfq_hypv(addr);
2256 break;
2257 #endif
2258 default:
2259 DPRINTF_MMU("helper_lddf: need to check MMU idx %d\n", mem_idx);
2260 break;
2261 }
2262 #else
2263 DT0 = ldfq_raw(address_mask(env, addr));
2264 #endif
2265 }
2266
2267 void helper_ldqf(target_ulong addr, int mem_idx)
2268 {
2269 /* XXX add 128 bit load */
2270 CPU_QuadU u;
2271
2272 helper_check_align(addr, 7);
2273 #if !defined(CONFIG_USER_ONLY)
2274 switch (mem_idx) {
2275 case MMU_USER_IDX:
2276 u.ll.upper = ldq_user(addr);
2277 u.ll.lower = ldq_user(addr + 8);
2278 QT0 = u.q;
2279 break;
2280 case MMU_KERNEL_IDX:
2281 u.ll.upper = ldq_kernel(addr);
2282 u.ll.lower = ldq_kernel(addr + 8);
2283 QT0 = u.q;
2284 break;
2285 #ifdef TARGET_SPARC64
2286 case MMU_HYPV_IDX:
2287 u.ll.upper = ldq_hypv(addr);
2288 u.ll.lower = ldq_hypv(addr + 8);
2289 QT0 = u.q;
2290 break;
2291 #endif
2292 default:
2293 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx);
2294 break;
2295 }
2296 #else
2297 u.ll.upper = ldq_raw(address_mask(env, addr));
2298 u.ll.lower = ldq_raw(address_mask(env, addr + 8));
2299 QT0 = u.q;
2300 #endif
2301 }
2302
2303 void helper_stqf(target_ulong addr, int mem_idx)
2304 {
2305 /* XXX add 128 bit store */
2306 CPU_QuadU u;
2307
2308 helper_check_align(addr, 7);
2309 #if !defined(CONFIG_USER_ONLY)
2310 switch (mem_idx) {
2311 case MMU_USER_IDX:
2312 u.q = QT0;
2313 stq_user(addr, u.ll.upper);
2314 stq_user(addr + 8, u.ll.lower);
2315 break;
2316 case MMU_KERNEL_IDX:
2317 u.q = QT0;
2318 stq_kernel(addr, u.ll.upper);
2319 stq_kernel(addr + 8, u.ll.lower);
2320 break;
2321 #ifdef TARGET_SPARC64
2322 case MMU_HYPV_IDX:
2323 u.q = QT0;
2324 stq_hypv(addr, u.ll.upper);
2325 stq_hypv(addr + 8, u.ll.lower);
2326 break;
2327 #endif
2328 default:
2329 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx);
2330 break;
2331 }
2332 #else
2333 u.q = QT0;
2334 stq_raw(address_mask(env, addr), u.ll.upper);
2335 stq_raw(address_mask(env, addr + 8), u.ll.lower);
2336 #endif
2337 }
2338
2339 #ifndef TARGET_SPARC64
2340 #if !defined(CONFIG_USER_ONLY)
2341 static void do_unassigned_access(target_phys_addr_t addr, int is_write,
2342 int is_exec, int is_asi, int size)
2343 {
2344 int fault_type;
2345
2346 #ifdef DEBUG_UNASSIGNED
2347 if (is_asi) {
2348 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2349 " asi 0x%02x from " TARGET_FMT_lx "\n",
2350 is_exec ? "exec" : is_write ? "write" : "read", size,
2351 size == 1 ? "" : "s", addr, is_asi, env->pc);
2352 } else {
2353 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2354 " from " TARGET_FMT_lx "\n",
2355 is_exec ? "exec" : is_write ? "write" : "read", size,
2356 size == 1 ? "" : "s", addr, env->pc);
2357 }
2358 #endif
2359 /* Don't overwrite translation and access faults */
2360 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
2361 if ((fault_type > 4) || (fault_type == 0)) {
2362 env->mmuregs[3] = 0; /* Fault status register */
2363 if (is_asi) {
2364 env->mmuregs[3] |= 1 << 16;
2365 }
2366 if (env->psrs) {
2367 env->mmuregs[3] |= 1 << 5;
2368 }
2369 if (is_exec) {
2370 env->mmuregs[3] |= 1 << 6;
2371 }
2372 if (is_write) {
2373 env->mmuregs[3] |= 1 << 7;
2374 }
2375 env->mmuregs[3] |= (5 << 2) | 2;
2376 /* SuperSPARC will never place instruction fault addresses in the FAR */
2377 if (!is_exec) {
2378 env->mmuregs[4] = addr; /* Fault address register */
2379 }
2380 }
2381 /* overflow (same type fault was not read before another fault) */
2382 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
2383 env->mmuregs[3] |= 1;
2384 }
2385
2386 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
2387 if (is_exec) {
2388 helper_raise_exception(env, TT_CODE_ACCESS);
2389 } else {
2390 helper_raise_exception(env, TT_DATA_ACCESS);
2391 }
2392 }
2393
2394 /* flush neverland mappings created during no-fault mode,
2395 so the sequential MMU faults report proper fault types */
2396 if (env->mmuregs[0] & MMU_NF) {
2397 tlb_flush(env, 1);
2398 }
2399 }
2400 #endif
2401 #else
2402 #if defined(CONFIG_USER_ONLY)
2403 static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
2404 int is_asi, int size)
2405 #else
2406 static void do_unassigned_access(target_phys_addr_t addr, int is_write,
2407 int is_exec, int is_asi, int size)
2408 #endif
2409 {
2410 #ifdef DEBUG_UNASSIGNED
2411 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
2412 "\n", addr, env->pc);
2413 #endif
2414
2415 if (is_exec) {
2416 helper_raise_exception(env, TT_CODE_ACCESS);
2417 } else {
2418 helper_raise_exception(env, TT_DATA_ACCESS);
2419 }
2420 }
2421 #endif
2422
2423 #if !defined(CONFIG_USER_ONLY)
2424 void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
2425 int is_write, int is_exec, int is_asi, int size)
2426 {
2427 CPUState *saved_env;
2428
2429 saved_env = env;
2430 env = env1;
2431 do_unassigned_access(addr, is_write, is_exec, is_asi, size);
2432 env = saved_env;
2433 }
2434 #endif
Qemu copy for testing