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Sparc: avoid AREG0 for memory access helpers
[qemu.git] / target-sparc / ldst_helper.c
1 /*
2 * Helpers for loads and stores
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "helper.h"
22
23 //#define DEBUG_MMU
24 //#define DEBUG_MXCC
25 //#define DEBUG_UNALIGNED
26 //#define DEBUG_UNASSIGNED
27 //#define DEBUG_ASI
28 //#define DEBUG_CACHE_CONTROL
29
30 #ifdef DEBUG_MMU
31 #define DPRINTF_MMU(fmt, ...) \
32 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
33 #else
34 #define DPRINTF_MMU(fmt, ...) do {} while (0)
35 #endif
36
37 #ifdef DEBUG_MXCC
38 #define DPRINTF_MXCC(fmt, ...) \
39 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
40 #else
41 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
42 #endif
43
44 #ifdef DEBUG_ASI
45 #define DPRINTF_ASI(fmt, ...) \
46 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
47 #endif
48
49 #ifdef DEBUG_CACHE_CONTROL
50 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
51 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
52 #else
53 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
54 #endif
55
56 #ifdef TARGET_SPARC64
57 #ifndef TARGET_ABI32
58 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
59 #else
60 #define AM_CHECK(env1) (1)
61 #endif
62 #endif
63
64 #define QT0 (env->qt0)
65 #define QT1 (env->qt1)
66
67 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
68 /* Calculates TSB pointer value for fault page size 8k or 64k */
69 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
70 uint64_t tag_access_register,
71 int page_size)
72 {
73 uint64_t tsb_base = tsb_register & ~0x1fffULL;
74 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
75 int tsb_size = tsb_register & 0xf;
76
77 /* discard lower 13 bits which hold tag access context */
78 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
79
80 /* now reorder bits */
81 uint64_t tsb_base_mask = ~0x1fffULL;
82 uint64_t va = tag_access_va;
83
84 /* move va bits to correct position */
85 if (page_size == 8*1024) {
86 va >>= 9;
87 } else if (page_size == 64*1024) {
88 va >>= 12;
89 }
90
91 if (tsb_size) {
92 tsb_base_mask <<= tsb_size;
93 }
94
95 /* calculate tsb_base mask and adjust va if split is in use */
96 if (tsb_split) {
97 if (page_size == 8*1024) {
98 va &= ~(1ULL << (13 + tsb_size));
99 } else if (page_size == 64*1024) {
100 va |= (1ULL << (13 + tsb_size));
101 }
102 tsb_base_mask <<= 1;
103 }
104
105 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
106 }
107
108 /* Calculates tag target register value by reordering bits
109 in tag access register */
110 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
111 {
112 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
113 }
114
115 static void replace_tlb_entry(SparcTLBEntry *tlb,
116 uint64_t tlb_tag, uint64_t tlb_tte,
117 CPUSPARCState *env1)
118 {
119 target_ulong mask, size, va, offset;
120
121 /* flush page range if translation is valid */
122 if (TTE_IS_VALID(tlb->tte)) {
123
124 mask = 0xffffffffffffe000ULL;
125 mask <<= 3 * ((tlb->tte >> 61) & 3);
126 size = ~mask + 1;
127
128 va = tlb->tag & mask;
129
130 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
131 tlb_flush_page(env1, va + offset);
132 }
133 }
134
135 tlb->tag = tlb_tag;
136 tlb->tte = tlb_tte;
137 }
138
139 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
140 const char *strmmu, CPUSPARCState *env1)
141 {
142 unsigned int i;
143 target_ulong mask;
144 uint64_t context;
145
146 int is_demap_context = (demap_addr >> 6) & 1;
147
148 /* demap context */
149 switch ((demap_addr >> 4) & 3) {
150 case 0: /* primary */
151 context = env1->dmmu.mmu_primary_context;
152 break;
153 case 1: /* secondary */
154 context = env1->dmmu.mmu_secondary_context;
155 break;
156 case 2: /* nucleus */
157 context = 0;
158 break;
159 case 3: /* reserved */
160 default:
161 return;
162 }
163
164 for (i = 0; i < 64; i++) {
165 if (TTE_IS_VALID(tlb[i].tte)) {
166
167 if (is_demap_context) {
168 /* will remove non-global entries matching context value */
169 if (TTE_IS_GLOBAL(tlb[i].tte) ||
170 !tlb_compare_context(&tlb[i], context)) {
171 continue;
172 }
173 } else {
174 /* demap page
175 will remove any entry matching VA */
176 mask = 0xffffffffffffe000ULL;
177 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
178
179 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
180 continue;
181 }
182
183 /* entry should be global or matching context value */
184 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
185 !tlb_compare_context(&tlb[i], context)) {
186 continue;
187 }
188 }
189
190 replace_tlb_entry(&tlb[i], 0, 0, env1);
191 #ifdef DEBUG_MMU
192 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
193 dump_mmu(stdout, fprintf, env1);
194 #endif
195 }
196 }
197 }
198
199 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
200 uint64_t tlb_tag, uint64_t tlb_tte,
201 const char *strmmu, CPUSPARCState *env1)
202 {
203 unsigned int i, replace_used;
204
205 /* Try replacing invalid entry */
206 for (i = 0; i < 64; i++) {
207 if (!TTE_IS_VALID(tlb[i].tte)) {
208 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
209 #ifdef DEBUG_MMU
210 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
211 dump_mmu(stdout, fprintf, env1);
212 #endif
213 return;
214 }
215 }
216
217 /* All entries are valid, try replacing unlocked entry */
218
219 for (replace_used = 0; replace_used < 2; ++replace_used) {
220
221 /* Used entries are not replaced on first pass */
222
223 for (i = 0; i < 64; i++) {
224 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
225
226 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
227 #ifdef DEBUG_MMU
228 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
229 strmmu, (replace_used ? "used" : "unused"), i);
230 dump_mmu(stdout, fprintf, env1);
231 #endif
232 return;
233 }
234 }
235
236 /* Now reset used bit and search for unused entries again */
237
238 for (i = 0; i < 64; i++) {
239 TTE_SET_UNUSED(tlb[i].tte);
240 }
241 }
242
243 #ifdef DEBUG_MMU
244 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
245 #endif
246 /* error state? */
247 }
248
249 #endif
250
251 static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr)
252 {
253 #ifdef TARGET_SPARC64
254 if (AM_CHECK(env1)) {
255 addr &= 0xffffffffULL;
256 }
257 #endif
258 return addr;
259 }
260
261 /* returns true if access using this ASI is to have address translated by MMU
262 otherwise access is to raw physical address */
263 static inline int is_translating_asi(int asi)
264 {
265 #ifdef TARGET_SPARC64
266 /* Ultrasparc IIi translating asi
267 - note this list is defined by cpu implementation
268 */
269 switch (asi) {
270 case 0x04 ... 0x11:
271 case 0x16 ... 0x19:
272 case 0x1E ... 0x1F:
273 case 0x24 ... 0x2C:
274 case 0x70 ... 0x73:
275 case 0x78 ... 0x79:
276 case 0x80 ... 0xFF:
277 return 1;
278
279 default:
280 return 0;
281 }
282 #else
283 /* TODO: check sparc32 bits */
284 return 0;
285 #endif
286 }
287
288 static inline target_ulong asi_address_mask(CPUSPARCState *env,
289 int asi, target_ulong addr)
290 {
291 if (is_translating_asi(asi)) {
292 return address_mask(env, addr);
293 } else {
294 return addr;
295 }
296 }
297
298 void helper_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align)
299 {
300 if (addr & align) {
301 #ifdef DEBUG_UNALIGNED
302 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
303 "\n", addr, env->pc);
304 #endif
305 helper_raise_exception(env, TT_UNALIGNED);
306 }
307 }
308
309 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
310 defined(DEBUG_MXCC)
311 static void dump_mxcc(CPUSPARCState *env)
312 {
313 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
314 "\n",
315 env->mxccdata[0], env->mxccdata[1],
316 env->mxccdata[2], env->mxccdata[3]);
317 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
318 "\n"
319 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
320 "\n",
321 env->mxccregs[0], env->mxccregs[1],
322 env->mxccregs[2], env->mxccregs[3],
323 env->mxccregs[4], env->mxccregs[5],
324 env->mxccregs[6], env->mxccregs[7]);
325 }
326 #endif
327
328 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
329 && defined(DEBUG_ASI)
330 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
331 uint64_t r1)
332 {
333 switch (size) {
334 case 1:
335 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
336 addr, asi, r1 & 0xff);
337 break;
338 case 2:
339 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
340 addr, asi, r1 & 0xffff);
341 break;
342 case 4:
343 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
344 addr, asi, r1 & 0xffffffff);
345 break;
346 case 8:
347 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
348 addr, asi, r1);
349 break;
350 }
351 }
352 #endif
353
354 #ifndef TARGET_SPARC64
355 #ifndef CONFIG_USER_ONLY
356
357
358 /* Leon3 cache control */
359
360 static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr,
361 uint64_t val, int size)
362 {
363 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
364 addr, val, size);
365
366 if (size != 4) {
367 DPRINTF_CACHE_CONTROL("32bits only\n");
368 return;
369 }
370
371 switch (addr) {
372 case 0x00: /* Cache control */
373
374 /* These values must always be read as zeros */
375 val &= ~CACHE_CTRL_FD;
376 val &= ~CACHE_CTRL_FI;
377 val &= ~CACHE_CTRL_IB;
378 val &= ~CACHE_CTRL_IP;
379 val &= ~CACHE_CTRL_DP;
380
381 env->cache_control = val;
382 break;
383 case 0x04: /* Instruction cache configuration */
384 case 0x08: /* Data cache configuration */
385 /* Read Only */
386 break;
387 default:
388 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
389 break;
390 };
391 }
392
393 static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr,
394 int size)
395 {
396 uint64_t ret = 0;
397
398 if (size != 4) {
399 DPRINTF_CACHE_CONTROL("32bits only\n");
400 return 0;
401 }
402
403 switch (addr) {
404 case 0x00: /* Cache control */
405 ret = env->cache_control;
406 break;
407
408 /* Configuration registers are read and only always keep those
409 predefined values */
410
411 case 0x04: /* Instruction cache configuration */
412 ret = 0x10220000;
413 break;
414 case 0x08: /* Data cache configuration */
415 ret = 0x18220000;
416 break;
417 default:
418 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
419 break;
420 };
421 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
422 addr, ret, size);
423 return ret;
424 }
425
426 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
427 int sign)
428 {
429 uint64_t ret = 0;
430 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
431 uint32_t last_addr = addr;
432 #endif
433
434 helper_check_align(env, addr, size - 1);
435 switch (asi) {
436 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
437 switch (addr) {
438 case 0x00: /* Leon3 Cache Control */
439 case 0x08: /* Leon3 Instruction Cache config */
440 case 0x0C: /* Leon3 Date Cache config */
441 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
442 ret = leon3_cache_control_ld(env, addr, size);
443 }
444 break;
445 case 0x01c00a00: /* MXCC control register */
446 if (size == 8) {
447 ret = env->mxccregs[3];
448 } else {
449 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
450 size);
451 }
452 break;
453 case 0x01c00a04: /* MXCC control register */
454 if (size == 4) {
455 ret = env->mxccregs[3];
456 } else {
457 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
458 size);
459 }
460 break;
461 case 0x01c00c00: /* Module reset register */
462 if (size == 8) {
463 ret = env->mxccregs[5];
464 /* should we do something here? */
465 } else {
466 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
467 size);
468 }
469 break;
470 case 0x01c00f00: /* MBus port address register */
471 if (size == 8) {
472 ret = env->mxccregs[7];
473 } else {
474 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
475 size);
476 }
477 break;
478 default:
479 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
480 size);
481 break;
482 }
483 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
484 "addr = %08x -> ret = %" PRIx64 ","
485 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
486 #ifdef DEBUG_MXCC
487 dump_mxcc(env);
488 #endif
489 break;
490 case 3: /* MMU probe */
491 {
492 int mmulev;
493
494 mmulev = (addr >> 8) & 15;
495 if (mmulev > 4) {
496 ret = 0;
497 } else {
498 ret = mmu_probe(env, addr, mmulev);
499 }
500 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
501 addr, mmulev, ret);
502 }
503 break;
504 case 4: /* read MMU regs */
505 {
506 int reg = (addr >> 8) & 0x1f;
507
508 ret = env->mmuregs[reg];
509 if (reg == 3) { /* Fault status cleared on read */
510 env->mmuregs[3] = 0;
511 } else if (reg == 0x13) { /* Fault status read */
512 ret = env->mmuregs[3];
513 } else if (reg == 0x14) { /* Fault address read */
514 ret = env->mmuregs[4];
515 }
516 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
517 }
518 break;
519 case 5: /* Turbosparc ITLB Diagnostic */
520 case 6: /* Turbosparc DTLB Diagnostic */
521 case 7: /* Turbosparc IOTLB Diagnostic */
522 break;
523 case 9: /* Supervisor code access */
524 switch (size) {
525 case 1:
526 ret = ldub_code(addr);
527 break;
528 case 2:
529 ret = lduw_code(addr);
530 break;
531 default:
532 case 4:
533 ret = ldl_code(addr);
534 break;
535 case 8:
536 ret = ldq_code(addr);
537 break;
538 }
539 break;
540 case 0xa: /* User data access */
541 switch (size) {
542 case 1:
543 ret = cpu_ldub_user(env, addr);
544 break;
545 case 2:
546 ret = cpu_lduw_user(env, addr);
547 break;
548 default:
549 case 4:
550 ret = cpu_ldl_user(env, addr);
551 break;
552 case 8:
553 ret = cpu_ldq_user(env, addr);
554 break;
555 }
556 break;
557 case 0xb: /* Supervisor data access */
558 switch (size) {
559 case 1:
560 ret = cpu_ldub_kernel(env, addr);
561 break;
562 case 2:
563 ret = cpu_lduw_kernel(env, addr);
564 break;
565 default:
566 case 4:
567 ret = cpu_ldl_kernel(env, addr);
568 break;
569 case 8:
570 ret = cpu_ldq_kernel(env, addr);
571 break;
572 }
573 break;
574 case 0xc: /* I-cache tag */
575 case 0xd: /* I-cache data */
576 case 0xe: /* D-cache tag */
577 case 0xf: /* D-cache data */
578 break;
579 case 0x20: /* MMU passthrough */
580 switch (size) {
581 case 1:
582 ret = ldub_phys(addr);
583 break;
584 case 2:
585 ret = lduw_phys(addr);
586 break;
587 default:
588 case 4:
589 ret = ldl_phys(addr);
590 break;
591 case 8:
592 ret = ldq_phys(addr);
593 break;
594 }
595 break;
596 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
597 switch (size) {
598 case 1:
599 ret = ldub_phys((target_phys_addr_t)addr
600 | ((target_phys_addr_t)(asi & 0xf) << 32));
601 break;
602 case 2:
603 ret = lduw_phys((target_phys_addr_t)addr
604 | ((target_phys_addr_t)(asi & 0xf) << 32));
605 break;
606 default:
607 case 4:
608 ret = ldl_phys((target_phys_addr_t)addr
609 | ((target_phys_addr_t)(asi & 0xf) << 32));
610 break;
611 case 8:
612 ret = ldq_phys((target_phys_addr_t)addr
613 | ((target_phys_addr_t)(asi & 0xf) << 32));
614 break;
615 }
616 break;
617 case 0x30: /* Turbosparc secondary cache diagnostic */
618 case 0x31: /* Turbosparc RAM snoop */
619 case 0x32: /* Turbosparc page table descriptor diagnostic */
620 case 0x39: /* data cache diagnostic register */
621 ret = 0;
622 break;
623 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
624 {
625 int reg = (addr >> 8) & 3;
626
627 switch (reg) {
628 case 0: /* Breakpoint Value (Addr) */
629 ret = env->mmubpregs[reg];
630 break;
631 case 1: /* Breakpoint Mask */
632 ret = env->mmubpregs[reg];
633 break;
634 case 2: /* Breakpoint Control */
635 ret = env->mmubpregs[reg];
636 break;
637 case 3: /* Breakpoint Status */
638 ret = env->mmubpregs[reg];
639 env->mmubpregs[reg] = 0ULL;
640 break;
641 }
642 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
643 ret);
644 }
645 break;
646 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
647 ret = env->mmubpctrv;
648 break;
649 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
650 ret = env->mmubpctrc;
651 break;
652 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
653 ret = env->mmubpctrs;
654 break;
655 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
656 ret = env->mmubpaction;
657 break;
658 case 8: /* User code access, XXX */
659 default:
660 cpu_unassigned_access(env, addr, 0, 0, asi, size);
661 ret = 0;
662 break;
663 }
664 if (sign) {
665 switch (size) {
666 case 1:
667 ret = (int8_t) ret;
668 break;
669 case 2:
670 ret = (int16_t) ret;
671 break;
672 case 4:
673 ret = (int32_t) ret;
674 break;
675 default:
676 break;
677 }
678 }
679 #ifdef DEBUG_ASI
680 dump_asi("read ", last_addr, asi, size, ret);
681 #endif
682 return ret;
683 }
684
685 void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
686 int size)
687 {
688 helper_check_align(env, addr, size - 1);
689 switch (asi) {
690 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
691 switch (addr) {
692 case 0x00: /* Leon3 Cache Control */
693 case 0x08: /* Leon3 Instruction Cache config */
694 case 0x0C: /* Leon3 Date Cache config */
695 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
696 leon3_cache_control_st(env, addr, val, size);
697 }
698 break;
699
700 case 0x01c00000: /* MXCC stream data register 0 */
701 if (size == 8) {
702 env->mxccdata[0] = val;
703 } else {
704 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
705 size);
706 }
707 break;
708 case 0x01c00008: /* MXCC stream data register 1 */
709 if (size == 8) {
710 env->mxccdata[1] = val;
711 } else {
712 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
713 size);
714 }
715 break;
716 case 0x01c00010: /* MXCC stream data register 2 */
717 if (size == 8) {
718 env->mxccdata[2] = val;
719 } else {
720 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
721 size);
722 }
723 break;
724 case 0x01c00018: /* MXCC stream data register 3 */
725 if (size == 8) {
726 env->mxccdata[3] = val;
727 } else {
728 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
729 size);
730 }
731 break;
732 case 0x01c00100: /* MXCC stream source */
733 if (size == 8) {
734 env->mxccregs[0] = val;
735 } else {
736 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
737 size);
738 }
739 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
740 0);
741 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
742 8);
743 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
744 16);
745 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
746 24);
747 break;
748 case 0x01c00200: /* MXCC stream destination */
749 if (size == 8) {
750 env->mxccregs[1] = val;
751 } else {
752 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
753 size);
754 }
755 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
756 env->mxccdata[0]);
757 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
758 env->mxccdata[1]);
759 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
760 env->mxccdata[2]);
761 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
762 env->mxccdata[3]);
763 break;
764 case 0x01c00a00: /* MXCC control register */
765 if (size == 8) {
766 env->mxccregs[3] = val;
767 } else {
768 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
769 size);
770 }
771 break;
772 case 0x01c00a04: /* MXCC control register */
773 if (size == 4) {
774 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
775 | val;
776 } else {
777 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
778 size);
779 }
780 break;
781 case 0x01c00e00: /* MXCC error register */
782 /* writing a 1 bit clears the error */
783 if (size == 8) {
784 env->mxccregs[6] &= ~val;
785 } else {
786 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
787 size);
788 }
789 break;
790 case 0x01c00f00: /* MBus port address register */
791 if (size == 8) {
792 env->mxccregs[7] = val;
793 } else {
794 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
795 size);
796 }
797 break;
798 default:
799 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
800 size);
801 break;
802 }
803 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
804 asi, size, addr, val);
805 #ifdef DEBUG_MXCC
806 dump_mxcc(env);
807 #endif
808 break;
809 case 3: /* MMU flush */
810 {
811 int mmulev;
812
813 mmulev = (addr >> 8) & 15;
814 DPRINTF_MMU("mmu flush level %d\n", mmulev);
815 switch (mmulev) {
816 case 0: /* flush page */
817 tlb_flush_page(env, addr & 0xfffff000);
818 break;
819 case 1: /* flush segment (256k) */
820 case 2: /* flush region (16M) */
821 case 3: /* flush context (4G) */
822 case 4: /* flush entire */
823 tlb_flush(env, 1);
824 break;
825 default:
826 break;
827 }
828 #ifdef DEBUG_MMU
829 dump_mmu(stdout, fprintf, env);
830 #endif
831 }
832 break;
833 case 4: /* write MMU regs */
834 {
835 int reg = (addr >> 8) & 0x1f;
836 uint32_t oldreg;
837
838 oldreg = env->mmuregs[reg];
839 switch (reg) {
840 case 0: /* Control Register */
841 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
842 (val & 0x00ffffff);
843 /* Mappings generated during no-fault mode or MMU
844 disabled mode are invalid in normal mode */
845 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
846 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) {
847 tlb_flush(env, 1);
848 }
849 break;
850 case 1: /* Context Table Pointer Register */
851 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
852 break;
853 case 2: /* Context Register */
854 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
855 if (oldreg != env->mmuregs[reg]) {
856 /* we flush when the MMU context changes because
857 QEMU has no MMU context support */
858 tlb_flush(env, 1);
859 }
860 break;
861 case 3: /* Synchronous Fault Status Register with Clear */
862 case 4: /* Synchronous Fault Address Register */
863 break;
864 case 0x10: /* TLB Replacement Control Register */
865 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
866 break;
867 case 0x13: /* Synchronous Fault Status Register with Read
868 and Clear */
869 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
870 break;
871 case 0x14: /* Synchronous Fault Address Register */
872 env->mmuregs[4] = val;
873 break;
874 default:
875 env->mmuregs[reg] = val;
876 break;
877 }
878 if (oldreg != env->mmuregs[reg]) {
879 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
880 reg, oldreg, env->mmuregs[reg]);
881 }
882 #ifdef DEBUG_MMU
883 dump_mmu(stdout, fprintf, env);
884 #endif
885 }
886 break;
887 case 5: /* Turbosparc ITLB Diagnostic */
888 case 6: /* Turbosparc DTLB Diagnostic */
889 case 7: /* Turbosparc IOTLB Diagnostic */
890 break;
891 case 0xa: /* User data access */
892 switch (size) {
893 case 1:
894 cpu_stb_user(env, addr, val);
895 break;
896 case 2:
897 cpu_stw_user(env, addr, val);
898 break;
899 default:
900 case 4:
901 cpu_stl_user(env, addr, val);
902 break;
903 case 8:
904 cpu_stq_user(env, addr, val);
905 break;
906 }
907 break;
908 case 0xb: /* Supervisor data access */
909 switch (size) {
910 case 1:
911 cpu_stb_kernel(env, addr, val);
912 break;
913 case 2:
914 cpu_stw_kernel(env, addr, val);
915 break;
916 default:
917 case 4:
918 cpu_stl_kernel(env, addr, val);
919 break;
920 case 8:
921 cpu_stq_kernel(env, addr, val);
922 break;
923 }
924 break;
925 case 0xc: /* I-cache tag */
926 case 0xd: /* I-cache data */
927 case 0xe: /* D-cache tag */
928 case 0xf: /* D-cache data */
929 case 0x10: /* I/D-cache flush page */
930 case 0x11: /* I/D-cache flush segment */
931 case 0x12: /* I/D-cache flush region */
932 case 0x13: /* I/D-cache flush context */
933 case 0x14: /* I/D-cache flush user */
934 break;
935 case 0x17: /* Block copy, sta access */
936 {
937 /* val = src
938 addr = dst
939 copy 32 bytes */
940 unsigned int i;
941 uint32_t src = val & ~3, dst = addr & ~3, temp;
942
943 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
944 temp = cpu_ldl_kernel(env, src);
945 cpu_stl_kernel(env, dst, temp);
946 }
947 }
948 break;
949 case 0x1f: /* Block fill, stda access */
950 {
951 /* addr = dst
952 fill 32 bytes with val */
953 unsigned int i;
954 uint32_t dst = addr & 7;
955
956 for (i = 0; i < 32; i += 8, dst += 8) {
957 cpu_stq_kernel(env, dst, val);
958 }
959 }
960 break;
961 case 0x20: /* MMU passthrough */
962 {
963 switch (size) {
964 case 1:
965 stb_phys(addr, val);
966 break;
967 case 2:
968 stw_phys(addr, val);
969 break;
970 case 4:
971 default:
972 stl_phys(addr, val);
973 break;
974 case 8:
975 stq_phys(addr, val);
976 break;
977 }
978 }
979 break;
980 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
981 {
982 switch (size) {
983 case 1:
984 stb_phys((target_phys_addr_t)addr
985 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
986 break;
987 case 2:
988 stw_phys((target_phys_addr_t)addr
989 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
990 break;
991 case 4:
992 default:
993 stl_phys((target_phys_addr_t)addr
994 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
995 break;
996 case 8:
997 stq_phys((target_phys_addr_t)addr
998 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
999 break;
1000 }
1001 }
1002 break;
1003 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1004 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1005 Turbosparc snoop RAM */
1006 case 0x32: /* store buffer control or Turbosparc page table
1007 descriptor diagnostic */
1008 case 0x36: /* I-cache flash clear */
1009 case 0x37: /* D-cache flash clear */
1010 break;
1011 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1012 {
1013 int reg = (addr >> 8) & 3;
1014
1015 switch (reg) {
1016 case 0: /* Breakpoint Value (Addr) */
1017 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1018 break;
1019 case 1: /* Breakpoint Mask */
1020 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1021 break;
1022 case 2: /* Breakpoint Control */
1023 env->mmubpregs[reg] = (val & 0x7fULL);
1024 break;
1025 case 3: /* Breakpoint Status */
1026 env->mmubpregs[reg] = (val & 0xfULL);
1027 break;
1028 }
1029 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
1030 env->mmuregs[reg]);
1031 }
1032 break;
1033 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1034 env->mmubpctrv = val & 0xffffffff;
1035 break;
1036 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1037 env->mmubpctrc = val & 0x3;
1038 break;
1039 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1040 env->mmubpctrs = val & 0x3;
1041 break;
1042 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1043 env->mmubpaction = val & 0x1fff;
1044 break;
1045 case 8: /* User code access, XXX */
1046 case 9: /* Supervisor code access, XXX */
1047 default:
1048 cpu_unassigned_access(env, addr, 1, 0, asi, size);
1049 break;
1050 }
1051 #ifdef DEBUG_ASI
1052 dump_asi("write", addr, asi, size, val);
1053 #endif
1054 }
1055
1056 #endif /* CONFIG_USER_ONLY */
1057 #else /* TARGET_SPARC64 */
1058
1059 #ifdef CONFIG_USER_ONLY
1060 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1061 int sign)
1062 {
1063 uint64_t ret = 0;
1064 #if defined(DEBUG_ASI)
1065 target_ulong last_addr = addr;
1066 #endif
1067
1068 if (asi < 0x80) {
1069 helper_raise_exception(env, TT_PRIV_ACT);
1070 }
1071
1072 helper_check_align(env, addr, size - 1);
1073 addr = asi_address_mask(env, asi, addr);
1074
1075 switch (asi) {
1076 case 0x82: /* Primary no-fault */
1077 case 0x8a: /* Primary no-fault LE */
1078 if (page_check_range(addr, size, PAGE_READ) == -1) {
1079 #ifdef DEBUG_ASI
1080 dump_asi("read ", last_addr, asi, size, ret);
1081 #endif
1082 return 0;
1083 }
1084 /* Fall through */
1085 case 0x80: /* Primary */
1086 case 0x88: /* Primary LE */
1087 {
1088 switch (size) {
1089 case 1:
1090 ret = ldub_raw(addr);
1091 break;
1092 case 2:
1093 ret = lduw_raw(addr);
1094 break;
1095 case 4:
1096 ret = ldl_raw(addr);
1097 break;
1098 default:
1099 case 8:
1100 ret = ldq_raw(addr);
1101 break;
1102 }
1103 }
1104 break;
1105 case 0x83: /* Secondary no-fault */
1106 case 0x8b: /* Secondary no-fault LE */
1107 if (page_check_range(addr, size, PAGE_READ) == -1) {
1108 #ifdef DEBUG_ASI
1109 dump_asi("read ", last_addr, asi, size, ret);
1110 #endif
1111 return 0;
1112 }
1113 /* Fall through */
1114 case 0x81: /* Secondary */
1115 case 0x89: /* Secondary LE */
1116 /* XXX */
1117 break;
1118 default:
1119 break;
1120 }
1121
1122 /* Convert from little endian */
1123 switch (asi) {
1124 case 0x88: /* Primary LE */
1125 case 0x89: /* Secondary LE */
1126 case 0x8a: /* Primary no-fault LE */
1127 case 0x8b: /* Secondary no-fault LE */
1128 switch (size) {
1129 case 2:
1130 ret = bswap16(ret);
1131 break;
1132 case 4:
1133 ret = bswap32(ret);
1134 break;
1135 case 8:
1136 ret = bswap64(ret);
1137 break;
1138 default:
1139 break;
1140 }
1141 default:
1142 break;
1143 }
1144
1145 /* Convert to signed number */
1146 if (sign) {
1147 switch (size) {
1148 case 1:
1149 ret = (int8_t) ret;
1150 break;
1151 case 2:
1152 ret = (int16_t) ret;
1153 break;
1154 case 4:
1155 ret = (int32_t) ret;
1156 break;
1157 default:
1158 break;
1159 }
1160 }
1161 #ifdef DEBUG_ASI
1162 dump_asi("read ", last_addr, asi, size, ret);
1163 #endif
1164 return ret;
1165 }
1166
1167 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1168 int asi, int size)
1169 {
1170 #ifdef DEBUG_ASI
1171 dump_asi("write", addr, asi, size, val);
1172 #endif
1173 if (asi < 0x80) {
1174 helper_raise_exception(env, TT_PRIV_ACT);
1175 }
1176
1177 helper_check_align(env, addr, size - 1);
1178 addr = asi_address_mask(env, asi, addr);
1179
1180 /* Convert to little endian */
1181 switch (asi) {
1182 case 0x88: /* Primary LE */
1183 case 0x89: /* Secondary LE */
1184 switch (size) {
1185 case 2:
1186 val = bswap16(val);
1187 break;
1188 case 4:
1189 val = bswap32(val);
1190 break;
1191 case 8:
1192 val = bswap64(val);
1193 break;
1194 default:
1195 break;
1196 }
1197 default:
1198 break;
1199 }
1200
1201 switch (asi) {
1202 case 0x80: /* Primary */
1203 case 0x88: /* Primary LE */
1204 {
1205 switch (size) {
1206 case 1:
1207 stb_raw(addr, val);
1208 break;
1209 case 2:
1210 stw_raw(addr, val);
1211 break;
1212 case 4:
1213 stl_raw(addr, val);
1214 break;
1215 case 8:
1216 default:
1217 stq_raw(addr, val);
1218 break;
1219 }
1220 }
1221 break;
1222 case 0x81: /* Secondary */
1223 case 0x89: /* Secondary LE */
1224 /* XXX */
1225 return;
1226
1227 case 0x82: /* Primary no-fault, RO */
1228 case 0x83: /* Secondary no-fault, RO */
1229 case 0x8a: /* Primary no-fault LE, RO */
1230 case 0x8b: /* Secondary no-fault LE, RO */
1231 default:
1232 helper_raise_exception(env, TT_DATA_ACCESS);
1233 return;
1234 }
1235 }
1236
1237 #else /* CONFIG_USER_ONLY */
1238
1239 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1240 int sign)
1241 {
1242 uint64_t ret = 0;
1243 #if defined(DEBUG_ASI)
1244 target_ulong last_addr = addr;
1245 #endif
1246
1247 asi &= 0xff;
1248
1249 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1250 || (cpu_has_hypervisor(env)
1251 && asi >= 0x30 && asi < 0x80
1252 && !(env->hpstate & HS_PRIV))) {
1253 helper_raise_exception(env, TT_PRIV_ACT);
1254 }
1255
1256 helper_check_align(env, addr, size - 1);
1257 addr = asi_address_mask(env, asi, addr);
1258
1259 /* process nonfaulting loads first */
1260 if ((asi & 0xf6) == 0x82) {
1261 int mmu_idx;
1262
1263 /* secondary space access has lowest asi bit equal to 1 */
1264 if (env->pstate & PS_PRIV) {
1265 mmu_idx = (asi & 1) ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX;
1266 } else {
1267 mmu_idx = (asi & 1) ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX;
1268 }
1269
1270 if (cpu_get_phys_page_nofault(env, addr, mmu_idx) == -1ULL) {
1271 #ifdef DEBUG_ASI
1272 dump_asi("read ", last_addr, asi, size, ret);
1273 #endif
1274 /* env->exception_index is set in get_physical_address_data(). */
1275 helper_raise_exception(env, env->exception_index);
1276 }
1277
1278 /* convert nonfaulting load ASIs to normal load ASIs */
1279 asi &= ~0x02;
1280 }
1281
1282 switch (asi) {
1283 case 0x10: /* As if user primary */
1284 case 0x11: /* As if user secondary */
1285 case 0x18: /* As if user primary LE */
1286 case 0x19: /* As if user secondary LE */
1287 case 0x80: /* Primary */
1288 case 0x81: /* Secondary */
1289 case 0x88: /* Primary LE */
1290 case 0x89: /* Secondary LE */
1291 case 0xe2: /* UA2007 Primary block init */
1292 case 0xe3: /* UA2007 Secondary block init */
1293 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1294 if (cpu_hypervisor_mode(env)) {
1295 switch (size) {
1296 case 1:
1297 ret = cpu_ldub_hypv(env, addr);
1298 break;
1299 case 2:
1300 ret = cpu_lduw_hypv(env, addr);
1301 break;
1302 case 4:
1303 ret = cpu_ldl_hypv(env, addr);
1304 break;
1305 default:
1306 case 8:
1307 ret = cpu_ldq_hypv(env, addr);
1308 break;
1309 }
1310 } else {
1311 /* secondary space access has lowest asi bit equal to 1 */
1312 if (asi & 1) {
1313 switch (size) {
1314 case 1:
1315 ret = cpu_ldub_kernel_secondary(env, addr);
1316 break;
1317 case 2:
1318 ret = cpu_lduw_kernel_secondary(env, addr);
1319 break;
1320 case 4:
1321 ret = cpu_ldl_kernel_secondary(env, addr);
1322 break;
1323 default:
1324 case 8:
1325 ret = cpu_ldq_kernel_secondary(env, addr);
1326 break;
1327 }
1328 } else {
1329 switch (size) {
1330 case 1:
1331 ret = cpu_ldub_kernel(env, addr);
1332 break;
1333 case 2:
1334 ret = cpu_lduw_kernel(env, addr);
1335 break;
1336 case 4:
1337 ret = cpu_ldl_kernel(env, addr);
1338 break;
1339 default:
1340 case 8:
1341 ret = cpu_ldq_kernel(env, addr);
1342 break;
1343 }
1344 }
1345 }
1346 } else {
1347 /* secondary space access has lowest asi bit equal to 1 */
1348 if (asi & 1) {
1349 switch (size) {
1350 case 1:
1351 ret = cpu_ldub_user_secondary(env, addr);
1352 break;
1353 case 2:
1354 ret = cpu_lduw_user_secondary(env, addr);
1355 break;
1356 case 4:
1357 ret = cpu_ldl_user_secondary(env, addr);
1358 break;
1359 default:
1360 case 8:
1361 ret = cpu_ldq_user_secondary(env, addr);
1362 break;
1363 }
1364 } else {
1365 switch (size) {
1366 case 1:
1367 ret = cpu_ldub_user(env, addr);
1368 break;
1369 case 2:
1370 ret = cpu_lduw_user(env, addr);
1371 break;
1372 case 4:
1373 ret = cpu_ldl_user(env, addr);
1374 break;
1375 default:
1376 case 8:
1377 ret = cpu_ldq_user(env, addr);
1378 break;
1379 }
1380 }
1381 }
1382 break;
1383 case 0x14: /* Bypass */
1384 case 0x15: /* Bypass, non-cacheable */
1385 case 0x1c: /* Bypass LE */
1386 case 0x1d: /* Bypass, non-cacheable LE */
1387 {
1388 switch (size) {
1389 case 1:
1390 ret = ldub_phys(addr);
1391 break;
1392 case 2:
1393 ret = lduw_phys(addr);
1394 break;
1395 case 4:
1396 ret = ldl_phys(addr);
1397 break;
1398 default:
1399 case 8:
1400 ret = ldq_phys(addr);
1401 break;
1402 }
1403 break;
1404 }
1405 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1406 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1407 Only ldda allowed */
1408 helper_raise_exception(env, TT_ILL_INSN);
1409 return 0;
1410 case 0x04: /* Nucleus */
1411 case 0x0c: /* Nucleus Little Endian (LE) */
1412 {
1413 switch (size) {
1414 case 1:
1415 ret = cpu_ldub_nucleus(env, addr);
1416 break;
1417 case 2:
1418 ret = cpu_lduw_nucleus(env, addr);
1419 break;
1420 case 4:
1421 ret = cpu_ldl_nucleus(env, addr);
1422 break;
1423 default:
1424 case 8:
1425 ret = cpu_ldq_nucleus(env, addr);
1426 break;
1427 }
1428 break;
1429 }
1430 case 0x4a: /* UPA config */
1431 /* XXX */
1432 break;
1433 case 0x45: /* LSU */
1434 ret = env->lsu;
1435 break;
1436 case 0x50: /* I-MMU regs */
1437 {
1438 int reg = (addr >> 3) & 0xf;
1439
1440 if (reg == 0) {
1441 /* I-TSB Tag Target register */
1442 ret = ultrasparc_tag_target(env->immu.tag_access);
1443 } else {
1444 ret = env->immuregs[reg];
1445 }
1446
1447 break;
1448 }
1449 case 0x51: /* I-MMU 8k TSB pointer */
1450 {
1451 /* env->immuregs[5] holds I-MMU TSB register value
1452 env->immuregs[6] holds I-MMU Tag Access register value */
1453 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1454 8*1024);
1455 break;
1456 }
1457 case 0x52: /* I-MMU 64k TSB pointer */
1458 {
1459 /* env->immuregs[5] holds I-MMU TSB register value
1460 env->immuregs[6] holds I-MMU Tag Access register value */
1461 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1462 64*1024);
1463 break;
1464 }
1465 case 0x55: /* I-MMU data access */
1466 {
1467 int reg = (addr >> 3) & 0x3f;
1468
1469 ret = env->itlb[reg].tte;
1470 break;
1471 }
1472 case 0x56: /* I-MMU tag read */
1473 {
1474 int reg = (addr >> 3) & 0x3f;
1475
1476 ret = env->itlb[reg].tag;
1477 break;
1478 }
1479 case 0x58: /* D-MMU regs */
1480 {
1481 int reg = (addr >> 3) & 0xf;
1482
1483 if (reg == 0) {
1484 /* D-TSB Tag Target register */
1485 ret = ultrasparc_tag_target(env->dmmu.tag_access);
1486 } else {
1487 ret = env->dmmuregs[reg];
1488 }
1489 break;
1490 }
1491 case 0x59: /* D-MMU 8k TSB pointer */
1492 {
1493 /* env->dmmuregs[5] holds D-MMU TSB register value
1494 env->dmmuregs[6] holds D-MMU Tag Access register value */
1495 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1496 8*1024);
1497 break;
1498 }
1499 case 0x5a: /* D-MMU 64k TSB pointer */
1500 {
1501 /* env->dmmuregs[5] holds D-MMU TSB register value
1502 env->dmmuregs[6] holds D-MMU Tag Access register value */
1503 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1504 64*1024);
1505 break;
1506 }
1507 case 0x5d: /* D-MMU data access */
1508 {
1509 int reg = (addr >> 3) & 0x3f;
1510
1511 ret = env->dtlb[reg].tte;
1512 break;
1513 }
1514 case 0x5e: /* D-MMU tag read */
1515 {
1516 int reg = (addr >> 3) & 0x3f;
1517
1518 ret = env->dtlb[reg].tag;
1519 break;
1520 }
1521 case 0x48: /* Interrupt dispatch, RO */
1522 break;
1523 case 0x49: /* Interrupt data receive */
1524 ret = env->ivec_status;
1525 break;
1526 case 0x7f: /* Incoming interrupt vector, RO */
1527 {
1528 int reg = (addr >> 4) & 0x3;
1529 if (reg < 3) {
1530 ret = env->ivec_data[reg];
1531 }
1532 break;
1533 }
1534 case 0x46: /* D-cache data */
1535 case 0x47: /* D-cache tag access */
1536 case 0x4b: /* E-cache error enable */
1537 case 0x4c: /* E-cache asynchronous fault status */
1538 case 0x4d: /* E-cache asynchronous fault address */
1539 case 0x4e: /* E-cache tag data */
1540 case 0x66: /* I-cache instruction access */
1541 case 0x67: /* I-cache tag access */
1542 case 0x6e: /* I-cache predecode */
1543 case 0x6f: /* I-cache LRU etc. */
1544 case 0x76: /* E-cache tag */
1545 case 0x7e: /* E-cache tag */
1546 break;
1547 case 0x5b: /* D-MMU data pointer */
1548 case 0x54: /* I-MMU data in, WO */
1549 case 0x57: /* I-MMU demap, WO */
1550 case 0x5c: /* D-MMU data in, WO */
1551 case 0x5f: /* D-MMU demap, WO */
1552 case 0x77: /* Interrupt vector, WO */
1553 default:
1554 cpu_unassigned_access(env, addr, 0, 0, 1, size);
1555 ret = 0;
1556 break;
1557 }
1558
1559 /* Convert from little endian */
1560 switch (asi) {
1561 case 0x0c: /* Nucleus Little Endian (LE) */
1562 case 0x18: /* As if user primary LE */
1563 case 0x19: /* As if user secondary LE */
1564 case 0x1c: /* Bypass LE */
1565 case 0x1d: /* Bypass, non-cacheable LE */
1566 case 0x88: /* Primary LE */
1567 case 0x89: /* Secondary LE */
1568 switch(size) {
1569 case 2:
1570 ret = bswap16(ret);
1571 break;
1572 case 4:
1573 ret = bswap32(ret);
1574 break;
1575 case 8:
1576 ret = bswap64(ret);
1577 break;
1578 default:
1579 break;
1580 }
1581 default:
1582 break;
1583 }
1584
1585 /* Convert to signed number */
1586 if (sign) {
1587 switch (size) {
1588 case 1:
1589 ret = (int8_t) ret;
1590 break;
1591 case 2:
1592 ret = (int16_t) ret;
1593 break;
1594 case 4:
1595 ret = (int32_t) ret;
1596 break;
1597 default:
1598 break;
1599 }
1600 }
1601 #ifdef DEBUG_ASI
1602 dump_asi("read ", last_addr, asi, size, ret);
1603 #endif
1604 return ret;
1605 }
1606
1607 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1608 int asi, int size)
1609 {
1610 #ifdef DEBUG_ASI
1611 dump_asi("write", addr, asi, size, val);
1612 #endif
1613
1614 asi &= 0xff;
1615
1616 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1617 || (cpu_has_hypervisor(env)
1618 && asi >= 0x30 && asi < 0x80
1619 && !(env->hpstate & HS_PRIV))) {
1620 helper_raise_exception(env, TT_PRIV_ACT);
1621 }
1622
1623 helper_check_align(env, addr, size - 1);
1624 addr = asi_address_mask(env, asi, addr);
1625
1626 /* Convert to little endian */
1627 switch (asi) {
1628 case 0x0c: /* Nucleus Little Endian (LE) */
1629 case 0x18: /* As if user primary LE */
1630 case 0x19: /* As if user secondary LE */
1631 case 0x1c: /* Bypass LE */
1632 case 0x1d: /* Bypass, non-cacheable LE */
1633 case 0x88: /* Primary LE */
1634 case 0x89: /* Secondary LE */
1635 switch (size) {
1636 case 2:
1637 val = bswap16(val);
1638 break;
1639 case 4:
1640 val = bswap32(val);
1641 break;
1642 case 8:
1643 val = bswap64(val);
1644 break;
1645 default:
1646 break;
1647 }
1648 default:
1649 break;
1650 }
1651
1652 switch (asi) {
1653 case 0x10: /* As if user primary */
1654 case 0x11: /* As if user secondary */
1655 case 0x18: /* As if user primary LE */
1656 case 0x19: /* As if user secondary LE */
1657 case 0x80: /* Primary */
1658 case 0x81: /* Secondary */
1659 case 0x88: /* Primary LE */
1660 case 0x89: /* Secondary LE */
1661 case 0xe2: /* UA2007 Primary block init */
1662 case 0xe3: /* UA2007 Secondary block init */
1663 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1664 if (cpu_hypervisor_mode(env)) {
1665 switch (size) {
1666 case 1:
1667 cpu_stb_hypv(env, addr, val);
1668 break;
1669 case 2:
1670 cpu_stw_hypv(env, addr, val);
1671 break;
1672 case 4:
1673 cpu_stl_hypv(env, addr, val);
1674 break;
1675 case 8:
1676 default:
1677 cpu_stq_hypv(env, addr, val);
1678 break;
1679 }
1680 } else {
1681 /* secondary space access has lowest asi bit equal to 1 */
1682 if (asi & 1) {
1683 switch (size) {
1684 case 1:
1685 cpu_stb_kernel_secondary(env, addr, val);
1686 break;
1687 case 2:
1688 cpu_stw_kernel_secondary(env, addr, val);
1689 break;
1690 case 4:
1691 cpu_stl_kernel_secondary(env, addr, val);
1692 break;
1693 case 8:
1694 default:
1695 cpu_stq_kernel_secondary(env, addr, val);
1696 break;
1697 }
1698 } else {
1699 switch (size) {
1700 case 1:
1701 cpu_stb_kernel(env, addr, val);
1702 break;
1703 case 2:
1704 cpu_stw_kernel(env, addr, val);
1705 break;
1706 case 4:
1707 cpu_stl_kernel(env, addr, val);
1708 break;
1709 case 8:
1710 default:
1711 cpu_stq_kernel(env, addr, val);
1712 break;
1713 }
1714 }
1715 }
1716 } else {
1717 /* secondary space access has lowest asi bit equal to 1 */
1718 if (asi & 1) {
1719 switch (size) {
1720 case 1:
1721 cpu_stb_user_secondary(env, addr, val);
1722 break;
1723 case 2:
1724 cpu_stw_user_secondary(env, addr, val);
1725 break;
1726 case 4:
1727 cpu_stl_user_secondary(env, addr, val);
1728 break;
1729 case 8:
1730 default:
1731 cpu_stq_user_secondary(env, addr, val);
1732 break;
1733 }
1734 } else {
1735 switch (size) {
1736 case 1:
1737 cpu_stb_user(env, addr, val);
1738 break;
1739 case 2:
1740 cpu_stw_user(env, addr, val);
1741 break;
1742 case 4:
1743 cpu_stl_user(env, addr, val);
1744 break;
1745 case 8:
1746 default:
1747 cpu_stq_user(env, addr, val);
1748 break;
1749 }
1750 }
1751 }
1752 break;
1753 case 0x14: /* Bypass */
1754 case 0x15: /* Bypass, non-cacheable */
1755 case 0x1c: /* Bypass LE */
1756 case 0x1d: /* Bypass, non-cacheable LE */
1757 {
1758 switch (size) {
1759 case 1:
1760 stb_phys(addr, val);
1761 break;
1762 case 2:
1763 stw_phys(addr, val);
1764 break;
1765 case 4:
1766 stl_phys(addr, val);
1767 break;
1768 case 8:
1769 default:
1770 stq_phys(addr, val);
1771 break;
1772 }
1773 }
1774 return;
1775 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1776 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1777 Only ldda allowed */
1778 helper_raise_exception(env, TT_ILL_INSN);
1779 return;
1780 case 0x04: /* Nucleus */
1781 case 0x0c: /* Nucleus Little Endian (LE) */
1782 {
1783 switch (size) {
1784 case 1:
1785 cpu_stb_nucleus(env, addr, val);
1786 break;
1787 case 2:
1788 cpu_stw_nucleus(env, addr, val);
1789 break;
1790 case 4:
1791 cpu_stl_nucleus(env, addr, val);
1792 break;
1793 default:
1794 case 8:
1795 cpu_stq_nucleus(env, addr, val);
1796 break;
1797 }
1798 break;
1799 }
1800
1801 case 0x4a: /* UPA config */
1802 /* XXX */
1803 return;
1804 case 0x45: /* LSU */
1805 {
1806 uint64_t oldreg;
1807
1808 oldreg = env->lsu;
1809 env->lsu = val & (DMMU_E | IMMU_E);
1810 /* Mappings generated during D/I MMU disabled mode are
1811 invalid in normal mode */
1812 if (oldreg != env->lsu) {
1813 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
1814 oldreg, env->lsu);
1815 #ifdef DEBUG_MMU
1816 dump_mmu(stdout, fprintf, env1);
1817 #endif
1818 tlb_flush(env, 1);
1819 }
1820 return;
1821 }
1822 case 0x50: /* I-MMU regs */
1823 {
1824 int reg = (addr >> 3) & 0xf;
1825 uint64_t oldreg;
1826
1827 oldreg = env->immuregs[reg];
1828 switch (reg) {
1829 case 0: /* RO */
1830 return;
1831 case 1: /* Not in I-MMU */
1832 case 2:
1833 return;
1834 case 3: /* SFSR */
1835 if ((val & 1) == 0) {
1836 val = 0; /* Clear SFSR */
1837 }
1838 env->immu.sfsr = val;
1839 break;
1840 case 4: /* RO */
1841 return;
1842 case 5: /* TSB access */
1843 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
1844 PRIx64 "\n", env->immu.tsb, val);
1845 env->immu.tsb = val;
1846 break;
1847 case 6: /* Tag access */
1848 env->immu.tag_access = val;
1849 break;
1850 case 7:
1851 case 8:
1852 return;
1853 default:
1854 break;
1855 }
1856
1857 if (oldreg != env->immuregs[reg]) {
1858 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1859 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1860 }
1861 #ifdef DEBUG_MMU
1862 dump_mmu(stdout, fprintf, env);
1863 #endif
1864 return;
1865 }
1866 case 0x54: /* I-MMU data in */
1867 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
1868 return;
1869 case 0x55: /* I-MMU data access */
1870 {
1871 /* TODO: auto demap */
1872
1873 unsigned int i = (addr >> 3) & 0x3f;
1874
1875 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env);
1876
1877 #ifdef DEBUG_MMU
1878 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
1879 dump_mmu(stdout, fprintf, env);
1880 #endif
1881 return;
1882 }
1883 case 0x57: /* I-MMU demap */
1884 demap_tlb(env->itlb, addr, "immu", env);
1885 return;
1886 case 0x58: /* D-MMU regs */
1887 {
1888 int reg = (addr >> 3) & 0xf;
1889 uint64_t oldreg;
1890
1891 oldreg = env->dmmuregs[reg];
1892 switch (reg) {
1893 case 0: /* RO */
1894 case 4:
1895 return;
1896 case 3: /* SFSR */
1897 if ((val & 1) == 0) {
1898 val = 0; /* Clear SFSR, Fault address */
1899 env->dmmu.sfar = 0;
1900 }
1901 env->dmmu.sfsr = val;
1902 break;
1903 case 1: /* Primary context */
1904 env->dmmu.mmu_primary_context = val;
1905 /* can be optimized to only flush MMU_USER_IDX
1906 and MMU_KERNEL_IDX entries */
1907 tlb_flush(env, 1);
1908 break;
1909 case 2: /* Secondary context */
1910 env->dmmu.mmu_secondary_context = val;
1911 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1912 and MMU_KERNEL_SECONDARY_IDX entries */
1913 tlb_flush(env, 1);
1914 break;
1915 case 5: /* TSB access */
1916 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
1917 PRIx64 "\n", env->dmmu.tsb, val);
1918 env->dmmu.tsb = val;
1919 break;
1920 case 6: /* Tag access */
1921 env->dmmu.tag_access = val;
1922 break;
1923 case 7: /* Virtual Watchpoint */
1924 case 8: /* Physical Watchpoint */
1925 default:
1926 env->dmmuregs[reg] = val;
1927 break;
1928 }
1929
1930 if (oldreg != env->dmmuregs[reg]) {
1931 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1932 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1933 }
1934 #ifdef DEBUG_MMU
1935 dump_mmu(stdout, fprintf, env);
1936 #endif
1937 return;
1938 }
1939 case 0x5c: /* D-MMU data in */
1940 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
1941 return;
1942 case 0x5d: /* D-MMU data access */
1943 {
1944 unsigned int i = (addr >> 3) & 0x3f;
1945
1946 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env);
1947
1948 #ifdef DEBUG_MMU
1949 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
1950 dump_mmu(stdout, fprintf, env);
1951 #endif
1952 return;
1953 }
1954 case 0x5f: /* D-MMU demap */
1955 demap_tlb(env->dtlb, addr, "dmmu", env);
1956 return;
1957 case 0x49: /* Interrupt data receive */
1958 env->ivec_status = val & 0x20;
1959 return;
1960 case 0x46: /* D-cache data */
1961 case 0x47: /* D-cache tag access */
1962 case 0x4b: /* E-cache error enable */
1963 case 0x4c: /* E-cache asynchronous fault status */
1964 case 0x4d: /* E-cache asynchronous fault address */
1965 case 0x4e: /* E-cache tag data */
1966 case 0x66: /* I-cache instruction access */
1967 case 0x67: /* I-cache tag access */
1968 case 0x6e: /* I-cache predecode */
1969 case 0x6f: /* I-cache LRU etc. */
1970 case 0x76: /* E-cache tag */
1971 case 0x7e: /* E-cache tag */
1972 return;
1973 case 0x51: /* I-MMU 8k TSB pointer, RO */
1974 case 0x52: /* I-MMU 64k TSB pointer, RO */
1975 case 0x56: /* I-MMU tag read, RO */
1976 case 0x59: /* D-MMU 8k TSB pointer, RO */
1977 case 0x5a: /* D-MMU 64k TSB pointer, RO */
1978 case 0x5b: /* D-MMU data pointer, RO */
1979 case 0x5e: /* D-MMU tag read, RO */
1980 case 0x48: /* Interrupt dispatch, RO */
1981 case 0x7f: /* Incoming interrupt vector, RO */
1982 case 0x82: /* Primary no-fault, RO */
1983 case 0x83: /* Secondary no-fault, RO */
1984 case 0x8a: /* Primary no-fault LE, RO */
1985 case 0x8b: /* Secondary no-fault LE, RO */
1986 default:
1987 cpu_unassigned_access(env, addr, 1, 0, 1, size);
1988 return;
1989 }
1990 }
1991 #endif /* CONFIG_USER_ONLY */
1992
1993 void helper_ldda_asi(CPUSPARCState *env, target_ulong addr, int asi, int rd)
1994 {
1995 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1996 || (cpu_has_hypervisor(env)
1997 && asi >= 0x30 && asi < 0x80
1998 && !(env->hpstate & HS_PRIV))) {
1999 helper_raise_exception(env, TT_PRIV_ACT);
2000 }
2001
2002 addr = asi_address_mask(env, asi, addr);
2003
2004 switch (asi) {
2005 #if !defined(CONFIG_USER_ONLY)
2006 case 0x24: /* Nucleus quad LDD 128 bit atomic */
2007 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE */
2008 helper_check_align(env, addr, 0xf);
2009 if (rd == 0) {
2010 env->gregs[1] = cpu_ldq_nucleus(env, addr + 8);
2011 if (asi == 0x2c) {
2012 bswap64s(&env->gregs[1]);
2013 }
2014 } else if (rd < 8) {
2015 env->gregs[rd] = cpu_ldq_nucleus(env, addr);
2016 env->gregs[rd + 1] = cpu_ldq_nucleus(env, addr + 8);
2017 if (asi == 0x2c) {
2018 bswap64s(&env->gregs[rd]);
2019 bswap64s(&env->gregs[rd + 1]);
2020 }
2021 } else {
2022 env->regwptr[rd] = cpu_ldq_nucleus(env, addr);
2023 env->regwptr[rd + 1] = cpu_ldq_nucleus(env, addr + 8);
2024 if (asi == 0x2c) {
2025 bswap64s(&env->regwptr[rd]);
2026 bswap64s(&env->regwptr[rd + 1]);
2027 }
2028 }
2029 break;
2030 #endif
2031 default:
2032 helper_check_align(env, addr, 0x3);
2033 if (rd == 0) {
2034 env->gregs[1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2035 } else if (rd < 8) {
2036 env->gregs[rd] = helper_ld_asi(env, addr, asi, 4, 0);
2037 env->gregs[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2038 } else {
2039 env->regwptr[rd] = helper_ld_asi(env, addr, asi, 4, 0);
2040 env->regwptr[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2041 }
2042 break;
2043 }
2044 }
2045
2046 void helper_ldf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2047 int rd)
2048 {
2049 unsigned int i;
2050 target_ulong val;
2051
2052 helper_check_align(env, addr, 3);
2053 addr = asi_address_mask(env, asi, addr);
2054
2055 switch (asi) {
2056 case 0xf0: /* UA2007/JPS1 Block load primary */
2057 case 0xf1: /* UA2007/JPS1 Block load secondary */
2058 case 0xf8: /* UA2007/JPS1 Block load primary LE */
2059 case 0xf9: /* UA2007/JPS1 Block load secondary LE */
2060 if (rd & 7) {
2061 helper_raise_exception(env, TT_ILL_INSN);
2062 return;
2063 }
2064 helper_check_align(env, addr, 0x3f);
2065 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2066 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x8f, 8, 0);
2067 }
2068 return;
2069
2070 case 0x16: /* UA2007 Block load primary, user privilege */
2071 case 0x17: /* UA2007 Block load secondary, user privilege */
2072 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2073 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2074 case 0x70: /* JPS1 Block load primary, user privilege */
2075 case 0x71: /* JPS1 Block load secondary, user privilege */
2076 case 0x78: /* JPS1 Block load primary LE, user privilege */
2077 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2078 if (rd & 7) {
2079 helper_raise_exception(env, TT_ILL_INSN);
2080 return;
2081 }
2082 helper_check_align(env, addr, 0x3f);
2083 for (i = 0; i < 8; i++, rd += 2, addr += 4) {
2084 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x19, 8, 0);
2085 }
2086 return;
2087
2088 default:
2089 break;
2090 }
2091
2092 switch (size) {
2093 default:
2094 case 4:
2095 val = helper_ld_asi(env, addr, asi, size, 0);
2096 if (rd & 1) {
2097 env->fpr[rd / 2].l.lower = val;
2098 } else {
2099 env->fpr[rd / 2].l.upper = val;
2100 }
2101 break;
2102 case 8:
2103 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, size, 0);
2104 break;
2105 case 16:
2106 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, 8, 0);
2107 env->fpr[rd / 2 + 1].ll = helper_ld_asi(env, addr + 8, asi, 8, 0);
2108 break;
2109 }
2110 }
2111
2112 void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2113 int rd)
2114 {
2115 unsigned int i;
2116 target_ulong val;
2117
2118 helper_check_align(env, addr, 3);
2119 addr = asi_address_mask(env, asi, addr);
2120
2121 switch (asi) {
2122 case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */
2123 case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */
2124 case 0xf0: /* UA2007/JPS1 Block store primary */
2125 case 0xf1: /* UA2007/JPS1 Block store secondary */
2126 case 0xf8: /* UA2007/JPS1 Block store primary LE */
2127 case 0xf9: /* UA2007/JPS1 Block store secondary LE */
2128 if (rd & 7) {
2129 helper_raise_exception(env, TT_ILL_INSN);
2130 return;
2131 }
2132 helper_check_align(env, addr, 0x3f);
2133 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2134 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x8f, 8);
2135 }
2136
2137 return;
2138 case 0x16: /* UA2007 Block load primary, user privilege */
2139 case 0x17: /* UA2007 Block load secondary, user privilege */
2140 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2141 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2142 case 0x70: /* JPS1 Block store primary, user privilege */
2143 case 0x71: /* JPS1 Block store secondary, user privilege */
2144 case 0x78: /* JPS1 Block load primary LE, user privilege */
2145 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2146 if (rd & 7) {
2147 helper_raise_exception(env, TT_ILL_INSN);
2148 return;
2149 }
2150 helper_check_align(env, addr, 0x3f);
2151 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2152 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x19, 8);
2153 }
2154
2155 return;
2156 default:
2157 break;
2158 }
2159
2160 switch (size) {
2161 default:
2162 case 4:
2163 if (rd & 1) {
2164 val = env->fpr[rd / 2].l.lower;
2165 } else {
2166 val = env->fpr[rd / 2].l.upper;
2167 }
2168 helper_st_asi(env, addr, val, asi, size);
2169 break;
2170 case 8:
2171 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, size);
2172 break;
2173 case 16:
2174 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, 8);
2175 helper_st_asi(env, addr + 8, env->fpr[rd / 2 + 1].ll, asi, 8);
2176 break;
2177 }
2178 }
2179
2180 target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr,
2181 target_ulong val1, target_ulong val2, uint32_t asi)
2182 {
2183 target_ulong ret;
2184
2185 val2 &= 0xffffffffUL;
2186 ret = helper_ld_asi(env, addr, asi, 4, 0);
2187 ret &= 0xffffffffUL;
2188 if (val2 == ret) {
2189 helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4);
2190 }
2191 return ret;
2192 }
2193
2194 target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr,
2195 target_ulong val1, target_ulong val2,
2196 uint32_t asi)
2197 {
2198 target_ulong ret;
2199
2200 ret = helper_ld_asi(env, addr, asi, 8, 0);
2201 if (val2 == ret) {
2202 helper_st_asi(env, addr, val1, asi, 8);
2203 }
2204 return ret;
2205 }
2206 #endif /* TARGET_SPARC64 */
2207
2208 void helper_ldqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
2209 {
2210 /* XXX add 128 bit load */
2211 CPU_QuadU u;
2212
2213 helper_check_align(env, addr, 7);
2214 #if !defined(CONFIG_USER_ONLY)
2215 switch (mem_idx) {
2216 case MMU_USER_IDX:
2217 u.ll.upper = cpu_ldq_user(env, addr);
2218 u.ll.lower = cpu_ldq_user(env, addr + 8);
2219 QT0 = u.q;
2220 break;
2221 case MMU_KERNEL_IDX:
2222 u.ll.upper = cpu_ldq_kernel(env, addr);
2223 u.ll.lower = cpu_ldq_kernel(env, addr + 8);
2224 QT0 = u.q;
2225 break;
2226 #ifdef TARGET_SPARC64
2227 case MMU_HYPV_IDX:
2228 u.ll.upper = cpu_ldq_hypv(env, addr);
2229 u.ll.lower = cpu_ldq_hypv(env, addr + 8);
2230 QT0 = u.q;
2231 break;
2232 #endif
2233 default:
2234 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx);
2235 break;
2236 }
2237 #else
2238 u.ll.upper = ldq_raw(address_mask(env, addr));
2239 u.ll.lower = ldq_raw(address_mask(env, addr + 8));
2240 QT0 = u.q;
2241 #endif
2242 }
2243
2244 void helper_stqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
2245 {
2246 /* XXX add 128 bit store */
2247 CPU_QuadU u;
2248
2249 helper_check_align(env, addr, 7);
2250 #if !defined(CONFIG_USER_ONLY)
2251 switch (mem_idx) {
2252 case MMU_USER_IDX:
2253 u.q = QT0;
2254 cpu_stq_user(env, addr, u.ll.upper);
2255 cpu_stq_user(env, addr + 8, u.ll.lower);
2256 break;
2257 case MMU_KERNEL_IDX:
2258 u.q = QT0;
2259 cpu_stq_kernel(env, addr, u.ll.upper);
2260 cpu_stq_kernel(env, addr + 8, u.ll.lower);
2261 break;
2262 #ifdef TARGET_SPARC64
2263 case MMU_HYPV_IDX:
2264 u.q = QT0;
2265 cpu_stq_hypv(env, addr, u.ll.upper);
2266 cpu_stq_hypv(env, addr + 8, u.ll.lower);
2267 break;
2268 #endif
2269 default:
2270 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx);
2271 break;
2272 }
2273 #else
2274 u.q = QT0;
2275 stq_raw(address_mask(env, addr), u.ll.upper);
2276 stq_raw(address_mask(env, addr + 8), u.ll.lower);
2277 #endif
2278 }
2279
2280 #if !defined(CONFIG_USER_ONLY)
2281 #ifndef TARGET_SPARC64
2282 void cpu_unassigned_access(CPUSPARCState *env, target_phys_addr_t addr,
2283 int is_write, int is_exec, int is_asi, int size)
2284 {
2285 int fault_type;
2286
2287 #ifdef DEBUG_UNASSIGNED
2288 if (is_asi) {
2289 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2290 " asi 0x%02x from " TARGET_FMT_lx "\n",
2291 is_exec ? "exec" : is_write ? "write" : "read", size,
2292 size == 1 ? "" : "s", addr, is_asi, env->pc);
2293 } else {
2294 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2295 " from " TARGET_FMT_lx "\n",
2296 is_exec ? "exec" : is_write ? "write" : "read", size,
2297 size == 1 ? "" : "s", addr, env->pc);
2298 }
2299 #endif
2300 /* Don't overwrite translation and access faults */
2301 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
2302 if ((fault_type > 4) || (fault_type == 0)) {
2303 env->mmuregs[3] = 0; /* Fault status register */
2304 if (is_asi) {
2305 env->mmuregs[3] |= 1 << 16;
2306 }
2307 if (env->psrs) {
2308 env->mmuregs[3] |= 1 << 5;
2309 }
2310 if (is_exec) {
2311 env->mmuregs[3] |= 1 << 6;
2312 }
2313 if (is_write) {
2314 env->mmuregs[3] |= 1 << 7;
2315 }
2316 env->mmuregs[3] |= (5 << 2) | 2;
2317 /* SuperSPARC will never place instruction fault addresses in the FAR */
2318 if (!is_exec) {
2319 env->mmuregs[4] = addr; /* Fault address register */
2320 }
2321 }
2322 /* overflow (same type fault was not read before another fault) */
2323 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
2324 env->mmuregs[3] |= 1;
2325 }
2326
2327 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
2328 if (is_exec) {
2329 helper_raise_exception(env, TT_CODE_ACCESS);
2330 } else {
2331 helper_raise_exception(env, TT_DATA_ACCESS);
2332 }
2333 }
2334
2335 /* flush neverland mappings created during no-fault mode,
2336 so the sequential MMU faults report proper fault types */
2337 if (env->mmuregs[0] & MMU_NF) {
2338 tlb_flush(env, 1);
2339 }
2340 }
2341 #else
2342 void cpu_unassigned_access(CPUSPARCState *env, target_phys_addr_t addr,
2343 int is_write, int is_exec, int is_asi, int size)
2344 {
2345 #ifdef DEBUG_UNASSIGNED
2346 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
2347 "\n", addr, env->pc);
2348 #endif
2349
2350 if (is_exec) {
2351 helper_raise_exception(env, TT_CODE_ACCESS);
2352 } else {
2353 helper_raise_exception(env, TT_DATA_ACCESS);
2354 }
2355 }
2356 #endif
2357 #endif
Qemu copy for testing