target-sparc/op_helper.c

   1 #include <math.h>
   2 #include <fenv.h>
   3 #include "exec.h"
   4
   5 #ifdef USE_INT_TO_FLOAT_HELPERS
   6 void do_fitos(void)
   7 {
   8     FT0 = (float) *((int32_t *)&FT1);
   9 }
  10
  11 void do_fitod(void)
  12 {
  13     DT0 = (double) *((int32_t *)&FT1);
  14 }
  15 #endif
  16
  17 void do_fabss(void)
  18 {
  19     FT0 = fabsf(FT1);
  20 }
  21
  22 void do_fsqrts(void)
  23 {
  24     FT0 = sqrtf(FT1);
  25 }
  26
  27 void do_fsqrtd(void)
  28 {
  29     DT0 = sqrt(DT1);
  30 }
  31
  32 void do_fcmps (void)
  33 {
  34     if (isnan(FT0) || isnan(FT1)) {
  35         T0 = FSR_FCC1 | FSR_FCC0;
  36     } else if (FT0 < FT1) {
  37         T0 = FSR_FCC0;
  38     } else if (FT0 > FT1) {
  39         T0 = FSR_FCC1;
  40     } else {
  41         T0 = 0;
  42     }
  43     env->fsr = T0;
  44 }
  45
  46 void do_fcmpd (void)
  47 {
  48     if (isnan(DT0) || isnan(DT1)) {
  49         T0 = FSR_FCC1 | FSR_FCC0;
  50     } else if (DT0 < DT1) {
  51         T0 = FSR_FCC0;
  52     } else if (DT0 > DT1) {
  53         T0 = FSR_FCC1;
  54     } else {
  55         T0 = 0;
  56     }
  57     env->fsr = T0;
  58 }
  59
  60 void helper_ld_asi(int asi, int size, int sign)
  61 {
  62     switch(asi) {
  63     case 3: /* MMU probe */
  64         T1 = 0;
  65         return;
  66     case 4: /* read MMU regs */
  67         {
  68             int temp, reg = (T0 >> 8) & 0xf;
  69
  70             temp = env->mmuregs[reg];
  71             if (reg == 3 || reg == 4) /* Fault status, addr cleared on read*/
  72                 env->mmuregs[reg] = 0;
  73             T1 = temp;
  74         }
  75         return;
  76     case 0x20 ... 0x2f: /* MMU passthrough */
  77         {
  78             int temp;
  79
  80             cpu_physical_memory_read(T0, (void *) &temp, size);
  81             bswap32s(&temp);
  82             T1 = temp;
  83         }
  84         return;
  85     default:
  86         T1 = 0;
  87         return;
  88     }
  89 }
  90
  91 void helper_st_asi(int asi, int size, int sign)
  92 {
  93     switch(asi) {
  94     case 3: /* MMU flush */
  95         return;
  96     case 4: /* write MMU regs */
  97         {
  98             int reg = (T0 >> 8) & 0xf;
  99             if (reg == 0) {
 100                 env->mmuregs[reg] &= ~(MMU_E | MMU_NF);
 101                 env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF);
 102             } else
 103                 env->mmuregs[reg] = T1;
 104             return;
 105         }
 106     case 0x20 ... 0x2f: /* MMU passthrough */
 107         {
 108             int temp = T1;
 109
 110             bswap32s(&temp);
 111             cpu_physical_memory_write(T0, (void *) &temp, size);
 112         }
 113         return;
 114     default:
 115         return;
 116     }
 117 }
 118
 119 #if 0
 120 void do_ldd_raw(uint32_t addr)
 121 {
 122     T1 = ldl_raw((void *) addr);
 123     T0 = ldl_raw((void *) (addr + 4));
 124 }
 125
 126 #if !defined(CONFIG_USER_ONLY)
 127 void do_ldd_user(uint32_t addr)
 128 {
 129     T1 = ldl_user((void *) addr);
 130     T0 = ldl_user((void *) (addr + 4));
 131 }
 132 void do_ldd_kernel(uint32_t addr)
 133 {
 134     T1 = ldl_kernel((void *) addr);
 135     T0 = ldl_kernel((void *) (addr + 4));
 136 }
 137 #endif
 138 #endif
 139
 140 void helper_rett()
 141 {
 142     int cwp;
 143     env->psret = 1;
 144     cwp = (env->cwp + 1) & (NWINDOWS - 1);
 145     if (env->wim & (1 << cwp)) {
 146         raise_exception(TT_WIN_UNF);
 147     }
 148     set_cwp(cwp);
 149     env->psrs = env->psrps;
 150 }
 151
 152 void helper_ldfsr(void)
 153 {
 154     switch (env->fsr & FSR_RD_MASK) {
 155     case FSR_RD_NEAREST:
 156         fesetround(FE_TONEAREST);
 157         break;
 158     case FSR_RD_ZERO:
 159         fesetround(FE_TOWARDZERO);
 160         break;
 161     case FSR_RD_POS:
 162         fesetround(FE_UPWARD);
 163         break;
 164     case FSR_RD_NEG:
 165         fesetround(FE_DOWNWARD);
 166         break;
 167     }
 168 }