]>
git.proxmox.com Git - qemu.git/blob - target-sparc/op_helper.c
2 #include "host-utils.h"
7 //#define DEBUG_UNALIGNED
8 //#define DEBUG_UNASSIGNED
11 //#define DEBUG_PSTATE
14 #define DPRINTF_MMU(fmt, ...) \
15 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
17 #define DPRINTF_MMU(fmt, ...) do {} while (0)
21 #define DPRINTF_MXCC(fmt, ...) \
22 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
24 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
28 #define DPRINTF_ASI(fmt, ...) \
29 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
33 #define DPRINTF_PSTATE(fmt, ...) \
34 do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
36 #define DPRINTF_PSTATE(fmt, ...) do {} while (0)
41 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
43 #define AM_CHECK(env1) (1)
47 #if defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
48 static void do_unassigned_access(target_ulong addr
, int is_write
, int is_exec
,
49 int is_asi
, int size
);
52 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
53 // Calculates TSB pointer value for fault page size 8k or 64k
54 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register
,
55 uint64_t tag_access_register
,
58 uint64_t tsb_base
= tsb_register
& ~0x1fffULL
;
59 int tsb_split
= (tsb_register
& 0x1000ULL
) ? 1 : 0;
60 int tsb_size
= tsb_register
& 0xf;
62 // discard lower 13 bits which hold tag access context
63 uint64_t tag_access_va
= tag_access_register
& ~0x1fffULL
;
66 uint64_t tsb_base_mask
= ~0x1fffULL
;
67 uint64_t va
= tag_access_va
;
69 // move va bits to correct position
70 if (page_size
== 8*1024) {
72 } else if (page_size
== 64*1024) {
77 tsb_base_mask
<<= tsb_size
;
80 // calculate tsb_base mask and adjust va if split is in use
82 if (page_size
== 8*1024) {
83 va
&= ~(1ULL << (13 + tsb_size
));
84 } else if (page_size
== 64*1024) {
85 va
|= (1ULL << (13 + tsb_size
));
90 return ((tsb_base
& tsb_base_mask
) | (va
& ~tsb_base_mask
)) & ~0xfULL
;
93 // Calculates tag target register value by reordering bits
94 // in tag access register
95 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register
)
97 return ((tag_access_register
& 0x1fff) << 48) | (tag_access_register
>> 22);
100 static void replace_tlb_entry(SparcTLBEntry
*tlb
,
101 uint64_t tlb_tag
, uint64_t tlb_tte
,
104 target_ulong mask
, size
, va
, offset
;
106 // flush page range if translation is valid
107 if (TTE_IS_VALID(tlb
->tte
)) {
109 mask
= 0xffffffffffffe000ULL
;
110 mask
<<= 3 * ((tlb
->tte
>> 61) & 3);
113 va
= tlb
->tag
& mask
;
115 for (offset
= 0; offset
< size
; offset
+= TARGET_PAGE_SIZE
) {
116 tlb_flush_page(env1
, va
+ offset
);
124 static void demap_tlb(SparcTLBEntry
*tlb
, target_ulong demap_addr
,
125 const char* strmmu
, CPUState
*env1
)
131 int is_demap_context
= (demap_addr
>> 6) & 1;
134 switch ((demap_addr
>> 4) & 3) {
136 context
= env1
->dmmu
.mmu_primary_context
;
139 context
= env1
->dmmu
.mmu_secondary_context
;
149 for (i
= 0; i
< 64; i
++) {
150 if (TTE_IS_VALID(tlb
[i
].tte
)) {
152 if (is_demap_context
) {
153 // will remove non-global entries matching context value
154 if (TTE_IS_GLOBAL(tlb
[i
].tte
) ||
155 !tlb_compare_context(&tlb
[i
], context
)) {
160 // will remove any entry matching VA
161 mask
= 0xffffffffffffe000ULL
;
162 mask
<<= 3 * ((tlb
[i
].tte
>> 61) & 3);
164 if (!compare_masked(demap_addr
, tlb
[i
].tag
, mask
)) {
168 // entry should be global or matching context value
169 if (!TTE_IS_GLOBAL(tlb
[i
].tte
) &&
170 !tlb_compare_context(&tlb
[i
], context
)) {
175 replace_tlb_entry(&tlb
[i
], 0, 0, env1
);
177 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu
, i
);
184 static void replace_tlb_1bit_lru(SparcTLBEntry
*tlb
,
185 uint64_t tlb_tag
, uint64_t tlb_tte
,
186 const char* strmmu
, CPUState
*env1
)
188 unsigned int i
, replace_used
;
190 // Try replacing invalid entry
191 for (i
= 0; i
< 64; i
++) {
192 if (!TTE_IS_VALID(tlb
[i
].tte
)) {
193 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
195 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu
, i
);
202 // All entries are valid, try replacing unlocked entry
204 for (replace_used
= 0; replace_used
< 2; ++replace_used
) {
206 // Used entries are not replaced on first pass
208 for (i
= 0; i
< 64; i
++) {
209 if (!TTE_IS_LOCKED(tlb
[i
].tte
) && !TTE_IS_USED(tlb
[i
].tte
)) {
211 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
213 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
214 strmmu
, (replace_used
?"used":"unused"), i
);
221 // Now reset used bit and search for unused entries again
223 for (i
= 0; i
< 64; i
++) {
224 TTE_SET_UNUSED(tlb
[i
].tte
);
229 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu
);
236 static inline target_ulong
address_mask(CPUState
*env1
, target_ulong addr
)
238 #ifdef TARGET_SPARC64
240 addr
&= 0xffffffffULL
;
245 static void raise_exception(int tt
)
247 env
->exception_index
= tt
;
251 void HELPER(raise_exception
)(int tt
)
256 static inline void set_cwp(int new_cwp
)
258 cpu_set_cwp(env
, new_cwp
);
261 void helper_check_align(target_ulong addr
, uint32_t align
)
264 #ifdef DEBUG_UNALIGNED
265 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
266 "\n", addr
, env
->pc
);
268 raise_exception(TT_UNALIGNED
);
272 #define F_HELPER(name, p) void helper_f##name##p(void)
274 #define F_BINOP(name) \
275 float32 helper_f ## name ## s (float32 src1, float32 src2) \
277 return float32_ ## name (src1, src2, &env->fp_status); \
281 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
285 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
294 void helper_fsmuld(float32 src1
, float32 src2
)
296 DT0
= float64_mul(float32_to_float64(src1
, &env
->fp_status
),
297 float32_to_float64(src2
, &env
->fp_status
),
301 void helper_fdmulq(void)
303 QT0
= float128_mul(float64_to_float128(DT0
, &env
->fp_status
),
304 float64_to_float128(DT1
, &env
->fp_status
),
308 float32
helper_fnegs(float32 src
)
310 return float32_chs(src
);
313 #ifdef TARGET_SPARC64
316 DT0
= float64_chs(DT1
);
321 QT0
= float128_chs(QT1
);
325 /* Integer to float conversion. */
326 float32
helper_fitos(int32_t src
)
328 return int32_to_float32(src
, &env
->fp_status
);
331 void helper_fitod(int32_t src
)
333 DT0
= int32_to_float64(src
, &env
->fp_status
);
336 void helper_fitoq(int32_t src
)
338 QT0
= int32_to_float128(src
, &env
->fp_status
);
341 #ifdef TARGET_SPARC64
342 float32
helper_fxtos(void)
344 return int64_to_float32(*((int64_t *)&DT1
), &env
->fp_status
);
349 DT0
= int64_to_float64(*((int64_t *)&DT1
), &env
->fp_status
);
354 QT0
= int64_to_float128(*((int64_t *)&DT1
), &env
->fp_status
);
359 /* floating point conversion */
360 float32
helper_fdtos(void)
362 return float64_to_float32(DT1
, &env
->fp_status
);
365 void helper_fstod(float32 src
)
367 DT0
= float32_to_float64(src
, &env
->fp_status
);
370 float32
helper_fqtos(void)
372 return float128_to_float32(QT1
, &env
->fp_status
);
375 void helper_fstoq(float32 src
)
377 QT0
= float32_to_float128(src
, &env
->fp_status
);
380 void helper_fqtod(void)
382 DT0
= float128_to_float64(QT1
, &env
->fp_status
);
385 void helper_fdtoq(void)
387 QT0
= float64_to_float128(DT1
, &env
->fp_status
);
390 /* Float to integer conversion. */
391 int32_t helper_fstoi(float32 src
)
393 return float32_to_int32_round_to_zero(src
, &env
->fp_status
);
396 int32_t helper_fdtoi(void)
398 return float64_to_int32_round_to_zero(DT1
, &env
->fp_status
);
401 int32_t helper_fqtoi(void)
403 return float128_to_int32_round_to_zero(QT1
, &env
->fp_status
);
406 #ifdef TARGET_SPARC64
407 void helper_fstox(float32 src
)
409 *((int64_t *)&DT0
) = float32_to_int64_round_to_zero(src
, &env
->fp_status
);
412 void helper_fdtox(void)
414 *((int64_t *)&DT0
) = float64_to_int64_round_to_zero(DT1
, &env
->fp_status
);
417 void helper_fqtox(void)
419 *((int64_t *)&DT0
) = float128_to_int64_round_to_zero(QT1
, &env
->fp_status
);
422 void helper_faligndata(void)
426 tmp
= (*((uint64_t *)&DT0
)) << ((env
->gsr
& 7) * 8);
427 /* on many architectures a shift of 64 does nothing */
428 if ((env
->gsr
& 7) != 0) {
429 tmp
|= (*((uint64_t *)&DT1
)) >> (64 - (env
->gsr
& 7) * 8);
431 *((uint64_t *)&DT0
) = tmp
;
434 #ifdef HOST_WORDS_BIGENDIAN
435 #define VIS_B64(n) b[7 - (n)]
436 #define VIS_W64(n) w[3 - (n)]
437 #define VIS_SW64(n) sw[3 - (n)]
438 #define VIS_L64(n) l[1 - (n)]
439 #define VIS_B32(n) b[3 - (n)]
440 #define VIS_W32(n) w[1 - (n)]
442 #define VIS_B64(n) b[n]
443 #define VIS_W64(n) w[n]
444 #define VIS_SW64(n) sw[n]
445 #define VIS_L64(n) l[n]
446 #define VIS_B32(n) b[n]
447 #define VIS_W32(n) w[n]
465 void helper_fpmerge(void)
472 // Reverse calculation order to handle overlap
473 d
.VIS_B64(7) = s
.VIS_B64(3);
474 d
.VIS_B64(6) = d
.VIS_B64(3);
475 d
.VIS_B64(5) = s
.VIS_B64(2);
476 d
.VIS_B64(4) = d
.VIS_B64(2);
477 d
.VIS_B64(3) = s
.VIS_B64(1);
478 d
.VIS_B64(2) = d
.VIS_B64(1);
479 d
.VIS_B64(1) = s
.VIS_B64(0);
480 //d.VIS_B64(0) = d.VIS_B64(0);
485 void helper_fmul8x16(void)
494 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
495 if ((tmp & 0xff) > 0x7f) \
497 d.VIS_W64(r) = tmp >> 8;
508 void helper_fmul8x16al(void)
517 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
518 if ((tmp & 0xff) > 0x7f) \
520 d.VIS_W64(r) = tmp >> 8;
531 void helper_fmul8x16au(void)
540 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
541 if ((tmp & 0xff) > 0x7f) \
543 d.VIS_W64(r) = tmp >> 8;
554 void helper_fmul8sux16(void)
563 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
564 if ((tmp & 0xff) > 0x7f) \
566 d.VIS_W64(r) = tmp >> 8;
577 void helper_fmul8ulx16(void)
586 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
587 if ((tmp & 0xff) > 0x7f) \
589 d.VIS_W64(r) = tmp >> 8;
600 void helper_fmuld8sux16(void)
609 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
610 if ((tmp & 0xff) > 0x7f) \
614 // Reverse calculation order to handle overlap
622 void helper_fmuld8ulx16(void)
631 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
632 if ((tmp & 0xff) > 0x7f) \
636 // Reverse calculation order to handle overlap
644 void helper_fexpand(void)
649 s
.l
= (uint32_t)(*(uint64_t *)&DT0
& 0xffffffff);
651 d
.VIS_W64(0) = s
.VIS_B32(0) << 4;
652 d
.VIS_W64(1) = s
.VIS_B32(1) << 4;
653 d
.VIS_W64(2) = s
.VIS_B32(2) << 4;
654 d
.VIS_W64(3) = s
.VIS_B32(3) << 4;
659 #define VIS_HELPER(name, F) \
660 void name##16(void) \
667 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
668 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
669 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
670 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
675 uint32_t name##16s(uint32_t src1, uint32_t src2) \
682 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
683 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
688 void name##32(void) \
695 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
696 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
701 uint32_t name##32s(uint32_t src1, uint32_t src2) \
713 #define FADD(a, b) ((a) + (b))
714 #define FSUB(a, b) ((a) - (b))
715 VIS_HELPER(helper_fpadd
, FADD
)
716 VIS_HELPER(helper_fpsub
, FSUB
)
718 #define VIS_CMPHELPER(name, F) \
719 void name##16(void) \
726 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
727 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
728 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
729 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
734 void name##32(void) \
741 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
742 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
747 #define FCMPGT(a, b) ((a) > (b))
748 #define FCMPEQ(a, b) ((a) == (b))
749 #define FCMPLE(a, b) ((a) <= (b))
750 #define FCMPNE(a, b) ((a) != (b))
752 VIS_CMPHELPER(helper_fcmpgt
, FCMPGT
)
753 VIS_CMPHELPER(helper_fcmpeq
, FCMPEQ
)
754 VIS_CMPHELPER(helper_fcmple
, FCMPLE
)
755 VIS_CMPHELPER(helper_fcmpne
, FCMPNE
)
758 void helper_check_ieee_exceptions(void)
762 status
= get_float_exception_flags(&env
->fp_status
);
764 /* Copy IEEE 754 flags into FSR */
765 if (status
& float_flag_invalid
)
767 if (status
& float_flag_overflow
)
769 if (status
& float_flag_underflow
)
771 if (status
& float_flag_divbyzero
)
773 if (status
& float_flag_inexact
)
776 if ((env
->fsr
& FSR_CEXC_MASK
) & ((env
->fsr
& FSR_TEM_MASK
) >> 23)) {
777 /* Unmasked exception, generate a trap */
778 env
->fsr
|= FSR_FTT_IEEE_EXCP
;
779 raise_exception(TT_FP_EXCP
);
781 /* Accumulate exceptions */
782 env
->fsr
|= (env
->fsr
& FSR_CEXC_MASK
) << 5;
787 void helper_clear_float_exceptions(void)
789 set_float_exception_flags(0, &env
->fp_status
);
792 float32
helper_fabss(float32 src
)
794 return float32_abs(src
);
797 #ifdef TARGET_SPARC64
798 void helper_fabsd(void)
800 DT0
= float64_abs(DT1
);
803 void helper_fabsq(void)
805 QT0
= float128_abs(QT1
);
809 float32
helper_fsqrts(float32 src
)
811 return float32_sqrt(src
, &env
->fp_status
);
814 void helper_fsqrtd(void)
816 DT0
= float64_sqrt(DT1
, &env
->fp_status
);
819 void helper_fsqrtq(void)
821 QT0
= float128_sqrt(QT1
, &env
->fp_status
);
824 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
825 void glue(helper_, name) (void) \
827 target_ulong new_fsr; \
829 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
830 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
831 case float_relation_unordered: \
832 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
833 if ((env->fsr & FSR_NVM) || TRAP) { \
834 env->fsr |= new_fsr; \
835 env->fsr |= FSR_NVC; \
836 env->fsr |= FSR_FTT_IEEE_EXCP; \
837 raise_exception(TT_FP_EXCP); \
839 env->fsr |= FSR_NVA; \
842 case float_relation_less: \
843 new_fsr = FSR_FCC0 << FS; \
845 case float_relation_greater: \
846 new_fsr = FSR_FCC1 << FS; \
852 env->fsr |= new_fsr; \
854 #define GEN_FCMPS(name, size, FS, TRAP) \
855 void glue(helper_, name)(float32 src1, float32 src2) \
857 target_ulong new_fsr; \
859 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
860 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
861 case float_relation_unordered: \
862 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
863 if ((env->fsr & FSR_NVM) || TRAP) { \
864 env->fsr |= new_fsr; \
865 env->fsr |= FSR_NVC; \
866 env->fsr |= FSR_FTT_IEEE_EXCP; \
867 raise_exception(TT_FP_EXCP); \
869 env->fsr |= FSR_NVA; \
872 case float_relation_less: \
873 new_fsr = FSR_FCC0 << FS; \
875 case float_relation_greater: \
876 new_fsr = FSR_FCC1 << FS; \
882 env->fsr |= new_fsr; \
885 GEN_FCMPS(fcmps
, float32
, 0, 0);
886 GEN_FCMP(fcmpd
, float64
, DT0
, DT1
, 0, 0);
888 GEN_FCMPS(fcmpes
, float32
, 0, 1);
889 GEN_FCMP(fcmped
, float64
, DT0
, DT1
, 0, 1);
891 GEN_FCMP(fcmpq
, float128
, QT0
, QT1
, 0, 0);
892 GEN_FCMP(fcmpeq
, float128
, QT0
, QT1
, 0, 1);
894 static uint32_t compute_all_flags(void)
896 return env
->psr
& PSR_ICC
;
899 static uint32_t compute_C_flags(void)
901 return env
->psr
& PSR_CARRY
;
904 static inline uint32_t get_NZ_icc(target_ulong dst
)
908 if (!(dst
& 0xffffffffULL
))
910 if ((int32_t) (dst
& 0xffffffffULL
) < 0)
915 #ifdef TARGET_SPARC64
916 static uint32_t compute_all_flags_xcc(void)
918 return env
->xcc
& PSR_ICC
;
921 static uint32_t compute_C_flags_xcc(void)
923 return env
->xcc
& PSR_CARRY
;
926 static inline uint32_t get_NZ_xcc(target_ulong dst
)
932 if ((int64_t)dst
< 0)
938 static inline uint32_t get_V_div_icc(target_ulong src2
)
947 static uint32_t compute_all_div(void)
951 ret
= get_NZ_icc(CC_DST
);
952 ret
|= get_V_div_icc(CC_SRC2
);
956 static uint32_t compute_C_div(void)
961 /* carry = (src1[31] & src2[31]) | ( ~dst[31] & (src1[31] | src2[31])) */
962 static inline uint32_t get_C_add_icc(target_ulong dst
, target_ulong src1
,
967 if (((src1
& (1ULL << 31)) & (src2
& (1ULL << 31)))
968 | ((~(dst
& (1ULL << 31)))
969 & ((src1
& (1ULL << 31)) | (src2
& (1ULL << 31)))))
974 static inline uint32_t get_V_add_icc(target_ulong dst
, target_ulong src1
,
979 if (((src1
^ src2
^ -1) & (src1
^ dst
)) & (1ULL << 31))
984 #ifdef TARGET_SPARC64
985 static inline uint32_t get_C_add_xcc(target_ulong dst
, target_ulong src1
)
994 static inline uint32_t get_V_add_xcc(target_ulong dst
, target_ulong src1
,
999 if (((src1
^ src2
^ -1) & (src1
^ dst
)) & (1ULL << 63))
1004 static uint32_t compute_all_add_xcc(void)
1008 ret
= get_NZ_xcc(CC_DST
);
1009 ret
|= get_C_add_xcc(CC_DST
, CC_SRC
);
1010 ret
|= get_V_add_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1014 static uint32_t compute_C_add_xcc(void)
1016 return get_C_add_xcc(CC_DST
, CC_SRC
);
1020 static uint32_t compute_all_add(void)
1024 ret
= get_NZ_icc(CC_DST
);
1025 ret
|= get_C_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1026 ret
|= get_V_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1030 static uint32_t compute_C_add(void)
1032 return get_C_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1035 #ifdef TARGET_SPARC64
1036 static uint32_t compute_all_addx_xcc(void)
1040 ret
= get_NZ_xcc(CC_DST
);
1041 ret
|= get_C_add_xcc(CC_DST
- CC_SRC2
, CC_SRC
);
1042 ret
|= get_C_add_xcc(CC_DST
, CC_SRC
);
1043 ret
|= get_V_add_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1047 static uint32_t compute_C_addx_xcc(void)
1051 ret
= get_C_add_xcc(CC_DST
- CC_SRC2
, CC_SRC
);
1052 ret
|= get_C_add_xcc(CC_DST
, CC_SRC
);
1057 static inline uint32_t get_V_tag_icc(target_ulong src1
, target_ulong src2
)
1061 if ((src1
| src2
) & 0x3)
1066 static uint32_t compute_all_tadd(void)
1070 ret
= get_NZ_icc(CC_DST
);
1071 ret
|= get_C_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1072 ret
|= get_V_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1073 ret
|= get_V_tag_icc(CC_SRC
, CC_SRC2
);
1077 static uint32_t compute_C_tadd(void)
1079 return get_C_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1082 static uint32_t compute_all_taddtv(void)
1086 ret
= get_NZ_icc(CC_DST
);
1087 ret
|= get_C_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1091 static uint32_t compute_C_taddtv(void)
1093 return get_C_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1096 /* carry = (~src1[31] & src2[31]) | ( dst[31] & (~src1[31] | src2[31])) */
1097 static inline uint32_t get_C_sub_icc(target_ulong dst
, target_ulong src1
,
1102 if (((~(src1
& (1ULL << 31))) & (src2
& (1ULL << 31)))
1103 | ((dst
& (1ULL << 31)) & (( ~(src1
& (1ULL << 31)))
1104 | (src2
& (1ULL << 31)))))
1109 static inline uint32_t get_V_sub_icc(target_ulong dst
, target_ulong src1
,
1114 if (((src1
^ src2
) & (src1
^ dst
)) & (1ULL << 31))
1120 #ifdef TARGET_SPARC64
1121 static inline uint32_t get_C_sub_xcc(target_ulong src1
, target_ulong src2
)
1130 static inline uint32_t get_V_sub_xcc(target_ulong dst
, target_ulong src1
,
1135 if (((src1
^ src2
) & (src1
^ dst
)) & (1ULL << 63))
1140 static uint32_t compute_all_sub_xcc(void)
1144 ret
= get_NZ_xcc(CC_DST
);
1145 ret
|= get_C_sub_xcc(CC_SRC
, CC_SRC2
);
1146 ret
|= get_V_sub_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1150 static uint32_t compute_C_sub_xcc(void)
1152 return get_C_sub_xcc(CC_SRC
, CC_SRC2
);
1156 static uint32_t compute_all_sub(void)
1160 ret
= get_NZ_icc(CC_DST
);
1161 ret
|= get_C_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1162 ret
|= get_V_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1166 static uint32_t compute_C_sub(void)
1168 return get_C_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1171 #ifdef TARGET_SPARC64
1172 static uint32_t compute_all_subx_xcc(void)
1176 ret
= get_NZ_xcc(CC_DST
);
1177 ret
|= get_C_sub_xcc(CC_DST
- CC_SRC2
, CC_SRC
);
1178 ret
|= get_C_sub_xcc(CC_DST
, CC_SRC2
);
1179 ret
|= get_V_sub_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1183 static uint32_t compute_C_subx_xcc(void)
1187 ret
= get_C_sub_xcc(CC_DST
- CC_SRC2
, CC_SRC
);
1188 ret
|= get_C_sub_xcc(CC_DST
, CC_SRC2
);
1193 static uint32_t compute_all_tsub(void)
1197 ret
= get_NZ_icc(CC_DST
);
1198 ret
|= get_C_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1199 ret
|= get_V_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1200 ret
|= get_V_tag_icc(CC_SRC
, CC_SRC2
);
1204 static uint32_t compute_C_tsub(void)
1206 return get_C_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1209 static uint32_t compute_all_tsubtv(void)
1213 ret
= get_NZ_icc(CC_DST
);
1214 ret
|= get_C_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1218 static uint32_t compute_C_tsubtv(void)
1220 return get_C_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1223 static uint32_t compute_all_logic(void)
1225 return get_NZ_icc(CC_DST
);
1228 static uint32_t compute_C_logic(void)
1233 #ifdef TARGET_SPARC64
1234 static uint32_t compute_all_logic_xcc(void)
1236 return get_NZ_xcc(CC_DST
);
1240 typedef struct CCTable
{
1241 uint32_t (*compute_all
)(void); /* return all the flags */
1242 uint32_t (*compute_c
)(void); /* return the C flag */
1245 static const CCTable icc_table
[CC_OP_NB
] = {
1246 /* CC_OP_DYNAMIC should never happen */
1247 [CC_OP_FLAGS
] = { compute_all_flags
, compute_C_flags
},
1248 [CC_OP_DIV
] = { compute_all_div
, compute_C_div
},
1249 [CC_OP_ADD
] = { compute_all_add
, compute_C_add
},
1250 [CC_OP_ADDX
] = { compute_all_add
, compute_C_add
},
1251 [CC_OP_TADD
] = { compute_all_tadd
, compute_C_tadd
},
1252 [CC_OP_TADDTV
] = { compute_all_taddtv
, compute_C_taddtv
},
1253 [CC_OP_SUB
] = { compute_all_sub
, compute_C_sub
},
1254 [CC_OP_SUBX
] = { compute_all_sub
, compute_C_sub
},
1255 [CC_OP_TSUB
] = { compute_all_tsub
, compute_C_tsub
},
1256 [CC_OP_TSUBTV
] = { compute_all_tsubtv
, compute_C_tsubtv
},
1257 [CC_OP_LOGIC
] = { compute_all_logic
, compute_C_logic
},
1260 #ifdef TARGET_SPARC64
1261 static const CCTable xcc_table
[CC_OP_NB
] = {
1262 /* CC_OP_DYNAMIC should never happen */
1263 [CC_OP_FLAGS
] = { compute_all_flags_xcc
, compute_C_flags_xcc
},
1264 [CC_OP_DIV
] = { compute_all_logic_xcc
, compute_C_logic
},
1265 [CC_OP_ADD
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1266 [CC_OP_ADDX
] = { compute_all_addx_xcc
, compute_C_addx_xcc
},
1267 [CC_OP_TADD
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1268 [CC_OP_TADDTV
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1269 [CC_OP_SUB
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1270 [CC_OP_SUBX
] = { compute_all_subx_xcc
, compute_C_subx_xcc
},
1271 [CC_OP_TSUB
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1272 [CC_OP_TSUBTV
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1273 [CC_OP_LOGIC
] = { compute_all_logic_xcc
, compute_C_logic
},
1277 void helper_compute_psr(void)
1281 new_psr
= icc_table
[CC_OP
].compute_all();
1283 #ifdef TARGET_SPARC64
1284 new_psr
= xcc_table
[CC_OP
].compute_all();
1287 CC_OP
= CC_OP_FLAGS
;
1290 uint32_t helper_compute_C_icc(void)
1294 ret
= icc_table
[CC_OP
].compute_c() >> PSR_CARRY_SHIFT
;
1298 #ifdef TARGET_SPARC64
1299 GEN_FCMPS(fcmps_fcc1
, float32
, 22, 0);
1300 GEN_FCMP(fcmpd_fcc1
, float64
, DT0
, DT1
, 22, 0);
1301 GEN_FCMP(fcmpq_fcc1
, float128
, QT0
, QT1
, 22, 0);
1303 GEN_FCMPS(fcmps_fcc2
, float32
, 24, 0);
1304 GEN_FCMP(fcmpd_fcc2
, float64
, DT0
, DT1
, 24, 0);
1305 GEN_FCMP(fcmpq_fcc2
, float128
, QT0
, QT1
, 24, 0);
1307 GEN_FCMPS(fcmps_fcc3
, float32
, 26, 0);
1308 GEN_FCMP(fcmpd_fcc3
, float64
, DT0
, DT1
, 26, 0);
1309 GEN_FCMP(fcmpq_fcc3
, float128
, QT0
, QT1
, 26, 0);
1311 GEN_FCMPS(fcmpes_fcc1
, float32
, 22, 1);
1312 GEN_FCMP(fcmped_fcc1
, float64
, DT0
, DT1
, 22, 1);
1313 GEN_FCMP(fcmpeq_fcc1
, float128
, QT0
, QT1
, 22, 1);
1315 GEN_FCMPS(fcmpes_fcc2
, float32
, 24, 1);
1316 GEN_FCMP(fcmped_fcc2
, float64
, DT0
, DT1
, 24, 1);
1317 GEN_FCMP(fcmpeq_fcc2
, float128
, QT0
, QT1
, 24, 1);
1319 GEN_FCMPS(fcmpes_fcc3
, float32
, 26, 1);
1320 GEN_FCMP(fcmped_fcc3
, float64
, DT0
, DT1
, 26, 1);
1321 GEN_FCMP(fcmpeq_fcc3
, float128
, QT0
, QT1
, 26, 1);
1325 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
1327 static void dump_mxcc(CPUState
*env
)
1329 printf("mxccdata: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1331 env
->mxccdata
[0], env
->mxccdata
[1],
1332 env
->mxccdata
[2], env
->mxccdata
[3]);
1333 printf("mxccregs: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1335 " %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1337 env
->mxccregs
[0], env
->mxccregs
[1],
1338 env
->mxccregs
[2], env
->mxccregs
[3],
1339 env
->mxccregs
[4], env
->mxccregs
[5],
1340 env
->mxccregs
[6], env
->mxccregs
[7]);
1344 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
1345 && defined(DEBUG_ASI)
1346 static void dump_asi(const char *txt
, target_ulong addr
, int asi
, int size
,
1352 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %02" PRIx64
"\n", txt
,
1353 addr
, asi
, r1
& 0xff);
1356 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %04" PRIx64
"\n", txt
,
1357 addr
, asi
, r1
& 0xffff);
1360 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %08" PRIx64
"\n", txt
,
1361 addr
, asi
, r1
& 0xffffffff);
1364 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %016" PRIx64
"\n", txt
,
1371 #ifndef TARGET_SPARC64
1372 #ifndef CONFIG_USER_ONLY
1373 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
1376 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
1377 uint32_t last_addr
= addr
;
1380 helper_check_align(addr
, size
- 1);
1382 case 2: /* SuperSparc MXCC registers */
1384 case 0x01c00a00: /* MXCC control register */
1386 ret
= env
->mxccregs
[3];
1388 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1391 case 0x01c00a04: /* MXCC control register */
1393 ret
= env
->mxccregs
[3];
1395 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1398 case 0x01c00c00: /* Module reset register */
1400 ret
= env
->mxccregs
[5];
1401 // should we do something here?
1403 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1406 case 0x01c00f00: /* MBus port address register */
1408 ret
= env
->mxccregs
[7];
1410 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1414 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
1418 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
1419 "addr = %08x -> ret = %" PRIx64
","
1420 "addr = %08x\n", asi
, size
, sign
, last_addr
, ret
, addr
);
1425 case 3: /* MMU probe */
1429 mmulev
= (addr
>> 8) & 15;
1433 ret
= mmu_probe(env
, addr
, mmulev
);
1434 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64
"\n",
1438 case 4: /* read MMU regs */
1440 int reg
= (addr
>> 8) & 0x1f;
1442 ret
= env
->mmuregs
[reg
];
1443 if (reg
== 3) /* Fault status cleared on read */
1444 env
->mmuregs
[3] = 0;
1445 else if (reg
== 0x13) /* Fault status read */
1446 ret
= env
->mmuregs
[3];
1447 else if (reg
== 0x14) /* Fault address read */
1448 ret
= env
->mmuregs
[4];
1449 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64
"\n", reg
, ret
);
1452 case 5: // Turbosparc ITLB Diagnostic
1453 case 6: // Turbosparc DTLB Diagnostic
1454 case 7: // Turbosparc IOTLB Diagnostic
1456 case 9: /* Supervisor code access */
1459 ret
= ldub_code(addr
);
1462 ret
= lduw_code(addr
);
1466 ret
= ldl_code(addr
);
1469 ret
= ldq_code(addr
);
1473 case 0xa: /* User data access */
1476 ret
= ldub_user(addr
);
1479 ret
= lduw_user(addr
);
1483 ret
= ldl_user(addr
);
1486 ret
= ldq_user(addr
);
1490 case 0xb: /* Supervisor data access */
1493 ret
= ldub_kernel(addr
);
1496 ret
= lduw_kernel(addr
);
1500 ret
= ldl_kernel(addr
);
1503 ret
= ldq_kernel(addr
);
1507 case 0xc: /* I-cache tag */
1508 case 0xd: /* I-cache data */
1509 case 0xe: /* D-cache tag */
1510 case 0xf: /* D-cache data */
1512 case 0x20: /* MMU passthrough */
1515 ret
= ldub_phys(addr
);
1518 ret
= lduw_phys(addr
);
1522 ret
= ldl_phys(addr
);
1525 ret
= ldq_phys(addr
);
1529 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1532 ret
= ldub_phys((target_phys_addr_t
)addr
1533 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1536 ret
= lduw_phys((target_phys_addr_t
)addr
1537 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1541 ret
= ldl_phys((target_phys_addr_t
)addr
1542 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1545 ret
= ldq_phys((target_phys_addr_t
)addr
1546 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1550 case 0x30: // Turbosparc secondary cache diagnostic
1551 case 0x31: // Turbosparc RAM snoop
1552 case 0x32: // Turbosparc page table descriptor diagnostic
1553 case 0x39: /* data cache diagnostic register */
1556 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
1558 int reg
= (addr
>> 8) & 3;
1561 case 0: /* Breakpoint Value (Addr) */
1562 ret
= env
->mmubpregs
[reg
];
1564 case 1: /* Breakpoint Mask */
1565 ret
= env
->mmubpregs
[reg
];
1567 case 2: /* Breakpoint Control */
1568 ret
= env
->mmubpregs
[reg
];
1570 case 3: /* Breakpoint Status */
1571 ret
= env
->mmubpregs
[reg
];
1572 env
->mmubpregs
[reg
] = 0ULL;
1575 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64
"\n", reg
,
1579 case 8: /* User code access, XXX */
1581 do_unassigned_access(addr
, 0, 0, asi
, size
);
1591 ret
= (int16_t) ret
;
1594 ret
= (int32_t) ret
;
1601 dump_asi("read ", last_addr
, asi
, size
, ret
);
1606 void helper_st_asi(target_ulong addr
, uint64_t val
, int asi
, int size
)
1608 helper_check_align(addr
, size
- 1);
1610 case 2: /* SuperSparc MXCC registers */
1612 case 0x01c00000: /* MXCC stream data register 0 */
1614 env
->mxccdata
[0] = val
;
1616 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1619 case 0x01c00008: /* MXCC stream data register 1 */
1621 env
->mxccdata
[1] = val
;
1623 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1626 case 0x01c00010: /* MXCC stream data register 2 */
1628 env
->mxccdata
[2] = val
;
1630 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1633 case 0x01c00018: /* MXCC stream data register 3 */
1635 env
->mxccdata
[3] = val
;
1637 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1640 case 0x01c00100: /* MXCC stream source */
1642 env
->mxccregs
[0] = val
;
1644 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1646 env
->mxccdata
[0] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1648 env
->mxccdata
[1] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1650 env
->mxccdata
[2] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1652 env
->mxccdata
[3] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1655 case 0x01c00200: /* MXCC stream destination */
1657 env
->mxccregs
[1] = val
;
1659 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1661 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 0,
1663 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 8,
1665 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 16,
1667 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 24,
1670 case 0x01c00a00: /* MXCC control register */
1672 env
->mxccregs
[3] = val
;
1674 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1677 case 0x01c00a04: /* MXCC control register */
1679 env
->mxccregs
[3] = (env
->mxccregs
[3] & 0xffffffff00000000ULL
)
1682 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1685 case 0x01c00e00: /* MXCC error register */
1686 // writing a 1 bit clears the error
1688 env
->mxccregs
[6] &= ~val
;
1690 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1693 case 0x01c00f00: /* MBus port address register */
1695 env
->mxccregs
[7] = val
;
1697 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1701 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
1705 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64
"\n",
1706 asi
, size
, addr
, val
);
1711 case 3: /* MMU flush */
1715 mmulev
= (addr
>> 8) & 15;
1716 DPRINTF_MMU("mmu flush level %d\n", mmulev
);
1718 case 0: // flush page
1719 tlb_flush_page(env
, addr
& 0xfffff000);
1721 case 1: // flush segment (256k)
1722 case 2: // flush region (16M)
1723 case 3: // flush context (4G)
1724 case 4: // flush entire
1735 case 4: /* write MMU regs */
1737 int reg
= (addr
>> 8) & 0x1f;
1740 oldreg
= env
->mmuregs
[reg
];
1742 case 0: // Control Register
1743 env
->mmuregs
[reg
] = (env
->mmuregs
[reg
] & 0xff000000) |
1745 // Mappings generated during no-fault mode or MMU
1746 // disabled mode are invalid in normal mode
1747 if ((oldreg
& (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)) !=
1748 (env
->mmuregs
[reg
] & (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)))
1751 case 1: // Context Table Pointer Register
1752 env
->mmuregs
[reg
] = val
& env
->def
->mmu_ctpr_mask
;
1754 case 2: // Context Register
1755 env
->mmuregs
[reg
] = val
& env
->def
->mmu_cxr_mask
;
1756 if (oldreg
!= env
->mmuregs
[reg
]) {
1757 /* we flush when the MMU context changes because
1758 QEMU has no MMU context support */
1762 case 3: // Synchronous Fault Status Register with Clear
1763 case 4: // Synchronous Fault Address Register
1765 case 0x10: // TLB Replacement Control Register
1766 env
->mmuregs
[reg
] = val
& env
->def
->mmu_trcr_mask
;
1768 case 0x13: // Synchronous Fault Status Register with Read and Clear
1769 env
->mmuregs
[3] = val
& env
->def
->mmu_sfsr_mask
;
1771 case 0x14: // Synchronous Fault Address Register
1772 env
->mmuregs
[4] = val
;
1775 env
->mmuregs
[reg
] = val
;
1778 if (oldreg
!= env
->mmuregs
[reg
]) {
1779 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1780 reg
, oldreg
, env
->mmuregs
[reg
]);
1787 case 5: // Turbosparc ITLB Diagnostic
1788 case 6: // Turbosparc DTLB Diagnostic
1789 case 7: // Turbosparc IOTLB Diagnostic
1791 case 0xa: /* User data access */
1794 stb_user(addr
, val
);
1797 stw_user(addr
, val
);
1801 stl_user(addr
, val
);
1804 stq_user(addr
, val
);
1808 case 0xb: /* Supervisor data access */
1811 stb_kernel(addr
, val
);
1814 stw_kernel(addr
, val
);
1818 stl_kernel(addr
, val
);
1821 stq_kernel(addr
, val
);
1825 case 0xc: /* I-cache tag */
1826 case 0xd: /* I-cache data */
1827 case 0xe: /* D-cache tag */
1828 case 0xf: /* D-cache data */
1829 case 0x10: /* I/D-cache flush page */
1830 case 0x11: /* I/D-cache flush segment */
1831 case 0x12: /* I/D-cache flush region */
1832 case 0x13: /* I/D-cache flush context */
1833 case 0x14: /* I/D-cache flush user */
1835 case 0x17: /* Block copy, sta access */
1841 uint32_t src
= val
& ~3, dst
= addr
& ~3, temp
;
1843 for (i
= 0; i
< 32; i
+= 4, src
+= 4, dst
+= 4) {
1844 temp
= ldl_kernel(src
);
1845 stl_kernel(dst
, temp
);
1849 case 0x1f: /* Block fill, stda access */
1852 // fill 32 bytes with val
1854 uint32_t dst
= addr
& 7;
1856 for (i
= 0; i
< 32; i
+= 8, dst
+= 8)
1857 stq_kernel(dst
, val
);
1860 case 0x20: /* MMU passthrough */
1864 stb_phys(addr
, val
);
1867 stw_phys(addr
, val
);
1871 stl_phys(addr
, val
);
1874 stq_phys(addr
, val
);
1879 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1883 stb_phys((target_phys_addr_t
)addr
1884 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1887 stw_phys((target_phys_addr_t
)addr
1888 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1892 stl_phys((target_phys_addr_t
)addr
1893 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1896 stq_phys((target_phys_addr_t
)addr
1897 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1902 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
1903 case 0x31: // store buffer data, Ross RT620 I-cache flush or
1904 // Turbosparc snoop RAM
1905 case 0x32: // store buffer control or Turbosparc page table
1906 // descriptor diagnostic
1907 case 0x36: /* I-cache flash clear */
1908 case 0x37: /* D-cache flash clear */
1909 case 0x4c: /* breakpoint action */
1911 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1913 int reg
= (addr
>> 8) & 3;
1916 case 0: /* Breakpoint Value (Addr) */
1917 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1919 case 1: /* Breakpoint Mask */
1920 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1922 case 2: /* Breakpoint Control */
1923 env
->mmubpregs
[reg
] = (val
& 0x7fULL
);
1925 case 3: /* Breakpoint Status */
1926 env
->mmubpregs
[reg
] = (val
& 0xfULL
);
1929 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg
,
1933 case 8: /* User code access, XXX */
1934 case 9: /* Supervisor code access, XXX */
1936 do_unassigned_access(addr
, 1, 0, asi
, size
);
1940 dump_asi("write", addr
, asi
, size
, val
);
1944 #endif /* CONFIG_USER_ONLY */
1945 #else /* TARGET_SPARC64 */
1947 #ifdef CONFIG_USER_ONLY
1948 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
1951 #if defined(DEBUG_ASI)
1952 target_ulong last_addr
= addr
;
1956 raise_exception(TT_PRIV_ACT
);
1958 helper_check_align(addr
, size
- 1);
1959 addr
= address_mask(env
, addr
);
1962 case 0x82: // Primary no-fault
1963 case 0x8a: // Primary no-fault LE
1964 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1966 dump_asi("read ", last_addr
, asi
, size
, ret
);
1971 case 0x80: // Primary
1972 case 0x88: // Primary LE
1976 ret
= ldub_raw(addr
);
1979 ret
= lduw_raw(addr
);
1982 ret
= ldl_raw(addr
);
1986 ret
= ldq_raw(addr
);
1991 case 0x83: // Secondary no-fault
1992 case 0x8b: // Secondary no-fault LE
1993 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1995 dump_asi("read ", last_addr
, asi
, size
, ret
);
2000 case 0x81: // Secondary
2001 case 0x89: // Secondary LE
2008 /* Convert from little endian */
2010 case 0x88: // Primary LE
2011 case 0x89: // Secondary LE
2012 case 0x8a: // Primary no-fault LE
2013 case 0x8b: // Secondary no-fault LE
2031 /* Convert to signed number */
2038 ret
= (int16_t) ret
;
2041 ret
= (int32_t) ret
;
2048 dump_asi("read ", last_addr
, asi
, size
, ret
);
2053 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
2056 dump_asi("write", addr
, asi
, size
, val
);
2059 raise_exception(TT_PRIV_ACT
);
2061 helper_check_align(addr
, size
- 1);
2062 addr
= address_mask(env
, addr
);
2064 /* Convert to little endian */
2066 case 0x88: // Primary LE
2067 case 0x89: // Secondary LE
2086 case 0x80: // Primary
2087 case 0x88: // Primary LE
2106 case 0x81: // Secondary
2107 case 0x89: // Secondary LE
2111 case 0x82: // Primary no-fault, RO
2112 case 0x83: // Secondary no-fault, RO
2113 case 0x8a: // Primary no-fault LE, RO
2114 case 0x8b: // Secondary no-fault LE, RO
2116 do_unassigned_access(addr
, 1, 0, 1, size
);
2121 #else /* CONFIG_USER_ONLY */
2123 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
2126 #if defined(DEBUG_ASI)
2127 target_ulong last_addr
= addr
;
2132 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2133 || ((env
->def
->features
& CPU_FEATURE_HYPV
)
2134 && asi
>= 0x30 && asi
< 0x80
2135 && !(env
->hpstate
& HS_PRIV
)))
2136 raise_exception(TT_PRIV_ACT
);
2138 helper_check_align(addr
, size
- 1);
2140 case 0x82: // Primary no-fault
2141 case 0x8a: // Primary no-fault LE
2142 case 0x83: // Secondary no-fault
2143 case 0x8b: // Secondary no-fault LE
2145 /* secondary space access has lowest asi bit equal to 1 */
2146 int access_mmu_idx
= ( asi
& 1 ) ? MMU_KERNEL_IDX
2147 : MMU_KERNEL_SECONDARY_IDX
;
2149 if (cpu_get_phys_page_nofault(env
, addr
, access_mmu_idx
) == -1ULL) {
2151 dump_asi("read ", last_addr
, asi
, size
, ret
);
2157 case 0x10: // As if user primary
2158 case 0x11: // As if user secondary
2159 case 0x18: // As if user primary LE
2160 case 0x19: // As if user secondary LE
2161 case 0x80: // Primary
2162 case 0x81: // Secondary
2163 case 0x88: // Primary LE
2164 case 0x89: // Secondary LE
2165 case 0xe2: // UA2007 Primary block init
2166 case 0xe3: // UA2007 Secondary block init
2167 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
2168 if ((env
->def
->features
& CPU_FEATURE_HYPV
)
2169 && env
->hpstate
& HS_PRIV
) {
2172 ret
= ldub_hypv(addr
);
2175 ret
= lduw_hypv(addr
);
2178 ret
= ldl_hypv(addr
);
2182 ret
= ldq_hypv(addr
);
2186 /* secondary space access has lowest asi bit equal to 1 */
2190 ret
= ldub_kernel_secondary(addr
);
2193 ret
= lduw_kernel_secondary(addr
);
2196 ret
= ldl_kernel_secondary(addr
);
2200 ret
= ldq_kernel_secondary(addr
);
2206 ret
= ldub_kernel(addr
);
2209 ret
= lduw_kernel(addr
);
2212 ret
= ldl_kernel(addr
);
2216 ret
= ldq_kernel(addr
);
2222 /* secondary space access has lowest asi bit equal to 1 */
2226 ret
= ldub_user_secondary(addr
);
2229 ret
= lduw_user_secondary(addr
);
2232 ret
= ldl_user_secondary(addr
);
2236 ret
= ldq_user_secondary(addr
);
2242 ret
= ldub_user(addr
);
2245 ret
= lduw_user(addr
);
2248 ret
= ldl_user(addr
);
2252 ret
= ldq_user(addr
);
2258 case 0x14: // Bypass
2259 case 0x15: // Bypass, non-cacheable
2260 case 0x1c: // Bypass LE
2261 case 0x1d: // Bypass, non-cacheable LE
2265 ret
= ldub_phys(addr
);
2268 ret
= lduw_phys(addr
);
2271 ret
= ldl_phys(addr
);
2275 ret
= ldq_phys(addr
);
2280 case 0x24: // Nucleus quad LDD 128 bit atomic
2281 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2282 // Only ldda allowed
2283 raise_exception(TT_ILL_INSN
);
2285 case 0x04: // Nucleus
2286 case 0x0c: // Nucleus Little Endian (LE)
2290 ret
= ldub_nucleus(addr
);
2293 ret
= lduw_nucleus(addr
);
2296 ret
= ldl_nucleus(addr
);
2300 ret
= ldq_nucleus(addr
);
2305 case 0x4a: // UPA config
2311 case 0x50: // I-MMU regs
2313 int reg
= (addr
>> 3) & 0xf;
2316 // I-TSB Tag Target register
2317 ret
= ultrasparc_tag_target(env
->immu
.tag_access
);
2319 ret
= env
->immuregs
[reg
];
2324 case 0x51: // I-MMU 8k TSB pointer
2326 // env->immuregs[5] holds I-MMU TSB register value
2327 // env->immuregs[6] holds I-MMU Tag Access register value
2328 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
2332 case 0x52: // I-MMU 64k TSB pointer
2334 // env->immuregs[5] holds I-MMU TSB register value
2335 // env->immuregs[6] holds I-MMU Tag Access register value
2336 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
2340 case 0x55: // I-MMU data access
2342 int reg
= (addr
>> 3) & 0x3f;
2344 ret
= env
->itlb
[reg
].tte
;
2347 case 0x56: // I-MMU tag read
2349 int reg
= (addr
>> 3) & 0x3f;
2351 ret
= env
->itlb
[reg
].tag
;
2354 case 0x58: // D-MMU regs
2356 int reg
= (addr
>> 3) & 0xf;
2359 // D-TSB Tag Target register
2360 ret
= ultrasparc_tag_target(env
->dmmu
.tag_access
);
2362 ret
= env
->dmmuregs
[reg
];
2366 case 0x59: // D-MMU 8k TSB pointer
2368 // env->dmmuregs[5] holds D-MMU TSB register value
2369 // env->dmmuregs[6] holds D-MMU Tag Access register value
2370 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
2374 case 0x5a: // D-MMU 64k TSB pointer
2376 // env->dmmuregs[5] holds D-MMU TSB register value
2377 // env->dmmuregs[6] holds D-MMU Tag Access register value
2378 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
2382 case 0x5d: // D-MMU data access
2384 int reg
= (addr
>> 3) & 0x3f;
2386 ret
= env
->dtlb
[reg
].tte
;
2389 case 0x5e: // D-MMU tag read
2391 int reg
= (addr
>> 3) & 0x3f;
2393 ret
= env
->dtlb
[reg
].tag
;
2396 case 0x46: // D-cache data
2397 case 0x47: // D-cache tag access
2398 case 0x4b: // E-cache error enable
2399 case 0x4c: // E-cache asynchronous fault status
2400 case 0x4d: // E-cache asynchronous fault address
2401 case 0x4e: // E-cache tag data
2402 case 0x66: // I-cache instruction access
2403 case 0x67: // I-cache tag access
2404 case 0x6e: // I-cache predecode
2405 case 0x6f: // I-cache LRU etc.
2406 case 0x76: // E-cache tag
2407 case 0x7e: // E-cache tag
2409 case 0x5b: // D-MMU data pointer
2410 case 0x48: // Interrupt dispatch, RO
2411 case 0x49: // Interrupt data receive
2412 case 0x7f: // Incoming interrupt vector, RO
2415 case 0x54: // I-MMU data in, WO
2416 case 0x57: // I-MMU demap, WO
2417 case 0x5c: // D-MMU data in, WO
2418 case 0x5f: // D-MMU demap, WO
2419 case 0x77: // Interrupt vector, WO
2421 do_unassigned_access(addr
, 0, 0, 1, size
);
2426 /* Convert from little endian */
2428 case 0x0c: // Nucleus Little Endian (LE)
2429 case 0x18: // As if user primary LE
2430 case 0x19: // As if user secondary LE
2431 case 0x1c: // Bypass LE
2432 case 0x1d: // Bypass, non-cacheable LE
2433 case 0x88: // Primary LE
2434 case 0x89: // Secondary LE
2435 case 0x8a: // Primary no-fault LE
2436 case 0x8b: // Secondary no-fault LE
2454 /* Convert to signed number */
2461 ret
= (int16_t) ret
;
2464 ret
= (int32_t) ret
;
2471 dump_asi("read ", last_addr
, asi
, size
, ret
);
2476 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
2479 dump_asi("write", addr
, asi
, size
, val
);
2484 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2485 || ((env
->def
->features
& CPU_FEATURE_HYPV
)
2486 && asi
>= 0x30 && asi
< 0x80
2487 && !(env
->hpstate
& HS_PRIV
)))
2488 raise_exception(TT_PRIV_ACT
);
2490 helper_check_align(addr
, size
- 1);
2491 /* Convert to little endian */
2493 case 0x0c: // Nucleus Little Endian (LE)
2494 case 0x18: // As if user primary LE
2495 case 0x19: // As if user secondary LE
2496 case 0x1c: // Bypass LE
2497 case 0x1d: // Bypass, non-cacheable LE
2498 case 0x88: // Primary LE
2499 case 0x89: // Secondary LE
2518 case 0x10: // As if user primary
2519 case 0x11: // As if user secondary
2520 case 0x18: // As if user primary LE
2521 case 0x19: // As if user secondary LE
2522 case 0x80: // Primary
2523 case 0x81: // Secondary
2524 case 0x88: // Primary LE
2525 case 0x89: // Secondary LE
2526 case 0xe2: // UA2007 Primary block init
2527 case 0xe3: // UA2007 Secondary block init
2528 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
2529 if ((env
->def
->features
& CPU_FEATURE_HYPV
)
2530 && env
->hpstate
& HS_PRIV
) {
2533 stb_hypv(addr
, val
);
2536 stw_hypv(addr
, val
);
2539 stl_hypv(addr
, val
);
2543 stq_hypv(addr
, val
);
2547 /* secondary space access has lowest asi bit equal to 1 */
2551 stb_kernel_secondary(addr
, val
);
2554 stw_kernel_secondary(addr
, val
);
2557 stl_kernel_secondary(addr
, val
);
2561 stq_kernel_secondary(addr
, val
);
2567 stb_kernel(addr
, val
);
2570 stw_kernel(addr
, val
);
2573 stl_kernel(addr
, val
);
2577 stq_kernel(addr
, val
);
2583 /* secondary space access has lowest asi bit equal to 1 */
2587 stb_user_secondary(addr
, val
);
2590 stw_user_secondary(addr
, val
);
2593 stl_user_secondary(addr
, val
);
2597 stq_user_secondary(addr
, val
);
2603 stb_user(addr
, val
);
2606 stw_user(addr
, val
);
2609 stl_user(addr
, val
);
2613 stq_user(addr
, val
);
2619 case 0x14: // Bypass
2620 case 0x15: // Bypass, non-cacheable
2621 case 0x1c: // Bypass LE
2622 case 0x1d: // Bypass, non-cacheable LE
2626 stb_phys(addr
, val
);
2629 stw_phys(addr
, val
);
2632 stl_phys(addr
, val
);
2636 stq_phys(addr
, val
);
2641 case 0x24: // Nucleus quad LDD 128 bit atomic
2642 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2643 // Only ldda allowed
2644 raise_exception(TT_ILL_INSN
);
2646 case 0x04: // Nucleus
2647 case 0x0c: // Nucleus Little Endian (LE)
2651 stb_nucleus(addr
, val
);
2654 stw_nucleus(addr
, val
);
2657 stl_nucleus(addr
, val
);
2661 stq_nucleus(addr
, val
);
2667 case 0x4a: // UPA config
2675 env
->lsu
= val
& (DMMU_E
| IMMU_E
);
2676 // Mappings generated during D/I MMU disabled mode are
2677 // invalid in normal mode
2678 if (oldreg
!= env
->lsu
) {
2679 DPRINTF_MMU("LSU change: 0x%" PRIx64
" -> 0x%" PRIx64
"\n",
2688 case 0x50: // I-MMU regs
2690 int reg
= (addr
>> 3) & 0xf;
2693 oldreg
= env
->immuregs
[reg
];
2697 case 1: // Not in I-MMU
2702 val
= 0; // Clear SFSR
2703 env
->immu
.sfsr
= val
;
2707 case 5: // TSB access
2708 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64
" -> 0x%016"
2709 PRIx64
"\n", env
->immu
.tsb
, val
);
2710 env
->immu
.tsb
= val
;
2712 case 6: // Tag access
2713 env
->immu
.tag_access
= val
;
2722 if (oldreg
!= env
->immuregs
[reg
]) {
2723 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
2724 PRIx64
"\n", reg
, oldreg
, env
->immuregs
[reg
]);
2731 case 0x54: // I-MMU data in
2732 replace_tlb_1bit_lru(env
->itlb
, env
->immu
.tag_access
, val
, "immu", env
);
2734 case 0x55: // I-MMU data access
2738 unsigned int i
= (addr
>> 3) & 0x3f;
2740 replace_tlb_entry(&env
->itlb
[i
], env
->immu
.tag_access
, val
, env
);
2743 DPRINTF_MMU("immu data access replaced entry [%i]\n", i
);
2748 case 0x57: // I-MMU demap
2749 demap_tlb(env
->itlb
, val
, "immu", env
);
2751 case 0x58: // D-MMU regs
2753 int reg
= (addr
>> 3) & 0xf;
2756 oldreg
= env
->dmmuregs
[reg
];
2762 if ((val
& 1) == 0) {
2763 val
= 0; // Clear SFSR, Fault address
2766 env
->dmmu
.sfsr
= val
;
2768 case 1: // Primary context
2769 env
->dmmu
.mmu_primary_context
= val
;
2771 case 2: // Secondary context
2772 env
->dmmu
.mmu_secondary_context
= val
;
2774 case 5: // TSB access
2775 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64
" -> 0x%016"
2776 PRIx64
"\n", env
->dmmu
.tsb
, val
);
2777 env
->dmmu
.tsb
= val
;
2779 case 6: // Tag access
2780 env
->dmmu
.tag_access
= val
;
2782 case 7: // Virtual Watchpoint
2783 case 8: // Physical Watchpoint
2785 env
->dmmuregs
[reg
] = val
;
2789 if (oldreg
!= env
->dmmuregs
[reg
]) {
2790 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
2791 PRIx64
"\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
2798 case 0x5c: // D-MMU data in
2799 replace_tlb_1bit_lru(env
->dtlb
, env
->dmmu
.tag_access
, val
, "dmmu", env
);
2801 case 0x5d: // D-MMU data access
2803 unsigned int i
= (addr
>> 3) & 0x3f;
2805 replace_tlb_entry(&env
->dtlb
[i
], env
->dmmu
.tag_access
, val
, env
);
2808 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i
);
2813 case 0x5f: // D-MMU demap
2814 demap_tlb(env
->dtlb
, val
, "dmmu", env
);
2816 case 0x49: // Interrupt data receive
2819 case 0x46: // D-cache data
2820 case 0x47: // D-cache tag access
2821 case 0x4b: // E-cache error enable
2822 case 0x4c: // E-cache asynchronous fault status
2823 case 0x4d: // E-cache asynchronous fault address
2824 case 0x4e: // E-cache tag data
2825 case 0x66: // I-cache instruction access
2826 case 0x67: // I-cache tag access
2827 case 0x6e: // I-cache predecode
2828 case 0x6f: // I-cache LRU etc.
2829 case 0x76: // E-cache tag
2830 case 0x7e: // E-cache tag
2832 case 0x51: // I-MMU 8k TSB pointer, RO
2833 case 0x52: // I-MMU 64k TSB pointer, RO
2834 case 0x56: // I-MMU tag read, RO
2835 case 0x59: // D-MMU 8k TSB pointer, RO
2836 case 0x5a: // D-MMU 64k TSB pointer, RO
2837 case 0x5b: // D-MMU data pointer, RO
2838 case 0x5e: // D-MMU tag read, RO
2839 case 0x48: // Interrupt dispatch, RO
2840 case 0x7f: // Incoming interrupt vector, RO
2841 case 0x82: // Primary no-fault, RO
2842 case 0x83: // Secondary no-fault, RO
2843 case 0x8a: // Primary no-fault LE, RO
2844 case 0x8b: // Secondary no-fault LE, RO
2846 do_unassigned_access(addr
, 1, 0, 1, size
);
2850 #endif /* CONFIG_USER_ONLY */
2852 void helper_ldda_asi(target_ulong addr
, int asi
, int rd
)
2854 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2855 || ((env
->def
->features
& CPU_FEATURE_HYPV
)
2856 && asi
>= 0x30 && asi
< 0x80
2857 && !(env
->hpstate
& HS_PRIV
)))
2858 raise_exception(TT_PRIV_ACT
);
2861 case 0x24: // Nucleus quad LDD 128 bit atomic
2862 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2863 helper_check_align(addr
, 0xf);
2865 env
->gregs
[1] = ldq_kernel(addr
+ 8);
2867 bswap64s(&env
->gregs
[1]);
2868 } else if (rd
< 8) {
2869 env
->gregs
[rd
] = ldq_kernel(addr
);
2870 env
->gregs
[rd
+ 1] = ldq_kernel(addr
+ 8);
2872 bswap64s(&env
->gregs
[rd
]);
2873 bswap64s(&env
->gregs
[rd
+ 1]);
2876 env
->regwptr
[rd
] = ldq_kernel(addr
);
2877 env
->regwptr
[rd
+ 1] = ldq_kernel(addr
+ 8);
2879 bswap64s(&env
->regwptr
[rd
]);
2880 bswap64s(&env
->regwptr
[rd
+ 1]);
2885 helper_check_align(addr
, 0x3);
2887 env
->gregs
[1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
2889 env
->gregs
[rd
] = helper_ld_asi(addr
, asi
, 4, 0);
2890 env
->gregs
[rd
+ 1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
2892 env
->regwptr
[rd
] = helper_ld_asi(addr
, asi
, 4, 0);
2893 env
->regwptr
[rd
+ 1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
2899 void helper_ldf_asi(target_ulong addr
, int asi
, int size
, int rd
)
2904 helper_check_align(addr
, 3);
2906 case 0xf0: // Block load primary
2907 case 0xf1: // Block load secondary
2908 case 0xf8: // Block load primary LE
2909 case 0xf9: // Block load secondary LE
2911 raise_exception(TT_ILL_INSN
);
2914 helper_check_align(addr
, 0x3f);
2915 for (i
= 0; i
< 16; i
++) {
2916 *(uint32_t *)&env
->fpr
[rd
++] = helper_ld_asi(addr
, asi
& 0x8f, 4,
2926 val
= helper_ld_asi(addr
, asi
, size
, 0);
2930 *((uint32_t *)&env
->fpr
[rd
]) = val
;
2933 *((int64_t *)&DT0
) = val
;
2941 void helper_stf_asi(target_ulong addr
, int asi
, int size
, int rd
)
2944 target_ulong val
= 0;
2946 helper_check_align(addr
, 3);
2948 case 0xe0: // UA2007 Block commit store primary (cache flush)
2949 case 0xe1: // UA2007 Block commit store secondary (cache flush)
2950 case 0xf0: // Block store primary
2951 case 0xf1: // Block store secondary
2952 case 0xf8: // Block store primary LE
2953 case 0xf9: // Block store secondary LE
2955 raise_exception(TT_ILL_INSN
);
2958 helper_check_align(addr
, 0x3f);
2959 for (i
= 0; i
< 16; i
++) {
2960 val
= *(uint32_t *)&env
->fpr
[rd
++];
2961 helper_st_asi(addr
, val
, asi
& 0x8f, 4);
2973 val
= *((uint32_t *)&env
->fpr
[rd
]);
2976 val
= *((int64_t *)&DT0
);
2982 helper_st_asi(addr
, val
, asi
, size
);
2985 target_ulong
helper_cas_asi(target_ulong addr
, target_ulong val1
,
2986 target_ulong val2
, uint32_t asi
)
2990 val2
&= 0xffffffffUL
;
2991 ret
= helper_ld_asi(addr
, asi
, 4, 0);
2992 ret
&= 0xffffffffUL
;
2994 helper_st_asi(addr
, val1
& 0xffffffffUL
, asi
, 4);
2998 target_ulong
helper_casx_asi(target_ulong addr
, target_ulong val1
,
2999 target_ulong val2
, uint32_t asi
)
3003 ret
= helper_ld_asi(addr
, asi
, 8, 0);
3005 helper_st_asi(addr
, val1
, asi
, 8);
3008 #endif /* TARGET_SPARC64 */
3010 #ifndef TARGET_SPARC64
3011 void helper_rett(void)
3015 if (env
->psret
== 1)
3016 raise_exception(TT_ILL_INSN
);
3019 cwp
= cpu_cwp_inc(env
, env
->cwp
+ 1) ;
3020 if (env
->wim
& (1 << cwp
)) {
3021 raise_exception(TT_WIN_UNF
);
3024 env
->psrs
= env
->psrps
;
3028 target_ulong
helper_udiv(target_ulong a
, target_ulong b
)
3033 x0
= (a
& 0xffffffff) | ((int64_t) (env
->y
) << 32);
3037 raise_exception(TT_DIV_ZERO
);
3041 if (x0
> 0xffffffff) {
3050 target_ulong
helper_sdiv(target_ulong a
, target_ulong b
)
3055 x0
= (a
& 0xffffffff) | ((int64_t) (env
->y
) << 32);
3059 raise_exception(TT_DIV_ZERO
);
3063 if ((int32_t) x0
!= x0
) {
3065 return x0
< 0? 0x80000000: 0x7fffffff;
3072 void helper_stdf(target_ulong addr
, int mem_idx
)
3074 helper_check_align(addr
, 7);
3075 #if !defined(CONFIG_USER_ONLY)
3078 stfq_user(addr
, DT0
);
3081 stfq_kernel(addr
, DT0
);
3083 #ifdef TARGET_SPARC64
3085 stfq_hypv(addr
, DT0
);
3092 stfq_raw(address_mask(env
, addr
), DT0
);
3096 void helper_lddf(target_ulong addr
, int mem_idx
)
3098 helper_check_align(addr
, 7);
3099 #if !defined(CONFIG_USER_ONLY)
3102 DT0
= ldfq_user(addr
);
3105 DT0
= ldfq_kernel(addr
);
3107 #ifdef TARGET_SPARC64
3109 DT0
= ldfq_hypv(addr
);
3116 DT0
= ldfq_raw(address_mask(env
, addr
));
3120 void helper_ldqf(target_ulong addr
, int mem_idx
)
3122 // XXX add 128 bit load
3125 helper_check_align(addr
, 7);
3126 #if !defined(CONFIG_USER_ONLY)
3129 u
.ll
.upper
= ldq_user(addr
);
3130 u
.ll
.lower
= ldq_user(addr
+ 8);
3134 u
.ll
.upper
= ldq_kernel(addr
);
3135 u
.ll
.lower
= ldq_kernel(addr
+ 8);
3138 #ifdef TARGET_SPARC64
3140 u
.ll
.upper
= ldq_hypv(addr
);
3141 u
.ll
.lower
= ldq_hypv(addr
+ 8);
3149 u
.ll
.upper
= ldq_raw(address_mask(env
, addr
));
3150 u
.ll
.lower
= ldq_raw(address_mask(env
, addr
+ 8));
3155 void helper_stqf(target_ulong addr
, int mem_idx
)
3157 // XXX add 128 bit store
3160 helper_check_align(addr
, 7);
3161 #if !defined(CONFIG_USER_ONLY)
3165 stq_user(addr
, u
.ll
.upper
);
3166 stq_user(addr
+ 8, u
.ll
.lower
);
3170 stq_kernel(addr
, u
.ll
.upper
);
3171 stq_kernel(addr
+ 8, u
.ll
.lower
);
3173 #ifdef TARGET_SPARC64
3176 stq_hypv(addr
, u
.ll
.upper
);
3177 stq_hypv(addr
+ 8, u
.ll
.lower
);
3185 stq_raw(address_mask(env
, addr
), u
.ll
.upper
);
3186 stq_raw(address_mask(env
, addr
+ 8), u
.ll
.lower
);
3190 static inline void set_fsr(void)
3194 switch (env
->fsr
& FSR_RD_MASK
) {
3195 case FSR_RD_NEAREST
:
3196 rnd_mode
= float_round_nearest_even
;
3200 rnd_mode
= float_round_to_zero
;
3203 rnd_mode
= float_round_up
;
3206 rnd_mode
= float_round_down
;
3209 set_float_rounding_mode(rnd_mode
, &env
->fp_status
);
3212 void helper_ldfsr(uint32_t new_fsr
)
3214 env
->fsr
= (new_fsr
& FSR_LDFSR_MASK
) | (env
->fsr
& FSR_LDFSR_OLDMASK
);
3218 #ifdef TARGET_SPARC64
3219 void helper_ldxfsr(uint64_t new_fsr
)
3221 env
->fsr
= (new_fsr
& FSR_LDXFSR_MASK
) | (env
->fsr
& FSR_LDXFSR_OLDMASK
);
3226 void helper_debug(void)
3228 env
->exception_index
= EXCP_DEBUG
;
3232 #ifndef TARGET_SPARC64
3233 /* XXX: use another pointer for %iN registers to avoid slow wrapping
3235 void helper_save(void)
3239 cwp
= cpu_cwp_dec(env
, env
->cwp
- 1);
3240 if (env
->wim
& (1 << cwp
)) {
3241 raise_exception(TT_WIN_OVF
);
3246 void helper_restore(void)
3250 cwp
= cpu_cwp_inc(env
, env
->cwp
+ 1);
3251 if (env
->wim
& (1 << cwp
)) {
3252 raise_exception(TT_WIN_UNF
);
3257 void helper_wrpsr(target_ulong new_psr
)
3259 if ((new_psr
& PSR_CWP
) >= env
->nwindows
)
3260 raise_exception(TT_ILL_INSN
);
3262 PUT_PSR(env
, new_psr
);
3265 target_ulong
helper_rdpsr(void)
3267 return GET_PSR(env
);
3271 /* XXX: use another pointer for %iN registers to avoid slow wrapping
3273 void helper_save(void)
3277 cwp
= cpu_cwp_dec(env
, env
->cwp
- 1);
3278 if (env
->cansave
== 0) {
3279 raise_exception(TT_SPILL
| (env
->otherwin
!= 0 ?
3280 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3281 ((env
->wstate
& 0x7) << 2)));
3283 if (env
->cleanwin
- env
->canrestore
== 0) {
3284 // XXX Clean windows without trap
3285 raise_exception(TT_CLRWIN
);
3294 void helper_restore(void)
3298 cwp
= cpu_cwp_inc(env
, env
->cwp
+ 1);
3299 if (env
->canrestore
== 0) {
3300 raise_exception(TT_FILL
| (env
->otherwin
!= 0 ?
3301 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3302 ((env
->wstate
& 0x7) << 2)));
3310 void helper_flushw(void)
3312 if (env
->cansave
!= env
->nwindows
- 2) {
3313 raise_exception(TT_SPILL
| (env
->otherwin
!= 0 ?
3314 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3315 ((env
->wstate
& 0x7) << 2)));
3319 void helper_saved(void)
3322 if (env
->otherwin
== 0)
3328 void helper_restored(void)
3331 if (env
->cleanwin
< env
->nwindows
- 1)
3333 if (env
->otherwin
== 0)
3339 target_ulong
helper_rdccr(void)
3341 return GET_CCR(env
);
3344 void helper_wrccr(target_ulong new_ccr
)
3346 PUT_CCR(env
, new_ccr
);
3349 // CWP handling is reversed in V9, but we still use the V8 register
3351 target_ulong
helper_rdcwp(void)
3353 return GET_CWP64(env
);
3356 void helper_wrcwp(target_ulong new_cwp
)
3358 PUT_CWP64(env
, new_cwp
);
3361 // This function uses non-native bit order
3362 #define GET_FIELD(X, FROM, TO) \
3363 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
3365 // This function uses the order in the manuals, i.e. bit 0 is 2^0
3366 #define GET_FIELD_SP(X, FROM, TO) \
3367 GET_FIELD(X, 63 - (TO), 63 - (FROM))
3369 target_ulong
helper_array8(target_ulong pixel_addr
, target_ulong cubesize
)
3371 return (GET_FIELD_SP(pixel_addr
, 60, 63) << (17 + 2 * cubesize
)) |
3372 (GET_FIELD_SP(pixel_addr
, 39, 39 + cubesize
- 1) << (17 + cubesize
)) |
3373 (GET_FIELD_SP(pixel_addr
, 17 + cubesize
- 1, 17) << 17) |
3374 (GET_FIELD_SP(pixel_addr
, 56, 59) << 13) |
3375 (GET_FIELD_SP(pixel_addr
, 35, 38) << 9) |
3376 (GET_FIELD_SP(pixel_addr
, 13, 16) << 5) |
3377 (((pixel_addr
>> 55) & 1) << 4) |
3378 (GET_FIELD_SP(pixel_addr
, 33, 34) << 2) |
3379 GET_FIELD_SP(pixel_addr
, 11, 12);
3382 target_ulong
helper_alignaddr(target_ulong addr
, target_ulong offset
)
3386 tmp
= addr
+ offset
;
3388 env
->gsr
|= tmp
& 7ULL;
3392 target_ulong
helper_popc(target_ulong val
)
3394 return ctpop64(val
);
3397 static inline uint64_t *get_gregset(uint32_t pstate
)
3401 DPRINTF_PSTATE("ERROR in get_gregset: active pstate bits=%x%s%s%s\n",
3403 (pstate
& PS_IG
) ? " IG" : "",
3404 (pstate
& PS_MG
) ? " MG" : "",
3405 (pstate
& PS_AG
) ? " AG" : "");
3406 /* pass through to normal set of global registers */
3418 static inline void change_pstate(uint32_t new_pstate
)
3420 uint32_t pstate_regs
, new_pstate_regs
;
3421 uint64_t *src
, *dst
;
3423 if (env
->def
->features
& CPU_FEATURE_GL
) {
3424 // PS_AG is not implemented in this case
3425 new_pstate
&= ~PS_AG
;
3428 pstate_regs
= env
->pstate
& 0xc01;
3429 new_pstate_regs
= new_pstate
& 0xc01;
3431 if (new_pstate_regs
!= pstate_regs
) {
3432 DPRINTF_PSTATE("change_pstate: switching regs old=%x new=%x\n",
3433 pstate_regs
, new_pstate_regs
);
3434 // Switch global register bank
3435 src
= get_gregset(new_pstate_regs
);
3436 dst
= get_gregset(pstate_regs
);
3437 memcpy32(dst
, env
->gregs
);
3438 memcpy32(env
->gregs
, src
);
3441 DPRINTF_PSTATE("change_pstate: regs new=%x (unchanged)\n",
3444 env
->pstate
= new_pstate
;
3447 void helper_wrpstate(target_ulong new_state
)
3449 change_pstate(new_state
& 0xf3f);
3451 #if !defined(CONFIG_USER_ONLY)
3452 if (cpu_interrupts_enabled(env
)) {
3453 cpu_check_irqs(env
);
3458 void helper_wrpil(target_ulong new_pil
)
3460 #if !defined(CONFIG_USER_ONLY)
3461 DPRINTF_PSTATE("helper_wrpil old=%x new=%x\n",
3462 env
->psrpil
, (uint32_t)new_pil
);
3464 env
->psrpil
= new_pil
;
3466 if (cpu_interrupts_enabled(env
)) {
3467 cpu_check_irqs(env
);
3472 void helper_done(void)
3474 trap_state
* tsptr
= cpu_tsptr(env
);
3476 env
->pc
= tsptr
->tnpc
;
3477 env
->npc
= tsptr
->tnpc
+ 4;
3478 PUT_CCR(env
, tsptr
->tstate
>> 32);
3479 env
->asi
= (tsptr
->tstate
>> 24) & 0xff;
3480 change_pstate((tsptr
->tstate
>> 8) & 0xf3f);
3481 PUT_CWP64(env
, tsptr
->tstate
& 0xff);
3484 DPRINTF_PSTATE("... helper_done tl=%d\n", env
->tl
);
3486 #if !defined(CONFIG_USER_ONLY)
3487 if (cpu_interrupts_enabled(env
)) {
3488 cpu_check_irqs(env
);
3493 void helper_retry(void)
3495 trap_state
* tsptr
= cpu_tsptr(env
);
3497 env
->pc
= tsptr
->tpc
;
3498 env
->npc
= tsptr
->tnpc
;
3499 PUT_CCR(env
, tsptr
->tstate
>> 32);
3500 env
->asi
= (tsptr
->tstate
>> 24) & 0xff;
3501 change_pstate((tsptr
->tstate
>> 8) & 0xf3f);
3502 PUT_CWP64(env
, tsptr
->tstate
& 0xff);
3505 DPRINTF_PSTATE("... helper_retry tl=%d\n", env
->tl
);
3507 #if !defined(CONFIG_USER_ONLY)
3508 if (cpu_interrupts_enabled(env
)) {
3509 cpu_check_irqs(env
);
3514 static void do_modify_softint(const char* operation
, uint32_t value
)
3516 if (env
->softint
!= value
) {
3517 env
->softint
= value
;
3518 DPRINTF_PSTATE(": %s new %08x\n", operation
, env
->softint
);
3519 #if !defined(CONFIG_USER_ONLY)
3520 if (cpu_interrupts_enabled(env
)) {
3521 cpu_check_irqs(env
);
3527 void helper_set_softint(uint64_t value
)
3529 do_modify_softint("helper_set_softint", env
->softint
| (uint32_t)value
);
3532 void helper_clear_softint(uint64_t value
)
3534 do_modify_softint("helper_clear_softint", env
->softint
& (uint32_t)~value
);
3537 void helper_write_softint(uint64_t value
)
3539 do_modify_softint("helper_write_softint", (uint32_t)value
);
3543 void helper_flush(target_ulong addr
)
3546 tb_invalidate_page_range(addr
, addr
+ 8);
3549 #ifdef TARGET_SPARC64
3551 static const char * const excp_names
[0x80] = {
3552 [TT_TFAULT
] = "Instruction Access Fault",
3553 [TT_TMISS
] = "Instruction Access MMU Miss",
3554 [TT_CODE_ACCESS
] = "Instruction Access Error",
3555 [TT_ILL_INSN
] = "Illegal Instruction",
3556 [TT_PRIV_INSN
] = "Privileged Instruction",
3557 [TT_NFPU_INSN
] = "FPU Disabled",
3558 [TT_FP_EXCP
] = "FPU Exception",
3559 [TT_TOVF
] = "Tag Overflow",
3560 [TT_CLRWIN
] = "Clean Windows",
3561 [TT_DIV_ZERO
] = "Division By Zero",
3562 [TT_DFAULT
] = "Data Access Fault",
3563 [TT_DMISS
] = "Data Access MMU Miss",
3564 [TT_DATA_ACCESS
] = "Data Access Error",
3565 [TT_DPROT
] = "Data Protection Error",
3566 [TT_UNALIGNED
] = "Unaligned Memory Access",
3567 [TT_PRIV_ACT
] = "Privileged Action",
3568 [TT_EXTINT
| 0x1] = "External Interrupt 1",
3569 [TT_EXTINT
| 0x2] = "External Interrupt 2",
3570 [TT_EXTINT
| 0x3] = "External Interrupt 3",
3571 [TT_EXTINT
| 0x4] = "External Interrupt 4",
3572 [TT_EXTINT
| 0x5] = "External Interrupt 5",
3573 [TT_EXTINT
| 0x6] = "External Interrupt 6",
3574 [TT_EXTINT
| 0x7] = "External Interrupt 7",
3575 [TT_EXTINT
| 0x8] = "External Interrupt 8",
3576 [TT_EXTINT
| 0x9] = "External Interrupt 9",
3577 [TT_EXTINT
| 0xa] = "External Interrupt 10",
3578 [TT_EXTINT
| 0xb] = "External Interrupt 11",
3579 [TT_EXTINT
| 0xc] = "External Interrupt 12",
3580 [TT_EXTINT
| 0xd] = "External Interrupt 13",
3581 [TT_EXTINT
| 0xe] = "External Interrupt 14",
3582 [TT_EXTINT
| 0xf] = "External Interrupt 15",
3586 trap_state
* cpu_tsptr(CPUState
* env
)
3588 return &env
->ts
[env
->tl
& MAXTL_MASK
];
3591 void do_interrupt(CPUState
*env
)
3593 int intno
= env
->exception_index
;
3597 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
3601 if (intno
< 0 || intno
>= 0x180)
3603 else if (intno
>= 0x100)
3604 name
= "Trap Instruction";
3605 else if (intno
>= 0xc0)
3606 name
= "Window Fill";
3607 else if (intno
>= 0x80)
3608 name
= "Window Spill";
3610 name
= excp_names
[intno
];
3615 qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64
" npc=%016" PRIx64
3616 " SP=%016" PRIx64
"\n",
3619 env
->npc
, env
->regwptr
[6]);
3620 log_cpu_state(env
, 0);
3627 ptr
= (uint8_t *)env
->pc
;
3628 for(i
= 0; i
< 16; i
++) {
3629 qemu_log(" %02x", ldub(ptr
+ i
));
3637 #if !defined(CONFIG_USER_ONLY)
3638 if (env
->tl
>= env
->maxtl
) {
3639 cpu_abort(env
, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
3640 " Error state", env
->exception_index
, env
->tl
, env
->maxtl
);
3644 if (env
->tl
< env
->maxtl
- 1) {
3647 env
->pstate
|= PS_RED
;
3648 if (env
->tl
< env
->maxtl
)
3651 tsptr
= cpu_tsptr(env
);
3653 tsptr
->tstate
= ((uint64_t)GET_CCR(env
) << 32) |
3654 ((env
->asi
& 0xff) << 24) | ((env
->pstate
& 0xf3f) << 8) |
3656 tsptr
->tpc
= env
->pc
;
3657 tsptr
->tnpc
= env
->npc
;
3662 change_pstate(PS_PEF
| PS_PRIV
| PS_IG
);
3666 case TT_TMISS
... TT_TMISS
+ 3:
3667 case TT_DMISS
... TT_DMISS
+ 3:
3668 case TT_DPROT
... TT_DPROT
+ 3:
3669 change_pstate(PS_PEF
| PS_PRIV
| PS_MG
);
3672 change_pstate(PS_PEF
| PS_PRIV
| PS_AG
);
3676 if (intno
== TT_CLRWIN
)
3677 cpu_set_cwp(env
, cpu_cwp_dec(env
, env
->cwp
- 1));
3678 else if ((intno
& 0x1c0) == TT_SPILL
)
3679 cpu_set_cwp(env
, cpu_cwp_dec(env
, env
->cwp
- env
->cansave
- 2));
3680 else if ((intno
& 0x1c0) == TT_FILL
)
3681 cpu_set_cwp(env
, cpu_cwp_inc(env
, env
->cwp
+ 1));
3682 env
->tbr
&= ~0x7fffULL
;
3683 env
->tbr
|= ((env
->tl
> 1) ? 1 << 14 : 0) | (intno
<< 5);
3685 env
->npc
= env
->pc
+ 4;
3686 env
->exception_index
= -1;
3690 static const char * const excp_names
[0x80] = {
3691 [TT_TFAULT
] = "Instruction Access Fault",
3692 [TT_ILL_INSN
] = "Illegal Instruction",
3693 [TT_PRIV_INSN
] = "Privileged Instruction",
3694 [TT_NFPU_INSN
] = "FPU Disabled",
3695 [TT_WIN_OVF
] = "Window Overflow",
3696 [TT_WIN_UNF
] = "Window Underflow",
3697 [TT_UNALIGNED
] = "Unaligned Memory Access",
3698 [TT_FP_EXCP
] = "FPU Exception",
3699 [TT_DFAULT
] = "Data Access Fault",
3700 [TT_TOVF
] = "Tag Overflow",
3701 [TT_EXTINT
| 0x1] = "External Interrupt 1",
3702 [TT_EXTINT
| 0x2] = "External Interrupt 2",
3703 [TT_EXTINT
| 0x3] = "External Interrupt 3",
3704 [TT_EXTINT
| 0x4] = "External Interrupt 4",
3705 [TT_EXTINT
| 0x5] = "External Interrupt 5",
3706 [TT_EXTINT
| 0x6] = "External Interrupt 6",
3707 [TT_EXTINT
| 0x7] = "External Interrupt 7",
3708 [TT_EXTINT
| 0x8] = "External Interrupt 8",
3709 [TT_EXTINT
| 0x9] = "External Interrupt 9",
3710 [TT_EXTINT
| 0xa] = "External Interrupt 10",
3711 [TT_EXTINT
| 0xb] = "External Interrupt 11",
3712 [TT_EXTINT
| 0xc] = "External Interrupt 12",
3713 [TT_EXTINT
| 0xd] = "External Interrupt 13",
3714 [TT_EXTINT
| 0xe] = "External Interrupt 14",
3715 [TT_EXTINT
| 0xf] = "External Interrupt 15",
3716 [TT_TOVF
] = "Tag Overflow",
3717 [TT_CODE_ACCESS
] = "Instruction Access Error",
3718 [TT_DATA_ACCESS
] = "Data Access Error",
3719 [TT_DIV_ZERO
] = "Division By Zero",
3720 [TT_NCP_INSN
] = "Coprocessor Disabled",
3724 void do_interrupt(CPUState
*env
)
3726 int cwp
, intno
= env
->exception_index
;
3729 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
3733 if (intno
< 0 || intno
>= 0x100)
3735 else if (intno
>= 0x80)
3736 name
= "Trap Instruction";
3738 name
= excp_names
[intno
];
3743 qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
3746 env
->npc
, env
->regwptr
[6]);
3747 log_cpu_state(env
, 0);
3754 ptr
= (uint8_t *)env
->pc
;
3755 for(i
= 0; i
< 16; i
++) {
3756 qemu_log(" %02x", ldub(ptr
+ i
));
3764 #if !defined(CONFIG_USER_ONLY)
3765 if (env
->psret
== 0) {
3766 cpu_abort(env
, "Trap 0x%02x while interrupts disabled, Error state",
3767 env
->exception_index
);
3772 cwp
= cpu_cwp_dec(env
, env
->cwp
- 1);
3773 cpu_set_cwp(env
, cwp
);
3774 env
->regwptr
[9] = env
->pc
;
3775 env
->regwptr
[10] = env
->npc
;
3776 env
->psrps
= env
->psrs
;
3778 env
->tbr
= (env
->tbr
& TBR_BASE_MASK
) | (intno
<< 4);
3780 env
->npc
= env
->pc
+ 4;
3781 env
->exception_index
= -1;
3785 #if !defined(CONFIG_USER_ONLY)
3787 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
3790 #define MMUSUFFIX _mmu
3791 #define ALIGNED_ONLY
3794 #include "softmmu_template.h"
3797 #include "softmmu_template.h"
3800 #include "softmmu_template.h"
3803 #include "softmmu_template.h"
3805 /* XXX: make it generic ? */
3806 static void cpu_restore_state2(void *retaddr
)
3808 TranslationBlock
*tb
;
3812 /* now we have a real cpu fault */
3813 pc
= (unsigned long)retaddr
;
3814 tb
= tb_find_pc(pc
);
3816 /* the PC is inside the translated code. It means that we have
3817 a virtual CPU fault */
3818 cpu_restore_state(tb
, env
, pc
, (void *)(long)env
->cond
);
3823 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
3826 #ifdef DEBUG_UNALIGNED
3827 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
3828 "\n", addr
, env
->pc
);
3830 cpu_restore_state2(retaddr
);
3831 raise_exception(TT_UNALIGNED
);
3834 /* try to fill the TLB and return an exception if error. If retaddr is
3835 NULL, it means that the function was called in C code (i.e. not
3836 from generated code or from helper.c) */
3837 /* XXX: fix it to restore all registers */
3838 void tlb_fill(target_ulong addr
, int is_write
, int mmu_idx
, void *retaddr
)
3841 CPUState
*saved_env
;
3843 /* XXX: hack to restore env in all cases, even if not called from
3846 env
= cpu_single_env
;
3848 ret
= cpu_sparc_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
, 1);
3850 cpu_restore_state2(retaddr
);
3856 #endif /* !CONFIG_USER_ONLY */
3858 #ifndef TARGET_SPARC64
3859 #if !defined(CONFIG_USER_ONLY)
3860 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
3861 int is_asi
, int size
)
3863 CPUState
*saved_env
;
3866 /* XXX: hack to restore env in all cases, even if not called from
3869 env
= cpu_single_env
;
3870 #ifdef DEBUG_UNASSIGNED
3872 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
3873 " asi 0x%02x from " TARGET_FMT_lx
"\n",
3874 is_exec
? "exec" : is_write
? "write" : "read", size
,
3875 size
== 1 ? "" : "s", addr
, is_asi
, env
->pc
);
3877 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
3878 " from " TARGET_FMT_lx
"\n",
3879 is_exec
? "exec" : is_write
? "write" : "read", size
,
3880 size
== 1 ? "" : "s", addr
, env
->pc
);
3882 /* Don't overwrite translation and access faults */
3883 fault_type
= (env
->mmuregs
[3] & 0x1c) >> 2;
3884 if ((fault_type
> 4) || (fault_type
== 0)) {
3885 env
->mmuregs
[3] = 0; /* Fault status register */
3887 env
->mmuregs
[3] |= 1 << 16;
3889 env
->mmuregs
[3] |= 1 << 5;
3891 env
->mmuregs
[3] |= 1 << 6;
3893 env
->mmuregs
[3] |= 1 << 7;
3894 env
->mmuregs
[3] |= (5 << 2) | 2;
3895 /* SuperSPARC will never place instruction fault addresses in the FAR */
3897 env
->mmuregs
[4] = addr
; /* Fault address register */
3900 /* overflow (same type fault was not read before another fault) */
3901 if (fault_type
== ((env
->mmuregs
[3] & 0x1c)) >> 2) {
3902 env
->mmuregs
[3] |= 1;
3905 if ((env
->mmuregs
[0] & MMU_E
) && !(env
->mmuregs
[0] & MMU_NF
)) {
3907 raise_exception(TT_CODE_ACCESS
);
3909 raise_exception(TT_DATA_ACCESS
);
3912 /* flush neverland mappings created during no-fault mode,
3913 so the sequential MMU faults report proper fault types */
3914 if (env
->mmuregs
[0] & MMU_NF
) {
3922 #if defined(CONFIG_USER_ONLY)
3923 static void do_unassigned_access(target_ulong addr
, int is_write
, int is_exec
,
3924 int is_asi
, int size
)
3926 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
3927 int is_asi
, int size
)
3930 CPUState
*saved_env
;
3932 /* XXX: hack to restore env in all cases, even if not called from
3935 env
= cpu_single_env
;
3937 #ifdef DEBUG_UNASSIGNED
3938 printf("Unassigned mem access to " TARGET_FMT_plx
" from " TARGET_FMT_lx
3939 "\n", addr
, env
->pc
);
3943 raise_exception(TT_CODE_ACCESS
);
3945 raise_exception(TT_DATA_ACCESS
);
3952 #ifdef TARGET_SPARC64
3953 void helper_tick_set_count(void *opaque
, uint64_t count
)
3955 #if !defined(CONFIG_USER_ONLY)
3956 cpu_tick_set_count(opaque
, count
);
3960 uint64_t helper_tick_get_count(void *opaque
)
3962 #if !defined(CONFIG_USER_ONLY)
3963 return cpu_tick_get_count(opaque
);
3969 void helper_tick_set_limit(void *opaque
, uint64_t limit
)
3971 #if !defined(CONFIG_USER_ONLY)
3972 cpu_tick_set_limit(opaque
, limit
);