]>
git.proxmox.com Git - qemu.git/blob - target-sparc/op_helper.c
6 void raise_exception(int tt
)
8 env
->exception_index
= tt
;
12 #ifdef USE_INT_TO_FLOAT_HELPERS
15 FT0
= (float) *((int32_t *)&FT1
);
20 DT0
= (double) *((int32_t *)&FT1
);
26 FT0
= float32_abs(FT1
);
32 DT0
= float64_abs(DT1
);
38 FT0
= float32_sqrt(FT1
, &env
->fp_status
);
43 DT0
= float64_sqrt(DT1
, &env
->fp_status
);
49 env
->fsr
&= ~((FSR_FCC1
| FSR_FCC0
) << FS
);
50 if (isnan(FT0
) || isnan(FT1
)) {
51 T0
= (FSR_FCC1
| FSR_FCC0
) << FS
;
52 if (env
->fsr
& FSR_NVM
) {
54 raise_exception(TT_FP_EXCP
);
58 } else if (FT0
< FT1
) {
60 } else if (FT0
> FT1
) {
70 env
->fsr
&= ~((FSR_FCC1
| FSR_FCC0
) << FS
);
71 if (isnan(DT0
) || isnan(DT1
)) {
72 T0
= (FSR_FCC1
| FSR_FCC0
) << FS
;
73 if (env
->fsr
& FSR_NVM
) {
75 raise_exception(TT_FP_EXCP
);
79 } else if (DT0
< DT1
) {
81 } else if (DT0
> DT1
) {
92 void do_fcmps_fcc1 (void)
94 env
->fsr
&= ~((FSR_FCC1
| FSR_FCC0
) << FS
);
95 if (isnan(FT0
) || isnan(FT1
)) {
96 T0
= (FSR_FCC1
| FSR_FCC0
) << FS
;
97 if (env
->fsr
& FSR_NVM
) {
99 raise_exception(TT_FP_EXCP
);
103 } else if (FT0
< FT1
) {
105 } else if (FT0
> FT1
) {
113 void do_fcmpd_fcc1 (void)
115 env
->fsr
&= ~((FSR_FCC1
| FSR_FCC0
) << FS
);
116 if (isnan(DT0
) || isnan(DT1
)) {
117 T0
= (FSR_FCC1
| FSR_FCC0
) << FS
;
118 if (env
->fsr
& FSR_NVM
) {
120 raise_exception(TT_FP_EXCP
);
124 } else if (DT0
< DT1
) {
126 } else if (DT0
> DT1
) {
136 void do_fcmps_fcc2 (void)
138 env
->fsr
&= ~((FSR_FCC1
| FSR_FCC0
) << FS
);
139 if (isnan(FT0
) || isnan(FT1
)) {
140 T0
= (FSR_FCC1
| FSR_FCC0
) << FS
;
141 if (env
->fsr
& FSR_NVM
) {
143 raise_exception(TT_FP_EXCP
);
147 } else if (FT0
< FT1
) {
149 } else if (FT0
> FT1
) {
157 void do_fcmpd_fcc2 (void)
159 env
->fsr
&= ~((FSR_FCC1
| FSR_FCC0
) << FS
);
160 if (isnan(DT0
) || isnan(DT1
)) {
161 T0
= (FSR_FCC1
| FSR_FCC0
) << FS
;
162 if (env
->fsr
& FSR_NVM
) {
164 raise_exception(TT_FP_EXCP
);
168 } else if (DT0
< DT1
) {
170 } else if (DT0
> DT1
) {
180 void do_fcmps_fcc3 (void)
182 env
->fsr
&= ~((FSR_FCC1
| FSR_FCC0
) << FS
);
183 if (isnan(FT0
) || isnan(FT1
)) {
184 T0
= (FSR_FCC1
| FSR_FCC0
) << FS
;
185 if (env
->fsr
& FSR_NVM
) {
187 raise_exception(TT_FP_EXCP
);
191 } else if (FT0
< FT1
) {
193 } else if (FT0
> FT1
) {
201 void do_fcmpd_fcc3 (void)
203 env
->fsr
&= ~((FSR_FCC1
| FSR_FCC0
) << FS
);
204 if (isnan(DT0
) || isnan(DT1
)) {
205 T0
= (FSR_FCC1
| FSR_FCC0
) << FS
;
206 if (env
->fsr
& FSR_NVM
) {
208 raise_exception(TT_FP_EXCP
);
212 } else if (DT0
< DT1
) {
214 } else if (DT0
> DT1
) {
224 #if defined(CONFIG_USER_ONLY)
225 void helper_ld_asi(int asi
, int size
, int sign
)
229 void helper_st_asi(int asi
, int size
, int sign
)
233 #ifndef TARGET_SPARC64
234 void helper_ld_asi(int asi
, int size
, int sign
)
239 case 3: /* MMU probe */
243 mmulev
= (T0
>> 8) & 15;
247 ret
= mmu_probe(env
, T0
, mmulev
);
251 printf("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0
, mmulev
, ret
);
255 case 4: /* read MMU regs */
257 int reg
= (T0
>> 8) & 0xf;
259 ret
= env
->mmuregs
[reg
];
260 if (reg
== 3) /* Fault status cleared on read */
261 env
->mmuregs
[reg
] = 0;
263 printf("mmu_read: reg[%d] = 0x%08x\n", reg
, ret
);
267 case 0x20 ... 0x2f: /* MMU passthrough */
273 ret
= lduw_phys(T0
& ~1);
277 ret
= ldl_phys(T0
& ~3);
280 ret
= ldl_phys(T0
& ~3);
281 T0
= ldl_phys((T0
+ 4) & ~3);
292 void helper_st_asi(int asi
, int size
, int sign
)
295 case 3: /* MMU flush */
299 mmulev
= (T0
>> 8) & 15;
301 printf("mmu flush level %d\n", mmulev
);
304 case 0: // flush page
305 tlb_flush_page(env
, T0
& 0xfffff000);
307 case 1: // flush segment (256k)
308 case 2: // flush region (16M)
309 case 3: // flush context (4G)
310 case 4: // flush entire
321 case 4: /* write MMU regs */
323 int reg
= (T0
>> 8) & 0xf;
326 oldreg
= env
->mmuregs
[reg
];
329 env
->mmuregs
[reg
] &= ~(MMU_E
| MMU_NF
);
330 env
->mmuregs
[reg
] |= T1
& (MMU_E
| MMU_NF
);
331 // Mappings generated during no-fault mode or MMU
332 // disabled mode are invalid in normal mode
333 if (oldreg
!= env
->mmuregs
[reg
])
337 env
->mmuregs
[reg
] = T1
;
338 if (oldreg
!= env
->mmuregs
[reg
]) {
339 /* we flush when the MMU context changes because
340 QEMU has no MMU context support */
348 env
->mmuregs
[reg
] = T1
;
352 if (oldreg
!= env
->mmuregs
[reg
]) {
353 printf("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg
, oldreg
, env
->mmuregs
[reg
]);
359 case 0x17: /* Block copy, sta access */
362 // address (T0) = dst
364 uint32_t src
= T1
, dst
= T0
;
369 cpu_physical_memory_read(src
, (void *) &temp
, 32);
370 cpu_physical_memory_write(dst
, (void *) &temp
, 32);
373 case 0x1f: /* Block fill, stda access */
376 // address (T0) = dst
382 val
= (((uint64_t)T1
) << 32) | T2
;
385 for (i
= 0; i
< 32; i
+= 8, dst
+= 8) {
386 cpu_physical_memory_write(dst
, (void *) &val
, 8);
390 case 0x20 ... 0x2f: /* MMU passthrough */
397 stw_phys(T0
& ~1, T1
);
401 stl_phys(T0
& ~3, T1
);
404 stl_phys(T0
& ~3, T1
);
405 stl_phys((T0
+ 4) & ~3, T2
);
417 void helper_ld_asi(int asi
, int size
, int sign
)
421 if (asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
422 raise_exception(TT_PRIV_ACT
);
426 case 0x15: // Bypass, non-cacheable
433 ret
= lduw_phys(T0
& ~1);
436 ret
= ldl_phys(T0
& ~3);
440 ret
= ldq_phys(T0
& ~7);
445 case 0x04: // Nucleus
446 case 0x0c: // Nucleus Little Endian (LE)
447 case 0x10: // As if user primary
448 case 0x11: // As if user secondary
449 case 0x18: // As if user primary LE
450 case 0x19: // As if user secondary LE
451 case 0x1c: // Bypass LE
452 case 0x1d: // Bypass, non-cacheable LE
453 case 0x24: // Nucleus quad LDD 128 bit atomic
454 case 0x2c: // Nucleus quad LDD 128 bit atomic
455 case 0x4a: // UPA config
456 case 0x82: // Primary no-fault
457 case 0x83: // Secondary no-fault
458 case 0x88: // Primary LE
459 case 0x89: // Secondary LE
460 case 0x8a: // Primary no-fault LE
461 case 0x8b: // Secondary no-fault LE
467 case 0x50: // I-MMU regs
469 int reg
= (T0
>> 3) & 0xf;
471 ret
= env
->immuregs
[reg
];
474 case 0x51: // I-MMU 8k TSB pointer
475 case 0x52: // I-MMU 64k TSB pointer
476 case 0x55: // I-MMU data access
479 case 0x56: // I-MMU tag read
483 for (i
= 0; i
< 64; i
++) {
484 // Valid, ctx match, vaddr match
485 if ((env
->itlb_tte
[i
] & 0x8000000000000000ULL
) != 0 &&
486 env
->itlb_tag
[i
] == T0
) {
487 ret
= env
->itlb_tag
[i
];
493 case 0x58: // D-MMU regs
495 int reg
= (T0
>> 3) & 0xf;
497 ret
= env
->dmmuregs
[reg
];
500 case 0x5e: // D-MMU tag read
504 for (i
= 0; i
< 64; i
++) {
505 // Valid, ctx match, vaddr match
506 if ((env
->dtlb_tte
[i
] & 0x8000000000000000ULL
) != 0 &&
507 env
->dtlb_tag
[i
] == T0
) {
508 ret
= env
->dtlb_tag
[i
];
514 case 0x59: // D-MMU 8k TSB pointer
515 case 0x5a: // D-MMU 64k TSB pointer
516 case 0x5b: // D-MMU data pointer
517 case 0x5d: // D-MMU data access
518 case 0x48: // Interrupt dispatch, RO
519 case 0x49: // Interrupt data receive
520 case 0x7f: // Incoming interrupt vector, RO
523 case 0x54: // I-MMU data in, WO
524 case 0x57: // I-MMU demap, WO
525 case 0x5c: // D-MMU data in, WO
526 case 0x5f: // D-MMU demap, WO
527 case 0x77: // Interrupt vector, WO
535 void helper_st_asi(int asi
, int size
, int sign
)
537 if (asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
538 raise_exception(TT_PRIV_ACT
);
542 case 0x15: // Bypass, non-cacheable
549 stw_phys(T0
& ~1, T1
);
552 stl_phys(T0
& ~3, T1
);
556 stq_phys(T0
& ~7, T1
);
561 case 0x04: // Nucleus
562 case 0x0c: // Nucleus Little Endian (LE)
563 case 0x10: // As if user primary
564 case 0x11: // As if user secondary
565 case 0x18: // As if user primary LE
566 case 0x19: // As if user secondary LE
567 case 0x1c: // Bypass LE
568 case 0x1d: // Bypass, non-cacheable LE
569 case 0x24: // Nucleus quad LDD 128 bit atomic
570 case 0x2c: // Nucleus quad LDD 128 bit atomic
571 case 0x4a: // UPA config
572 case 0x88: // Primary LE
573 case 0x89: // Secondary LE
581 env
->lsu
= T1
& (DMMU_E
| IMMU_E
);
582 // Mappings generated during D/I MMU disabled mode are
583 // invalid in normal mode
584 if (oldreg
!= env
->lsu
) {
586 printf("LSU change: 0x%llx -> 0x%llx\n", oldreg
, env
->lsu
);
593 case 0x50: // I-MMU regs
595 int reg
= (T0
>> 3) & 0xf;
598 oldreg
= env
->immuregs
[reg
];
603 case 1: // Not in I-MMU
610 T1
= 0; // Clear SFSR
612 case 5: // TSB access
613 case 6: // Tag access
617 env
->immuregs
[reg
] = T1
;
619 if (oldreg
!= env
->immuregs
[reg
]) {
620 printf("mmu change reg[%d]: 0x%08llx -> 0x%08llx\n", reg
, oldreg
, env
->immuregs
[reg
]);
626 case 0x54: // I-MMU data in
630 // Try finding an invalid entry
631 for (i
= 0; i
< 64; i
++) {
632 if ((env
->itlb_tte
[i
] & 0x8000000000000000ULL
) == 0) {
633 env
->itlb_tag
[i
] = env
->immuregs
[6];
634 env
->itlb_tte
[i
] = T1
;
638 // Try finding an unlocked entry
639 for (i
= 0; i
< 64; i
++) {
640 if ((env
->itlb_tte
[i
] & 0x40) == 0) {
641 env
->itlb_tag
[i
] = env
->immuregs
[6];
642 env
->itlb_tte
[i
] = T1
;
649 case 0x55: // I-MMU data access
651 unsigned int i
= (T0
>> 3) & 0x3f;
653 env
->itlb_tag
[i
] = env
->immuregs
[6];
654 env
->itlb_tte
[i
] = T1
;
657 case 0x57: // I-MMU demap
660 case 0x58: // D-MMU regs
662 int reg
= (T0
>> 3) & 0xf;
665 oldreg
= env
->dmmuregs
[reg
];
672 T1
= 0; // Clear SFSR, Fault address
673 env
->dmmuregs
[4] = 0;
675 env
->dmmuregs
[reg
] = T1
;
677 case 1: // Primary context
678 case 2: // Secondary context
679 case 5: // TSB access
680 case 6: // Tag access
681 case 7: // Virtual Watchpoint
682 case 8: // Physical Watchpoint
686 env
->dmmuregs
[reg
] = T1
;
688 if (oldreg
!= env
->dmmuregs
[reg
]) {
689 printf("mmu change reg[%d]: 0x%08llx -> 0x%08llx\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
695 case 0x5c: // D-MMU data in
699 // Try finding an invalid entry
700 for (i
= 0; i
< 64; i
++) {
701 if ((env
->dtlb_tte
[i
] & 0x8000000000000000ULL
) == 0) {
702 env
->dtlb_tag
[i
] = env
->dmmuregs
[6];
703 env
->dtlb_tte
[i
] = T1
;
707 // Try finding an unlocked entry
708 for (i
= 0; i
< 64; i
++) {
709 if ((env
->dtlb_tte
[i
] & 0x40) == 0) {
710 env
->dtlb_tag
[i
] = env
->dmmuregs
[6];
711 env
->dtlb_tte
[i
] = T1
;
718 case 0x5d: // D-MMU data access
720 unsigned int i
= (T0
>> 3) & 0x3f;
722 env
->dtlb_tag
[i
] = env
->dmmuregs
[6];
723 env
->dtlb_tte
[i
] = T1
;
726 case 0x5f: // D-MMU demap
727 case 0x49: // Interrupt data receive
730 case 0x51: // I-MMU 8k TSB pointer, RO
731 case 0x52: // I-MMU 64k TSB pointer, RO
732 case 0x56: // I-MMU tag read, RO
733 case 0x59: // D-MMU 8k TSB pointer, RO
734 case 0x5a: // D-MMU 64k TSB pointer, RO
735 case 0x5b: // D-MMU data pointer, RO
736 case 0x5e: // D-MMU tag read, RO
737 case 0x48: // Interrupt dispatch, RO
738 case 0x7f: // Incoming interrupt vector, RO
739 case 0x82: // Primary no-fault, RO
740 case 0x83: // Secondary no-fault, RO
741 case 0x8a: // Primary no-fault LE, RO
742 case 0x8b: // Secondary no-fault LE, RO
748 #endif /* !CONFIG_USER_ONLY */
750 #ifndef TARGET_SPARC64
756 cwp
= (env
->cwp
+ 1) & (NWINDOWS
- 1);
757 if (env
->wim
& (1 << cwp
)) {
758 raise_exception(TT_WIN_UNF
);
761 env
->psrs
= env
->psrps
;
765 void helper_ldfsr(void)
768 switch (env
->fsr
& FSR_RD_MASK
) {
770 rnd_mode
= float_round_nearest_even
;
774 rnd_mode
= float_round_to_zero
;
777 rnd_mode
= float_round_up
;
780 rnd_mode
= float_round_down
;
783 set_float_rounding_mode(rnd_mode
, &env
->fp_status
);
786 void cpu_get_fp64(uint64_t *pmant
, uint16_t *pexp
, double f
)
790 *pmant
= ldexp(frexp(f
, &exptemp
), 53);
794 double cpu_put_fp64(uint64_t mant
, uint16_t exp
)
796 return ldexp((double) mant
, exp
- 53);
801 env
->exception_index
= EXCP_DEBUG
;
805 #ifndef TARGET_SPARC64
820 T0
= (T1
& 0x5555555555555555ULL
) + ((T1
>> 1) & 0x5555555555555555ULL
);
821 T0
= (T0
& 0x3333333333333333ULL
) + ((T0
>> 2) & 0x3333333333333333ULL
);
822 T0
= (T0
& 0x0f0f0f0f0f0f0f0fULL
) + ((T0
>> 4) & 0x0f0f0f0f0f0f0f0fULL
);
823 T0
= (T0
& 0x00ff00ff00ff00ffULL
) + ((T0
>> 8) & 0x00ff00ff00ff00ffULL
);
824 T0
= (T0
& 0x0000ffff0000ffffULL
) + ((T0
>> 16) & 0x0000ffff0000ffffULL
);
825 T0
= (T0
& 0x00000000ffffffffULL
) + ((T0
>> 32) & 0x00000000ffffffffULL
);
828 static inline uint64_t *get_gregset(uint64_t pstate
)
845 uint64_t new_pstate
, pstate_regs
, new_pstate_regs
;
848 new_pstate
= T0
& 0xf3f;
849 pstate_regs
= env
->pstate
& 0xc01;
850 new_pstate_regs
= new_pstate
& 0xc01;
851 if (new_pstate_regs
!= pstate_regs
) {
852 // Switch global register bank
853 src
= get_gregset(new_pstate_regs
);
854 dst
= get_gregset(pstate_regs
);
855 memcpy32(dst
, env
->gregs
);
856 memcpy32(env
->gregs
, src
);
858 env
->pstate
= new_pstate
;
864 env
->pc
= env
->tnpc
[env
->tl
];
865 env
->npc
= env
->tnpc
[env
->tl
] + 4;
866 PUT_CCR(env
, env
->tstate
[env
->tl
] >> 32);
867 env
->asi
= (env
->tstate
[env
->tl
] >> 24) & 0xff;
868 env
->pstate
= (env
->tstate
[env
->tl
] >> 8) & 0xfff;
869 set_cwp(env
->tstate
[env
->tl
] & 0xff);
875 env
->pc
= env
->tpc
[env
->tl
];
876 env
->npc
= env
->tnpc
[env
->tl
];
877 PUT_CCR(env
, env
->tstate
[env
->tl
] >> 32);
878 env
->asi
= (env
->tstate
[env
->tl
] >> 24) & 0xff;
879 env
->pstate
= (env
->tstate
[env
->tl
] >> 8) & 0xfff;
880 set_cwp(env
->tstate
[env
->tl
] & 0xff);
884 void set_cwp(int new_cwp
)
886 /* put the modified wrap registers at their proper location */
887 if (env
->cwp
== (NWINDOWS
- 1))
888 memcpy32(env
->regbase
, env
->regbase
+ NWINDOWS
* 16);
890 /* put the wrap registers at their temporary location */
891 if (new_cwp
== (NWINDOWS
- 1))
892 memcpy32(env
->regbase
+ NWINDOWS
* 16, env
->regbase
);
893 env
->regwptr
= env
->regbase
+ (new_cwp
* 16);
894 REGWPTR
= env
->regwptr
;
897 void cpu_set_cwp(CPUState
*env1
, int new_cwp
)
901 target_ulong
*saved_regwptr
;
906 saved_regwptr
= REGWPTR
;
912 REGWPTR
= saved_regwptr
;
916 #ifdef TARGET_SPARC64
917 void do_interrupt(int intno
)
920 if (loglevel
& CPU_LOG_INT
) {
922 fprintf(logfile
, "%6d: v=%04x pc=%016llx npc=%016llx SP=%016llx\n",
925 env
->npc
, env
->regwptr
[6]);
926 cpu_dump_state(env
, logfile
, fprintf
, 0);
932 fprintf(logfile
, " code=");
933 ptr
= (uint8_t *)env
->pc
;
934 for(i
= 0; i
< 16; i
++) {
935 fprintf(logfile
, " %02x", ldub(ptr
+ i
));
937 fprintf(logfile
, "\n");
943 #if !defined(CONFIG_USER_ONLY)
944 if (env
->tl
== MAXTL
) {
945 cpu_abort(cpu_single_env
, "Trap 0x%04x while trap level is MAXTL, Error state", env
->exception_index
);
949 env
->tstate
[env
->tl
] = ((uint64_t)GET_CCR(env
) << 32) | ((env
->asi
& 0xff) << 24) |
950 ((env
->pstate
& 0xfff) << 8) | (env
->cwp
& 0xff);
951 env
->tpc
[env
->tl
] = env
->pc
;
952 env
->tnpc
[env
->tl
] = env
->npc
;
953 env
->tt
[env
->tl
] = intno
;
954 env
->pstate
= PS_PEF
| PS_PRIV
| PS_AG
;
955 env
->tbr
&= ~0x7fffULL
;
956 env
->tbr
|= ((env
->tl
> 1) ? 1 << 14 : 0) | (intno
<< 5);
957 if (env
->tl
< MAXTL
- 1) {
960 env
->pstate
|= PS_RED
;
961 if (env
->tl
!= MAXTL
)
965 env
->npc
= env
->pc
+ 4;
966 env
->exception_index
= 0;
969 void do_interrupt(int intno
)
974 if (loglevel
& CPU_LOG_INT
) {
976 fprintf(logfile
, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
979 env
->npc
, env
->regwptr
[6]);
980 cpu_dump_state(env
, logfile
, fprintf
, 0);
986 fprintf(logfile
, " code=");
987 ptr
= (uint8_t *)env
->pc
;
988 for(i
= 0; i
< 16; i
++) {
989 fprintf(logfile
, " %02x", ldub(ptr
+ i
));
991 fprintf(logfile
, "\n");
997 #if !defined(CONFIG_USER_ONLY)
998 if (env
->psret
== 0) {
999 cpu_abort(cpu_single_env
, "Trap 0x%02x while interrupts disabled, Error state", env
->exception_index
);
1004 cwp
= (env
->cwp
- 1) & (NWINDOWS
- 1);
1006 env
->regwptr
[9] = env
->pc
;
1007 env
->regwptr
[10] = env
->npc
;
1008 env
->psrps
= env
->psrs
;
1010 env
->tbr
= (env
->tbr
& TBR_BASE_MASK
) | (intno
<< 4);
1012 env
->npc
= env
->pc
+ 4;
1013 env
->exception_index
= 0;
1017 #if !defined(CONFIG_USER_ONLY)
1019 #define MMUSUFFIX _mmu
1020 #define GETPC() (__builtin_return_address(0))
1023 #include "softmmu_template.h"
1026 #include "softmmu_template.h"
1029 #include "softmmu_template.h"
1032 #include "softmmu_template.h"
1035 /* try to fill the TLB and return an exception if error. If retaddr is
1036 NULL, it means that the function was called in C code (i.e. not
1037 from generated code or from helper.c) */
1038 /* XXX: fix it to restore all registers */
1039 void tlb_fill(target_ulong addr
, int is_write
, int is_user
, void *retaddr
)
1041 TranslationBlock
*tb
;
1044 CPUState
*saved_env
;
1046 /* XXX: hack to restore env in all cases, even if not called from
1049 env
= cpu_single_env
;
1051 ret
= cpu_sparc_handle_mmu_fault(env
, addr
, is_write
, is_user
, 1);
1054 /* now we have a real cpu fault */
1055 pc
= (unsigned long)retaddr
;
1056 tb
= tb_find_pc(pc
);
1058 /* the PC is inside the translated code. It means that we have
1059 a virtual CPU fault */
1060 cpu_restore_state(tb
, env
, pc
, (void *)T2
);