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Convert other float and VIS ops to TCG
[qemu.git] / target-sparc / op_helper.c
1 #include "exec.h"
2 #include "host-utils.h"
3 #include "helper.h"
4
5 //#define DEBUG_PCALL
6 //#define DEBUG_MMU
7 //#define DEBUG_MXCC
8 //#define DEBUG_UNALIGNED
9 //#define DEBUG_UNASSIGNED
10 //#define DEBUG_ASI
11
12 #ifdef DEBUG_MMU
13 #define DPRINTF_MMU(fmt, args...) \
14 do { printf("MMU: " fmt , ##args); } while (0)
15 #else
16 #define DPRINTF_MMU(fmt, args...)
17 #endif
18
19 #ifdef DEBUG_MXCC
20 #define DPRINTF_MXCC(fmt, args...) \
21 do { printf("MXCC: " fmt , ##args); } while (0)
22 #else
23 #define DPRINTF_MXCC(fmt, args...)
24 #endif
25
26 #ifdef DEBUG_ASI
27 #define DPRINTF_ASI(fmt, args...) \
28 do { printf("ASI: " fmt , ##args); } while (0)
29 #else
30 #define DPRINTF_ASI(fmt, args...)
31 #endif
32
33 void raise_exception(int tt)
34 {
35 env->exception_index = tt;
36 cpu_loop_exit();
37 }
38
39 void helper_trap(target_ulong nb_trap)
40 {
41 env->exception_index = TT_TRAP + (nb_trap & 0x7f);
42 cpu_loop_exit();
43 }
44
45 void helper_trapcc(target_ulong nb_trap, target_ulong do_trap)
46 {
47 if (do_trap) {
48 env->exception_index = TT_TRAP + (nb_trap & 0x7f);
49 cpu_loop_exit();
50 }
51 }
52
53 #define F_HELPER(name, p) void helper_f##name##p(void)
54
55 #if defined(CONFIG_USER_ONLY)
56 #define F_BINOP(name) \
57 F_HELPER(name, s) \
58 { \
59 FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \
60 } \
61 F_HELPER(name, d) \
62 { \
63 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
64 } \
65 F_HELPER(name, q) \
66 { \
67 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
68 }
69 #else
70 #define F_BINOP(name) \
71 F_HELPER(name, s) \
72 { \
73 FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \
74 } \
75 F_HELPER(name, d) \
76 { \
77 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
78 }
79 #endif
80
81 F_BINOP(add);
82 F_BINOP(sub);
83 F_BINOP(mul);
84 F_BINOP(div);
85 #undef F_BINOP
86
87 void helper_fsmuld(void)
88 {
89 DT0 = float64_mul(float32_to_float64(FT0, &env->fp_status),
90 float32_to_float64(FT1, &env->fp_status),
91 &env->fp_status);
92 }
93
94 #if defined(CONFIG_USER_ONLY)
95 void helper_fdmulq(void)
96 {
97 QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
98 float64_to_float128(DT1, &env->fp_status),
99 &env->fp_status);
100 }
101 #endif
102
103 F_HELPER(neg, s)
104 {
105 FT0 = float32_chs(FT1);
106 }
107
108 #ifdef TARGET_SPARC64
109 F_HELPER(neg, d)
110 {
111 DT0 = float64_chs(DT1);
112 }
113
114 #if defined(CONFIG_USER_ONLY)
115 F_HELPER(neg, q)
116 {
117 QT0 = float128_chs(QT1);
118 }
119 #endif
120 #endif
121
122 /* Integer to float conversion. */
123 F_HELPER(ito, s)
124 {
125 FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
126 }
127
128 F_HELPER(ito, d)
129 {
130 DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
131 }
132
133 #if defined(CONFIG_USER_ONLY)
134 F_HELPER(ito, q)
135 {
136 QT0 = int32_to_float128(*((int32_t *)&FT1), &env->fp_status);
137 }
138 #endif
139
140 #ifdef TARGET_SPARC64
141 F_HELPER(xto, s)
142 {
143 FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
144 }
145
146 F_HELPER(xto, d)
147 {
148 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
149 }
150 #if defined(CONFIG_USER_ONLY)
151 F_HELPER(xto, q)
152 {
153 QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
154 }
155 #endif
156 #endif
157 #undef F_HELPER
158
159 /* floating point conversion */
160 void helper_fdtos(void)
161 {
162 FT0 = float64_to_float32(DT1, &env->fp_status);
163 }
164
165 void helper_fstod(void)
166 {
167 DT0 = float32_to_float64(FT1, &env->fp_status);
168 }
169
170 #if defined(CONFIG_USER_ONLY)
171 void helper_fqtos(void)
172 {
173 FT0 = float128_to_float32(QT1, &env->fp_status);
174 }
175
176 void helper_fstoq(void)
177 {
178 QT0 = float32_to_float128(FT1, &env->fp_status);
179 }
180
181 void helper_fqtod(void)
182 {
183 DT0 = float128_to_float64(QT1, &env->fp_status);
184 }
185
186 void helper_fdtoq(void)
187 {
188 QT0 = float64_to_float128(DT1, &env->fp_status);
189 }
190 #endif
191
192 /* Float to integer conversion. */
193 void helper_fstoi(void)
194 {
195 *((int32_t *)&FT0) = float32_to_int32_round_to_zero(FT1, &env->fp_status);
196 }
197
198 void helper_fdtoi(void)
199 {
200 *((int32_t *)&FT0) = float64_to_int32_round_to_zero(DT1, &env->fp_status);
201 }
202
203 #if defined(CONFIG_USER_ONLY)
204 void helper_fqtoi(void)
205 {
206 *((int32_t *)&FT0) = float128_to_int32_round_to_zero(QT1, &env->fp_status);
207 }
208 #endif
209
210 #ifdef TARGET_SPARC64
211 void helper_fstox(void)
212 {
213 *((int64_t *)&DT0) = float32_to_int64_round_to_zero(FT1, &env->fp_status);
214 }
215
216 void helper_fdtox(void)
217 {
218 *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
219 }
220
221 #if defined(CONFIG_USER_ONLY)
222 void helper_fqtox(void)
223 {
224 *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
225 }
226 #endif
227
228 void helper_faligndata(void)
229 {
230 uint64_t tmp;
231
232 tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
233 tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
234 *((uint64_t *)&DT0) = tmp;
235 }
236
237 void helper_movl_FT0_0(void)
238 {
239 *((uint32_t *)&FT0) = 0;
240 }
241
242 void helper_movl_DT0_0(void)
243 {
244 *((uint64_t *)&DT0) = 0;
245 }
246
247 void helper_movl_FT0_1(void)
248 {
249 *((uint32_t *)&FT0) = 0xffffffff;
250 }
251
252 void helper_movl_DT0_1(void)
253 {
254 *((uint64_t *)&DT0) = 0xffffffffffffffffULL;
255 }
256
257 void helper_fnot(void)
258 {
259 *(uint64_t *)&DT0 = ~*(uint64_t *)&DT1;
260 }
261
262 void helper_fnots(void)
263 {
264 *(uint32_t *)&FT0 = ~*(uint32_t *)&FT1;
265 }
266
267 void helper_fnor(void)
268 {
269 *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 | *(uint64_t *)&DT1);
270 }
271
272 void helper_fnors(void)
273 {
274 *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 | *(uint32_t *)&FT1);
275 }
276
277 void helper_for(void)
278 {
279 *(uint64_t *)&DT0 |= *(uint64_t *)&DT1;
280 }
281
282 void helper_fors(void)
283 {
284 *(uint32_t *)&FT0 |= *(uint32_t *)&FT1;
285 }
286
287 void helper_fxor(void)
288 {
289 *(uint64_t *)&DT0 ^= *(uint64_t *)&DT1;
290 }
291
292 void helper_fxors(void)
293 {
294 *(uint32_t *)&FT0 ^= *(uint32_t *)&FT1;
295 }
296
297 void helper_fand(void)
298 {
299 *(uint64_t *)&DT0 &= *(uint64_t *)&DT1;
300 }
301
302 void helper_fands(void)
303 {
304 *(uint32_t *)&FT0 &= *(uint32_t *)&FT1;
305 }
306
307 void helper_fornot(void)
308 {
309 *(uint64_t *)&DT0 = *(uint64_t *)&DT0 | ~*(uint64_t *)&DT1;
310 }
311
312 void helper_fornots(void)
313 {
314 *(uint32_t *)&FT0 = *(uint32_t *)&FT0 | ~*(uint32_t *)&FT1;
315 }
316
317 void helper_fandnot(void)
318 {
319 *(uint64_t *)&DT0 = *(uint64_t *)&DT0 & ~*(uint64_t *)&DT1;
320 }
321
322 void helper_fandnots(void)
323 {
324 *(uint32_t *)&FT0 = *(uint32_t *)&FT0 & ~*(uint32_t *)&FT1;
325 }
326
327 void helper_fnand(void)
328 {
329 *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 & *(uint64_t *)&DT1);
330 }
331
332 void helper_fnands(void)
333 {
334 *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 & *(uint32_t *)&FT1);
335 }
336
337 void helper_fxnor(void)
338 {
339 *(uint64_t *)&DT0 ^= ~*(uint64_t *)&DT1;
340 }
341
342 void helper_fxnors(void)
343 {
344 *(uint32_t *)&FT0 ^= ~*(uint32_t *)&FT1;
345 }
346
347 #ifdef WORDS_BIGENDIAN
348 #define VIS_B64(n) b[7 - (n)]
349 #define VIS_W64(n) w[3 - (n)]
350 #define VIS_SW64(n) sw[3 - (n)]
351 #define VIS_L64(n) l[1 - (n)]
352 #define VIS_B32(n) b[3 - (n)]
353 #define VIS_W32(n) w[1 - (n)]
354 #else
355 #define VIS_B64(n) b[n]
356 #define VIS_W64(n) w[n]
357 #define VIS_SW64(n) sw[n]
358 #define VIS_L64(n) l[n]
359 #define VIS_B32(n) b[n]
360 #define VIS_W32(n) w[n]
361 #endif
362
363 typedef union {
364 uint8_t b[8];
365 uint16_t w[4];
366 int16_t sw[4];
367 uint32_t l[2];
368 float64 d;
369 } vis64;
370
371 typedef union {
372 uint8_t b[4];
373 uint16_t w[2];
374 uint32_t l;
375 float32 f;
376 } vis32;
377
378 void helper_fpmerge(void)
379 {
380 vis64 s, d;
381
382 s.d = DT0;
383 d.d = DT1;
384
385 // Reverse calculation order to handle overlap
386 d.VIS_B64(7) = s.VIS_B64(3);
387 d.VIS_B64(6) = d.VIS_B64(3);
388 d.VIS_B64(5) = s.VIS_B64(2);
389 d.VIS_B64(4) = d.VIS_B64(2);
390 d.VIS_B64(3) = s.VIS_B64(1);
391 d.VIS_B64(2) = d.VIS_B64(1);
392 d.VIS_B64(1) = s.VIS_B64(0);
393 //d.VIS_B64(0) = d.VIS_B64(0);
394
395 DT0 = d.d;
396 }
397
398 void helper_fmul8x16(void)
399 {
400 vis64 s, d;
401 uint32_t tmp;
402
403 s.d = DT0;
404 d.d = DT1;
405
406 #define PMUL(r) \
407 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
408 if ((tmp & 0xff) > 0x7f) \
409 tmp += 0x100; \
410 d.VIS_W64(r) = tmp >> 8;
411
412 PMUL(0);
413 PMUL(1);
414 PMUL(2);
415 PMUL(3);
416 #undef PMUL
417
418 DT0 = d.d;
419 }
420
421 void helper_fmul8x16al(void)
422 {
423 vis64 s, d;
424 uint32_t tmp;
425
426 s.d = DT0;
427 d.d = DT1;
428
429 #define PMUL(r) \
430 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
431 if ((tmp & 0xff) > 0x7f) \
432 tmp += 0x100; \
433 d.VIS_W64(r) = tmp >> 8;
434
435 PMUL(0);
436 PMUL(1);
437 PMUL(2);
438 PMUL(3);
439 #undef PMUL
440
441 DT0 = d.d;
442 }
443
444 void helper_fmul8x16au(void)
445 {
446 vis64 s, d;
447 uint32_t tmp;
448
449 s.d = DT0;
450 d.d = DT1;
451
452 #define PMUL(r) \
453 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
454 if ((tmp & 0xff) > 0x7f) \
455 tmp += 0x100; \
456 d.VIS_W64(r) = tmp >> 8;
457
458 PMUL(0);
459 PMUL(1);
460 PMUL(2);
461 PMUL(3);
462 #undef PMUL
463
464 DT0 = d.d;
465 }
466
467 void helper_fmul8sux16(void)
468 {
469 vis64 s, d;
470 uint32_t tmp;
471
472 s.d = DT0;
473 d.d = DT1;
474
475 #define PMUL(r) \
476 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
477 if ((tmp & 0xff) > 0x7f) \
478 tmp += 0x100; \
479 d.VIS_W64(r) = tmp >> 8;
480
481 PMUL(0);
482 PMUL(1);
483 PMUL(2);
484 PMUL(3);
485 #undef PMUL
486
487 DT0 = d.d;
488 }
489
490 void helper_fmul8ulx16(void)
491 {
492 vis64 s, d;
493 uint32_t tmp;
494
495 s.d = DT0;
496 d.d = DT1;
497
498 #define PMUL(r) \
499 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
500 if ((tmp & 0xff) > 0x7f) \
501 tmp += 0x100; \
502 d.VIS_W64(r) = tmp >> 8;
503
504 PMUL(0);
505 PMUL(1);
506 PMUL(2);
507 PMUL(3);
508 #undef PMUL
509
510 DT0 = d.d;
511 }
512
513 void helper_fmuld8sux16(void)
514 {
515 vis64 s, d;
516 uint32_t tmp;
517
518 s.d = DT0;
519 d.d = DT1;
520
521 #define PMUL(r) \
522 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
523 if ((tmp & 0xff) > 0x7f) \
524 tmp += 0x100; \
525 d.VIS_L64(r) = tmp;
526
527 // Reverse calculation order to handle overlap
528 PMUL(1);
529 PMUL(0);
530 #undef PMUL
531
532 DT0 = d.d;
533 }
534
535 void helper_fmuld8ulx16(void)
536 {
537 vis64 s, d;
538 uint32_t tmp;
539
540 s.d = DT0;
541 d.d = DT1;
542
543 #define PMUL(r) \
544 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
545 if ((tmp & 0xff) > 0x7f) \
546 tmp += 0x100; \
547 d.VIS_L64(r) = tmp;
548
549 // Reverse calculation order to handle overlap
550 PMUL(1);
551 PMUL(0);
552 #undef PMUL
553
554 DT0 = d.d;
555 }
556
557 void helper_fexpand(void)
558 {
559 vis32 s;
560 vis64 d;
561
562 s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
563 d.d = DT1;
564 d.VIS_L64(0) = s.VIS_W32(0) << 4;
565 d.VIS_L64(1) = s.VIS_W32(1) << 4;
566 d.VIS_L64(2) = s.VIS_W32(2) << 4;
567 d.VIS_L64(3) = s.VIS_W32(3) << 4;
568
569 DT0 = d.d;
570 }
571
572 #define VIS_HELPER(name, F) \
573 void name##16(void) \
574 { \
575 vis64 s, d; \
576 \
577 s.d = DT0; \
578 d.d = DT1; \
579 \
580 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
581 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
582 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
583 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
584 \
585 DT0 = d.d; \
586 } \
587 \
588 void name##16s(void) \
589 { \
590 vis32 s, d; \
591 \
592 s.f = FT0; \
593 d.f = FT1; \
594 \
595 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
596 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
597 \
598 FT0 = d.f; \
599 } \
600 \
601 void name##32(void) \
602 { \
603 vis64 s, d; \
604 \
605 s.d = DT0; \
606 d.d = DT1; \
607 \
608 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
609 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
610 \
611 DT0 = d.d; \
612 } \
613 \
614 void name##32s(void) \
615 { \
616 vis32 s, d; \
617 \
618 s.f = FT0; \
619 d.f = FT1; \
620 \
621 d.l = F(d.l, s.l); \
622 \
623 FT0 = d.f; \
624 }
625
626 #define FADD(a, b) ((a) + (b))
627 #define FSUB(a, b) ((a) - (b))
628 VIS_HELPER(helper_fpadd, FADD)
629 VIS_HELPER(helper_fpsub, FSUB)
630
631 #define VIS_CMPHELPER(name, F) \
632 void name##16(void) \
633 { \
634 vis64 s, d; \
635 \
636 s.d = DT0; \
637 d.d = DT1; \
638 \
639 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
640 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
641 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
642 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
643 \
644 DT0 = d.d; \
645 } \
646 \
647 void name##32(void) \
648 { \
649 vis64 s, d; \
650 \
651 s.d = DT0; \
652 d.d = DT1; \
653 \
654 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
655 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
656 \
657 DT0 = d.d; \
658 }
659
660 #define FCMPGT(a, b) ((a) > (b))
661 #define FCMPEQ(a, b) ((a) == (b))
662 #define FCMPLE(a, b) ((a) <= (b))
663 #define FCMPNE(a, b) ((a) != (b))
664
665 VIS_CMPHELPER(helper_fcmpgt, FCMPGT)
666 VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
667 VIS_CMPHELPER(helper_fcmple, FCMPLE)
668 VIS_CMPHELPER(helper_fcmpne, FCMPNE)
669 #endif
670
671 void helper_check_ieee_exceptions(void)
672 {
673 target_ulong status;
674
675 status = get_float_exception_flags(&env->fp_status);
676 if (status) {
677 /* Copy IEEE 754 flags into FSR */
678 if (status & float_flag_invalid)
679 env->fsr |= FSR_NVC;
680 if (status & float_flag_overflow)
681 env->fsr |= FSR_OFC;
682 if (status & float_flag_underflow)
683 env->fsr |= FSR_UFC;
684 if (status & float_flag_divbyzero)
685 env->fsr |= FSR_DZC;
686 if (status & float_flag_inexact)
687 env->fsr |= FSR_NXC;
688
689 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
690 /* Unmasked exception, generate a trap */
691 env->fsr |= FSR_FTT_IEEE_EXCP;
692 raise_exception(TT_FP_EXCP);
693 } else {
694 /* Accumulate exceptions */
695 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
696 }
697 }
698 }
699
700 void helper_clear_float_exceptions(void)
701 {
702 set_float_exception_flags(0, &env->fp_status);
703 }
704
705 void helper_fabss(void)
706 {
707 FT0 = float32_abs(FT1);
708 }
709
710 #ifdef TARGET_SPARC64
711 void helper_fabsd(void)
712 {
713 DT0 = float64_abs(DT1);
714 }
715
716 #if defined(CONFIG_USER_ONLY)
717 void helper_fabsq(void)
718 {
719 QT0 = float128_abs(QT1);
720 }
721 #endif
722 #endif
723
724 void helper_fsqrts(void)
725 {
726 FT0 = float32_sqrt(FT1, &env->fp_status);
727 }
728
729 void helper_fsqrtd(void)
730 {
731 DT0 = float64_sqrt(DT1, &env->fp_status);
732 }
733
734 #if defined(CONFIG_USER_ONLY)
735 void helper_fsqrtq(void)
736 {
737 QT0 = float128_sqrt(QT1, &env->fp_status);
738 }
739 #endif
740
741 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
742 void glue(helper_, name) (void) \
743 { \
744 target_ulong new_fsr; \
745 \
746 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
747 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
748 case float_relation_unordered: \
749 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
750 if ((env->fsr & FSR_NVM) || TRAP) { \
751 env->fsr |= new_fsr; \
752 env->fsr |= FSR_NVC; \
753 env->fsr |= FSR_FTT_IEEE_EXCP; \
754 raise_exception(TT_FP_EXCP); \
755 } else { \
756 env->fsr |= FSR_NVA; \
757 } \
758 break; \
759 case float_relation_less: \
760 new_fsr = FSR_FCC0 << FS; \
761 break; \
762 case float_relation_greater: \
763 new_fsr = FSR_FCC1 << FS; \
764 break; \
765 default: \
766 new_fsr = 0; \
767 break; \
768 } \
769 env->fsr |= new_fsr; \
770 }
771
772 GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0);
773 GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
774
775 GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1);
776 GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
777
778 #ifdef CONFIG_USER_ONLY
779 GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
780 GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
781 #endif
782
783 #ifdef TARGET_SPARC64
784 GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0);
785 GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
786
787 GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0);
788 GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
789
790 GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0);
791 GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
792
793 GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1);
794 GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
795
796 GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1);
797 GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
798
799 GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1);
800 GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
801 #ifdef CONFIG_USER_ONLY
802 GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
803 GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
804 GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
805 GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
806 GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
807 GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
808 #endif
809 #endif
810
811 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && defined(DEBUG_MXCC)
812 static void dump_mxcc(CPUState *env)
813 {
814 printf("mxccdata: %016llx %016llx %016llx %016llx\n",
815 env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]);
816 printf("mxccregs: %016llx %016llx %016llx %016llx\n"
817 " %016llx %016llx %016llx %016llx\n",
818 env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3],
819 env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]);
820 }
821 #endif
822
823 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
824 && defined(DEBUG_ASI)
825 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
826 uint64_t r1)
827 {
828 switch (size)
829 {
830 case 1:
831 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
832 addr, asi, r1 & 0xff);
833 break;
834 case 2:
835 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
836 addr, asi, r1 & 0xffff);
837 break;
838 case 4:
839 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
840 addr, asi, r1 & 0xffffffff);
841 break;
842 case 8:
843 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
844 addr, asi, r1);
845 break;
846 }
847 }
848 #endif
849
850 #ifndef TARGET_SPARC64
851 #ifndef CONFIG_USER_ONLY
852 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
853 {
854 uint64_t ret = 0;
855 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
856 uint32_t last_addr = addr;
857 #endif
858
859 switch (asi) {
860 case 2: /* SuperSparc MXCC registers */
861 switch (addr) {
862 case 0x01c00a00: /* MXCC control register */
863 if (size == 8)
864 ret = env->mxccregs[3];
865 else
866 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
867 break;
868 case 0x01c00a04: /* MXCC control register */
869 if (size == 4)
870 ret = env->mxccregs[3];
871 else
872 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
873 break;
874 case 0x01c00c00: /* Module reset register */
875 if (size == 8) {
876 ret = env->mxccregs[5];
877 // should we do something here?
878 } else
879 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
880 break;
881 case 0x01c00f00: /* MBus port address register */
882 if (size == 8)
883 ret = env->mxccregs[7];
884 else
885 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
886 break;
887 default:
888 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
889 break;
890 }
891 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, addr = %08x -> ret = %08x,"
892 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
893 #ifdef DEBUG_MXCC
894 dump_mxcc(env);
895 #endif
896 break;
897 case 3: /* MMU probe */
898 {
899 int mmulev;
900
901 mmulev = (addr >> 8) & 15;
902 if (mmulev > 4)
903 ret = 0;
904 else
905 ret = mmu_probe(env, addr, mmulev);
906 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
907 addr, mmulev, ret);
908 }
909 break;
910 case 4: /* read MMU regs */
911 {
912 int reg = (addr >> 8) & 0x1f;
913
914 ret = env->mmuregs[reg];
915 if (reg == 3) /* Fault status cleared on read */
916 env->mmuregs[3] = 0;
917 else if (reg == 0x13) /* Fault status read */
918 ret = env->mmuregs[3];
919 else if (reg == 0x14) /* Fault address read */
920 ret = env->mmuregs[4];
921 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
922 }
923 break;
924 case 5: // Turbosparc ITLB Diagnostic
925 case 6: // Turbosparc DTLB Diagnostic
926 case 7: // Turbosparc IOTLB Diagnostic
927 break;
928 case 9: /* Supervisor code access */
929 switch(size) {
930 case 1:
931 ret = ldub_code(addr);
932 break;
933 case 2:
934 ret = lduw_code(addr & ~1);
935 break;
936 default:
937 case 4:
938 ret = ldl_code(addr & ~3);
939 break;
940 case 8:
941 ret = ldq_code(addr & ~7);
942 break;
943 }
944 break;
945 case 0xa: /* User data access */
946 switch(size) {
947 case 1:
948 ret = ldub_user(addr);
949 break;
950 case 2:
951 ret = lduw_user(addr & ~1);
952 break;
953 default:
954 case 4:
955 ret = ldl_user(addr & ~3);
956 break;
957 case 8:
958 ret = ldq_user(addr & ~7);
959 break;
960 }
961 break;
962 case 0xb: /* Supervisor data access */
963 switch(size) {
964 case 1:
965 ret = ldub_kernel(addr);
966 break;
967 case 2:
968 ret = lduw_kernel(addr & ~1);
969 break;
970 default:
971 case 4:
972 ret = ldl_kernel(addr & ~3);
973 break;
974 case 8:
975 ret = ldq_kernel(addr & ~7);
976 break;
977 }
978 break;
979 case 0xc: /* I-cache tag */
980 case 0xd: /* I-cache data */
981 case 0xe: /* D-cache tag */
982 case 0xf: /* D-cache data */
983 break;
984 case 0x20: /* MMU passthrough */
985 switch(size) {
986 case 1:
987 ret = ldub_phys(addr);
988 break;
989 case 2:
990 ret = lduw_phys(addr & ~1);
991 break;
992 default:
993 case 4:
994 ret = ldl_phys(addr & ~3);
995 break;
996 case 8:
997 ret = ldq_phys(addr & ~7);
998 break;
999 }
1000 break;
1001 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1002 switch(size) {
1003 case 1:
1004 ret = ldub_phys((target_phys_addr_t)addr
1005 | ((target_phys_addr_t)(asi & 0xf) << 32));
1006 break;
1007 case 2:
1008 ret = lduw_phys((target_phys_addr_t)(addr & ~1)
1009 | ((target_phys_addr_t)(asi & 0xf) << 32));
1010 break;
1011 default:
1012 case 4:
1013 ret = ldl_phys((target_phys_addr_t)(addr & ~3)
1014 | ((target_phys_addr_t)(asi & 0xf) << 32));
1015 break;
1016 case 8:
1017 ret = ldq_phys((target_phys_addr_t)(addr & ~7)
1018 | ((target_phys_addr_t)(asi & 0xf) << 32));
1019 break;
1020 }
1021 break;
1022 case 0x30: // Turbosparc secondary cache diagnostic
1023 case 0x31: // Turbosparc RAM snoop
1024 case 0x32: // Turbosparc page table descriptor diagnostic
1025 case 0x39: /* data cache diagnostic register */
1026 ret = 0;
1027 break;
1028 case 8: /* User code access, XXX */
1029 default:
1030 do_unassigned_access(addr, 0, 0, asi);
1031 ret = 0;
1032 break;
1033 }
1034 if (sign) {
1035 switch(size) {
1036 case 1:
1037 ret = (int8_t) ret;
1038 break;
1039 case 2:
1040 ret = (int16_t) ret;
1041 break;
1042 case 4:
1043 ret = (int32_t) ret;
1044 break;
1045 default:
1046 break;
1047 }
1048 }
1049 #ifdef DEBUG_ASI
1050 dump_asi("read ", last_addr, asi, size, ret);
1051 #endif
1052 return ret;
1053 }
1054
1055 void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
1056 {
1057 switch(asi) {
1058 case 2: /* SuperSparc MXCC registers */
1059 switch (addr) {
1060 case 0x01c00000: /* MXCC stream data register 0 */
1061 if (size == 8)
1062 env->mxccdata[0] = val;
1063 else
1064 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
1065 break;
1066 case 0x01c00008: /* MXCC stream data register 1 */
1067 if (size == 8)
1068 env->mxccdata[1] = val;
1069 else
1070 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
1071 break;
1072 case 0x01c00010: /* MXCC stream data register 2 */
1073 if (size == 8)
1074 env->mxccdata[2] = val;
1075 else
1076 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
1077 break;
1078 case 0x01c00018: /* MXCC stream data register 3 */
1079 if (size == 8)
1080 env->mxccdata[3] = val;
1081 else
1082 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
1083 break;
1084 case 0x01c00100: /* MXCC stream source */
1085 if (size == 8)
1086 env->mxccregs[0] = val;
1087 else
1088 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
1089 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0);
1090 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8);
1091 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16);
1092 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24);
1093 break;
1094 case 0x01c00200: /* MXCC stream destination */
1095 if (size == 8)
1096 env->mxccregs[1] = val;
1097 else
1098 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
1099 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]);
1100 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]);
1101 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]);
1102 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]);
1103 break;
1104 case 0x01c00a00: /* MXCC control register */
1105 if (size == 8)
1106 env->mxccregs[3] = val;
1107 else
1108 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
1109 break;
1110 case 0x01c00a04: /* MXCC control register */
1111 if (size == 4)
1112 env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) | val;
1113 else
1114 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
1115 break;
1116 case 0x01c00e00: /* MXCC error register */
1117 // writing a 1 bit clears the error
1118 if (size == 8)
1119 env->mxccregs[6] &= ~val;
1120 else
1121 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
1122 break;
1123 case 0x01c00f00: /* MBus port address register */
1124 if (size == 8)
1125 env->mxccregs[7] = val;
1126 else
1127 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
1128 break;
1129 default:
1130 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
1131 break;
1132 }
1133 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi, size, addr, val);
1134 #ifdef DEBUG_MXCC
1135 dump_mxcc(env);
1136 #endif
1137 break;
1138 case 3: /* MMU flush */
1139 {
1140 int mmulev;
1141
1142 mmulev = (addr >> 8) & 15;
1143 DPRINTF_MMU("mmu flush level %d\n", mmulev);
1144 switch (mmulev) {
1145 case 0: // flush page
1146 tlb_flush_page(env, addr & 0xfffff000);
1147 break;
1148 case 1: // flush segment (256k)
1149 case 2: // flush region (16M)
1150 case 3: // flush context (4G)
1151 case 4: // flush entire
1152 tlb_flush(env, 1);
1153 break;
1154 default:
1155 break;
1156 }
1157 #ifdef DEBUG_MMU
1158 dump_mmu(env);
1159 #endif
1160 }
1161 break;
1162 case 4: /* write MMU regs */
1163 {
1164 int reg = (addr >> 8) & 0x1f;
1165 uint32_t oldreg;
1166
1167 oldreg = env->mmuregs[reg];
1168 switch(reg) {
1169 case 0: // Control Register
1170 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
1171 (val & 0x00ffffff);
1172 // Mappings generated during no-fault mode or MMU
1173 // disabled mode are invalid in normal mode
1174 if ((oldreg & (MMU_E | MMU_NF | env->mmu_bm)) !=
1175 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->mmu_bm)))
1176 tlb_flush(env, 1);
1177 break;
1178 case 1: // Context Table Pointer Register
1179 env->mmuregs[reg] = val & env->mmu_ctpr_mask;
1180 break;
1181 case 2: // Context Register
1182 env->mmuregs[reg] = val & env->mmu_cxr_mask;
1183 if (oldreg != env->mmuregs[reg]) {
1184 /* we flush when the MMU context changes because
1185 QEMU has no MMU context support */
1186 tlb_flush(env, 1);
1187 }
1188 break;
1189 case 3: // Synchronous Fault Status Register with Clear
1190 case 4: // Synchronous Fault Address Register
1191 break;
1192 case 0x10: // TLB Replacement Control Register
1193 env->mmuregs[reg] = val & env->mmu_trcr_mask;
1194 break;
1195 case 0x13: // Synchronous Fault Status Register with Read and Clear
1196 env->mmuregs[3] = val & env->mmu_sfsr_mask;
1197 break;
1198 case 0x14: // Synchronous Fault Address Register
1199 env->mmuregs[4] = val;
1200 break;
1201 default:
1202 env->mmuregs[reg] = val;
1203 break;
1204 }
1205 if (oldreg != env->mmuregs[reg]) {
1206 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
1207 }
1208 #ifdef DEBUG_MMU
1209 dump_mmu(env);
1210 #endif
1211 }
1212 break;
1213 case 5: // Turbosparc ITLB Diagnostic
1214 case 6: // Turbosparc DTLB Diagnostic
1215 case 7: // Turbosparc IOTLB Diagnostic
1216 break;
1217 case 0xa: /* User data access */
1218 switch(size) {
1219 case 1:
1220 stb_user(addr, val);
1221 break;
1222 case 2:
1223 stw_user(addr & ~1, val);
1224 break;
1225 default:
1226 case 4:
1227 stl_user(addr & ~3, val);
1228 break;
1229 case 8:
1230 stq_user(addr & ~7, val);
1231 break;
1232 }
1233 break;
1234 case 0xb: /* Supervisor data access */
1235 switch(size) {
1236 case 1:
1237 stb_kernel(addr, val);
1238 break;
1239 case 2:
1240 stw_kernel(addr & ~1, val);
1241 break;
1242 default:
1243 case 4:
1244 stl_kernel(addr & ~3, val);
1245 break;
1246 case 8:
1247 stq_kernel(addr & ~7, val);
1248 break;
1249 }
1250 break;
1251 case 0xc: /* I-cache tag */
1252 case 0xd: /* I-cache data */
1253 case 0xe: /* D-cache tag */
1254 case 0xf: /* D-cache data */
1255 case 0x10: /* I/D-cache flush page */
1256 case 0x11: /* I/D-cache flush segment */
1257 case 0x12: /* I/D-cache flush region */
1258 case 0x13: /* I/D-cache flush context */
1259 case 0x14: /* I/D-cache flush user */
1260 break;
1261 case 0x17: /* Block copy, sta access */
1262 {
1263 // val = src
1264 // addr = dst
1265 // copy 32 bytes
1266 unsigned int i;
1267 uint32_t src = val & ~3, dst = addr & ~3, temp;
1268
1269 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
1270 temp = ldl_kernel(src);
1271 stl_kernel(dst, temp);
1272 }
1273 }
1274 break;
1275 case 0x1f: /* Block fill, stda access */
1276 {
1277 // addr = dst
1278 // fill 32 bytes with val
1279 unsigned int i;
1280 uint32_t dst = addr & 7;
1281
1282 for (i = 0; i < 32; i += 8, dst += 8)
1283 stq_kernel(dst, val);
1284 }
1285 break;
1286 case 0x20: /* MMU passthrough */
1287 {
1288 switch(size) {
1289 case 1:
1290 stb_phys(addr, val);
1291 break;
1292 case 2:
1293 stw_phys(addr & ~1, val);
1294 break;
1295 case 4:
1296 default:
1297 stl_phys(addr & ~3, val);
1298 break;
1299 case 8:
1300 stq_phys(addr & ~7, val);
1301 break;
1302 }
1303 }
1304 break;
1305 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1306 {
1307 switch(size) {
1308 case 1:
1309 stb_phys((target_phys_addr_t)addr
1310 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1311 break;
1312 case 2:
1313 stw_phys((target_phys_addr_t)(addr & ~1)
1314 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1315 break;
1316 case 4:
1317 default:
1318 stl_phys((target_phys_addr_t)(addr & ~3)
1319 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1320 break;
1321 case 8:
1322 stq_phys((target_phys_addr_t)(addr & ~7)
1323 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1324 break;
1325 }
1326 }
1327 break;
1328 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
1329 case 0x31: // store buffer data, Ross RT620 I-cache flush or
1330 // Turbosparc snoop RAM
1331 case 0x32: // store buffer control or Turbosparc page table descriptor diagnostic
1332 case 0x36: /* I-cache flash clear */
1333 case 0x37: /* D-cache flash clear */
1334 case 0x38: /* breakpoint diagnostics */
1335 case 0x4c: /* breakpoint action */
1336 break;
1337 case 8: /* User code access, XXX */
1338 case 9: /* Supervisor code access, XXX */
1339 default:
1340 do_unassigned_access(addr, 1, 0, asi);
1341 break;
1342 }
1343 #ifdef DEBUG_ASI
1344 dump_asi("write", addr, asi, size, val);
1345 #endif
1346 }
1347
1348 #endif /* CONFIG_USER_ONLY */
1349 #else /* TARGET_SPARC64 */
1350
1351 #ifdef CONFIG_USER_ONLY
1352 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1353 {
1354 uint64_t ret = 0;
1355 #if defined(DEBUG_ASI)
1356 target_ulong last_addr = addr;
1357 #endif
1358
1359 if (asi < 0x80)
1360 raise_exception(TT_PRIV_ACT);
1361
1362 switch (asi) {
1363 case 0x80: // Primary
1364 case 0x82: // Primary no-fault
1365 case 0x88: // Primary LE
1366 case 0x8a: // Primary no-fault LE
1367 {
1368 switch(size) {
1369 case 1:
1370 ret = ldub_raw(addr);
1371 break;
1372 case 2:
1373 ret = lduw_raw(addr & ~1);
1374 break;
1375 case 4:
1376 ret = ldl_raw(addr & ~3);
1377 break;
1378 default:
1379 case 8:
1380 ret = ldq_raw(addr & ~7);
1381 break;
1382 }
1383 }
1384 break;
1385 case 0x81: // Secondary
1386 case 0x83: // Secondary no-fault
1387 case 0x89: // Secondary LE
1388 case 0x8b: // Secondary no-fault LE
1389 // XXX
1390 break;
1391 default:
1392 break;
1393 }
1394
1395 /* Convert from little endian */
1396 switch (asi) {
1397 case 0x88: // Primary LE
1398 case 0x89: // Secondary LE
1399 case 0x8a: // Primary no-fault LE
1400 case 0x8b: // Secondary no-fault LE
1401 switch(size) {
1402 case 2:
1403 ret = bswap16(ret);
1404 break;
1405 case 4:
1406 ret = bswap32(ret);
1407 break;
1408 case 8:
1409 ret = bswap64(ret);
1410 break;
1411 default:
1412 break;
1413 }
1414 default:
1415 break;
1416 }
1417
1418 /* Convert to signed number */
1419 if (sign) {
1420 switch(size) {
1421 case 1:
1422 ret = (int8_t) ret;
1423 break;
1424 case 2:
1425 ret = (int16_t) ret;
1426 break;
1427 case 4:
1428 ret = (int32_t) ret;
1429 break;
1430 default:
1431 break;
1432 }
1433 }
1434 #ifdef DEBUG_ASI
1435 dump_asi("read ", last_addr, asi, size, ret);
1436 #endif
1437 return ret;
1438 }
1439
1440 void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
1441 {
1442 #ifdef DEBUG_ASI
1443 dump_asi("write", addr, asi, size, val);
1444 #endif
1445 if (asi < 0x80)
1446 raise_exception(TT_PRIV_ACT);
1447
1448 /* Convert to little endian */
1449 switch (asi) {
1450 case 0x88: // Primary LE
1451 case 0x89: // Secondary LE
1452 switch(size) {
1453 case 2:
1454 addr = bswap16(addr);
1455 break;
1456 case 4:
1457 addr = bswap32(addr);
1458 break;
1459 case 8:
1460 addr = bswap64(addr);
1461 break;
1462 default:
1463 break;
1464 }
1465 default:
1466 break;
1467 }
1468
1469 switch(asi) {
1470 case 0x80: // Primary
1471 case 0x88: // Primary LE
1472 {
1473 switch(size) {
1474 case 1:
1475 stb_raw(addr, val);
1476 break;
1477 case 2:
1478 stw_raw(addr & ~1, val);
1479 break;
1480 case 4:
1481 stl_raw(addr & ~3, val);
1482 break;
1483 case 8:
1484 default:
1485 stq_raw(addr & ~7, val);
1486 break;
1487 }
1488 }
1489 break;
1490 case 0x81: // Secondary
1491 case 0x89: // Secondary LE
1492 // XXX
1493 return;
1494
1495 case 0x82: // Primary no-fault, RO
1496 case 0x83: // Secondary no-fault, RO
1497 case 0x8a: // Primary no-fault LE, RO
1498 case 0x8b: // Secondary no-fault LE, RO
1499 default:
1500 do_unassigned_access(addr, 1, 0, 1);
1501 return;
1502 }
1503 }
1504
1505 #else /* CONFIG_USER_ONLY */
1506
1507 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1508 {
1509 uint64_t ret = 0;
1510 #if defined(DEBUG_ASI)
1511 target_ulong last_addr = addr;
1512 #endif
1513
1514 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1515 || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
1516 raise_exception(TT_PRIV_ACT);
1517
1518 switch (asi) {
1519 case 0x10: // As if user primary
1520 case 0x18: // As if user primary LE
1521 case 0x80: // Primary
1522 case 0x82: // Primary no-fault
1523 case 0x88: // Primary LE
1524 case 0x8a: // Primary no-fault LE
1525 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1526 if (env->hpstate & HS_PRIV) {
1527 switch(size) {
1528 case 1:
1529 ret = ldub_hypv(addr);
1530 break;
1531 case 2:
1532 ret = lduw_hypv(addr & ~1);
1533 break;
1534 case 4:
1535 ret = ldl_hypv(addr & ~3);
1536 break;
1537 default:
1538 case 8:
1539 ret = ldq_hypv(addr & ~7);
1540 break;
1541 }
1542 } else {
1543 switch(size) {
1544 case 1:
1545 ret = ldub_kernel(addr);
1546 break;
1547 case 2:
1548 ret = lduw_kernel(addr & ~1);
1549 break;
1550 case 4:
1551 ret = ldl_kernel(addr & ~3);
1552 break;
1553 default:
1554 case 8:
1555 ret = ldq_kernel(addr & ~7);
1556 break;
1557 }
1558 }
1559 } else {
1560 switch(size) {
1561 case 1:
1562 ret = ldub_user(addr);
1563 break;
1564 case 2:
1565 ret = lduw_user(addr & ~1);
1566 break;
1567 case 4:
1568 ret = ldl_user(addr & ~3);
1569 break;
1570 default:
1571 case 8:
1572 ret = ldq_user(addr & ~7);
1573 break;
1574 }
1575 }
1576 break;
1577 case 0x14: // Bypass
1578 case 0x15: // Bypass, non-cacheable
1579 case 0x1c: // Bypass LE
1580 case 0x1d: // Bypass, non-cacheable LE
1581 {
1582 switch(size) {
1583 case 1:
1584 ret = ldub_phys(addr);
1585 break;
1586 case 2:
1587 ret = lduw_phys(addr & ~1);
1588 break;
1589 case 4:
1590 ret = ldl_phys(addr & ~3);
1591 break;
1592 default:
1593 case 8:
1594 ret = ldq_phys(addr & ~7);
1595 break;
1596 }
1597 break;
1598 }
1599 case 0x04: // Nucleus
1600 case 0x0c: // Nucleus Little Endian (LE)
1601 case 0x11: // As if user secondary
1602 case 0x19: // As if user secondary LE
1603 case 0x24: // Nucleus quad LDD 128 bit atomic
1604 case 0x2c: // Nucleus quad LDD 128 bit atomic
1605 case 0x4a: // UPA config
1606 case 0x81: // Secondary
1607 case 0x83: // Secondary no-fault
1608 case 0x89: // Secondary LE
1609 case 0x8b: // Secondary no-fault LE
1610 // XXX
1611 break;
1612 case 0x45: // LSU
1613 ret = env->lsu;
1614 break;
1615 case 0x50: // I-MMU regs
1616 {
1617 int reg = (addr >> 3) & 0xf;
1618
1619 ret = env->immuregs[reg];
1620 break;
1621 }
1622 case 0x51: // I-MMU 8k TSB pointer
1623 case 0x52: // I-MMU 64k TSB pointer
1624 case 0x55: // I-MMU data access
1625 // XXX
1626 break;
1627 case 0x56: // I-MMU tag read
1628 {
1629 unsigned int i;
1630
1631 for (i = 0; i < 64; i++) {
1632 // Valid, ctx match, vaddr match
1633 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
1634 env->itlb_tag[i] == addr) {
1635 ret = env->itlb_tag[i];
1636 break;
1637 }
1638 }
1639 break;
1640 }
1641 case 0x58: // D-MMU regs
1642 {
1643 int reg = (addr >> 3) & 0xf;
1644
1645 ret = env->dmmuregs[reg];
1646 break;
1647 }
1648 case 0x5e: // D-MMU tag read
1649 {
1650 unsigned int i;
1651
1652 for (i = 0; i < 64; i++) {
1653 // Valid, ctx match, vaddr match
1654 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
1655 env->dtlb_tag[i] == addr) {
1656 ret = env->dtlb_tag[i];
1657 break;
1658 }
1659 }
1660 break;
1661 }
1662 case 0x59: // D-MMU 8k TSB pointer
1663 case 0x5a: // D-MMU 64k TSB pointer
1664 case 0x5b: // D-MMU data pointer
1665 case 0x5d: // D-MMU data access
1666 case 0x48: // Interrupt dispatch, RO
1667 case 0x49: // Interrupt data receive
1668 case 0x7f: // Incoming interrupt vector, RO
1669 // XXX
1670 break;
1671 case 0x54: // I-MMU data in, WO
1672 case 0x57: // I-MMU demap, WO
1673 case 0x5c: // D-MMU data in, WO
1674 case 0x5f: // D-MMU demap, WO
1675 case 0x77: // Interrupt vector, WO
1676 default:
1677 do_unassigned_access(addr, 0, 0, 1);
1678 ret = 0;
1679 break;
1680 }
1681
1682 /* Convert from little endian */
1683 switch (asi) {
1684 case 0x0c: // Nucleus Little Endian (LE)
1685 case 0x18: // As if user primary LE
1686 case 0x19: // As if user secondary LE
1687 case 0x1c: // Bypass LE
1688 case 0x1d: // Bypass, non-cacheable LE
1689 case 0x88: // Primary LE
1690 case 0x89: // Secondary LE
1691 case 0x8a: // Primary no-fault LE
1692 case 0x8b: // Secondary no-fault LE
1693 switch(size) {
1694 case 2:
1695 ret = bswap16(ret);
1696 break;
1697 case 4:
1698 ret = bswap32(ret);
1699 break;
1700 case 8:
1701 ret = bswap64(ret);
1702 break;
1703 default:
1704 break;
1705 }
1706 default:
1707 break;
1708 }
1709
1710 /* Convert to signed number */
1711 if (sign) {
1712 switch(size) {
1713 case 1:
1714 ret = (int8_t) ret;
1715 break;
1716 case 2:
1717 ret = (int16_t) ret;
1718 break;
1719 case 4:
1720 ret = (int32_t) ret;
1721 break;
1722 default:
1723 break;
1724 }
1725 }
1726 #ifdef DEBUG_ASI
1727 dump_asi("read ", last_addr, asi, size, ret);
1728 #endif
1729 return ret;
1730 }
1731
1732 void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
1733 {
1734 #ifdef DEBUG_ASI
1735 dump_asi("write", addr, asi, size, val);
1736 #endif
1737 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1738 || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
1739 raise_exception(TT_PRIV_ACT);
1740
1741 /* Convert to little endian */
1742 switch (asi) {
1743 case 0x0c: // Nucleus Little Endian (LE)
1744 case 0x18: // As if user primary LE
1745 case 0x19: // As if user secondary LE
1746 case 0x1c: // Bypass LE
1747 case 0x1d: // Bypass, non-cacheable LE
1748 case 0x88: // Primary LE
1749 case 0x89: // Secondary LE
1750 switch(size) {
1751 case 2:
1752 addr = bswap16(addr);
1753 break;
1754 case 4:
1755 addr = bswap32(addr);
1756 break;
1757 case 8:
1758 addr = bswap64(addr);
1759 break;
1760 default:
1761 break;
1762 }
1763 default:
1764 break;
1765 }
1766
1767 switch(asi) {
1768 case 0x10: // As if user primary
1769 case 0x18: // As if user primary LE
1770 case 0x80: // Primary
1771 case 0x88: // Primary LE
1772 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1773 if (env->hpstate & HS_PRIV) {
1774 switch(size) {
1775 case 1:
1776 stb_hypv(addr, val);
1777 break;
1778 case 2:
1779 stw_hypv(addr & ~1, val);
1780 break;
1781 case 4:
1782 stl_hypv(addr & ~3, val);
1783 break;
1784 case 8:
1785 default:
1786 stq_hypv(addr & ~7, val);
1787 break;
1788 }
1789 } else {
1790 switch(size) {
1791 case 1:
1792 stb_kernel(addr, val);
1793 break;
1794 case 2:
1795 stw_kernel(addr & ~1, val);
1796 break;
1797 case 4:
1798 stl_kernel(addr & ~3, val);
1799 break;
1800 case 8:
1801 default:
1802 stq_kernel(addr & ~7, val);
1803 break;
1804 }
1805 }
1806 } else {
1807 switch(size) {
1808 case 1:
1809 stb_user(addr, val);
1810 break;
1811 case 2:
1812 stw_user(addr & ~1, val);
1813 break;
1814 case 4:
1815 stl_user(addr & ~3, val);
1816 break;
1817 case 8:
1818 default:
1819 stq_user(addr & ~7, val);
1820 break;
1821 }
1822 }
1823 break;
1824 case 0x14: // Bypass
1825 case 0x15: // Bypass, non-cacheable
1826 case 0x1c: // Bypass LE
1827 case 0x1d: // Bypass, non-cacheable LE
1828 {
1829 switch(size) {
1830 case 1:
1831 stb_phys(addr, val);
1832 break;
1833 case 2:
1834 stw_phys(addr & ~1, val);
1835 break;
1836 case 4:
1837 stl_phys(addr & ~3, val);
1838 break;
1839 case 8:
1840 default:
1841 stq_phys(addr & ~7, val);
1842 break;
1843 }
1844 }
1845 return;
1846 case 0x04: // Nucleus
1847 case 0x0c: // Nucleus Little Endian (LE)
1848 case 0x11: // As if user secondary
1849 case 0x19: // As if user secondary LE
1850 case 0x24: // Nucleus quad LDD 128 bit atomic
1851 case 0x2c: // Nucleus quad LDD 128 bit atomic
1852 case 0x4a: // UPA config
1853 case 0x81: // Secondary
1854 case 0x89: // Secondary LE
1855 // XXX
1856 return;
1857 case 0x45: // LSU
1858 {
1859 uint64_t oldreg;
1860
1861 oldreg = env->lsu;
1862 env->lsu = val & (DMMU_E | IMMU_E);
1863 // Mappings generated during D/I MMU disabled mode are
1864 // invalid in normal mode
1865 if (oldreg != env->lsu) {
1866 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
1867 #ifdef DEBUG_MMU
1868 dump_mmu(env);
1869 #endif
1870 tlb_flush(env, 1);
1871 }
1872 return;
1873 }
1874 case 0x50: // I-MMU regs
1875 {
1876 int reg = (addr >> 3) & 0xf;
1877 uint64_t oldreg;
1878
1879 oldreg = env->immuregs[reg];
1880 switch(reg) {
1881 case 0: // RO
1882 case 4:
1883 return;
1884 case 1: // Not in I-MMU
1885 case 2:
1886 case 7:
1887 case 8:
1888 return;
1889 case 3: // SFSR
1890 if ((val & 1) == 0)
1891 val = 0; // Clear SFSR
1892 break;
1893 case 5: // TSB access
1894 case 6: // Tag access
1895 default:
1896 break;
1897 }
1898 env->immuregs[reg] = val;
1899 if (oldreg != env->immuregs[reg]) {
1900 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1901 }
1902 #ifdef DEBUG_MMU
1903 dump_mmu(env);
1904 #endif
1905 return;
1906 }
1907 case 0x54: // I-MMU data in
1908 {
1909 unsigned int i;
1910
1911 // Try finding an invalid entry
1912 for (i = 0; i < 64; i++) {
1913 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
1914 env->itlb_tag[i] = env->immuregs[6];
1915 env->itlb_tte[i] = val;
1916 return;
1917 }
1918 }
1919 // Try finding an unlocked entry
1920 for (i = 0; i < 64; i++) {
1921 if ((env->itlb_tte[i] & 0x40) == 0) {
1922 env->itlb_tag[i] = env->immuregs[6];
1923 env->itlb_tte[i] = val;
1924 return;
1925 }
1926 }
1927 // error state?
1928 return;
1929 }
1930 case 0x55: // I-MMU data access
1931 {
1932 unsigned int i = (addr >> 3) & 0x3f;
1933
1934 env->itlb_tag[i] = env->immuregs[6];
1935 env->itlb_tte[i] = val;
1936 return;
1937 }
1938 case 0x57: // I-MMU demap
1939 // XXX
1940 return;
1941 case 0x58: // D-MMU regs
1942 {
1943 int reg = (addr >> 3) & 0xf;
1944 uint64_t oldreg;
1945
1946 oldreg = env->dmmuregs[reg];
1947 switch(reg) {
1948 case 0: // RO
1949 case 4:
1950 return;
1951 case 3: // SFSR
1952 if ((val & 1) == 0) {
1953 val = 0; // Clear SFSR, Fault address
1954 env->dmmuregs[4] = 0;
1955 }
1956 env->dmmuregs[reg] = val;
1957 break;
1958 case 1: // Primary context
1959 case 2: // Secondary context
1960 case 5: // TSB access
1961 case 6: // Tag access
1962 case 7: // Virtual Watchpoint
1963 case 8: // Physical Watchpoint
1964 default:
1965 break;
1966 }
1967 env->dmmuregs[reg] = val;
1968 if (oldreg != env->dmmuregs[reg]) {
1969 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1970 }
1971 #ifdef DEBUG_MMU
1972 dump_mmu(env);
1973 #endif
1974 return;
1975 }
1976 case 0x5c: // D-MMU data in
1977 {
1978 unsigned int i;
1979
1980 // Try finding an invalid entry
1981 for (i = 0; i < 64; i++) {
1982 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
1983 env->dtlb_tag[i] = env->dmmuregs[6];
1984 env->dtlb_tte[i] = val;
1985 return;
1986 }
1987 }
1988 // Try finding an unlocked entry
1989 for (i = 0; i < 64; i++) {
1990 if ((env->dtlb_tte[i] & 0x40) == 0) {
1991 env->dtlb_tag[i] = env->dmmuregs[6];
1992 env->dtlb_tte[i] = val;
1993 return;
1994 }
1995 }
1996 // error state?
1997 return;
1998 }
1999 case 0x5d: // D-MMU data access
2000 {
2001 unsigned int i = (addr >> 3) & 0x3f;
2002
2003 env->dtlb_tag[i] = env->dmmuregs[6];
2004 env->dtlb_tte[i] = val;
2005 return;
2006 }
2007 case 0x5f: // D-MMU demap
2008 case 0x49: // Interrupt data receive
2009 // XXX
2010 return;
2011 case 0x51: // I-MMU 8k TSB pointer, RO
2012 case 0x52: // I-MMU 64k TSB pointer, RO
2013 case 0x56: // I-MMU tag read, RO
2014 case 0x59: // D-MMU 8k TSB pointer, RO
2015 case 0x5a: // D-MMU 64k TSB pointer, RO
2016 case 0x5b: // D-MMU data pointer, RO
2017 case 0x5e: // D-MMU tag read, RO
2018 case 0x48: // Interrupt dispatch, RO
2019 case 0x7f: // Incoming interrupt vector, RO
2020 case 0x82: // Primary no-fault, RO
2021 case 0x83: // Secondary no-fault, RO
2022 case 0x8a: // Primary no-fault LE, RO
2023 case 0x8b: // Secondary no-fault LE, RO
2024 default:
2025 do_unassigned_access(addr, 1, 0, 1);
2026 return;
2027 }
2028 }
2029 #endif /* CONFIG_USER_ONLY */
2030
2031 void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
2032 {
2033 unsigned int i;
2034 target_ulong val;
2035
2036 switch (asi) {
2037 case 0xf0: // Block load primary
2038 case 0xf1: // Block load secondary
2039 case 0xf8: // Block load primary LE
2040 case 0xf9: // Block load secondary LE
2041 if (rd & 7) {
2042 raise_exception(TT_ILL_INSN);
2043 return;
2044 }
2045 if (addr & 0x3f) {
2046 raise_exception(TT_UNALIGNED);
2047 return;
2048 }
2049 for (i = 0; i < 16; i++) {
2050 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, 0);
2051 addr += 4;
2052 }
2053
2054 return;
2055 default:
2056 break;
2057 }
2058
2059 val = helper_ld_asi(addr, asi, size, 0);
2060 switch(size) {
2061 default:
2062 case 4:
2063 *((uint32_t *)&FT0) = val;
2064 break;
2065 case 8:
2066 *((int64_t *)&DT0) = val;
2067 break;
2068 #if defined(CONFIG_USER_ONLY)
2069 case 16:
2070 // XXX
2071 break;
2072 #endif
2073 }
2074 }
2075
2076 void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
2077 {
2078 unsigned int i;
2079 target_ulong val = 0;
2080
2081 switch (asi) {
2082 case 0xf0: // Block store primary
2083 case 0xf1: // Block store secondary
2084 case 0xf8: // Block store primary LE
2085 case 0xf9: // Block store secondary LE
2086 if (rd & 7) {
2087 raise_exception(TT_ILL_INSN);
2088 return;
2089 }
2090 if (addr & 0x3f) {
2091 raise_exception(TT_UNALIGNED);
2092 return;
2093 }
2094 for (i = 0; i < 16; i++) {
2095 val = *(uint32_t *)&env->fpr[rd++];
2096 helper_st_asi(addr, val, asi & 0x8f, 4);
2097 addr += 4;
2098 }
2099
2100 return;
2101 default:
2102 break;
2103 }
2104
2105 switch(size) {
2106 default:
2107 case 4:
2108 val = *((uint32_t *)&FT0);
2109 break;
2110 case 8:
2111 val = *((int64_t *)&DT0);
2112 break;
2113 #if defined(CONFIG_USER_ONLY)
2114 case 16:
2115 // XXX
2116 break;
2117 #endif
2118 }
2119 helper_st_asi(addr, val, asi, size);
2120 }
2121
2122 target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
2123 target_ulong val2, uint32_t asi)
2124 {
2125 target_ulong ret;
2126
2127 val1 &= 0xffffffffUL;
2128 ret = helper_ld_asi(addr, asi, 4, 0);
2129 ret &= 0xffffffffUL;
2130 if (val1 == ret)
2131 helper_st_asi(addr, val2 & 0xffffffffUL, asi, 4);
2132 return ret;
2133 }
2134
2135 target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
2136 target_ulong val2, uint32_t asi)
2137 {
2138 target_ulong ret;
2139
2140 ret = helper_ld_asi(addr, asi, 8, 0);
2141 if (val1 == ret)
2142 helper_st_asi(addr, val2, asi, 8);
2143 return ret;
2144 }
2145 #endif /* TARGET_SPARC64 */
2146
2147 #ifndef TARGET_SPARC64
2148 void helper_rett(void)
2149 {
2150 unsigned int cwp;
2151
2152 if (env->psret == 1)
2153 raise_exception(TT_ILL_INSN);
2154
2155 env->psret = 1;
2156 cwp = (env->cwp + 1) & (NWINDOWS - 1);
2157 if (env->wim & (1 << cwp)) {
2158 raise_exception(TT_WIN_UNF);
2159 }
2160 set_cwp(cwp);
2161 env->psrs = env->psrps;
2162 }
2163 #endif
2164
2165 target_ulong helper_udiv(target_ulong a, target_ulong b)
2166 {
2167 uint64_t x0;
2168 uint32_t x1;
2169
2170 x0 = a | ((uint64_t) (env->y) << 32);
2171 x1 = b;
2172
2173 if (x1 == 0) {
2174 raise_exception(TT_DIV_ZERO);
2175 }
2176
2177 x0 = x0 / x1;
2178 if (x0 > 0xffffffff) {
2179 env->cc_src2 = 1;
2180 return 0xffffffff;
2181 } else {
2182 env->cc_src2 = 0;
2183 return x0;
2184 }
2185 }
2186
2187 target_ulong helper_sdiv(target_ulong a, target_ulong b)
2188 {
2189 int64_t x0;
2190 int32_t x1;
2191
2192 x0 = a | ((int64_t) (env->y) << 32);
2193 x1 = b;
2194
2195 if (x1 == 0) {
2196 raise_exception(TT_DIV_ZERO);
2197 }
2198
2199 x0 = x0 / x1;
2200 if ((int32_t) x0 != x0) {
2201 env->cc_src2 = 1;
2202 return x0 < 0? 0x80000000: 0x7fffffff;
2203 } else {
2204 env->cc_src2 = 0;
2205 return x0;
2206 }
2207 }
2208
2209 uint64_t helper_pack64(target_ulong high, target_ulong low)
2210 {
2211 return ((uint64_t)high << 32) | (uint64_t)(low & 0xffffffff);
2212 }
2213
2214 void helper_ldfsr(void)
2215 {
2216 int rnd_mode;
2217
2218 PUT_FSR32(env, *((uint32_t *) &FT0));
2219 switch (env->fsr & FSR_RD_MASK) {
2220 case FSR_RD_NEAREST:
2221 rnd_mode = float_round_nearest_even;
2222 break;
2223 default:
2224 case FSR_RD_ZERO:
2225 rnd_mode = float_round_to_zero;
2226 break;
2227 case FSR_RD_POS:
2228 rnd_mode = float_round_up;
2229 break;
2230 case FSR_RD_NEG:
2231 rnd_mode = float_round_down;
2232 break;
2233 }
2234 set_float_rounding_mode(rnd_mode, &env->fp_status);
2235 }
2236
2237 void helper_stfsr(void)
2238 {
2239 *((uint32_t *) &FT0) = GET_FSR32(env);
2240 }
2241
2242 void helper_debug(void)
2243 {
2244 env->exception_index = EXCP_DEBUG;
2245 cpu_loop_exit();
2246 }
2247
2248 #ifndef TARGET_SPARC64
2249 void helper_wrpsr(target_ulong new_psr)
2250 {
2251 if ((new_psr & PSR_CWP) >= NWINDOWS)
2252 raise_exception(TT_ILL_INSN);
2253 else
2254 PUT_PSR(env, new_psr);
2255 }
2256
2257 target_ulong helper_rdpsr(void)
2258 {
2259 return GET_PSR(env);
2260 }
2261
2262 #else
2263 target_ulong helper_rdccr(void)
2264 {
2265 return GET_CCR(env);
2266 }
2267
2268 void helper_wrccr(target_ulong new_ccr)
2269 {
2270 PUT_CCR(env, new_ccr);
2271 }
2272
2273 // CWP handling is reversed in V9, but we still use the V8 register
2274 // order.
2275 target_ulong helper_rdcwp(void)
2276 {
2277 return GET_CWP64(env);
2278 }
2279
2280 void helper_wrcwp(target_ulong new_cwp)
2281 {
2282 PUT_CWP64(env, new_cwp);
2283 }
2284
2285 // This function uses non-native bit order
2286 #define GET_FIELD(X, FROM, TO) \
2287 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
2288
2289 // This function uses the order in the manuals, i.e. bit 0 is 2^0
2290 #define GET_FIELD_SP(X, FROM, TO) \
2291 GET_FIELD(X, 63 - (TO), 63 - (FROM))
2292
2293 target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
2294 {
2295 return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
2296 (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
2297 (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
2298 (GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
2299 (GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
2300 (GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
2301 (((pixel_addr >> 55) & 1) << 4) |
2302 (GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
2303 GET_FIELD_SP(pixel_addr, 11, 12);
2304 }
2305
2306 target_ulong helper_alignaddr(target_ulong addr, target_ulong offset)
2307 {
2308 uint64_t tmp;
2309
2310 tmp = addr + offset;
2311 env->gsr &= ~7ULL;
2312 env->gsr |= tmp & 7ULL;
2313 return tmp & ~7ULL;
2314 }
2315
2316 target_ulong helper_popc(target_ulong val)
2317 {
2318 return ctpop64(val);
2319 }
2320
2321 static inline uint64_t *get_gregset(uint64_t pstate)
2322 {
2323 switch (pstate) {
2324 default:
2325 case 0:
2326 return env->bgregs;
2327 case PS_AG:
2328 return env->agregs;
2329 case PS_MG:
2330 return env->mgregs;
2331 case PS_IG:
2332 return env->igregs;
2333 }
2334 }
2335
2336 static inline void change_pstate(uint64_t new_pstate)
2337 {
2338 uint64_t pstate_regs, new_pstate_regs;
2339 uint64_t *src, *dst;
2340
2341 pstate_regs = env->pstate & 0xc01;
2342 new_pstate_regs = new_pstate & 0xc01;
2343 if (new_pstate_regs != pstate_regs) {
2344 // Switch global register bank
2345 src = get_gregset(new_pstate_regs);
2346 dst = get_gregset(pstate_regs);
2347 memcpy32(dst, env->gregs);
2348 memcpy32(env->gregs, src);
2349 }
2350 env->pstate = new_pstate;
2351 }
2352
2353 void helper_wrpstate(target_ulong new_state)
2354 {
2355 change_pstate(new_state & 0xf3f);
2356 }
2357
2358 void helper_done(void)
2359 {
2360 env->tl--;
2361 env->tsptr = &env->ts[env->tl];
2362 env->pc = env->tsptr->tpc;
2363 env->npc = env->tsptr->tnpc + 4;
2364 PUT_CCR(env, env->tsptr->tstate >> 32);
2365 env->asi = (env->tsptr->tstate >> 24) & 0xff;
2366 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2367 PUT_CWP64(env, env->tsptr->tstate & 0xff);
2368 }
2369
2370 void helper_retry(void)
2371 {
2372 env->tl--;
2373 env->tsptr = &env->ts[env->tl];
2374 env->pc = env->tsptr->tpc;
2375 env->npc = env->tsptr->tnpc;
2376 PUT_CCR(env, env->tsptr->tstate >> 32);
2377 env->asi = (env->tsptr->tstate >> 24) & 0xff;
2378 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2379 PUT_CWP64(env, env->tsptr->tstate & 0xff);
2380 }
2381 #endif
2382
2383 void set_cwp(int new_cwp)
2384 {
2385 /* put the modified wrap registers at their proper location */
2386 if (env->cwp == (NWINDOWS - 1))
2387 memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
2388 env->cwp = new_cwp;
2389 /* put the wrap registers at their temporary location */
2390 if (new_cwp == (NWINDOWS - 1))
2391 memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
2392 env->regwptr = env->regbase + (new_cwp * 16);
2393 REGWPTR = env->regwptr;
2394 }
2395
2396 void cpu_set_cwp(CPUState *env1, int new_cwp)
2397 {
2398 CPUState *saved_env;
2399 #ifdef reg_REGWPTR
2400 target_ulong *saved_regwptr;
2401 #endif
2402
2403 saved_env = env;
2404 #ifdef reg_REGWPTR
2405 saved_regwptr = REGWPTR;
2406 #endif
2407 env = env1;
2408 set_cwp(new_cwp);
2409 env = saved_env;
2410 #ifdef reg_REGWPTR
2411 REGWPTR = saved_regwptr;
2412 #endif
2413 }
2414
2415 #ifdef TARGET_SPARC64
2416 #ifdef DEBUG_PCALL
2417 static const char * const excp_names[0x50] = {
2418 [TT_TFAULT] = "Instruction Access Fault",
2419 [TT_TMISS] = "Instruction Access MMU Miss",
2420 [TT_CODE_ACCESS] = "Instruction Access Error",
2421 [TT_ILL_INSN] = "Illegal Instruction",
2422 [TT_PRIV_INSN] = "Privileged Instruction",
2423 [TT_NFPU_INSN] = "FPU Disabled",
2424 [TT_FP_EXCP] = "FPU Exception",
2425 [TT_TOVF] = "Tag Overflow",
2426 [TT_CLRWIN] = "Clean Windows",
2427 [TT_DIV_ZERO] = "Division By Zero",
2428 [TT_DFAULT] = "Data Access Fault",
2429 [TT_DMISS] = "Data Access MMU Miss",
2430 [TT_DATA_ACCESS] = "Data Access Error",
2431 [TT_DPROT] = "Data Protection Error",
2432 [TT_UNALIGNED] = "Unaligned Memory Access",
2433 [TT_PRIV_ACT] = "Privileged Action",
2434 [TT_EXTINT | 0x1] = "External Interrupt 1",
2435 [TT_EXTINT | 0x2] = "External Interrupt 2",
2436 [TT_EXTINT | 0x3] = "External Interrupt 3",
2437 [TT_EXTINT | 0x4] = "External Interrupt 4",
2438 [TT_EXTINT | 0x5] = "External Interrupt 5",
2439 [TT_EXTINT | 0x6] = "External Interrupt 6",
2440 [TT_EXTINT | 0x7] = "External Interrupt 7",
2441 [TT_EXTINT | 0x8] = "External Interrupt 8",
2442 [TT_EXTINT | 0x9] = "External Interrupt 9",
2443 [TT_EXTINT | 0xa] = "External Interrupt 10",
2444 [TT_EXTINT | 0xb] = "External Interrupt 11",
2445 [TT_EXTINT | 0xc] = "External Interrupt 12",
2446 [TT_EXTINT | 0xd] = "External Interrupt 13",
2447 [TT_EXTINT | 0xe] = "External Interrupt 14",
2448 [TT_EXTINT | 0xf] = "External Interrupt 15",
2449 };
2450 #endif
2451
2452 void do_interrupt(int intno)
2453 {
2454 #ifdef DEBUG_PCALL
2455 if (loglevel & CPU_LOG_INT) {
2456 static int count;
2457 const char *name;
2458
2459 if (intno < 0 || intno >= 0x180 || (intno > 0x4f && intno < 0x80))
2460 name = "Unknown";
2461 else if (intno >= 0x100)
2462 name = "Trap Instruction";
2463 else if (intno >= 0xc0)
2464 name = "Window Fill";
2465 else if (intno >= 0x80)
2466 name = "Window Spill";
2467 else {
2468 name = excp_names[intno];
2469 if (!name)
2470 name = "Unknown";
2471 }
2472
2473 fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
2474 " SP=%016" PRIx64 "\n",
2475 count, name, intno,
2476 env->pc,
2477 env->npc, env->regwptr[6]);
2478 cpu_dump_state(env, logfile, fprintf, 0);
2479 #if 0
2480 {
2481 int i;
2482 uint8_t *ptr;
2483
2484 fprintf(logfile, " code=");
2485 ptr = (uint8_t *)env->pc;
2486 for(i = 0; i < 16; i++) {
2487 fprintf(logfile, " %02x", ldub(ptr + i));
2488 }
2489 fprintf(logfile, "\n");
2490 }
2491 #endif
2492 count++;
2493 }
2494 #endif
2495 #if !defined(CONFIG_USER_ONLY)
2496 if (env->tl == MAXTL) {
2497 cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
2498 return;
2499 }
2500 #endif
2501 env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
2502 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
2503 GET_CWP64(env);
2504 env->tsptr->tpc = env->pc;
2505 env->tsptr->tnpc = env->npc;
2506 env->tsptr->tt = intno;
2507 change_pstate(PS_PEF | PS_PRIV | PS_AG);
2508
2509 if (intno == TT_CLRWIN)
2510 set_cwp((env->cwp - 1) & (NWINDOWS - 1));
2511 else if ((intno & 0x1c0) == TT_SPILL)
2512 set_cwp((env->cwp - env->cansave - 2) & (NWINDOWS - 1));
2513 else if ((intno & 0x1c0) == TT_FILL)
2514 set_cwp((env->cwp + 1) & (NWINDOWS - 1));
2515 env->tbr &= ~0x7fffULL;
2516 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
2517 if (env->tl < MAXTL - 1) {
2518 env->tl++;
2519 } else {
2520 env->pstate |= PS_RED;
2521 if (env->tl != MAXTL)
2522 env->tl++;
2523 }
2524 env->tsptr = &env->ts[env->tl];
2525 env->pc = env->tbr;
2526 env->npc = env->pc + 4;
2527 env->exception_index = 0;
2528 }
2529 #else
2530 #ifdef DEBUG_PCALL
2531 static const char * const excp_names[0x80] = {
2532 [TT_TFAULT] = "Instruction Access Fault",
2533 [TT_ILL_INSN] = "Illegal Instruction",
2534 [TT_PRIV_INSN] = "Privileged Instruction",
2535 [TT_NFPU_INSN] = "FPU Disabled",
2536 [TT_WIN_OVF] = "Window Overflow",
2537 [TT_WIN_UNF] = "Window Underflow",
2538 [TT_UNALIGNED] = "Unaligned Memory Access",
2539 [TT_FP_EXCP] = "FPU Exception",
2540 [TT_DFAULT] = "Data Access Fault",
2541 [TT_TOVF] = "Tag Overflow",
2542 [TT_EXTINT | 0x1] = "External Interrupt 1",
2543 [TT_EXTINT | 0x2] = "External Interrupt 2",
2544 [TT_EXTINT | 0x3] = "External Interrupt 3",
2545 [TT_EXTINT | 0x4] = "External Interrupt 4",
2546 [TT_EXTINT | 0x5] = "External Interrupt 5",
2547 [TT_EXTINT | 0x6] = "External Interrupt 6",
2548 [TT_EXTINT | 0x7] = "External Interrupt 7",
2549 [TT_EXTINT | 0x8] = "External Interrupt 8",
2550 [TT_EXTINT | 0x9] = "External Interrupt 9",
2551 [TT_EXTINT | 0xa] = "External Interrupt 10",
2552 [TT_EXTINT | 0xb] = "External Interrupt 11",
2553 [TT_EXTINT | 0xc] = "External Interrupt 12",
2554 [TT_EXTINT | 0xd] = "External Interrupt 13",
2555 [TT_EXTINT | 0xe] = "External Interrupt 14",
2556 [TT_EXTINT | 0xf] = "External Interrupt 15",
2557 [TT_TOVF] = "Tag Overflow",
2558 [TT_CODE_ACCESS] = "Instruction Access Error",
2559 [TT_DATA_ACCESS] = "Data Access Error",
2560 [TT_DIV_ZERO] = "Division By Zero",
2561 [TT_NCP_INSN] = "Coprocessor Disabled",
2562 };
2563 #endif
2564
2565 void do_interrupt(int intno)
2566 {
2567 int cwp;
2568
2569 #ifdef DEBUG_PCALL
2570 if (loglevel & CPU_LOG_INT) {
2571 static int count;
2572 const char *name;
2573
2574 if (intno < 0 || intno >= 0x100)
2575 name = "Unknown";
2576 else if (intno >= 0x80)
2577 name = "Trap Instruction";
2578 else {
2579 name = excp_names[intno];
2580 if (!name)
2581 name = "Unknown";
2582 }
2583
2584 fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
2585 count, name, intno,
2586 env->pc,
2587 env->npc, env->regwptr[6]);
2588 cpu_dump_state(env, logfile, fprintf, 0);
2589 #if 0
2590 {
2591 int i;
2592 uint8_t *ptr;
2593
2594 fprintf(logfile, " code=");
2595 ptr = (uint8_t *)env->pc;
2596 for(i = 0; i < 16; i++) {
2597 fprintf(logfile, " %02x", ldub(ptr + i));
2598 }
2599 fprintf(logfile, "\n");
2600 }
2601 #endif
2602 count++;
2603 }
2604 #endif
2605 #if !defined(CONFIG_USER_ONLY)
2606 if (env->psret == 0) {
2607 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
2608 return;
2609 }
2610 #endif
2611 env->psret = 0;
2612 cwp = (env->cwp - 1) & (NWINDOWS - 1);
2613 set_cwp(cwp);
2614 env->regwptr[9] = env->pc;
2615 env->regwptr[10] = env->npc;
2616 env->psrps = env->psrs;
2617 env->psrs = 1;
2618 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
2619 env->pc = env->tbr;
2620 env->npc = env->pc + 4;
2621 env->exception_index = 0;
2622 }
2623 #endif
2624
2625 #if !defined(CONFIG_USER_ONLY)
2626
2627 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
2628 void *retaddr);
2629
2630 #define MMUSUFFIX _mmu
2631 #define ALIGNED_ONLY
2632 #ifdef __s390__
2633 # define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
2634 #else
2635 # define GETPC() (__builtin_return_address(0))
2636 #endif
2637
2638 #define SHIFT 0
2639 #include "softmmu_template.h"
2640
2641 #define SHIFT 1
2642 #include "softmmu_template.h"
2643
2644 #define SHIFT 2
2645 #include "softmmu_template.h"
2646
2647 #define SHIFT 3
2648 #include "softmmu_template.h"
2649
2650 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
2651 void *retaddr)
2652 {
2653 #ifdef DEBUG_UNALIGNED
2654 printf("Unaligned access to 0x%x from 0x%x\n", addr, env->pc);
2655 #endif
2656 raise_exception(TT_UNALIGNED);
2657 }
2658
2659 /* try to fill the TLB and return an exception if error. If retaddr is
2660 NULL, it means that the function was called in C code (i.e. not
2661 from generated code or from helper.c) */
2662 /* XXX: fix it to restore all registers */
2663 void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2664 {
2665 TranslationBlock *tb;
2666 int ret;
2667 unsigned long pc;
2668 CPUState *saved_env;
2669
2670 /* XXX: hack to restore env in all cases, even if not called from
2671 generated code */
2672 saved_env = env;
2673 env = cpu_single_env;
2674
2675 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2676 if (ret) {
2677 if (retaddr) {
2678 /* now we have a real cpu fault */
2679 pc = (unsigned long)retaddr;
2680 tb = tb_find_pc(pc);
2681 if (tb) {
2682 /* the PC is inside the translated code. It means that we have
2683 a virtual CPU fault */
2684 cpu_restore_state(tb, env, pc, (void *)T2);
2685 }
2686 }
2687 cpu_loop_exit();
2688 }
2689 env = saved_env;
2690 }
2691
2692 #endif
2693
2694 #ifndef TARGET_SPARC64
2695 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
2696 int is_asi)
2697 {
2698 CPUState *saved_env;
2699
2700 /* XXX: hack to restore env in all cases, even if not called from
2701 generated code */
2702 saved_env = env;
2703 env = cpu_single_env;
2704 #ifdef DEBUG_UNASSIGNED
2705 if (is_asi)
2706 printf("Unassigned mem %s access to " TARGET_FMT_plx " asi 0x%02x from "
2707 TARGET_FMT_lx "\n",
2708 is_exec ? "exec" : is_write ? "write" : "read", addr, is_asi,
2709 env->pc);
2710 else
2711 printf("Unassigned mem %s access to " TARGET_FMT_plx " from "
2712 TARGET_FMT_lx "\n",
2713 is_exec ? "exec" : is_write ? "write" : "read", addr, env->pc);
2714 #endif
2715 if (env->mmuregs[3]) /* Fault status register */
2716 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
2717 if (is_asi)
2718 env->mmuregs[3] |= 1 << 16;
2719 if (env->psrs)
2720 env->mmuregs[3] |= 1 << 5;
2721 if (is_exec)
2722 env->mmuregs[3] |= 1 << 6;
2723 if (is_write)
2724 env->mmuregs[3] |= 1 << 7;
2725 env->mmuregs[3] |= (5 << 2) | 2;
2726 env->mmuregs[4] = addr; /* Fault address register */
2727 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
2728 if (is_exec)
2729 raise_exception(TT_CODE_ACCESS);
2730 else
2731 raise_exception(TT_DATA_ACCESS);
2732 }
2733 env = saved_env;
2734 }
2735 #else
2736 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
2737 int is_asi)
2738 {
2739 #ifdef DEBUG_UNASSIGNED
2740 CPUState *saved_env;
2741
2742 /* XXX: hack to restore env in all cases, even if not called from
2743 generated code */
2744 saved_env = env;
2745 env = cpu_single_env;
2746 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n",
2747 addr, env->pc);
2748 env = saved_env;
2749 #endif
2750 if (is_exec)
2751 raise_exception(TT_CODE_ACCESS);
2752 else
2753 raise_exception(TT_DATA_ACCESS);
2754 }
2755 #endif
2756
Qemu copy for testing