]>
git.proxmox.com Git - qemu.git/blob - target-sparc/op_helper.c
2 #include "host-utils.h"
7 //#define DEBUG_UNALIGNED
8 //#define DEBUG_UNASSIGNED
11 //#define DEBUG_PSTATE
14 #define DPRINTF_MMU(fmt, ...) \
15 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
17 #define DPRINTF_MMU(fmt, ...) do {} while (0)
21 #define DPRINTF_MXCC(fmt, ...) \
22 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
24 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
28 #define DPRINTF_ASI(fmt, ...) \
29 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
33 #define DPRINTF_PSTATE(fmt, ...) \
34 do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
36 #define DPRINTF_PSTATE(fmt, ...) do {} while (0)
41 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
43 #define AM_CHECK(env1) (1)
47 #if defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
48 static void do_unassigned_access(target_ulong addr
, int is_write
, int is_exec
,
49 int is_asi
, int size
);
52 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
53 // Calculates TSB pointer value for fault page size 8k or 64k
54 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register
,
55 uint64_t tag_access_register
,
58 uint64_t tsb_base
= tsb_register
& ~0x1fffULL
;
59 int tsb_split
= (tsb_register
& 0x1000ULL
) ? 1 : 0;
60 int tsb_size
= tsb_register
& 0xf;
62 // discard lower 13 bits which hold tag access context
63 uint64_t tag_access_va
= tag_access_register
& ~0x1fffULL
;
66 uint64_t tsb_base_mask
= ~0x1fffULL
;
67 uint64_t va
= tag_access_va
;
69 // move va bits to correct position
70 if (page_size
== 8*1024) {
72 } else if (page_size
== 64*1024) {
77 tsb_base_mask
<<= tsb_size
;
80 // calculate tsb_base mask and adjust va if split is in use
82 if (page_size
== 8*1024) {
83 va
&= ~(1ULL << (13 + tsb_size
));
84 } else if (page_size
== 64*1024) {
85 va
|= (1ULL << (13 + tsb_size
));
90 return ((tsb_base
& tsb_base_mask
) | (va
& ~tsb_base_mask
)) & ~0xfULL
;
93 // Calculates tag target register value by reordering bits
94 // in tag access register
95 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register
)
97 return ((tag_access_register
& 0x1fff) << 48) | (tag_access_register
>> 22);
100 static void replace_tlb_entry(SparcTLBEntry
*tlb
,
101 uint64_t tlb_tag
, uint64_t tlb_tte
,
104 target_ulong mask
, size
, va
, offset
;
106 // flush page range if translation is valid
107 if (TTE_IS_VALID(tlb
->tte
)) {
109 mask
= 0xffffffffffffe000ULL
;
110 mask
<<= 3 * ((tlb
->tte
>> 61) & 3);
113 va
= tlb
->tag
& mask
;
115 for (offset
= 0; offset
< size
; offset
+= TARGET_PAGE_SIZE
) {
116 tlb_flush_page(env1
, va
+ offset
);
124 static void demap_tlb(SparcTLBEntry
*tlb
, target_ulong demap_addr
,
125 const char* strmmu
, CPUState
*env1
)
131 int is_demap_context
= (demap_addr
>> 6) & 1;
134 switch ((demap_addr
>> 4) & 3) {
136 context
= env1
->dmmu
.mmu_primary_context
;
139 context
= env1
->dmmu
.mmu_secondary_context
;
149 for (i
= 0; i
< 64; i
++) {
150 if (TTE_IS_VALID(tlb
[i
].tte
)) {
152 if (is_demap_context
) {
153 // will remove non-global entries matching context value
154 if (TTE_IS_GLOBAL(tlb
[i
].tte
) ||
155 !tlb_compare_context(&tlb
[i
], context
)) {
160 // will remove any entry matching VA
161 mask
= 0xffffffffffffe000ULL
;
162 mask
<<= 3 * ((tlb
[i
].tte
>> 61) & 3);
164 if (!compare_masked(demap_addr
, tlb
[i
].tag
, mask
)) {
168 // entry should be global or matching context value
169 if (!TTE_IS_GLOBAL(tlb
[i
].tte
) &&
170 !tlb_compare_context(&tlb
[i
], context
)) {
175 replace_tlb_entry(&tlb
[i
], 0, 0, env1
);
177 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu
, i
);
184 static void replace_tlb_1bit_lru(SparcTLBEntry
*tlb
,
185 uint64_t tlb_tag
, uint64_t tlb_tte
,
186 const char* strmmu
, CPUState
*env1
)
188 unsigned int i
, replace_used
;
190 // Try replacing invalid entry
191 for (i
= 0; i
< 64; i
++) {
192 if (!TTE_IS_VALID(tlb
[i
].tte
)) {
193 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
195 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu
, i
);
202 // All entries are valid, try replacing unlocked entry
204 for (replace_used
= 0; replace_used
< 2; ++replace_used
) {
206 // Used entries are not replaced on first pass
208 for (i
= 0; i
< 64; i
++) {
209 if (!TTE_IS_LOCKED(tlb
[i
].tte
) && !TTE_IS_USED(tlb
[i
].tte
)) {
211 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
213 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
214 strmmu
, (replace_used
?"used":"unused"), i
);
221 // Now reset used bit and search for unused entries again
223 for (i
= 0; i
< 64; i
++) {
224 TTE_SET_UNUSED(tlb
[i
].tte
);
229 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu
);
236 static inline target_ulong
address_mask(CPUState
*env1
, target_ulong addr
)
238 #ifdef TARGET_SPARC64
240 addr
&= 0xffffffffULL
;
245 static void raise_exception(int tt
)
247 env
->exception_index
= tt
;
251 void HELPER(raise_exception
)(int tt
)
256 void helper_check_align(target_ulong addr
, uint32_t align
)
259 #ifdef DEBUG_UNALIGNED
260 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
261 "\n", addr
, env
->pc
);
263 raise_exception(TT_UNALIGNED
);
267 #define F_HELPER(name, p) void helper_f##name##p(void)
269 #define F_BINOP(name) \
270 float32 helper_f ## name ## s (float32 src1, float32 src2) \
272 return float32_ ## name (src1, src2, &env->fp_status); \
276 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
280 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
289 void helper_fsmuld(float32 src1
, float32 src2
)
291 DT0
= float64_mul(float32_to_float64(src1
, &env
->fp_status
),
292 float32_to_float64(src2
, &env
->fp_status
),
296 void helper_fdmulq(void)
298 QT0
= float128_mul(float64_to_float128(DT0
, &env
->fp_status
),
299 float64_to_float128(DT1
, &env
->fp_status
),
303 float32
helper_fnegs(float32 src
)
305 return float32_chs(src
);
308 #ifdef TARGET_SPARC64
311 DT0
= float64_chs(DT1
);
316 QT0
= float128_chs(QT1
);
320 /* Integer to float conversion. */
321 float32
helper_fitos(int32_t src
)
323 return int32_to_float32(src
, &env
->fp_status
);
326 void helper_fitod(int32_t src
)
328 DT0
= int32_to_float64(src
, &env
->fp_status
);
331 void helper_fitoq(int32_t src
)
333 QT0
= int32_to_float128(src
, &env
->fp_status
);
336 #ifdef TARGET_SPARC64
337 float32
helper_fxtos(void)
339 return int64_to_float32(*((int64_t *)&DT1
), &env
->fp_status
);
344 DT0
= int64_to_float64(*((int64_t *)&DT1
), &env
->fp_status
);
349 QT0
= int64_to_float128(*((int64_t *)&DT1
), &env
->fp_status
);
354 /* floating point conversion */
355 float32
helper_fdtos(void)
357 return float64_to_float32(DT1
, &env
->fp_status
);
360 void helper_fstod(float32 src
)
362 DT0
= float32_to_float64(src
, &env
->fp_status
);
365 float32
helper_fqtos(void)
367 return float128_to_float32(QT1
, &env
->fp_status
);
370 void helper_fstoq(float32 src
)
372 QT0
= float32_to_float128(src
, &env
->fp_status
);
375 void helper_fqtod(void)
377 DT0
= float128_to_float64(QT1
, &env
->fp_status
);
380 void helper_fdtoq(void)
382 QT0
= float64_to_float128(DT1
, &env
->fp_status
);
385 /* Float to integer conversion. */
386 int32_t helper_fstoi(float32 src
)
388 return float32_to_int32_round_to_zero(src
, &env
->fp_status
);
391 int32_t helper_fdtoi(void)
393 return float64_to_int32_round_to_zero(DT1
, &env
->fp_status
);
396 int32_t helper_fqtoi(void)
398 return float128_to_int32_round_to_zero(QT1
, &env
->fp_status
);
401 #ifdef TARGET_SPARC64
402 void helper_fstox(float32 src
)
404 *((int64_t *)&DT0
) = float32_to_int64_round_to_zero(src
, &env
->fp_status
);
407 void helper_fdtox(void)
409 *((int64_t *)&DT0
) = float64_to_int64_round_to_zero(DT1
, &env
->fp_status
);
412 void helper_fqtox(void)
414 *((int64_t *)&DT0
) = float128_to_int64_round_to_zero(QT1
, &env
->fp_status
);
417 void helper_faligndata(void)
421 tmp
= (*((uint64_t *)&DT0
)) << ((env
->gsr
& 7) * 8);
422 /* on many architectures a shift of 64 does nothing */
423 if ((env
->gsr
& 7) != 0) {
424 tmp
|= (*((uint64_t *)&DT1
)) >> (64 - (env
->gsr
& 7) * 8);
426 *((uint64_t *)&DT0
) = tmp
;
429 #ifdef HOST_WORDS_BIGENDIAN
430 #define VIS_B64(n) b[7 - (n)]
431 #define VIS_W64(n) w[3 - (n)]
432 #define VIS_SW64(n) sw[3 - (n)]
433 #define VIS_L64(n) l[1 - (n)]
434 #define VIS_B32(n) b[3 - (n)]
435 #define VIS_W32(n) w[1 - (n)]
437 #define VIS_B64(n) b[n]
438 #define VIS_W64(n) w[n]
439 #define VIS_SW64(n) sw[n]
440 #define VIS_L64(n) l[n]
441 #define VIS_B32(n) b[n]
442 #define VIS_W32(n) w[n]
460 void helper_fpmerge(void)
467 // Reverse calculation order to handle overlap
468 d
.VIS_B64(7) = s
.VIS_B64(3);
469 d
.VIS_B64(6) = d
.VIS_B64(3);
470 d
.VIS_B64(5) = s
.VIS_B64(2);
471 d
.VIS_B64(4) = d
.VIS_B64(2);
472 d
.VIS_B64(3) = s
.VIS_B64(1);
473 d
.VIS_B64(2) = d
.VIS_B64(1);
474 d
.VIS_B64(1) = s
.VIS_B64(0);
475 //d.VIS_B64(0) = d.VIS_B64(0);
480 void helper_fmul8x16(void)
489 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
490 if ((tmp & 0xff) > 0x7f) \
492 d.VIS_W64(r) = tmp >> 8;
503 void helper_fmul8x16al(void)
512 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
513 if ((tmp & 0xff) > 0x7f) \
515 d.VIS_W64(r) = tmp >> 8;
526 void helper_fmul8x16au(void)
535 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
536 if ((tmp & 0xff) > 0x7f) \
538 d.VIS_W64(r) = tmp >> 8;
549 void helper_fmul8sux16(void)
558 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
559 if ((tmp & 0xff) > 0x7f) \
561 d.VIS_W64(r) = tmp >> 8;
572 void helper_fmul8ulx16(void)
581 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
582 if ((tmp & 0xff) > 0x7f) \
584 d.VIS_W64(r) = tmp >> 8;
595 void helper_fmuld8sux16(void)
604 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
605 if ((tmp & 0xff) > 0x7f) \
609 // Reverse calculation order to handle overlap
617 void helper_fmuld8ulx16(void)
626 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
627 if ((tmp & 0xff) > 0x7f) \
631 // Reverse calculation order to handle overlap
639 void helper_fexpand(void)
644 s
.l
= (uint32_t)(*(uint64_t *)&DT0
& 0xffffffff);
646 d
.VIS_W64(0) = s
.VIS_B32(0) << 4;
647 d
.VIS_W64(1) = s
.VIS_B32(1) << 4;
648 d
.VIS_W64(2) = s
.VIS_B32(2) << 4;
649 d
.VIS_W64(3) = s
.VIS_B32(3) << 4;
654 #define VIS_HELPER(name, F) \
655 void name##16(void) \
662 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
663 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
664 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
665 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
670 uint32_t name##16s(uint32_t src1, uint32_t src2) \
677 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
678 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
683 void name##32(void) \
690 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
691 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
696 uint32_t name##32s(uint32_t src1, uint32_t src2) \
708 #define FADD(a, b) ((a) + (b))
709 #define FSUB(a, b) ((a) - (b))
710 VIS_HELPER(helper_fpadd
, FADD
)
711 VIS_HELPER(helper_fpsub
, FSUB
)
713 #define VIS_CMPHELPER(name, F) \
714 void name##16(void) \
721 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
722 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
723 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
724 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
729 void name##32(void) \
736 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
737 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
742 #define FCMPGT(a, b) ((a) > (b))
743 #define FCMPEQ(a, b) ((a) == (b))
744 #define FCMPLE(a, b) ((a) <= (b))
745 #define FCMPNE(a, b) ((a) != (b))
747 VIS_CMPHELPER(helper_fcmpgt
, FCMPGT
)
748 VIS_CMPHELPER(helper_fcmpeq
, FCMPEQ
)
749 VIS_CMPHELPER(helper_fcmple
, FCMPLE
)
750 VIS_CMPHELPER(helper_fcmpne
, FCMPNE
)
753 void helper_check_ieee_exceptions(void)
757 status
= get_float_exception_flags(&env
->fp_status
);
759 /* Copy IEEE 754 flags into FSR */
760 if (status
& float_flag_invalid
)
762 if (status
& float_flag_overflow
)
764 if (status
& float_flag_underflow
)
766 if (status
& float_flag_divbyzero
)
768 if (status
& float_flag_inexact
)
771 if ((env
->fsr
& FSR_CEXC_MASK
) & ((env
->fsr
& FSR_TEM_MASK
) >> 23)) {
772 /* Unmasked exception, generate a trap */
773 env
->fsr
|= FSR_FTT_IEEE_EXCP
;
774 raise_exception(TT_FP_EXCP
);
776 /* Accumulate exceptions */
777 env
->fsr
|= (env
->fsr
& FSR_CEXC_MASK
) << 5;
782 void helper_clear_float_exceptions(void)
784 set_float_exception_flags(0, &env
->fp_status
);
787 float32
helper_fabss(float32 src
)
789 return float32_abs(src
);
792 #ifdef TARGET_SPARC64
793 void helper_fabsd(void)
795 DT0
= float64_abs(DT1
);
798 void helper_fabsq(void)
800 QT0
= float128_abs(QT1
);
804 float32
helper_fsqrts(float32 src
)
806 return float32_sqrt(src
, &env
->fp_status
);
809 void helper_fsqrtd(void)
811 DT0
= float64_sqrt(DT1
, &env
->fp_status
);
814 void helper_fsqrtq(void)
816 QT0
= float128_sqrt(QT1
, &env
->fp_status
);
819 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
820 void glue(helper_, name) (void) \
822 target_ulong new_fsr; \
824 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
825 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
826 case float_relation_unordered: \
827 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
828 if ((env->fsr & FSR_NVM) || TRAP) { \
829 env->fsr |= new_fsr; \
830 env->fsr |= FSR_NVC; \
831 env->fsr |= FSR_FTT_IEEE_EXCP; \
832 raise_exception(TT_FP_EXCP); \
834 env->fsr |= FSR_NVA; \
837 case float_relation_less: \
838 new_fsr = FSR_FCC0 << FS; \
840 case float_relation_greater: \
841 new_fsr = FSR_FCC1 << FS; \
847 env->fsr |= new_fsr; \
849 #define GEN_FCMPS(name, size, FS, TRAP) \
850 void glue(helper_, name)(float32 src1, float32 src2) \
852 target_ulong new_fsr; \
854 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
855 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
856 case float_relation_unordered: \
857 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
858 if ((env->fsr & FSR_NVM) || TRAP) { \
859 env->fsr |= new_fsr; \
860 env->fsr |= FSR_NVC; \
861 env->fsr |= FSR_FTT_IEEE_EXCP; \
862 raise_exception(TT_FP_EXCP); \
864 env->fsr |= FSR_NVA; \
867 case float_relation_less: \
868 new_fsr = FSR_FCC0 << FS; \
870 case float_relation_greater: \
871 new_fsr = FSR_FCC1 << FS; \
877 env->fsr |= new_fsr; \
880 GEN_FCMPS(fcmps
, float32
, 0, 0);
881 GEN_FCMP(fcmpd
, float64
, DT0
, DT1
, 0, 0);
883 GEN_FCMPS(fcmpes
, float32
, 0, 1);
884 GEN_FCMP(fcmped
, float64
, DT0
, DT1
, 0, 1);
886 GEN_FCMP(fcmpq
, float128
, QT0
, QT1
, 0, 0);
887 GEN_FCMP(fcmpeq
, float128
, QT0
, QT1
, 0, 1);
889 static uint32_t compute_all_flags(void)
891 return env
->psr
& PSR_ICC
;
894 static uint32_t compute_C_flags(void)
896 return env
->psr
& PSR_CARRY
;
899 static inline uint32_t get_NZ_icc(target_ulong dst
)
903 if (!(dst
& 0xffffffffULL
))
905 if ((int32_t) (dst
& 0xffffffffULL
) < 0)
910 #ifdef TARGET_SPARC64
911 static uint32_t compute_all_flags_xcc(void)
913 return env
->xcc
& PSR_ICC
;
916 static uint32_t compute_C_flags_xcc(void)
918 return env
->xcc
& PSR_CARRY
;
921 static inline uint32_t get_NZ_xcc(target_ulong dst
)
927 if ((int64_t)dst
< 0)
933 static inline uint32_t get_V_div_icc(target_ulong src2
)
942 static uint32_t compute_all_div(void)
946 ret
= get_NZ_icc(CC_DST
);
947 ret
|= get_V_div_icc(CC_SRC2
);
951 static uint32_t compute_C_div(void)
956 /* carry = (src1[31] & src2[31]) | ( ~dst[31] & (src1[31] | src2[31])) */
957 static inline uint32_t get_C_add_icc(target_ulong dst
, target_ulong src1
,
962 if (((src1
& (1ULL << 31)) & (src2
& (1ULL << 31)))
963 | ((~(dst
& (1ULL << 31)))
964 & ((src1
& (1ULL << 31)) | (src2
& (1ULL << 31)))))
969 static inline uint32_t get_V_add_icc(target_ulong dst
, target_ulong src1
,
974 if (((src1
^ src2
^ -1) & (src1
^ dst
)) & (1ULL << 31))
979 #ifdef TARGET_SPARC64
980 static inline uint32_t get_C_add_xcc(target_ulong dst
, target_ulong src1
)
989 static inline uint32_t get_V_add_xcc(target_ulong dst
, target_ulong src1
,
994 if (((src1
^ src2
^ -1) & (src1
^ dst
)) & (1ULL << 63))
999 static uint32_t compute_all_add_xcc(void)
1003 ret
= get_NZ_xcc(CC_DST
);
1004 ret
|= get_C_add_xcc(CC_DST
, CC_SRC
);
1005 ret
|= get_V_add_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1009 static uint32_t compute_C_add_xcc(void)
1011 return get_C_add_xcc(CC_DST
, CC_SRC
);
1015 static uint32_t compute_all_add(void)
1019 ret
= get_NZ_icc(CC_DST
);
1020 ret
|= get_C_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1021 ret
|= get_V_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1025 static uint32_t compute_C_add(void)
1027 return get_C_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1030 #ifdef TARGET_SPARC64
1031 static uint32_t compute_all_addx_xcc(void)
1035 ret
= get_NZ_xcc(CC_DST
);
1036 ret
|= get_C_add_xcc(CC_DST
- CC_SRC2
, CC_SRC
);
1037 ret
|= get_C_add_xcc(CC_DST
, CC_SRC
);
1038 ret
|= get_V_add_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1042 static uint32_t compute_C_addx_xcc(void)
1046 ret
= get_C_add_xcc(CC_DST
- CC_SRC2
, CC_SRC
);
1047 ret
|= get_C_add_xcc(CC_DST
, CC_SRC
);
1052 static inline uint32_t get_V_tag_icc(target_ulong src1
, target_ulong src2
)
1056 if ((src1
| src2
) & 0x3)
1061 static uint32_t compute_all_tadd(void)
1065 ret
= get_NZ_icc(CC_DST
);
1066 ret
|= get_C_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1067 ret
|= get_V_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1068 ret
|= get_V_tag_icc(CC_SRC
, CC_SRC2
);
1072 static uint32_t compute_C_tadd(void)
1074 return get_C_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1077 static uint32_t compute_all_taddtv(void)
1081 ret
= get_NZ_icc(CC_DST
);
1082 ret
|= get_C_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1086 static uint32_t compute_C_taddtv(void)
1088 return get_C_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1091 /* carry = (~src1[31] & src2[31]) | ( dst[31] & (~src1[31] | src2[31])) */
1092 static inline uint32_t get_C_sub_icc(target_ulong dst
, target_ulong src1
,
1097 if (((~(src1
& (1ULL << 31))) & (src2
& (1ULL << 31)))
1098 | ((dst
& (1ULL << 31)) & (( ~(src1
& (1ULL << 31)))
1099 | (src2
& (1ULL << 31)))))
1104 static inline uint32_t get_V_sub_icc(target_ulong dst
, target_ulong src1
,
1109 if (((src1
^ src2
) & (src1
^ dst
)) & (1ULL << 31))
1115 #ifdef TARGET_SPARC64
1116 static inline uint32_t get_C_sub_xcc(target_ulong src1
, target_ulong src2
)
1125 static inline uint32_t get_V_sub_xcc(target_ulong dst
, target_ulong src1
,
1130 if (((src1
^ src2
) & (src1
^ dst
)) & (1ULL << 63))
1135 static uint32_t compute_all_sub_xcc(void)
1139 ret
= get_NZ_xcc(CC_DST
);
1140 ret
|= get_C_sub_xcc(CC_SRC
, CC_SRC2
);
1141 ret
|= get_V_sub_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1145 static uint32_t compute_C_sub_xcc(void)
1147 return get_C_sub_xcc(CC_SRC
, CC_SRC2
);
1151 static uint32_t compute_all_sub(void)
1155 ret
= get_NZ_icc(CC_DST
);
1156 ret
|= get_C_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1157 ret
|= get_V_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1161 static uint32_t compute_C_sub(void)
1163 return get_C_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1166 #ifdef TARGET_SPARC64
1167 static uint32_t compute_all_subx_xcc(void)
1171 ret
= get_NZ_xcc(CC_DST
);
1172 ret
|= get_C_sub_xcc(CC_DST
- CC_SRC2
, CC_SRC
);
1173 ret
|= get_C_sub_xcc(CC_DST
, CC_SRC2
);
1174 ret
|= get_V_sub_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1178 static uint32_t compute_C_subx_xcc(void)
1182 ret
= get_C_sub_xcc(CC_DST
- CC_SRC2
, CC_SRC
);
1183 ret
|= get_C_sub_xcc(CC_DST
, CC_SRC2
);
1188 static uint32_t compute_all_tsub(void)
1192 ret
= get_NZ_icc(CC_DST
);
1193 ret
|= get_C_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1194 ret
|= get_V_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1195 ret
|= get_V_tag_icc(CC_SRC
, CC_SRC2
);
1199 static uint32_t compute_C_tsub(void)
1201 return get_C_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1204 static uint32_t compute_all_tsubtv(void)
1208 ret
= get_NZ_icc(CC_DST
);
1209 ret
|= get_C_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1213 static uint32_t compute_C_tsubtv(void)
1215 return get_C_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1218 static uint32_t compute_all_logic(void)
1220 return get_NZ_icc(CC_DST
);
1223 static uint32_t compute_C_logic(void)
1228 #ifdef TARGET_SPARC64
1229 static uint32_t compute_all_logic_xcc(void)
1231 return get_NZ_xcc(CC_DST
);
1235 typedef struct CCTable
{
1236 uint32_t (*compute_all
)(void); /* return all the flags */
1237 uint32_t (*compute_c
)(void); /* return the C flag */
1240 static const CCTable icc_table
[CC_OP_NB
] = {
1241 /* CC_OP_DYNAMIC should never happen */
1242 [CC_OP_FLAGS
] = { compute_all_flags
, compute_C_flags
},
1243 [CC_OP_DIV
] = { compute_all_div
, compute_C_div
},
1244 [CC_OP_ADD
] = { compute_all_add
, compute_C_add
},
1245 [CC_OP_ADDX
] = { compute_all_add
, compute_C_add
},
1246 [CC_OP_TADD
] = { compute_all_tadd
, compute_C_tadd
},
1247 [CC_OP_TADDTV
] = { compute_all_taddtv
, compute_C_taddtv
},
1248 [CC_OP_SUB
] = { compute_all_sub
, compute_C_sub
},
1249 [CC_OP_SUBX
] = { compute_all_sub
, compute_C_sub
},
1250 [CC_OP_TSUB
] = { compute_all_tsub
, compute_C_tsub
},
1251 [CC_OP_TSUBTV
] = { compute_all_tsubtv
, compute_C_tsubtv
},
1252 [CC_OP_LOGIC
] = { compute_all_logic
, compute_C_logic
},
1255 #ifdef TARGET_SPARC64
1256 static const CCTable xcc_table
[CC_OP_NB
] = {
1257 /* CC_OP_DYNAMIC should never happen */
1258 [CC_OP_FLAGS
] = { compute_all_flags_xcc
, compute_C_flags_xcc
},
1259 [CC_OP_DIV
] = { compute_all_logic_xcc
, compute_C_logic
},
1260 [CC_OP_ADD
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1261 [CC_OP_ADDX
] = { compute_all_addx_xcc
, compute_C_addx_xcc
},
1262 [CC_OP_TADD
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1263 [CC_OP_TADDTV
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1264 [CC_OP_SUB
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1265 [CC_OP_SUBX
] = { compute_all_subx_xcc
, compute_C_subx_xcc
},
1266 [CC_OP_TSUB
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1267 [CC_OP_TSUBTV
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1268 [CC_OP_LOGIC
] = { compute_all_logic_xcc
, compute_C_logic
},
1272 void helper_compute_psr(void)
1276 new_psr
= icc_table
[CC_OP
].compute_all();
1278 #ifdef TARGET_SPARC64
1279 new_psr
= xcc_table
[CC_OP
].compute_all();
1282 CC_OP
= CC_OP_FLAGS
;
1285 uint32_t helper_compute_C_icc(void)
1289 ret
= icc_table
[CC_OP
].compute_c() >> PSR_CARRY_SHIFT
;
1293 static inline void memcpy32(target_ulong
*dst
, const target_ulong
*src
)
1305 static void set_cwp(int new_cwp
)
1307 /* put the modified wrap registers at their proper location */
1308 if (env
->cwp
== env
->nwindows
- 1) {
1309 memcpy32(env
->regbase
, env
->regbase
+ env
->nwindows
* 16);
1313 /* put the wrap registers at their temporary location */
1314 if (new_cwp
== env
->nwindows
- 1) {
1315 memcpy32(env
->regbase
+ env
->nwindows
* 16, env
->regbase
);
1317 env
->regwptr
= env
->regbase
+ (new_cwp
* 16);
1320 void cpu_set_cwp(CPUState
*env1
, int new_cwp
)
1322 CPUState
*saved_env
;
1330 static target_ulong
get_psr(void)
1332 helper_compute_psr();
1334 #if !defined (TARGET_SPARC64)
1335 return env
->version
| (env
->psr
& PSR_ICC
) |
1336 (env
->psref
? PSR_EF
: 0) |
1337 (env
->psrpil
<< 8) |
1338 (env
->psrs
? PSR_S
: 0) |
1339 (env
->psrps
? PSR_PS
: 0) |
1340 (env
->psret
? PSR_ET
: 0) | env
->cwp
;
1342 return env
->version
| (env
->psr
& PSR_ICC
) |
1343 (env
->psref
? PSR_EF
: 0) |
1344 (env
->psrpil
<< 8) |
1345 (env
->psrs
? PSR_S
: 0) |
1346 (env
->psrps
? PSR_PS
: 0) | env
->cwp
;
1350 target_ulong
cpu_get_psr(CPUState
*env1
)
1352 CPUState
*saved_env
;
1362 static void put_psr(target_ulong val
)
1364 env
->psr
= val
& PSR_ICC
;
1365 env
->psref
= (val
& PSR_EF
)? 1 : 0;
1366 env
->psrpil
= (val
& PSR_PIL
) >> 8;
1367 #if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
1368 cpu_check_irqs(env
);
1370 env
->psrs
= (val
& PSR_S
)? 1 : 0;
1371 env
->psrps
= (val
& PSR_PS
)? 1 : 0;
1372 #if !defined (TARGET_SPARC64)
1373 env
->psret
= (val
& PSR_ET
)? 1 : 0;
1375 set_cwp(val
& PSR_CWP
);
1376 env
->cc_op
= CC_OP_FLAGS
;
1379 void cpu_put_psr(CPUState
*env1
, target_ulong val
)
1381 CPUState
*saved_env
;
1389 static int cwp_inc(int cwp
)
1391 if (unlikely(cwp
>= env
->nwindows
)) {
1392 cwp
-= env
->nwindows
;
1397 int cpu_cwp_inc(CPUState
*env1
, int cwp
)
1399 CPUState
*saved_env
;
1409 static int cwp_dec(int cwp
)
1411 if (unlikely(cwp
< 0)) {
1412 cwp
+= env
->nwindows
;
1417 int cpu_cwp_dec(CPUState
*env1
, int cwp
)
1419 CPUState
*saved_env
;
1429 #ifdef TARGET_SPARC64
1430 GEN_FCMPS(fcmps_fcc1
, float32
, 22, 0);
1431 GEN_FCMP(fcmpd_fcc1
, float64
, DT0
, DT1
, 22, 0);
1432 GEN_FCMP(fcmpq_fcc1
, float128
, QT0
, QT1
, 22, 0);
1434 GEN_FCMPS(fcmps_fcc2
, float32
, 24, 0);
1435 GEN_FCMP(fcmpd_fcc2
, float64
, DT0
, DT1
, 24, 0);
1436 GEN_FCMP(fcmpq_fcc2
, float128
, QT0
, QT1
, 24, 0);
1438 GEN_FCMPS(fcmps_fcc3
, float32
, 26, 0);
1439 GEN_FCMP(fcmpd_fcc3
, float64
, DT0
, DT1
, 26, 0);
1440 GEN_FCMP(fcmpq_fcc3
, float128
, QT0
, QT1
, 26, 0);
1442 GEN_FCMPS(fcmpes_fcc1
, float32
, 22, 1);
1443 GEN_FCMP(fcmped_fcc1
, float64
, DT0
, DT1
, 22, 1);
1444 GEN_FCMP(fcmpeq_fcc1
, float128
, QT0
, QT1
, 22, 1);
1446 GEN_FCMPS(fcmpes_fcc2
, float32
, 24, 1);
1447 GEN_FCMP(fcmped_fcc2
, float64
, DT0
, DT1
, 24, 1);
1448 GEN_FCMP(fcmpeq_fcc2
, float128
, QT0
, QT1
, 24, 1);
1450 GEN_FCMPS(fcmpes_fcc3
, float32
, 26, 1);
1451 GEN_FCMP(fcmped_fcc3
, float64
, DT0
, DT1
, 26, 1);
1452 GEN_FCMP(fcmpeq_fcc3
, float128
, QT0
, QT1
, 26, 1);
1456 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
1458 static void dump_mxcc(CPUState
*env
)
1460 printf("mxccdata: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1462 env
->mxccdata
[0], env
->mxccdata
[1],
1463 env
->mxccdata
[2], env
->mxccdata
[3]);
1464 printf("mxccregs: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1466 " %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1468 env
->mxccregs
[0], env
->mxccregs
[1],
1469 env
->mxccregs
[2], env
->mxccregs
[3],
1470 env
->mxccregs
[4], env
->mxccregs
[5],
1471 env
->mxccregs
[6], env
->mxccregs
[7]);
1475 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
1476 && defined(DEBUG_ASI)
1477 static void dump_asi(const char *txt
, target_ulong addr
, int asi
, int size
,
1483 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %02" PRIx64
"\n", txt
,
1484 addr
, asi
, r1
& 0xff);
1487 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %04" PRIx64
"\n", txt
,
1488 addr
, asi
, r1
& 0xffff);
1491 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %08" PRIx64
"\n", txt
,
1492 addr
, asi
, r1
& 0xffffffff);
1495 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %016" PRIx64
"\n", txt
,
1502 #ifndef TARGET_SPARC64
1503 #ifndef CONFIG_USER_ONLY
1504 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
1507 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
1508 uint32_t last_addr
= addr
;
1511 helper_check_align(addr
, size
- 1);
1513 case 2: /* SuperSparc MXCC registers */
1515 case 0x01c00a00: /* MXCC control register */
1517 ret
= env
->mxccregs
[3];
1519 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1522 case 0x01c00a04: /* MXCC control register */
1524 ret
= env
->mxccregs
[3];
1526 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1529 case 0x01c00c00: /* Module reset register */
1531 ret
= env
->mxccregs
[5];
1532 // should we do something here?
1534 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1537 case 0x01c00f00: /* MBus port address register */
1539 ret
= env
->mxccregs
[7];
1541 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1545 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
1549 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
1550 "addr = %08x -> ret = %" PRIx64
","
1551 "addr = %08x\n", asi
, size
, sign
, last_addr
, ret
, addr
);
1556 case 3: /* MMU probe */
1560 mmulev
= (addr
>> 8) & 15;
1564 ret
= mmu_probe(env
, addr
, mmulev
);
1565 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64
"\n",
1569 case 4: /* read MMU regs */
1571 int reg
= (addr
>> 8) & 0x1f;
1573 ret
= env
->mmuregs
[reg
];
1574 if (reg
== 3) /* Fault status cleared on read */
1575 env
->mmuregs
[3] = 0;
1576 else if (reg
== 0x13) /* Fault status read */
1577 ret
= env
->mmuregs
[3];
1578 else if (reg
== 0x14) /* Fault address read */
1579 ret
= env
->mmuregs
[4];
1580 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64
"\n", reg
, ret
);
1583 case 5: // Turbosparc ITLB Diagnostic
1584 case 6: // Turbosparc DTLB Diagnostic
1585 case 7: // Turbosparc IOTLB Diagnostic
1587 case 9: /* Supervisor code access */
1590 ret
= ldub_code(addr
);
1593 ret
= lduw_code(addr
);
1597 ret
= ldl_code(addr
);
1600 ret
= ldq_code(addr
);
1604 case 0xa: /* User data access */
1607 ret
= ldub_user(addr
);
1610 ret
= lduw_user(addr
);
1614 ret
= ldl_user(addr
);
1617 ret
= ldq_user(addr
);
1621 case 0xb: /* Supervisor data access */
1624 ret
= ldub_kernel(addr
);
1627 ret
= lduw_kernel(addr
);
1631 ret
= ldl_kernel(addr
);
1634 ret
= ldq_kernel(addr
);
1638 case 0xc: /* I-cache tag */
1639 case 0xd: /* I-cache data */
1640 case 0xe: /* D-cache tag */
1641 case 0xf: /* D-cache data */
1643 case 0x20: /* MMU passthrough */
1646 ret
= ldub_phys(addr
);
1649 ret
= lduw_phys(addr
);
1653 ret
= ldl_phys(addr
);
1656 ret
= ldq_phys(addr
);
1660 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1663 ret
= ldub_phys((target_phys_addr_t
)addr
1664 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1667 ret
= lduw_phys((target_phys_addr_t
)addr
1668 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1672 ret
= ldl_phys((target_phys_addr_t
)addr
1673 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1676 ret
= ldq_phys((target_phys_addr_t
)addr
1677 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1681 case 0x30: // Turbosparc secondary cache diagnostic
1682 case 0x31: // Turbosparc RAM snoop
1683 case 0x32: // Turbosparc page table descriptor diagnostic
1684 case 0x39: /* data cache diagnostic register */
1687 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
1689 int reg
= (addr
>> 8) & 3;
1692 case 0: /* Breakpoint Value (Addr) */
1693 ret
= env
->mmubpregs
[reg
];
1695 case 1: /* Breakpoint Mask */
1696 ret
= env
->mmubpregs
[reg
];
1698 case 2: /* Breakpoint Control */
1699 ret
= env
->mmubpregs
[reg
];
1701 case 3: /* Breakpoint Status */
1702 ret
= env
->mmubpregs
[reg
];
1703 env
->mmubpregs
[reg
] = 0ULL;
1706 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64
"\n", reg
,
1710 case 8: /* User code access, XXX */
1712 do_unassigned_access(addr
, 0, 0, asi
, size
);
1722 ret
= (int16_t) ret
;
1725 ret
= (int32_t) ret
;
1732 dump_asi("read ", last_addr
, asi
, size
, ret
);
1737 void helper_st_asi(target_ulong addr
, uint64_t val
, int asi
, int size
)
1739 helper_check_align(addr
, size
- 1);
1741 case 2: /* SuperSparc MXCC registers */
1743 case 0x01c00000: /* MXCC stream data register 0 */
1745 env
->mxccdata
[0] = val
;
1747 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1750 case 0x01c00008: /* MXCC stream data register 1 */
1752 env
->mxccdata
[1] = val
;
1754 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1757 case 0x01c00010: /* MXCC stream data register 2 */
1759 env
->mxccdata
[2] = val
;
1761 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1764 case 0x01c00018: /* MXCC stream data register 3 */
1766 env
->mxccdata
[3] = val
;
1768 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1771 case 0x01c00100: /* MXCC stream source */
1773 env
->mxccregs
[0] = val
;
1775 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1777 env
->mxccdata
[0] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1779 env
->mxccdata
[1] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1781 env
->mxccdata
[2] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1783 env
->mxccdata
[3] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1786 case 0x01c00200: /* MXCC stream destination */
1788 env
->mxccregs
[1] = val
;
1790 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1792 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 0,
1794 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 8,
1796 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 16,
1798 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 24,
1801 case 0x01c00a00: /* MXCC control register */
1803 env
->mxccregs
[3] = val
;
1805 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1808 case 0x01c00a04: /* MXCC control register */
1810 env
->mxccregs
[3] = (env
->mxccregs
[3] & 0xffffffff00000000ULL
)
1813 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1816 case 0x01c00e00: /* MXCC error register */
1817 // writing a 1 bit clears the error
1819 env
->mxccregs
[6] &= ~val
;
1821 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1824 case 0x01c00f00: /* MBus port address register */
1826 env
->mxccregs
[7] = val
;
1828 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1832 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
1836 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64
"\n",
1837 asi
, size
, addr
, val
);
1842 case 3: /* MMU flush */
1846 mmulev
= (addr
>> 8) & 15;
1847 DPRINTF_MMU("mmu flush level %d\n", mmulev
);
1849 case 0: // flush page
1850 tlb_flush_page(env
, addr
& 0xfffff000);
1852 case 1: // flush segment (256k)
1853 case 2: // flush region (16M)
1854 case 3: // flush context (4G)
1855 case 4: // flush entire
1866 case 4: /* write MMU regs */
1868 int reg
= (addr
>> 8) & 0x1f;
1871 oldreg
= env
->mmuregs
[reg
];
1873 case 0: // Control Register
1874 env
->mmuregs
[reg
] = (env
->mmuregs
[reg
] & 0xff000000) |
1876 // Mappings generated during no-fault mode or MMU
1877 // disabled mode are invalid in normal mode
1878 if ((oldreg
& (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)) !=
1879 (env
->mmuregs
[reg
] & (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)))
1882 case 1: // Context Table Pointer Register
1883 env
->mmuregs
[reg
] = val
& env
->def
->mmu_ctpr_mask
;
1885 case 2: // Context Register
1886 env
->mmuregs
[reg
] = val
& env
->def
->mmu_cxr_mask
;
1887 if (oldreg
!= env
->mmuregs
[reg
]) {
1888 /* we flush when the MMU context changes because
1889 QEMU has no MMU context support */
1893 case 3: // Synchronous Fault Status Register with Clear
1894 case 4: // Synchronous Fault Address Register
1896 case 0x10: // TLB Replacement Control Register
1897 env
->mmuregs
[reg
] = val
& env
->def
->mmu_trcr_mask
;
1899 case 0x13: // Synchronous Fault Status Register with Read and Clear
1900 env
->mmuregs
[3] = val
& env
->def
->mmu_sfsr_mask
;
1902 case 0x14: // Synchronous Fault Address Register
1903 env
->mmuregs
[4] = val
;
1906 env
->mmuregs
[reg
] = val
;
1909 if (oldreg
!= env
->mmuregs
[reg
]) {
1910 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1911 reg
, oldreg
, env
->mmuregs
[reg
]);
1918 case 5: // Turbosparc ITLB Diagnostic
1919 case 6: // Turbosparc DTLB Diagnostic
1920 case 7: // Turbosparc IOTLB Diagnostic
1922 case 0xa: /* User data access */
1925 stb_user(addr
, val
);
1928 stw_user(addr
, val
);
1932 stl_user(addr
, val
);
1935 stq_user(addr
, val
);
1939 case 0xb: /* Supervisor data access */
1942 stb_kernel(addr
, val
);
1945 stw_kernel(addr
, val
);
1949 stl_kernel(addr
, val
);
1952 stq_kernel(addr
, val
);
1956 case 0xc: /* I-cache tag */
1957 case 0xd: /* I-cache data */
1958 case 0xe: /* D-cache tag */
1959 case 0xf: /* D-cache data */
1960 case 0x10: /* I/D-cache flush page */
1961 case 0x11: /* I/D-cache flush segment */
1962 case 0x12: /* I/D-cache flush region */
1963 case 0x13: /* I/D-cache flush context */
1964 case 0x14: /* I/D-cache flush user */
1966 case 0x17: /* Block copy, sta access */
1972 uint32_t src
= val
& ~3, dst
= addr
& ~3, temp
;
1974 for (i
= 0; i
< 32; i
+= 4, src
+= 4, dst
+= 4) {
1975 temp
= ldl_kernel(src
);
1976 stl_kernel(dst
, temp
);
1980 case 0x1f: /* Block fill, stda access */
1983 // fill 32 bytes with val
1985 uint32_t dst
= addr
& 7;
1987 for (i
= 0; i
< 32; i
+= 8, dst
+= 8)
1988 stq_kernel(dst
, val
);
1991 case 0x20: /* MMU passthrough */
1995 stb_phys(addr
, val
);
1998 stw_phys(addr
, val
);
2002 stl_phys(addr
, val
);
2005 stq_phys(addr
, val
);
2010 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
2014 stb_phys((target_phys_addr_t
)addr
2015 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
2018 stw_phys((target_phys_addr_t
)addr
2019 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
2023 stl_phys((target_phys_addr_t
)addr
2024 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
2027 stq_phys((target_phys_addr_t
)addr
2028 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
2033 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
2034 case 0x31: // store buffer data, Ross RT620 I-cache flush or
2035 // Turbosparc snoop RAM
2036 case 0x32: // store buffer control or Turbosparc page table
2037 // descriptor diagnostic
2038 case 0x36: /* I-cache flash clear */
2039 case 0x37: /* D-cache flash clear */
2040 case 0x4c: /* breakpoint action */
2042 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
2044 int reg
= (addr
>> 8) & 3;
2047 case 0: /* Breakpoint Value (Addr) */
2048 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
2050 case 1: /* Breakpoint Mask */
2051 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
2053 case 2: /* Breakpoint Control */
2054 env
->mmubpregs
[reg
] = (val
& 0x7fULL
);
2056 case 3: /* Breakpoint Status */
2057 env
->mmubpregs
[reg
] = (val
& 0xfULL
);
2060 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg
,
2064 case 8: /* User code access, XXX */
2065 case 9: /* Supervisor code access, XXX */
2067 do_unassigned_access(addr
, 1, 0, asi
, size
);
2071 dump_asi("write", addr
, asi
, size
, val
);
2075 #endif /* CONFIG_USER_ONLY */
2076 #else /* TARGET_SPARC64 */
2078 #ifdef CONFIG_USER_ONLY
2079 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
2082 #if defined(DEBUG_ASI)
2083 target_ulong last_addr
= addr
;
2087 raise_exception(TT_PRIV_ACT
);
2089 helper_check_align(addr
, size
- 1);
2090 addr
= address_mask(env
, addr
);
2093 case 0x82: // Primary no-fault
2094 case 0x8a: // Primary no-fault LE
2095 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
2097 dump_asi("read ", last_addr
, asi
, size
, ret
);
2102 case 0x80: // Primary
2103 case 0x88: // Primary LE
2107 ret
= ldub_raw(addr
);
2110 ret
= lduw_raw(addr
);
2113 ret
= ldl_raw(addr
);
2117 ret
= ldq_raw(addr
);
2122 case 0x83: // Secondary no-fault
2123 case 0x8b: // Secondary no-fault LE
2124 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
2126 dump_asi("read ", last_addr
, asi
, size
, ret
);
2131 case 0x81: // Secondary
2132 case 0x89: // Secondary LE
2139 /* Convert from little endian */
2141 case 0x88: // Primary LE
2142 case 0x89: // Secondary LE
2143 case 0x8a: // Primary no-fault LE
2144 case 0x8b: // Secondary no-fault LE
2162 /* Convert to signed number */
2169 ret
= (int16_t) ret
;
2172 ret
= (int32_t) ret
;
2179 dump_asi("read ", last_addr
, asi
, size
, ret
);
2184 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
2187 dump_asi("write", addr
, asi
, size
, val
);
2190 raise_exception(TT_PRIV_ACT
);
2192 helper_check_align(addr
, size
- 1);
2193 addr
= address_mask(env
, addr
);
2195 /* Convert to little endian */
2197 case 0x88: // Primary LE
2198 case 0x89: // Secondary LE
2217 case 0x80: // Primary
2218 case 0x88: // Primary LE
2237 case 0x81: // Secondary
2238 case 0x89: // Secondary LE
2242 case 0x82: // Primary no-fault, RO
2243 case 0x83: // Secondary no-fault, RO
2244 case 0x8a: // Primary no-fault LE, RO
2245 case 0x8b: // Secondary no-fault LE, RO
2247 do_unassigned_access(addr
, 1, 0, 1, size
);
2252 #else /* CONFIG_USER_ONLY */
2254 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
2257 #if defined(DEBUG_ASI)
2258 target_ulong last_addr
= addr
;
2263 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2264 || ((env
->def
->features
& CPU_FEATURE_HYPV
)
2265 && asi
>= 0x30 && asi
< 0x80
2266 && !(env
->hpstate
& HS_PRIV
)))
2267 raise_exception(TT_PRIV_ACT
);
2269 helper_check_align(addr
, size
- 1);
2271 case 0x82: // Primary no-fault
2272 case 0x8a: // Primary no-fault LE
2273 case 0x83: // Secondary no-fault
2274 case 0x8b: // Secondary no-fault LE
2276 /* secondary space access has lowest asi bit equal to 1 */
2277 int access_mmu_idx
= ( asi
& 1 ) ? MMU_KERNEL_IDX
2278 : MMU_KERNEL_SECONDARY_IDX
;
2280 if (cpu_get_phys_page_nofault(env
, addr
, access_mmu_idx
) == -1ULL) {
2282 dump_asi("read ", last_addr
, asi
, size
, ret
);
2288 case 0x10: // As if user primary
2289 case 0x11: // As if user secondary
2290 case 0x18: // As if user primary LE
2291 case 0x19: // As if user secondary LE
2292 case 0x80: // Primary
2293 case 0x81: // Secondary
2294 case 0x88: // Primary LE
2295 case 0x89: // Secondary LE
2296 case 0xe2: // UA2007 Primary block init
2297 case 0xe3: // UA2007 Secondary block init
2298 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
2299 if ((env
->def
->features
& CPU_FEATURE_HYPV
)
2300 && env
->hpstate
& HS_PRIV
) {
2303 ret
= ldub_hypv(addr
);
2306 ret
= lduw_hypv(addr
);
2309 ret
= ldl_hypv(addr
);
2313 ret
= ldq_hypv(addr
);
2317 /* secondary space access has lowest asi bit equal to 1 */
2321 ret
= ldub_kernel_secondary(addr
);
2324 ret
= lduw_kernel_secondary(addr
);
2327 ret
= ldl_kernel_secondary(addr
);
2331 ret
= ldq_kernel_secondary(addr
);
2337 ret
= ldub_kernel(addr
);
2340 ret
= lduw_kernel(addr
);
2343 ret
= ldl_kernel(addr
);
2347 ret
= ldq_kernel(addr
);
2353 /* secondary space access has lowest asi bit equal to 1 */
2357 ret
= ldub_user_secondary(addr
);
2360 ret
= lduw_user_secondary(addr
);
2363 ret
= ldl_user_secondary(addr
);
2367 ret
= ldq_user_secondary(addr
);
2373 ret
= ldub_user(addr
);
2376 ret
= lduw_user(addr
);
2379 ret
= ldl_user(addr
);
2383 ret
= ldq_user(addr
);
2389 case 0x14: // Bypass
2390 case 0x15: // Bypass, non-cacheable
2391 case 0x1c: // Bypass LE
2392 case 0x1d: // Bypass, non-cacheable LE
2396 ret
= ldub_phys(addr
);
2399 ret
= lduw_phys(addr
);
2402 ret
= ldl_phys(addr
);
2406 ret
= ldq_phys(addr
);
2411 case 0x24: // Nucleus quad LDD 128 bit atomic
2412 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2413 // Only ldda allowed
2414 raise_exception(TT_ILL_INSN
);
2416 case 0x04: // Nucleus
2417 case 0x0c: // Nucleus Little Endian (LE)
2421 ret
= ldub_nucleus(addr
);
2424 ret
= lduw_nucleus(addr
);
2427 ret
= ldl_nucleus(addr
);
2431 ret
= ldq_nucleus(addr
);
2436 case 0x4a: // UPA config
2442 case 0x50: // I-MMU regs
2444 int reg
= (addr
>> 3) & 0xf;
2447 // I-TSB Tag Target register
2448 ret
= ultrasparc_tag_target(env
->immu
.tag_access
);
2450 ret
= env
->immuregs
[reg
];
2455 case 0x51: // I-MMU 8k TSB pointer
2457 // env->immuregs[5] holds I-MMU TSB register value
2458 // env->immuregs[6] holds I-MMU Tag Access register value
2459 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
2463 case 0x52: // I-MMU 64k TSB pointer
2465 // env->immuregs[5] holds I-MMU TSB register value
2466 // env->immuregs[6] holds I-MMU Tag Access register value
2467 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
2471 case 0x55: // I-MMU data access
2473 int reg
= (addr
>> 3) & 0x3f;
2475 ret
= env
->itlb
[reg
].tte
;
2478 case 0x56: // I-MMU tag read
2480 int reg
= (addr
>> 3) & 0x3f;
2482 ret
= env
->itlb
[reg
].tag
;
2485 case 0x58: // D-MMU regs
2487 int reg
= (addr
>> 3) & 0xf;
2490 // D-TSB Tag Target register
2491 ret
= ultrasparc_tag_target(env
->dmmu
.tag_access
);
2493 ret
= env
->dmmuregs
[reg
];
2497 case 0x59: // D-MMU 8k TSB pointer
2499 // env->dmmuregs[5] holds D-MMU TSB register value
2500 // env->dmmuregs[6] holds D-MMU Tag Access register value
2501 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
2505 case 0x5a: // D-MMU 64k TSB pointer
2507 // env->dmmuregs[5] holds D-MMU TSB register value
2508 // env->dmmuregs[6] holds D-MMU Tag Access register value
2509 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
2513 case 0x5d: // D-MMU data access
2515 int reg
= (addr
>> 3) & 0x3f;
2517 ret
= env
->dtlb
[reg
].tte
;
2520 case 0x5e: // D-MMU tag read
2522 int reg
= (addr
>> 3) & 0x3f;
2524 ret
= env
->dtlb
[reg
].tag
;
2527 case 0x46: // D-cache data
2528 case 0x47: // D-cache tag access
2529 case 0x4b: // E-cache error enable
2530 case 0x4c: // E-cache asynchronous fault status
2531 case 0x4d: // E-cache asynchronous fault address
2532 case 0x4e: // E-cache tag data
2533 case 0x66: // I-cache instruction access
2534 case 0x67: // I-cache tag access
2535 case 0x6e: // I-cache predecode
2536 case 0x6f: // I-cache LRU etc.
2537 case 0x76: // E-cache tag
2538 case 0x7e: // E-cache tag
2540 case 0x5b: // D-MMU data pointer
2541 case 0x48: // Interrupt dispatch, RO
2542 case 0x49: // Interrupt data receive
2543 case 0x7f: // Incoming interrupt vector, RO
2546 case 0x54: // I-MMU data in, WO
2547 case 0x57: // I-MMU demap, WO
2548 case 0x5c: // D-MMU data in, WO
2549 case 0x5f: // D-MMU demap, WO
2550 case 0x77: // Interrupt vector, WO
2552 do_unassigned_access(addr
, 0, 0, 1, size
);
2557 /* Convert from little endian */
2559 case 0x0c: // Nucleus Little Endian (LE)
2560 case 0x18: // As if user primary LE
2561 case 0x19: // As if user secondary LE
2562 case 0x1c: // Bypass LE
2563 case 0x1d: // Bypass, non-cacheable LE
2564 case 0x88: // Primary LE
2565 case 0x89: // Secondary LE
2566 case 0x8a: // Primary no-fault LE
2567 case 0x8b: // Secondary no-fault LE
2585 /* Convert to signed number */
2592 ret
= (int16_t) ret
;
2595 ret
= (int32_t) ret
;
2602 dump_asi("read ", last_addr
, asi
, size
, ret
);
2607 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
2610 dump_asi("write", addr
, asi
, size
, val
);
2615 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2616 || ((env
->def
->features
& CPU_FEATURE_HYPV
)
2617 && asi
>= 0x30 && asi
< 0x80
2618 && !(env
->hpstate
& HS_PRIV
)))
2619 raise_exception(TT_PRIV_ACT
);
2621 helper_check_align(addr
, size
- 1);
2622 /* Convert to little endian */
2624 case 0x0c: // Nucleus Little Endian (LE)
2625 case 0x18: // As if user primary LE
2626 case 0x19: // As if user secondary LE
2627 case 0x1c: // Bypass LE
2628 case 0x1d: // Bypass, non-cacheable LE
2629 case 0x88: // Primary LE
2630 case 0x89: // Secondary LE
2649 case 0x10: // As if user primary
2650 case 0x11: // As if user secondary
2651 case 0x18: // As if user primary LE
2652 case 0x19: // As if user secondary LE
2653 case 0x80: // Primary
2654 case 0x81: // Secondary
2655 case 0x88: // Primary LE
2656 case 0x89: // Secondary LE
2657 case 0xe2: // UA2007 Primary block init
2658 case 0xe3: // UA2007 Secondary block init
2659 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
2660 if ((env
->def
->features
& CPU_FEATURE_HYPV
)
2661 && env
->hpstate
& HS_PRIV
) {
2664 stb_hypv(addr
, val
);
2667 stw_hypv(addr
, val
);
2670 stl_hypv(addr
, val
);
2674 stq_hypv(addr
, val
);
2678 /* secondary space access has lowest asi bit equal to 1 */
2682 stb_kernel_secondary(addr
, val
);
2685 stw_kernel_secondary(addr
, val
);
2688 stl_kernel_secondary(addr
, val
);
2692 stq_kernel_secondary(addr
, val
);
2698 stb_kernel(addr
, val
);
2701 stw_kernel(addr
, val
);
2704 stl_kernel(addr
, val
);
2708 stq_kernel(addr
, val
);
2714 /* secondary space access has lowest asi bit equal to 1 */
2718 stb_user_secondary(addr
, val
);
2721 stw_user_secondary(addr
, val
);
2724 stl_user_secondary(addr
, val
);
2728 stq_user_secondary(addr
, val
);
2734 stb_user(addr
, val
);
2737 stw_user(addr
, val
);
2740 stl_user(addr
, val
);
2744 stq_user(addr
, val
);
2750 case 0x14: // Bypass
2751 case 0x15: // Bypass, non-cacheable
2752 case 0x1c: // Bypass LE
2753 case 0x1d: // Bypass, non-cacheable LE
2757 stb_phys(addr
, val
);
2760 stw_phys(addr
, val
);
2763 stl_phys(addr
, val
);
2767 stq_phys(addr
, val
);
2772 case 0x24: // Nucleus quad LDD 128 bit atomic
2773 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2774 // Only ldda allowed
2775 raise_exception(TT_ILL_INSN
);
2777 case 0x04: // Nucleus
2778 case 0x0c: // Nucleus Little Endian (LE)
2782 stb_nucleus(addr
, val
);
2785 stw_nucleus(addr
, val
);
2788 stl_nucleus(addr
, val
);
2792 stq_nucleus(addr
, val
);
2798 case 0x4a: // UPA config
2806 env
->lsu
= val
& (DMMU_E
| IMMU_E
);
2807 // Mappings generated during D/I MMU disabled mode are
2808 // invalid in normal mode
2809 if (oldreg
!= env
->lsu
) {
2810 DPRINTF_MMU("LSU change: 0x%" PRIx64
" -> 0x%" PRIx64
"\n",
2819 case 0x50: // I-MMU regs
2821 int reg
= (addr
>> 3) & 0xf;
2824 oldreg
= env
->immuregs
[reg
];
2828 case 1: // Not in I-MMU
2833 val
= 0; // Clear SFSR
2834 env
->immu
.sfsr
= val
;
2838 case 5: // TSB access
2839 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64
" -> 0x%016"
2840 PRIx64
"\n", env
->immu
.tsb
, val
);
2841 env
->immu
.tsb
= val
;
2843 case 6: // Tag access
2844 env
->immu
.tag_access
= val
;
2853 if (oldreg
!= env
->immuregs
[reg
]) {
2854 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
2855 PRIx64
"\n", reg
, oldreg
, env
->immuregs
[reg
]);
2862 case 0x54: // I-MMU data in
2863 replace_tlb_1bit_lru(env
->itlb
, env
->immu
.tag_access
, val
, "immu", env
);
2865 case 0x55: // I-MMU data access
2869 unsigned int i
= (addr
>> 3) & 0x3f;
2871 replace_tlb_entry(&env
->itlb
[i
], env
->immu
.tag_access
, val
, env
);
2874 DPRINTF_MMU("immu data access replaced entry [%i]\n", i
);
2879 case 0x57: // I-MMU demap
2880 demap_tlb(env
->itlb
, val
, "immu", env
);
2882 case 0x58: // D-MMU regs
2884 int reg
= (addr
>> 3) & 0xf;
2887 oldreg
= env
->dmmuregs
[reg
];
2893 if ((val
& 1) == 0) {
2894 val
= 0; // Clear SFSR, Fault address
2897 env
->dmmu
.sfsr
= val
;
2899 case 1: // Primary context
2900 env
->dmmu
.mmu_primary_context
= val
;
2902 case 2: // Secondary context
2903 env
->dmmu
.mmu_secondary_context
= val
;
2905 case 5: // TSB access
2906 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64
" -> 0x%016"
2907 PRIx64
"\n", env
->dmmu
.tsb
, val
);
2908 env
->dmmu
.tsb
= val
;
2910 case 6: // Tag access
2911 env
->dmmu
.tag_access
= val
;
2913 case 7: // Virtual Watchpoint
2914 case 8: // Physical Watchpoint
2916 env
->dmmuregs
[reg
] = val
;
2920 if (oldreg
!= env
->dmmuregs
[reg
]) {
2921 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
2922 PRIx64
"\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
2929 case 0x5c: // D-MMU data in
2930 replace_tlb_1bit_lru(env
->dtlb
, env
->dmmu
.tag_access
, val
, "dmmu", env
);
2932 case 0x5d: // D-MMU data access
2934 unsigned int i
= (addr
>> 3) & 0x3f;
2936 replace_tlb_entry(&env
->dtlb
[i
], env
->dmmu
.tag_access
, val
, env
);
2939 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i
);
2944 case 0x5f: // D-MMU demap
2945 demap_tlb(env
->dtlb
, val
, "dmmu", env
);
2947 case 0x49: // Interrupt data receive
2950 case 0x46: // D-cache data
2951 case 0x47: // D-cache tag access
2952 case 0x4b: // E-cache error enable
2953 case 0x4c: // E-cache asynchronous fault status
2954 case 0x4d: // E-cache asynchronous fault address
2955 case 0x4e: // E-cache tag data
2956 case 0x66: // I-cache instruction access
2957 case 0x67: // I-cache tag access
2958 case 0x6e: // I-cache predecode
2959 case 0x6f: // I-cache LRU etc.
2960 case 0x76: // E-cache tag
2961 case 0x7e: // E-cache tag
2963 case 0x51: // I-MMU 8k TSB pointer, RO
2964 case 0x52: // I-MMU 64k TSB pointer, RO
2965 case 0x56: // I-MMU tag read, RO
2966 case 0x59: // D-MMU 8k TSB pointer, RO
2967 case 0x5a: // D-MMU 64k TSB pointer, RO
2968 case 0x5b: // D-MMU data pointer, RO
2969 case 0x5e: // D-MMU tag read, RO
2970 case 0x48: // Interrupt dispatch, RO
2971 case 0x7f: // Incoming interrupt vector, RO
2972 case 0x82: // Primary no-fault, RO
2973 case 0x83: // Secondary no-fault, RO
2974 case 0x8a: // Primary no-fault LE, RO
2975 case 0x8b: // Secondary no-fault LE, RO
2977 do_unassigned_access(addr
, 1, 0, 1, size
);
2981 #endif /* CONFIG_USER_ONLY */
2983 void helper_ldda_asi(target_ulong addr
, int asi
, int rd
)
2985 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2986 || ((env
->def
->features
& CPU_FEATURE_HYPV
)
2987 && asi
>= 0x30 && asi
< 0x80
2988 && !(env
->hpstate
& HS_PRIV
)))
2989 raise_exception(TT_PRIV_ACT
);
2992 case 0x24: // Nucleus quad LDD 128 bit atomic
2993 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2994 helper_check_align(addr
, 0xf);
2996 env
->gregs
[1] = ldq_kernel(addr
+ 8);
2998 bswap64s(&env
->gregs
[1]);
2999 } else if (rd
< 8) {
3000 env
->gregs
[rd
] = ldq_kernel(addr
);
3001 env
->gregs
[rd
+ 1] = ldq_kernel(addr
+ 8);
3003 bswap64s(&env
->gregs
[rd
]);
3004 bswap64s(&env
->gregs
[rd
+ 1]);
3007 env
->regwptr
[rd
] = ldq_kernel(addr
);
3008 env
->regwptr
[rd
+ 1] = ldq_kernel(addr
+ 8);
3010 bswap64s(&env
->regwptr
[rd
]);
3011 bswap64s(&env
->regwptr
[rd
+ 1]);
3016 helper_check_align(addr
, 0x3);
3018 env
->gregs
[1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
3020 env
->gregs
[rd
] = helper_ld_asi(addr
, asi
, 4, 0);
3021 env
->gregs
[rd
+ 1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
3023 env
->regwptr
[rd
] = helper_ld_asi(addr
, asi
, 4, 0);
3024 env
->regwptr
[rd
+ 1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
3030 void helper_ldf_asi(target_ulong addr
, int asi
, int size
, int rd
)
3035 helper_check_align(addr
, 3);
3037 case 0xf0: // Block load primary
3038 case 0xf1: // Block load secondary
3039 case 0xf8: // Block load primary LE
3040 case 0xf9: // Block load secondary LE
3042 raise_exception(TT_ILL_INSN
);
3045 helper_check_align(addr
, 0x3f);
3046 for (i
= 0; i
< 16; i
++) {
3047 *(uint32_t *)&env
->fpr
[rd
++] = helper_ld_asi(addr
, asi
& 0x8f, 4,
3057 val
= helper_ld_asi(addr
, asi
, size
, 0);
3061 *((uint32_t *)&env
->fpr
[rd
]) = val
;
3064 *((int64_t *)&DT0
) = val
;
3072 void helper_stf_asi(target_ulong addr
, int asi
, int size
, int rd
)
3075 target_ulong val
= 0;
3077 helper_check_align(addr
, 3);
3079 case 0xe0: // UA2007 Block commit store primary (cache flush)
3080 case 0xe1: // UA2007 Block commit store secondary (cache flush)
3081 case 0xf0: // Block store primary
3082 case 0xf1: // Block store secondary
3083 case 0xf8: // Block store primary LE
3084 case 0xf9: // Block store secondary LE
3086 raise_exception(TT_ILL_INSN
);
3089 helper_check_align(addr
, 0x3f);
3090 for (i
= 0; i
< 16; i
++) {
3091 val
= *(uint32_t *)&env
->fpr
[rd
++];
3092 helper_st_asi(addr
, val
, asi
& 0x8f, 4);
3104 val
= *((uint32_t *)&env
->fpr
[rd
]);
3107 val
= *((int64_t *)&DT0
);
3113 helper_st_asi(addr
, val
, asi
, size
);
3116 target_ulong
helper_cas_asi(target_ulong addr
, target_ulong val1
,
3117 target_ulong val2
, uint32_t asi
)
3121 val2
&= 0xffffffffUL
;
3122 ret
= helper_ld_asi(addr
, asi
, 4, 0);
3123 ret
&= 0xffffffffUL
;
3125 helper_st_asi(addr
, val1
& 0xffffffffUL
, asi
, 4);
3129 target_ulong
helper_casx_asi(target_ulong addr
, target_ulong val1
,
3130 target_ulong val2
, uint32_t asi
)
3134 ret
= helper_ld_asi(addr
, asi
, 8, 0);
3136 helper_st_asi(addr
, val1
, asi
, 8);
3139 #endif /* TARGET_SPARC64 */
3141 #ifndef TARGET_SPARC64
3142 void helper_rett(void)
3146 if (env
->psret
== 1)
3147 raise_exception(TT_ILL_INSN
);
3150 cwp
= cwp_inc(env
->cwp
+ 1) ;
3151 if (env
->wim
& (1 << cwp
)) {
3152 raise_exception(TT_WIN_UNF
);
3155 env
->psrs
= env
->psrps
;
3159 target_ulong
helper_udiv(target_ulong a
, target_ulong b
)
3164 x0
= (a
& 0xffffffff) | ((int64_t) (env
->y
) << 32);
3168 raise_exception(TT_DIV_ZERO
);
3172 if (x0
> 0xffffffff) {
3181 target_ulong
helper_sdiv(target_ulong a
, target_ulong b
)
3186 x0
= (a
& 0xffffffff) | ((int64_t) (env
->y
) << 32);
3190 raise_exception(TT_DIV_ZERO
);
3194 if ((int32_t) x0
!= x0
) {
3196 return x0
< 0? 0x80000000: 0x7fffffff;
3203 void helper_stdf(target_ulong addr
, int mem_idx
)
3205 helper_check_align(addr
, 7);
3206 #if !defined(CONFIG_USER_ONLY)
3209 stfq_user(addr
, DT0
);
3212 stfq_kernel(addr
, DT0
);
3214 #ifdef TARGET_SPARC64
3216 stfq_hypv(addr
, DT0
);
3223 stfq_raw(address_mask(env
, addr
), DT0
);
3227 void helper_lddf(target_ulong addr
, int mem_idx
)
3229 helper_check_align(addr
, 7);
3230 #if !defined(CONFIG_USER_ONLY)
3233 DT0
= ldfq_user(addr
);
3236 DT0
= ldfq_kernel(addr
);
3238 #ifdef TARGET_SPARC64
3240 DT0
= ldfq_hypv(addr
);
3247 DT0
= ldfq_raw(address_mask(env
, addr
));
3251 void helper_ldqf(target_ulong addr
, int mem_idx
)
3253 // XXX add 128 bit load
3256 helper_check_align(addr
, 7);
3257 #if !defined(CONFIG_USER_ONLY)
3260 u
.ll
.upper
= ldq_user(addr
);
3261 u
.ll
.lower
= ldq_user(addr
+ 8);
3265 u
.ll
.upper
= ldq_kernel(addr
);
3266 u
.ll
.lower
= ldq_kernel(addr
+ 8);
3269 #ifdef TARGET_SPARC64
3271 u
.ll
.upper
= ldq_hypv(addr
);
3272 u
.ll
.lower
= ldq_hypv(addr
+ 8);
3280 u
.ll
.upper
= ldq_raw(address_mask(env
, addr
));
3281 u
.ll
.lower
= ldq_raw(address_mask(env
, addr
+ 8));
3286 void helper_stqf(target_ulong addr
, int mem_idx
)
3288 // XXX add 128 bit store
3291 helper_check_align(addr
, 7);
3292 #if !defined(CONFIG_USER_ONLY)
3296 stq_user(addr
, u
.ll
.upper
);
3297 stq_user(addr
+ 8, u
.ll
.lower
);
3301 stq_kernel(addr
, u
.ll
.upper
);
3302 stq_kernel(addr
+ 8, u
.ll
.lower
);
3304 #ifdef TARGET_SPARC64
3307 stq_hypv(addr
, u
.ll
.upper
);
3308 stq_hypv(addr
+ 8, u
.ll
.lower
);
3316 stq_raw(address_mask(env
, addr
), u
.ll
.upper
);
3317 stq_raw(address_mask(env
, addr
+ 8), u
.ll
.lower
);
3321 static inline void set_fsr(void)
3325 switch (env
->fsr
& FSR_RD_MASK
) {
3326 case FSR_RD_NEAREST
:
3327 rnd_mode
= float_round_nearest_even
;
3331 rnd_mode
= float_round_to_zero
;
3334 rnd_mode
= float_round_up
;
3337 rnd_mode
= float_round_down
;
3340 set_float_rounding_mode(rnd_mode
, &env
->fp_status
);
3343 void helper_ldfsr(uint32_t new_fsr
)
3345 env
->fsr
= (new_fsr
& FSR_LDFSR_MASK
) | (env
->fsr
& FSR_LDFSR_OLDMASK
);
3349 #ifdef TARGET_SPARC64
3350 void helper_ldxfsr(uint64_t new_fsr
)
3352 env
->fsr
= (new_fsr
& FSR_LDXFSR_MASK
) | (env
->fsr
& FSR_LDXFSR_OLDMASK
);
3357 void helper_debug(void)
3359 env
->exception_index
= EXCP_DEBUG
;
3363 #ifndef TARGET_SPARC64
3364 /* XXX: use another pointer for %iN registers to avoid slow wrapping
3366 void helper_save(void)
3370 cwp
= cwp_dec(env
->cwp
- 1);
3371 if (env
->wim
& (1 << cwp
)) {
3372 raise_exception(TT_WIN_OVF
);
3377 void helper_restore(void)
3381 cwp
= cwp_inc(env
->cwp
+ 1);
3382 if (env
->wim
& (1 << cwp
)) {
3383 raise_exception(TT_WIN_UNF
);
3388 void helper_wrpsr(target_ulong new_psr
)
3390 if ((new_psr
& PSR_CWP
) >= env
->nwindows
) {
3391 raise_exception(TT_ILL_INSN
);
3393 cpu_put_psr(env
, new_psr
);
3397 target_ulong
helper_rdpsr(void)
3403 /* XXX: use another pointer for %iN registers to avoid slow wrapping
3405 void helper_save(void)
3409 cwp
= cwp_dec(env
->cwp
- 1);
3410 if (env
->cansave
== 0) {
3411 raise_exception(TT_SPILL
| (env
->otherwin
!= 0 ?
3412 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3413 ((env
->wstate
& 0x7) << 2)));
3415 if (env
->cleanwin
- env
->canrestore
== 0) {
3416 // XXX Clean windows without trap
3417 raise_exception(TT_CLRWIN
);
3426 void helper_restore(void)
3430 cwp
= cwp_inc(env
->cwp
+ 1);
3431 if (env
->canrestore
== 0) {
3432 raise_exception(TT_FILL
| (env
->otherwin
!= 0 ?
3433 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3434 ((env
->wstate
& 0x7) << 2)));
3442 void helper_flushw(void)
3444 if (env
->cansave
!= env
->nwindows
- 2) {
3445 raise_exception(TT_SPILL
| (env
->otherwin
!= 0 ?
3446 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3447 ((env
->wstate
& 0x7) << 2)));
3451 void helper_saved(void)
3454 if (env
->otherwin
== 0)
3460 void helper_restored(void)
3463 if (env
->cleanwin
< env
->nwindows
- 1)
3465 if (env
->otherwin
== 0)
3471 static target_ulong
get_ccr(void)
3477 return ((env
->xcc
>> 20) << 4) | ((psr
& PSR_ICC
) >> 20);
3480 target_ulong
cpu_get_ccr(CPUState
*env1
)
3482 CPUState
*saved_env
;
3492 static void put_ccr(target_ulong val
)
3494 target_ulong tmp
= val
;
3496 env
->xcc
= (tmp
>> 4) << 20;
3497 env
->psr
= (tmp
& 0xf) << 20;
3498 CC_OP
= CC_OP_FLAGS
;
3501 void cpu_put_ccr(CPUState
*env1
, target_ulong val
)
3503 CPUState
*saved_env
;
3511 static target_ulong
get_cwp64(void)
3513 return env
->nwindows
- 1 - env
->cwp
;
3516 target_ulong
cpu_get_cwp64(CPUState
*env1
)
3518 CPUState
*saved_env
;
3528 static void put_cwp64(int cwp
)
3530 if (unlikely(cwp
>= env
->nwindows
|| cwp
< 0)) {
3531 cwp
%= env
->nwindows
;
3533 set_cwp(env
->nwindows
- 1 - cwp
);
3536 void cpu_put_cwp64(CPUState
*env1
, int cwp
)
3538 CPUState
*saved_env
;
3546 target_ulong
helper_rdccr(void)
3551 void helper_wrccr(target_ulong new_ccr
)
3556 // CWP handling is reversed in V9, but we still use the V8 register
3558 target_ulong
helper_rdcwp(void)
3563 void helper_wrcwp(target_ulong new_cwp
)
3568 // This function uses non-native bit order
3569 #define GET_FIELD(X, FROM, TO) \
3570 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
3572 // This function uses the order in the manuals, i.e. bit 0 is 2^0
3573 #define GET_FIELD_SP(X, FROM, TO) \
3574 GET_FIELD(X, 63 - (TO), 63 - (FROM))
3576 target_ulong
helper_array8(target_ulong pixel_addr
, target_ulong cubesize
)
3578 return (GET_FIELD_SP(pixel_addr
, 60, 63) << (17 + 2 * cubesize
)) |
3579 (GET_FIELD_SP(pixel_addr
, 39, 39 + cubesize
- 1) << (17 + cubesize
)) |
3580 (GET_FIELD_SP(pixel_addr
, 17 + cubesize
- 1, 17) << 17) |
3581 (GET_FIELD_SP(pixel_addr
, 56, 59) << 13) |
3582 (GET_FIELD_SP(pixel_addr
, 35, 38) << 9) |
3583 (GET_FIELD_SP(pixel_addr
, 13, 16) << 5) |
3584 (((pixel_addr
>> 55) & 1) << 4) |
3585 (GET_FIELD_SP(pixel_addr
, 33, 34) << 2) |
3586 GET_FIELD_SP(pixel_addr
, 11, 12);
3589 target_ulong
helper_alignaddr(target_ulong addr
, target_ulong offset
)
3593 tmp
= addr
+ offset
;
3595 env
->gsr
|= tmp
& 7ULL;
3599 target_ulong
helper_popc(target_ulong val
)
3601 return ctpop64(val
);
3604 static inline uint64_t *get_gregset(uint32_t pstate
)
3608 DPRINTF_PSTATE("ERROR in get_gregset: active pstate bits=%x%s%s%s\n",
3610 (pstate
& PS_IG
) ? " IG" : "",
3611 (pstate
& PS_MG
) ? " MG" : "",
3612 (pstate
& PS_AG
) ? " AG" : "");
3613 /* pass through to normal set of global registers */
3625 static inline void change_pstate(uint32_t new_pstate
)
3627 uint32_t pstate_regs
, new_pstate_regs
;
3628 uint64_t *src
, *dst
;
3630 if (env
->def
->features
& CPU_FEATURE_GL
) {
3631 // PS_AG is not implemented in this case
3632 new_pstate
&= ~PS_AG
;
3635 pstate_regs
= env
->pstate
& 0xc01;
3636 new_pstate_regs
= new_pstate
& 0xc01;
3638 if (new_pstate_regs
!= pstate_regs
) {
3639 DPRINTF_PSTATE("change_pstate: switching regs old=%x new=%x\n",
3640 pstate_regs
, new_pstate_regs
);
3641 // Switch global register bank
3642 src
= get_gregset(new_pstate_regs
);
3643 dst
= get_gregset(pstate_regs
);
3644 memcpy32(dst
, env
->gregs
);
3645 memcpy32(env
->gregs
, src
);
3648 DPRINTF_PSTATE("change_pstate: regs new=%x (unchanged)\n",
3651 env
->pstate
= new_pstate
;
3654 void helper_wrpstate(target_ulong new_state
)
3656 change_pstate(new_state
& 0xf3f);
3658 #if !defined(CONFIG_USER_ONLY)
3659 if (cpu_interrupts_enabled(env
)) {
3660 cpu_check_irqs(env
);
3665 void helper_wrpil(target_ulong new_pil
)
3667 #if !defined(CONFIG_USER_ONLY)
3668 DPRINTF_PSTATE("helper_wrpil old=%x new=%x\n",
3669 env
->psrpil
, (uint32_t)new_pil
);
3671 env
->psrpil
= new_pil
;
3673 if (cpu_interrupts_enabled(env
)) {
3674 cpu_check_irqs(env
);
3679 void helper_done(void)
3681 trap_state
* tsptr
= cpu_tsptr(env
);
3683 env
->pc
= tsptr
->tnpc
;
3684 env
->npc
= tsptr
->tnpc
+ 4;
3685 put_ccr(tsptr
->tstate
>> 32);
3686 env
->asi
= (tsptr
->tstate
>> 24) & 0xff;
3687 change_pstate((tsptr
->tstate
>> 8) & 0xf3f);
3688 put_cwp64(tsptr
->tstate
& 0xff);
3691 DPRINTF_PSTATE("... helper_done tl=%d\n", env
->tl
);
3693 #if !defined(CONFIG_USER_ONLY)
3694 if (cpu_interrupts_enabled(env
)) {
3695 cpu_check_irqs(env
);
3700 void helper_retry(void)
3702 trap_state
* tsptr
= cpu_tsptr(env
);
3704 env
->pc
= tsptr
->tpc
;
3705 env
->npc
= tsptr
->tnpc
;
3706 put_ccr(tsptr
->tstate
>> 32);
3707 env
->asi
= (tsptr
->tstate
>> 24) & 0xff;
3708 change_pstate((tsptr
->tstate
>> 8) & 0xf3f);
3709 put_cwp64(tsptr
->tstate
& 0xff);
3712 DPRINTF_PSTATE("... helper_retry tl=%d\n", env
->tl
);
3714 #if !defined(CONFIG_USER_ONLY)
3715 if (cpu_interrupts_enabled(env
)) {
3716 cpu_check_irqs(env
);
3721 static void do_modify_softint(const char* operation
, uint32_t value
)
3723 if (env
->softint
!= value
) {
3724 env
->softint
= value
;
3725 DPRINTF_PSTATE(": %s new %08x\n", operation
, env
->softint
);
3726 #if !defined(CONFIG_USER_ONLY)
3727 if (cpu_interrupts_enabled(env
)) {
3728 cpu_check_irqs(env
);
3734 void helper_set_softint(uint64_t value
)
3736 do_modify_softint("helper_set_softint", env
->softint
| (uint32_t)value
);
3739 void helper_clear_softint(uint64_t value
)
3741 do_modify_softint("helper_clear_softint", env
->softint
& (uint32_t)~value
);
3744 void helper_write_softint(uint64_t value
)
3746 do_modify_softint("helper_write_softint", (uint32_t)value
);
3750 void helper_flush(target_ulong addr
)
3753 tb_invalidate_page_range(addr
, addr
+ 8);
3756 #ifdef TARGET_SPARC64
3758 static const char * const excp_names
[0x80] = {
3759 [TT_TFAULT
] = "Instruction Access Fault",
3760 [TT_TMISS
] = "Instruction Access MMU Miss",
3761 [TT_CODE_ACCESS
] = "Instruction Access Error",
3762 [TT_ILL_INSN
] = "Illegal Instruction",
3763 [TT_PRIV_INSN
] = "Privileged Instruction",
3764 [TT_NFPU_INSN
] = "FPU Disabled",
3765 [TT_FP_EXCP
] = "FPU Exception",
3766 [TT_TOVF
] = "Tag Overflow",
3767 [TT_CLRWIN
] = "Clean Windows",
3768 [TT_DIV_ZERO
] = "Division By Zero",
3769 [TT_DFAULT
] = "Data Access Fault",
3770 [TT_DMISS
] = "Data Access MMU Miss",
3771 [TT_DATA_ACCESS
] = "Data Access Error",
3772 [TT_DPROT
] = "Data Protection Error",
3773 [TT_UNALIGNED
] = "Unaligned Memory Access",
3774 [TT_PRIV_ACT
] = "Privileged Action",
3775 [TT_EXTINT
| 0x1] = "External Interrupt 1",
3776 [TT_EXTINT
| 0x2] = "External Interrupt 2",
3777 [TT_EXTINT
| 0x3] = "External Interrupt 3",
3778 [TT_EXTINT
| 0x4] = "External Interrupt 4",
3779 [TT_EXTINT
| 0x5] = "External Interrupt 5",
3780 [TT_EXTINT
| 0x6] = "External Interrupt 6",
3781 [TT_EXTINT
| 0x7] = "External Interrupt 7",
3782 [TT_EXTINT
| 0x8] = "External Interrupt 8",
3783 [TT_EXTINT
| 0x9] = "External Interrupt 9",
3784 [TT_EXTINT
| 0xa] = "External Interrupt 10",
3785 [TT_EXTINT
| 0xb] = "External Interrupt 11",
3786 [TT_EXTINT
| 0xc] = "External Interrupt 12",
3787 [TT_EXTINT
| 0xd] = "External Interrupt 13",
3788 [TT_EXTINT
| 0xe] = "External Interrupt 14",
3789 [TT_EXTINT
| 0xf] = "External Interrupt 15",
3793 trap_state
* cpu_tsptr(CPUState
* env
)
3795 return &env
->ts
[env
->tl
& MAXTL_MASK
];
3798 void do_interrupt(CPUState
*env
)
3800 int intno
= env
->exception_index
;
3804 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
3808 if (intno
< 0 || intno
>= 0x180)
3810 else if (intno
>= 0x100)
3811 name
= "Trap Instruction";
3812 else if (intno
>= 0xc0)
3813 name
= "Window Fill";
3814 else if (intno
>= 0x80)
3815 name
= "Window Spill";
3817 name
= excp_names
[intno
];
3822 qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64
" npc=%016" PRIx64
3823 " SP=%016" PRIx64
"\n",
3826 env
->npc
, env
->regwptr
[6]);
3827 log_cpu_state(env
, 0);
3834 ptr
= (uint8_t *)env
->pc
;
3835 for(i
= 0; i
< 16; i
++) {
3836 qemu_log(" %02x", ldub(ptr
+ i
));
3844 #if !defined(CONFIG_USER_ONLY)
3845 if (env
->tl
>= env
->maxtl
) {
3846 cpu_abort(env
, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
3847 " Error state", env
->exception_index
, env
->tl
, env
->maxtl
);
3851 if (env
->tl
< env
->maxtl
- 1) {
3854 env
->pstate
|= PS_RED
;
3855 if (env
->tl
< env
->maxtl
)
3858 tsptr
= cpu_tsptr(env
);
3860 tsptr
->tstate
= (get_ccr() << 32) |
3861 ((env
->asi
& 0xff) << 24) | ((env
->pstate
& 0xf3f) << 8) |
3863 tsptr
->tpc
= env
->pc
;
3864 tsptr
->tnpc
= env
->npc
;
3869 change_pstate(PS_PEF
| PS_PRIV
| PS_IG
);
3873 case TT_TMISS
... TT_TMISS
+ 3:
3874 case TT_DMISS
... TT_DMISS
+ 3:
3875 case TT_DPROT
... TT_DPROT
+ 3:
3876 change_pstate(PS_PEF
| PS_PRIV
| PS_MG
);
3879 change_pstate(PS_PEF
| PS_PRIV
| PS_AG
);
3883 if (intno
== TT_CLRWIN
) {
3884 set_cwp(cwp_dec(env
->cwp
- 1));
3885 } else if ((intno
& 0x1c0) == TT_SPILL
) {
3886 set_cwp(cwp_dec(env
->cwp
- env
->cansave
- 2));
3887 } else if ((intno
& 0x1c0) == TT_FILL
) {
3888 set_cwp(cwp_inc(env
->cwp
+ 1));
3890 env
->tbr
&= ~0x7fffULL
;
3891 env
->tbr
|= ((env
->tl
> 1) ? 1 << 14 : 0) | (intno
<< 5);
3893 env
->npc
= env
->pc
+ 4;
3894 env
->exception_index
= -1;
3898 static const char * const excp_names
[0x80] = {
3899 [TT_TFAULT
] = "Instruction Access Fault",
3900 [TT_ILL_INSN
] = "Illegal Instruction",
3901 [TT_PRIV_INSN
] = "Privileged Instruction",
3902 [TT_NFPU_INSN
] = "FPU Disabled",
3903 [TT_WIN_OVF
] = "Window Overflow",
3904 [TT_WIN_UNF
] = "Window Underflow",
3905 [TT_UNALIGNED
] = "Unaligned Memory Access",
3906 [TT_FP_EXCP
] = "FPU Exception",
3907 [TT_DFAULT
] = "Data Access Fault",
3908 [TT_TOVF
] = "Tag Overflow",
3909 [TT_EXTINT
| 0x1] = "External Interrupt 1",
3910 [TT_EXTINT
| 0x2] = "External Interrupt 2",
3911 [TT_EXTINT
| 0x3] = "External Interrupt 3",
3912 [TT_EXTINT
| 0x4] = "External Interrupt 4",
3913 [TT_EXTINT
| 0x5] = "External Interrupt 5",
3914 [TT_EXTINT
| 0x6] = "External Interrupt 6",
3915 [TT_EXTINT
| 0x7] = "External Interrupt 7",
3916 [TT_EXTINT
| 0x8] = "External Interrupt 8",
3917 [TT_EXTINT
| 0x9] = "External Interrupt 9",
3918 [TT_EXTINT
| 0xa] = "External Interrupt 10",
3919 [TT_EXTINT
| 0xb] = "External Interrupt 11",
3920 [TT_EXTINT
| 0xc] = "External Interrupt 12",
3921 [TT_EXTINT
| 0xd] = "External Interrupt 13",
3922 [TT_EXTINT
| 0xe] = "External Interrupt 14",
3923 [TT_EXTINT
| 0xf] = "External Interrupt 15",
3924 [TT_TOVF
] = "Tag Overflow",
3925 [TT_CODE_ACCESS
] = "Instruction Access Error",
3926 [TT_DATA_ACCESS
] = "Data Access Error",
3927 [TT_DIV_ZERO
] = "Division By Zero",
3928 [TT_NCP_INSN
] = "Coprocessor Disabled",
3932 void do_interrupt(CPUState
*env
)
3934 int cwp
, intno
= env
->exception_index
;
3937 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
3941 if (intno
< 0 || intno
>= 0x100)
3943 else if (intno
>= 0x80)
3944 name
= "Trap Instruction";
3946 name
= excp_names
[intno
];
3951 qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
3954 env
->npc
, env
->regwptr
[6]);
3955 log_cpu_state(env
, 0);
3962 ptr
= (uint8_t *)env
->pc
;
3963 for(i
= 0; i
< 16; i
++) {
3964 qemu_log(" %02x", ldub(ptr
+ i
));
3972 #if !defined(CONFIG_USER_ONLY)
3973 if (env
->psret
== 0) {
3974 cpu_abort(env
, "Trap 0x%02x while interrupts disabled, Error state",
3975 env
->exception_index
);
3980 cwp
= cwp_dec(env
->cwp
- 1);
3982 env
->regwptr
[9] = env
->pc
;
3983 env
->regwptr
[10] = env
->npc
;
3984 env
->psrps
= env
->psrs
;
3986 env
->tbr
= (env
->tbr
& TBR_BASE_MASK
) | (intno
<< 4);
3988 env
->npc
= env
->pc
+ 4;
3989 env
->exception_index
= -1;
3993 #if !defined(CONFIG_USER_ONLY)
3995 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
3998 #define MMUSUFFIX _mmu
3999 #define ALIGNED_ONLY
4002 #include "softmmu_template.h"
4005 #include "softmmu_template.h"
4008 #include "softmmu_template.h"
4011 #include "softmmu_template.h"
4013 /* XXX: make it generic ? */
4014 static void cpu_restore_state2(void *retaddr
)
4016 TranslationBlock
*tb
;
4020 /* now we have a real cpu fault */
4021 pc
= (unsigned long)retaddr
;
4022 tb
= tb_find_pc(pc
);
4024 /* the PC is inside the translated code. It means that we have
4025 a virtual CPU fault */
4026 cpu_restore_state(tb
, env
, pc
, (void *)(long)env
->cond
);
4031 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
4034 #ifdef DEBUG_UNALIGNED
4035 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
4036 "\n", addr
, env
->pc
);
4038 cpu_restore_state2(retaddr
);
4039 raise_exception(TT_UNALIGNED
);
4042 /* try to fill the TLB and return an exception if error. If retaddr is
4043 NULL, it means that the function was called in C code (i.e. not
4044 from generated code or from helper.c) */
4045 /* XXX: fix it to restore all registers */
4046 void tlb_fill(target_ulong addr
, int is_write
, int mmu_idx
, void *retaddr
)
4049 CPUState
*saved_env
;
4051 /* XXX: hack to restore env in all cases, even if not called from
4054 env
= cpu_single_env
;
4056 ret
= cpu_sparc_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
, 1);
4058 cpu_restore_state2(retaddr
);
4064 #endif /* !CONFIG_USER_ONLY */
4066 #ifndef TARGET_SPARC64
4067 #if !defined(CONFIG_USER_ONLY)
4068 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
4069 int is_asi
, int size
)
4071 CPUState
*saved_env
;
4074 /* XXX: hack to restore env in all cases, even if not called from
4077 env
= cpu_single_env
;
4078 #ifdef DEBUG_UNASSIGNED
4080 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
4081 " asi 0x%02x from " TARGET_FMT_lx
"\n",
4082 is_exec
? "exec" : is_write
? "write" : "read", size
,
4083 size
== 1 ? "" : "s", addr
, is_asi
, env
->pc
);
4085 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
4086 " from " TARGET_FMT_lx
"\n",
4087 is_exec
? "exec" : is_write
? "write" : "read", size
,
4088 size
== 1 ? "" : "s", addr
, env
->pc
);
4090 /* Don't overwrite translation and access faults */
4091 fault_type
= (env
->mmuregs
[3] & 0x1c) >> 2;
4092 if ((fault_type
> 4) || (fault_type
== 0)) {
4093 env
->mmuregs
[3] = 0; /* Fault status register */
4095 env
->mmuregs
[3] |= 1 << 16;
4097 env
->mmuregs
[3] |= 1 << 5;
4099 env
->mmuregs
[3] |= 1 << 6;
4101 env
->mmuregs
[3] |= 1 << 7;
4102 env
->mmuregs
[3] |= (5 << 2) | 2;
4103 /* SuperSPARC will never place instruction fault addresses in the FAR */
4105 env
->mmuregs
[4] = addr
; /* Fault address register */
4108 /* overflow (same type fault was not read before another fault) */
4109 if (fault_type
== ((env
->mmuregs
[3] & 0x1c)) >> 2) {
4110 env
->mmuregs
[3] |= 1;
4113 if ((env
->mmuregs
[0] & MMU_E
) && !(env
->mmuregs
[0] & MMU_NF
)) {
4115 raise_exception(TT_CODE_ACCESS
);
4117 raise_exception(TT_DATA_ACCESS
);
4120 /* flush neverland mappings created during no-fault mode,
4121 so the sequential MMU faults report proper fault types */
4122 if (env
->mmuregs
[0] & MMU_NF
) {
4130 #if defined(CONFIG_USER_ONLY)
4131 static void do_unassigned_access(target_ulong addr
, int is_write
, int is_exec
,
4132 int is_asi
, int size
)
4134 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
4135 int is_asi
, int size
)
4138 CPUState
*saved_env
;
4140 /* XXX: hack to restore env in all cases, even if not called from
4143 env
= cpu_single_env
;
4145 #ifdef DEBUG_UNASSIGNED
4146 printf("Unassigned mem access to " TARGET_FMT_plx
" from " TARGET_FMT_lx
4147 "\n", addr
, env
->pc
);
4151 raise_exception(TT_CODE_ACCESS
);
4153 raise_exception(TT_DATA_ACCESS
);
4160 #ifdef TARGET_SPARC64
4161 void helper_tick_set_count(void *opaque
, uint64_t count
)
4163 #if !defined(CONFIG_USER_ONLY)
4164 cpu_tick_set_count(opaque
, count
);
4168 uint64_t helper_tick_get_count(void *opaque
)
4170 #if !defined(CONFIG_USER_ONLY)
4171 return cpu_tick_get_count(opaque
);
4177 void helper_tick_set_limit(void *opaque
, uint64_t limit
)
4179 #if !defined(CONFIG_USER_ONLY)
4180 cpu_tick_set_limit(opaque
, limit
);