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Merge remote branch 'mst/for_anthony' into staging
[qemu.git] / target-sparc / op_helper.c
1 #include "exec.h"
2 #include "host-utils.h"
3 #include "helper.h"
4
5 //#define DEBUG_MMU
6 //#define DEBUG_MXCC
7 //#define DEBUG_UNALIGNED
8 //#define DEBUG_UNASSIGNED
9 //#define DEBUG_ASI
10 //#define DEBUG_PCALL
11 //#define DEBUG_PSTATE
12
13 #ifdef DEBUG_MMU
14 #define DPRINTF_MMU(fmt, ...) \
15 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
16 #else
17 #define DPRINTF_MMU(fmt, ...) do {} while (0)
18 #endif
19
20 #ifdef DEBUG_MXCC
21 #define DPRINTF_MXCC(fmt, ...) \
22 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
23 #else
24 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
25 #endif
26
27 #ifdef DEBUG_ASI
28 #define DPRINTF_ASI(fmt, ...) \
29 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
30 #endif
31
32 #ifdef DEBUG_PSTATE
33 #define DPRINTF_PSTATE(fmt, ...) \
34 do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
35 #else
36 #define DPRINTF_PSTATE(fmt, ...) do {} while (0)
37 #endif
38
39 #ifdef TARGET_SPARC64
40 #ifndef TARGET_ABI32
41 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
42 #else
43 #define AM_CHECK(env1) (1)
44 #endif
45 #endif
46
47 #define DT0 (env->dt0)
48 #define DT1 (env->dt1)
49 #define QT0 (env->qt0)
50 #define QT1 (env->qt1)
51
52 #if defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
53 static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
54 int is_asi, int size);
55 #endif
56
57 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
58 // Calculates TSB pointer value for fault page size 8k or 64k
59 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
60 uint64_t tag_access_register,
61 int page_size)
62 {
63 uint64_t tsb_base = tsb_register & ~0x1fffULL;
64 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
65 int tsb_size = tsb_register & 0xf;
66
67 // discard lower 13 bits which hold tag access context
68 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
69
70 // now reorder bits
71 uint64_t tsb_base_mask = ~0x1fffULL;
72 uint64_t va = tag_access_va;
73
74 // move va bits to correct position
75 if (page_size == 8*1024) {
76 va >>= 9;
77 } else if (page_size == 64*1024) {
78 va >>= 12;
79 }
80
81 if (tsb_size) {
82 tsb_base_mask <<= tsb_size;
83 }
84
85 // calculate tsb_base mask and adjust va if split is in use
86 if (tsb_split) {
87 if (page_size == 8*1024) {
88 va &= ~(1ULL << (13 + tsb_size));
89 } else if (page_size == 64*1024) {
90 va |= (1ULL << (13 + tsb_size));
91 }
92 tsb_base_mask <<= 1;
93 }
94
95 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
96 }
97
98 // Calculates tag target register value by reordering bits
99 // in tag access register
100 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
101 {
102 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
103 }
104
105 static void replace_tlb_entry(SparcTLBEntry *tlb,
106 uint64_t tlb_tag, uint64_t tlb_tte,
107 CPUState *env1)
108 {
109 target_ulong mask, size, va, offset;
110
111 // flush page range if translation is valid
112 if (TTE_IS_VALID(tlb->tte)) {
113
114 mask = 0xffffffffffffe000ULL;
115 mask <<= 3 * ((tlb->tte >> 61) & 3);
116 size = ~mask + 1;
117
118 va = tlb->tag & mask;
119
120 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
121 tlb_flush_page(env1, va + offset);
122 }
123 }
124
125 tlb->tag = tlb_tag;
126 tlb->tte = tlb_tte;
127 }
128
129 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
130 const char* strmmu, CPUState *env1)
131 {
132 unsigned int i;
133 target_ulong mask;
134 uint64_t context;
135
136 int is_demap_context = (demap_addr >> 6) & 1;
137
138 // demap context
139 switch ((demap_addr >> 4) & 3) {
140 case 0: // primary
141 context = env1->dmmu.mmu_primary_context;
142 break;
143 case 1: // secondary
144 context = env1->dmmu.mmu_secondary_context;
145 break;
146 case 2: // nucleus
147 context = 0;
148 break;
149 case 3: // reserved
150 default:
151 return;
152 }
153
154 for (i = 0; i < 64; i++) {
155 if (TTE_IS_VALID(tlb[i].tte)) {
156
157 if (is_demap_context) {
158 // will remove non-global entries matching context value
159 if (TTE_IS_GLOBAL(tlb[i].tte) ||
160 !tlb_compare_context(&tlb[i], context)) {
161 continue;
162 }
163 } else {
164 // demap page
165 // will remove any entry matching VA
166 mask = 0xffffffffffffe000ULL;
167 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
168
169 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
170 continue;
171 }
172
173 // entry should be global or matching context value
174 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
175 !tlb_compare_context(&tlb[i], context)) {
176 continue;
177 }
178 }
179
180 replace_tlb_entry(&tlb[i], 0, 0, env1);
181 #ifdef DEBUG_MMU
182 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
183 dump_mmu(stdout, fprintf, env1);
184 #endif
185 }
186 }
187 }
188
189 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
190 uint64_t tlb_tag, uint64_t tlb_tte,
191 const char* strmmu, CPUState *env1)
192 {
193 unsigned int i, replace_used;
194
195 // Try replacing invalid entry
196 for (i = 0; i < 64; i++) {
197 if (!TTE_IS_VALID(tlb[i].tte)) {
198 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
199 #ifdef DEBUG_MMU
200 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
201 dump_mmu(stdout, fprintf, env1);
202 #endif
203 return;
204 }
205 }
206
207 // All entries are valid, try replacing unlocked entry
208
209 for (replace_used = 0; replace_used < 2; ++replace_used) {
210
211 // Used entries are not replaced on first pass
212
213 for (i = 0; i < 64; i++) {
214 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
215
216 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
217 #ifdef DEBUG_MMU
218 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
219 strmmu, (replace_used?"used":"unused"), i);
220 dump_mmu(stdout, fprintf, env1);
221 #endif
222 return;
223 }
224 }
225
226 // Now reset used bit and search for unused entries again
227
228 for (i = 0; i < 64; i++) {
229 TTE_SET_UNUSED(tlb[i].tte);
230 }
231 }
232
233 #ifdef DEBUG_MMU
234 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
235 #endif
236 // error state?
237 }
238
239 #endif
240
241 static inline target_ulong address_mask(CPUState *env1, target_ulong addr)
242 {
243 #ifdef TARGET_SPARC64
244 if (AM_CHECK(env1))
245 addr &= 0xffffffffULL;
246 #endif
247 return addr;
248 }
249
250 /* returns true if access using this ASI is to have address translated by MMU
251 otherwise access is to raw physical address */
252 static inline int is_translating_asi(int asi)
253 {
254 #ifdef TARGET_SPARC64
255 /* Ultrasparc IIi translating asi
256 - note this list is defined by cpu implementation
257 */
258 switch (asi) {
259 case 0x04 ... 0x11:
260 case 0x18 ... 0x19:
261 case 0x24 ... 0x2C:
262 case 0x70 ... 0x73:
263 case 0x78 ... 0x79:
264 case 0x80 ... 0xFF:
265 return 1;
266
267 default:
268 return 0;
269 }
270 #else
271 /* TODO: check sparc32 bits */
272 return 0;
273 #endif
274 }
275
276 static inline target_ulong asi_address_mask(CPUState *env1,
277 int asi, target_ulong addr)
278 {
279 if (is_translating_asi(asi)) {
280 return address_mask(env, addr);
281 } else {
282 return addr;
283 }
284 }
285
286 static void raise_exception(int tt)
287 {
288 env->exception_index = tt;
289 cpu_loop_exit();
290 }
291
292 void HELPER(raise_exception)(int tt)
293 {
294 raise_exception(tt);
295 }
296
297 void helper_check_align(target_ulong addr, uint32_t align)
298 {
299 if (addr & align) {
300 #ifdef DEBUG_UNALIGNED
301 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
302 "\n", addr, env->pc);
303 #endif
304 raise_exception(TT_UNALIGNED);
305 }
306 }
307
308 #define F_HELPER(name, p) void helper_f##name##p(void)
309
310 #define F_BINOP(name) \
311 float32 helper_f ## name ## s (float32 src1, float32 src2) \
312 { \
313 return float32_ ## name (src1, src2, &env->fp_status); \
314 } \
315 F_HELPER(name, d) \
316 { \
317 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
318 } \
319 F_HELPER(name, q) \
320 { \
321 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
322 }
323
324 F_BINOP(add);
325 F_BINOP(sub);
326 F_BINOP(mul);
327 F_BINOP(div);
328 #undef F_BINOP
329
330 void helper_fsmuld(float32 src1, float32 src2)
331 {
332 DT0 = float64_mul(float32_to_float64(src1, &env->fp_status),
333 float32_to_float64(src2, &env->fp_status),
334 &env->fp_status);
335 }
336
337 void helper_fdmulq(void)
338 {
339 QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
340 float64_to_float128(DT1, &env->fp_status),
341 &env->fp_status);
342 }
343
344 float32 helper_fnegs(float32 src)
345 {
346 return float32_chs(src);
347 }
348
349 #ifdef TARGET_SPARC64
350 F_HELPER(neg, d)
351 {
352 DT0 = float64_chs(DT1);
353 }
354
355 F_HELPER(neg, q)
356 {
357 QT0 = float128_chs(QT1);
358 }
359 #endif
360
361 /* Integer to float conversion. */
362 float32 helper_fitos(int32_t src)
363 {
364 return int32_to_float32(src, &env->fp_status);
365 }
366
367 void helper_fitod(int32_t src)
368 {
369 DT0 = int32_to_float64(src, &env->fp_status);
370 }
371
372 void helper_fitoq(int32_t src)
373 {
374 QT0 = int32_to_float128(src, &env->fp_status);
375 }
376
377 #ifdef TARGET_SPARC64
378 float32 helper_fxtos(void)
379 {
380 return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
381 }
382
383 F_HELPER(xto, d)
384 {
385 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
386 }
387
388 F_HELPER(xto, q)
389 {
390 QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
391 }
392 #endif
393 #undef F_HELPER
394
395 /* floating point conversion */
396 float32 helper_fdtos(void)
397 {
398 return float64_to_float32(DT1, &env->fp_status);
399 }
400
401 void helper_fstod(float32 src)
402 {
403 DT0 = float32_to_float64(src, &env->fp_status);
404 }
405
406 float32 helper_fqtos(void)
407 {
408 return float128_to_float32(QT1, &env->fp_status);
409 }
410
411 void helper_fstoq(float32 src)
412 {
413 QT0 = float32_to_float128(src, &env->fp_status);
414 }
415
416 void helper_fqtod(void)
417 {
418 DT0 = float128_to_float64(QT1, &env->fp_status);
419 }
420
421 void helper_fdtoq(void)
422 {
423 QT0 = float64_to_float128(DT1, &env->fp_status);
424 }
425
426 /* Float to integer conversion. */
427 int32_t helper_fstoi(float32 src)
428 {
429 return float32_to_int32_round_to_zero(src, &env->fp_status);
430 }
431
432 int32_t helper_fdtoi(void)
433 {
434 return float64_to_int32_round_to_zero(DT1, &env->fp_status);
435 }
436
437 int32_t helper_fqtoi(void)
438 {
439 return float128_to_int32_round_to_zero(QT1, &env->fp_status);
440 }
441
442 #ifdef TARGET_SPARC64
443 void helper_fstox(float32 src)
444 {
445 *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status);
446 }
447
448 void helper_fdtox(void)
449 {
450 *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
451 }
452
453 void helper_fqtox(void)
454 {
455 *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
456 }
457
458 void helper_faligndata(void)
459 {
460 uint64_t tmp;
461
462 tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
463 /* on many architectures a shift of 64 does nothing */
464 if ((env->gsr & 7) != 0) {
465 tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
466 }
467 *((uint64_t *)&DT0) = tmp;
468 }
469
470 #ifdef HOST_WORDS_BIGENDIAN
471 #define VIS_B64(n) b[7 - (n)]
472 #define VIS_W64(n) w[3 - (n)]
473 #define VIS_SW64(n) sw[3 - (n)]
474 #define VIS_L64(n) l[1 - (n)]
475 #define VIS_B32(n) b[3 - (n)]
476 #define VIS_W32(n) w[1 - (n)]
477 #else
478 #define VIS_B64(n) b[n]
479 #define VIS_W64(n) w[n]
480 #define VIS_SW64(n) sw[n]
481 #define VIS_L64(n) l[n]
482 #define VIS_B32(n) b[n]
483 #define VIS_W32(n) w[n]
484 #endif
485
486 typedef union {
487 uint8_t b[8];
488 uint16_t w[4];
489 int16_t sw[4];
490 uint32_t l[2];
491 float64 d;
492 } vis64;
493
494 typedef union {
495 uint8_t b[4];
496 uint16_t w[2];
497 uint32_t l;
498 float32 f;
499 } vis32;
500
501 void helper_fpmerge(void)
502 {
503 vis64 s, d;
504
505 s.d = DT0;
506 d.d = DT1;
507
508 // Reverse calculation order to handle overlap
509 d.VIS_B64(7) = s.VIS_B64(3);
510 d.VIS_B64(6) = d.VIS_B64(3);
511 d.VIS_B64(5) = s.VIS_B64(2);
512 d.VIS_B64(4) = d.VIS_B64(2);
513 d.VIS_B64(3) = s.VIS_B64(1);
514 d.VIS_B64(2) = d.VIS_B64(1);
515 d.VIS_B64(1) = s.VIS_B64(0);
516 //d.VIS_B64(0) = d.VIS_B64(0);
517
518 DT0 = d.d;
519 }
520
521 void helper_fmul8x16(void)
522 {
523 vis64 s, d;
524 uint32_t tmp;
525
526 s.d = DT0;
527 d.d = DT1;
528
529 #define PMUL(r) \
530 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
531 if ((tmp & 0xff) > 0x7f) \
532 tmp += 0x100; \
533 d.VIS_W64(r) = tmp >> 8;
534
535 PMUL(0);
536 PMUL(1);
537 PMUL(2);
538 PMUL(3);
539 #undef PMUL
540
541 DT0 = d.d;
542 }
543
544 void helper_fmul8x16al(void)
545 {
546 vis64 s, d;
547 uint32_t tmp;
548
549 s.d = DT0;
550 d.d = DT1;
551
552 #define PMUL(r) \
553 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
554 if ((tmp & 0xff) > 0x7f) \
555 tmp += 0x100; \
556 d.VIS_W64(r) = tmp >> 8;
557
558 PMUL(0);
559 PMUL(1);
560 PMUL(2);
561 PMUL(3);
562 #undef PMUL
563
564 DT0 = d.d;
565 }
566
567 void helper_fmul8x16au(void)
568 {
569 vis64 s, d;
570 uint32_t tmp;
571
572 s.d = DT0;
573 d.d = DT1;
574
575 #define PMUL(r) \
576 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
577 if ((tmp & 0xff) > 0x7f) \
578 tmp += 0x100; \
579 d.VIS_W64(r) = tmp >> 8;
580
581 PMUL(0);
582 PMUL(1);
583 PMUL(2);
584 PMUL(3);
585 #undef PMUL
586
587 DT0 = d.d;
588 }
589
590 void helper_fmul8sux16(void)
591 {
592 vis64 s, d;
593 uint32_t tmp;
594
595 s.d = DT0;
596 d.d = DT1;
597
598 #define PMUL(r) \
599 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
600 if ((tmp & 0xff) > 0x7f) \
601 tmp += 0x100; \
602 d.VIS_W64(r) = tmp >> 8;
603
604 PMUL(0);
605 PMUL(1);
606 PMUL(2);
607 PMUL(3);
608 #undef PMUL
609
610 DT0 = d.d;
611 }
612
613 void helper_fmul8ulx16(void)
614 {
615 vis64 s, d;
616 uint32_t tmp;
617
618 s.d = DT0;
619 d.d = DT1;
620
621 #define PMUL(r) \
622 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
623 if ((tmp & 0xff) > 0x7f) \
624 tmp += 0x100; \
625 d.VIS_W64(r) = tmp >> 8;
626
627 PMUL(0);
628 PMUL(1);
629 PMUL(2);
630 PMUL(3);
631 #undef PMUL
632
633 DT0 = d.d;
634 }
635
636 void helper_fmuld8sux16(void)
637 {
638 vis64 s, d;
639 uint32_t tmp;
640
641 s.d = DT0;
642 d.d = DT1;
643
644 #define PMUL(r) \
645 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
646 if ((tmp & 0xff) > 0x7f) \
647 tmp += 0x100; \
648 d.VIS_L64(r) = tmp;
649
650 // Reverse calculation order to handle overlap
651 PMUL(1);
652 PMUL(0);
653 #undef PMUL
654
655 DT0 = d.d;
656 }
657
658 void helper_fmuld8ulx16(void)
659 {
660 vis64 s, d;
661 uint32_t tmp;
662
663 s.d = DT0;
664 d.d = DT1;
665
666 #define PMUL(r) \
667 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
668 if ((tmp & 0xff) > 0x7f) \
669 tmp += 0x100; \
670 d.VIS_L64(r) = tmp;
671
672 // Reverse calculation order to handle overlap
673 PMUL(1);
674 PMUL(0);
675 #undef PMUL
676
677 DT0 = d.d;
678 }
679
680 void helper_fexpand(void)
681 {
682 vis32 s;
683 vis64 d;
684
685 s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
686 d.d = DT1;
687 d.VIS_W64(0) = s.VIS_B32(0) << 4;
688 d.VIS_W64(1) = s.VIS_B32(1) << 4;
689 d.VIS_W64(2) = s.VIS_B32(2) << 4;
690 d.VIS_W64(3) = s.VIS_B32(3) << 4;
691
692 DT0 = d.d;
693 }
694
695 #define VIS_HELPER(name, F) \
696 void name##16(void) \
697 { \
698 vis64 s, d; \
699 \
700 s.d = DT0; \
701 d.d = DT1; \
702 \
703 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
704 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
705 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
706 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
707 \
708 DT0 = d.d; \
709 } \
710 \
711 uint32_t name##16s(uint32_t src1, uint32_t src2) \
712 { \
713 vis32 s, d; \
714 \
715 s.l = src1; \
716 d.l = src2; \
717 \
718 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
719 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
720 \
721 return d.l; \
722 } \
723 \
724 void name##32(void) \
725 { \
726 vis64 s, d; \
727 \
728 s.d = DT0; \
729 d.d = DT1; \
730 \
731 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
732 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
733 \
734 DT0 = d.d; \
735 } \
736 \
737 uint32_t name##32s(uint32_t src1, uint32_t src2) \
738 { \
739 vis32 s, d; \
740 \
741 s.l = src1; \
742 d.l = src2; \
743 \
744 d.l = F(d.l, s.l); \
745 \
746 return d.l; \
747 }
748
749 #define FADD(a, b) ((a) + (b))
750 #define FSUB(a, b) ((a) - (b))
751 VIS_HELPER(helper_fpadd, FADD)
752 VIS_HELPER(helper_fpsub, FSUB)
753
754 #define VIS_CMPHELPER(name, F) \
755 void name##16(void) \
756 { \
757 vis64 s, d; \
758 \
759 s.d = DT0; \
760 d.d = DT1; \
761 \
762 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
763 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
764 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
765 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
766 \
767 DT0 = d.d; \
768 } \
769 \
770 void name##32(void) \
771 { \
772 vis64 s, d; \
773 \
774 s.d = DT0; \
775 d.d = DT1; \
776 \
777 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
778 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
779 \
780 DT0 = d.d; \
781 }
782
783 #define FCMPGT(a, b) ((a) > (b))
784 #define FCMPEQ(a, b) ((a) == (b))
785 #define FCMPLE(a, b) ((a) <= (b))
786 #define FCMPNE(a, b) ((a) != (b))
787
788 VIS_CMPHELPER(helper_fcmpgt, FCMPGT)
789 VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
790 VIS_CMPHELPER(helper_fcmple, FCMPLE)
791 VIS_CMPHELPER(helper_fcmpne, FCMPNE)
792 #endif
793
794 void helper_check_ieee_exceptions(void)
795 {
796 target_ulong status;
797
798 status = get_float_exception_flags(&env->fp_status);
799 if (status) {
800 /* Copy IEEE 754 flags into FSR */
801 if (status & float_flag_invalid)
802 env->fsr |= FSR_NVC;
803 if (status & float_flag_overflow)
804 env->fsr |= FSR_OFC;
805 if (status & float_flag_underflow)
806 env->fsr |= FSR_UFC;
807 if (status & float_flag_divbyzero)
808 env->fsr |= FSR_DZC;
809 if (status & float_flag_inexact)
810 env->fsr |= FSR_NXC;
811
812 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
813 /* Unmasked exception, generate a trap */
814 env->fsr |= FSR_FTT_IEEE_EXCP;
815 raise_exception(TT_FP_EXCP);
816 } else {
817 /* Accumulate exceptions */
818 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
819 }
820 }
821 }
822
823 void helper_clear_float_exceptions(void)
824 {
825 set_float_exception_flags(0, &env->fp_status);
826 }
827
828 float32 helper_fabss(float32 src)
829 {
830 return float32_abs(src);
831 }
832
833 #ifdef TARGET_SPARC64
834 void helper_fabsd(void)
835 {
836 DT0 = float64_abs(DT1);
837 }
838
839 void helper_fabsq(void)
840 {
841 QT0 = float128_abs(QT1);
842 }
843 #endif
844
845 float32 helper_fsqrts(float32 src)
846 {
847 return float32_sqrt(src, &env->fp_status);
848 }
849
850 void helper_fsqrtd(void)
851 {
852 DT0 = float64_sqrt(DT1, &env->fp_status);
853 }
854
855 void helper_fsqrtq(void)
856 {
857 QT0 = float128_sqrt(QT1, &env->fp_status);
858 }
859
860 #define GEN_FCMP(name, size, reg1, reg2, FS, E) \
861 void glue(helper_, name) (void) \
862 { \
863 env->fsr &= FSR_FTT_NMASK; \
864 if (E && (glue(size, _is_any_nan)(reg1) || \
865 glue(size, _is_any_nan)(reg2)) && \
866 (env->fsr & FSR_NVM)) { \
867 env->fsr |= FSR_NVC; \
868 env->fsr |= FSR_FTT_IEEE_EXCP; \
869 raise_exception(TT_FP_EXCP); \
870 } \
871 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
872 case float_relation_unordered: \
873 if ((env->fsr & FSR_NVM)) { \
874 env->fsr |= FSR_NVC; \
875 env->fsr |= FSR_FTT_IEEE_EXCP; \
876 raise_exception(TT_FP_EXCP); \
877 } else { \
878 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
879 env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
880 env->fsr |= FSR_NVA; \
881 } \
882 break; \
883 case float_relation_less: \
884 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
885 env->fsr |= FSR_FCC0 << FS; \
886 break; \
887 case float_relation_greater: \
888 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
889 env->fsr |= FSR_FCC1 << FS; \
890 break; \
891 default: \
892 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
893 break; \
894 } \
895 }
896 #define GEN_FCMPS(name, size, FS, E) \
897 void glue(helper_, name)(float32 src1, float32 src2) \
898 { \
899 env->fsr &= FSR_FTT_NMASK; \
900 if (E && (glue(size, _is_any_nan)(src1) || \
901 glue(size, _is_any_nan)(src2)) && \
902 (env->fsr & FSR_NVM)) { \
903 env->fsr |= FSR_NVC; \
904 env->fsr |= FSR_FTT_IEEE_EXCP; \
905 raise_exception(TT_FP_EXCP); \
906 } \
907 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
908 case float_relation_unordered: \
909 if ((env->fsr & FSR_NVM)) { \
910 env->fsr |= FSR_NVC; \
911 env->fsr |= FSR_FTT_IEEE_EXCP; \
912 raise_exception(TT_FP_EXCP); \
913 } else { \
914 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
915 env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
916 env->fsr |= FSR_NVA; \
917 } \
918 break; \
919 case float_relation_less: \
920 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
921 env->fsr |= FSR_FCC0 << FS; \
922 break; \
923 case float_relation_greater: \
924 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
925 env->fsr |= FSR_FCC1 << FS; \
926 break; \
927 default: \
928 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
929 break; \
930 } \
931 }
932
933 GEN_FCMPS(fcmps, float32, 0, 0);
934 GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
935
936 GEN_FCMPS(fcmpes, float32, 0, 1);
937 GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
938
939 GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
940 GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
941
942 static uint32_t compute_all_flags(void)
943 {
944 return env->psr & PSR_ICC;
945 }
946
947 static uint32_t compute_C_flags(void)
948 {
949 return env->psr & PSR_CARRY;
950 }
951
952 static inline uint32_t get_NZ_icc(int32_t dst)
953 {
954 uint32_t ret = 0;
955
956 if (dst == 0) {
957 ret = PSR_ZERO;
958 } else if (dst < 0) {
959 ret = PSR_NEG;
960 }
961 return ret;
962 }
963
964 #ifdef TARGET_SPARC64
965 static uint32_t compute_all_flags_xcc(void)
966 {
967 return env->xcc & PSR_ICC;
968 }
969
970 static uint32_t compute_C_flags_xcc(void)
971 {
972 return env->xcc & PSR_CARRY;
973 }
974
975 static inline uint32_t get_NZ_xcc(target_long dst)
976 {
977 uint32_t ret = 0;
978
979 if (!dst) {
980 ret = PSR_ZERO;
981 } else if (dst < 0) {
982 ret = PSR_NEG;
983 }
984 return ret;
985 }
986 #endif
987
988 static inline uint32_t get_V_div_icc(target_ulong src2)
989 {
990 uint32_t ret = 0;
991
992 if (src2 != 0) {
993 ret = PSR_OVF;
994 }
995 return ret;
996 }
997
998 static uint32_t compute_all_div(void)
999 {
1000 uint32_t ret;
1001
1002 ret = get_NZ_icc(CC_DST);
1003 ret |= get_V_div_icc(CC_SRC2);
1004 return ret;
1005 }
1006
1007 static uint32_t compute_C_div(void)
1008 {
1009 return 0;
1010 }
1011
1012 static inline uint32_t get_C_add_icc(uint32_t dst, uint32_t src1)
1013 {
1014 uint32_t ret = 0;
1015
1016 if (dst < src1) {
1017 ret = PSR_CARRY;
1018 }
1019 return ret;
1020 }
1021
1022 static inline uint32_t get_C_addx_icc(uint32_t dst, uint32_t src1,
1023 uint32_t src2)
1024 {
1025 uint32_t ret = 0;
1026
1027 if (((src1 & src2) | (~dst & (src1 | src2))) & (1U << 31)) {
1028 ret = PSR_CARRY;
1029 }
1030 return ret;
1031 }
1032
1033 static inline uint32_t get_V_add_icc(uint32_t dst, uint32_t src1,
1034 uint32_t src2)
1035 {
1036 uint32_t ret = 0;
1037
1038 if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1U << 31)) {
1039 ret = PSR_OVF;
1040 }
1041 return ret;
1042 }
1043
1044 #ifdef TARGET_SPARC64
1045 static inline uint32_t get_C_add_xcc(target_ulong dst, target_ulong src1)
1046 {
1047 uint32_t ret = 0;
1048
1049 if (dst < src1) {
1050 ret = PSR_CARRY;
1051 }
1052 return ret;
1053 }
1054
1055 static inline uint32_t get_C_addx_xcc(target_ulong dst, target_ulong src1,
1056 target_ulong src2)
1057 {
1058 uint32_t ret = 0;
1059
1060 if (((src1 & src2) | (~dst & (src1 | src2))) & (1ULL << 63)) {
1061 ret = PSR_CARRY;
1062 }
1063 return ret;
1064 }
1065
1066 static inline uint32_t get_V_add_xcc(target_ulong dst, target_ulong src1,
1067 target_ulong src2)
1068 {
1069 uint32_t ret = 0;
1070
1071 if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1ULL << 63)) {
1072 ret = PSR_OVF;
1073 }
1074 return ret;
1075 }
1076
1077 static uint32_t compute_all_add_xcc(void)
1078 {
1079 uint32_t ret;
1080
1081 ret = get_NZ_xcc(CC_DST);
1082 ret |= get_C_add_xcc(CC_DST, CC_SRC);
1083 ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2);
1084 return ret;
1085 }
1086
1087 static uint32_t compute_C_add_xcc(void)
1088 {
1089 return get_C_add_xcc(CC_DST, CC_SRC);
1090 }
1091 #endif
1092
1093 static uint32_t compute_all_add(void)
1094 {
1095 uint32_t ret;
1096
1097 ret = get_NZ_icc(CC_DST);
1098 ret |= get_C_add_icc(CC_DST, CC_SRC);
1099 ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2);
1100 return ret;
1101 }
1102
1103 static uint32_t compute_C_add(void)
1104 {
1105 return get_C_add_icc(CC_DST, CC_SRC);
1106 }
1107
1108 #ifdef TARGET_SPARC64
1109 static uint32_t compute_all_addx_xcc(void)
1110 {
1111 uint32_t ret;
1112
1113 ret = get_NZ_xcc(CC_DST);
1114 ret |= get_C_addx_xcc(CC_DST, CC_SRC, CC_SRC2);
1115 ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2);
1116 return ret;
1117 }
1118
1119 static uint32_t compute_C_addx_xcc(void)
1120 {
1121 uint32_t ret;
1122
1123 ret = get_C_addx_xcc(CC_DST, CC_SRC, CC_SRC2);
1124 return ret;
1125 }
1126 #endif
1127
1128 static uint32_t compute_all_addx(void)
1129 {
1130 uint32_t ret;
1131
1132 ret = get_NZ_icc(CC_DST);
1133 ret |= get_C_addx_icc(CC_DST, CC_SRC, CC_SRC2);
1134 ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2);
1135 return ret;
1136 }
1137
1138 static uint32_t compute_C_addx(void)
1139 {
1140 uint32_t ret;
1141
1142 ret = get_C_addx_icc(CC_DST, CC_SRC, CC_SRC2);
1143 return ret;
1144 }
1145
1146 static inline uint32_t get_V_tag_icc(target_ulong src1, target_ulong src2)
1147 {
1148 uint32_t ret = 0;
1149
1150 if ((src1 | src2) & 0x3) {
1151 ret = PSR_OVF;
1152 }
1153 return ret;
1154 }
1155
1156 static uint32_t compute_all_tadd(void)
1157 {
1158 uint32_t ret;
1159
1160 ret = get_NZ_icc(CC_DST);
1161 ret |= get_C_add_icc(CC_DST, CC_SRC);
1162 ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2);
1163 ret |= get_V_tag_icc(CC_SRC, CC_SRC2);
1164 return ret;
1165 }
1166
1167 static uint32_t compute_all_taddtv(void)
1168 {
1169 uint32_t ret;
1170
1171 ret = get_NZ_icc(CC_DST);
1172 ret |= get_C_add_icc(CC_DST, CC_SRC);
1173 return ret;
1174 }
1175
1176 static inline uint32_t get_C_sub_icc(uint32_t src1, uint32_t src2)
1177 {
1178 uint32_t ret = 0;
1179
1180 if (src1 < src2) {
1181 ret = PSR_CARRY;
1182 }
1183 return ret;
1184 }
1185
1186 static inline uint32_t get_C_subx_icc(uint32_t dst, uint32_t src1,
1187 uint32_t src2)
1188 {
1189 uint32_t ret = 0;
1190
1191 if (((~src1 & src2) | (dst & (~src1 | src2))) & (1U << 31)) {
1192 ret = PSR_CARRY;
1193 }
1194 return ret;
1195 }
1196
1197 static inline uint32_t get_V_sub_icc(uint32_t dst, uint32_t src1,
1198 uint32_t src2)
1199 {
1200 uint32_t ret = 0;
1201
1202 if (((src1 ^ src2) & (src1 ^ dst)) & (1U << 31)) {
1203 ret = PSR_OVF;
1204 }
1205 return ret;
1206 }
1207
1208
1209 #ifdef TARGET_SPARC64
1210 static inline uint32_t get_C_sub_xcc(target_ulong src1, target_ulong src2)
1211 {
1212 uint32_t ret = 0;
1213
1214 if (src1 < src2) {
1215 ret = PSR_CARRY;
1216 }
1217 return ret;
1218 }
1219
1220 static inline uint32_t get_C_subx_xcc(target_ulong dst, target_ulong src1,
1221 target_ulong src2)
1222 {
1223 uint32_t ret = 0;
1224
1225 if (((~src1 & src2) | (dst & (~src1 | src2))) & (1ULL << 63)) {
1226 ret = PSR_CARRY;
1227 }
1228 return ret;
1229 }
1230
1231 static inline uint32_t get_V_sub_xcc(target_ulong dst, target_ulong src1,
1232 target_ulong src2)
1233 {
1234 uint32_t ret = 0;
1235
1236 if (((src1 ^ src2) & (src1 ^ dst)) & (1ULL << 63)) {
1237 ret = PSR_OVF;
1238 }
1239 return ret;
1240 }
1241
1242 static uint32_t compute_all_sub_xcc(void)
1243 {
1244 uint32_t ret;
1245
1246 ret = get_NZ_xcc(CC_DST);
1247 ret |= get_C_sub_xcc(CC_SRC, CC_SRC2);
1248 ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2);
1249 return ret;
1250 }
1251
1252 static uint32_t compute_C_sub_xcc(void)
1253 {
1254 return get_C_sub_xcc(CC_SRC, CC_SRC2);
1255 }
1256 #endif
1257
1258 static uint32_t compute_all_sub(void)
1259 {
1260 uint32_t ret;
1261
1262 ret = get_NZ_icc(CC_DST);
1263 ret |= get_C_sub_icc(CC_SRC, CC_SRC2);
1264 ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2);
1265 return ret;
1266 }
1267
1268 static uint32_t compute_C_sub(void)
1269 {
1270 return get_C_sub_icc(CC_SRC, CC_SRC2);
1271 }
1272
1273 #ifdef TARGET_SPARC64
1274 static uint32_t compute_all_subx_xcc(void)
1275 {
1276 uint32_t ret;
1277
1278 ret = get_NZ_xcc(CC_DST);
1279 ret |= get_C_subx_xcc(CC_DST, CC_SRC, CC_SRC2);
1280 ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2);
1281 return ret;
1282 }
1283
1284 static uint32_t compute_C_subx_xcc(void)
1285 {
1286 uint32_t ret;
1287
1288 ret = get_C_subx_xcc(CC_DST, CC_SRC, CC_SRC2);
1289 return ret;
1290 }
1291 #endif
1292
1293 static uint32_t compute_all_subx(void)
1294 {
1295 uint32_t ret;
1296
1297 ret = get_NZ_icc(CC_DST);
1298 ret |= get_C_subx_icc(CC_DST, CC_SRC, CC_SRC2);
1299 ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2);
1300 return ret;
1301 }
1302
1303 static uint32_t compute_C_subx(void)
1304 {
1305 uint32_t ret;
1306
1307 ret = get_C_subx_icc(CC_DST, CC_SRC, CC_SRC2);
1308 return ret;
1309 }
1310
1311 static uint32_t compute_all_tsub(void)
1312 {
1313 uint32_t ret;
1314
1315 ret = get_NZ_icc(CC_DST);
1316 ret |= get_C_sub_icc(CC_SRC, CC_SRC2);
1317 ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2);
1318 ret |= get_V_tag_icc(CC_SRC, CC_SRC2);
1319 return ret;
1320 }
1321
1322 static uint32_t compute_all_tsubtv(void)
1323 {
1324 uint32_t ret;
1325
1326 ret = get_NZ_icc(CC_DST);
1327 ret |= get_C_sub_icc(CC_SRC, CC_SRC2);
1328 return ret;
1329 }
1330
1331 static uint32_t compute_all_logic(void)
1332 {
1333 return get_NZ_icc(CC_DST);
1334 }
1335
1336 static uint32_t compute_C_logic(void)
1337 {
1338 return 0;
1339 }
1340
1341 #ifdef TARGET_SPARC64
1342 static uint32_t compute_all_logic_xcc(void)
1343 {
1344 return get_NZ_xcc(CC_DST);
1345 }
1346 #endif
1347
1348 typedef struct CCTable {
1349 uint32_t (*compute_all)(void); /* return all the flags */
1350 uint32_t (*compute_c)(void); /* return the C flag */
1351 } CCTable;
1352
1353 static const CCTable icc_table[CC_OP_NB] = {
1354 /* CC_OP_DYNAMIC should never happen */
1355 [CC_OP_FLAGS] = { compute_all_flags, compute_C_flags },
1356 [CC_OP_DIV] = { compute_all_div, compute_C_div },
1357 [CC_OP_ADD] = { compute_all_add, compute_C_add },
1358 [CC_OP_ADDX] = { compute_all_addx, compute_C_addx },
1359 [CC_OP_TADD] = { compute_all_tadd, compute_C_add },
1360 [CC_OP_TADDTV] = { compute_all_taddtv, compute_C_add },
1361 [CC_OP_SUB] = { compute_all_sub, compute_C_sub },
1362 [CC_OP_SUBX] = { compute_all_subx, compute_C_subx },
1363 [CC_OP_TSUB] = { compute_all_tsub, compute_C_sub },
1364 [CC_OP_TSUBTV] = { compute_all_tsubtv, compute_C_sub },
1365 [CC_OP_LOGIC] = { compute_all_logic, compute_C_logic },
1366 };
1367
1368 #ifdef TARGET_SPARC64
1369 static const CCTable xcc_table[CC_OP_NB] = {
1370 /* CC_OP_DYNAMIC should never happen */
1371 [CC_OP_FLAGS] = { compute_all_flags_xcc, compute_C_flags_xcc },
1372 [CC_OP_DIV] = { compute_all_logic_xcc, compute_C_logic },
1373 [CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc },
1374 [CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc },
1375 [CC_OP_TADD] = { compute_all_add_xcc, compute_C_add_xcc },
1376 [CC_OP_TADDTV] = { compute_all_add_xcc, compute_C_add_xcc },
1377 [CC_OP_SUB] = { compute_all_sub_xcc, compute_C_sub_xcc },
1378 [CC_OP_SUBX] = { compute_all_subx_xcc, compute_C_subx_xcc },
1379 [CC_OP_TSUB] = { compute_all_sub_xcc, compute_C_sub_xcc },
1380 [CC_OP_TSUBTV] = { compute_all_sub_xcc, compute_C_sub_xcc },
1381 [CC_OP_LOGIC] = { compute_all_logic_xcc, compute_C_logic },
1382 };
1383 #endif
1384
1385 void helper_compute_psr(void)
1386 {
1387 uint32_t new_psr;
1388
1389 new_psr = icc_table[CC_OP].compute_all();
1390 env->psr = new_psr;
1391 #ifdef TARGET_SPARC64
1392 new_psr = xcc_table[CC_OP].compute_all();
1393 env->xcc = new_psr;
1394 #endif
1395 CC_OP = CC_OP_FLAGS;
1396 }
1397
1398 uint32_t helper_compute_C_icc(void)
1399 {
1400 uint32_t ret;
1401
1402 ret = icc_table[CC_OP].compute_c() >> PSR_CARRY_SHIFT;
1403 return ret;
1404 }
1405
1406 static inline void memcpy32(target_ulong *dst, const target_ulong *src)
1407 {
1408 dst[0] = src[0];
1409 dst[1] = src[1];
1410 dst[2] = src[2];
1411 dst[3] = src[3];
1412 dst[4] = src[4];
1413 dst[5] = src[5];
1414 dst[6] = src[6];
1415 dst[7] = src[7];
1416 }
1417
1418 static void set_cwp(int new_cwp)
1419 {
1420 /* put the modified wrap registers at their proper location */
1421 if (env->cwp == env->nwindows - 1) {
1422 memcpy32(env->regbase, env->regbase + env->nwindows * 16);
1423 }
1424 env->cwp = new_cwp;
1425
1426 /* put the wrap registers at their temporary location */
1427 if (new_cwp == env->nwindows - 1) {
1428 memcpy32(env->regbase + env->nwindows * 16, env->regbase);
1429 }
1430 env->regwptr = env->regbase + (new_cwp * 16);
1431 }
1432
1433 void cpu_set_cwp(CPUState *env1, int new_cwp)
1434 {
1435 CPUState *saved_env;
1436
1437 saved_env = env;
1438 env = env1;
1439 set_cwp(new_cwp);
1440 env = saved_env;
1441 }
1442
1443 static target_ulong get_psr(void)
1444 {
1445 helper_compute_psr();
1446
1447 #if !defined (TARGET_SPARC64)
1448 return env->version | (env->psr & PSR_ICC) |
1449 (env->psref? PSR_EF : 0) |
1450 (env->psrpil << 8) |
1451 (env->psrs? PSR_S : 0) |
1452 (env->psrps? PSR_PS : 0) |
1453 (env->psret? PSR_ET : 0) | env->cwp;
1454 #else
1455 return env->psr & PSR_ICC;
1456 #endif
1457 }
1458
1459 target_ulong cpu_get_psr(CPUState *env1)
1460 {
1461 CPUState *saved_env;
1462 target_ulong ret;
1463
1464 saved_env = env;
1465 env = env1;
1466 ret = get_psr();
1467 env = saved_env;
1468 return ret;
1469 }
1470
1471 static void put_psr(target_ulong val)
1472 {
1473 env->psr = val & PSR_ICC;
1474 #if !defined (TARGET_SPARC64)
1475 env->psref = (val & PSR_EF)? 1 : 0;
1476 env->psrpil = (val & PSR_PIL) >> 8;
1477 #endif
1478 #if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
1479 cpu_check_irqs(env);
1480 #endif
1481 #if !defined (TARGET_SPARC64)
1482 env->psrs = (val & PSR_S)? 1 : 0;
1483 env->psrps = (val & PSR_PS)? 1 : 0;
1484 env->psret = (val & PSR_ET)? 1 : 0;
1485 set_cwp(val & PSR_CWP);
1486 #endif
1487 env->cc_op = CC_OP_FLAGS;
1488 }
1489
1490 void cpu_put_psr(CPUState *env1, target_ulong val)
1491 {
1492 CPUState *saved_env;
1493
1494 saved_env = env;
1495 env = env1;
1496 put_psr(val);
1497 env = saved_env;
1498 }
1499
1500 static int cwp_inc(int cwp)
1501 {
1502 if (unlikely(cwp >= env->nwindows)) {
1503 cwp -= env->nwindows;
1504 }
1505 return cwp;
1506 }
1507
1508 int cpu_cwp_inc(CPUState *env1, int cwp)
1509 {
1510 CPUState *saved_env;
1511 target_ulong ret;
1512
1513 saved_env = env;
1514 env = env1;
1515 ret = cwp_inc(cwp);
1516 env = saved_env;
1517 return ret;
1518 }
1519
1520 static int cwp_dec(int cwp)
1521 {
1522 if (unlikely(cwp < 0)) {
1523 cwp += env->nwindows;
1524 }
1525 return cwp;
1526 }
1527
1528 int cpu_cwp_dec(CPUState *env1, int cwp)
1529 {
1530 CPUState *saved_env;
1531 target_ulong ret;
1532
1533 saved_env = env;
1534 env = env1;
1535 ret = cwp_dec(cwp);
1536 env = saved_env;
1537 return ret;
1538 }
1539
1540 #ifdef TARGET_SPARC64
1541 GEN_FCMPS(fcmps_fcc1, float32, 22, 0);
1542 GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
1543 GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
1544
1545 GEN_FCMPS(fcmps_fcc2, float32, 24, 0);
1546 GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
1547 GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
1548
1549 GEN_FCMPS(fcmps_fcc3, float32, 26, 0);
1550 GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
1551 GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
1552
1553 GEN_FCMPS(fcmpes_fcc1, float32, 22, 1);
1554 GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
1555 GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
1556
1557 GEN_FCMPS(fcmpes_fcc2, float32, 24, 1);
1558 GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
1559 GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
1560
1561 GEN_FCMPS(fcmpes_fcc3, float32, 26, 1);
1562 GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
1563 GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
1564 #endif
1565 #undef GEN_FCMPS
1566
1567 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
1568 defined(DEBUG_MXCC)
1569 static void dump_mxcc(CPUState *env)
1570 {
1571 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
1572 "\n",
1573 env->mxccdata[0], env->mxccdata[1],
1574 env->mxccdata[2], env->mxccdata[3]);
1575 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
1576 "\n"
1577 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
1578 "\n",
1579 env->mxccregs[0], env->mxccregs[1],
1580 env->mxccregs[2], env->mxccregs[3],
1581 env->mxccregs[4], env->mxccregs[5],
1582 env->mxccregs[6], env->mxccregs[7]);
1583 }
1584 #endif
1585
1586 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
1587 && defined(DEBUG_ASI)
1588 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
1589 uint64_t r1)
1590 {
1591 switch (size)
1592 {
1593 case 1:
1594 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
1595 addr, asi, r1 & 0xff);
1596 break;
1597 case 2:
1598 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
1599 addr, asi, r1 & 0xffff);
1600 break;
1601 case 4:
1602 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
1603 addr, asi, r1 & 0xffffffff);
1604 break;
1605 case 8:
1606 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
1607 addr, asi, r1);
1608 break;
1609 }
1610 }
1611 #endif
1612
1613 #ifndef TARGET_SPARC64
1614 #ifndef CONFIG_USER_ONLY
1615 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1616 {
1617 uint64_t ret = 0;
1618 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
1619 uint32_t last_addr = addr;
1620 #endif
1621
1622 helper_check_align(addr, size - 1);
1623 switch (asi) {
1624 case 2: /* SuperSparc MXCC registers */
1625 switch (addr) {
1626 case 0x01c00a00: /* MXCC control register */
1627 if (size == 8)
1628 ret = env->mxccregs[3];
1629 else
1630 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1631 size);
1632 break;
1633 case 0x01c00a04: /* MXCC control register */
1634 if (size == 4)
1635 ret = env->mxccregs[3];
1636 else
1637 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1638 size);
1639 break;
1640 case 0x01c00c00: /* Module reset register */
1641 if (size == 8) {
1642 ret = env->mxccregs[5];
1643 // should we do something here?
1644 } else
1645 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1646 size);
1647 break;
1648 case 0x01c00f00: /* MBus port address register */
1649 if (size == 8)
1650 ret = env->mxccregs[7];
1651 else
1652 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1653 size);
1654 break;
1655 default:
1656 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
1657 size);
1658 break;
1659 }
1660 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
1661 "addr = %08x -> ret = %" PRIx64 ","
1662 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
1663 #ifdef DEBUG_MXCC
1664 dump_mxcc(env);
1665 #endif
1666 break;
1667 case 3: /* MMU probe */
1668 {
1669 int mmulev;
1670
1671 mmulev = (addr >> 8) & 15;
1672 if (mmulev > 4)
1673 ret = 0;
1674 else
1675 ret = mmu_probe(env, addr, mmulev);
1676 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
1677 addr, mmulev, ret);
1678 }
1679 break;
1680 case 4: /* read MMU regs */
1681 {
1682 int reg = (addr >> 8) & 0x1f;
1683
1684 ret = env->mmuregs[reg];
1685 if (reg == 3) /* Fault status cleared on read */
1686 env->mmuregs[3] = 0;
1687 else if (reg == 0x13) /* Fault status read */
1688 ret = env->mmuregs[3];
1689 else if (reg == 0x14) /* Fault address read */
1690 ret = env->mmuregs[4];
1691 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
1692 }
1693 break;
1694 case 5: // Turbosparc ITLB Diagnostic
1695 case 6: // Turbosparc DTLB Diagnostic
1696 case 7: // Turbosparc IOTLB Diagnostic
1697 break;
1698 case 9: /* Supervisor code access */
1699 switch(size) {
1700 case 1:
1701 ret = ldub_code(addr);
1702 break;
1703 case 2:
1704 ret = lduw_code(addr);
1705 break;
1706 default:
1707 case 4:
1708 ret = ldl_code(addr);
1709 break;
1710 case 8:
1711 ret = ldq_code(addr);
1712 break;
1713 }
1714 break;
1715 case 0xa: /* User data access */
1716 switch(size) {
1717 case 1:
1718 ret = ldub_user(addr);
1719 break;
1720 case 2:
1721 ret = lduw_user(addr);
1722 break;
1723 default:
1724 case 4:
1725 ret = ldl_user(addr);
1726 break;
1727 case 8:
1728 ret = ldq_user(addr);
1729 break;
1730 }
1731 break;
1732 case 0xb: /* Supervisor data access */
1733 switch(size) {
1734 case 1:
1735 ret = ldub_kernel(addr);
1736 break;
1737 case 2:
1738 ret = lduw_kernel(addr);
1739 break;
1740 default:
1741 case 4:
1742 ret = ldl_kernel(addr);
1743 break;
1744 case 8:
1745 ret = ldq_kernel(addr);
1746 break;
1747 }
1748 break;
1749 case 0xc: /* I-cache tag */
1750 case 0xd: /* I-cache data */
1751 case 0xe: /* D-cache tag */
1752 case 0xf: /* D-cache data */
1753 break;
1754 case 0x20: /* MMU passthrough */
1755 switch(size) {
1756 case 1:
1757 ret = ldub_phys(addr);
1758 break;
1759 case 2:
1760 ret = lduw_phys(addr);
1761 break;
1762 default:
1763 case 4:
1764 ret = ldl_phys(addr);
1765 break;
1766 case 8:
1767 ret = ldq_phys(addr);
1768 break;
1769 }
1770 break;
1771 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1772 switch(size) {
1773 case 1:
1774 ret = ldub_phys((target_phys_addr_t)addr
1775 | ((target_phys_addr_t)(asi & 0xf) << 32));
1776 break;
1777 case 2:
1778 ret = lduw_phys((target_phys_addr_t)addr
1779 | ((target_phys_addr_t)(asi & 0xf) << 32));
1780 break;
1781 default:
1782 case 4:
1783 ret = ldl_phys((target_phys_addr_t)addr
1784 | ((target_phys_addr_t)(asi & 0xf) << 32));
1785 break;
1786 case 8:
1787 ret = ldq_phys((target_phys_addr_t)addr
1788 | ((target_phys_addr_t)(asi & 0xf) << 32));
1789 break;
1790 }
1791 break;
1792 case 0x30: // Turbosparc secondary cache diagnostic
1793 case 0x31: // Turbosparc RAM snoop
1794 case 0x32: // Turbosparc page table descriptor diagnostic
1795 case 0x39: /* data cache diagnostic register */
1796 case 0x4c: /* SuperSPARC MMU Breakpoint Action register */
1797 ret = 0;
1798 break;
1799 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
1800 {
1801 int reg = (addr >> 8) & 3;
1802
1803 switch(reg) {
1804 case 0: /* Breakpoint Value (Addr) */
1805 ret = env->mmubpregs[reg];
1806 break;
1807 case 1: /* Breakpoint Mask */
1808 ret = env->mmubpregs[reg];
1809 break;
1810 case 2: /* Breakpoint Control */
1811 ret = env->mmubpregs[reg];
1812 break;
1813 case 3: /* Breakpoint Status */
1814 ret = env->mmubpregs[reg];
1815 env->mmubpregs[reg] = 0ULL;
1816 break;
1817 }
1818 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
1819 ret);
1820 }
1821 break;
1822 case 8: /* User code access, XXX */
1823 default:
1824 do_unassigned_access(addr, 0, 0, asi, size);
1825 ret = 0;
1826 break;
1827 }
1828 if (sign) {
1829 switch(size) {
1830 case 1:
1831 ret = (int8_t) ret;
1832 break;
1833 case 2:
1834 ret = (int16_t) ret;
1835 break;
1836 case 4:
1837 ret = (int32_t) ret;
1838 break;
1839 default:
1840 break;
1841 }
1842 }
1843 #ifdef DEBUG_ASI
1844 dump_asi("read ", last_addr, asi, size, ret);
1845 #endif
1846 return ret;
1847 }
1848
1849 void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
1850 {
1851 helper_check_align(addr, size - 1);
1852 switch(asi) {
1853 case 2: /* SuperSparc MXCC registers */
1854 switch (addr) {
1855 case 0x01c00000: /* MXCC stream data register 0 */
1856 if (size == 8)
1857 env->mxccdata[0] = val;
1858 else
1859 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1860 size);
1861 break;
1862 case 0x01c00008: /* MXCC stream data register 1 */
1863 if (size == 8)
1864 env->mxccdata[1] = val;
1865 else
1866 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1867 size);
1868 break;
1869 case 0x01c00010: /* MXCC stream data register 2 */
1870 if (size == 8)
1871 env->mxccdata[2] = val;
1872 else
1873 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1874 size);
1875 break;
1876 case 0x01c00018: /* MXCC stream data register 3 */
1877 if (size == 8)
1878 env->mxccdata[3] = val;
1879 else
1880 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1881 size);
1882 break;
1883 case 0x01c00100: /* MXCC stream source */
1884 if (size == 8)
1885 env->mxccregs[0] = val;
1886 else
1887 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1888 size);
1889 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1890 0);
1891 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1892 8);
1893 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1894 16);
1895 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1896 24);
1897 break;
1898 case 0x01c00200: /* MXCC stream destination */
1899 if (size == 8)
1900 env->mxccregs[1] = val;
1901 else
1902 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1903 size);
1904 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
1905 env->mxccdata[0]);
1906 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
1907 env->mxccdata[1]);
1908 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
1909 env->mxccdata[2]);
1910 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
1911 env->mxccdata[3]);
1912 break;
1913 case 0x01c00a00: /* MXCC control register */
1914 if (size == 8)
1915 env->mxccregs[3] = val;
1916 else
1917 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1918 size);
1919 break;
1920 case 0x01c00a04: /* MXCC control register */
1921 if (size == 4)
1922 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
1923 | val;
1924 else
1925 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1926 size);
1927 break;
1928 case 0x01c00e00: /* MXCC error register */
1929 // writing a 1 bit clears the error
1930 if (size == 8)
1931 env->mxccregs[6] &= ~val;
1932 else
1933 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1934 size);
1935 break;
1936 case 0x01c00f00: /* MBus port address register */
1937 if (size == 8)
1938 env->mxccregs[7] = val;
1939 else
1940 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1941 size);
1942 break;
1943 default:
1944 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
1945 size);
1946 break;
1947 }
1948 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
1949 asi, size, addr, val);
1950 #ifdef DEBUG_MXCC
1951 dump_mxcc(env);
1952 #endif
1953 break;
1954 case 3: /* MMU flush */
1955 {
1956 int mmulev;
1957
1958 mmulev = (addr >> 8) & 15;
1959 DPRINTF_MMU("mmu flush level %d\n", mmulev);
1960 switch (mmulev) {
1961 case 0: // flush page
1962 tlb_flush_page(env, addr & 0xfffff000);
1963 break;
1964 case 1: // flush segment (256k)
1965 case 2: // flush region (16M)
1966 case 3: // flush context (4G)
1967 case 4: // flush entire
1968 tlb_flush(env, 1);
1969 break;
1970 default:
1971 break;
1972 }
1973 #ifdef DEBUG_MMU
1974 dump_mmu(stdout, fprintf, env);
1975 #endif
1976 }
1977 break;
1978 case 4: /* write MMU regs */
1979 {
1980 int reg = (addr >> 8) & 0x1f;
1981 uint32_t oldreg;
1982
1983 oldreg = env->mmuregs[reg];
1984 switch(reg) {
1985 case 0: // Control Register
1986 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
1987 (val & 0x00ffffff);
1988 // Mappings generated during no-fault mode or MMU
1989 // disabled mode are invalid in normal mode
1990 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
1991 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm)))
1992 tlb_flush(env, 1);
1993 break;
1994 case 1: // Context Table Pointer Register
1995 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
1996 break;
1997 case 2: // Context Register
1998 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
1999 if (oldreg != env->mmuregs[reg]) {
2000 /* we flush when the MMU context changes because
2001 QEMU has no MMU context support */
2002 tlb_flush(env, 1);
2003 }
2004 break;
2005 case 3: // Synchronous Fault Status Register with Clear
2006 case 4: // Synchronous Fault Address Register
2007 break;
2008 case 0x10: // TLB Replacement Control Register
2009 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
2010 break;
2011 case 0x13: // Synchronous Fault Status Register with Read and Clear
2012 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
2013 break;
2014 case 0x14: // Synchronous Fault Address Register
2015 env->mmuregs[4] = val;
2016 break;
2017 default:
2018 env->mmuregs[reg] = val;
2019 break;
2020 }
2021 if (oldreg != env->mmuregs[reg]) {
2022 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
2023 reg, oldreg, env->mmuregs[reg]);
2024 }
2025 #ifdef DEBUG_MMU
2026 dump_mmu(stdout, fprintf, env);
2027 #endif
2028 }
2029 break;
2030 case 5: // Turbosparc ITLB Diagnostic
2031 case 6: // Turbosparc DTLB Diagnostic
2032 case 7: // Turbosparc IOTLB Diagnostic
2033 break;
2034 case 0xa: /* User data access */
2035 switch(size) {
2036 case 1:
2037 stb_user(addr, val);
2038 break;
2039 case 2:
2040 stw_user(addr, val);
2041 break;
2042 default:
2043 case 4:
2044 stl_user(addr, val);
2045 break;
2046 case 8:
2047 stq_user(addr, val);
2048 break;
2049 }
2050 break;
2051 case 0xb: /* Supervisor data access */
2052 switch(size) {
2053 case 1:
2054 stb_kernel(addr, val);
2055 break;
2056 case 2:
2057 stw_kernel(addr, val);
2058 break;
2059 default:
2060 case 4:
2061 stl_kernel(addr, val);
2062 break;
2063 case 8:
2064 stq_kernel(addr, val);
2065 break;
2066 }
2067 break;
2068 case 0xc: /* I-cache tag */
2069 case 0xd: /* I-cache data */
2070 case 0xe: /* D-cache tag */
2071 case 0xf: /* D-cache data */
2072 case 0x10: /* I/D-cache flush page */
2073 case 0x11: /* I/D-cache flush segment */
2074 case 0x12: /* I/D-cache flush region */
2075 case 0x13: /* I/D-cache flush context */
2076 case 0x14: /* I/D-cache flush user */
2077 break;
2078 case 0x17: /* Block copy, sta access */
2079 {
2080 // val = src
2081 // addr = dst
2082 // copy 32 bytes
2083 unsigned int i;
2084 uint32_t src = val & ~3, dst = addr & ~3, temp;
2085
2086 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
2087 temp = ldl_kernel(src);
2088 stl_kernel(dst, temp);
2089 }
2090 }
2091 break;
2092 case 0x1f: /* Block fill, stda access */
2093 {
2094 // addr = dst
2095 // fill 32 bytes with val
2096 unsigned int i;
2097 uint32_t dst = addr & 7;
2098
2099 for (i = 0; i < 32; i += 8, dst += 8)
2100 stq_kernel(dst, val);
2101 }
2102 break;
2103 case 0x20: /* MMU passthrough */
2104 {
2105 switch(size) {
2106 case 1:
2107 stb_phys(addr, val);
2108 break;
2109 case 2:
2110 stw_phys(addr, val);
2111 break;
2112 case 4:
2113 default:
2114 stl_phys(addr, val);
2115 break;
2116 case 8:
2117 stq_phys(addr, val);
2118 break;
2119 }
2120 }
2121 break;
2122 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
2123 {
2124 switch(size) {
2125 case 1:
2126 stb_phys((target_phys_addr_t)addr
2127 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
2128 break;
2129 case 2:
2130 stw_phys((target_phys_addr_t)addr
2131 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
2132 break;
2133 case 4:
2134 default:
2135 stl_phys((target_phys_addr_t)addr
2136 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
2137 break;
2138 case 8:
2139 stq_phys((target_phys_addr_t)addr
2140 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
2141 break;
2142 }
2143 }
2144 break;
2145 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
2146 case 0x31: // store buffer data, Ross RT620 I-cache flush or
2147 // Turbosparc snoop RAM
2148 case 0x32: // store buffer control or Turbosparc page table
2149 // descriptor diagnostic
2150 case 0x36: /* I-cache flash clear */
2151 case 0x37: /* D-cache flash clear */
2152 case 0x4c: /* breakpoint action */
2153 break;
2154 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
2155 {
2156 int reg = (addr >> 8) & 3;
2157
2158 switch(reg) {
2159 case 0: /* Breakpoint Value (Addr) */
2160 env->mmubpregs[reg] = (val & 0xfffffffffULL);
2161 break;
2162 case 1: /* Breakpoint Mask */
2163 env->mmubpregs[reg] = (val & 0xfffffffffULL);
2164 break;
2165 case 2: /* Breakpoint Control */
2166 env->mmubpregs[reg] = (val & 0x7fULL);
2167 break;
2168 case 3: /* Breakpoint Status */
2169 env->mmubpregs[reg] = (val & 0xfULL);
2170 break;
2171 }
2172 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
2173 env->mmuregs[reg]);
2174 }
2175 break;
2176 case 8: /* User code access, XXX */
2177 case 9: /* Supervisor code access, XXX */
2178 default:
2179 do_unassigned_access(addr, 1, 0, asi, size);
2180 break;
2181 }
2182 #ifdef DEBUG_ASI
2183 dump_asi("write", addr, asi, size, val);
2184 #endif
2185 }
2186
2187 #endif /* CONFIG_USER_ONLY */
2188 #else /* TARGET_SPARC64 */
2189
2190 #ifdef CONFIG_USER_ONLY
2191 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
2192 {
2193 uint64_t ret = 0;
2194 #if defined(DEBUG_ASI)
2195 target_ulong last_addr = addr;
2196 #endif
2197
2198 if (asi < 0x80)
2199 raise_exception(TT_PRIV_ACT);
2200
2201 helper_check_align(addr, size - 1);
2202 addr = asi_address_mask(env, asi, addr);
2203
2204 switch (asi) {
2205 case 0x82: // Primary no-fault
2206 case 0x8a: // Primary no-fault LE
2207 if (page_check_range(addr, size, PAGE_READ) == -1) {
2208 #ifdef DEBUG_ASI
2209 dump_asi("read ", last_addr, asi, size, ret);
2210 #endif
2211 return 0;
2212 }
2213 // Fall through
2214 case 0x80: // Primary
2215 case 0x88: // Primary LE
2216 {
2217 switch(size) {
2218 case 1:
2219 ret = ldub_raw(addr);
2220 break;
2221 case 2:
2222 ret = lduw_raw(addr);
2223 break;
2224 case 4:
2225 ret = ldl_raw(addr);
2226 break;
2227 default:
2228 case 8:
2229 ret = ldq_raw(addr);
2230 break;
2231 }
2232 }
2233 break;
2234 case 0x83: // Secondary no-fault
2235 case 0x8b: // Secondary no-fault LE
2236 if (page_check_range(addr, size, PAGE_READ) == -1) {
2237 #ifdef DEBUG_ASI
2238 dump_asi("read ", last_addr, asi, size, ret);
2239 #endif
2240 return 0;
2241 }
2242 // Fall through
2243 case 0x81: // Secondary
2244 case 0x89: // Secondary LE
2245 // XXX
2246 break;
2247 default:
2248 break;
2249 }
2250
2251 /* Convert from little endian */
2252 switch (asi) {
2253 case 0x88: // Primary LE
2254 case 0x89: // Secondary LE
2255 case 0x8a: // Primary no-fault LE
2256 case 0x8b: // Secondary no-fault LE
2257 switch(size) {
2258 case 2:
2259 ret = bswap16(ret);
2260 break;
2261 case 4:
2262 ret = bswap32(ret);
2263 break;
2264 case 8:
2265 ret = bswap64(ret);
2266 break;
2267 default:
2268 break;
2269 }
2270 default:
2271 break;
2272 }
2273
2274 /* Convert to signed number */
2275 if (sign) {
2276 switch(size) {
2277 case 1:
2278 ret = (int8_t) ret;
2279 break;
2280 case 2:
2281 ret = (int16_t) ret;
2282 break;
2283 case 4:
2284 ret = (int32_t) ret;
2285 break;
2286 default:
2287 break;
2288 }
2289 }
2290 #ifdef DEBUG_ASI
2291 dump_asi("read ", last_addr, asi, size, ret);
2292 #endif
2293 return ret;
2294 }
2295
2296 void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
2297 {
2298 #ifdef DEBUG_ASI
2299 dump_asi("write", addr, asi, size, val);
2300 #endif
2301 if (asi < 0x80)
2302 raise_exception(TT_PRIV_ACT);
2303
2304 helper_check_align(addr, size - 1);
2305 addr = asi_address_mask(env, asi, addr);
2306
2307 /* Convert to little endian */
2308 switch (asi) {
2309 case 0x88: // Primary LE
2310 case 0x89: // Secondary LE
2311 switch(size) {
2312 case 2:
2313 val = bswap16(val);
2314 break;
2315 case 4:
2316 val = bswap32(val);
2317 break;
2318 case 8:
2319 val = bswap64(val);
2320 break;
2321 default:
2322 break;
2323 }
2324 default:
2325 break;
2326 }
2327
2328 switch(asi) {
2329 case 0x80: // Primary
2330 case 0x88: // Primary LE
2331 {
2332 switch(size) {
2333 case 1:
2334 stb_raw(addr, val);
2335 break;
2336 case 2:
2337 stw_raw(addr, val);
2338 break;
2339 case 4:
2340 stl_raw(addr, val);
2341 break;
2342 case 8:
2343 default:
2344 stq_raw(addr, val);
2345 break;
2346 }
2347 }
2348 break;
2349 case 0x81: // Secondary
2350 case 0x89: // Secondary LE
2351 // XXX
2352 return;
2353
2354 case 0x82: // Primary no-fault, RO
2355 case 0x83: // Secondary no-fault, RO
2356 case 0x8a: // Primary no-fault LE, RO
2357 case 0x8b: // Secondary no-fault LE, RO
2358 default:
2359 do_unassigned_access(addr, 1, 0, 1, size);
2360 return;
2361 }
2362 }
2363
2364 #else /* CONFIG_USER_ONLY */
2365
2366 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
2367 {
2368 uint64_t ret = 0;
2369 #if defined(DEBUG_ASI)
2370 target_ulong last_addr = addr;
2371 #endif
2372
2373 asi &= 0xff;
2374
2375 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2376 || (cpu_has_hypervisor(env)
2377 && asi >= 0x30 && asi < 0x80
2378 && !(env->hpstate & HS_PRIV)))
2379 raise_exception(TT_PRIV_ACT);
2380
2381 helper_check_align(addr, size - 1);
2382 addr = asi_address_mask(env, asi, addr);
2383
2384 switch (asi) {
2385 case 0x82: // Primary no-fault
2386 case 0x8a: // Primary no-fault LE
2387 case 0x83: // Secondary no-fault
2388 case 0x8b: // Secondary no-fault LE
2389 {
2390 /* secondary space access has lowest asi bit equal to 1 */
2391 int access_mmu_idx = ( asi & 1 ) ? MMU_KERNEL_IDX
2392 : MMU_KERNEL_SECONDARY_IDX;
2393
2394 if (cpu_get_phys_page_nofault(env, addr, access_mmu_idx) == -1ULL) {
2395 #ifdef DEBUG_ASI
2396 dump_asi("read ", last_addr, asi, size, ret);
2397 #endif
2398 return 0;
2399 }
2400 }
2401 // Fall through
2402 case 0x10: // As if user primary
2403 case 0x11: // As if user secondary
2404 case 0x18: // As if user primary LE
2405 case 0x19: // As if user secondary LE
2406 case 0x80: // Primary
2407 case 0x81: // Secondary
2408 case 0x88: // Primary LE
2409 case 0x89: // Secondary LE
2410 case 0xe2: // UA2007 Primary block init
2411 case 0xe3: // UA2007 Secondary block init
2412 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
2413 if (cpu_hypervisor_mode(env)) {
2414 switch(size) {
2415 case 1:
2416 ret = ldub_hypv(addr);
2417 break;
2418 case 2:
2419 ret = lduw_hypv(addr);
2420 break;
2421 case 4:
2422 ret = ldl_hypv(addr);
2423 break;
2424 default:
2425 case 8:
2426 ret = ldq_hypv(addr);
2427 break;
2428 }
2429 } else {
2430 /* secondary space access has lowest asi bit equal to 1 */
2431 if (asi & 1) {
2432 switch(size) {
2433 case 1:
2434 ret = ldub_kernel_secondary(addr);
2435 break;
2436 case 2:
2437 ret = lduw_kernel_secondary(addr);
2438 break;
2439 case 4:
2440 ret = ldl_kernel_secondary(addr);
2441 break;
2442 default:
2443 case 8:
2444 ret = ldq_kernel_secondary(addr);
2445 break;
2446 }
2447 } else {
2448 switch(size) {
2449 case 1:
2450 ret = ldub_kernel(addr);
2451 break;
2452 case 2:
2453 ret = lduw_kernel(addr);
2454 break;
2455 case 4:
2456 ret = ldl_kernel(addr);
2457 break;
2458 default:
2459 case 8:
2460 ret = ldq_kernel(addr);
2461 break;
2462 }
2463 }
2464 }
2465 } else {
2466 /* secondary space access has lowest asi bit equal to 1 */
2467 if (asi & 1) {
2468 switch(size) {
2469 case 1:
2470 ret = ldub_user_secondary(addr);
2471 break;
2472 case 2:
2473 ret = lduw_user_secondary(addr);
2474 break;
2475 case 4:
2476 ret = ldl_user_secondary(addr);
2477 break;
2478 default:
2479 case 8:
2480 ret = ldq_user_secondary(addr);
2481 break;
2482 }
2483 } else {
2484 switch(size) {
2485 case 1:
2486 ret = ldub_user(addr);
2487 break;
2488 case 2:
2489 ret = lduw_user(addr);
2490 break;
2491 case 4:
2492 ret = ldl_user(addr);
2493 break;
2494 default:
2495 case 8:
2496 ret = ldq_user(addr);
2497 break;
2498 }
2499 }
2500 }
2501 break;
2502 case 0x14: // Bypass
2503 case 0x15: // Bypass, non-cacheable
2504 case 0x1c: // Bypass LE
2505 case 0x1d: // Bypass, non-cacheable LE
2506 {
2507 switch(size) {
2508 case 1:
2509 ret = ldub_phys(addr);
2510 break;
2511 case 2:
2512 ret = lduw_phys(addr);
2513 break;
2514 case 4:
2515 ret = ldl_phys(addr);
2516 break;
2517 default:
2518 case 8:
2519 ret = ldq_phys(addr);
2520 break;
2521 }
2522 break;
2523 }
2524 case 0x24: // Nucleus quad LDD 128 bit atomic
2525 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2526 // Only ldda allowed
2527 raise_exception(TT_ILL_INSN);
2528 return 0;
2529 case 0x04: // Nucleus
2530 case 0x0c: // Nucleus Little Endian (LE)
2531 {
2532 switch(size) {
2533 case 1:
2534 ret = ldub_nucleus(addr);
2535 break;
2536 case 2:
2537 ret = lduw_nucleus(addr);
2538 break;
2539 case 4:
2540 ret = ldl_nucleus(addr);
2541 break;
2542 default:
2543 case 8:
2544 ret = ldq_nucleus(addr);
2545 break;
2546 }
2547 break;
2548 }
2549 case 0x4a: // UPA config
2550 // XXX
2551 break;
2552 case 0x45: // LSU
2553 ret = env->lsu;
2554 break;
2555 case 0x50: // I-MMU regs
2556 {
2557 int reg = (addr >> 3) & 0xf;
2558
2559 if (reg == 0) {
2560 // I-TSB Tag Target register
2561 ret = ultrasparc_tag_target(env->immu.tag_access);
2562 } else {
2563 ret = env->immuregs[reg];
2564 }
2565
2566 break;
2567 }
2568 case 0x51: // I-MMU 8k TSB pointer
2569 {
2570 // env->immuregs[5] holds I-MMU TSB register value
2571 // env->immuregs[6] holds I-MMU Tag Access register value
2572 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
2573 8*1024);
2574 break;
2575 }
2576 case 0x52: // I-MMU 64k TSB pointer
2577 {
2578 // env->immuregs[5] holds I-MMU TSB register value
2579 // env->immuregs[6] holds I-MMU Tag Access register value
2580 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
2581 64*1024);
2582 break;
2583 }
2584 case 0x55: // I-MMU data access
2585 {
2586 int reg = (addr >> 3) & 0x3f;
2587
2588 ret = env->itlb[reg].tte;
2589 break;
2590 }
2591 case 0x56: // I-MMU tag read
2592 {
2593 int reg = (addr >> 3) & 0x3f;
2594
2595 ret = env->itlb[reg].tag;
2596 break;
2597 }
2598 case 0x58: // D-MMU regs
2599 {
2600 int reg = (addr >> 3) & 0xf;
2601
2602 if (reg == 0) {
2603 // D-TSB Tag Target register
2604 ret = ultrasparc_tag_target(env->dmmu.tag_access);
2605 } else {
2606 ret = env->dmmuregs[reg];
2607 }
2608 break;
2609 }
2610 case 0x59: // D-MMU 8k TSB pointer
2611 {
2612 // env->dmmuregs[5] holds D-MMU TSB register value
2613 // env->dmmuregs[6] holds D-MMU Tag Access register value
2614 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
2615 8*1024);
2616 break;
2617 }
2618 case 0x5a: // D-MMU 64k TSB pointer
2619 {
2620 // env->dmmuregs[5] holds D-MMU TSB register value
2621 // env->dmmuregs[6] holds D-MMU Tag Access register value
2622 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
2623 64*1024);
2624 break;
2625 }
2626 case 0x5d: // D-MMU data access
2627 {
2628 int reg = (addr >> 3) & 0x3f;
2629
2630 ret = env->dtlb[reg].tte;
2631 break;
2632 }
2633 case 0x5e: // D-MMU tag read
2634 {
2635 int reg = (addr >> 3) & 0x3f;
2636
2637 ret = env->dtlb[reg].tag;
2638 break;
2639 }
2640 case 0x46: // D-cache data
2641 case 0x47: // D-cache tag access
2642 case 0x4b: // E-cache error enable
2643 case 0x4c: // E-cache asynchronous fault status
2644 case 0x4d: // E-cache asynchronous fault address
2645 case 0x4e: // E-cache tag data
2646 case 0x66: // I-cache instruction access
2647 case 0x67: // I-cache tag access
2648 case 0x6e: // I-cache predecode
2649 case 0x6f: // I-cache LRU etc.
2650 case 0x76: // E-cache tag
2651 case 0x7e: // E-cache tag
2652 break;
2653 case 0x5b: // D-MMU data pointer
2654 case 0x48: // Interrupt dispatch, RO
2655 case 0x49: // Interrupt data receive
2656 case 0x7f: // Incoming interrupt vector, RO
2657 // XXX
2658 break;
2659 case 0x54: // I-MMU data in, WO
2660 case 0x57: // I-MMU demap, WO
2661 case 0x5c: // D-MMU data in, WO
2662 case 0x5f: // D-MMU demap, WO
2663 case 0x77: // Interrupt vector, WO
2664 default:
2665 do_unassigned_access(addr, 0, 0, 1, size);
2666 ret = 0;
2667 break;
2668 }
2669
2670 /* Convert from little endian */
2671 switch (asi) {
2672 case 0x0c: // Nucleus Little Endian (LE)
2673 case 0x18: // As if user primary LE
2674 case 0x19: // As if user secondary LE
2675 case 0x1c: // Bypass LE
2676 case 0x1d: // Bypass, non-cacheable LE
2677 case 0x88: // Primary LE
2678 case 0x89: // Secondary LE
2679 case 0x8a: // Primary no-fault LE
2680 case 0x8b: // Secondary no-fault LE
2681 switch(size) {
2682 case 2:
2683 ret = bswap16(ret);
2684 break;
2685 case 4:
2686 ret = bswap32(ret);
2687 break;
2688 case 8:
2689 ret = bswap64(ret);
2690 break;
2691 default:
2692 break;
2693 }
2694 default:
2695 break;
2696 }
2697
2698 /* Convert to signed number */
2699 if (sign) {
2700 switch(size) {
2701 case 1:
2702 ret = (int8_t) ret;
2703 break;
2704 case 2:
2705 ret = (int16_t) ret;
2706 break;
2707 case 4:
2708 ret = (int32_t) ret;
2709 break;
2710 default:
2711 break;
2712 }
2713 }
2714 #ifdef DEBUG_ASI
2715 dump_asi("read ", last_addr, asi, size, ret);
2716 #endif
2717 return ret;
2718 }
2719
2720 void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
2721 {
2722 #ifdef DEBUG_ASI
2723 dump_asi("write", addr, asi, size, val);
2724 #endif
2725
2726 asi &= 0xff;
2727
2728 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2729 || (cpu_has_hypervisor(env)
2730 && asi >= 0x30 && asi < 0x80
2731 && !(env->hpstate & HS_PRIV)))
2732 raise_exception(TT_PRIV_ACT);
2733
2734 helper_check_align(addr, size - 1);
2735 addr = asi_address_mask(env, asi, addr);
2736
2737 /* Convert to little endian */
2738 switch (asi) {
2739 case 0x0c: // Nucleus Little Endian (LE)
2740 case 0x18: // As if user primary LE
2741 case 0x19: // As if user secondary LE
2742 case 0x1c: // Bypass LE
2743 case 0x1d: // Bypass, non-cacheable LE
2744 case 0x88: // Primary LE
2745 case 0x89: // Secondary LE
2746 switch(size) {
2747 case 2:
2748 val = bswap16(val);
2749 break;
2750 case 4:
2751 val = bswap32(val);
2752 break;
2753 case 8:
2754 val = bswap64(val);
2755 break;
2756 default:
2757 break;
2758 }
2759 default:
2760 break;
2761 }
2762
2763 switch(asi) {
2764 case 0x10: // As if user primary
2765 case 0x11: // As if user secondary
2766 case 0x18: // As if user primary LE
2767 case 0x19: // As if user secondary LE
2768 case 0x80: // Primary
2769 case 0x81: // Secondary
2770 case 0x88: // Primary LE
2771 case 0x89: // Secondary LE
2772 case 0xe2: // UA2007 Primary block init
2773 case 0xe3: // UA2007 Secondary block init
2774 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
2775 if (cpu_hypervisor_mode(env)) {
2776 switch(size) {
2777 case 1:
2778 stb_hypv(addr, val);
2779 break;
2780 case 2:
2781 stw_hypv(addr, val);
2782 break;
2783 case 4:
2784 stl_hypv(addr, val);
2785 break;
2786 case 8:
2787 default:
2788 stq_hypv(addr, val);
2789 break;
2790 }
2791 } else {
2792 /* secondary space access has lowest asi bit equal to 1 */
2793 if (asi & 1) {
2794 switch(size) {
2795 case 1:
2796 stb_kernel_secondary(addr, val);
2797 break;
2798 case 2:
2799 stw_kernel_secondary(addr, val);
2800 break;
2801 case 4:
2802 stl_kernel_secondary(addr, val);
2803 break;
2804 case 8:
2805 default:
2806 stq_kernel_secondary(addr, val);
2807 break;
2808 }
2809 } else {
2810 switch(size) {
2811 case 1:
2812 stb_kernel(addr, val);
2813 break;
2814 case 2:
2815 stw_kernel(addr, val);
2816 break;
2817 case 4:
2818 stl_kernel(addr, val);
2819 break;
2820 case 8:
2821 default:
2822 stq_kernel(addr, val);
2823 break;
2824 }
2825 }
2826 }
2827 } else {
2828 /* secondary space access has lowest asi bit equal to 1 */
2829 if (asi & 1) {
2830 switch(size) {
2831 case 1:
2832 stb_user_secondary(addr, val);
2833 break;
2834 case 2:
2835 stw_user_secondary(addr, val);
2836 break;
2837 case 4:
2838 stl_user_secondary(addr, val);
2839 break;
2840 case 8:
2841 default:
2842 stq_user_secondary(addr, val);
2843 break;
2844 }
2845 } else {
2846 switch(size) {
2847 case 1:
2848 stb_user(addr, val);
2849 break;
2850 case 2:
2851 stw_user(addr, val);
2852 break;
2853 case 4:
2854 stl_user(addr, val);
2855 break;
2856 case 8:
2857 default:
2858 stq_user(addr, val);
2859 break;
2860 }
2861 }
2862 }
2863 break;
2864 case 0x14: // Bypass
2865 case 0x15: // Bypass, non-cacheable
2866 case 0x1c: // Bypass LE
2867 case 0x1d: // Bypass, non-cacheable LE
2868 {
2869 switch(size) {
2870 case 1:
2871 stb_phys(addr, val);
2872 break;
2873 case 2:
2874 stw_phys(addr, val);
2875 break;
2876 case 4:
2877 stl_phys(addr, val);
2878 break;
2879 case 8:
2880 default:
2881 stq_phys(addr, val);
2882 break;
2883 }
2884 }
2885 return;
2886 case 0x24: // Nucleus quad LDD 128 bit atomic
2887 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2888 // Only ldda allowed
2889 raise_exception(TT_ILL_INSN);
2890 return;
2891 case 0x04: // Nucleus
2892 case 0x0c: // Nucleus Little Endian (LE)
2893 {
2894 switch(size) {
2895 case 1:
2896 stb_nucleus(addr, val);
2897 break;
2898 case 2:
2899 stw_nucleus(addr, val);
2900 break;
2901 case 4:
2902 stl_nucleus(addr, val);
2903 break;
2904 default:
2905 case 8:
2906 stq_nucleus(addr, val);
2907 break;
2908 }
2909 break;
2910 }
2911
2912 case 0x4a: // UPA config
2913 // XXX
2914 return;
2915 case 0x45: // LSU
2916 {
2917 uint64_t oldreg;
2918
2919 oldreg = env->lsu;
2920 env->lsu = val & (DMMU_E | IMMU_E);
2921 // Mappings generated during D/I MMU disabled mode are
2922 // invalid in normal mode
2923 if (oldreg != env->lsu) {
2924 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
2925 oldreg, env->lsu);
2926 #ifdef DEBUG_MMU
2927 dump_mmu(stdout, fprintf, env1);
2928 #endif
2929 tlb_flush(env, 1);
2930 }
2931 return;
2932 }
2933 case 0x50: // I-MMU regs
2934 {
2935 int reg = (addr >> 3) & 0xf;
2936 uint64_t oldreg;
2937
2938 oldreg = env->immuregs[reg];
2939 switch(reg) {
2940 case 0: // RO
2941 return;
2942 case 1: // Not in I-MMU
2943 case 2:
2944 return;
2945 case 3: // SFSR
2946 if ((val & 1) == 0)
2947 val = 0; // Clear SFSR
2948 env->immu.sfsr = val;
2949 break;
2950 case 4: // RO
2951 return;
2952 case 5: // TSB access
2953 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
2954 PRIx64 "\n", env->immu.tsb, val);
2955 env->immu.tsb = val;
2956 break;
2957 case 6: // Tag access
2958 env->immu.tag_access = val;
2959 break;
2960 case 7:
2961 case 8:
2962 return;
2963 default:
2964 break;
2965 }
2966
2967 if (oldreg != env->immuregs[reg]) {
2968 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
2969 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
2970 }
2971 #ifdef DEBUG_MMU
2972 dump_mmu(stdout, fprintf, env);
2973 #endif
2974 return;
2975 }
2976 case 0x54: // I-MMU data in
2977 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
2978 return;
2979 case 0x55: // I-MMU data access
2980 {
2981 // TODO: auto demap
2982
2983 unsigned int i = (addr >> 3) & 0x3f;
2984
2985 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env);
2986
2987 #ifdef DEBUG_MMU
2988 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
2989 dump_mmu(stdout, fprintf, env);
2990 #endif
2991 return;
2992 }
2993 case 0x57: // I-MMU demap
2994 demap_tlb(env->itlb, addr, "immu", env);
2995 return;
2996 case 0x58: // D-MMU regs
2997 {
2998 int reg = (addr >> 3) & 0xf;
2999 uint64_t oldreg;
3000
3001 oldreg = env->dmmuregs[reg];
3002 switch(reg) {
3003 case 0: // RO
3004 case 4:
3005 return;
3006 case 3: // SFSR
3007 if ((val & 1) == 0) {
3008 val = 0; // Clear SFSR, Fault address
3009 env->dmmu.sfar = 0;
3010 }
3011 env->dmmu.sfsr = val;
3012 break;
3013 case 1: // Primary context
3014 env->dmmu.mmu_primary_context = val;
3015 /* can be optimized to only flush MMU_USER_IDX
3016 and MMU_KERNEL_IDX entries */
3017 tlb_flush(env, 1);
3018 break;
3019 case 2: // Secondary context
3020 env->dmmu.mmu_secondary_context = val;
3021 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
3022 and MMU_KERNEL_SECONDARY_IDX entries */
3023 tlb_flush(env, 1);
3024 break;
3025 case 5: // TSB access
3026 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
3027 PRIx64 "\n", env->dmmu.tsb, val);
3028 env->dmmu.tsb = val;
3029 break;
3030 case 6: // Tag access
3031 env->dmmu.tag_access = val;
3032 break;
3033 case 7: // Virtual Watchpoint
3034 case 8: // Physical Watchpoint
3035 default:
3036 env->dmmuregs[reg] = val;
3037 break;
3038 }
3039
3040 if (oldreg != env->dmmuregs[reg]) {
3041 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
3042 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
3043 }
3044 #ifdef DEBUG_MMU
3045 dump_mmu(stdout, fprintf, env);
3046 #endif
3047 return;
3048 }
3049 case 0x5c: // D-MMU data in
3050 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
3051 return;
3052 case 0x5d: // D-MMU data access
3053 {
3054 unsigned int i = (addr >> 3) & 0x3f;
3055
3056 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env);
3057
3058 #ifdef DEBUG_MMU
3059 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
3060 dump_mmu(stdout, fprintf, env);
3061 #endif
3062 return;
3063 }
3064 case 0x5f: // D-MMU demap
3065 demap_tlb(env->dtlb, addr, "dmmu", env);
3066 return;
3067 case 0x49: // Interrupt data receive
3068 // XXX
3069 return;
3070 case 0x46: // D-cache data
3071 case 0x47: // D-cache tag access
3072 case 0x4b: // E-cache error enable
3073 case 0x4c: // E-cache asynchronous fault status
3074 case 0x4d: // E-cache asynchronous fault address
3075 case 0x4e: // E-cache tag data
3076 case 0x66: // I-cache instruction access
3077 case 0x67: // I-cache tag access
3078 case 0x6e: // I-cache predecode
3079 case 0x6f: // I-cache LRU etc.
3080 case 0x76: // E-cache tag
3081 case 0x7e: // E-cache tag
3082 return;
3083 case 0x51: // I-MMU 8k TSB pointer, RO
3084 case 0x52: // I-MMU 64k TSB pointer, RO
3085 case 0x56: // I-MMU tag read, RO
3086 case 0x59: // D-MMU 8k TSB pointer, RO
3087 case 0x5a: // D-MMU 64k TSB pointer, RO
3088 case 0x5b: // D-MMU data pointer, RO
3089 case 0x5e: // D-MMU tag read, RO
3090 case 0x48: // Interrupt dispatch, RO
3091 case 0x7f: // Incoming interrupt vector, RO
3092 case 0x82: // Primary no-fault, RO
3093 case 0x83: // Secondary no-fault, RO
3094 case 0x8a: // Primary no-fault LE, RO
3095 case 0x8b: // Secondary no-fault LE, RO
3096 default:
3097 do_unassigned_access(addr, 1, 0, 1, size);
3098 return;
3099 }
3100 }
3101 #endif /* CONFIG_USER_ONLY */
3102
3103 void helper_ldda_asi(target_ulong addr, int asi, int rd)
3104 {
3105 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
3106 || (cpu_has_hypervisor(env)
3107 && asi >= 0x30 && asi < 0x80
3108 && !(env->hpstate & HS_PRIV)))
3109 raise_exception(TT_PRIV_ACT);
3110
3111 addr = asi_address_mask(env, asi, addr);
3112
3113 switch (asi) {
3114 #if !defined(CONFIG_USER_ONLY)
3115 case 0x24: // Nucleus quad LDD 128 bit atomic
3116 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
3117 helper_check_align(addr, 0xf);
3118 if (rd == 0) {
3119 env->gregs[1] = ldq_nucleus(addr + 8);
3120 if (asi == 0x2c)
3121 bswap64s(&env->gregs[1]);
3122 } else if (rd < 8) {
3123 env->gregs[rd] = ldq_nucleus(addr);
3124 env->gregs[rd + 1] = ldq_nucleus(addr + 8);
3125 if (asi == 0x2c) {
3126 bswap64s(&env->gregs[rd]);
3127 bswap64s(&env->gregs[rd + 1]);
3128 }
3129 } else {
3130 env->regwptr[rd] = ldq_nucleus(addr);
3131 env->regwptr[rd + 1] = ldq_nucleus(addr + 8);
3132 if (asi == 0x2c) {
3133 bswap64s(&env->regwptr[rd]);
3134 bswap64s(&env->regwptr[rd + 1]);
3135 }
3136 }
3137 break;
3138 #endif
3139 default:
3140 helper_check_align(addr, 0x3);
3141 if (rd == 0)
3142 env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0);
3143 else if (rd < 8) {
3144 env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0);
3145 env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
3146 } else {
3147 env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0);
3148 env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
3149 }
3150 break;
3151 }
3152 }
3153
3154 void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
3155 {
3156 unsigned int i;
3157 target_ulong val;
3158
3159 helper_check_align(addr, 3);
3160 addr = asi_address_mask(env, asi, addr);
3161
3162 switch (asi) {
3163 case 0xf0: // Block load primary
3164 case 0xf1: // Block load secondary
3165 case 0xf8: // Block load primary LE
3166 case 0xf9: // Block load secondary LE
3167 if (rd & 7) {
3168 raise_exception(TT_ILL_INSN);
3169 return;
3170 }
3171 helper_check_align(addr, 0x3f);
3172 for (i = 0; i < 16; i++) {
3173 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4,
3174 0);
3175 addr += 4;
3176 }
3177
3178 return;
3179 case 0x70: // Block load primary, user privilege
3180 case 0x71: // Block load secondary, user privilege
3181 if (rd & 7) {
3182 raise_exception(TT_ILL_INSN);
3183 return;
3184 }
3185 helper_check_align(addr, 0x3f);
3186 for (i = 0; i < 16; i++) {
3187 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x1f, 4,
3188 0);
3189 addr += 4;
3190 }
3191
3192 return;
3193 default:
3194 break;
3195 }
3196
3197 val = helper_ld_asi(addr, asi, size, 0);
3198 switch(size) {
3199 default:
3200 case 4:
3201 *((uint32_t *)&env->fpr[rd]) = val;
3202 break;
3203 case 8:
3204 *((int64_t *)&DT0) = val;
3205 break;
3206 case 16:
3207 // XXX
3208 break;
3209 }
3210 }
3211
3212 void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
3213 {
3214 unsigned int i;
3215 target_ulong val = 0;
3216
3217 helper_check_align(addr, 3);
3218 addr = asi_address_mask(env, asi, addr);
3219
3220 switch (asi) {
3221 case 0xe0: // UA2007 Block commit store primary (cache flush)
3222 case 0xe1: // UA2007 Block commit store secondary (cache flush)
3223 case 0xf0: // Block store primary
3224 case 0xf1: // Block store secondary
3225 case 0xf8: // Block store primary LE
3226 case 0xf9: // Block store secondary LE
3227 if (rd & 7) {
3228 raise_exception(TT_ILL_INSN);
3229 return;
3230 }
3231 helper_check_align(addr, 0x3f);
3232 for (i = 0; i < 16; i++) {
3233 val = *(uint32_t *)&env->fpr[rd++];
3234 helper_st_asi(addr, val, asi & 0x8f, 4);
3235 addr += 4;
3236 }
3237
3238 return;
3239 case 0x70: // Block store primary, user privilege
3240 case 0x71: // Block store secondary, user privilege
3241 if (rd & 7) {
3242 raise_exception(TT_ILL_INSN);
3243 return;
3244 }
3245 helper_check_align(addr, 0x3f);
3246 for (i = 0; i < 16; i++) {
3247 val = *(uint32_t *)&env->fpr[rd++];
3248 helper_st_asi(addr, val, asi & 0x1f, 4);
3249 addr += 4;
3250 }
3251
3252 return;
3253 default:
3254 break;
3255 }
3256
3257 switch(size) {
3258 default:
3259 case 4:
3260 val = *((uint32_t *)&env->fpr[rd]);
3261 break;
3262 case 8:
3263 val = *((int64_t *)&DT0);
3264 break;
3265 case 16:
3266 // XXX
3267 break;
3268 }
3269 helper_st_asi(addr, val, asi, size);
3270 }
3271
3272 target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
3273 target_ulong val2, uint32_t asi)
3274 {
3275 target_ulong ret;
3276
3277 val2 &= 0xffffffffUL;
3278 ret = helper_ld_asi(addr, asi, 4, 0);
3279 ret &= 0xffffffffUL;
3280 if (val2 == ret)
3281 helper_st_asi(addr, val1 & 0xffffffffUL, asi, 4);
3282 return ret;
3283 }
3284
3285 target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
3286 target_ulong val2, uint32_t asi)
3287 {
3288 target_ulong ret;
3289
3290 ret = helper_ld_asi(addr, asi, 8, 0);
3291 if (val2 == ret)
3292 helper_st_asi(addr, val1, asi, 8);
3293 return ret;
3294 }
3295 #endif /* TARGET_SPARC64 */
3296
3297 #ifndef TARGET_SPARC64
3298 void helper_rett(void)
3299 {
3300 unsigned int cwp;
3301
3302 if (env->psret == 1)
3303 raise_exception(TT_ILL_INSN);
3304
3305 env->psret = 1;
3306 cwp = cwp_inc(env->cwp + 1) ;
3307 if (env->wim & (1 << cwp)) {
3308 raise_exception(TT_WIN_UNF);
3309 }
3310 set_cwp(cwp);
3311 env->psrs = env->psrps;
3312 }
3313 #endif
3314
3315 static target_ulong helper_udiv_common(target_ulong a, target_ulong b, int cc)
3316 {
3317 int overflow = 0;
3318 uint64_t x0;
3319 uint32_t x1;
3320
3321 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
3322 x1 = (b & 0xffffffff);
3323
3324 if (x1 == 0) {
3325 raise_exception(TT_DIV_ZERO);
3326 }
3327
3328 x0 = x0 / x1;
3329 if (x0 > 0xffffffff) {
3330 x0 = 0xffffffff;
3331 overflow = 1;
3332 }
3333
3334 if (cc) {
3335 env->cc_dst = x0;
3336 env->cc_src2 = overflow;
3337 env->cc_op = CC_OP_DIV;
3338 }
3339 return x0;
3340 }
3341
3342 target_ulong helper_udiv(target_ulong a, target_ulong b)
3343 {
3344 return helper_udiv_common(a, b, 0);
3345 }
3346
3347 target_ulong helper_udiv_cc(target_ulong a, target_ulong b)
3348 {
3349 return helper_udiv_common(a, b, 1);
3350 }
3351
3352 static target_ulong helper_sdiv_common(target_ulong a, target_ulong b, int cc)
3353 {
3354 int overflow = 0;
3355 int64_t x0;
3356 int32_t x1;
3357
3358 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
3359 x1 = (b & 0xffffffff);
3360
3361 if (x1 == 0) {
3362 raise_exception(TT_DIV_ZERO);
3363 }
3364
3365 x0 = x0 / x1;
3366 if ((int32_t) x0 != x0) {
3367 x0 = x0 < 0 ? 0x80000000: 0x7fffffff;
3368 overflow = 1;
3369 }
3370
3371 if (cc) {
3372 env->cc_dst = x0;
3373 env->cc_src2 = overflow;
3374 env->cc_op = CC_OP_DIV;
3375 }
3376 return x0;
3377 }
3378
3379 target_ulong helper_sdiv(target_ulong a, target_ulong b)
3380 {
3381 return helper_sdiv_common(a, b, 0);
3382 }
3383
3384 target_ulong helper_sdiv_cc(target_ulong a, target_ulong b)
3385 {
3386 return helper_sdiv_common(a, b, 1);
3387 }
3388
3389 void helper_stdf(target_ulong addr, int mem_idx)
3390 {
3391 helper_check_align(addr, 7);
3392 #if !defined(CONFIG_USER_ONLY)
3393 switch (mem_idx) {
3394 case MMU_USER_IDX:
3395 stfq_user(addr, DT0);
3396 break;
3397 case MMU_KERNEL_IDX:
3398 stfq_kernel(addr, DT0);
3399 break;
3400 #ifdef TARGET_SPARC64
3401 case MMU_HYPV_IDX:
3402 stfq_hypv(addr, DT0);
3403 break;
3404 #endif
3405 default:
3406 DPRINTF_MMU("helper_stdf: need to check MMU idx %d\n", mem_idx);
3407 break;
3408 }
3409 #else
3410 stfq_raw(address_mask(env, addr), DT0);
3411 #endif
3412 }
3413
3414 void helper_lddf(target_ulong addr, int mem_idx)
3415 {
3416 helper_check_align(addr, 7);
3417 #if !defined(CONFIG_USER_ONLY)
3418 switch (mem_idx) {
3419 case MMU_USER_IDX:
3420 DT0 = ldfq_user(addr);
3421 break;
3422 case MMU_KERNEL_IDX:
3423 DT0 = ldfq_kernel(addr);
3424 break;
3425 #ifdef TARGET_SPARC64
3426 case MMU_HYPV_IDX:
3427 DT0 = ldfq_hypv(addr);
3428 break;
3429 #endif
3430 default:
3431 DPRINTF_MMU("helper_lddf: need to check MMU idx %d\n", mem_idx);
3432 break;
3433 }
3434 #else
3435 DT0 = ldfq_raw(address_mask(env, addr));
3436 #endif
3437 }
3438
3439 void helper_ldqf(target_ulong addr, int mem_idx)
3440 {
3441 // XXX add 128 bit load
3442 CPU_QuadU u;
3443
3444 helper_check_align(addr, 7);
3445 #if !defined(CONFIG_USER_ONLY)
3446 switch (mem_idx) {
3447 case MMU_USER_IDX:
3448 u.ll.upper = ldq_user(addr);
3449 u.ll.lower = ldq_user(addr + 8);
3450 QT0 = u.q;
3451 break;
3452 case MMU_KERNEL_IDX:
3453 u.ll.upper = ldq_kernel(addr);
3454 u.ll.lower = ldq_kernel(addr + 8);
3455 QT0 = u.q;
3456 break;
3457 #ifdef TARGET_SPARC64
3458 case MMU_HYPV_IDX:
3459 u.ll.upper = ldq_hypv(addr);
3460 u.ll.lower = ldq_hypv(addr + 8);
3461 QT0 = u.q;
3462 break;
3463 #endif
3464 default:
3465 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx);
3466 break;
3467 }
3468 #else
3469 u.ll.upper = ldq_raw(address_mask(env, addr));
3470 u.ll.lower = ldq_raw(address_mask(env, addr + 8));
3471 QT0 = u.q;
3472 #endif
3473 }
3474
3475 void helper_stqf(target_ulong addr, int mem_idx)
3476 {
3477 // XXX add 128 bit store
3478 CPU_QuadU u;
3479
3480 helper_check_align(addr, 7);
3481 #if !defined(CONFIG_USER_ONLY)
3482 switch (mem_idx) {
3483 case MMU_USER_IDX:
3484 u.q = QT0;
3485 stq_user(addr, u.ll.upper);
3486 stq_user(addr + 8, u.ll.lower);
3487 break;
3488 case MMU_KERNEL_IDX:
3489 u.q = QT0;
3490 stq_kernel(addr, u.ll.upper);
3491 stq_kernel(addr + 8, u.ll.lower);
3492 break;
3493 #ifdef TARGET_SPARC64
3494 case MMU_HYPV_IDX:
3495 u.q = QT0;
3496 stq_hypv(addr, u.ll.upper);
3497 stq_hypv(addr + 8, u.ll.lower);
3498 break;
3499 #endif
3500 default:
3501 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx);
3502 break;
3503 }
3504 #else
3505 u.q = QT0;
3506 stq_raw(address_mask(env, addr), u.ll.upper);
3507 stq_raw(address_mask(env, addr + 8), u.ll.lower);
3508 #endif
3509 }
3510
3511 static inline void set_fsr(void)
3512 {
3513 int rnd_mode;
3514
3515 switch (env->fsr & FSR_RD_MASK) {
3516 case FSR_RD_NEAREST:
3517 rnd_mode = float_round_nearest_even;
3518 break;
3519 default:
3520 case FSR_RD_ZERO:
3521 rnd_mode = float_round_to_zero;
3522 break;
3523 case FSR_RD_POS:
3524 rnd_mode = float_round_up;
3525 break;
3526 case FSR_RD_NEG:
3527 rnd_mode = float_round_down;
3528 break;
3529 }
3530 set_float_rounding_mode(rnd_mode, &env->fp_status);
3531 }
3532
3533 void helper_ldfsr(uint32_t new_fsr)
3534 {
3535 env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK);
3536 set_fsr();
3537 }
3538
3539 #ifdef TARGET_SPARC64
3540 void helper_ldxfsr(uint64_t new_fsr)
3541 {
3542 env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK);
3543 set_fsr();
3544 }
3545 #endif
3546
3547 void helper_debug(void)
3548 {
3549 env->exception_index = EXCP_DEBUG;
3550 cpu_loop_exit();
3551 }
3552
3553 #ifndef TARGET_SPARC64
3554 /* XXX: use another pointer for %iN registers to avoid slow wrapping
3555 handling ? */
3556 void helper_save(void)
3557 {
3558 uint32_t cwp;
3559
3560 cwp = cwp_dec(env->cwp - 1);
3561 if (env->wim & (1 << cwp)) {
3562 raise_exception(TT_WIN_OVF);
3563 }
3564 set_cwp(cwp);
3565 }
3566
3567 void helper_restore(void)
3568 {
3569 uint32_t cwp;
3570
3571 cwp = cwp_inc(env->cwp + 1);
3572 if (env->wim & (1 << cwp)) {
3573 raise_exception(TT_WIN_UNF);
3574 }
3575 set_cwp(cwp);
3576 }
3577
3578 void helper_wrpsr(target_ulong new_psr)
3579 {
3580 if ((new_psr & PSR_CWP) >= env->nwindows) {
3581 raise_exception(TT_ILL_INSN);
3582 } else {
3583 cpu_put_psr(env, new_psr);
3584 }
3585 }
3586
3587 target_ulong helper_rdpsr(void)
3588 {
3589 return get_psr();
3590 }
3591
3592 #else
3593 /* XXX: use another pointer for %iN registers to avoid slow wrapping
3594 handling ? */
3595 void helper_save(void)
3596 {
3597 uint32_t cwp;
3598
3599 cwp = cwp_dec(env->cwp - 1);
3600 if (env->cansave == 0) {
3601 raise_exception(TT_SPILL | (env->otherwin != 0 ?
3602 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
3603 ((env->wstate & 0x7) << 2)));
3604 } else {
3605 if (env->cleanwin - env->canrestore == 0) {
3606 // XXX Clean windows without trap
3607 raise_exception(TT_CLRWIN);
3608 } else {
3609 env->cansave--;
3610 env->canrestore++;
3611 set_cwp(cwp);
3612 }
3613 }
3614 }
3615
3616 void helper_restore(void)
3617 {
3618 uint32_t cwp;
3619
3620 cwp = cwp_inc(env->cwp + 1);
3621 if (env->canrestore == 0) {
3622 raise_exception(TT_FILL | (env->otherwin != 0 ?
3623 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
3624 ((env->wstate & 0x7) << 2)));
3625 } else {
3626 env->cansave++;
3627 env->canrestore--;
3628 set_cwp(cwp);
3629 }
3630 }
3631
3632 void helper_flushw(void)
3633 {
3634 if (env->cansave != env->nwindows - 2) {
3635 raise_exception(TT_SPILL | (env->otherwin != 0 ?
3636 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
3637 ((env->wstate & 0x7) << 2)));
3638 }
3639 }
3640
3641 void helper_saved(void)
3642 {
3643 env->cansave++;
3644 if (env->otherwin == 0)
3645 env->canrestore--;
3646 else
3647 env->otherwin--;
3648 }
3649
3650 void helper_restored(void)
3651 {
3652 env->canrestore++;
3653 if (env->cleanwin < env->nwindows - 1)
3654 env->cleanwin++;
3655 if (env->otherwin == 0)
3656 env->cansave--;
3657 else
3658 env->otherwin--;
3659 }
3660
3661 static target_ulong get_ccr(void)
3662 {
3663 target_ulong psr;
3664
3665 psr = get_psr();
3666
3667 return ((env->xcc >> 20) << 4) | ((psr & PSR_ICC) >> 20);
3668 }
3669
3670 target_ulong cpu_get_ccr(CPUState *env1)
3671 {
3672 CPUState *saved_env;
3673 target_ulong ret;
3674
3675 saved_env = env;
3676 env = env1;
3677 ret = get_ccr();
3678 env = saved_env;
3679 return ret;
3680 }
3681
3682 static void put_ccr(target_ulong val)
3683 {
3684 target_ulong tmp = val;
3685
3686 env->xcc = (tmp >> 4) << 20;
3687 env->psr = (tmp & 0xf) << 20;
3688 CC_OP = CC_OP_FLAGS;
3689 }
3690
3691 void cpu_put_ccr(CPUState *env1, target_ulong val)
3692 {
3693 CPUState *saved_env;
3694
3695 saved_env = env;
3696 env = env1;
3697 put_ccr(val);
3698 env = saved_env;
3699 }
3700
3701 static target_ulong get_cwp64(void)
3702 {
3703 return env->nwindows - 1 - env->cwp;
3704 }
3705
3706 target_ulong cpu_get_cwp64(CPUState *env1)
3707 {
3708 CPUState *saved_env;
3709 target_ulong ret;
3710
3711 saved_env = env;
3712 env = env1;
3713 ret = get_cwp64();
3714 env = saved_env;
3715 return ret;
3716 }
3717
3718 static void put_cwp64(int cwp)
3719 {
3720 if (unlikely(cwp >= env->nwindows || cwp < 0)) {
3721 cwp %= env->nwindows;
3722 }
3723 set_cwp(env->nwindows - 1 - cwp);
3724 }
3725
3726 void cpu_put_cwp64(CPUState *env1, int cwp)
3727 {
3728 CPUState *saved_env;
3729
3730 saved_env = env;
3731 env = env1;
3732 put_cwp64(cwp);
3733 env = saved_env;
3734 }
3735
3736 target_ulong helper_rdccr(void)
3737 {
3738 return get_ccr();
3739 }
3740
3741 void helper_wrccr(target_ulong new_ccr)
3742 {
3743 put_ccr(new_ccr);
3744 }
3745
3746 // CWP handling is reversed in V9, but we still use the V8 register
3747 // order.
3748 target_ulong helper_rdcwp(void)
3749 {
3750 return get_cwp64();
3751 }
3752
3753 void helper_wrcwp(target_ulong new_cwp)
3754 {
3755 put_cwp64(new_cwp);
3756 }
3757
3758 // This function uses non-native bit order
3759 #define GET_FIELD(X, FROM, TO) \
3760 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
3761
3762 // This function uses the order in the manuals, i.e. bit 0 is 2^0
3763 #define GET_FIELD_SP(X, FROM, TO) \
3764 GET_FIELD(X, 63 - (TO), 63 - (FROM))
3765
3766 target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
3767 {
3768 return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
3769 (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
3770 (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
3771 (GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
3772 (GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
3773 (GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
3774 (((pixel_addr >> 55) & 1) << 4) |
3775 (GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
3776 GET_FIELD_SP(pixel_addr, 11, 12);
3777 }
3778
3779 target_ulong helper_alignaddr(target_ulong addr, target_ulong offset)
3780 {
3781 uint64_t tmp;
3782
3783 tmp = addr + offset;
3784 env->gsr &= ~7ULL;
3785 env->gsr |= tmp & 7ULL;
3786 return tmp & ~7ULL;
3787 }
3788
3789 target_ulong helper_popc(target_ulong val)
3790 {
3791 return ctpop64(val);
3792 }
3793
3794 static inline uint64_t *get_gregset(uint32_t pstate)
3795 {
3796 switch (pstate) {
3797 default:
3798 DPRINTF_PSTATE("ERROR in get_gregset: active pstate bits=%x%s%s%s\n",
3799 pstate,
3800 (pstate & PS_IG) ? " IG" : "",
3801 (pstate & PS_MG) ? " MG" : "",
3802 (pstate & PS_AG) ? " AG" : "");
3803 /* pass through to normal set of global registers */
3804 case 0:
3805 return env->bgregs;
3806 case PS_AG:
3807 return env->agregs;
3808 case PS_MG:
3809 return env->mgregs;
3810 case PS_IG:
3811 return env->igregs;
3812 }
3813 }
3814
3815 static inline void change_pstate(uint32_t new_pstate)
3816 {
3817 uint32_t pstate_regs, new_pstate_regs;
3818 uint64_t *src, *dst;
3819
3820 if (env->def->features & CPU_FEATURE_GL) {
3821 // PS_AG is not implemented in this case
3822 new_pstate &= ~PS_AG;
3823 }
3824
3825 pstate_regs = env->pstate & 0xc01;
3826 new_pstate_regs = new_pstate & 0xc01;
3827
3828 if (new_pstate_regs != pstate_regs) {
3829 DPRINTF_PSTATE("change_pstate: switching regs old=%x new=%x\n",
3830 pstate_regs, new_pstate_regs);
3831 // Switch global register bank
3832 src = get_gregset(new_pstate_regs);
3833 dst = get_gregset(pstate_regs);
3834 memcpy32(dst, env->gregs);
3835 memcpy32(env->gregs, src);
3836 }
3837 else {
3838 DPRINTF_PSTATE("change_pstate: regs new=%x (unchanged)\n",
3839 new_pstate_regs);
3840 }
3841 env->pstate = new_pstate;
3842 }
3843
3844 void helper_wrpstate(target_ulong new_state)
3845 {
3846 change_pstate(new_state & 0xf3f);
3847
3848 #if !defined(CONFIG_USER_ONLY)
3849 if (cpu_interrupts_enabled(env)) {
3850 cpu_check_irqs(env);
3851 }
3852 #endif
3853 }
3854
3855 void helper_wrpil(target_ulong new_pil)
3856 {
3857 #if !defined(CONFIG_USER_ONLY)
3858 DPRINTF_PSTATE("helper_wrpil old=%x new=%x\n",
3859 env->psrpil, (uint32_t)new_pil);
3860
3861 env->psrpil = new_pil;
3862
3863 if (cpu_interrupts_enabled(env)) {
3864 cpu_check_irqs(env);
3865 }
3866 #endif
3867 }
3868
3869 void helper_done(void)
3870 {
3871 trap_state* tsptr = cpu_tsptr(env);
3872
3873 env->pc = tsptr->tnpc;
3874 env->npc = tsptr->tnpc + 4;
3875 put_ccr(tsptr->tstate >> 32);
3876 env->asi = (tsptr->tstate >> 24) & 0xff;
3877 change_pstate((tsptr->tstate >> 8) & 0xf3f);
3878 put_cwp64(tsptr->tstate & 0xff);
3879 env->tl--;
3880
3881 DPRINTF_PSTATE("... helper_done tl=%d\n", env->tl);
3882
3883 #if !defined(CONFIG_USER_ONLY)
3884 if (cpu_interrupts_enabled(env)) {
3885 cpu_check_irqs(env);
3886 }
3887 #endif
3888 }
3889
3890 void helper_retry(void)
3891 {
3892 trap_state* tsptr = cpu_tsptr(env);
3893
3894 env->pc = tsptr->tpc;
3895 env->npc = tsptr->tnpc;
3896 put_ccr(tsptr->tstate >> 32);
3897 env->asi = (tsptr->tstate >> 24) & 0xff;
3898 change_pstate((tsptr->tstate >> 8) & 0xf3f);
3899 put_cwp64(tsptr->tstate & 0xff);
3900 env->tl--;
3901
3902 DPRINTF_PSTATE("... helper_retry tl=%d\n", env->tl);
3903
3904 #if !defined(CONFIG_USER_ONLY)
3905 if (cpu_interrupts_enabled(env)) {
3906 cpu_check_irqs(env);
3907 }
3908 #endif
3909 }
3910
3911 static void do_modify_softint(const char* operation, uint32_t value)
3912 {
3913 if (env->softint != value) {
3914 env->softint = value;
3915 DPRINTF_PSTATE(": %s new %08x\n", operation, env->softint);
3916 #if !defined(CONFIG_USER_ONLY)
3917 if (cpu_interrupts_enabled(env)) {
3918 cpu_check_irqs(env);
3919 }
3920 #endif
3921 }
3922 }
3923
3924 void helper_set_softint(uint64_t value)
3925 {
3926 do_modify_softint("helper_set_softint", env->softint | (uint32_t)value);
3927 }
3928
3929 void helper_clear_softint(uint64_t value)
3930 {
3931 do_modify_softint("helper_clear_softint", env->softint & (uint32_t)~value);
3932 }
3933
3934 void helper_write_softint(uint64_t value)
3935 {
3936 do_modify_softint("helper_write_softint", (uint32_t)value);
3937 }
3938 #endif
3939
3940 void helper_flush(target_ulong addr)
3941 {
3942 addr &= ~7;
3943 tb_invalidate_page_range(addr, addr + 8);
3944 }
3945
3946 #ifdef TARGET_SPARC64
3947 #ifdef DEBUG_PCALL
3948 static const char * const excp_names[0x80] = {
3949 [TT_TFAULT] = "Instruction Access Fault",
3950 [TT_TMISS] = "Instruction Access MMU Miss",
3951 [TT_CODE_ACCESS] = "Instruction Access Error",
3952 [TT_ILL_INSN] = "Illegal Instruction",
3953 [TT_PRIV_INSN] = "Privileged Instruction",
3954 [TT_NFPU_INSN] = "FPU Disabled",
3955 [TT_FP_EXCP] = "FPU Exception",
3956 [TT_TOVF] = "Tag Overflow",
3957 [TT_CLRWIN] = "Clean Windows",
3958 [TT_DIV_ZERO] = "Division By Zero",
3959 [TT_DFAULT] = "Data Access Fault",
3960 [TT_DMISS] = "Data Access MMU Miss",
3961 [TT_DATA_ACCESS] = "Data Access Error",
3962 [TT_DPROT] = "Data Protection Error",
3963 [TT_UNALIGNED] = "Unaligned Memory Access",
3964 [TT_PRIV_ACT] = "Privileged Action",
3965 [TT_EXTINT | 0x1] = "External Interrupt 1",
3966 [TT_EXTINT | 0x2] = "External Interrupt 2",
3967 [TT_EXTINT | 0x3] = "External Interrupt 3",
3968 [TT_EXTINT | 0x4] = "External Interrupt 4",
3969 [TT_EXTINT | 0x5] = "External Interrupt 5",
3970 [TT_EXTINT | 0x6] = "External Interrupt 6",
3971 [TT_EXTINT | 0x7] = "External Interrupt 7",
3972 [TT_EXTINT | 0x8] = "External Interrupt 8",
3973 [TT_EXTINT | 0x9] = "External Interrupt 9",
3974 [TT_EXTINT | 0xa] = "External Interrupt 10",
3975 [TT_EXTINT | 0xb] = "External Interrupt 11",
3976 [TT_EXTINT | 0xc] = "External Interrupt 12",
3977 [TT_EXTINT | 0xd] = "External Interrupt 13",
3978 [TT_EXTINT | 0xe] = "External Interrupt 14",
3979 [TT_EXTINT | 0xf] = "External Interrupt 15",
3980 };
3981 #endif
3982
3983 trap_state* cpu_tsptr(CPUState* env)
3984 {
3985 return &env->ts[env->tl & MAXTL_MASK];
3986 }
3987
3988 void do_interrupt(CPUState *env)
3989 {
3990 int intno = env->exception_index;
3991 trap_state* tsptr;
3992
3993 #ifdef DEBUG_PCALL
3994 if (qemu_loglevel_mask(CPU_LOG_INT)) {
3995 static int count;
3996 const char *name;
3997
3998 if (intno < 0 || intno >= 0x180)
3999 name = "Unknown";
4000 else if (intno >= 0x100)
4001 name = "Trap Instruction";
4002 else if (intno >= 0xc0)
4003 name = "Window Fill";
4004 else if (intno >= 0x80)
4005 name = "Window Spill";
4006 else {
4007 name = excp_names[intno];
4008 if (!name)
4009 name = "Unknown";
4010 }
4011
4012 qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
4013 " SP=%016" PRIx64 "\n",
4014 count, name, intno,
4015 env->pc,
4016 env->npc, env->regwptr[6]);
4017 log_cpu_state(env, 0);
4018 #if 0
4019 {
4020 int i;
4021 uint8_t *ptr;
4022
4023 qemu_log(" code=");
4024 ptr = (uint8_t *)env->pc;
4025 for(i = 0; i < 16; i++) {
4026 qemu_log(" %02x", ldub(ptr + i));
4027 }
4028 qemu_log("\n");
4029 }
4030 #endif
4031 count++;
4032 }
4033 #endif
4034 #if !defined(CONFIG_USER_ONLY)
4035 if (env->tl >= env->maxtl) {
4036 cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
4037 " Error state", env->exception_index, env->tl, env->maxtl);
4038 return;
4039 }
4040 #endif
4041 if (env->tl < env->maxtl - 1) {
4042 env->tl++;
4043 } else {
4044 env->pstate |= PS_RED;
4045 if (env->tl < env->maxtl)
4046 env->tl++;
4047 }
4048 tsptr = cpu_tsptr(env);
4049
4050 tsptr->tstate = (get_ccr() << 32) |
4051 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
4052 get_cwp64();
4053 tsptr->tpc = env->pc;
4054 tsptr->tnpc = env->npc;
4055 tsptr->tt = intno;
4056
4057 switch (intno) {
4058 case TT_IVEC:
4059 change_pstate(PS_PEF | PS_PRIV | PS_IG);
4060 break;
4061 case TT_TFAULT:
4062 case TT_DFAULT:
4063 case TT_TMISS ... TT_TMISS + 3:
4064 case TT_DMISS ... TT_DMISS + 3:
4065 case TT_DPROT ... TT_DPROT + 3:
4066 change_pstate(PS_PEF | PS_PRIV | PS_MG);
4067 break;
4068 default:
4069 change_pstate(PS_PEF | PS_PRIV | PS_AG);
4070 break;
4071 }
4072
4073 if (intno == TT_CLRWIN) {
4074 set_cwp(cwp_dec(env->cwp - 1));
4075 } else if ((intno & 0x1c0) == TT_SPILL) {
4076 set_cwp(cwp_dec(env->cwp - env->cansave - 2));
4077 } else if ((intno & 0x1c0) == TT_FILL) {
4078 set_cwp(cwp_inc(env->cwp + 1));
4079 }
4080 env->tbr &= ~0x7fffULL;
4081 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
4082 env->pc = env->tbr;
4083 env->npc = env->pc + 4;
4084 env->exception_index = -1;
4085 }
4086 #else
4087 #ifdef DEBUG_PCALL
4088 static const char * const excp_names[0x80] = {
4089 [TT_TFAULT] = "Instruction Access Fault",
4090 [TT_ILL_INSN] = "Illegal Instruction",
4091 [TT_PRIV_INSN] = "Privileged Instruction",
4092 [TT_NFPU_INSN] = "FPU Disabled",
4093 [TT_WIN_OVF] = "Window Overflow",
4094 [TT_WIN_UNF] = "Window Underflow",
4095 [TT_UNALIGNED] = "Unaligned Memory Access",
4096 [TT_FP_EXCP] = "FPU Exception",
4097 [TT_DFAULT] = "Data Access Fault",
4098 [TT_TOVF] = "Tag Overflow",
4099 [TT_EXTINT | 0x1] = "External Interrupt 1",
4100 [TT_EXTINT | 0x2] = "External Interrupt 2",
4101 [TT_EXTINT | 0x3] = "External Interrupt 3",
4102 [TT_EXTINT | 0x4] = "External Interrupt 4",
4103 [TT_EXTINT | 0x5] = "External Interrupt 5",
4104 [TT_EXTINT | 0x6] = "External Interrupt 6",
4105 [TT_EXTINT | 0x7] = "External Interrupt 7",
4106 [TT_EXTINT | 0x8] = "External Interrupt 8",
4107 [TT_EXTINT | 0x9] = "External Interrupt 9",
4108 [TT_EXTINT | 0xa] = "External Interrupt 10",
4109 [TT_EXTINT | 0xb] = "External Interrupt 11",
4110 [TT_EXTINT | 0xc] = "External Interrupt 12",
4111 [TT_EXTINT | 0xd] = "External Interrupt 13",
4112 [TT_EXTINT | 0xe] = "External Interrupt 14",
4113 [TT_EXTINT | 0xf] = "External Interrupt 15",
4114 [TT_TOVF] = "Tag Overflow",
4115 [TT_CODE_ACCESS] = "Instruction Access Error",
4116 [TT_DATA_ACCESS] = "Data Access Error",
4117 [TT_DIV_ZERO] = "Division By Zero",
4118 [TT_NCP_INSN] = "Coprocessor Disabled",
4119 };
4120 #endif
4121
4122 void do_interrupt(CPUState *env)
4123 {
4124 int cwp, intno = env->exception_index;
4125
4126 #ifdef DEBUG_PCALL
4127 if (qemu_loglevel_mask(CPU_LOG_INT)) {
4128 static int count;
4129 const char *name;
4130
4131 if (intno < 0 || intno >= 0x100)
4132 name = "Unknown";
4133 else if (intno >= 0x80)
4134 name = "Trap Instruction";
4135 else {
4136 name = excp_names[intno];
4137 if (!name)
4138 name = "Unknown";
4139 }
4140
4141 qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
4142 count, name, intno,
4143 env->pc,
4144 env->npc, env->regwptr[6]);
4145 log_cpu_state(env, 0);
4146 #if 0
4147 {
4148 int i;
4149 uint8_t *ptr;
4150
4151 qemu_log(" code=");
4152 ptr = (uint8_t *)env->pc;
4153 for(i = 0; i < 16; i++) {
4154 qemu_log(" %02x", ldub(ptr + i));
4155 }
4156 qemu_log("\n");
4157 }
4158 #endif
4159 count++;
4160 }
4161 #endif
4162 #if !defined(CONFIG_USER_ONLY)
4163 if (env->psret == 0) {
4164 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
4165 env->exception_index);
4166 return;
4167 }
4168 #endif
4169 env->psret = 0;
4170 cwp = cwp_dec(env->cwp - 1);
4171 set_cwp(cwp);
4172 env->regwptr[9] = env->pc;
4173 env->regwptr[10] = env->npc;
4174 env->psrps = env->psrs;
4175 env->psrs = 1;
4176 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
4177 env->pc = env->tbr;
4178 env->npc = env->pc + 4;
4179 env->exception_index = -1;
4180 }
4181 #endif
4182
4183 #if !defined(CONFIG_USER_ONLY)
4184
4185 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
4186 void *retaddr);
4187
4188 #define MMUSUFFIX _mmu
4189 #define ALIGNED_ONLY
4190
4191 #define SHIFT 0
4192 #include "softmmu_template.h"
4193
4194 #define SHIFT 1
4195 #include "softmmu_template.h"
4196
4197 #define SHIFT 2
4198 #include "softmmu_template.h"
4199
4200 #define SHIFT 3
4201 #include "softmmu_template.h"
4202
4203 /* XXX: make it generic ? */
4204 static void cpu_restore_state2(void *retaddr)
4205 {
4206 TranslationBlock *tb;
4207 unsigned long pc;
4208
4209 if (retaddr) {
4210 /* now we have a real cpu fault */
4211 pc = (unsigned long)retaddr;
4212 tb = tb_find_pc(pc);
4213 if (tb) {
4214 /* the PC is inside the translated code. It means that we have
4215 a virtual CPU fault */
4216 cpu_restore_state(tb, env, pc, (void *)(long)env->cond);
4217 }
4218 }
4219 }
4220
4221 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
4222 void *retaddr)
4223 {
4224 #ifdef DEBUG_UNALIGNED
4225 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
4226 "\n", addr, env->pc);
4227 #endif
4228 cpu_restore_state2(retaddr);
4229 raise_exception(TT_UNALIGNED);
4230 }
4231
4232 /* try to fill the TLB and return an exception if error. If retaddr is
4233 NULL, it means that the function was called in C code (i.e. not
4234 from generated code or from helper.c) */
4235 /* XXX: fix it to restore all registers */
4236 void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
4237 {
4238 int ret;
4239 CPUState *saved_env;
4240
4241 /* XXX: hack to restore env in all cases, even if not called from
4242 generated code */
4243 saved_env = env;
4244 env = cpu_single_env;
4245
4246 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
4247 if (ret) {
4248 cpu_restore_state2(retaddr);
4249 cpu_loop_exit();
4250 }
4251 env = saved_env;
4252 }
4253
4254 #endif /* !CONFIG_USER_ONLY */
4255
4256 #ifndef TARGET_SPARC64
4257 #if !defined(CONFIG_USER_ONLY)
4258 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
4259 int is_asi, int size)
4260 {
4261 CPUState *saved_env;
4262 int fault_type;
4263
4264 /* XXX: hack to restore env in all cases, even if not called from
4265 generated code */
4266 saved_env = env;
4267 env = cpu_single_env;
4268 #ifdef DEBUG_UNASSIGNED
4269 if (is_asi)
4270 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
4271 " asi 0x%02x from " TARGET_FMT_lx "\n",
4272 is_exec ? "exec" : is_write ? "write" : "read", size,
4273 size == 1 ? "" : "s", addr, is_asi, env->pc);
4274 else
4275 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
4276 " from " TARGET_FMT_lx "\n",
4277 is_exec ? "exec" : is_write ? "write" : "read", size,
4278 size == 1 ? "" : "s", addr, env->pc);
4279 #endif
4280 /* Don't overwrite translation and access faults */
4281 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
4282 if ((fault_type > 4) || (fault_type == 0)) {
4283 env->mmuregs[3] = 0; /* Fault status register */
4284 if (is_asi)
4285 env->mmuregs[3] |= 1 << 16;
4286 if (env->psrs)
4287 env->mmuregs[3] |= 1 << 5;
4288 if (is_exec)
4289 env->mmuregs[3] |= 1 << 6;
4290 if (is_write)
4291 env->mmuregs[3] |= 1 << 7;
4292 env->mmuregs[3] |= (5 << 2) | 2;
4293 /* SuperSPARC will never place instruction fault addresses in the FAR */
4294 if (!is_exec) {
4295 env->mmuregs[4] = addr; /* Fault address register */
4296 }
4297 }
4298 /* overflow (same type fault was not read before another fault) */
4299 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
4300 env->mmuregs[3] |= 1;
4301 }
4302
4303 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
4304 if (is_exec)
4305 raise_exception(TT_CODE_ACCESS);
4306 else
4307 raise_exception(TT_DATA_ACCESS);
4308 }
4309
4310 /* flush neverland mappings created during no-fault mode,
4311 so the sequential MMU faults report proper fault types */
4312 if (env->mmuregs[0] & MMU_NF) {
4313 tlb_flush(env, 1);
4314 }
4315
4316 env = saved_env;
4317 }
4318 #endif
4319 #else
4320 #if defined(CONFIG_USER_ONLY)
4321 static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
4322 int is_asi, int size)
4323 #else
4324 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
4325 int is_asi, int size)
4326 #endif
4327 {
4328 CPUState *saved_env;
4329
4330 /* XXX: hack to restore env in all cases, even if not called from
4331 generated code */
4332 saved_env = env;
4333 env = cpu_single_env;
4334
4335 #ifdef DEBUG_UNASSIGNED
4336 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
4337 "\n", addr, env->pc);
4338 #endif
4339
4340 if (is_exec)
4341 raise_exception(TT_CODE_ACCESS);
4342 else
4343 raise_exception(TT_DATA_ACCESS);
4344
4345 env = saved_env;
4346 }
4347 #endif
4348
4349
4350 #ifdef TARGET_SPARC64
4351 void helper_tick_set_count(void *opaque, uint64_t count)
4352 {
4353 #if !defined(CONFIG_USER_ONLY)
4354 cpu_tick_set_count(opaque, count);
4355 #endif
4356 }
4357
4358 uint64_t helper_tick_get_count(void *opaque)
4359 {
4360 #if !defined(CONFIG_USER_ONLY)
4361 return cpu_tick_get_count(opaque);
4362 #else
4363 return 0;
4364 #endif
4365 }
4366
4367 void helper_tick_set_limit(void *opaque, uint64_t limit)
4368 {
4369 #if !defined(CONFIG_USER_ONLY)
4370 cpu_tick_set_limit(opaque, limit);
4371 #endif
4372 }
4373 #endif
Qemu copy for testing