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target-sparc: Inline some generation of carry for ADDX/SUBX.
[qemu.git] / target-sparc / op_helper.c
1 #include "exec.h"
2 #include "host-utils.h"
3 #include "helper.h"
4
5 //#define DEBUG_MMU
6 //#define DEBUG_MXCC
7 //#define DEBUG_UNALIGNED
8 //#define DEBUG_UNASSIGNED
9 //#define DEBUG_ASI
10 //#define DEBUG_PCALL
11 //#define DEBUG_PSTATE
12
13 #ifdef DEBUG_MMU
14 #define DPRINTF_MMU(fmt, ...) \
15 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
16 #else
17 #define DPRINTF_MMU(fmt, ...) do {} while (0)
18 #endif
19
20 #ifdef DEBUG_MXCC
21 #define DPRINTF_MXCC(fmt, ...) \
22 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
23 #else
24 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
25 #endif
26
27 #ifdef DEBUG_ASI
28 #define DPRINTF_ASI(fmt, ...) \
29 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
30 #endif
31
32 #ifdef DEBUG_PSTATE
33 #define DPRINTF_PSTATE(fmt, ...) \
34 do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
35 #else
36 #define DPRINTF_PSTATE(fmt, ...) do {} while (0)
37 #endif
38
39 #ifdef TARGET_SPARC64
40 #ifndef TARGET_ABI32
41 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
42 #else
43 #define AM_CHECK(env1) (1)
44 #endif
45 #endif
46
47 #define DT0 (env->dt0)
48 #define DT1 (env->dt1)
49 #define QT0 (env->qt0)
50 #define QT1 (env->qt1)
51
52 #if defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
53 static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
54 int is_asi, int size);
55 #endif
56
57 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
58 // Calculates TSB pointer value for fault page size 8k or 64k
59 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
60 uint64_t tag_access_register,
61 int page_size)
62 {
63 uint64_t tsb_base = tsb_register & ~0x1fffULL;
64 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
65 int tsb_size = tsb_register & 0xf;
66
67 // discard lower 13 bits which hold tag access context
68 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
69
70 // now reorder bits
71 uint64_t tsb_base_mask = ~0x1fffULL;
72 uint64_t va = tag_access_va;
73
74 // move va bits to correct position
75 if (page_size == 8*1024) {
76 va >>= 9;
77 } else if (page_size == 64*1024) {
78 va >>= 12;
79 }
80
81 if (tsb_size) {
82 tsb_base_mask <<= tsb_size;
83 }
84
85 // calculate tsb_base mask and adjust va if split is in use
86 if (tsb_split) {
87 if (page_size == 8*1024) {
88 va &= ~(1ULL << (13 + tsb_size));
89 } else if (page_size == 64*1024) {
90 va |= (1ULL << (13 + tsb_size));
91 }
92 tsb_base_mask <<= 1;
93 }
94
95 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
96 }
97
98 // Calculates tag target register value by reordering bits
99 // in tag access register
100 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
101 {
102 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
103 }
104
105 static void replace_tlb_entry(SparcTLBEntry *tlb,
106 uint64_t tlb_tag, uint64_t tlb_tte,
107 CPUState *env1)
108 {
109 target_ulong mask, size, va, offset;
110
111 // flush page range if translation is valid
112 if (TTE_IS_VALID(tlb->tte)) {
113
114 mask = 0xffffffffffffe000ULL;
115 mask <<= 3 * ((tlb->tte >> 61) & 3);
116 size = ~mask + 1;
117
118 va = tlb->tag & mask;
119
120 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
121 tlb_flush_page(env1, va + offset);
122 }
123 }
124
125 tlb->tag = tlb_tag;
126 tlb->tte = tlb_tte;
127 }
128
129 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
130 const char* strmmu, CPUState *env1)
131 {
132 unsigned int i;
133 target_ulong mask;
134 uint64_t context;
135
136 int is_demap_context = (demap_addr >> 6) & 1;
137
138 // demap context
139 switch ((demap_addr >> 4) & 3) {
140 case 0: // primary
141 context = env1->dmmu.mmu_primary_context;
142 break;
143 case 1: // secondary
144 context = env1->dmmu.mmu_secondary_context;
145 break;
146 case 2: // nucleus
147 context = 0;
148 break;
149 case 3: // reserved
150 default:
151 return;
152 }
153
154 for (i = 0; i < 64; i++) {
155 if (TTE_IS_VALID(tlb[i].tte)) {
156
157 if (is_demap_context) {
158 // will remove non-global entries matching context value
159 if (TTE_IS_GLOBAL(tlb[i].tte) ||
160 !tlb_compare_context(&tlb[i], context)) {
161 continue;
162 }
163 } else {
164 // demap page
165 // will remove any entry matching VA
166 mask = 0xffffffffffffe000ULL;
167 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
168
169 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
170 continue;
171 }
172
173 // entry should be global or matching context value
174 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
175 !tlb_compare_context(&tlb[i], context)) {
176 continue;
177 }
178 }
179
180 replace_tlb_entry(&tlb[i], 0, 0, env1);
181 #ifdef DEBUG_MMU
182 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
183 dump_mmu(env1);
184 #endif
185 }
186 }
187 }
188
189 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
190 uint64_t tlb_tag, uint64_t tlb_tte,
191 const char* strmmu, CPUState *env1)
192 {
193 unsigned int i, replace_used;
194
195 // Try replacing invalid entry
196 for (i = 0; i < 64; i++) {
197 if (!TTE_IS_VALID(tlb[i].tte)) {
198 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
199 #ifdef DEBUG_MMU
200 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
201 dump_mmu(env1);
202 #endif
203 return;
204 }
205 }
206
207 // All entries are valid, try replacing unlocked entry
208
209 for (replace_used = 0; replace_used < 2; ++replace_used) {
210
211 // Used entries are not replaced on first pass
212
213 for (i = 0; i < 64; i++) {
214 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
215
216 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
217 #ifdef DEBUG_MMU
218 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
219 strmmu, (replace_used?"used":"unused"), i);
220 dump_mmu(env1);
221 #endif
222 return;
223 }
224 }
225
226 // Now reset used bit and search for unused entries again
227
228 for (i = 0; i < 64; i++) {
229 TTE_SET_UNUSED(tlb[i].tte);
230 }
231 }
232
233 #ifdef DEBUG_MMU
234 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
235 #endif
236 // error state?
237 }
238
239 #endif
240
241 static inline target_ulong address_mask(CPUState *env1, target_ulong addr)
242 {
243 #ifdef TARGET_SPARC64
244 if (AM_CHECK(env1))
245 addr &= 0xffffffffULL;
246 #endif
247 return addr;
248 }
249
250 static void raise_exception(int tt)
251 {
252 env->exception_index = tt;
253 cpu_loop_exit();
254 }
255
256 void HELPER(raise_exception)(int tt)
257 {
258 raise_exception(tt);
259 }
260
261 void helper_check_align(target_ulong addr, uint32_t align)
262 {
263 if (addr & align) {
264 #ifdef DEBUG_UNALIGNED
265 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
266 "\n", addr, env->pc);
267 #endif
268 raise_exception(TT_UNALIGNED);
269 }
270 }
271
272 #define F_HELPER(name, p) void helper_f##name##p(void)
273
274 #define F_BINOP(name) \
275 float32 helper_f ## name ## s (float32 src1, float32 src2) \
276 { \
277 return float32_ ## name (src1, src2, &env->fp_status); \
278 } \
279 F_HELPER(name, d) \
280 { \
281 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
282 } \
283 F_HELPER(name, q) \
284 { \
285 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
286 }
287
288 F_BINOP(add);
289 F_BINOP(sub);
290 F_BINOP(mul);
291 F_BINOP(div);
292 #undef F_BINOP
293
294 void helper_fsmuld(float32 src1, float32 src2)
295 {
296 DT0 = float64_mul(float32_to_float64(src1, &env->fp_status),
297 float32_to_float64(src2, &env->fp_status),
298 &env->fp_status);
299 }
300
301 void helper_fdmulq(void)
302 {
303 QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
304 float64_to_float128(DT1, &env->fp_status),
305 &env->fp_status);
306 }
307
308 float32 helper_fnegs(float32 src)
309 {
310 return float32_chs(src);
311 }
312
313 #ifdef TARGET_SPARC64
314 F_HELPER(neg, d)
315 {
316 DT0 = float64_chs(DT1);
317 }
318
319 F_HELPER(neg, q)
320 {
321 QT0 = float128_chs(QT1);
322 }
323 #endif
324
325 /* Integer to float conversion. */
326 float32 helper_fitos(int32_t src)
327 {
328 return int32_to_float32(src, &env->fp_status);
329 }
330
331 void helper_fitod(int32_t src)
332 {
333 DT0 = int32_to_float64(src, &env->fp_status);
334 }
335
336 void helper_fitoq(int32_t src)
337 {
338 QT0 = int32_to_float128(src, &env->fp_status);
339 }
340
341 #ifdef TARGET_SPARC64
342 float32 helper_fxtos(void)
343 {
344 return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
345 }
346
347 F_HELPER(xto, d)
348 {
349 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
350 }
351
352 F_HELPER(xto, q)
353 {
354 QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
355 }
356 #endif
357 #undef F_HELPER
358
359 /* floating point conversion */
360 float32 helper_fdtos(void)
361 {
362 return float64_to_float32(DT1, &env->fp_status);
363 }
364
365 void helper_fstod(float32 src)
366 {
367 DT0 = float32_to_float64(src, &env->fp_status);
368 }
369
370 float32 helper_fqtos(void)
371 {
372 return float128_to_float32(QT1, &env->fp_status);
373 }
374
375 void helper_fstoq(float32 src)
376 {
377 QT0 = float32_to_float128(src, &env->fp_status);
378 }
379
380 void helper_fqtod(void)
381 {
382 DT0 = float128_to_float64(QT1, &env->fp_status);
383 }
384
385 void helper_fdtoq(void)
386 {
387 QT0 = float64_to_float128(DT1, &env->fp_status);
388 }
389
390 /* Float to integer conversion. */
391 int32_t helper_fstoi(float32 src)
392 {
393 return float32_to_int32_round_to_zero(src, &env->fp_status);
394 }
395
396 int32_t helper_fdtoi(void)
397 {
398 return float64_to_int32_round_to_zero(DT1, &env->fp_status);
399 }
400
401 int32_t helper_fqtoi(void)
402 {
403 return float128_to_int32_round_to_zero(QT1, &env->fp_status);
404 }
405
406 #ifdef TARGET_SPARC64
407 void helper_fstox(float32 src)
408 {
409 *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status);
410 }
411
412 void helper_fdtox(void)
413 {
414 *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
415 }
416
417 void helper_fqtox(void)
418 {
419 *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
420 }
421
422 void helper_faligndata(void)
423 {
424 uint64_t tmp;
425
426 tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
427 /* on many architectures a shift of 64 does nothing */
428 if ((env->gsr & 7) != 0) {
429 tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
430 }
431 *((uint64_t *)&DT0) = tmp;
432 }
433
434 #ifdef HOST_WORDS_BIGENDIAN
435 #define VIS_B64(n) b[7 - (n)]
436 #define VIS_W64(n) w[3 - (n)]
437 #define VIS_SW64(n) sw[3 - (n)]
438 #define VIS_L64(n) l[1 - (n)]
439 #define VIS_B32(n) b[3 - (n)]
440 #define VIS_W32(n) w[1 - (n)]
441 #else
442 #define VIS_B64(n) b[n]
443 #define VIS_W64(n) w[n]
444 #define VIS_SW64(n) sw[n]
445 #define VIS_L64(n) l[n]
446 #define VIS_B32(n) b[n]
447 #define VIS_W32(n) w[n]
448 #endif
449
450 typedef union {
451 uint8_t b[8];
452 uint16_t w[4];
453 int16_t sw[4];
454 uint32_t l[2];
455 float64 d;
456 } vis64;
457
458 typedef union {
459 uint8_t b[4];
460 uint16_t w[2];
461 uint32_t l;
462 float32 f;
463 } vis32;
464
465 void helper_fpmerge(void)
466 {
467 vis64 s, d;
468
469 s.d = DT0;
470 d.d = DT1;
471
472 // Reverse calculation order to handle overlap
473 d.VIS_B64(7) = s.VIS_B64(3);
474 d.VIS_B64(6) = d.VIS_B64(3);
475 d.VIS_B64(5) = s.VIS_B64(2);
476 d.VIS_B64(4) = d.VIS_B64(2);
477 d.VIS_B64(3) = s.VIS_B64(1);
478 d.VIS_B64(2) = d.VIS_B64(1);
479 d.VIS_B64(1) = s.VIS_B64(0);
480 //d.VIS_B64(0) = d.VIS_B64(0);
481
482 DT0 = d.d;
483 }
484
485 void helper_fmul8x16(void)
486 {
487 vis64 s, d;
488 uint32_t tmp;
489
490 s.d = DT0;
491 d.d = DT1;
492
493 #define PMUL(r) \
494 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
495 if ((tmp & 0xff) > 0x7f) \
496 tmp += 0x100; \
497 d.VIS_W64(r) = tmp >> 8;
498
499 PMUL(0);
500 PMUL(1);
501 PMUL(2);
502 PMUL(3);
503 #undef PMUL
504
505 DT0 = d.d;
506 }
507
508 void helper_fmul8x16al(void)
509 {
510 vis64 s, d;
511 uint32_t tmp;
512
513 s.d = DT0;
514 d.d = DT1;
515
516 #define PMUL(r) \
517 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
518 if ((tmp & 0xff) > 0x7f) \
519 tmp += 0x100; \
520 d.VIS_W64(r) = tmp >> 8;
521
522 PMUL(0);
523 PMUL(1);
524 PMUL(2);
525 PMUL(3);
526 #undef PMUL
527
528 DT0 = d.d;
529 }
530
531 void helper_fmul8x16au(void)
532 {
533 vis64 s, d;
534 uint32_t tmp;
535
536 s.d = DT0;
537 d.d = DT1;
538
539 #define PMUL(r) \
540 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
541 if ((tmp & 0xff) > 0x7f) \
542 tmp += 0x100; \
543 d.VIS_W64(r) = tmp >> 8;
544
545 PMUL(0);
546 PMUL(1);
547 PMUL(2);
548 PMUL(3);
549 #undef PMUL
550
551 DT0 = d.d;
552 }
553
554 void helper_fmul8sux16(void)
555 {
556 vis64 s, d;
557 uint32_t tmp;
558
559 s.d = DT0;
560 d.d = DT1;
561
562 #define PMUL(r) \
563 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
564 if ((tmp & 0xff) > 0x7f) \
565 tmp += 0x100; \
566 d.VIS_W64(r) = tmp >> 8;
567
568 PMUL(0);
569 PMUL(1);
570 PMUL(2);
571 PMUL(3);
572 #undef PMUL
573
574 DT0 = d.d;
575 }
576
577 void helper_fmul8ulx16(void)
578 {
579 vis64 s, d;
580 uint32_t tmp;
581
582 s.d = DT0;
583 d.d = DT1;
584
585 #define PMUL(r) \
586 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
587 if ((tmp & 0xff) > 0x7f) \
588 tmp += 0x100; \
589 d.VIS_W64(r) = tmp >> 8;
590
591 PMUL(0);
592 PMUL(1);
593 PMUL(2);
594 PMUL(3);
595 #undef PMUL
596
597 DT0 = d.d;
598 }
599
600 void helper_fmuld8sux16(void)
601 {
602 vis64 s, d;
603 uint32_t tmp;
604
605 s.d = DT0;
606 d.d = DT1;
607
608 #define PMUL(r) \
609 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
610 if ((tmp & 0xff) > 0x7f) \
611 tmp += 0x100; \
612 d.VIS_L64(r) = tmp;
613
614 // Reverse calculation order to handle overlap
615 PMUL(1);
616 PMUL(0);
617 #undef PMUL
618
619 DT0 = d.d;
620 }
621
622 void helper_fmuld8ulx16(void)
623 {
624 vis64 s, d;
625 uint32_t tmp;
626
627 s.d = DT0;
628 d.d = DT1;
629
630 #define PMUL(r) \
631 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
632 if ((tmp & 0xff) > 0x7f) \
633 tmp += 0x100; \
634 d.VIS_L64(r) = tmp;
635
636 // Reverse calculation order to handle overlap
637 PMUL(1);
638 PMUL(0);
639 #undef PMUL
640
641 DT0 = d.d;
642 }
643
644 void helper_fexpand(void)
645 {
646 vis32 s;
647 vis64 d;
648
649 s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
650 d.d = DT1;
651 d.VIS_W64(0) = s.VIS_B32(0) << 4;
652 d.VIS_W64(1) = s.VIS_B32(1) << 4;
653 d.VIS_W64(2) = s.VIS_B32(2) << 4;
654 d.VIS_W64(3) = s.VIS_B32(3) << 4;
655
656 DT0 = d.d;
657 }
658
659 #define VIS_HELPER(name, F) \
660 void name##16(void) \
661 { \
662 vis64 s, d; \
663 \
664 s.d = DT0; \
665 d.d = DT1; \
666 \
667 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
668 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
669 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
670 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
671 \
672 DT0 = d.d; \
673 } \
674 \
675 uint32_t name##16s(uint32_t src1, uint32_t src2) \
676 { \
677 vis32 s, d; \
678 \
679 s.l = src1; \
680 d.l = src2; \
681 \
682 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
683 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
684 \
685 return d.l; \
686 } \
687 \
688 void name##32(void) \
689 { \
690 vis64 s, d; \
691 \
692 s.d = DT0; \
693 d.d = DT1; \
694 \
695 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
696 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
697 \
698 DT0 = d.d; \
699 } \
700 \
701 uint32_t name##32s(uint32_t src1, uint32_t src2) \
702 { \
703 vis32 s, d; \
704 \
705 s.l = src1; \
706 d.l = src2; \
707 \
708 d.l = F(d.l, s.l); \
709 \
710 return d.l; \
711 }
712
713 #define FADD(a, b) ((a) + (b))
714 #define FSUB(a, b) ((a) - (b))
715 VIS_HELPER(helper_fpadd, FADD)
716 VIS_HELPER(helper_fpsub, FSUB)
717
718 #define VIS_CMPHELPER(name, F) \
719 void name##16(void) \
720 { \
721 vis64 s, d; \
722 \
723 s.d = DT0; \
724 d.d = DT1; \
725 \
726 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
727 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
728 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
729 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
730 \
731 DT0 = d.d; \
732 } \
733 \
734 void name##32(void) \
735 { \
736 vis64 s, d; \
737 \
738 s.d = DT0; \
739 d.d = DT1; \
740 \
741 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
742 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
743 \
744 DT0 = d.d; \
745 }
746
747 #define FCMPGT(a, b) ((a) > (b))
748 #define FCMPEQ(a, b) ((a) == (b))
749 #define FCMPLE(a, b) ((a) <= (b))
750 #define FCMPNE(a, b) ((a) != (b))
751
752 VIS_CMPHELPER(helper_fcmpgt, FCMPGT)
753 VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
754 VIS_CMPHELPER(helper_fcmple, FCMPLE)
755 VIS_CMPHELPER(helper_fcmpne, FCMPNE)
756 #endif
757
758 void helper_check_ieee_exceptions(void)
759 {
760 target_ulong status;
761
762 status = get_float_exception_flags(&env->fp_status);
763 if (status) {
764 /* Copy IEEE 754 flags into FSR */
765 if (status & float_flag_invalid)
766 env->fsr |= FSR_NVC;
767 if (status & float_flag_overflow)
768 env->fsr |= FSR_OFC;
769 if (status & float_flag_underflow)
770 env->fsr |= FSR_UFC;
771 if (status & float_flag_divbyzero)
772 env->fsr |= FSR_DZC;
773 if (status & float_flag_inexact)
774 env->fsr |= FSR_NXC;
775
776 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
777 /* Unmasked exception, generate a trap */
778 env->fsr |= FSR_FTT_IEEE_EXCP;
779 raise_exception(TT_FP_EXCP);
780 } else {
781 /* Accumulate exceptions */
782 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
783 }
784 }
785 }
786
787 void helper_clear_float_exceptions(void)
788 {
789 set_float_exception_flags(0, &env->fp_status);
790 }
791
792 float32 helper_fabss(float32 src)
793 {
794 return float32_abs(src);
795 }
796
797 #ifdef TARGET_SPARC64
798 void helper_fabsd(void)
799 {
800 DT0 = float64_abs(DT1);
801 }
802
803 void helper_fabsq(void)
804 {
805 QT0 = float128_abs(QT1);
806 }
807 #endif
808
809 float32 helper_fsqrts(float32 src)
810 {
811 return float32_sqrt(src, &env->fp_status);
812 }
813
814 void helper_fsqrtd(void)
815 {
816 DT0 = float64_sqrt(DT1, &env->fp_status);
817 }
818
819 void helper_fsqrtq(void)
820 {
821 QT0 = float128_sqrt(QT1, &env->fp_status);
822 }
823
824 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
825 void glue(helper_, name) (void) \
826 { \
827 target_ulong new_fsr; \
828 \
829 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
830 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
831 case float_relation_unordered: \
832 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
833 if ((env->fsr & FSR_NVM) || TRAP) { \
834 env->fsr |= new_fsr; \
835 env->fsr |= FSR_NVC; \
836 env->fsr |= FSR_FTT_IEEE_EXCP; \
837 raise_exception(TT_FP_EXCP); \
838 } else { \
839 env->fsr |= FSR_NVA; \
840 } \
841 break; \
842 case float_relation_less: \
843 new_fsr = FSR_FCC0 << FS; \
844 break; \
845 case float_relation_greater: \
846 new_fsr = FSR_FCC1 << FS; \
847 break; \
848 default: \
849 new_fsr = 0; \
850 break; \
851 } \
852 env->fsr |= new_fsr; \
853 }
854 #define GEN_FCMPS(name, size, FS, TRAP) \
855 void glue(helper_, name)(float32 src1, float32 src2) \
856 { \
857 target_ulong new_fsr; \
858 \
859 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
860 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
861 case float_relation_unordered: \
862 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
863 if ((env->fsr & FSR_NVM) || TRAP) { \
864 env->fsr |= new_fsr; \
865 env->fsr |= FSR_NVC; \
866 env->fsr |= FSR_FTT_IEEE_EXCP; \
867 raise_exception(TT_FP_EXCP); \
868 } else { \
869 env->fsr |= FSR_NVA; \
870 } \
871 break; \
872 case float_relation_less: \
873 new_fsr = FSR_FCC0 << FS; \
874 break; \
875 case float_relation_greater: \
876 new_fsr = FSR_FCC1 << FS; \
877 break; \
878 default: \
879 new_fsr = 0; \
880 break; \
881 } \
882 env->fsr |= new_fsr; \
883 }
884
885 GEN_FCMPS(fcmps, float32, 0, 0);
886 GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
887
888 GEN_FCMPS(fcmpes, float32, 0, 1);
889 GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
890
891 GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
892 GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
893
894 static uint32_t compute_all_flags(void)
895 {
896 return env->psr & PSR_ICC;
897 }
898
899 static uint32_t compute_C_flags(void)
900 {
901 return env->psr & PSR_CARRY;
902 }
903
904 static inline uint32_t get_NZ_icc(int32_t dst)
905 {
906 uint32_t ret = 0;
907
908 if (dst == 0) {
909 ret = PSR_ZERO;
910 } else if (dst < 0) {
911 ret = PSR_NEG;
912 }
913 return ret;
914 }
915
916 #ifdef TARGET_SPARC64
917 static uint32_t compute_all_flags_xcc(void)
918 {
919 return env->xcc & PSR_ICC;
920 }
921
922 static uint32_t compute_C_flags_xcc(void)
923 {
924 return env->xcc & PSR_CARRY;
925 }
926
927 static inline uint32_t get_NZ_xcc(target_long dst)
928 {
929 uint32_t ret = 0;
930
931 if (!dst) {
932 ret = PSR_ZERO;
933 } else if (dst < 0) {
934 ret = PSR_NEG;
935 }
936 return ret;
937 }
938 #endif
939
940 static inline uint32_t get_V_div_icc(target_ulong src2)
941 {
942 uint32_t ret = 0;
943
944 if (src2 != 0) {
945 ret = PSR_OVF;
946 }
947 return ret;
948 }
949
950 static uint32_t compute_all_div(void)
951 {
952 uint32_t ret;
953
954 ret = get_NZ_icc(CC_DST);
955 ret |= get_V_div_icc(CC_SRC2);
956 return ret;
957 }
958
959 static uint32_t compute_C_div(void)
960 {
961 return 0;
962 }
963
964 static inline uint32_t get_C_add_icc(uint32_t dst, uint32_t src1)
965 {
966 uint32_t ret = 0;
967
968 if (dst < src1) {
969 ret = PSR_CARRY;
970 }
971 return ret;
972 }
973
974 static inline uint32_t get_C_addx_icc(uint32_t dst, uint32_t src1,
975 uint32_t src2)
976 {
977 uint32_t ret = 0;
978
979 if (((src1 & src2) | (~dst & (src1 | src2))) & (1U << 31)) {
980 ret = PSR_CARRY;
981 }
982 return ret;
983 }
984
985 static inline uint32_t get_V_add_icc(uint32_t dst, uint32_t src1,
986 uint32_t src2)
987 {
988 uint32_t ret = 0;
989
990 if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1U << 31)) {
991 ret = PSR_OVF;
992 }
993 return ret;
994 }
995
996 #ifdef TARGET_SPARC64
997 static inline uint32_t get_C_add_xcc(target_ulong dst, target_ulong src1)
998 {
999 uint32_t ret = 0;
1000
1001 if (dst < src1) {
1002 ret = PSR_CARRY;
1003 }
1004 return ret;
1005 }
1006
1007 static inline uint32_t get_C_addx_xcc(target_ulong dst, target_ulong src1,
1008 target_ulong src2)
1009 {
1010 uint32_t ret = 0;
1011
1012 if (((src1 & src2) | (~dst & (src1 | src2))) & (1ULL << 63)) {
1013 ret = PSR_CARRY;
1014 }
1015 return ret;
1016 }
1017
1018 static inline uint32_t get_V_add_xcc(target_ulong dst, target_ulong src1,
1019 target_ulong src2)
1020 {
1021 uint32_t ret = 0;
1022
1023 if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1ULL << 63)) {
1024 ret = PSR_OVF;
1025 }
1026 return ret;
1027 }
1028
1029 static uint32_t compute_all_add_xcc(void)
1030 {
1031 uint32_t ret;
1032
1033 ret = get_NZ_xcc(CC_DST);
1034 ret |= get_C_add_xcc(CC_DST, CC_SRC);
1035 ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2);
1036 return ret;
1037 }
1038
1039 static uint32_t compute_C_add_xcc(void)
1040 {
1041 return get_C_add_xcc(CC_DST, CC_SRC);
1042 }
1043 #endif
1044
1045 static uint32_t compute_all_add(void)
1046 {
1047 uint32_t ret;
1048
1049 ret = get_NZ_icc(CC_DST);
1050 ret |= get_C_add_icc(CC_DST, CC_SRC);
1051 ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2);
1052 return ret;
1053 }
1054
1055 static uint32_t compute_C_add(void)
1056 {
1057 return get_C_add_icc(CC_DST, CC_SRC);
1058 }
1059
1060 #ifdef TARGET_SPARC64
1061 static uint32_t compute_all_addx_xcc(void)
1062 {
1063 uint32_t ret;
1064
1065 ret = get_NZ_xcc(CC_DST);
1066 ret |= get_C_addx_xcc(CC_DST, CC_SRC, CC_SRC2);
1067 ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2);
1068 return ret;
1069 }
1070
1071 static uint32_t compute_C_addx_xcc(void)
1072 {
1073 uint32_t ret;
1074
1075 ret = get_C_addx_xcc(CC_DST, CC_SRC, CC_SRC2);
1076 return ret;
1077 }
1078 #endif
1079
1080 static uint32_t compute_all_addx(void)
1081 {
1082 uint32_t ret;
1083
1084 ret = get_NZ_icc(CC_DST);
1085 ret |= get_C_addx_icc(CC_DST, CC_SRC, CC_SRC2);
1086 ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2);
1087 return ret;
1088 }
1089
1090 static uint32_t compute_C_addx(void)
1091 {
1092 uint32_t ret;
1093
1094 ret = get_C_addx_icc(CC_DST, CC_SRC, CC_SRC2);
1095 return ret;
1096 }
1097
1098 static inline uint32_t get_V_tag_icc(target_ulong src1, target_ulong src2)
1099 {
1100 uint32_t ret = 0;
1101
1102 if ((src1 | src2) & 0x3) {
1103 ret = PSR_OVF;
1104 }
1105 return ret;
1106 }
1107
1108 static uint32_t compute_all_tadd(void)
1109 {
1110 uint32_t ret;
1111
1112 ret = get_NZ_icc(CC_DST);
1113 ret |= get_C_add_icc(CC_DST, CC_SRC);
1114 ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2);
1115 ret |= get_V_tag_icc(CC_SRC, CC_SRC2);
1116 return ret;
1117 }
1118
1119 static uint32_t compute_all_taddtv(void)
1120 {
1121 uint32_t ret;
1122
1123 ret = get_NZ_icc(CC_DST);
1124 ret |= get_C_add_icc(CC_DST, CC_SRC);
1125 return ret;
1126 }
1127
1128 static inline uint32_t get_C_sub_icc(uint32_t src1, uint32_t src2)
1129 {
1130 uint32_t ret = 0;
1131
1132 if (src1 < src2) {
1133 ret = PSR_CARRY;
1134 }
1135 return ret;
1136 }
1137
1138 static inline uint32_t get_C_subx_icc(uint32_t dst, uint32_t src1,
1139 uint32_t src2)
1140 {
1141 uint32_t ret = 0;
1142
1143 if (((~src1 & src2) | (dst & (~src1 | src2))) & (1U << 31)) {
1144 ret = PSR_CARRY;
1145 }
1146 return ret;
1147 }
1148
1149 static inline uint32_t get_V_sub_icc(uint32_t dst, uint32_t src1,
1150 uint32_t src2)
1151 {
1152 uint32_t ret = 0;
1153
1154 if (((src1 ^ src2) & (src1 ^ dst)) & (1U << 31)) {
1155 ret = PSR_OVF;
1156 }
1157 return ret;
1158 }
1159
1160
1161 #ifdef TARGET_SPARC64
1162 static inline uint32_t get_C_sub_xcc(target_ulong src1, target_ulong src2)
1163 {
1164 uint32_t ret = 0;
1165
1166 if (src1 < src2) {
1167 ret = PSR_CARRY;
1168 }
1169 return ret;
1170 }
1171
1172 static inline uint32_t get_C_subx_xcc(target_ulong dst, target_ulong src1,
1173 target_ulong src2)
1174 {
1175 uint32_t ret = 0;
1176
1177 if (((~src1 & src2) | (dst & (~src1 | src2))) & (1ULL << 63)) {
1178 ret = PSR_CARRY;
1179 }
1180 return ret;
1181 }
1182
1183 static inline uint32_t get_V_sub_xcc(target_ulong dst, target_ulong src1,
1184 target_ulong src2)
1185 {
1186 uint32_t ret = 0;
1187
1188 if (((src1 ^ src2) & (src1 ^ dst)) & (1ULL << 63)) {
1189 ret = PSR_OVF;
1190 }
1191 return ret;
1192 }
1193
1194 static uint32_t compute_all_sub_xcc(void)
1195 {
1196 uint32_t ret;
1197
1198 ret = get_NZ_xcc(CC_DST);
1199 ret |= get_C_sub_xcc(CC_SRC, CC_SRC2);
1200 ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2);
1201 return ret;
1202 }
1203
1204 static uint32_t compute_C_sub_xcc(void)
1205 {
1206 return get_C_sub_xcc(CC_SRC, CC_SRC2);
1207 }
1208 #endif
1209
1210 static uint32_t compute_all_sub(void)
1211 {
1212 uint32_t ret;
1213
1214 ret = get_NZ_icc(CC_DST);
1215 ret |= get_C_sub_icc(CC_SRC, CC_SRC2);
1216 ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2);
1217 return ret;
1218 }
1219
1220 static uint32_t compute_C_sub(void)
1221 {
1222 return get_C_sub_icc(CC_SRC, CC_SRC2);
1223 }
1224
1225 #ifdef TARGET_SPARC64
1226 static uint32_t compute_all_subx_xcc(void)
1227 {
1228 uint32_t ret;
1229
1230 ret = get_NZ_xcc(CC_DST);
1231 ret |= get_C_subx_xcc(CC_DST, CC_SRC, CC_SRC2);
1232 ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2);
1233 return ret;
1234 }
1235
1236 static uint32_t compute_C_subx_xcc(void)
1237 {
1238 uint32_t ret;
1239
1240 ret = get_C_subx_xcc(CC_DST, CC_SRC, CC_SRC2);
1241 return ret;
1242 }
1243 #endif
1244
1245 static uint32_t compute_all_subx(void)
1246 {
1247 uint32_t ret;
1248
1249 ret = get_NZ_icc(CC_DST);
1250 ret |= get_C_subx_icc(CC_DST, CC_SRC, CC_SRC2);
1251 ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2);
1252 return ret;
1253 }
1254
1255 static uint32_t compute_C_subx(void)
1256 {
1257 uint32_t ret;
1258
1259 ret = get_C_subx_icc(CC_DST, CC_SRC, CC_SRC2);
1260 return ret;
1261 }
1262
1263 static uint32_t compute_all_tsub(void)
1264 {
1265 uint32_t ret;
1266
1267 ret = get_NZ_icc(CC_DST);
1268 ret |= get_C_sub_icc(CC_SRC, CC_SRC2);
1269 ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2);
1270 ret |= get_V_tag_icc(CC_SRC, CC_SRC2);
1271 return ret;
1272 }
1273
1274 static uint32_t compute_all_tsubtv(void)
1275 {
1276 uint32_t ret;
1277
1278 ret = get_NZ_icc(CC_DST);
1279 ret |= get_C_sub_icc(CC_SRC, CC_SRC2);
1280 return ret;
1281 }
1282
1283 static uint32_t compute_all_logic(void)
1284 {
1285 return get_NZ_icc(CC_DST);
1286 }
1287
1288 static uint32_t compute_C_logic(void)
1289 {
1290 return 0;
1291 }
1292
1293 #ifdef TARGET_SPARC64
1294 static uint32_t compute_all_logic_xcc(void)
1295 {
1296 return get_NZ_xcc(CC_DST);
1297 }
1298 #endif
1299
1300 typedef struct CCTable {
1301 uint32_t (*compute_all)(void); /* return all the flags */
1302 uint32_t (*compute_c)(void); /* return the C flag */
1303 } CCTable;
1304
1305 static const CCTable icc_table[CC_OP_NB] = {
1306 /* CC_OP_DYNAMIC should never happen */
1307 [CC_OP_FLAGS] = { compute_all_flags, compute_C_flags },
1308 [CC_OP_DIV] = { compute_all_div, compute_C_div },
1309 [CC_OP_ADD] = { compute_all_add, compute_C_add },
1310 [CC_OP_ADDX] = { compute_all_addx, compute_C_addx },
1311 [CC_OP_TADD] = { compute_all_tadd, compute_C_add },
1312 [CC_OP_TADDTV] = { compute_all_taddtv, compute_C_add },
1313 [CC_OP_SUB] = { compute_all_sub, compute_C_sub },
1314 [CC_OP_SUBX] = { compute_all_subx, compute_C_subx },
1315 [CC_OP_TSUB] = { compute_all_tsub, compute_C_sub },
1316 [CC_OP_TSUBTV] = { compute_all_tsubtv, compute_C_sub },
1317 [CC_OP_LOGIC] = { compute_all_logic, compute_C_logic },
1318 };
1319
1320 #ifdef TARGET_SPARC64
1321 static const CCTable xcc_table[CC_OP_NB] = {
1322 /* CC_OP_DYNAMIC should never happen */
1323 [CC_OP_FLAGS] = { compute_all_flags_xcc, compute_C_flags_xcc },
1324 [CC_OP_DIV] = { compute_all_logic_xcc, compute_C_logic },
1325 [CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc },
1326 [CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc },
1327 [CC_OP_TADD] = { compute_all_add_xcc, compute_C_add_xcc },
1328 [CC_OP_TADDTV] = { compute_all_add_xcc, compute_C_add_xcc },
1329 [CC_OP_SUB] = { compute_all_sub_xcc, compute_C_sub_xcc },
1330 [CC_OP_SUBX] = { compute_all_subx_xcc, compute_C_subx_xcc },
1331 [CC_OP_TSUB] = { compute_all_sub_xcc, compute_C_sub_xcc },
1332 [CC_OP_TSUBTV] = { compute_all_sub_xcc, compute_C_sub_xcc },
1333 [CC_OP_LOGIC] = { compute_all_logic_xcc, compute_C_logic },
1334 };
1335 #endif
1336
1337 void helper_compute_psr(void)
1338 {
1339 uint32_t new_psr;
1340
1341 new_psr = icc_table[CC_OP].compute_all();
1342 env->psr = new_psr;
1343 #ifdef TARGET_SPARC64
1344 new_psr = xcc_table[CC_OP].compute_all();
1345 env->xcc = new_psr;
1346 #endif
1347 CC_OP = CC_OP_FLAGS;
1348 }
1349
1350 uint32_t helper_compute_C_icc(void)
1351 {
1352 uint32_t ret;
1353
1354 ret = icc_table[CC_OP].compute_c() >> PSR_CARRY_SHIFT;
1355 return ret;
1356 }
1357
1358 static inline void memcpy32(target_ulong *dst, const target_ulong *src)
1359 {
1360 dst[0] = src[0];
1361 dst[1] = src[1];
1362 dst[2] = src[2];
1363 dst[3] = src[3];
1364 dst[4] = src[4];
1365 dst[5] = src[5];
1366 dst[6] = src[6];
1367 dst[7] = src[7];
1368 }
1369
1370 static void set_cwp(int new_cwp)
1371 {
1372 /* put the modified wrap registers at their proper location */
1373 if (env->cwp == env->nwindows - 1) {
1374 memcpy32(env->regbase, env->regbase + env->nwindows * 16);
1375 }
1376 env->cwp = new_cwp;
1377
1378 /* put the wrap registers at their temporary location */
1379 if (new_cwp == env->nwindows - 1) {
1380 memcpy32(env->regbase + env->nwindows * 16, env->regbase);
1381 }
1382 env->regwptr = env->regbase + (new_cwp * 16);
1383 }
1384
1385 void cpu_set_cwp(CPUState *env1, int new_cwp)
1386 {
1387 CPUState *saved_env;
1388
1389 saved_env = env;
1390 env = env1;
1391 set_cwp(new_cwp);
1392 env = saved_env;
1393 }
1394
1395 static target_ulong get_psr(void)
1396 {
1397 helper_compute_psr();
1398
1399 #if !defined (TARGET_SPARC64)
1400 return env->version | (env->psr & PSR_ICC) |
1401 (env->psref? PSR_EF : 0) |
1402 (env->psrpil << 8) |
1403 (env->psrs? PSR_S : 0) |
1404 (env->psrps? PSR_PS : 0) |
1405 (env->psret? PSR_ET : 0) | env->cwp;
1406 #else
1407 return env->version | (env->psr & PSR_ICC) |
1408 (env->psref? PSR_EF : 0) |
1409 (env->psrpil << 8) |
1410 (env->psrs? PSR_S : 0) |
1411 (env->psrps? PSR_PS : 0) | env->cwp;
1412 #endif
1413 }
1414
1415 target_ulong cpu_get_psr(CPUState *env1)
1416 {
1417 CPUState *saved_env;
1418 target_ulong ret;
1419
1420 saved_env = env;
1421 env = env1;
1422 ret = get_psr();
1423 env = saved_env;
1424 return ret;
1425 }
1426
1427 static void put_psr(target_ulong val)
1428 {
1429 env->psr = val & PSR_ICC;
1430 env->psref = (val & PSR_EF)? 1 : 0;
1431 env->psrpil = (val & PSR_PIL) >> 8;
1432 #if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
1433 cpu_check_irqs(env);
1434 #endif
1435 env->psrs = (val & PSR_S)? 1 : 0;
1436 env->psrps = (val & PSR_PS)? 1 : 0;
1437 #if !defined (TARGET_SPARC64)
1438 env->psret = (val & PSR_ET)? 1 : 0;
1439 #endif
1440 set_cwp(val & PSR_CWP);
1441 env->cc_op = CC_OP_FLAGS;
1442 }
1443
1444 void cpu_put_psr(CPUState *env1, target_ulong val)
1445 {
1446 CPUState *saved_env;
1447
1448 saved_env = env;
1449 env = env1;
1450 put_psr(val);
1451 env = saved_env;
1452 }
1453
1454 static int cwp_inc(int cwp)
1455 {
1456 if (unlikely(cwp >= env->nwindows)) {
1457 cwp -= env->nwindows;
1458 }
1459 return cwp;
1460 }
1461
1462 int cpu_cwp_inc(CPUState *env1, int cwp)
1463 {
1464 CPUState *saved_env;
1465 target_ulong ret;
1466
1467 saved_env = env;
1468 env = env1;
1469 ret = cwp_inc(cwp);
1470 env = saved_env;
1471 return ret;
1472 }
1473
1474 static int cwp_dec(int cwp)
1475 {
1476 if (unlikely(cwp < 0)) {
1477 cwp += env->nwindows;
1478 }
1479 return cwp;
1480 }
1481
1482 int cpu_cwp_dec(CPUState *env1, int cwp)
1483 {
1484 CPUState *saved_env;
1485 target_ulong ret;
1486
1487 saved_env = env;
1488 env = env1;
1489 ret = cwp_dec(cwp);
1490 env = saved_env;
1491 return ret;
1492 }
1493
1494 #ifdef TARGET_SPARC64
1495 GEN_FCMPS(fcmps_fcc1, float32, 22, 0);
1496 GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
1497 GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
1498
1499 GEN_FCMPS(fcmps_fcc2, float32, 24, 0);
1500 GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
1501 GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
1502
1503 GEN_FCMPS(fcmps_fcc3, float32, 26, 0);
1504 GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
1505 GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
1506
1507 GEN_FCMPS(fcmpes_fcc1, float32, 22, 1);
1508 GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
1509 GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
1510
1511 GEN_FCMPS(fcmpes_fcc2, float32, 24, 1);
1512 GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
1513 GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
1514
1515 GEN_FCMPS(fcmpes_fcc3, float32, 26, 1);
1516 GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
1517 GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
1518 #endif
1519 #undef GEN_FCMPS
1520
1521 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
1522 defined(DEBUG_MXCC)
1523 static void dump_mxcc(CPUState *env)
1524 {
1525 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
1526 "\n",
1527 env->mxccdata[0], env->mxccdata[1],
1528 env->mxccdata[2], env->mxccdata[3]);
1529 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
1530 "\n"
1531 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
1532 "\n",
1533 env->mxccregs[0], env->mxccregs[1],
1534 env->mxccregs[2], env->mxccregs[3],
1535 env->mxccregs[4], env->mxccregs[5],
1536 env->mxccregs[6], env->mxccregs[7]);
1537 }
1538 #endif
1539
1540 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
1541 && defined(DEBUG_ASI)
1542 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
1543 uint64_t r1)
1544 {
1545 switch (size)
1546 {
1547 case 1:
1548 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
1549 addr, asi, r1 & 0xff);
1550 break;
1551 case 2:
1552 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
1553 addr, asi, r1 & 0xffff);
1554 break;
1555 case 4:
1556 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
1557 addr, asi, r1 & 0xffffffff);
1558 break;
1559 case 8:
1560 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
1561 addr, asi, r1);
1562 break;
1563 }
1564 }
1565 #endif
1566
1567 #ifndef TARGET_SPARC64
1568 #ifndef CONFIG_USER_ONLY
1569 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1570 {
1571 uint64_t ret = 0;
1572 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
1573 uint32_t last_addr = addr;
1574 #endif
1575
1576 helper_check_align(addr, size - 1);
1577 switch (asi) {
1578 case 2: /* SuperSparc MXCC registers */
1579 switch (addr) {
1580 case 0x01c00a00: /* MXCC control register */
1581 if (size == 8)
1582 ret = env->mxccregs[3];
1583 else
1584 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1585 size);
1586 break;
1587 case 0x01c00a04: /* MXCC control register */
1588 if (size == 4)
1589 ret = env->mxccregs[3];
1590 else
1591 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1592 size);
1593 break;
1594 case 0x01c00c00: /* Module reset register */
1595 if (size == 8) {
1596 ret = env->mxccregs[5];
1597 // should we do something here?
1598 } else
1599 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1600 size);
1601 break;
1602 case 0x01c00f00: /* MBus port address register */
1603 if (size == 8)
1604 ret = env->mxccregs[7];
1605 else
1606 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1607 size);
1608 break;
1609 default:
1610 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
1611 size);
1612 break;
1613 }
1614 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
1615 "addr = %08x -> ret = %" PRIx64 ","
1616 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
1617 #ifdef DEBUG_MXCC
1618 dump_mxcc(env);
1619 #endif
1620 break;
1621 case 3: /* MMU probe */
1622 {
1623 int mmulev;
1624
1625 mmulev = (addr >> 8) & 15;
1626 if (mmulev > 4)
1627 ret = 0;
1628 else
1629 ret = mmu_probe(env, addr, mmulev);
1630 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
1631 addr, mmulev, ret);
1632 }
1633 break;
1634 case 4: /* read MMU regs */
1635 {
1636 int reg = (addr >> 8) & 0x1f;
1637
1638 ret = env->mmuregs[reg];
1639 if (reg == 3) /* Fault status cleared on read */
1640 env->mmuregs[3] = 0;
1641 else if (reg == 0x13) /* Fault status read */
1642 ret = env->mmuregs[3];
1643 else if (reg == 0x14) /* Fault address read */
1644 ret = env->mmuregs[4];
1645 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
1646 }
1647 break;
1648 case 5: // Turbosparc ITLB Diagnostic
1649 case 6: // Turbosparc DTLB Diagnostic
1650 case 7: // Turbosparc IOTLB Diagnostic
1651 break;
1652 case 9: /* Supervisor code access */
1653 switch(size) {
1654 case 1:
1655 ret = ldub_code(addr);
1656 break;
1657 case 2:
1658 ret = lduw_code(addr);
1659 break;
1660 default:
1661 case 4:
1662 ret = ldl_code(addr);
1663 break;
1664 case 8:
1665 ret = ldq_code(addr);
1666 break;
1667 }
1668 break;
1669 case 0xa: /* User data access */
1670 switch(size) {
1671 case 1:
1672 ret = ldub_user(addr);
1673 break;
1674 case 2:
1675 ret = lduw_user(addr);
1676 break;
1677 default:
1678 case 4:
1679 ret = ldl_user(addr);
1680 break;
1681 case 8:
1682 ret = ldq_user(addr);
1683 break;
1684 }
1685 break;
1686 case 0xb: /* Supervisor data access */
1687 switch(size) {
1688 case 1:
1689 ret = ldub_kernel(addr);
1690 break;
1691 case 2:
1692 ret = lduw_kernel(addr);
1693 break;
1694 default:
1695 case 4:
1696 ret = ldl_kernel(addr);
1697 break;
1698 case 8:
1699 ret = ldq_kernel(addr);
1700 break;
1701 }
1702 break;
1703 case 0xc: /* I-cache tag */
1704 case 0xd: /* I-cache data */
1705 case 0xe: /* D-cache tag */
1706 case 0xf: /* D-cache data */
1707 break;
1708 case 0x20: /* MMU passthrough */
1709 switch(size) {
1710 case 1:
1711 ret = ldub_phys(addr);
1712 break;
1713 case 2:
1714 ret = lduw_phys(addr);
1715 break;
1716 default:
1717 case 4:
1718 ret = ldl_phys(addr);
1719 break;
1720 case 8:
1721 ret = ldq_phys(addr);
1722 break;
1723 }
1724 break;
1725 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1726 switch(size) {
1727 case 1:
1728 ret = ldub_phys((target_phys_addr_t)addr
1729 | ((target_phys_addr_t)(asi & 0xf) << 32));
1730 break;
1731 case 2:
1732 ret = lduw_phys((target_phys_addr_t)addr
1733 | ((target_phys_addr_t)(asi & 0xf) << 32));
1734 break;
1735 default:
1736 case 4:
1737 ret = ldl_phys((target_phys_addr_t)addr
1738 | ((target_phys_addr_t)(asi & 0xf) << 32));
1739 break;
1740 case 8:
1741 ret = ldq_phys((target_phys_addr_t)addr
1742 | ((target_phys_addr_t)(asi & 0xf) << 32));
1743 break;
1744 }
1745 break;
1746 case 0x30: // Turbosparc secondary cache diagnostic
1747 case 0x31: // Turbosparc RAM snoop
1748 case 0x32: // Turbosparc page table descriptor diagnostic
1749 case 0x39: /* data cache diagnostic register */
1750 ret = 0;
1751 break;
1752 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
1753 {
1754 int reg = (addr >> 8) & 3;
1755
1756 switch(reg) {
1757 case 0: /* Breakpoint Value (Addr) */
1758 ret = env->mmubpregs[reg];
1759 break;
1760 case 1: /* Breakpoint Mask */
1761 ret = env->mmubpregs[reg];
1762 break;
1763 case 2: /* Breakpoint Control */
1764 ret = env->mmubpregs[reg];
1765 break;
1766 case 3: /* Breakpoint Status */
1767 ret = env->mmubpregs[reg];
1768 env->mmubpregs[reg] = 0ULL;
1769 break;
1770 }
1771 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
1772 ret);
1773 }
1774 break;
1775 case 8: /* User code access, XXX */
1776 default:
1777 do_unassigned_access(addr, 0, 0, asi, size);
1778 ret = 0;
1779 break;
1780 }
1781 if (sign) {
1782 switch(size) {
1783 case 1:
1784 ret = (int8_t) ret;
1785 break;
1786 case 2:
1787 ret = (int16_t) ret;
1788 break;
1789 case 4:
1790 ret = (int32_t) ret;
1791 break;
1792 default:
1793 break;
1794 }
1795 }
1796 #ifdef DEBUG_ASI
1797 dump_asi("read ", last_addr, asi, size, ret);
1798 #endif
1799 return ret;
1800 }
1801
1802 void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
1803 {
1804 helper_check_align(addr, size - 1);
1805 switch(asi) {
1806 case 2: /* SuperSparc MXCC registers */
1807 switch (addr) {
1808 case 0x01c00000: /* MXCC stream data register 0 */
1809 if (size == 8)
1810 env->mxccdata[0] = val;
1811 else
1812 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1813 size);
1814 break;
1815 case 0x01c00008: /* MXCC stream data register 1 */
1816 if (size == 8)
1817 env->mxccdata[1] = val;
1818 else
1819 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1820 size);
1821 break;
1822 case 0x01c00010: /* MXCC stream data register 2 */
1823 if (size == 8)
1824 env->mxccdata[2] = val;
1825 else
1826 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1827 size);
1828 break;
1829 case 0x01c00018: /* MXCC stream data register 3 */
1830 if (size == 8)
1831 env->mxccdata[3] = val;
1832 else
1833 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1834 size);
1835 break;
1836 case 0x01c00100: /* MXCC stream source */
1837 if (size == 8)
1838 env->mxccregs[0] = val;
1839 else
1840 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1841 size);
1842 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1843 0);
1844 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1845 8);
1846 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1847 16);
1848 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1849 24);
1850 break;
1851 case 0x01c00200: /* MXCC stream destination */
1852 if (size == 8)
1853 env->mxccregs[1] = val;
1854 else
1855 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1856 size);
1857 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
1858 env->mxccdata[0]);
1859 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
1860 env->mxccdata[1]);
1861 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
1862 env->mxccdata[2]);
1863 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
1864 env->mxccdata[3]);
1865 break;
1866 case 0x01c00a00: /* MXCC control register */
1867 if (size == 8)
1868 env->mxccregs[3] = val;
1869 else
1870 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1871 size);
1872 break;
1873 case 0x01c00a04: /* MXCC control register */
1874 if (size == 4)
1875 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
1876 | val;
1877 else
1878 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1879 size);
1880 break;
1881 case 0x01c00e00: /* MXCC error register */
1882 // writing a 1 bit clears the error
1883 if (size == 8)
1884 env->mxccregs[6] &= ~val;
1885 else
1886 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1887 size);
1888 break;
1889 case 0x01c00f00: /* MBus port address register */
1890 if (size == 8)
1891 env->mxccregs[7] = val;
1892 else
1893 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1894 size);
1895 break;
1896 default:
1897 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
1898 size);
1899 break;
1900 }
1901 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
1902 asi, size, addr, val);
1903 #ifdef DEBUG_MXCC
1904 dump_mxcc(env);
1905 #endif
1906 break;
1907 case 3: /* MMU flush */
1908 {
1909 int mmulev;
1910
1911 mmulev = (addr >> 8) & 15;
1912 DPRINTF_MMU("mmu flush level %d\n", mmulev);
1913 switch (mmulev) {
1914 case 0: // flush page
1915 tlb_flush_page(env, addr & 0xfffff000);
1916 break;
1917 case 1: // flush segment (256k)
1918 case 2: // flush region (16M)
1919 case 3: // flush context (4G)
1920 case 4: // flush entire
1921 tlb_flush(env, 1);
1922 break;
1923 default:
1924 break;
1925 }
1926 #ifdef DEBUG_MMU
1927 dump_mmu(env);
1928 #endif
1929 }
1930 break;
1931 case 4: /* write MMU regs */
1932 {
1933 int reg = (addr >> 8) & 0x1f;
1934 uint32_t oldreg;
1935
1936 oldreg = env->mmuregs[reg];
1937 switch(reg) {
1938 case 0: // Control Register
1939 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
1940 (val & 0x00ffffff);
1941 // Mappings generated during no-fault mode or MMU
1942 // disabled mode are invalid in normal mode
1943 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
1944 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm)))
1945 tlb_flush(env, 1);
1946 break;
1947 case 1: // Context Table Pointer Register
1948 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
1949 break;
1950 case 2: // Context Register
1951 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
1952 if (oldreg != env->mmuregs[reg]) {
1953 /* we flush when the MMU context changes because
1954 QEMU has no MMU context support */
1955 tlb_flush(env, 1);
1956 }
1957 break;
1958 case 3: // Synchronous Fault Status Register with Clear
1959 case 4: // Synchronous Fault Address Register
1960 break;
1961 case 0x10: // TLB Replacement Control Register
1962 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
1963 break;
1964 case 0x13: // Synchronous Fault Status Register with Read and Clear
1965 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
1966 break;
1967 case 0x14: // Synchronous Fault Address Register
1968 env->mmuregs[4] = val;
1969 break;
1970 default:
1971 env->mmuregs[reg] = val;
1972 break;
1973 }
1974 if (oldreg != env->mmuregs[reg]) {
1975 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1976 reg, oldreg, env->mmuregs[reg]);
1977 }
1978 #ifdef DEBUG_MMU
1979 dump_mmu(env);
1980 #endif
1981 }
1982 break;
1983 case 5: // Turbosparc ITLB Diagnostic
1984 case 6: // Turbosparc DTLB Diagnostic
1985 case 7: // Turbosparc IOTLB Diagnostic
1986 break;
1987 case 0xa: /* User data access */
1988 switch(size) {
1989 case 1:
1990 stb_user(addr, val);
1991 break;
1992 case 2:
1993 stw_user(addr, val);
1994 break;
1995 default:
1996 case 4:
1997 stl_user(addr, val);
1998 break;
1999 case 8:
2000 stq_user(addr, val);
2001 break;
2002 }
2003 break;
2004 case 0xb: /* Supervisor data access */
2005 switch(size) {
2006 case 1:
2007 stb_kernel(addr, val);
2008 break;
2009 case 2:
2010 stw_kernel(addr, val);
2011 break;
2012 default:
2013 case 4:
2014 stl_kernel(addr, val);
2015 break;
2016 case 8:
2017 stq_kernel(addr, val);
2018 break;
2019 }
2020 break;
2021 case 0xc: /* I-cache tag */
2022 case 0xd: /* I-cache data */
2023 case 0xe: /* D-cache tag */
2024 case 0xf: /* D-cache data */
2025 case 0x10: /* I/D-cache flush page */
2026 case 0x11: /* I/D-cache flush segment */
2027 case 0x12: /* I/D-cache flush region */
2028 case 0x13: /* I/D-cache flush context */
2029 case 0x14: /* I/D-cache flush user */
2030 break;
2031 case 0x17: /* Block copy, sta access */
2032 {
2033 // val = src
2034 // addr = dst
2035 // copy 32 bytes
2036 unsigned int i;
2037 uint32_t src = val & ~3, dst = addr & ~3, temp;
2038
2039 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
2040 temp = ldl_kernel(src);
2041 stl_kernel(dst, temp);
2042 }
2043 }
2044 break;
2045 case 0x1f: /* Block fill, stda access */
2046 {
2047 // addr = dst
2048 // fill 32 bytes with val
2049 unsigned int i;
2050 uint32_t dst = addr & 7;
2051
2052 for (i = 0; i < 32; i += 8, dst += 8)
2053 stq_kernel(dst, val);
2054 }
2055 break;
2056 case 0x20: /* MMU passthrough */
2057 {
2058 switch(size) {
2059 case 1:
2060 stb_phys(addr, val);
2061 break;
2062 case 2:
2063 stw_phys(addr, val);
2064 break;
2065 case 4:
2066 default:
2067 stl_phys(addr, val);
2068 break;
2069 case 8:
2070 stq_phys(addr, val);
2071 break;
2072 }
2073 }
2074 break;
2075 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
2076 {
2077 switch(size) {
2078 case 1:
2079 stb_phys((target_phys_addr_t)addr
2080 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
2081 break;
2082 case 2:
2083 stw_phys((target_phys_addr_t)addr
2084 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
2085 break;
2086 case 4:
2087 default:
2088 stl_phys((target_phys_addr_t)addr
2089 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
2090 break;
2091 case 8:
2092 stq_phys((target_phys_addr_t)addr
2093 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
2094 break;
2095 }
2096 }
2097 break;
2098 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
2099 case 0x31: // store buffer data, Ross RT620 I-cache flush or
2100 // Turbosparc snoop RAM
2101 case 0x32: // store buffer control or Turbosparc page table
2102 // descriptor diagnostic
2103 case 0x36: /* I-cache flash clear */
2104 case 0x37: /* D-cache flash clear */
2105 case 0x4c: /* breakpoint action */
2106 break;
2107 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
2108 {
2109 int reg = (addr >> 8) & 3;
2110
2111 switch(reg) {
2112 case 0: /* Breakpoint Value (Addr) */
2113 env->mmubpregs[reg] = (val & 0xfffffffffULL);
2114 break;
2115 case 1: /* Breakpoint Mask */
2116 env->mmubpregs[reg] = (val & 0xfffffffffULL);
2117 break;
2118 case 2: /* Breakpoint Control */
2119 env->mmubpregs[reg] = (val & 0x7fULL);
2120 break;
2121 case 3: /* Breakpoint Status */
2122 env->mmubpregs[reg] = (val & 0xfULL);
2123 break;
2124 }
2125 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
2126 env->mmuregs[reg]);
2127 }
2128 break;
2129 case 8: /* User code access, XXX */
2130 case 9: /* Supervisor code access, XXX */
2131 default:
2132 do_unassigned_access(addr, 1, 0, asi, size);
2133 break;
2134 }
2135 #ifdef DEBUG_ASI
2136 dump_asi("write", addr, asi, size, val);
2137 #endif
2138 }
2139
2140 #endif /* CONFIG_USER_ONLY */
2141 #else /* TARGET_SPARC64 */
2142
2143 #ifdef CONFIG_USER_ONLY
2144 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
2145 {
2146 uint64_t ret = 0;
2147 #if defined(DEBUG_ASI)
2148 target_ulong last_addr = addr;
2149 #endif
2150
2151 if (asi < 0x80)
2152 raise_exception(TT_PRIV_ACT);
2153
2154 helper_check_align(addr, size - 1);
2155 addr = address_mask(env, addr);
2156
2157 switch (asi) {
2158 case 0x82: // Primary no-fault
2159 case 0x8a: // Primary no-fault LE
2160 if (page_check_range(addr, size, PAGE_READ) == -1) {
2161 #ifdef DEBUG_ASI
2162 dump_asi("read ", last_addr, asi, size, ret);
2163 #endif
2164 return 0;
2165 }
2166 // Fall through
2167 case 0x80: // Primary
2168 case 0x88: // Primary LE
2169 {
2170 switch(size) {
2171 case 1:
2172 ret = ldub_raw(addr);
2173 break;
2174 case 2:
2175 ret = lduw_raw(addr);
2176 break;
2177 case 4:
2178 ret = ldl_raw(addr);
2179 break;
2180 default:
2181 case 8:
2182 ret = ldq_raw(addr);
2183 break;
2184 }
2185 }
2186 break;
2187 case 0x83: // Secondary no-fault
2188 case 0x8b: // Secondary no-fault LE
2189 if (page_check_range(addr, size, PAGE_READ) == -1) {
2190 #ifdef DEBUG_ASI
2191 dump_asi("read ", last_addr, asi, size, ret);
2192 #endif
2193 return 0;
2194 }
2195 // Fall through
2196 case 0x81: // Secondary
2197 case 0x89: // Secondary LE
2198 // XXX
2199 break;
2200 default:
2201 break;
2202 }
2203
2204 /* Convert from little endian */
2205 switch (asi) {
2206 case 0x88: // Primary LE
2207 case 0x89: // Secondary LE
2208 case 0x8a: // Primary no-fault LE
2209 case 0x8b: // Secondary no-fault LE
2210 switch(size) {
2211 case 2:
2212 ret = bswap16(ret);
2213 break;
2214 case 4:
2215 ret = bswap32(ret);
2216 break;
2217 case 8:
2218 ret = bswap64(ret);
2219 break;
2220 default:
2221 break;
2222 }
2223 default:
2224 break;
2225 }
2226
2227 /* Convert to signed number */
2228 if (sign) {
2229 switch(size) {
2230 case 1:
2231 ret = (int8_t) ret;
2232 break;
2233 case 2:
2234 ret = (int16_t) ret;
2235 break;
2236 case 4:
2237 ret = (int32_t) ret;
2238 break;
2239 default:
2240 break;
2241 }
2242 }
2243 #ifdef DEBUG_ASI
2244 dump_asi("read ", last_addr, asi, size, ret);
2245 #endif
2246 return ret;
2247 }
2248
2249 void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
2250 {
2251 #ifdef DEBUG_ASI
2252 dump_asi("write", addr, asi, size, val);
2253 #endif
2254 if (asi < 0x80)
2255 raise_exception(TT_PRIV_ACT);
2256
2257 helper_check_align(addr, size - 1);
2258 addr = address_mask(env, addr);
2259
2260 /* Convert to little endian */
2261 switch (asi) {
2262 case 0x88: // Primary LE
2263 case 0x89: // Secondary LE
2264 switch(size) {
2265 case 2:
2266 val = bswap16(val);
2267 break;
2268 case 4:
2269 val = bswap32(val);
2270 break;
2271 case 8:
2272 val = bswap64(val);
2273 break;
2274 default:
2275 break;
2276 }
2277 default:
2278 break;
2279 }
2280
2281 switch(asi) {
2282 case 0x80: // Primary
2283 case 0x88: // Primary LE
2284 {
2285 switch(size) {
2286 case 1:
2287 stb_raw(addr, val);
2288 break;
2289 case 2:
2290 stw_raw(addr, val);
2291 break;
2292 case 4:
2293 stl_raw(addr, val);
2294 break;
2295 case 8:
2296 default:
2297 stq_raw(addr, val);
2298 break;
2299 }
2300 }
2301 break;
2302 case 0x81: // Secondary
2303 case 0x89: // Secondary LE
2304 // XXX
2305 return;
2306
2307 case 0x82: // Primary no-fault, RO
2308 case 0x83: // Secondary no-fault, RO
2309 case 0x8a: // Primary no-fault LE, RO
2310 case 0x8b: // Secondary no-fault LE, RO
2311 default:
2312 do_unassigned_access(addr, 1, 0, 1, size);
2313 return;
2314 }
2315 }
2316
2317 #else /* CONFIG_USER_ONLY */
2318
2319 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
2320 {
2321 uint64_t ret = 0;
2322 #if defined(DEBUG_ASI)
2323 target_ulong last_addr = addr;
2324 #endif
2325
2326 asi &= 0xff;
2327
2328 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2329 || ((env->def->features & CPU_FEATURE_HYPV)
2330 && asi >= 0x30 && asi < 0x80
2331 && !(env->hpstate & HS_PRIV)))
2332 raise_exception(TT_PRIV_ACT);
2333
2334 helper_check_align(addr, size - 1);
2335 switch (asi) {
2336 case 0x82: // Primary no-fault
2337 case 0x8a: // Primary no-fault LE
2338 case 0x83: // Secondary no-fault
2339 case 0x8b: // Secondary no-fault LE
2340 {
2341 /* secondary space access has lowest asi bit equal to 1 */
2342 int access_mmu_idx = ( asi & 1 ) ? MMU_KERNEL_IDX
2343 : MMU_KERNEL_SECONDARY_IDX;
2344
2345 if (cpu_get_phys_page_nofault(env, addr, access_mmu_idx) == -1ULL) {
2346 #ifdef DEBUG_ASI
2347 dump_asi("read ", last_addr, asi, size, ret);
2348 #endif
2349 return 0;
2350 }
2351 }
2352 // Fall through
2353 case 0x10: // As if user primary
2354 case 0x11: // As if user secondary
2355 case 0x18: // As if user primary LE
2356 case 0x19: // As if user secondary LE
2357 case 0x80: // Primary
2358 case 0x81: // Secondary
2359 case 0x88: // Primary LE
2360 case 0x89: // Secondary LE
2361 case 0xe2: // UA2007 Primary block init
2362 case 0xe3: // UA2007 Secondary block init
2363 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
2364 if ((env->def->features & CPU_FEATURE_HYPV)
2365 && env->hpstate & HS_PRIV) {
2366 switch(size) {
2367 case 1:
2368 ret = ldub_hypv(addr);
2369 break;
2370 case 2:
2371 ret = lduw_hypv(addr);
2372 break;
2373 case 4:
2374 ret = ldl_hypv(addr);
2375 break;
2376 default:
2377 case 8:
2378 ret = ldq_hypv(addr);
2379 break;
2380 }
2381 } else {
2382 /* secondary space access has lowest asi bit equal to 1 */
2383 if (asi & 1) {
2384 switch(size) {
2385 case 1:
2386 ret = ldub_kernel_secondary(addr);
2387 break;
2388 case 2:
2389 ret = lduw_kernel_secondary(addr);
2390 break;
2391 case 4:
2392 ret = ldl_kernel_secondary(addr);
2393 break;
2394 default:
2395 case 8:
2396 ret = ldq_kernel_secondary(addr);
2397 break;
2398 }
2399 } else {
2400 switch(size) {
2401 case 1:
2402 ret = ldub_kernel(addr);
2403 break;
2404 case 2:
2405 ret = lduw_kernel(addr);
2406 break;
2407 case 4:
2408 ret = ldl_kernel(addr);
2409 break;
2410 default:
2411 case 8:
2412 ret = ldq_kernel(addr);
2413 break;
2414 }
2415 }
2416 }
2417 } else {
2418 /* secondary space access has lowest asi bit equal to 1 */
2419 if (asi & 1) {
2420 switch(size) {
2421 case 1:
2422 ret = ldub_user_secondary(addr);
2423 break;
2424 case 2:
2425 ret = lduw_user_secondary(addr);
2426 break;
2427 case 4:
2428 ret = ldl_user_secondary(addr);
2429 break;
2430 default:
2431 case 8:
2432 ret = ldq_user_secondary(addr);
2433 break;
2434 }
2435 } else {
2436 switch(size) {
2437 case 1:
2438 ret = ldub_user(addr);
2439 break;
2440 case 2:
2441 ret = lduw_user(addr);
2442 break;
2443 case 4:
2444 ret = ldl_user(addr);
2445 break;
2446 default:
2447 case 8:
2448 ret = ldq_user(addr);
2449 break;
2450 }
2451 }
2452 }
2453 break;
2454 case 0x14: // Bypass
2455 case 0x15: // Bypass, non-cacheable
2456 case 0x1c: // Bypass LE
2457 case 0x1d: // Bypass, non-cacheable LE
2458 {
2459 switch(size) {
2460 case 1:
2461 ret = ldub_phys(addr);
2462 break;
2463 case 2:
2464 ret = lduw_phys(addr);
2465 break;
2466 case 4:
2467 ret = ldl_phys(addr);
2468 break;
2469 default:
2470 case 8:
2471 ret = ldq_phys(addr);
2472 break;
2473 }
2474 break;
2475 }
2476 case 0x24: // Nucleus quad LDD 128 bit atomic
2477 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2478 // Only ldda allowed
2479 raise_exception(TT_ILL_INSN);
2480 return 0;
2481 case 0x04: // Nucleus
2482 case 0x0c: // Nucleus Little Endian (LE)
2483 {
2484 switch(size) {
2485 case 1:
2486 ret = ldub_nucleus(addr);
2487 break;
2488 case 2:
2489 ret = lduw_nucleus(addr);
2490 break;
2491 case 4:
2492 ret = ldl_nucleus(addr);
2493 break;
2494 default:
2495 case 8:
2496 ret = ldq_nucleus(addr);
2497 break;
2498 }
2499 break;
2500 }
2501 case 0x4a: // UPA config
2502 // XXX
2503 break;
2504 case 0x45: // LSU
2505 ret = env->lsu;
2506 break;
2507 case 0x50: // I-MMU regs
2508 {
2509 int reg = (addr >> 3) & 0xf;
2510
2511 if (reg == 0) {
2512 // I-TSB Tag Target register
2513 ret = ultrasparc_tag_target(env->immu.tag_access);
2514 } else {
2515 ret = env->immuregs[reg];
2516 }
2517
2518 break;
2519 }
2520 case 0x51: // I-MMU 8k TSB pointer
2521 {
2522 // env->immuregs[5] holds I-MMU TSB register value
2523 // env->immuregs[6] holds I-MMU Tag Access register value
2524 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
2525 8*1024);
2526 break;
2527 }
2528 case 0x52: // I-MMU 64k TSB pointer
2529 {
2530 // env->immuregs[5] holds I-MMU TSB register value
2531 // env->immuregs[6] holds I-MMU Tag Access register value
2532 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
2533 64*1024);
2534 break;
2535 }
2536 case 0x55: // I-MMU data access
2537 {
2538 int reg = (addr >> 3) & 0x3f;
2539
2540 ret = env->itlb[reg].tte;
2541 break;
2542 }
2543 case 0x56: // I-MMU tag read
2544 {
2545 int reg = (addr >> 3) & 0x3f;
2546
2547 ret = env->itlb[reg].tag;
2548 break;
2549 }
2550 case 0x58: // D-MMU regs
2551 {
2552 int reg = (addr >> 3) & 0xf;
2553
2554 if (reg == 0) {
2555 // D-TSB Tag Target register
2556 ret = ultrasparc_tag_target(env->dmmu.tag_access);
2557 } else {
2558 ret = env->dmmuregs[reg];
2559 }
2560 break;
2561 }
2562 case 0x59: // D-MMU 8k TSB pointer
2563 {
2564 // env->dmmuregs[5] holds D-MMU TSB register value
2565 // env->dmmuregs[6] holds D-MMU Tag Access register value
2566 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
2567 8*1024);
2568 break;
2569 }
2570 case 0x5a: // D-MMU 64k TSB pointer
2571 {
2572 // env->dmmuregs[5] holds D-MMU TSB register value
2573 // env->dmmuregs[6] holds D-MMU Tag Access register value
2574 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
2575 64*1024);
2576 break;
2577 }
2578 case 0x5d: // D-MMU data access
2579 {
2580 int reg = (addr >> 3) & 0x3f;
2581
2582 ret = env->dtlb[reg].tte;
2583 break;
2584 }
2585 case 0x5e: // D-MMU tag read
2586 {
2587 int reg = (addr >> 3) & 0x3f;
2588
2589 ret = env->dtlb[reg].tag;
2590 break;
2591 }
2592 case 0x46: // D-cache data
2593 case 0x47: // D-cache tag access
2594 case 0x4b: // E-cache error enable
2595 case 0x4c: // E-cache asynchronous fault status
2596 case 0x4d: // E-cache asynchronous fault address
2597 case 0x4e: // E-cache tag data
2598 case 0x66: // I-cache instruction access
2599 case 0x67: // I-cache tag access
2600 case 0x6e: // I-cache predecode
2601 case 0x6f: // I-cache LRU etc.
2602 case 0x76: // E-cache tag
2603 case 0x7e: // E-cache tag
2604 break;
2605 case 0x5b: // D-MMU data pointer
2606 case 0x48: // Interrupt dispatch, RO
2607 case 0x49: // Interrupt data receive
2608 case 0x7f: // Incoming interrupt vector, RO
2609 // XXX
2610 break;
2611 case 0x54: // I-MMU data in, WO
2612 case 0x57: // I-MMU demap, WO
2613 case 0x5c: // D-MMU data in, WO
2614 case 0x5f: // D-MMU demap, WO
2615 case 0x77: // Interrupt vector, WO
2616 default:
2617 do_unassigned_access(addr, 0, 0, 1, size);
2618 ret = 0;
2619 break;
2620 }
2621
2622 /* Convert from little endian */
2623 switch (asi) {
2624 case 0x0c: // Nucleus Little Endian (LE)
2625 case 0x18: // As if user primary LE
2626 case 0x19: // As if user secondary LE
2627 case 0x1c: // Bypass LE
2628 case 0x1d: // Bypass, non-cacheable LE
2629 case 0x88: // Primary LE
2630 case 0x89: // Secondary LE
2631 case 0x8a: // Primary no-fault LE
2632 case 0x8b: // Secondary no-fault LE
2633 switch(size) {
2634 case 2:
2635 ret = bswap16(ret);
2636 break;
2637 case 4:
2638 ret = bswap32(ret);
2639 break;
2640 case 8:
2641 ret = bswap64(ret);
2642 break;
2643 default:
2644 break;
2645 }
2646 default:
2647 break;
2648 }
2649
2650 /* Convert to signed number */
2651 if (sign) {
2652 switch(size) {
2653 case 1:
2654 ret = (int8_t) ret;
2655 break;
2656 case 2:
2657 ret = (int16_t) ret;
2658 break;
2659 case 4:
2660 ret = (int32_t) ret;
2661 break;
2662 default:
2663 break;
2664 }
2665 }
2666 #ifdef DEBUG_ASI
2667 dump_asi("read ", last_addr, asi, size, ret);
2668 #endif
2669 return ret;
2670 }
2671
2672 void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
2673 {
2674 #ifdef DEBUG_ASI
2675 dump_asi("write", addr, asi, size, val);
2676 #endif
2677
2678 asi &= 0xff;
2679
2680 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2681 || ((env->def->features & CPU_FEATURE_HYPV)
2682 && asi >= 0x30 && asi < 0x80
2683 && !(env->hpstate & HS_PRIV)))
2684 raise_exception(TT_PRIV_ACT);
2685
2686 helper_check_align(addr, size - 1);
2687 /* Convert to little endian */
2688 switch (asi) {
2689 case 0x0c: // Nucleus Little Endian (LE)
2690 case 0x18: // As if user primary LE
2691 case 0x19: // As if user secondary LE
2692 case 0x1c: // Bypass LE
2693 case 0x1d: // Bypass, non-cacheable LE
2694 case 0x88: // Primary LE
2695 case 0x89: // Secondary LE
2696 switch(size) {
2697 case 2:
2698 val = bswap16(val);
2699 break;
2700 case 4:
2701 val = bswap32(val);
2702 break;
2703 case 8:
2704 val = bswap64(val);
2705 break;
2706 default:
2707 break;
2708 }
2709 default:
2710 break;
2711 }
2712
2713 switch(asi) {
2714 case 0x10: // As if user primary
2715 case 0x11: // As if user secondary
2716 case 0x18: // As if user primary LE
2717 case 0x19: // As if user secondary LE
2718 case 0x80: // Primary
2719 case 0x81: // Secondary
2720 case 0x88: // Primary LE
2721 case 0x89: // Secondary LE
2722 case 0xe2: // UA2007 Primary block init
2723 case 0xe3: // UA2007 Secondary block init
2724 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
2725 if ((env->def->features & CPU_FEATURE_HYPV)
2726 && env->hpstate & HS_PRIV) {
2727 switch(size) {
2728 case 1:
2729 stb_hypv(addr, val);
2730 break;
2731 case 2:
2732 stw_hypv(addr, val);
2733 break;
2734 case 4:
2735 stl_hypv(addr, val);
2736 break;
2737 case 8:
2738 default:
2739 stq_hypv(addr, val);
2740 break;
2741 }
2742 } else {
2743 /* secondary space access has lowest asi bit equal to 1 */
2744 if (asi & 1) {
2745 switch(size) {
2746 case 1:
2747 stb_kernel_secondary(addr, val);
2748 break;
2749 case 2:
2750 stw_kernel_secondary(addr, val);
2751 break;
2752 case 4:
2753 stl_kernel_secondary(addr, val);
2754 break;
2755 case 8:
2756 default:
2757 stq_kernel_secondary(addr, val);
2758 break;
2759 }
2760 } else {
2761 switch(size) {
2762 case 1:
2763 stb_kernel(addr, val);
2764 break;
2765 case 2:
2766 stw_kernel(addr, val);
2767 break;
2768 case 4:
2769 stl_kernel(addr, val);
2770 break;
2771 case 8:
2772 default:
2773 stq_kernel(addr, val);
2774 break;
2775 }
2776 }
2777 }
2778 } else {
2779 /* secondary space access has lowest asi bit equal to 1 */
2780 if (asi & 1) {
2781 switch(size) {
2782 case 1:
2783 stb_user_secondary(addr, val);
2784 break;
2785 case 2:
2786 stw_user_secondary(addr, val);
2787 break;
2788 case 4:
2789 stl_user_secondary(addr, val);
2790 break;
2791 case 8:
2792 default:
2793 stq_user_secondary(addr, val);
2794 break;
2795 }
2796 } else {
2797 switch(size) {
2798 case 1:
2799 stb_user(addr, val);
2800 break;
2801 case 2:
2802 stw_user(addr, val);
2803 break;
2804 case 4:
2805 stl_user(addr, val);
2806 break;
2807 case 8:
2808 default:
2809 stq_user(addr, val);
2810 break;
2811 }
2812 }
2813 }
2814 break;
2815 case 0x14: // Bypass
2816 case 0x15: // Bypass, non-cacheable
2817 case 0x1c: // Bypass LE
2818 case 0x1d: // Bypass, non-cacheable LE
2819 {
2820 switch(size) {
2821 case 1:
2822 stb_phys(addr, val);
2823 break;
2824 case 2:
2825 stw_phys(addr, val);
2826 break;
2827 case 4:
2828 stl_phys(addr, val);
2829 break;
2830 case 8:
2831 default:
2832 stq_phys(addr, val);
2833 break;
2834 }
2835 }
2836 return;
2837 case 0x24: // Nucleus quad LDD 128 bit atomic
2838 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2839 // Only ldda allowed
2840 raise_exception(TT_ILL_INSN);
2841 return;
2842 case 0x04: // Nucleus
2843 case 0x0c: // Nucleus Little Endian (LE)
2844 {
2845 switch(size) {
2846 case 1:
2847 stb_nucleus(addr, val);
2848 break;
2849 case 2:
2850 stw_nucleus(addr, val);
2851 break;
2852 case 4:
2853 stl_nucleus(addr, val);
2854 break;
2855 default:
2856 case 8:
2857 stq_nucleus(addr, val);
2858 break;
2859 }
2860 break;
2861 }
2862
2863 case 0x4a: // UPA config
2864 // XXX
2865 return;
2866 case 0x45: // LSU
2867 {
2868 uint64_t oldreg;
2869
2870 oldreg = env->lsu;
2871 env->lsu = val & (DMMU_E | IMMU_E);
2872 // Mappings generated during D/I MMU disabled mode are
2873 // invalid in normal mode
2874 if (oldreg != env->lsu) {
2875 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
2876 oldreg, env->lsu);
2877 #ifdef DEBUG_MMU
2878 dump_mmu(env);
2879 #endif
2880 tlb_flush(env, 1);
2881 }
2882 return;
2883 }
2884 case 0x50: // I-MMU regs
2885 {
2886 int reg = (addr >> 3) & 0xf;
2887 uint64_t oldreg;
2888
2889 oldreg = env->immuregs[reg];
2890 switch(reg) {
2891 case 0: // RO
2892 return;
2893 case 1: // Not in I-MMU
2894 case 2:
2895 return;
2896 case 3: // SFSR
2897 if ((val & 1) == 0)
2898 val = 0; // Clear SFSR
2899 env->immu.sfsr = val;
2900 break;
2901 case 4: // RO
2902 return;
2903 case 5: // TSB access
2904 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
2905 PRIx64 "\n", env->immu.tsb, val);
2906 env->immu.tsb = val;
2907 break;
2908 case 6: // Tag access
2909 env->immu.tag_access = val;
2910 break;
2911 case 7:
2912 case 8:
2913 return;
2914 default:
2915 break;
2916 }
2917
2918 if (oldreg != env->immuregs[reg]) {
2919 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
2920 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
2921 }
2922 #ifdef DEBUG_MMU
2923 dump_mmu(env);
2924 #endif
2925 return;
2926 }
2927 case 0x54: // I-MMU data in
2928 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
2929 return;
2930 case 0x55: // I-MMU data access
2931 {
2932 // TODO: auto demap
2933
2934 unsigned int i = (addr >> 3) & 0x3f;
2935
2936 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env);
2937
2938 #ifdef DEBUG_MMU
2939 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
2940 dump_mmu(env);
2941 #endif
2942 return;
2943 }
2944 case 0x57: // I-MMU demap
2945 demap_tlb(env->itlb, addr, "immu", env);
2946 return;
2947 case 0x58: // D-MMU regs
2948 {
2949 int reg = (addr >> 3) & 0xf;
2950 uint64_t oldreg;
2951
2952 oldreg = env->dmmuregs[reg];
2953 switch(reg) {
2954 case 0: // RO
2955 case 4:
2956 return;
2957 case 3: // SFSR
2958 if ((val & 1) == 0) {
2959 val = 0; // Clear SFSR, Fault address
2960 env->dmmu.sfar = 0;
2961 }
2962 env->dmmu.sfsr = val;
2963 break;
2964 case 1: // Primary context
2965 env->dmmu.mmu_primary_context = val;
2966 break;
2967 case 2: // Secondary context
2968 env->dmmu.mmu_secondary_context = val;
2969 break;
2970 case 5: // TSB access
2971 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
2972 PRIx64 "\n", env->dmmu.tsb, val);
2973 env->dmmu.tsb = val;
2974 break;
2975 case 6: // Tag access
2976 env->dmmu.tag_access = val;
2977 break;
2978 case 7: // Virtual Watchpoint
2979 case 8: // Physical Watchpoint
2980 default:
2981 env->dmmuregs[reg] = val;
2982 break;
2983 }
2984
2985 if (oldreg != env->dmmuregs[reg]) {
2986 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
2987 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
2988 }
2989 #ifdef DEBUG_MMU
2990 dump_mmu(env);
2991 #endif
2992 return;
2993 }
2994 case 0x5c: // D-MMU data in
2995 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
2996 return;
2997 case 0x5d: // D-MMU data access
2998 {
2999 unsigned int i = (addr >> 3) & 0x3f;
3000
3001 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env);
3002
3003 #ifdef DEBUG_MMU
3004 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
3005 dump_mmu(env);
3006 #endif
3007 return;
3008 }
3009 case 0x5f: // D-MMU demap
3010 demap_tlb(env->dtlb, addr, "dmmu", env);
3011 return;
3012 case 0x49: // Interrupt data receive
3013 // XXX
3014 return;
3015 case 0x46: // D-cache data
3016 case 0x47: // D-cache tag access
3017 case 0x4b: // E-cache error enable
3018 case 0x4c: // E-cache asynchronous fault status
3019 case 0x4d: // E-cache asynchronous fault address
3020 case 0x4e: // E-cache tag data
3021 case 0x66: // I-cache instruction access
3022 case 0x67: // I-cache tag access
3023 case 0x6e: // I-cache predecode
3024 case 0x6f: // I-cache LRU etc.
3025 case 0x76: // E-cache tag
3026 case 0x7e: // E-cache tag
3027 return;
3028 case 0x51: // I-MMU 8k TSB pointer, RO
3029 case 0x52: // I-MMU 64k TSB pointer, RO
3030 case 0x56: // I-MMU tag read, RO
3031 case 0x59: // D-MMU 8k TSB pointer, RO
3032 case 0x5a: // D-MMU 64k TSB pointer, RO
3033 case 0x5b: // D-MMU data pointer, RO
3034 case 0x5e: // D-MMU tag read, RO
3035 case 0x48: // Interrupt dispatch, RO
3036 case 0x7f: // Incoming interrupt vector, RO
3037 case 0x82: // Primary no-fault, RO
3038 case 0x83: // Secondary no-fault, RO
3039 case 0x8a: // Primary no-fault LE, RO
3040 case 0x8b: // Secondary no-fault LE, RO
3041 default:
3042 do_unassigned_access(addr, 1, 0, 1, size);
3043 return;
3044 }
3045 }
3046 #endif /* CONFIG_USER_ONLY */
3047
3048 void helper_ldda_asi(target_ulong addr, int asi, int rd)
3049 {
3050 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
3051 || ((env->def->features & CPU_FEATURE_HYPV)
3052 && asi >= 0x30 && asi < 0x80
3053 && !(env->hpstate & HS_PRIV)))
3054 raise_exception(TT_PRIV_ACT);
3055
3056 switch (asi) {
3057 case 0x24: // Nucleus quad LDD 128 bit atomic
3058 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
3059 helper_check_align(addr, 0xf);
3060 if (rd == 0) {
3061 env->gregs[1] = ldq_kernel(addr + 8);
3062 if (asi == 0x2c)
3063 bswap64s(&env->gregs[1]);
3064 } else if (rd < 8) {
3065 env->gregs[rd] = ldq_kernel(addr);
3066 env->gregs[rd + 1] = ldq_kernel(addr + 8);
3067 if (asi == 0x2c) {
3068 bswap64s(&env->gregs[rd]);
3069 bswap64s(&env->gregs[rd + 1]);
3070 }
3071 } else {
3072 env->regwptr[rd] = ldq_kernel(addr);
3073 env->regwptr[rd + 1] = ldq_kernel(addr + 8);
3074 if (asi == 0x2c) {
3075 bswap64s(&env->regwptr[rd]);
3076 bswap64s(&env->regwptr[rd + 1]);
3077 }
3078 }
3079 break;
3080 default:
3081 helper_check_align(addr, 0x3);
3082 if (rd == 0)
3083 env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0);
3084 else if (rd < 8) {
3085 env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0);
3086 env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
3087 } else {
3088 env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0);
3089 env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
3090 }
3091 break;
3092 }
3093 }
3094
3095 void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
3096 {
3097 unsigned int i;
3098 target_ulong val;
3099
3100 helper_check_align(addr, 3);
3101 switch (asi) {
3102 case 0xf0: // Block load primary
3103 case 0xf1: // Block load secondary
3104 case 0xf8: // Block load primary LE
3105 case 0xf9: // Block load secondary LE
3106 if (rd & 7) {
3107 raise_exception(TT_ILL_INSN);
3108 return;
3109 }
3110 helper_check_align(addr, 0x3f);
3111 for (i = 0; i < 16; i++) {
3112 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4,
3113 0);
3114 addr += 4;
3115 }
3116
3117 return;
3118 default:
3119 break;
3120 }
3121
3122 val = helper_ld_asi(addr, asi, size, 0);
3123 switch(size) {
3124 default:
3125 case 4:
3126 *((uint32_t *)&env->fpr[rd]) = val;
3127 break;
3128 case 8:
3129 *((int64_t *)&DT0) = val;
3130 break;
3131 case 16:
3132 // XXX
3133 break;
3134 }
3135 }
3136
3137 void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
3138 {
3139 unsigned int i;
3140 target_ulong val = 0;
3141
3142 helper_check_align(addr, 3);
3143 switch (asi) {
3144 case 0xe0: // UA2007 Block commit store primary (cache flush)
3145 case 0xe1: // UA2007 Block commit store secondary (cache flush)
3146 case 0xf0: // Block store primary
3147 case 0xf1: // Block store secondary
3148 case 0xf8: // Block store primary LE
3149 case 0xf9: // Block store secondary LE
3150 if (rd & 7) {
3151 raise_exception(TT_ILL_INSN);
3152 return;
3153 }
3154 helper_check_align(addr, 0x3f);
3155 for (i = 0; i < 16; i++) {
3156 val = *(uint32_t *)&env->fpr[rd++];
3157 helper_st_asi(addr, val, asi & 0x8f, 4);
3158 addr += 4;
3159 }
3160
3161 return;
3162 default:
3163 break;
3164 }
3165
3166 switch(size) {
3167 default:
3168 case 4:
3169 val = *((uint32_t *)&env->fpr[rd]);
3170 break;
3171 case 8:
3172 val = *((int64_t *)&DT0);
3173 break;
3174 case 16:
3175 // XXX
3176 break;
3177 }
3178 helper_st_asi(addr, val, asi, size);
3179 }
3180
3181 target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
3182 target_ulong val2, uint32_t asi)
3183 {
3184 target_ulong ret;
3185
3186 val2 &= 0xffffffffUL;
3187 ret = helper_ld_asi(addr, asi, 4, 0);
3188 ret &= 0xffffffffUL;
3189 if (val2 == ret)
3190 helper_st_asi(addr, val1 & 0xffffffffUL, asi, 4);
3191 return ret;
3192 }
3193
3194 target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
3195 target_ulong val2, uint32_t asi)
3196 {
3197 target_ulong ret;
3198
3199 ret = helper_ld_asi(addr, asi, 8, 0);
3200 if (val2 == ret)
3201 helper_st_asi(addr, val1, asi, 8);
3202 return ret;
3203 }
3204 #endif /* TARGET_SPARC64 */
3205
3206 #ifndef TARGET_SPARC64
3207 void helper_rett(void)
3208 {
3209 unsigned int cwp;
3210
3211 if (env->psret == 1)
3212 raise_exception(TT_ILL_INSN);
3213
3214 env->psret = 1;
3215 cwp = cwp_inc(env->cwp + 1) ;
3216 if (env->wim & (1 << cwp)) {
3217 raise_exception(TT_WIN_UNF);
3218 }
3219 set_cwp(cwp);
3220 env->psrs = env->psrps;
3221 }
3222 #endif
3223
3224 target_ulong helper_udiv(target_ulong a, target_ulong b)
3225 {
3226 uint64_t x0;
3227 uint32_t x1;
3228
3229 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
3230 x1 = b;
3231
3232 if (x1 == 0) {
3233 raise_exception(TT_DIV_ZERO);
3234 }
3235
3236 x0 = x0 / x1;
3237 if (x0 > 0xffffffff) {
3238 env->cc_src2 = 1;
3239 return 0xffffffff;
3240 } else {
3241 env->cc_src2 = 0;
3242 return x0;
3243 }
3244 }
3245
3246 target_ulong helper_sdiv(target_ulong a, target_ulong b)
3247 {
3248 int64_t x0;
3249 int32_t x1;
3250
3251 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
3252 x1 = b;
3253
3254 if (x1 == 0) {
3255 raise_exception(TT_DIV_ZERO);
3256 }
3257
3258 x0 = x0 / x1;
3259 if ((int32_t) x0 != x0) {
3260 env->cc_src2 = 1;
3261 return x0 < 0? 0x80000000: 0x7fffffff;
3262 } else {
3263 env->cc_src2 = 0;
3264 return x0;
3265 }
3266 }
3267
3268 void helper_stdf(target_ulong addr, int mem_idx)
3269 {
3270 helper_check_align(addr, 7);
3271 #if !defined(CONFIG_USER_ONLY)
3272 switch (mem_idx) {
3273 case 0:
3274 stfq_user(addr, DT0);
3275 break;
3276 case 1:
3277 stfq_kernel(addr, DT0);
3278 break;
3279 #ifdef TARGET_SPARC64
3280 case 2:
3281 stfq_hypv(addr, DT0);
3282 break;
3283 #endif
3284 default:
3285 break;
3286 }
3287 #else
3288 stfq_raw(address_mask(env, addr), DT0);
3289 #endif
3290 }
3291
3292 void helper_lddf(target_ulong addr, int mem_idx)
3293 {
3294 helper_check_align(addr, 7);
3295 #if !defined(CONFIG_USER_ONLY)
3296 switch (mem_idx) {
3297 case 0:
3298 DT0 = ldfq_user(addr);
3299 break;
3300 case 1:
3301 DT0 = ldfq_kernel(addr);
3302 break;
3303 #ifdef TARGET_SPARC64
3304 case 2:
3305 DT0 = ldfq_hypv(addr);
3306 break;
3307 #endif
3308 default:
3309 break;
3310 }
3311 #else
3312 DT0 = ldfq_raw(address_mask(env, addr));
3313 #endif
3314 }
3315
3316 void helper_ldqf(target_ulong addr, int mem_idx)
3317 {
3318 // XXX add 128 bit load
3319 CPU_QuadU u;
3320
3321 helper_check_align(addr, 7);
3322 #if !defined(CONFIG_USER_ONLY)
3323 switch (mem_idx) {
3324 case 0:
3325 u.ll.upper = ldq_user(addr);
3326 u.ll.lower = ldq_user(addr + 8);
3327 QT0 = u.q;
3328 break;
3329 case 1:
3330 u.ll.upper = ldq_kernel(addr);
3331 u.ll.lower = ldq_kernel(addr + 8);
3332 QT0 = u.q;
3333 break;
3334 #ifdef TARGET_SPARC64
3335 case 2:
3336 u.ll.upper = ldq_hypv(addr);
3337 u.ll.lower = ldq_hypv(addr + 8);
3338 QT0 = u.q;
3339 break;
3340 #endif
3341 default:
3342 break;
3343 }
3344 #else
3345 u.ll.upper = ldq_raw(address_mask(env, addr));
3346 u.ll.lower = ldq_raw(address_mask(env, addr + 8));
3347 QT0 = u.q;
3348 #endif
3349 }
3350
3351 void helper_stqf(target_ulong addr, int mem_idx)
3352 {
3353 // XXX add 128 bit store
3354 CPU_QuadU u;
3355
3356 helper_check_align(addr, 7);
3357 #if !defined(CONFIG_USER_ONLY)
3358 switch (mem_idx) {
3359 case 0:
3360 u.q = QT0;
3361 stq_user(addr, u.ll.upper);
3362 stq_user(addr + 8, u.ll.lower);
3363 break;
3364 case 1:
3365 u.q = QT0;
3366 stq_kernel(addr, u.ll.upper);
3367 stq_kernel(addr + 8, u.ll.lower);
3368 break;
3369 #ifdef TARGET_SPARC64
3370 case 2:
3371 u.q = QT0;
3372 stq_hypv(addr, u.ll.upper);
3373 stq_hypv(addr + 8, u.ll.lower);
3374 break;
3375 #endif
3376 default:
3377 break;
3378 }
3379 #else
3380 u.q = QT0;
3381 stq_raw(address_mask(env, addr), u.ll.upper);
3382 stq_raw(address_mask(env, addr + 8), u.ll.lower);
3383 #endif
3384 }
3385
3386 static inline void set_fsr(void)
3387 {
3388 int rnd_mode;
3389
3390 switch (env->fsr & FSR_RD_MASK) {
3391 case FSR_RD_NEAREST:
3392 rnd_mode = float_round_nearest_even;
3393 break;
3394 default:
3395 case FSR_RD_ZERO:
3396 rnd_mode = float_round_to_zero;
3397 break;
3398 case FSR_RD_POS:
3399 rnd_mode = float_round_up;
3400 break;
3401 case FSR_RD_NEG:
3402 rnd_mode = float_round_down;
3403 break;
3404 }
3405 set_float_rounding_mode(rnd_mode, &env->fp_status);
3406 }
3407
3408 void helper_ldfsr(uint32_t new_fsr)
3409 {
3410 env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK);
3411 set_fsr();
3412 }
3413
3414 #ifdef TARGET_SPARC64
3415 void helper_ldxfsr(uint64_t new_fsr)
3416 {
3417 env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK);
3418 set_fsr();
3419 }
3420 #endif
3421
3422 void helper_debug(void)
3423 {
3424 env->exception_index = EXCP_DEBUG;
3425 cpu_loop_exit();
3426 }
3427
3428 #ifndef TARGET_SPARC64
3429 /* XXX: use another pointer for %iN registers to avoid slow wrapping
3430 handling ? */
3431 void helper_save(void)
3432 {
3433 uint32_t cwp;
3434
3435 cwp = cwp_dec(env->cwp - 1);
3436 if (env->wim & (1 << cwp)) {
3437 raise_exception(TT_WIN_OVF);
3438 }
3439 set_cwp(cwp);
3440 }
3441
3442 void helper_restore(void)
3443 {
3444 uint32_t cwp;
3445
3446 cwp = cwp_inc(env->cwp + 1);
3447 if (env->wim & (1 << cwp)) {
3448 raise_exception(TT_WIN_UNF);
3449 }
3450 set_cwp(cwp);
3451 }
3452
3453 void helper_wrpsr(target_ulong new_psr)
3454 {
3455 if ((new_psr & PSR_CWP) >= env->nwindows) {
3456 raise_exception(TT_ILL_INSN);
3457 } else {
3458 cpu_put_psr(env, new_psr);
3459 }
3460 }
3461
3462 target_ulong helper_rdpsr(void)
3463 {
3464 return get_psr();
3465 }
3466
3467 #else
3468 /* XXX: use another pointer for %iN registers to avoid slow wrapping
3469 handling ? */
3470 void helper_save(void)
3471 {
3472 uint32_t cwp;
3473
3474 cwp = cwp_dec(env->cwp - 1);
3475 if (env->cansave == 0) {
3476 raise_exception(TT_SPILL | (env->otherwin != 0 ?
3477 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
3478 ((env->wstate & 0x7) << 2)));
3479 } else {
3480 if (env->cleanwin - env->canrestore == 0) {
3481 // XXX Clean windows without trap
3482 raise_exception(TT_CLRWIN);
3483 } else {
3484 env->cansave--;
3485 env->canrestore++;
3486 set_cwp(cwp);
3487 }
3488 }
3489 }
3490
3491 void helper_restore(void)
3492 {
3493 uint32_t cwp;
3494
3495 cwp = cwp_inc(env->cwp + 1);
3496 if (env->canrestore == 0) {
3497 raise_exception(TT_FILL | (env->otherwin != 0 ?
3498 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
3499 ((env->wstate & 0x7) << 2)));
3500 } else {
3501 env->cansave++;
3502 env->canrestore--;
3503 set_cwp(cwp);
3504 }
3505 }
3506
3507 void helper_flushw(void)
3508 {
3509 if (env->cansave != env->nwindows - 2) {
3510 raise_exception(TT_SPILL | (env->otherwin != 0 ?
3511 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
3512 ((env->wstate & 0x7) << 2)));
3513 }
3514 }
3515
3516 void helper_saved(void)
3517 {
3518 env->cansave++;
3519 if (env->otherwin == 0)
3520 env->canrestore--;
3521 else
3522 env->otherwin--;
3523 }
3524
3525 void helper_restored(void)
3526 {
3527 env->canrestore++;
3528 if (env->cleanwin < env->nwindows - 1)
3529 env->cleanwin++;
3530 if (env->otherwin == 0)
3531 env->cansave--;
3532 else
3533 env->otherwin--;
3534 }
3535
3536 static target_ulong get_ccr(void)
3537 {
3538 target_ulong psr;
3539
3540 psr = get_psr();
3541
3542 return ((env->xcc >> 20) << 4) | ((psr & PSR_ICC) >> 20);
3543 }
3544
3545 target_ulong cpu_get_ccr(CPUState *env1)
3546 {
3547 CPUState *saved_env;
3548 target_ulong ret;
3549
3550 saved_env = env;
3551 env = env1;
3552 ret = get_ccr();
3553 env = saved_env;
3554 return ret;
3555 }
3556
3557 static void put_ccr(target_ulong val)
3558 {
3559 target_ulong tmp = val;
3560
3561 env->xcc = (tmp >> 4) << 20;
3562 env->psr = (tmp & 0xf) << 20;
3563 CC_OP = CC_OP_FLAGS;
3564 }
3565
3566 void cpu_put_ccr(CPUState *env1, target_ulong val)
3567 {
3568 CPUState *saved_env;
3569
3570 saved_env = env;
3571 env = env1;
3572 put_ccr(val);
3573 env = saved_env;
3574 }
3575
3576 static target_ulong get_cwp64(void)
3577 {
3578 return env->nwindows - 1 - env->cwp;
3579 }
3580
3581 target_ulong cpu_get_cwp64(CPUState *env1)
3582 {
3583 CPUState *saved_env;
3584 target_ulong ret;
3585
3586 saved_env = env;
3587 env = env1;
3588 ret = get_cwp64();
3589 env = saved_env;
3590 return ret;
3591 }
3592
3593 static void put_cwp64(int cwp)
3594 {
3595 if (unlikely(cwp >= env->nwindows || cwp < 0)) {
3596 cwp %= env->nwindows;
3597 }
3598 set_cwp(env->nwindows - 1 - cwp);
3599 }
3600
3601 void cpu_put_cwp64(CPUState *env1, int cwp)
3602 {
3603 CPUState *saved_env;
3604
3605 saved_env = env;
3606 env = env1;
3607 put_cwp64(cwp);
3608 env = saved_env;
3609 }
3610
3611 target_ulong helper_rdccr(void)
3612 {
3613 return get_ccr();
3614 }
3615
3616 void helper_wrccr(target_ulong new_ccr)
3617 {
3618 put_ccr(new_ccr);
3619 }
3620
3621 // CWP handling is reversed in V9, but we still use the V8 register
3622 // order.
3623 target_ulong helper_rdcwp(void)
3624 {
3625 return get_cwp64();
3626 }
3627
3628 void helper_wrcwp(target_ulong new_cwp)
3629 {
3630 put_cwp64(new_cwp);
3631 }
3632
3633 // This function uses non-native bit order
3634 #define GET_FIELD(X, FROM, TO) \
3635 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
3636
3637 // This function uses the order in the manuals, i.e. bit 0 is 2^0
3638 #define GET_FIELD_SP(X, FROM, TO) \
3639 GET_FIELD(X, 63 - (TO), 63 - (FROM))
3640
3641 target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
3642 {
3643 return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
3644 (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
3645 (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
3646 (GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
3647 (GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
3648 (GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
3649 (((pixel_addr >> 55) & 1) << 4) |
3650 (GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
3651 GET_FIELD_SP(pixel_addr, 11, 12);
3652 }
3653
3654 target_ulong helper_alignaddr(target_ulong addr, target_ulong offset)
3655 {
3656 uint64_t tmp;
3657
3658 tmp = addr + offset;
3659 env->gsr &= ~7ULL;
3660 env->gsr |= tmp & 7ULL;
3661 return tmp & ~7ULL;
3662 }
3663
3664 target_ulong helper_popc(target_ulong val)
3665 {
3666 return ctpop64(val);
3667 }
3668
3669 static inline uint64_t *get_gregset(uint32_t pstate)
3670 {
3671 switch (pstate) {
3672 default:
3673 DPRINTF_PSTATE("ERROR in get_gregset: active pstate bits=%x%s%s%s\n",
3674 pstate,
3675 (pstate & PS_IG) ? " IG" : "",
3676 (pstate & PS_MG) ? " MG" : "",
3677 (pstate & PS_AG) ? " AG" : "");
3678 /* pass through to normal set of global registers */
3679 case 0:
3680 return env->bgregs;
3681 case PS_AG:
3682 return env->agregs;
3683 case PS_MG:
3684 return env->mgregs;
3685 case PS_IG:
3686 return env->igregs;
3687 }
3688 }
3689
3690 static inline void change_pstate(uint32_t new_pstate)
3691 {
3692 uint32_t pstate_regs, new_pstate_regs;
3693 uint64_t *src, *dst;
3694
3695 if (env->def->features & CPU_FEATURE_GL) {
3696 // PS_AG is not implemented in this case
3697 new_pstate &= ~PS_AG;
3698 }
3699
3700 pstate_regs = env->pstate & 0xc01;
3701 new_pstate_regs = new_pstate & 0xc01;
3702
3703 if (new_pstate_regs != pstate_regs) {
3704 DPRINTF_PSTATE("change_pstate: switching regs old=%x new=%x\n",
3705 pstate_regs, new_pstate_regs);
3706 // Switch global register bank
3707 src = get_gregset(new_pstate_regs);
3708 dst = get_gregset(pstate_regs);
3709 memcpy32(dst, env->gregs);
3710 memcpy32(env->gregs, src);
3711 }
3712 else {
3713 DPRINTF_PSTATE("change_pstate: regs new=%x (unchanged)\n",
3714 new_pstate_regs);
3715 }
3716 env->pstate = new_pstate;
3717 }
3718
3719 void helper_wrpstate(target_ulong new_state)
3720 {
3721 change_pstate(new_state & 0xf3f);
3722
3723 #if !defined(CONFIG_USER_ONLY)
3724 if (cpu_interrupts_enabled(env)) {
3725 cpu_check_irqs(env);
3726 }
3727 #endif
3728 }
3729
3730 void helper_wrpil(target_ulong new_pil)
3731 {
3732 #if !defined(CONFIG_USER_ONLY)
3733 DPRINTF_PSTATE("helper_wrpil old=%x new=%x\n",
3734 env->psrpil, (uint32_t)new_pil);
3735
3736 env->psrpil = new_pil;
3737
3738 if (cpu_interrupts_enabled(env)) {
3739 cpu_check_irqs(env);
3740 }
3741 #endif
3742 }
3743
3744 void helper_done(void)
3745 {
3746 trap_state* tsptr = cpu_tsptr(env);
3747
3748 env->pc = tsptr->tnpc;
3749 env->npc = tsptr->tnpc + 4;
3750 put_ccr(tsptr->tstate >> 32);
3751 env->asi = (tsptr->tstate >> 24) & 0xff;
3752 change_pstate((tsptr->tstate >> 8) & 0xf3f);
3753 put_cwp64(tsptr->tstate & 0xff);
3754 env->tl--;
3755
3756 DPRINTF_PSTATE("... helper_done tl=%d\n", env->tl);
3757
3758 #if !defined(CONFIG_USER_ONLY)
3759 if (cpu_interrupts_enabled(env)) {
3760 cpu_check_irqs(env);
3761 }
3762 #endif
3763 }
3764
3765 void helper_retry(void)
3766 {
3767 trap_state* tsptr = cpu_tsptr(env);
3768
3769 env->pc = tsptr->tpc;
3770 env->npc = tsptr->tnpc;
3771 put_ccr(tsptr->tstate >> 32);
3772 env->asi = (tsptr->tstate >> 24) & 0xff;
3773 change_pstate((tsptr->tstate >> 8) & 0xf3f);
3774 put_cwp64(tsptr->tstate & 0xff);
3775 env->tl--;
3776
3777 DPRINTF_PSTATE("... helper_retry tl=%d\n", env->tl);
3778
3779 #if !defined(CONFIG_USER_ONLY)
3780 if (cpu_interrupts_enabled(env)) {
3781 cpu_check_irqs(env);
3782 }
3783 #endif
3784 }
3785
3786 static void do_modify_softint(const char* operation, uint32_t value)
3787 {
3788 if (env->softint != value) {
3789 env->softint = value;
3790 DPRINTF_PSTATE(": %s new %08x\n", operation, env->softint);
3791 #if !defined(CONFIG_USER_ONLY)
3792 if (cpu_interrupts_enabled(env)) {
3793 cpu_check_irqs(env);
3794 }
3795 #endif
3796 }
3797 }
3798
3799 void helper_set_softint(uint64_t value)
3800 {
3801 do_modify_softint("helper_set_softint", env->softint | (uint32_t)value);
3802 }
3803
3804 void helper_clear_softint(uint64_t value)
3805 {
3806 do_modify_softint("helper_clear_softint", env->softint & (uint32_t)~value);
3807 }
3808
3809 void helper_write_softint(uint64_t value)
3810 {
3811 do_modify_softint("helper_write_softint", (uint32_t)value);
3812 }
3813 #endif
3814
3815 void helper_flush(target_ulong addr)
3816 {
3817 addr &= ~7;
3818 tb_invalidate_page_range(addr, addr + 8);
3819 }
3820
3821 #ifdef TARGET_SPARC64
3822 #ifdef DEBUG_PCALL
3823 static const char * const excp_names[0x80] = {
3824 [TT_TFAULT] = "Instruction Access Fault",
3825 [TT_TMISS] = "Instruction Access MMU Miss",
3826 [TT_CODE_ACCESS] = "Instruction Access Error",
3827 [TT_ILL_INSN] = "Illegal Instruction",
3828 [TT_PRIV_INSN] = "Privileged Instruction",
3829 [TT_NFPU_INSN] = "FPU Disabled",
3830 [TT_FP_EXCP] = "FPU Exception",
3831 [TT_TOVF] = "Tag Overflow",
3832 [TT_CLRWIN] = "Clean Windows",
3833 [TT_DIV_ZERO] = "Division By Zero",
3834 [TT_DFAULT] = "Data Access Fault",
3835 [TT_DMISS] = "Data Access MMU Miss",
3836 [TT_DATA_ACCESS] = "Data Access Error",
3837 [TT_DPROT] = "Data Protection Error",
3838 [TT_UNALIGNED] = "Unaligned Memory Access",
3839 [TT_PRIV_ACT] = "Privileged Action",
3840 [TT_EXTINT | 0x1] = "External Interrupt 1",
3841 [TT_EXTINT | 0x2] = "External Interrupt 2",
3842 [TT_EXTINT | 0x3] = "External Interrupt 3",
3843 [TT_EXTINT | 0x4] = "External Interrupt 4",
3844 [TT_EXTINT | 0x5] = "External Interrupt 5",
3845 [TT_EXTINT | 0x6] = "External Interrupt 6",
3846 [TT_EXTINT | 0x7] = "External Interrupt 7",
3847 [TT_EXTINT | 0x8] = "External Interrupt 8",
3848 [TT_EXTINT | 0x9] = "External Interrupt 9",
3849 [TT_EXTINT | 0xa] = "External Interrupt 10",
3850 [TT_EXTINT | 0xb] = "External Interrupt 11",
3851 [TT_EXTINT | 0xc] = "External Interrupt 12",
3852 [TT_EXTINT | 0xd] = "External Interrupt 13",
3853 [TT_EXTINT | 0xe] = "External Interrupt 14",
3854 [TT_EXTINT | 0xf] = "External Interrupt 15",
3855 };
3856 #endif
3857
3858 trap_state* cpu_tsptr(CPUState* env)
3859 {
3860 return &env->ts[env->tl & MAXTL_MASK];
3861 }
3862
3863 void do_interrupt(CPUState *env)
3864 {
3865 int intno = env->exception_index;
3866 trap_state* tsptr;
3867
3868 #ifdef DEBUG_PCALL
3869 if (qemu_loglevel_mask(CPU_LOG_INT)) {
3870 static int count;
3871 const char *name;
3872
3873 if (intno < 0 || intno >= 0x180)
3874 name = "Unknown";
3875 else if (intno >= 0x100)
3876 name = "Trap Instruction";
3877 else if (intno >= 0xc0)
3878 name = "Window Fill";
3879 else if (intno >= 0x80)
3880 name = "Window Spill";
3881 else {
3882 name = excp_names[intno];
3883 if (!name)
3884 name = "Unknown";
3885 }
3886
3887 qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
3888 " SP=%016" PRIx64 "\n",
3889 count, name, intno,
3890 env->pc,
3891 env->npc, env->regwptr[6]);
3892 log_cpu_state(env, 0);
3893 #if 0
3894 {
3895 int i;
3896 uint8_t *ptr;
3897
3898 qemu_log(" code=");
3899 ptr = (uint8_t *)env->pc;
3900 for(i = 0; i < 16; i++) {
3901 qemu_log(" %02x", ldub(ptr + i));
3902 }
3903 qemu_log("\n");
3904 }
3905 #endif
3906 count++;
3907 }
3908 #endif
3909 #if !defined(CONFIG_USER_ONLY)
3910 if (env->tl >= env->maxtl) {
3911 cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
3912 " Error state", env->exception_index, env->tl, env->maxtl);
3913 return;
3914 }
3915 #endif
3916 if (env->tl < env->maxtl - 1) {
3917 env->tl++;
3918 } else {
3919 env->pstate |= PS_RED;
3920 if (env->tl < env->maxtl)
3921 env->tl++;
3922 }
3923 tsptr = cpu_tsptr(env);
3924
3925 tsptr->tstate = (get_ccr() << 32) |
3926 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
3927 get_cwp64();
3928 tsptr->tpc = env->pc;
3929 tsptr->tnpc = env->npc;
3930 tsptr->tt = intno;
3931
3932 switch (intno) {
3933 case TT_IVEC:
3934 change_pstate(PS_PEF | PS_PRIV | PS_IG);
3935 break;
3936 case TT_TFAULT:
3937 case TT_DFAULT:
3938 case TT_TMISS ... TT_TMISS + 3:
3939 case TT_DMISS ... TT_DMISS + 3:
3940 case TT_DPROT ... TT_DPROT + 3:
3941 change_pstate(PS_PEF | PS_PRIV | PS_MG);
3942 break;
3943 default:
3944 change_pstate(PS_PEF | PS_PRIV | PS_AG);
3945 break;
3946 }
3947
3948 if (intno == TT_CLRWIN) {
3949 set_cwp(cwp_dec(env->cwp - 1));
3950 } else if ((intno & 0x1c0) == TT_SPILL) {
3951 set_cwp(cwp_dec(env->cwp - env->cansave - 2));
3952 } else if ((intno & 0x1c0) == TT_FILL) {
3953 set_cwp(cwp_inc(env->cwp + 1));
3954 }
3955 env->tbr &= ~0x7fffULL;
3956 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
3957 env->pc = env->tbr;
3958 env->npc = env->pc + 4;
3959 env->exception_index = -1;
3960 }
3961 #else
3962 #ifdef DEBUG_PCALL
3963 static const char * const excp_names[0x80] = {
3964 [TT_TFAULT] = "Instruction Access Fault",
3965 [TT_ILL_INSN] = "Illegal Instruction",
3966 [TT_PRIV_INSN] = "Privileged Instruction",
3967 [TT_NFPU_INSN] = "FPU Disabled",
3968 [TT_WIN_OVF] = "Window Overflow",
3969 [TT_WIN_UNF] = "Window Underflow",
3970 [TT_UNALIGNED] = "Unaligned Memory Access",
3971 [TT_FP_EXCP] = "FPU Exception",
3972 [TT_DFAULT] = "Data Access Fault",
3973 [TT_TOVF] = "Tag Overflow",
3974 [TT_EXTINT | 0x1] = "External Interrupt 1",
3975 [TT_EXTINT | 0x2] = "External Interrupt 2",
3976 [TT_EXTINT | 0x3] = "External Interrupt 3",
3977 [TT_EXTINT | 0x4] = "External Interrupt 4",
3978 [TT_EXTINT | 0x5] = "External Interrupt 5",
3979 [TT_EXTINT | 0x6] = "External Interrupt 6",
3980 [TT_EXTINT | 0x7] = "External Interrupt 7",
3981 [TT_EXTINT | 0x8] = "External Interrupt 8",
3982 [TT_EXTINT | 0x9] = "External Interrupt 9",
3983 [TT_EXTINT | 0xa] = "External Interrupt 10",
3984 [TT_EXTINT | 0xb] = "External Interrupt 11",
3985 [TT_EXTINT | 0xc] = "External Interrupt 12",
3986 [TT_EXTINT | 0xd] = "External Interrupt 13",
3987 [TT_EXTINT | 0xe] = "External Interrupt 14",
3988 [TT_EXTINT | 0xf] = "External Interrupt 15",
3989 [TT_TOVF] = "Tag Overflow",
3990 [TT_CODE_ACCESS] = "Instruction Access Error",
3991 [TT_DATA_ACCESS] = "Data Access Error",
3992 [TT_DIV_ZERO] = "Division By Zero",
3993 [TT_NCP_INSN] = "Coprocessor Disabled",
3994 };
3995 #endif
3996
3997 void do_interrupt(CPUState *env)
3998 {
3999 int cwp, intno = env->exception_index;
4000
4001 #ifdef DEBUG_PCALL
4002 if (qemu_loglevel_mask(CPU_LOG_INT)) {
4003 static int count;
4004 const char *name;
4005
4006 if (intno < 0 || intno >= 0x100)
4007 name = "Unknown";
4008 else if (intno >= 0x80)
4009 name = "Trap Instruction";
4010 else {
4011 name = excp_names[intno];
4012 if (!name)
4013 name = "Unknown";
4014 }
4015
4016 qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
4017 count, name, intno,
4018 env->pc,
4019 env->npc, env->regwptr[6]);
4020 log_cpu_state(env, 0);
4021 #if 0
4022 {
4023 int i;
4024 uint8_t *ptr;
4025
4026 qemu_log(" code=");
4027 ptr = (uint8_t *)env->pc;
4028 for(i = 0; i < 16; i++) {
4029 qemu_log(" %02x", ldub(ptr + i));
4030 }
4031 qemu_log("\n");
4032 }
4033 #endif
4034 count++;
4035 }
4036 #endif
4037 #if !defined(CONFIG_USER_ONLY)
4038 if (env->psret == 0) {
4039 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
4040 env->exception_index);
4041 return;
4042 }
4043 #endif
4044 env->psret = 0;
4045 cwp = cwp_dec(env->cwp - 1);
4046 set_cwp(cwp);
4047 env->regwptr[9] = env->pc;
4048 env->regwptr[10] = env->npc;
4049 env->psrps = env->psrs;
4050 env->psrs = 1;
4051 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
4052 env->pc = env->tbr;
4053 env->npc = env->pc + 4;
4054 env->exception_index = -1;
4055 }
4056 #endif
4057
4058 #if !defined(CONFIG_USER_ONLY)
4059
4060 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
4061 void *retaddr);
4062
4063 #define MMUSUFFIX _mmu
4064 #define ALIGNED_ONLY
4065
4066 #define SHIFT 0
4067 #include "softmmu_template.h"
4068
4069 #define SHIFT 1
4070 #include "softmmu_template.h"
4071
4072 #define SHIFT 2
4073 #include "softmmu_template.h"
4074
4075 #define SHIFT 3
4076 #include "softmmu_template.h"
4077
4078 /* XXX: make it generic ? */
4079 static void cpu_restore_state2(void *retaddr)
4080 {
4081 TranslationBlock *tb;
4082 unsigned long pc;
4083
4084 if (retaddr) {
4085 /* now we have a real cpu fault */
4086 pc = (unsigned long)retaddr;
4087 tb = tb_find_pc(pc);
4088 if (tb) {
4089 /* the PC is inside the translated code. It means that we have
4090 a virtual CPU fault */
4091 cpu_restore_state(tb, env, pc, (void *)(long)env->cond);
4092 }
4093 }
4094 }
4095
4096 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
4097 void *retaddr)
4098 {
4099 #ifdef DEBUG_UNALIGNED
4100 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
4101 "\n", addr, env->pc);
4102 #endif
4103 cpu_restore_state2(retaddr);
4104 raise_exception(TT_UNALIGNED);
4105 }
4106
4107 /* try to fill the TLB and return an exception if error. If retaddr is
4108 NULL, it means that the function was called in C code (i.e. not
4109 from generated code or from helper.c) */
4110 /* XXX: fix it to restore all registers */
4111 void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
4112 {
4113 int ret;
4114 CPUState *saved_env;
4115
4116 /* XXX: hack to restore env in all cases, even if not called from
4117 generated code */
4118 saved_env = env;
4119 env = cpu_single_env;
4120
4121 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
4122 if (ret) {
4123 cpu_restore_state2(retaddr);
4124 cpu_loop_exit();
4125 }
4126 env = saved_env;
4127 }
4128
4129 #endif /* !CONFIG_USER_ONLY */
4130
4131 #ifndef TARGET_SPARC64
4132 #if !defined(CONFIG_USER_ONLY)
4133 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
4134 int is_asi, int size)
4135 {
4136 CPUState *saved_env;
4137 int fault_type;
4138
4139 /* XXX: hack to restore env in all cases, even if not called from
4140 generated code */
4141 saved_env = env;
4142 env = cpu_single_env;
4143 #ifdef DEBUG_UNASSIGNED
4144 if (is_asi)
4145 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
4146 " asi 0x%02x from " TARGET_FMT_lx "\n",
4147 is_exec ? "exec" : is_write ? "write" : "read", size,
4148 size == 1 ? "" : "s", addr, is_asi, env->pc);
4149 else
4150 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
4151 " from " TARGET_FMT_lx "\n",
4152 is_exec ? "exec" : is_write ? "write" : "read", size,
4153 size == 1 ? "" : "s", addr, env->pc);
4154 #endif
4155 /* Don't overwrite translation and access faults */
4156 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
4157 if ((fault_type > 4) || (fault_type == 0)) {
4158 env->mmuregs[3] = 0; /* Fault status register */
4159 if (is_asi)
4160 env->mmuregs[3] |= 1 << 16;
4161 if (env->psrs)
4162 env->mmuregs[3] |= 1 << 5;
4163 if (is_exec)
4164 env->mmuregs[3] |= 1 << 6;
4165 if (is_write)
4166 env->mmuregs[3] |= 1 << 7;
4167 env->mmuregs[3] |= (5 << 2) | 2;
4168 /* SuperSPARC will never place instruction fault addresses in the FAR */
4169 if (!is_exec) {
4170 env->mmuregs[4] = addr; /* Fault address register */
4171 }
4172 }
4173 /* overflow (same type fault was not read before another fault) */
4174 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
4175 env->mmuregs[3] |= 1;
4176 }
4177
4178 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
4179 if (is_exec)
4180 raise_exception(TT_CODE_ACCESS);
4181 else
4182 raise_exception(TT_DATA_ACCESS);
4183 }
4184
4185 /* flush neverland mappings created during no-fault mode,
4186 so the sequential MMU faults report proper fault types */
4187 if (env->mmuregs[0] & MMU_NF) {
4188 tlb_flush(env, 1);
4189 }
4190
4191 env = saved_env;
4192 }
4193 #endif
4194 #else
4195 #if defined(CONFIG_USER_ONLY)
4196 static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
4197 int is_asi, int size)
4198 #else
4199 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
4200 int is_asi, int size)
4201 #endif
4202 {
4203 CPUState *saved_env;
4204
4205 /* XXX: hack to restore env in all cases, even if not called from
4206 generated code */
4207 saved_env = env;
4208 env = cpu_single_env;
4209
4210 #ifdef DEBUG_UNASSIGNED
4211 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
4212 "\n", addr, env->pc);
4213 #endif
4214
4215 if (is_exec)
4216 raise_exception(TT_CODE_ACCESS);
4217 else
4218 raise_exception(TT_DATA_ACCESS);
4219
4220 env = saved_env;
4221 }
4222 #endif
4223
4224
4225 #ifdef TARGET_SPARC64
4226 void helper_tick_set_count(void *opaque, uint64_t count)
4227 {
4228 #if !defined(CONFIG_USER_ONLY)
4229 cpu_tick_set_count(opaque, count);
4230 #endif
4231 }
4232
4233 uint64_t helper_tick_get_count(void *opaque)
4234 {
4235 #if !defined(CONFIG_USER_ONLY)
4236 return cpu_tick_get_count(opaque);
4237 #else
4238 return 0;
4239 #endif
4240 }
4241
4242 void helper_tick_set_limit(void *opaque, uint64_t limit)
4243 {
4244 #if !defined(CONFIG_USER_ONLY)
4245 cpu_tick_set_limit(opaque, limit);
4246 #endif
4247 }
4248 #endif
Qemu copy for testing